2 **********************************************************************
3 * hwaccess.c -- Hardware access layer
4 * Copyright 1999, 2000 Creative Labs, Inc.
6 **********************************************************************
8 * Date Author Summary of changes
9 * ---- ------ ------------------
10 * October 20, 1999 Bertrand Lee base code release
11 * December 9, 1999 Jon Taylor rewrote the I/O subsystem
13 **********************************************************************
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public
26 * License along with this program; if not, write to the Free
27 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
30 **********************************************************************
39 /*************************************************************************
40 * Function : srToPitch *
41 * Input : sampleRate - sampling rate *
42 * Return : pitch value *
43 * About : convert sampling rate to pitch *
44 * Note : for 8010, sampling rate is at 48kHz, this function should *
46 *************************************************************************/
47 u32 srToPitch(u32 sampleRate)
51 /* FIXME: These tables should be defined in a headerfile */
52 static u32 logMagTable[128] = {
53 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
54 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
55 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
56 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
57 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
58 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
59 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
60 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
61 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
62 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
63 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
64 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
65 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
66 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
67 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
68 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
71 static char logSlopeTable[128] = {
72 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
73 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
74 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
75 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
76 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
77 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
78 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
79 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
80 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
81 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
82 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
83 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
84 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
85 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
86 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
87 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
91 return 0; /* Bail out if no leading "1" */
93 sampleRate *= 11185; /* Scale 48000 to 0x20002380 */
95 for (i = 31; i > 0; i--) {
96 if (sampleRate & 0x80000000) { /* Detect leading "1" */
97 return (u32) (((s32) (i - 15) << 20) +
98 logMagTable[0x7f & (sampleRate >> 24)] +
99 (0x7f & (sampleRate >> 17)) * logSlopeTable[0x7f & (sampleRate >> 24)]);
101 sampleRate = sampleRate << 1;
104 DPF(2, "srToPitch: BUG!\n");
105 return 0; /* Should never reach this point */
108 /* Returns an attenuation based upon a cumulative volume value */
110 /* Algorithm calculates 0x200 - 0x10 log2 (input) */
111 u8 sumVolumeToAttenuation(u32 value)
119 /* Find first SET bit. This is the integer part of the value */
120 while ((value & 0x10000) == 0) {
125 /* The REST of the data is the fractional part. */
126 ans = (s16) (0x110 - ((count << 4) + ((value & 0x0FFFFL) >> 12)));
133 /*******************************************
134 * write/read PCI function 0 registers *
135 ********************************************/
136 void emu10k1_writefn0(struct emu10k1_card *card, u32 reg, u32 data)
140 if (reg & 0xff000000) {
144 size = (reg >> 24) & 0x3f;
145 offset = (reg >> 16) & 0x1f;
146 mask = ((1 << size) - 1) << offset;
147 data = (data << offset) & mask;
150 spin_lock_irqsave(&card->lock, flags);
151 data |= inl(card->iobase + reg) & ~mask;
152 outl(data, card->iobase + reg);
153 spin_unlock_irqrestore(&card->lock, flags);
155 spin_lock_irqsave(&card->lock, flags);
156 outl(data, card->iobase + reg);
157 spin_unlock_irqrestore(&card->lock, flags);
163 void emu10k1_writefn0_2(struct emu10k1_card *card, u32 reg, u32 data, int size)
167 spin_lock_irqsave(&card->lock, flags);
170 outl(data, card->iobase + (reg & 0x1F));
172 outw(data, card->iobase + (reg & 0x1F));
174 outb(data, card->iobase + (reg & 0x1F));
176 spin_unlock_irqrestore(&card->lock, flags);
181 u32 emu10k1_readfn0(struct emu10k1_card * card, u32 reg)
186 if (reg & 0xff000000) {
190 size = (reg >> 24) & 0x3f;
191 offset = (reg >> 16) & 0x1f;
192 mask = ((1 << size) - 1) << offset;
195 spin_lock_irqsave(&card->lock, flags);
196 val = inl(card->iobase + reg);
197 spin_unlock_irqrestore(&card->lock, flags);
199 return (val & mask) >> offset;
201 spin_lock_irqsave(&card->lock, flags);
202 val = inl(card->iobase + reg);
203 spin_unlock_irqrestore(&card->lock, flags);
208 void emu10k1_timer_set(struct emu10k1_card * card, u16 data)
212 spin_lock_irqsave(&card->lock, flags);
213 outw(data & TIMER_RATE_MASK, card->iobase + TIMER);
214 spin_unlock_irqrestore(&card->lock, flags);
217 /************************************************************************
218 * write/read Emu10k1 pointer-offset register set, accessed through *
219 * the PTR and DATA registers *
220 *************************************************************************/
221 #define A_PTR_ADDRESS_MASK 0x0fff0000
222 void sblive_writeptr(struct emu10k1_card *card, u32 reg, u32 channel, u32 data)
227 regptr = ((reg << 16) & A_PTR_ADDRESS_MASK) | (channel & PTR_CHANNELNUM_MASK);
229 if (reg & 0xff000000) {
233 size = (reg >> 24) & 0x3f;
234 offset = (reg >> 16) & 0x1f;
235 mask = ((1 << size) - 1) << offset;
236 data = (data << offset) & mask;
238 spin_lock_irqsave(&card->lock, flags);
239 outl(regptr, card->iobase + PTR);
240 data |= inl(card->iobase + DATA) & ~mask;
241 outl(data, card->iobase + DATA);
242 spin_unlock_irqrestore(&card->lock, flags);
244 spin_lock_irqsave(&card->lock, flags);
245 outl(regptr, card->iobase + PTR);
246 outl(data, card->iobase + DATA);
247 spin_unlock_irqrestore(&card->lock, flags);
251 /* ... : data, reg, ... , TAGLIST_END */
252 void sblive_writeptr_tag(struct emu10k1_card *card, u32 channel, ...)
259 va_start(args, channel);
261 spin_lock_irqsave(&card->lock, flags);
262 while ((reg = va_arg(args, u32)) != TAGLIST_END) {
263 u32 data = va_arg(args, u32);
264 u32 regptr = (((reg << 16) & A_PTR_ADDRESS_MASK)
265 | (channel & PTR_CHANNELNUM_MASK));
266 outl(regptr, card->iobase + PTR);
267 if (reg & 0xff000000) {
268 int size = (reg >> 24) & 0x3f;
269 int offset = (reg >> 16) & 0x1f;
270 u32 mask = ((1 << size) - 1) << offset;
271 data = (data << offset) & mask;
273 data |= inl(card->iobase + DATA) & ~mask;
275 outl(data, card->iobase + DATA);
277 spin_unlock_irqrestore(&card->lock, flags);
284 u32 sblive_readptr(struct emu10k1_card * card, u32 reg, u32 channel)
289 regptr = ((reg << 16) & A_PTR_ADDRESS_MASK) | (channel & PTR_CHANNELNUM_MASK);
291 if (reg & 0xff000000) {
295 size = (reg >> 24) & 0x3f;
296 offset = (reg >> 16) & 0x1f;
297 mask = ((1 << size) - 1) << offset;
299 spin_lock_irqsave(&card->lock, flags);
300 outl(regptr, card->iobase + PTR);
301 val = inl(card->iobase + DATA);
302 spin_unlock_irqrestore(&card->lock, flags);
304 return (val & mask) >> offset;
306 spin_lock_irqsave(&card->lock, flags);
307 outl(regptr, card->iobase + PTR);
308 val = inl(card->iobase + DATA);
309 spin_unlock_irqrestore(&card->lock, flags);
315 void emu10k1_irq_enable(struct emu10k1_card *card, u32 irq_mask)
320 DPF(2,"emu10k1_irq_enable()\n");
322 spin_lock_irqsave(&card->lock, flags);
323 val = inl(card->iobase + INTE) | irq_mask;
324 outl(val, card->iobase + INTE);
325 spin_unlock_irqrestore(&card->lock, flags);
329 void emu10k1_irq_disable(struct emu10k1_card *card, u32 irq_mask)
334 DPF(2,"emu10k1_irq_disable()\n");
336 spin_lock_irqsave(&card->lock, flags);
337 val = inl(card->iobase + INTE) & ~irq_mask;
338 outl(val, card->iobase + INTE);
339 spin_unlock_irqrestore(&card->lock, flags);
343 void emu10k1_set_stop_on_loop(struct emu10k1_card *card, u32 voicenum)
345 /* Voice interrupt */
347 sblive_writeptr(card, SOLEH | ((0x0100 | (voicenum - 32)) << 16), 0, 1);
349 sblive_writeptr(card, SOLEL | ((0x0100 | voicenum) << 16), 0, 1);
354 void emu10k1_clear_stop_on_loop(struct emu10k1_card *card, u32 voicenum)
356 /* Voice interrupt */
358 sblive_writeptr(card, SOLEH | ((0x0100 | (voicenum - 32)) << 16), 0, 0);
360 sblive_writeptr(card, SOLEL | ((0x0100 | voicenum) << 16), 0, 0);
365 static void sblive_wcwait(struct emu10k1_card *card, u32 wait)
367 volatile unsigned uCount;
368 u32 newtime = 0, curtime;
370 curtime = emu10k1_readfn0(card, WC_SAMPLECOUNTER);
373 while (uCount++ < TIMEOUT) {
374 newtime = emu10k1_readfn0(card, WC_SAMPLECOUNTER);
375 if (newtime != curtime)
379 if (uCount >= TIMEOUT)
386 u16 emu10k1_ac97_read(struct ac97_codec *codec, u8 reg)
388 struct emu10k1_card *card = codec->private_data;
392 spin_lock_irqsave(&card->lock, flags);
394 outb(reg, card->iobase + AC97ADDRESS);
395 data = inw(card->iobase + AC97DATA);
397 spin_unlock_irqrestore(&card->lock, flags);
402 void emu10k1_ac97_write(struct ac97_codec *codec, u8 reg, u16 value)
404 struct emu10k1_card *card = codec->private_data;
407 spin_lock_irqsave(&card->lock, flags);
409 outb(reg, card->iobase + AC97ADDRESS);
410 outw(value, card->iobase + AC97DATA);
411 outb( AC97_EXTENDED_ID, card->iobase + AC97ADDRESS);
412 spin_unlock_irqrestore(&card->lock, flags);
415 /*********************************************************
416 * MPU access functions *
417 **********************************************************/
419 int emu10k1_mpu_write_data(struct emu10k1_card *card, u8 data)
424 if (card->is_audigy) {
425 if ((sblive_readptr(card, A_MUSTAT,0) & MUSTAT_ORDYN) == 0) {
426 sblive_writeptr(card, A_MUDATA, 0, data);
431 spin_lock_irqsave(&card->lock, flags);
433 if ((inb(card->iobase + MUSTAT) & MUSTAT_ORDYN) == 0) {
434 outb(data, card->iobase + MUDATA);
439 spin_unlock_irqrestore(&card->lock, flags);
445 int emu10k1_mpu_read_data(struct emu10k1_card *card, u8 * data)
450 if (card->is_audigy) {
451 if ((sblive_readptr(card, A_MUSTAT,0) & MUSTAT_IRDYN) == 0) {
452 *data = sblive_readptr(card, A_MUDATA,0);
457 spin_lock_irqsave(&card->lock, flags);
459 if ((inb(card->iobase + MUSTAT) & MUSTAT_IRDYN) == 0) {
460 *data = inb(card->iobase + MUDATA);
465 spin_unlock_irqrestore(&card->lock, flags);
471 int emu10k1_mpu_reset(struct emu10k1_card *card)
476 DPF(2, "emu10k1_mpu_reset()\n");
477 if (card->is_audigy) {
478 if (card->mpuacqcount == 0) {
479 sblive_writeptr(card, A_MUCMD, 0, MUCMD_RESET);
480 sblive_wcwait(card, 8);
481 sblive_writeptr(card, A_MUCMD, 0, MUCMD_RESET);
482 sblive_wcwait(card, 8);
483 sblive_writeptr(card, A_MUCMD, 0, MUCMD_ENTERUARTMODE);
484 sblive_wcwait(card, 8);
485 status = sblive_readptr(card, A_MUDATA, 0);
494 if (card->mpuacqcount == 0) {
495 spin_lock_irqsave(&card->lock, flags);
496 outb(MUCMD_RESET, card->iobase + MUCMD);
497 spin_unlock_irqrestore(&card->lock, flags);
499 sblive_wcwait(card, 8);
501 spin_lock_irqsave(&card->lock, flags);
502 outb(MUCMD_RESET, card->iobase + MUCMD);
503 spin_unlock_irqrestore(&card->lock, flags);
505 sblive_wcwait(card, 8);
507 spin_lock_irqsave(&card->lock, flags);
508 outb(MUCMD_ENTERUARTMODE, card->iobase + MUCMD);
509 spin_unlock_irqrestore(&card->lock, flags);
511 sblive_wcwait(card, 8);
513 spin_lock_irqsave(&card->lock, flags);
514 status = inb(card->iobase + MUDATA);
515 spin_unlock_irqrestore(&card->lock, flags);
527 int emu10k1_mpu_acquire(struct emu10k1_card *card)
529 /* FIXME: This should be a macro */
535 int emu10k1_mpu_release(struct emu10k1_card *card)
537 /* FIXME: this should be a macro */