2 * Intel i810 and friends ICH driver for Linux
3 * Alan Cox <alan@redhat.com>
6 * Low level code: Zach Brown (original nonworking i810 OSS driver)
7 * Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
9 * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
10 * Extended by: Zach Brown <zab@redhat.com>
13 * Hardware Provided By:
14 * Analog Devices (A major AC97 codec maker)
15 * Intel Corp (you've probably heard of them already)
17 * AC97 clues and assistance provided by
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37 * Intel 810 theory of operation
39 * The chipset provides three DMA channels that talk to an AC97
40 * CODEC (AC97 is a digital/analog mixer standard). At its simplest
41 * you get 48Khz audio with basic volume and mixer controls. At the
42 * best you get rate adaption in the codec. We set the card up so
43 * that we never take completion interrupts but instead keep the card
44 * chasing its tail around a ring buffer. This is needed for mmap
45 * mode audio and happens to work rather well for non-mmap modes too.
47 * The board has one output channel for PCM audio (supported) and
48 * a stereo line in and mono microphone input. Again these are normally
49 * locked to 48Khz only. Right now recording is not finished.
51 * There is no midi support, no synth support. Use timidity. To get
52 * esd working you need to use esd -r 48000 as it won't probe 48KHz
53 * by default. mpg123 can't handle 48Khz only audio so use xmms.
55 * Fix The Sound On Dell
57 * Not everyone uses 48KHz. We know of no way to detect this reliably
58 * and certainly not to get the right data. If your i810 audio sounds
59 * stupid you may need to investigate other speeds. According to Analog
60 * they tend to use a 14.318MHz clock which gives you a base rate of
63 * This is available via the 'ftsodell=1' option.
65 * If you need to force a specific rate set the clocking= option
67 * This driver is cursed. (Ben LaHaise)
70 * Intel errata #7 for ICH3 IO. We need to disable SMI stuff
71 * when codec probing. [Not Yet Done]
75 * The ICH4 has the feature, that the codec ID doesn't have to be
76 * congruent with the IO connection.
78 * Therefore, from driver version 0.23 on, there is a "codec ID" <->
79 * "IO register base offset" mapping (card->ac97_id_map) field.
81 * Juergen "George" Sawinski (jsaw)
84 #include <linux/module.h>
85 #include <linux/string.h>
86 #include <linux/ctype.h>
87 #include <linux/ioport.h>
88 #include <linux/sched.h>
89 #include <linux/delay.h>
90 #include <linux/sound.h>
91 #include <linux/slab.h>
92 #include <linux/soundcard.h>
93 #include <linux/pci.h>
94 #include <linux/interrupt.h>
97 #include <linux/init.h>
98 #include <linux/poll.h>
99 #include <linux/spinlock.h>
100 #include <linux/smp_lock.h>
101 #include <linux/ac97_codec.h>
102 #include <linux/bitops.h>
103 #include <asm/uaccess.h>
104 #include <asm/hardirq.h>
106 #define DRIVER_VERSION "1.01"
108 #define MODULOP2(a, b) ((a) & ((b) - 1))
109 #define MASKP2(a, b) ((a) & ~((b) - 1))
112 static int strict_clocking;
113 static unsigned int clocking;
114 static int spdif_locked;
118 //#define DEBUG_INTERRUPTS
122 #define ADC_RUNNING 1
123 #define DAC_RUNNING 2
125 #define I810_FMT_16BIT 1
126 #define I810_FMT_STEREO 2
127 #define I810_FMT_MASK 3
129 #define SPDIF_ON 0x0004
130 #define SURR_ON 0x0010
131 #define CENTER_LFE_ON 0x0020
132 #define VOL_MUTED 0x8000
134 /* the 810's array of pointers to data buffers */
137 #define BUSADDR_MASK 0xFFFFFFFE
139 #define CON_IOC 0x80000000 /* interrupt on completion */
140 #define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */
141 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
145 /* an instance of the i810 channel */
149 /* these sg guys should probably be allocated
150 separately as nocache. Must be 8 byte aligned */
151 struct sg_item sg[SG_LEN]; /* 32*8 */
159 * we have 3 separate dma engines. pcm in, pcm out, and mic.
160 * each dma engine has controlling registers. These goofy
161 * names are from the datasheet, but make it easy to write
162 * code while leafing through it.
164 * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2,
165 * mic in 2, s/pdif. Of special interest is the fact that
166 * the upper 3 DMA engines on the ICH4 *must* be accessed
167 * via mmio access instead of pio access.
170 #define ENUM_ENGINE(PRE,DIG) \
172 PRE##_BASE = 0x##DIG##0, /* Base Address */ \
173 PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \
174 PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \
175 PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \
176 PRE##_SR = 0x##DIG##6, /* Status Register */ \
177 PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \
178 PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \
179 PRE##_CR = 0x##DIG##b /* Control Register */ \
182 ENUM_ENGINE(OFF,0); /* Offsets */
183 ENUM_ENGINE(PI,0); /* PCM In */
184 ENUM_ENGINE(PO,1); /* PCM Out */
185 ENUM_ENGINE(MC,2); /* Mic In */
188 GLOB_CNT = 0x2c, /* Global Control */
189 GLOB_STA = 0x30, /* Global Status */
190 CAS = 0x34 /* Codec Write Semaphore Register */
193 ENUM_ENGINE(MC2,4); /* Mic In 2 */
194 ENUM_ENGINE(PI2,5); /* PCM In 2 */
195 ENUM_ENGINE(SP,6); /* S/PDIF */
198 SDM = 0x80 /* SDATA_IN Map Register */
201 /* interrupts for a dma engine */
202 #define DMA_INT_FIFO (1<<4) /* fifo under/over flow */
203 #define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */
204 #define DMA_INT_LVI (1<<2) /* last valid done */
205 #define DMA_INT_CELV (1<<1) /* last valid is current */
206 #define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */
207 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
209 /* interrupts for the whole chip */
210 #define INT_SEC (1<<11)
211 #define INT_PRI (1<<10)
212 #define INT_MC (1<<7)
213 #define INT_PO (1<<6)
214 #define INT_PI (1<<5)
215 #define INT_MO (1<<2)
216 #define INT_NI (1<<1)
217 #define INT_GPI (1<<0)
218 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
220 /* magic numbers to protect our data structures */
221 #define I810_CARD_MAGIC 0x5072696E /* "Prin" */
222 #define I810_STATE_MAGIC 0x63657373 /* "cess" */
223 #define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */
226 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
229 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
230 /* stream at a minimum for this card to be happy */
231 static const unsigned sample_size[] = { 1, 2, 2, 4 };
232 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
233 /* values are one less than might be expected */
234 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
250 static char * card_names[] = {
259 "NVIDIA nForce Audio",
264 /* These are capabilities (and bugs) the chipsets _can_ have */
267 #define CAP_MMIO 0x0001
268 #define CAP_20BIT_AUDIO_SUPPORT 0x0002
271 { 1, 0x0000 }, /* ICH82801AA */
272 { 1, 0x0000 }, /* ICH82901AB */
273 { 1, 0x0000 }, /* INTEL440MX */
274 { 1, 0x0000 }, /* INTELICH2 */
275 { 2, 0x0000 }, /* INTELICH3 */
276 { 3, 0x0003 }, /* INTELICH4 */
277 { 3, 0x0003 }, /* INTELICH5 */
278 /*@FIXME to be verified*/ { 2, 0x0000 }, /* SI7012 */
279 /*@FIXME to be verified*/ { 2, 0x0000 }, /* NVIDIA_NFORCE */
280 /*@FIXME to be verified*/ { 2, 0x0000 }, /* AMD768 */
281 /*@FIXME to be verified*/ { 3, 0x0001 }, /* AMD8111 */
284 static struct pci_device_id i810_pci_tbl [] = {
285 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_5,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
287 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_5,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
289 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
291 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_4,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
293 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_5,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
295 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_5,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
297 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_5,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH5},
299 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012},
301 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
303 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
305 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
307 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7445,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768},
309 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AUDIO,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111},
311 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_5,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
313 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_18,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
319 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
322 #define PM_SUSPENDED(card) (card->pm_suspended)
324 #define PM_SUSPENDED(card) (0)
327 /* "software" or virtual channel, an instance of opened /dev/dsp */
330 struct i810_card *card; /* Card info */
332 /* single open lock mechanism, only used for recording */
333 struct semaphore open_sem;
334 wait_queue_head_t open_wait;
339 /* virtual channel number */
343 unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
346 /* wave sample stuff */
348 unsigned char fmt, enable, trigger;
350 /* hardware channel */
351 struct i810_channel *read_channel;
352 struct i810_channel *write_channel;
354 /* OSS buffer management stuff */
356 dma_addr_t dma_handle;
361 /* our buffer acts like a circular ring */
362 unsigned hwptr; /* where dma last started, updated by update_ptr */
363 unsigned swptr; /* where driver last clear/filled, updated by read/write */
364 int count; /* bytes to be consumed or been generated by dma machine */
365 unsigned total_bytes; /* total bytes dmaed by hardware */
367 unsigned error; /* number of over/underruns */
368 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
370 /* redundant, but makes calculations easier */
371 /* what the hardware uses */
374 unsigned fragsamples;
376 /* what we tell the user to expect */
378 unsigned userfragsize;
383 unsigned update_flag;
384 unsigned ossfragsize;
385 unsigned ossmaxfrags;
386 unsigned subdivision;
394 /* We keep i810 cards in a linked list */
395 struct i810_card *next;
397 /* The i810 has a certain amount of cross channel interaction
398 so we use a single per card lock */
401 /* Control AC97 access serialization */
402 spinlock_t ac97_lock;
404 /* PCI device stuff */
405 struct pci_dev * pci_dev;
407 u16 pci_id_internal; /* used to access card_cap[] */
410 u32 pm_save_state[64/sizeof(u32)];
411 int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
413 /* soundcore stuff */
416 /* structures for abstraction of hardware facilities, codecs, banks and channels*/
417 u16 ac97_id_map[NR_AC97];
418 struct ac97_codec *ac97_codec[NR_AC97];
419 struct i810_state *states[NR_HW_CH];
420 struct i810_channel *channel; /* 1:1 to states[] but diff. lifetime */
427 /* hardware resources */
428 unsigned long ac97base;
429 unsigned long iobase;
432 unsigned long ac97base_mmio_phys;
433 unsigned long iobase_mmio_phys;
434 u_int8_t *ac97base_mmio;
435 u_int8_t *iobase_mmio;
439 /* Function support */
440 struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
441 struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
442 struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
443 void (*free_pcm_channel)(struct i810_card *, int chan);
445 /* We have a *very* long init time possibly, so use this to block */
446 /* attempts to open our devices before we are ready (stops oops'es) */
450 /* extract register offset from codec struct */
451 #define IO_REG_OFF(codec) (((struct i810_card *) codec->private_data)->ac97_id_map[codec->id])
453 #define GET_CIV(port) MODULOP2(inb((port) + OFF_CIV), SG_LEN)
454 #define GET_LVI(port) MODULOP2(inb((port) + OFF_LVI), SG_LEN)
456 /* set LVI from CIV */
457 #define CIV_TO_LVI(port, off) \
458 outb(MODULOP2(GET_CIV((port)) + (off), SG_LEN), (port) + OFF_LVI)
460 static struct i810_card *devs = NULL;
462 static int i810_open_mixdev(struct inode *inode, struct file *file);
463 static int i810_ioctl_mixdev(struct inode *inode, struct file *file,
464 unsigned int cmd, unsigned long arg);
465 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
466 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
467 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg);
468 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data);
469 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg);
470 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data);
472 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
474 if(card->channel[1].used==1)
476 card->channel[1].used=1;
477 return &card->channel[1];
480 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
482 if(card->channel[0].used==1)
484 card->channel[0].used=1;
485 return &card->channel[0];
488 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
490 if(card->channel[2].used==1)
492 card->channel[2].used=1;
493 return &card->channel[2];
496 static void i810_free_pcm_channel(struct i810_card *card, int channel)
498 card->channel[channel].used=0;
501 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
503 unsigned long id = 0L;
505 id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
506 id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
508 printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
511 case 0x41445361: /* AD1886 */
516 default: /* all other codecs, until we know otherwiae */
517 if (rate == 48000 || rate == 44100 || rate == 32000) {
525 /* i810_set_spdif_output
527 * Configure the S/PDIF output transmitter. When we turn on
528 * S/PDIF, we turn off the analog output. This may not be
529 * the right thing to do.
532 * The DSP sample rate must already be set to a supported
533 * S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
535 static int i810_set_spdif_output(struct i810_state *state, int slots, int rate)
540 struct ac97_codec *codec = state->card->ac97_codec[0];
542 if(!codec->codec_ops->digital) {
543 state->card->ac97_status &= ~SPDIF_ON;
545 if ( slots == -1 ) { /* Turn off S/PDIF */
546 codec->codec_ops->digital(codec, 0, 0, 0);
547 /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
548 if ( !(state->card->ac97_status & VOL_MUTED) ) {
549 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
550 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
552 state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
556 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
557 state->card->ac97_status = vol & VOL_MUTED;
559 r = codec->codec_ops->digital(codec, slots, rate, 0);
562 state->card->ac97_status |= SPDIF_ON;
564 state->card->ac97_status &= ~SPDIF_ON;
566 /* Mute the analog output */
567 /* Should this only mute the PCM volume??? */
568 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
573 /* i810_set_dac_channels
575 * Configure the codec's multi-channel DACs
577 * The logic is backwards. Setting the bit to 1 turns off the DAC.
579 * What about the ICH? We currently configure it using the
580 * SNDCTL_DSP_CHANNELS ioctl. If we're turnning on the DAC,
581 * does that imply that we want the ICH set to support
585 * vailidate that the codec really supports these DACs
586 * before turning them on.
588 static void i810_set_dac_channels(struct i810_state *state, int channel)
591 struct ac97_codec *codec = state->card->ac97_codec[0];
593 /* No codec, no setup */
598 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
599 aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
600 state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
603 case 2: /* always enabled */
606 aud_reg &= ~AC97_EA_PRJ;
607 state->card->ac97_status |= SURR_ON;
610 aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
611 state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
616 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
621 /* set playback sample rate */
622 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
624 struct dmabuf *dmabuf = &state->dmabuf;
626 struct ac97_codec *codec=state->card->ac97_codec[0];
628 if(!(state->card->ac97_features&0x0001))
630 dmabuf->rate = clocking;
632 printk("Asked for %d Hz, but ac97_features says we only do %dHz. Sorry!\n",
645 * Adjust for misclocked crap
647 rate = ( rate * clocking)/48000;
648 if(strict_clocking && rate < 8000) {
650 dmabuf->rate = (rate * 48000)/clocking;
653 new_rate=ac97_set_dac_rate(codec, rate);
654 if(new_rate != rate) {
655 dmabuf->rate = (new_rate * 48000)/clocking;
658 printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
664 /* set recording sample rate */
665 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
667 struct dmabuf *dmabuf = &state->dmabuf;
669 struct ac97_codec *codec=state->card->ac97_codec[0];
671 if(!(state->card->ac97_features&0x0001))
673 dmabuf->rate = clocking;
684 * Adjust for misclocked crap
687 rate = ( rate * clocking)/48000;
688 if(strict_clocking && rate < 8000) {
690 dmabuf->rate = (rate * 48000)/clocking;
693 new_rate = ac97_set_adc_rate(codec, rate);
695 if(new_rate != rate) {
696 dmabuf->rate = (new_rate * 48000)/clocking;
700 printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
705 /* get current playback/recording dma buffer pointer (byte offset from LBA),
706 called with spinlock held! */
708 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
710 struct dmabuf *dmabuf = &state->dmabuf;
711 unsigned int civ, offset, port, port_picb, bytes = 2;
717 port = state->card->iobase + dmabuf->read_channel->port;
719 port = state->card->iobase + dmabuf->write_channel->port;
721 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) {
722 port_picb = port + OFF_SR;
725 port_picb = port + OFF_PICB;
729 offset = inw(port_picb);
730 /* Must have a delay here! */
733 /* Reread both registers and make sure that that total
734 * offset from the first reading to the second is 0.
735 * There is an issue with SiS hardware where it will count
736 * picb down to 0, then update civ to the next value,
737 * then set the new picb to fragsize bytes. We can catch
738 * it between the civ update and the picb update, making
739 * it look as though we are 1 fragsize ahead of where we
740 * are. The next to we get the address though, it will
741 * be back in the right place, and we will suddenly think
742 * we just went forward dmasize - fragsize bytes, causing
743 * totally stupid *huge* dma overrun messages. We are
744 * assuming that the 1us delay is more than long enough
745 * that we won't have to worry about the chip still being
746 * out of sync with reality ;-)
748 } while (civ != GET_CIV(port) || offset != inw(port_picb));
750 return (((civ + 1) * dmabuf->fragsize - (bytes * offset))
754 /* Stop recording (lock held) */
755 static inline void __stop_adc(struct i810_state *state)
757 struct dmabuf *dmabuf = &state->dmabuf;
758 struct i810_card *card = state->card;
760 dmabuf->enable &= ~ADC_RUNNING;
761 outb(0, card->iobase + PI_CR);
762 // wait for the card to acknowledge shutdown
763 while( inb(card->iobase + PI_CR) != 0 ) ;
764 // now clear any latent interrupt bits (like the halt bit)
765 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
766 outb( inb(card->iobase + PI_PICB), card->iobase + PI_PICB );
768 outb( inb(card->iobase + PI_SR), card->iobase + PI_SR );
769 outl( inl(card->iobase + GLOB_STA) & INT_PI, card->iobase + GLOB_STA);
772 static void stop_adc(struct i810_state *state)
774 struct i810_card *card = state->card;
777 spin_lock_irqsave(&card->lock, flags);
779 spin_unlock_irqrestore(&card->lock, flags);
782 static inline void __start_adc(struct i810_state *state)
784 struct dmabuf *dmabuf = &state->dmabuf;
786 if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
787 (dmabuf->trigger & PCM_ENABLE_INPUT)) {
788 dmabuf->enable |= ADC_RUNNING;
789 // Interrupt enable, LVI enable, DMA enable
790 outb(0x10 | 0x04 | 0x01, state->card->iobase + PI_CR);
794 static void start_adc(struct i810_state *state)
796 struct i810_card *card = state->card;
799 spin_lock_irqsave(&card->lock, flags);
801 spin_unlock_irqrestore(&card->lock, flags);
804 /* stop playback (lock held) */
805 static inline void __stop_dac(struct i810_state *state)
807 struct dmabuf *dmabuf = &state->dmabuf;
808 struct i810_card *card = state->card;
810 dmabuf->enable &= ~DAC_RUNNING;
811 outb(0, card->iobase + PO_CR);
812 // wait for the card to acknowledge shutdown
813 while( inb(card->iobase + PO_CR) != 0 ) ;
814 // now clear any latent interrupt bits (like the halt bit)
815 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
816 outb( inb(card->iobase + PO_PICB), card->iobase + PO_PICB );
818 outb( inb(card->iobase + PO_SR), card->iobase + PO_SR );
819 outl( inl(card->iobase + GLOB_STA) & INT_PO, card->iobase + GLOB_STA);
822 static void stop_dac(struct i810_state *state)
824 struct i810_card *card = state->card;
827 spin_lock_irqsave(&card->lock, flags);
829 spin_unlock_irqrestore(&card->lock, flags);
832 static inline void __start_dac(struct i810_state *state)
834 struct dmabuf *dmabuf = &state->dmabuf;
836 if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
837 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
838 dmabuf->enable |= DAC_RUNNING;
839 // Interrupt enable, LVI enable, DMA enable
840 outb(0x10 | 0x04 | 0x01, state->card->iobase + PO_CR);
843 static void start_dac(struct i810_state *state)
845 struct i810_card *card = state->card;
848 spin_lock_irqsave(&card->lock, flags);
850 spin_unlock_irqrestore(&card->lock, flags);
853 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
854 #define DMABUF_MINORDER 1
856 /* allocate DMA buffer, playback and recording buffer should be allocated separately */
857 static int alloc_dmabuf(struct i810_state *state)
859 struct dmabuf *dmabuf = &state->dmabuf;
862 struct page *page, *pend;
864 /* If we don't have any oss frag params, then use our default ones */
865 if(dmabuf->ossmaxfrags == 0)
866 dmabuf->ossmaxfrags = 4;
867 if(dmabuf->ossfragsize == 0)
868 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
869 size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
871 if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size)
873 /* alloc enough to satisfy the oss params */
874 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
875 if ( (PAGE_SIZE<<order) > size )
877 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
879 &dmabuf->dma_handle)))
887 printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
888 PAGE_SIZE << order, order, rawbuf);
891 dmabuf->ready = dmabuf->mapped = 0;
892 dmabuf->rawbuf = rawbuf;
893 dmabuf->buforder = order;
895 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
896 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
897 for (page = virt_to_page(rawbuf); page <= pend; page++)
898 SetPageReserved(page);
903 /* free DMA buffer */
904 static void dealloc_dmabuf(struct i810_state *state)
906 struct dmabuf *dmabuf = &state->dmabuf;
907 struct page *page, *pend;
909 if (dmabuf->rawbuf) {
910 /* undo marking the pages as reserved */
911 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
912 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
913 ClearPageReserved(page);
914 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
915 dmabuf->rawbuf, dmabuf->dma_handle);
917 dmabuf->rawbuf = NULL;
918 dmabuf->mapped = dmabuf->ready = 0;
921 static int prog_dmabuf(struct i810_state *state, unsigned rec)
923 struct dmabuf *dmabuf = &state->dmabuf;
924 struct i810_channel *c;
931 spin_lock_irqsave(&state->card->lock, flags);
932 if(dmabuf->enable & DAC_RUNNING)
934 if(dmabuf->enable & ADC_RUNNING)
936 dmabuf->total_bytes = 0;
937 dmabuf->count = dmabuf->error = 0;
938 dmabuf->swptr = dmabuf->hwptr = 0;
939 spin_unlock_irqrestore(&state->card->lock, flags);
941 /* allocate DMA buffer, let alloc_dmabuf determine if we are already
942 * allocated well enough or if we should replace the current buffer
943 * (assuming one is already allocated, if it isn't, then allocate it).
945 if ((ret = alloc_dmabuf(state)))
948 /* FIXME: figure out all this OSS fragment stuff */
949 /* I did, it now does what it should according to the OSS API. DL */
950 /* We may not have realloced our dmabuf, but the fragment size to
951 * fragment number ratio may have changed, so go ahead and reprogram
954 dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
955 dmabuf->numfrag = SG_LEN;
956 dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
957 dmabuf->fragsamples = dmabuf->fragsize >> 1;
958 dmabuf->fragshift = ffs(dmabuf->fragsize) - 1;
959 dmabuf->userfragsize = dmabuf->ossfragsize;
960 dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
962 memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
964 if(dmabuf->ossmaxfrags == 4) {
966 } else if (dmabuf->ossmaxfrags == 8) {
968 } else if (dmabuf->ossmaxfrags == 16) {
974 * Now set up the ring
976 if(dmabuf->read_channel)
977 c = dmabuf->read_channel;
979 c = dmabuf->write_channel;
983 * Load up 32 sg entries and take an interrupt at half
984 * way (we might want more interrupts later..)
987 for(i=0;i<dmabuf->numfrag;i++)
989 sg->busaddr=(u32)dmabuf->dma_handle+dmabuf->fragsize*i;
990 // the card will always be doing 16bit stereo
991 sg->control=dmabuf->fragsamples;
992 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012)
994 sg->control|=CON_BUFPAD;
995 // set us up to get IOC interrupts as often as needed to
996 // satisfy numfrag requirements, no more
997 if( ((i+1) % fragint) == 0) {
998 sg->control|=CON_IOC;
1002 spin_lock_irqsave(&state->card->lock, flags);
1003 outb(2, state->card->iobase+c->port+OFF_CR); /* reset DMA machine */
1004 while( inb(state->card->iobase+c->port+OFF_CR) & 0x02 ) ;
1005 outl((u32)state->card->chandma +
1006 c->num*sizeof(struct i810_channel),
1007 state->card->iobase+c->port+OFF_BDBAR);
1008 CIV_TO_LVI(state->card->iobase+c->port, 0);
1010 spin_unlock_irqrestore(&state->card->lock, flags);
1012 if(c != dmabuf->write_channel)
1013 c = dmabuf->write_channel;
1018 /* set the ready flag for the dma buffer */
1022 printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
1023 "fragsize = %d dmasize = %d\n",
1024 dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
1025 dmabuf->fragsize, dmabuf->dmasize);
1031 static void __i810_update_lvi(struct i810_state *state, int rec)
1033 struct dmabuf *dmabuf = &state->dmabuf;
1036 int count, fragsize;
1037 void (*start)(struct i810_state *);
1039 count = dmabuf->count;
1040 port = state->card->iobase;
1042 port += dmabuf->read_channel->port;
1043 trigger = PCM_ENABLE_INPUT;
1044 start = __start_adc;
1045 count = dmabuf->dmasize - count;
1047 port += dmabuf->write_channel->port;
1048 trigger = PCM_ENABLE_OUTPUT;
1049 start = __start_dac;
1052 /* Do not process partial fragments. */
1053 fragsize = dmabuf->fragsize;
1054 if (count < fragsize)
1057 if (!dmabuf->enable && dmabuf->ready) {
1058 if (!(dmabuf->trigger & trigger))
1062 while (!(inb(port + OFF_CR) & ((1<<4) | (1<<2))))
1066 /* MASKP2(swptr, fragsize) - 1 is the tail of our transfer */
1067 x = MODULOP2(MASKP2(dmabuf->swptr, fragsize) - 1, dmabuf->dmasize);
1068 x >>= dmabuf->fragshift;
1069 outb(x, port + OFF_LVI);
1072 static void i810_update_lvi(struct i810_state *state, int rec)
1074 struct dmabuf *dmabuf = &state->dmabuf;
1075 unsigned long flags;
1079 spin_lock_irqsave(&state->card->lock, flags);
1080 __i810_update_lvi(state, rec);
1081 spin_unlock_irqrestore(&state->card->lock, flags);
1084 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
1085 static void i810_update_ptr(struct i810_state *state)
1087 struct dmabuf *dmabuf = &state->dmabuf;
1089 unsigned fragmask, dmamask;
1092 fragmask = MASKP2(~0, dmabuf->fragsize);
1093 dmamask = MODULOP2(~0, dmabuf->dmasize);
1095 /* error handling and process wake up for ADC */
1096 if (dmabuf->enable == ADC_RUNNING) {
1097 /* update hardware pointer */
1098 hwptr = i810_get_dma_addr(state, 1) & fragmask;
1099 diff = (hwptr - dmabuf->hwptr) & dmamask;
1100 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1101 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1103 dmabuf->hwptr = hwptr;
1104 dmabuf->total_bytes += diff;
1105 dmabuf->count += diff;
1106 if (dmabuf->count > dmabuf->dmasize) {
1107 /* buffer underrun or buffer overrun */
1108 /* this is normal for the end of a read */
1109 /* only give an error if we went past the */
1110 /* last valid sg entry */
1111 if (GET_CIV(state->card->iobase + PI_BASE) !=
1112 GET_LVI(state->card->iobase + PI_BASE)) {
1113 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1118 wake_up(&dmabuf->wait);
1120 /* error handling and process wake up for DAC */
1121 if (dmabuf->enable == DAC_RUNNING) {
1122 /* update hardware pointer */
1123 hwptr = i810_get_dma_addr(state, 0) & fragmask;
1124 diff = (hwptr - dmabuf->hwptr) & dmamask;
1125 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1126 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1128 dmabuf->hwptr = hwptr;
1129 dmabuf->total_bytes += diff;
1130 dmabuf->count -= diff;
1131 if (dmabuf->count < 0) {
1132 /* buffer underrun or buffer overrun */
1133 /* this is normal for the end of a write */
1134 /* only give an error if we went past the */
1135 /* last valid sg entry */
1136 if (GET_CIV(state->card->iobase + PO_BASE) !=
1137 GET_LVI(state->card->iobase + PO_BASE)) {
1138 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1139 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1141 GET_CIV(state->card->iobase + PO_BASE),
1142 GET_LVI(state->card->iobase + PO_BASE),
1143 dmabuf->hwptr, dmabuf->count);
1148 wake_up(&dmabuf->wait);
1152 static inline int i810_get_free_write_space(struct i810_state *state)
1154 struct dmabuf *dmabuf = &state->dmabuf;
1157 i810_update_ptr(state);
1158 // catch underruns during playback
1159 if (dmabuf->count < 0) {
1161 dmabuf->swptr = dmabuf->hwptr;
1163 free = dmabuf->dmasize - dmabuf->count;
1169 static inline int i810_get_available_read_data(struct i810_state *state)
1171 struct dmabuf *dmabuf = &state->dmabuf;
1174 i810_update_ptr(state);
1175 // catch overruns during record
1176 if (dmabuf->count > dmabuf->dmasize) {
1177 dmabuf->count = dmabuf->dmasize;
1178 dmabuf->swptr = dmabuf->hwptr;
1180 avail = dmabuf->count;
1186 static inline void fill_partial_frag(struct dmabuf *dmabuf)
1189 unsigned swptr, len;
1191 fragsize = dmabuf->fragsize;
1192 swptr = dmabuf->swptr;
1193 len = fragsize - MODULOP2(dmabuf->swptr, fragsize);
1194 if (len == fragsize)
1197 memset(dmabuf->rawbuf + swptr, '\0', len);
1198 dmabuf->swptr = MODULOP2(swptr + len, dmabuf->dmasize);
1199 dmabuf->count += len;
1202 static int drain_dac(struct i810_state *state, int signals_allowed)
1204 DECLARE_WAITQUEUE(wait, current);
1205 struct dmabuf *dmabuf = &state->dmabuf;
1206 unsigned long flags;
1212 if(dmabuf->mapped) {
1217 spin_lock_irqsave(&state->card->lock, flags);
1219 fill_partial_frag(dmabuf);
1222 * This will make sure that our LVI is correct, that our
1223 * pointer is updated, and that the DAC is running. We
1224 * have to force the setting of dmabuf->trigger to avoid
1225 * any possible deadlocks.
1227 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1228 __i810_update_lvi(state, 0);
1230 spin_unlock_irqrestore(&state->card->lock, flags);
1232 add_wait_queue(&dmabuf->wait, &wait);
1235 spin_lock_irqsave(&state->card->lock, flags);
1236 i810_update_ptr(state);
1237 count = dmabuf->count;
1239 /* It seems that we have to set the current state to
1240 * TASK_INTERRUPTIBLE every time to make the process
1241 * really go to sleep. This also has to be *after* the
1242 * update_ptr() call because update_ptr is likely to
1243 * do a wake_up() which will unset this before we ever
1244 * try to sleep, resuling in a tight loop in this code
1245 * instead of actually sleeping and waiting for an
1246 * interrupt to wake us up!
1248 __set_current_state(signals_allowed ?
1249 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1250 spin_unlock_irqrestore(&state->card->lock, flags);
1255 if (signal_pending(current) && signals_allowed) {
1260 * set the timeout to significantly longer than it *should*
1261 * take for the DAC to drain the DMA buffer
1263 tmo = (count * HZ) / (dmabuf->rate);
1264 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){
1265 printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1270 set_current_state(TASK_RUNNING);
1271 remove_wait_queue(&dmabuf->wait, &wait);
1272 if(count > 0 && signal_pending(current) && signals_allowed)
1273 return -ERESTARTSYS;
1278 static void i810_channel_interrupt(struct i810_card *card)
1282 #ifdef DEBUG_INTERRUPTS
1285 for(i=0;i<NR_HW_CH;i++)
1287 struct i810_state *state = card->states[i];
1288 struct i810_channel *c;
1289 struct dmabuf *dmabuf;
1290 unsigned long port = card->iobase;
1295 if(!state->dmabuf.ready)
1297 dmabuf = &state->dmabuf;
1298 if(dmabuf->enable & DAC_RUNNING) {
1299 c=dmabuf->write_channel;
1300 } else if(dmabuf->enable & ADC_RUNNING) {
1301 c=dmabuf->read_channel;
1302 } else /* This can occur going from R/W to close */
1307 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1308 status = inw(port + OFF_PICB);
1310 status = inw(port + OFF_SR);
1312 #ifdef DEBUG_INTERRUPTS
1313 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1315 if(status & DMA_INT_COMPLETE)
1317 /* only wake_up() waiters if this interrupt signals
1318 * us being beyond a userfragsize of data open or
1319 * available, and i810_update_ptr() does that for
1322 i810_update_ptr(state);
1323 #ifdef DEBUG_INTERRUPTS
1324 printk("COMP %d ", dmabuf->hwptr /
1328 if(status & (DMA_INT_LVI | DMA_INT_DCH))
1330 /* wake_up() unconditionally on LVI and DCH */
1331 i810_update_ptr(state);
1332 wake_up(&dmabuf->wait);
1333 #ifdef DEBUG_INTERRUPTS
1334 if(status & DMA_INT_LVI)
1336 if(status & DMA_INT_DCH)
1339 count = dmabuf->count;
1340 if(dmabuf->enable & ADC_RUNNING)
1341 count = dmabuf->dmasize - count;
1342 if (count >= (int)dmabuf->fragsize) {
1343 outb(inb(port+OFF_CR) | 1, port+OFF_CR);
1344 #ifdef DEBUG_INTERRUPTS
1345 printk(" CONTINUE ");
1348 if (dmabuf->enable & DAC_RUNNING)
1350 if (dmabuf->enable & ADC_RUNNING)
1353 #ifdef DEBUG_INTERRUPTS
1358 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1359 outw(status & DMA_INT_MASK, port + OFF_PICB);
1361 outw(status & DMA_INT_MASK, port + OFF_SR);
1363 #ifdef DEBUG_INTERRUPTS
1368 static irqreturn_t i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1370 struct i810_card *card = (struct i810_card *)dev_id;
1373 spin_lock(&card->lock);
1375 status = inl(card->iobase + GLOB_STA);
1377 if(!(status & INT_MASK))
1379 spin_unlock(&card->lock);
1380 return IRQ_NONE; /* not for us */
1383 if(status & (INT_PO|INT_PI|INT_MC))
1384 i810_channel_interrupt(card);
1387 outl(status & INT_MASK, card->iobase + GLOB_STA);
1388 spin_unlock(&card->lock);
1392 /* in this loop, dmabuf.count signifies the amount of data that is
1393 waiting to be copied to the user's buffer. It is filled by the dma
1394 machine and drained by this loop. */
1396 static ssize_t i810_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1398 struct i810_state *state = (struct i810_state *)file->private_data;
1399 struct i810_card *card=state ? state->card : 0;
1400 struct dmabuf *dmabuf = &state->dmabuf;
1402 unsigned long flags;
1406 DECLARE_WAITQUEUE(waita, current);
1409 printk("i810_audio: i810_read called, count = %d\n", count);
1412 if (ppos != &file->f_pos)
1416 if (dmabuf->enable & DAC_RUNNING)
1418 if (!dmabuf->read_channel) {
1420 dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
1421 if (!dmabuf->read_channel) {
1425 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1427 if (!access_ok(VERIFY_WRITE, buffer, count))
1433 add_wait_queue(&dmabuf->wait, &waita);
1435 set_current_state(TASK_INTERRUPTIBLE);
1436 spin_lock_irqsave(&card->lock, flags);
1437 if (PM_SUSPENDED(card)) {
1438 spin_unlock_irqrestore(&card->lock, flags);
1440 if (signal_pending(current)) {
1441 if (!ret) ret = -EAGAIN;
1446 cnt = i810_get_available_read_data(state);
1447 swptr = dmabuf->swptr;
1448 // this is to make the copy_to_user simpler below
1449 if(cnt > (dmabuf->dmasize - swptr))
1450 cnt = dmabuf->dmasize - swptr;
1451 spin_unlock_irqrestore(&card->lock, flags);
1458 * Don't let us deadlock. The ADC won't start if
1459 * dmabuf->trigger isn't set. A call to SETTRIGGER
1460 * could have turned it off after we set it to on
1463 dmabuf->trigger = PCM_ENABLE_INPUT;
1465 * This does three things. Updates LVI to be correct,
1466 * makes sure the ADC is running, and updates the
1469 i810_update_lvi(state,1);
1470 if (file->f_flags & O_NONBLOCK) {
1471 if (!ret) ret = -EAGAIN;
1474 /* Set the timeout to how long it would take to fill
1475 * two of our buffers. If we haven't been woke up
1476 * by then, then we know something is wrong.
1478 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1479 /* There are two situations when sleep_on_timeout returns, one is when
1480 the interrupt is serviced correctly and the process is waked up by
1481 ISR ON TIME. Another is when timeout is expired, which means that
1482 either interrupt is NOT serviced correctly (pending interrupt) or it
1483 is TOO LATE for the process to be scheduled to run (scheduler latency)
1484 which results in a (potential) buffer overrun. And worse, there is
1485 NOTHING we can do to prevent it. */
1486 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1488 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1489 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1490 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1491 dmabuf->hwptr, dmabuf->swptr);
1493 /* a buffer overrun, we delay the recovery until next time the
1494 while loop begin and we REALLY have space to record */
1496 if (signal_pending(current)) {
1497 ret = ret ? ret : -ERESTARTSYS;
1503 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1504 if (!ret) ret = -EFAULT;
1508 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1510 spin_lock_irqsave(&card->lock, flags);
1512 if (PM_SUSPENDED(card)) {
1513 spin_unlock_irqrestore(&card->lock, flags);
1516 dmabuf->swptr = swptr;
1517 pending = dmabuf->count -= cnt;
1518 spin_unlock_irqrestore(&card->lock, flags);
1525 pending = dmabuf->dmasize - pending;
1526 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1527 i810_update_lvi(state, 1);
1528 set_current_state(TASK_RUNNING);
1529 remove_wait_queue(&dmabuf->wait, &waita);
1534 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1535 the soundcard. it is drained by the dma machine and filled by this loop. */
1536 static ssize_t i810_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1538 struct i810_state *state = (struct i810_state *)file->private_data;
1539 struct i810_card *card=state ? state->card : 0;
1540 struct dmabuf *dmabuf = &state->dmabuf;
1542 unsigned long flags;
1543 unsigned int swptr = 0;
1546 DECLARE_WAITQUEUE(waita, current);
1549 printk("i810_audio: i810_write called, count = %d\n", count);
1552 if (ppos != &file->f_pos)
1556 if (dmabuf->enable & ADC_RUNNING)
1558 if (!dmabuf->write_channel) {
1560 dmabuf->write_channel = card->alloc_pcm_channel(card);
1561 if(!dmabuf->write_channel)
1564 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1566 if (!access_ok(VERIFY_READ, buffer, count))
1572 add_wait_queue(&dmabuf->wait, &waita);
1574 set_current_state(TASK_INTERRUPTIBLE);
1575 spin_lock_irqsave(&state->card->lock, flags);
1576 if (PM_SUSPENDED(card)) {
1577 spin_unlock_irqrestore(&card->lock, flags);
1579 if (signal_pending(current)) {
1580 if (!ret) ret = -EAGAIN;
1586 cnt = i810_get_free_write_space(state);
1587 swptr = dmabuf->swptr;
1588 /* Bound the maximum size to how much we can copy to the
1589 * dma buffer before we hit the end. If we have more to
1590 * copy then it will get done in a second pass of this
1591 * loop starting from the beginning of the buffer.
1593 if(cnt > (dmabuf->dmasize - swptr))
1594 cnt = dmabuf->dmasize - swptr;
1595 spin_unlock_irqrestore(&state->card->lock, flags);
1598 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1604 // There is data waiting to be played
1606 * Force the trigger setting since we would
1607 * deadlock with it set any other way
1609 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1610 i810_update_lvi(state,0);
1611 if (file->f_flags & O_NONBLOCK) {
1612 if (!ret) ret = -EAGAIN;
1615 /* Not strictly correct but works */
1616 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1617 /* There are two situations when sleep_on_timeout returns, one is when
1618 the interrupt is serviced correctly and the process is waked up by
1619 ISR ON TIME. Another is when timeout is expired, which means that
1620 either interrupt is NOT serviced correctly (pending interrupt) or it
1621 is TOO LATE for the process to be scheduled to run (scheduler latency)
1622 which results in a (potential) buffer underrun. And worse, there is
1623 NOTHING we can do to prevent it. */
1624 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1626 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1627 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1628 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1629 dmabuf->hwptr, dmabuf->swptr);
1631 /* a buffer underrun, we delay the recovery until next time the
1632 while loop begin and we REALLY have data to play */
1635 if (signal_pending(current)) {
1636 if (!ret) ret = -ERESTARTSYS;
1641 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1642 if (!ret) ret = -EFAULT;
1646 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1648 spin_lock_irqsave(&state->card->lock, flags);
1649 if (PM_SUSPENDED(card)) {
1650 spin_unlock_irqrestore(&card->lock, flags);
1654 dmabuf->swptr = swptr;
1655 pending = dmabuf->count += cnt;
1660 spin_unlock_irqrestore(&state->card->lock, flags);
1663 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1664 i810_update_lvi(state, 0);
1665 set_current_state(TASK_RUNNING);
1666 remove_wait_queue(&dmabuf->wait, &waita);
1671 /* No kernel lock - we have our own spinlock */
1672 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1674 struct i810_state *state = (struct i810_state *)file->private_data;
1675 struct dmabuf *dmabuf = &state->dmabuf;
1676 unsigned long flags;
1677 unsigned int mask = 0;
1681 poll_wait(file, &dmabuf->wait, wait);
1682 spin_lock_irqsave(&state->card->lock, flags);
1683 if (dmabuf->enable & ADC_RUNNING ||
1684 dmabuf->trigger & PCM_ENABLE_INPUT) {
1685 if (i810_get_available_read_data(state) >=
1686 (signed)dmabuf->userfragsize)
1687 mask |= POLLIN | POLLRDNORM;
1689 if (dmabuf->enable & DAC_RUNNING ||
1690 dmabuf->trigger & PCM_ENABLE_OUTPUT) {
1691 if (i810_get_free_write_space(state) >=
1692 (signed)dmabuf->userfragsize)
1693 mask |= POLLOUT | POLLWRNORM;
1695 spin_unlock_irqrestore(&state->card->lock, flags);
1699 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1701 struct i810_state *state = (struct i810_state *)file->private_data;
1702 struct dmabuf *dmabuf = &state->dmabuf;
1707 if (vma->vm_flags & VM_WRITE) {
1708 if (!dmabuf->write_channel &&
1709 (dmabuf->write_channel =
1710 state->card->alloc_pcm_channel(state->card)) == NULL) {
1715 if (vma->vm_flags & VM_READ) {
1716 if (!dmabuf->read_channel &&
1717 (dmabuf->read_channel =
1718 state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1723 if ((ret = prog_dmabuf(state, 0)) != 0)
1727 if (vma->vm_pgoff != 0)
1729 size = vma->vm_end - vma->vm_start;
1730 if (size > (PAGE_SIZE << dmabuf->buforder))
1733 if (remap_page_range(vma, vma->vm_start, virt_to_phys(dmabuf->rawbuf),
1734 size, vma->vm_page_prot))
1737 dmabuf->trigger = 0;
1740 printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1747 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1749 struct i810_state *state = (struct i810_state *)file->private_data;
1750 struct i810_channel *c = NULL;
1751 struct dmabuf *dmabuf = &state->dmabuf;
1752 unsigned long flags;
1753 audio_buf_info abinfo;
1755 unsigned int i_glob_cnt;
1757 struct ac97_codec *codec = state->card->ac97_codec[0];
1760 printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *(int *)arg : 0);
1765 case OSS_GETVERSION:
1767 printk("OSS_GETVERSION\n");
1769 return put_user(SOUND_VERSION, (int *)arg);
1771 case SNDCTL_DSP_RESET:
1773 printk("SNDCTL_DSP_RESET\n");
1775 spin_lock_irqsave(&state->card->lock, flags);
1776 if (dmabuf->enable == DAC_RUNNING) {
1777 c = dmabuf->write_channel;
1780 if (dmabuf->enable == ADC_RUNNING) {
1781 c = dmabuf->read_channel;
1785 outb(2, state->card->iobase+c->port+OFF_CR); /* reset DMA machine */
1786 while ( inb(state->card->iobase+c->port+OFF_CR) & 2 )
1788 outl((u32)state->card->chandma +
1789 c->num*sizeof(struct i810_channel),
1790 state->card->iobase+c->port+OFF_BDBAR);
1791 CIV_TO_LVI(state->card->iobase+c->port, 0);
1794 spin_unlock_irqrestore(&state->card->lock, flags);
1795 synchronize_irq(state->card->pci_dev->irq);
1797 dmabuf->swptr = dmabuf->hwptr = 0;
1798 dmabuf->count = dmabuf->total_bytes = 0;
1801 case SNDCTL_DSP_SYNC:
1803 printk("SNDCTL_DSP_SYNC\n");
1805 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1807 if((val = drain_dac(state, 1)))
1809 dmabuf->total_bytes = 0;
1812 case SNDCTL_DSP_SPEED: /* set smaple rate */
1814 printk("SNDCTL_DSP_SPEED\n");
1816 if (get_user(val, (int *)arg))
1819 if (file->f_mode & FMODE_WRITE) {
1820 if ( (state->card->ac97_status & SPDIF_ON) ) { /* S/PDIF Enabled */
1821 /* AD1886 only supports 48000, need to check that */
1822 if ( i810_valid_spdif_rate ( codec, val ) ) {
1824 i810_set_spdif_output ( state, -1, 0 );
1827 spin_lock_irqsave(&state->card->lock, flags);
1828 i810_set_dac_rate(state, val);
1829 spin_unlock_irqrestore(&state->card->lock, flags);
1830 /* Set S/PDIF transmitter rate. */
1831 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1832 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1835 } else { /* Not a valid rate for S/PDIF, ignore it */
1841 spin_lock_irqsave(&state->card->lock, flags);
1842 i810_set_dac_rate(state, val);
1843 spin_unlock_irqrestore(&state->card->lock, flags);
1846 if (file->f_mode & FMODE_READ) {
1849 spin_lock_irqsave(&state->card->lock, flags);
1850 i810_set_adc_rate(state, val);
1851 spin_unlock_irqrestore(&state->card->lock, flags);
1854 return put_user(dmabuf->rate, (int *)arg);
1856 case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
1858 printk("SNDCTL_DSP_STEREO\n");
1860 if (dmabuf->enable & DAC_RUNNING) {
1863 if (dmabuf->enable & ADC_RUNNING) {
1866 return put_user(1, (int *)arg);
1868 case SNDCTL_DSP_GETBLKSIZE:
1869 if (file->f_mode & FMODE_WRITE) {
1870 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
1873 if (file->f_mode & FMODE_READ) {
1874 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
1878 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
1880 return put_user(dmabuf->userfragsize, (int *)arg);
1882 case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
1884 printk("SNDCTL_DSP_GETFMTS\n");
1886 return put_user(AFMT_S16_LE, (int *)arg);
1888 case SNDCTL_DSP_SETFMT: /* Select sample format */
1890 printk("SNDCTL_DSP_SETFMT\n");
1892 return put_user(AFMT_S16_LE, (int *)arg);
1894 case SNDCTL_DSP_CHANNELS:
1896 printk("SNDCTL_DSP_CHANNELS\n");
1898 if (get_user(val, (int *)arg))
1902 if (dmabuf->enable & DAC_RUNNING) {
1905 if (dmabuf->enable & ADC_RUNNING) {
1909 return put_user(state->card->channels, (int *)arg);
1912 /* ICH and ICH0 only support 2 channels */
1913 if ( state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AA_5
1914 || state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AB_5)
1915 return put_user(2, (int *)arg);
1917 /* Multi-channel support was added with ICH2. Bits in */
1918 /* Global Status and Global Control register are now */
1919 /* used to indicate this. */
1921 i_glob_cnt = inl(state->card->iobase + GLOB_CNT);
1923 /* Current # of channels enabled */
1924 if ( i_glob_cnt & 0x0100000 )
1926 else if ( i_glob_cnt & 0x0200000 )
1932 case 2: /* 2 channels is always supported */
1933 outl(i_glob_cnt & 0xffcfffff,
1934 state->card->iobase + GLOB_CNT);
1935 /* Do we need to change mixer settings???? */
1937 case 4: /* Supported on some chipsets, better check first */
1938 if ( state->card->channels >= 4 ) {
1939 outl((i_glob_cnt & 0xffcfffff) | 0x100000,
1940 state->card->iobase + GLOB_CNT);
1941 /* Do we need to change mixer settings??? */
1946 case 6: /* Supported on some chipsets, better check first */
1947 if ( state->card->channels >= 6 ) {
1948 outl((i_glob_cnt & 0xffcfffff) | 0x200000,
1949 state->card->iobase + GLOB_CNT);
1950 /* Do we need to change mixer settings??? */
1955 default: /* nothing else is ever supported by the chipset */
1960 return put_user(val, (int *)arg);
1962 case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
1963 /* we update the swptr to the end of the last sg segment then return */
1965 printk("SNDCTL_DSP_POST\n");
1967 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
1969 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
1970 val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
1971 dmabuf->swptr += val;
1972 dmabuf->count += val;
1976 case SNDCTL_DSP_SUBDIVIDE:
1977 if (dmabuf->subdivision)
1979 if (get_user(val, (int *)arg))
1981 if (val != 1 && val != 2 && val != 4)
1984 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
1986 dmabuf->subdivision = val;
1990 case SNDCTL_DSP_SETFRAGMENT:
1991 if (get_user(val, (int *)arg))
1994 dmabuf->ossfragsize = 1<<(val & 0xffff);
1995 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
1996 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags)
1999 * Bound the frag size into our allowed range of 256 - 4096
2001 if (dmabuf->ossfragsize < 256)
2002 dmabuf->ossfragsize = 256;
2003 else if (dmabuf->ossfragsize > 4096)
2004 dmabuf->ossfragsize = 4096;
2006 * The numfrags could be something reasonable, or it could
2007 * be 0xffff meaning "Give me as much as possible". So,
2008 * we check the numfrags * fragsize doesn't exceed our
2009 * 64k buffer limit, nor is it less than our 8k minimum.
2010 * If it fails either one of these checks, then adjust the
2011 * number of fragments, not the size of them. It's OK if
2012 * our number of fragments doesn't equal 32 or anything
2013 * like our hardware based number now since we are using
2014 * a different frag count for the hardware. Before we get
2015 * into this though, bound the maxfrags to avoid overflow
2016 * issues. A reasonable bound would be 64k / 256 since our
2017 * maximum buffer size is 64k and our minimum frag size is
2018 * 256. On the other end, our minimum buffer size is 8k and
2019 * our maximum frag size is 4k, so the lower bound should
2023 if(dmabuf->ossmaxfrags > 256)
2024 dmabuf->ossmaxfrags = 256;
2025 else if (dmabuf->ossmaxfrags < 2)
2026 dmabuf->ossmaxfrags = 2;
2028 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
2029 while (val < 8192) {
2031 dmabuf->ossmaxfrags <<= 1;
2033 while (val > 65536) {
2035 dmabuf->ossmaxfrags >>= 1;
2039 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
2040 dmabuf->ossfragsize, dmabuf->ossmaxfrags);
2045 case SNDCTL_DSP_GETOSPACE:
2046 if (!(file->f_mode & FMODE_WRITE))
2048 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2050 spin_lock_irqsave(&state->card->lock, flags);
2051 i810_update_ptr(state);
2052 abinfo.fragsize = dmabuf->userfragsize;
2053 abinfo.fragstotal = dmabuf->userfrags;
2055 abinfo.bytes = dmabuf->dmasize;
2057 abinfo.bytes = i810_get_free_write_space(state);
2058 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2059 spin_unlock_irqrestore(&state->card->lock, flags);
2060 #if defined(DEBUG) || defined(DEBUG_MMAP)
2061 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
2062 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2064 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2066 case SNDCTL_DSP_GETOPTR:
2067 if (!(file->f_mode & FMODE_WRITE))
2069 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2071 spin_lock_irqsave(&state->card->lock, flags);
2072 val = i810_get_free_write_space(state);
2073 cinfo.bytes = dmabuf->total_bytes;
2074 cinfo.ptr = dmabuf->hwptr;
2075 cinfo.blocks = val/dmabuf->userfragsize;
2076 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
2077 dmabuf->count += val;
2078 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2079 __i810_update_lvi(state, 0);
2081 spin_unlock_irqrestore(&state->card->lock, flags);
2082 #if defined(DEBUG) || defined(DEBUG_MMAP)
2083 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
2084 cinfo.blocks, cinfo.ptr, dmabuf->count);
2086 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2088 case SNDCTL_DSP_GETISPACE:
2089 if (!(file->f_mode & FMODE_READ))
2091 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
2093 spin_lock_irqsave(&state->card->lock, flags);
2094 abinfo.bytes = i810_get_available_read_data(state);
2095 abinfo.fragsize = dmabuf->userfragsize;
2096 abinfo.fragstotal = dmabuf->userfrags;
2097 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2098 spin_unlock_irqrestore(&state->card->lock, flags);
2099 #if defined(DEBUG) || defined(DEBUG_MMAP)
2100 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
2101 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2103 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2105 case SNDCTL_DSP_GETIPTR:
2106 if (!(file->f_mode & FMODE_READ))
2108 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2110 spin_lock_irqsave(&state->card->lock, flags);
2111 val = i810_get_available_read_data(state);
2112 cinfo.bytes = dmabuf->total_bytes;
2113 cinfo.blocks = val/dmabuf->userfragsize;
2114 cinfo.ptr = dmabuf->hwptr;
2115 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) {
2116 dmabuf->count -= val;
2117 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2118 __i810_update_lvi(state, 1);
2120 spin_unlock_irqrestore(&state->card->lock, flags);
2121 #if defined(DEBUG) || defined(DEBUG_MMAP)
2122 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
2123 cinfo.blocks, cinfo.ptr, dmabuf->count);
2125 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2127 case SNDCTL_DSP_NONBLOCK:
2129 printk("SNDCTL_DSP_NONBLOCK\n");
2131 file->f_flags |= O_NONBLOCK;
2134 case SNDCTL_DSP_GETCAPS:
2136 printk("SNDCTL_DSP_GETCAPS\n");
2138 return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
2141 case SNDCTL_DSP_GETTRIGGER:
2144 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
2146 return put_user(dmabuf->trigger, (int *)arg);
2148 case SNDCTL_DSP_SETTRIGGER:
2149 if (get_user(val, (int *)arg))
2151 #if defined(DEBUG) || defined(DEBUG_MMAP)
2152 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
2154 /* silently ignore invalid PCM_ENABLE_xxx bits,
2155 * like the other drivers do
2157 if (!(file->f_mode & FMODE_READ ))
2158 val &= ~PCM_ENABLE_INPUT;
2159 if (!(file->f_mode & FMODE_WRITE ))
2160 val &= ~PCM_ENABLE_OUTPUT;
2161 if((file->f_mode & FMODE_READ) && !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
2164 if((file->f_mode & FMODE_WRITE) && !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
2167 dmabuf->trigger = val;
2168 if((val & PCM_ENABLE_OUTPUT) && !(dmabuf->enable & DAC_RUNNING)) {
2169 if (!dmabuf->write_channel) {
2171 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
2172 if (!dmabuf->write_channel)
2175 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
2177 if (dmabuf->mapped) {
2178 spin_lock_irqsave(&state->card->lock, flags);
2179 i810_update_ptr(state);
2181 dmabuf->swptr = dmabuf->hwptr;
2182 dmabuf->count = i810_get_free_write_space(state);
2183 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize;
2184 spin_unlock_irqrestore(&state->card->lock, flags);
2186 i810_update_lvi(state, 0);
2189 if((val & PCM_ENABLE_INPUT) && !(dmabuf->enable & ADC_RUNNING)) {
2190 if (!dmabuf->read_channel) {
2192 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
2193 if (!dmabuf->read_channel)
2196 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
2198 if (dmabuf->mapped) {
2199 spin_lock_irqsave(&state->card->lock, flags);
2200 i810_update_ptr(state);
2201 dmabuf->swptr = dmabuf->hwptr;
2203 spin_unlock_irqrestore(&state->card->lock, flags);
2205 i810_update_lvi(state, 1);
2210 case SNDCTL_DSP_SETDUPLEX:
2212 printk("SNDCTL_DSP_SETDUPLEX\n");
2216 case SNDCTL_DSP_GETODELAY:
2217 if (!(file->f_mode & FMODE_WRITE))
2219 spin_lock_irqsave(&state->card->lock, flags);
2220 i810_update_ptr(state);
2221 val = dmabuf->count;
2222 spin_unlock_irqrestore(&state->card->lock, flags);
2224 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
2226 return put_user(val, (int *)arg);
2228 case SOUND_PCM_READ_RATE:
2230 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
2232 return put_user(dmabuf->rate, (int *)arg);
2234 case SOUND_PCM_READ_CHANNELS:
2236 printk("SOUND_PCM_READ_CHANNELS\n");
2238 return put_user(2, (int *)arg);
2240 case SOUND_PCM_READ_BITS:
2242 printk("SOUND_PCM_READ_BITS\n");
2244 return put_user(AFMT_S16_LE, (int *)arg);
2246 case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
2248 printk("SNDCTL_DSP_SETSPDIF\n");
2250 if (get_user(val, (int *)arg))
2253 /* Check to make sure the codec supports S/PDIF transmitter */
2255 if((state->card->ac97_features & 4)) {
2256 /* mask out the transmitter speed bits so the user can't set them */
2259 /* Add the current transmitter speed bits to the passed value */
2260 ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2261 val |= (ret & 0x3000);
2263 i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
2264 if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
2265 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
2271 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2273 return put_user(val, (int *)arg);
2275 case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2277 printk("SNDCTL_DSP_GETSPDIF\n");
2279 if (get_user(val, (int *)arg))
2282 /* Check to make sure the codec supports S/PDIF transmitter */
2284 if(!(state->card->ac97_features & 4)) {
2286 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2290 val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2292 //return put_user((val & 0xcfff), (int *)arg);
2293 return put_user(val, (int *)arg);
2295 case SNDCTL_DSP_GETCHANNELMASK:
2297 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2299 if (get_user(val, (int *)arg))
2302 /* Based on AC'97 DAC support, not ICH hardware */
2303 val = DSP_BIND_FRONT;
2304 if ( state->card->ac97_features & 0x0004 )
2305 val |= DSP_BIND_SPDIF;
2307 if ( state->card->ac97_features & 0x0080 )
2308 val |= DSP_BIND_SURR;
2309 if ( state->card->ac97_features & 0x0140 )
2310 val |= DSP_BIND_CENTER_LFE;
2312 return put_user(val, (int *)arg);
2314 case SNDCTL_DSP_BIND_CHANNEL:
2316 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2318 if (get_user(val, (int *)arg))
2320 if ( val == DSP_BIND_QUERY ) {
2321 val = DSP_BIND_FRONT; /* Always report this as being enabled */
2322 if ( state->card->ac97_status & SPDIF_ON )
2323 val |= DSP_BIND_SPDIF;
2325 if ( state->card->ac97_status & SURR_ON )
2326 val |= DSP_BIND_SURR;
2327 if ( state->card->ac97_status & CENTER_LFE_ON )
2328 val |= DSP_BIND_CENTER_LFE;
2330 } else { /* Not a query, set it */
2331 if (!(file->f_mode & FMODE_WRITE))
2333 if ( dmabuf->enable == DAC_RUNNING ) {
2336 if ( val & DSP_BIND_SPDIF ) { /* Turn on SPDIF */
2337 /* Ok, this should probably define what slots
2338 * to use. For now, we'll only set it to the
2341 * non multichannel codec maps to slots 3&4
2342 * 2 channel codec maps to slots 7&8
2343 * 4 channel codec maps to slots 6&9
2344 * 6 channel codec maps to slots 10&11
2346 * there should be some way for the app to
2347 * select the slot assignment.
2350 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2351 if ( !(state->card->ac97_status & SPDIF_ON) )
2352 val &= ~DSP_BIND_SPDIF;
2357 /* Turn off S/PDIF if it was on */
2358 if ( state->card->ac97_status & SPDIF_ON )
2359 i810_set_spdif_output ( state, -1, 0 );
2361 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2363 case DSP_BIND_FRONT:
2366 case DSP_BIND_FRONT|DSP_BIND_SURR:
2369 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2373 val = DSP_BIND_FRONT;
2377 i810_set_dac_channels ( state, channels );
2379 /* check that they really got turned on */
2380 if (!(state->card->ac97_status & SURR_ON))
2381 val &= ~DSP_BIND_SURR;
2382 if (!(state->card->ac97_status & CENTER_LFE_ON))
2383 val &= ~DSP_BIND_CENTER_LFE;
2386 return put_user(val, (int *)arg);
2388 case SNDCTL_DSP_MAPINBUF:
2389 case SNDCTL_DSP_MAPOUTBUF:
2390 case SNDCTL_DSP_SETSYNCRO:
2391 case SOUND_PCM_WRITE_FILTER:
2392 case SOUND_PCM_READ_FILTER:
2394 printk("SNDCTL_* -EINVAL\n");
2401 static int i810_open(struct inode *inode, struct file *file)
2404 struct i810_card *card = devs;
2405 struct i810_state *state = NULL;
2406 struct dmabuf *dmabuf = NULL;
2408 /* find an avaiable virtual channel (instance of /dev/dsp) */
2409 while (card != NULL) {
2411 * If we are initializing and then fail, card could go
2412 * away unuexpectedly while we are in the for() loop.
2413 * So, check for card on each iteration before we check
2414 * for card->initializing to avoid a possible oops.
2415 * This usually only matters for times when the driver is
2416 * autoloaded by kmod.
2418 for (i = 0; i < 50 && card && card->initializing; i++) {
2419 set_current_state(TASK_UNINTERRUPTIBLE);
2420 schedule_timeout(HZ/20);
2422 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) {
2423 if (card->states[i] == NULL) {
2424 state = card->states[i] = (struct i810_state *)
2425 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2428 memset(state, 0, sizeof(struct i810_state));
2429 dmabuf = &state->dmabuf;
2435 /* no more virtual channel avaiable */
2440 /* initialize the virtual channel */
2443 state->magic = I810_STATE_MAGIC;
2444 init_waitqueue_head(&dmabuf->wait);
2445 init_MUTEX(&state->open_sem);
2446 file->private_data = state;
2447 dmabuf->trigger = 0;
2449 /* allocate hardware channels */
2450 if(file->f_mode & FMODE_READ) {
2451 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2452 kfree (card->states[i]);
2453 card->states[i] = NULL;
2456 dmabuf->trigger |= PCM_ENABLE_INPUT;
2457 i810_set_adc_rate(state, 8000);
2459 if(file->f_mode & FMODE_WRITE) {
2460 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2461 /* make sure we free the record channel allocated above */
2462 if(file->f_mode & FMODE_READ)
2463 card->free_pcm_channel(card,dmabuf->read_channel->num);
2464 kfree (card->states[i]);
2465 card->states[i] = NULL;
2468 /* Initialize to 8kHz? What if we don't support 8kHz? */
2469 /* Let's change this to check for S/PDIF stuff */
2471 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2472 if ( spdif_locked ) {
2473 i810_set_dac_rate(state, spdif_locked);
2474 i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2476 i810_set_dac_rate(state, 8000);
2477 /* Put the ACLink in 2 channel mode by default */
2478 i = inl(card->iobase + GLOB_CNT);
2479 outl(i & 0xffcfffff, card->iobase + GLOB_CNT);
2483 /* set default sample format. According to OSS Programmer's Guide /dev/dsp
2484 should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2485 /dev/dspW will accept 16-bits sample, but we don't support those so we
2486 set it immediately to stereo and 16bit, which is all we do support */
2487 dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2488 dmabuf->ossfragsize = 0;
2489 dmabuf->ossmaxfrags = 0;
2490 dmabuf->subdivision = 0;
2492 state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2497 static int i810_release(struct inode *inode, struct file *file)
2499 struct i810_state *state = (struct i810_state *)file->private_data;
2500 struct i810_card *card = state->card;
2501 struct dmabuf *dmabuf = &state->dmabuf;
2502 unsigned long flags;
2506 /* stop DMA state machine and free DMA buffers/channels */
2507 if(dmabuf->trigger & PCM_ENABLE_OUTPUT) {
2508 drain_dac(state, 0);
2510 if(dmabuf->trigger & PCM_ENABLE_INPUT) {
2513 spin_lock_irqsave(&card->lock, flags);
2514 dealloc_dmabuf(state);
2515 if (file->f_mode & FMODE_WRITE) {
2516 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2518 if (file->f_mode & FMODE_READ) {
2519 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2522 state->card->states[state->virt] = NULL;
2524 spin_unlock_irqrestore(&card->lock, flags);
2530 static /*const*/ struct file_operations i810_audio_fops = {
2531 .owner = THIS_MODULE,
2532 .llseek = no_llseek,
2534 .write = i810_write,
2536 .ioctl = i810_ioctl,
2539 .release = i810_release,
2542 /* Write AC97 codec registers */
2544 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg)
2546 struct i810_card *card = dev->private_data;
2548 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2550 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2555 u16 ans = readw(card->ac97base_mmio + reg_set);
2556 printk(KERN_DEBUG "i810_audio: ac97_get_mmio(%d) -> 0x%04X\n", ((int) reg_set) & 0xffff, (u32) ans);
2560 return readw(card->ac97base_mmio + reg_set);
2564 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg)
2566 struct i810_card *card = dev->private_data;
2568 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2570 while(count-- && (inb(card->iobase + CAS) & 1))
2573 return inw(card->ac97base + reg_set);
2576 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data)
2578 struct i810_card *card = dev->private_data;
2580 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2582 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2585 writew(data, card->ac97base_mmio + reg_set);
2588 printk(KERN_DEBUG "i810_audio: ac97_set_mmio(0x%04X, %d)\n", (u32) data, ((int) reg_set) & 0xffff);
2592 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data)
2594 struct i810_card *card = dev->private_data;
2596 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2598 while(count-- && (inb(card->iobase + CAS) & 1))
2601 outw(data, card->ac97base + reg_set);
2604 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2606 struct i810_card *card = dev->private_data;
2609 spin_lock(&card->ac97_lock);
2610 if (card->use_mmio) {
2611 ret = i810_ac97_get_mmio(dev, reg);
2614 ret = i810_ac97_get_io(dev, reg);
2616 spin_unlock(&card->ac97_lock);
2621 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2623 struct i810_card *card = dev->private_data;
2625 spin_lock(&card->ac97_lock);
2626 if (card->use_mmio) {
2627 i810_ac97_set_mmio(dev, reg, data);
2630 i810_ac97_set_io(dev, reg, data);
2632 spin_unlock(&card->ac97_lock);
2636 /* OSS /dev/mixer file operation methods */
2638 static int i810_open_mixdev(struct inode *inode, struct file *file)
2641 int minor = iminor(inode);
2642 struct i810_card *card = devs;
2644 for (card = devs; card != NULL; card = card->next) {
2646 * If we are initializing and then fail, card could go
2647 * away unuexpectedly while we are in the for() loop.
2648 * So, check for card on each iteration before we check
2649 * for card->initializing to avoid a possible oops.
2650 * This usually only matters for times when the driver is
2651 * autoloaded by kmod.
2653 for (i = 0; i < 50 && card && card->initializing; i++) {
2654 set_current_state(TASK_UNINTERRUPTIBLE);
2655 schedule_timeout(HZ/20);
2657 for (i = 0; i < NR_AC97 && card && !card->initializing; i++)
2658 if (card->ac97_codec[i] != NULL &&
2659 card->ac97_codec[i]->dev_mixer == minor) {
2660 file->private_data = card->ac97_codec[i];
2667 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2670 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2672 return codec->mixer_ioctl(codec, cmd, arg);
2675 static /*const*/ struct file_operations i810_mixer_fops = {
2676 .owner = THIS_MODULE,
2677 .llseek = no_llseek,
2678 .ioctl = i810_ioctl_mixdev,
2679 .open = i810_open_mixdev,
2682 /* AC97 codec initialisation. These small functions exist so we don't
2683 duplicate code between module init and apm resume */
2685 static inline int i810_ac97_exists(struct i810_card *card, int ac97_number)
2687 u32 reg = inl(card->iobase + GLOB_STA);
2688 switch (ac97_number) {
2690 return reg & (1<<8);
2692 return reg & (1<<9);
2694 return reg & (1<<28);
2699 static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
2701 i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2702 i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2703 i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2705 return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
2709 static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
2711 /* Returns 0 on failure */
2714 if (ac97_probe_codec(codec) == 0) return 0;
2716 /* power it all up */
2717 i810_ac97_set(codec, AC97_POWER_CONTROL,
2718 i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2720 /* wait for analog ready */
2721 for (i=100; i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); i--)
2723 set_current_state(TASK_UNINTERRUPTIBLE);
2724 schedule_timeout(HZ/20);
2729 static int is_new_ich(u16 pci_id)
2732 case PCI_DEVICE_ID_INTEL_82801DB_5:
2733 case PCI_DEVICE_ID_INTEL_82801EB_5:
2734 case PCI_DEVICE_ID_INTEL_ESB_5:
2735 case PCI_DEVICE_ID_INTEL_ICH6_18:
2744 static inline int ich_use_mmio(struct i810_card *card)
2746 return is_new_ich(card->pci_id) && card->use_mmio;
2750 * i810_ac97_power_up_bus - bring up AC97 link
2751 * @card : ICH audio device to power up
2753 * Bring up the ACLink AC97 codec bus
2756 static int i810_ac97_power_up_bus(struct i810_card *card)
2758 u32 reg = inl(card->iobase + GLOB_CNT);
2760 int primary_codec_id = 0;
2762 if((reg&2)==0) /* Cold required */
2767 reg&=~8; /* ACLink on */
2769 /* At this point we deassert AC_RESET # */
2770 outl(reg , card->iobase + GLOB_CNT);
2772 /* We must now allow time for the Codec initialisation.
2773 600mS is the specified time */
2777 if((inl(card->iobase+GLOB_CNT)&4)==0)
2780 set_current_state(TASK_UNINTERRUPTIBLE);
2781 schedule_timeout(HZ/20);
2785 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2789 set_current_state(TASK_UNINTERRUPTIBLE);
2790 schedule_timeout(HZ/2);
2793 * See if the primary codec comes ready. This must happen
2794 * before we start doing DMA stuff
2796 /* see i810_ac97_init for the next 7 lines (jsaw) */
2797 inw(card->ac97base);
2798 if (ich_use_mmio(card)) {
2799 primary_codec_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2800 printk(KERN_INFO "i810_audio: Primary codec has ID %d\n",
2804 if(! i810_ac97_exists(card, primary_codec_id))
2806 printk(KERN_INFO "i810_audio: Codec not ready.. wait.. ");
2807 set_current_state(TASK_UNINTERRUPTIBLE);
2808 schedule_timeout(HZ); /* actually 600mS by the spec */
2810 if(i810_ac97_exists(card, primary_codec_id))
2813 printk("no response.\n");
2815 inw(card->ac97base);
2819 static int __devinit i810_ac97_init(struct i810_card *card)
2823 int total_channels = 0;
2824 int nr_ac97_max = card_cap[card->pci_id_internal].nr_ac97;
2825 struct ac97_codec *codec;
2829 if(!i810_ac97_power_up_bus(card)) return 0;
2831 /* Number of channels supported */
2832 /* What about the codec? Just because the ICH supports */
2833 /* multiple channels doesn't mean the codec does. */
2834 /* we'll have to modify this in the codec section below */
2835 /* to reflect what the codec has. */
2836 /* ICH and ICH0 only support 2 channels so don't bother */
2840 reg = inl(card->iobase + GLOB_STA);
2841 if ( reg & 0x0200000 )
2843 else if ( reg & 0x0100000 )
2845 printk(KERN_INFO "i810_audio: Audio Controller supports %d channels.\n", card->channels);
2846 printk(KERN_INFO "i810_audio: Defaulting to base 2 channel mode.\n");
2847 reg = inl(card->iobase + GLOB_CNT);
2848 outl(reg & 0xffcfffff, card->iobase + GLOB_CNT);
2850 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++)
2851 card->ac97_codec[num_ac97] = NULL;
2853 /*@FIXME I don't know, if I'm playing to safe here... (jsaw) */
2854 if ((nr_ac97_max > 2) && !card->use_mmio) nr_ac97_max = 2;
2856 for (num_ac97 = 0; num_ac97 < nr_ac97_max; num_ac97++) {
2858 printk(KERN_INFO "i810_audio: Resetting connection %d\n", num_ac97);
2859 if (card->use_mmio) readw(card->ac97base_mmio + 0x80*num_ac97);
2860 else inw(card->ac97base + 0x80*num_ac97);
2862 /* If we have the SDATA_IN Map Register, as on ICH4, we
2863 do not loop thru all possible codec IDs but thru all
2864 possible IO channels. Bit 0:1 of SDM then holds the
2865 last codec ID spoken to.
2867 if (ich_use_mmio(card)) {
2868 ac97_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2869 printk(KERN_INFO "i810_audio: Connection %d with codec id %d\n",
2876 /* The ICH programmer's reference says you should */
2877 /* check the ready status before probing. So we chk */
2878 /* What do we do if it's not ready? Wait and try */
2879 /* again, or abort? */
2880 if (!i810_ac97_exists(card, ac97_id)) {
2882 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
2885 if ((codec = ac97_alloc_codec()) == NULL)
2888 /* initialize some basic codec information, other fields will be filled
2889 in ac97_probe_codec */
2890 codec->private_data = card;
2891 codec->id = ac97_id;
2892 card->ac97_id_map[ac97_id] = num_ac97 * 0x80;
2894 if (card->use_mmio) {
2895 codec->codec_read = i810_ac97_get_mmio;
2896 codec->codec_write = i810_ac97_set_mmio;
2899 codec->codec_read = i810_ac97_get_io;
2900 codec->codec_write = i810_ac97_set_io;
2903 if(!i810_ac97_probe_and_powerup(card,codec)) {
2904 printk(KERN_ERR "i810_audio: timed out waiting for codec %d analog ready.\n", ac97_id);
2905 ac97_release_codec(codec);
2906 break; /* it didn't work */
2908 /* Store state information about S/PDIF transmitter */
2909 card->ac97_status = 0;
2911 /* Don't attempt to get eid until powerup is complete */
2912 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2916 printk(KERN_WARNING "i810_audio: no codec attached ?\n");
2917 ac97_release_codec(codec);
2921 /* Check for an AC97 1.0 soft modem (ID1) */
2925 printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", ac97_id);
2926 ac97_release_codec(codec);
2930 card->ac97_features = eid;
2932 /* Now check the codec for useful features to make up for
2933 the dumbness of the 810 hardware engine */
2936 printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
2939 if(!i810_ac97_enable_variable_rate(codec)) {
2940 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
2941 card->ac97_features&=~1;
2945 /* Turn on the amplifier */
2947 codec->codec_write(codec, AC97_POWER_CONTROL,
2948 codec->codec_read(codec, AC97_POWER_CONTROL) & ~0x8000);
2950 /* Determine how many channels the codec(s) support */
2951 /* - The primary codec always supports 2 */
2952 /* - If the codec supports AMAP, surround DACs will */
2953 /* automaticlly get assigned to slots. */
2954 /* * Check for surround DACs and increment if */
2956 /* - Else check if the codec is revision 2.2 */
2957 /* * If surround DACs exist, assign them to slots */
2958 /* and increment channel count. */
2960 /* All of this only applies to ICH2 and above. ICH */
2961 /* and ICH0 only support 2 channels. ICH2 will only */
2962 /* support multiple codecs in a "split audio" config. */
2963 /* as described above. */
2965 /* TODO: Remove all the debugging messages! */
2967 if((eid & 0xc000) == 0) /* primary codec */
2968 total_channels += 2;
2970 if(eid & 0x200) { /* GOOD, AMAP support */
2971 if (eid & 0x0080) /* L/R Surround channels */
2972 total_channels += 2;
2973 if (eid & 0x0140) /* LFE and Center channels */
2974 total_channels += 2;
2975 printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", ac97_id, total_channels);
2976 } else if (eid & 0x0400) { /* this only works on 2.2 compliant codecs */
2978 if((eid & 0xc000) != 0) {
2979 switch ( total_channels ) {
2981 /* Set dsa1, dsa0 to 01 */
2985 /* Set dsa1, dsa0 to 10 */
2989 /* Set dsa1, dsa0 to 11 */
2993 total_channels += 2;
2995 i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
2996 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2997 printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", ac97_id, eid);
2998 if (eid & 0x0080) /* L/R Surround channels */
2999 total_channels += 2;
3000 if (eid & 0x0140) /* LFE and Center channels */
3001 total_channels += 2;
3002 printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", ac97_id, total_channels);
3004 printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", ac97_id, total_channels);
3007 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
3008 printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
3009 ac97_release_codec(codec);
3013 card->ac97_codec[num_ac97] = codec;
3016 /* pick the minimum of channels supported by ICHx or codec(s) */
3017 card->channels = (card->channels > total_channels)?total_channels:card->channels;
3022 static void __devinit i810_configure_clocking (void)
3024 struct i810_card *card;
3025 struct i810_state *state;
3026 struct dmabuf *dmabuf;
3027 unsigned int i, offset, new_offset;
3028 unsigned long flags;
3031 /* We could try to set the clocking for multiple cards, but can you even have
3032 * more than one i810 in a machine? Besides, clocking is global, so unless
3033 * someone actually thinks more than one i810 in a machine is possible and
3034 * decides to rewrite that little bit, setting the rate for more than one card
3035 * is a waste of time.
3038 state = card->states[0] = (struct i810_state *)
3039 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
3042 memset(state, 0, sizeof(struct i810_state));
3043 dmabuf = &state->dmabuf;
3045 dmabuf->write_channel = card->alloc_pcm_channel(card);
3048 state->magic = I810_STATE_MAGIC;
3049 init_waitqueue_head(&dmabuf->wait);
3050 init_MUTEX(&state->open_sem);
3051 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
3052 dmabuf->trigger = PCM_ENABLE_OUTPUT;
3053 i810_set_spdif_output(state, -1, 0);
3054 i810_set_dac_channels(state, 2);
3055 i810_set_dac_rate(state, 48000);
3056 if(prog_dmabuf(state, 0) != 0) {
3057 goto config_out_nodmabuf;
3059 if(dmabuf->dmasize < 16384) {
3062 dmabuf->count = dmabuf->dmasize;
3063 CIV_TO_LVI(card->iobase+dmabuf->write_channel->port, -1);
3064 local_irq_save(flags);
3066 offset = i810_get_dma_addr(state, 0);
3068 new_offset = i810_get_dma_addr(state, 0);
3070 local_irq_restore(flags);
3071 i = new_offset - offset;
3072 #ifdef DEBUG_INTERRUPTS
3073 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
3078 if (i > 48500 || i < 47500) {
3079 clocking = clocking * clocking / i;
3080 printk("i810_audio: setting clocking to %d\n", clocking);
3083 dealloc_dmabuf(state);
3084 config_out_nodmabuf:
3085 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
3087 card->states[0] = NULL;
3091 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
3092 until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
3094 static int __devinit i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
3096 struct i810_card *card;
3098 if (pci_enable_device(pci_dev))
3101 if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
3102 printk(KERN_ERR "i810_audio: architecture does not support"
3103 " 32bit PCI busmaster DMA\n");
3107 if( pci_resource_start(pci_dev, 1) == 0)
3109 /* MMIO only ICH5 .. here be dragons .. */
3110 printk(KERN_ERR "i810_audio: Pure MMIO interfaces not yet supported.\n");
3114 if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
3115 printk(KERN_ERR "i810_audio: out of memory\n");
3118 memset(card, 0, sizeof(*card));
3120 card->initializing = 1;
3121 card->pci_dev = pci_dev;
3122 card->pci_id = pci_id->device;
3123 card->ac97base = pci_resource_start (pci_dev, 0);
3124 card->iobase = pci_resource_start (pci_dev, 1);
3126 /* if chipset could have mmio capability, check it */
3127 if (card_cap[pci_id->driver_data].flags & CAP_MMIO) {
3128 card->ac97base_mmio_phys = pci_resource_start (pci_dev, 2);
3129 card->iobase_mmio_phys = pci_resource_start (pci_dev, 3);
3131 if ((card->ac97base_mmio_phys) && (card->iobase_mmio_phys)) {
3135 card->ac97base_mmio_phys = 0;
3136 card->iobase_mmio_phys = 0;
3140 card->irq = pci_dev->irq;
3142 card->magic = I810_CARD_MAGIC;
3144 card->pm_suspended=0;
3146 spin_lock_init(&card->lock);
3147 spin_lock_init(&card->ac97_lock);
3150 pci_set_master(pci_dev);
3152 printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, "
3153 "MEM 0x%04lx and 0x%04lx, IRQ %d\n",
3154 card_names[pci_id->driver_data],
3155 card->iobase, card->ac97base,
3156 card->ac97base_mmio_phys, card->iobase_mmio_phys,
3159 card->alloc_pcm_channel = i810_alloc_pcm_channel;
3160 card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
3161 card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
3162 card->free_pcm_channel = i810_free_pcm_channel;
3164 if ((card->channel = pci_alloc_consistent(pci_dev,
3165 sizeof(struct i810_channel)*NR_HW_CH, &card->chandma)) == NULL) {
3166 printk(KERN_ERR "i810: cannot allocate channel DMA memory\n");
3170 { /* We may dispose of this altogether some time soon, so... */
3171 struct i810_channel *cp = card->channel;
3184 /* claim our iospace and irq */
3185 request_region(card->iobase, 64, card_names[pci_id->driver_data]);
3186 request_region(card->ac97base, 256, card_names[pci_id->driver_data]);
3188 if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
3189 card_names[pci_id->driver_data], card)) {
3190 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
3194 if (card->use_mmio) {
3195 if (request_mem_region(card->ac97base_mmio_phys, 512, "ich_audio MMBAR")) {
3196 if ((card->ac97base_mmio = ioremap(card->ac97base_mmio_phys, 512))) { /*@FIXME can ioremap fail? don't know (jsaw) */
3197 if (request_mem_region(card->iobase_mmio_phys, 256, "ich_audio MBBAR")) {
3198 if ((card->iobase_mmio = ioremap(card->iobase_mmio_phys, 256))) {
3199 printk(KERN_INFO "i810: %s mmio at 0x%04lx and 0x%04lx\n",
3200 card_names[pci_id->driver_data],
3201 (unsigned long) card->ac97base_mmio,
3202 (unsigned long) card->iobase_mmio);
3205 iounmap(card->ac97base_mmio);
3206 release_mem_region(card->ac97base_mmio_phys, 512);
3207 release_mem_region(card->iobase_mmio_phys, 512);
3212 iounmap(card->ac97base_mmio);
3213 release_mem_region(card->ac97base_mmio_phys, 512);
3223 /* initialize AC97 codec and register /dev/mixer */
3224 if (i810_ac97_init(card) <= 0) {
3225 free_irq(card->irq, card);
3228 pci_set_drvdata(pci_dev, card);
3232 i810_configure_clocking();
3235 /* register /dev/dsp */
3236 if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
3238 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
3239 free_irq(card->irq, card);
3240 for (i = 0; i < NR_AC97; i++)
3241 if (card->ac97_codec[i] != NULL) {
3242 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3243 ac97_release_codec(card->ac97_codec[i]);
3248 card->initializing = 0;
3252 if (card->use_mmio) {
3253 iounmap(card->ac97base_mmio);
3254 iounmap(card->iobase_mmio);
3255 release_mem_region(card->ac97base_mmio_phys, 512);
3256 release_mem_region(card->iobase_mmio_phys, 256);
3259 release_region(card->iobase, 64);
3260 release_region(card->ac97base, 256);
3261 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3262 card->channel, card->chandma);
3268 static void __devexit i810_remove(struct pci_dev *pci_dev)
3271 struct i810_card *card = pci_get_drvdata(pci_dev);
3272 /* free hardware resources */
3273 free_irq(card->irq, devs);
3274 release_region(card->iobase, 64);
3275 release_region(card->ac97base, 256);
3276 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3277 card->channel, card->chandma);
3278 if (card->use_mmio) {
3279 iounmap(card->ac97base_mmio);
3280 iounmap(card->iobase_mmio);
3281 release_mem_region(card->ac97base_mmio_phys, 512);
3282 release_mem_region(card->iobase_mmio_phys, 256);
3285 /* unregister audio devices */
3286 for (i = 0; i < NR_AC97; i++)
3287 if (card->ac97_codec[i] != NULL) {
3288 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3289 ac97_release_codec(card->ac97_codec[i]);
3290 card->ac97_codec[i] = NULL;
3292 unregister_sound_dsp(card->dev_audio);
3297 static int i810_pm_suspend(struct pci_dev *dev, u32 pm_state)
3299 struct i810_card *card = pci_get_drvdata(dev);
3300 struct i810_state *state;
3301 unsigned long flags;
3302 struct dmabuf *dmabuf;
3305 printk("i810_audio: i810_pm_suspend called\n");
3308 spin_lock_irqsave(&card->lock, flags);
3309 card->pm_suspended=1;
3310 for(i=0;i<NR_HW_CH;i++) {
3311 state = card->states[i];
3312 if(!state) continue;
3313 /* this happens only if there are open files */
3314 dmabuf = &state->dmabuf;
3315 if(dmabuf->enable & DAC_RUNNING ||
3316 (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
3317 state->pm_saved_dac_rate=dmabuf->rate;
3320 state->pm_saved_dac_rate=0;
3322 if(dmabuf->enable & ADC_RUNNING) {
3323 state->pm_saved_adc_rate=dmabuf->rate;
3326 state->pm_saved_adc_rate=0;
3329 dmabuf->swptr = dmabuf->hwptr = 0;
3330 dmabuf->count = dmabuf->total_bytes = 0;
3333 spin_unlock_irqrestore(&card->lock, flags);
3335 /* save mixer settings */
3336 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3337 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3338 if(!codec) continue;
3339 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3340 if((supported_mixer(codec,i)) &&
3341 (codec->read_mixer)) {
3342 card->pm_saved_mixer_settings[i][num_ac97]=
3343 codec->read_mixer(codec,i);
3347 pci_save_state(dev,card->pm_save_state); /* XXX do we need this? */
3348 pci_disable_device(dev); /* disable busmastering */
3349 pci_set_power_state(dev,3); /* Zzz. */
3355 static int i810_pm_resume(struct pci_dev *dev)
3358 struct i810_card *card=pci_get_drvdata(dev);
3359 pci_enable_device(dev);
3360 pci_restore_state (dev,card->pm_save_state);
3362 /* observation of a toshiba portege 3440ct suggests that the
3363 hardware has to be more or less completely reinitialized from
3364 scratch after an apm suspend. Works For Me. -dan */
3366 i810_ac97_power_up_bus(card);
3368 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3369 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3370 /* check they haven't stolen the hardware while we were
3372 if(!codec || !i810_ac97_exists(card,num_ac97)) {
3373 if(num_ac97) continue;
3376 if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
3378 if((card->ac97_features&0x0001)) {
3379 /* at probe time we found we could do variable
3380 rates, but APM suspend has made it forget
3381 its magical powers */
3382 if(!i810_ac97_enable_variable_rate(codec)) BUG();
3384 /* we lost our mixer settings, so restore them */
3385 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3386 if(supported_mixer(codec,i)){
3388 pm_saved_mixer_settings[i][num_ac97];
3389 codec->mixer_state[i]=val;
3390 codec->write_mixer(codec,i,
3392 ((val >> 8) & 0xff) );
3397 /* we need to restore the sample rate from whatever it was */
3398 for(i=0;i<NR_HW_CH;i++) {
3399 struct i810_state * state=card->states[i];
3401 if(state->pm_saved_adc_rate)
3402 i810_set_adc_rate(state,state->pm_saved_adc_rate);
3403 if(state->pm_saved_dac_rate)
3404 i810_set_dac_rate(state,state->pm_saved_dac_rate);
3409 card->pm_suspended = 0;
3411 /* any processes that were reading/writing during the suspend
3412 probably ended up here */
3413 for(i=0;i<NR_HW_CH;i++) {
3414 struct i810_state *state = card->states[i];
3415 if(state) wake_up(&state->dmabuf.wait);
3420 #endif /* CONFIG_PM */
3423 MODULE_DESCRIPTION("Intel 810 audio support");
3424 MODULE_LICENSE("GPL");
3425 MODULE_PARM(ftsodell, "i");
3426 MODULE_PARM(clocking, "i");
3427 MODULE_PARM(strict_clocking, "i");
3428 MODULE_PARM(spdif_locked, "i");
3430 #define I810_MODULE_NAME "intel810_audio"
3432 static struct pci_driver i810_pci_driver = {
3433 .name = I810_MODULE_NAME,
3434 .id_table = i810_pci_tbl,
3435 .probe = i810_probe,
3436 .remove = __devexit_p(i810_remove),
3438 .suspend = i810_pm_suspend,
3439 .resume = i810_pm_resume,
3440 #endif /* CONFIG_PM */
3444 static int __init i810_init_module (void)
3446 printk(KERN_INFO "Intel 810 + AC97 Audio, version "
3447 DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
3449 if (!pci_register_driver(&i810_pci_driver)) {
3450 pci_unregister_driver(&i810_pci_driver);
3454 printk("i810_audio: ftsodell is now a deprecated option.\n");
3456 if(spdif_locked > 0 ) {
3457 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
3458 printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
3460 printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n");
3468 static void __exit i810_cleanup_module (void)
3470 pci_unregister_driver(&i810_pci_driver);
3473 module_init(i810_init_module);
3474 module_exit(i810_cleanup_module);