sound/oss/i810_audio.c

   1 /*
   2  *      Intel i810 and friends ICH driver for Linux
   3  *      Alan Cox <alan@redhat.com>
   4  *
   5  *  Built from:
   6  *      Low level code:  Zach Brown (original nonworking i810 OSS driver)
   7  *                       Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
   8  *
   9  *      Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
  10  *      Extended by: Zach Brown <zab@redhat.com>
  11  *                      and others..
  12  *
  13  *  Hardware Provided By:
  14  *      Analog Devices (A major AC97 codec maker)
  15  *      Intel Corp  (you've probably heard of them already)
  16  *
  17  *  AC97 clues and assistance provided by
  18  *      Analog Devices
  19  *      Zach 'Fufu' Brown
  20  *      Jeff Garzik
  21  *
  22  *      This program is free software; you can redistribute it and/or modify
  23  *      it under the terms of the GNU General Public License as published by
  24  *      the Free Software Foundation; either version 2 of the License, or
  25  *      (at your option) any later version.
  26  *
  27  *      This program is distributed in the hope that it will be useful,
  28  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  *      GNU General Public License for more details.
  31  *
  32  *      You should have received a copy of the GNU General Public License
  33  *      along with this program; if not, write to the Free Software
  34  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35  *
  36  *
  37  *      Intel 810 theory of operation
  38  *
  39  *      The chipset provides three DMA channels that talk to an AC97
  40  *      CODEC (AC97 is a digital/analog mixer standard). At its simplest
  41  *      you get 48Khz audio with basic volume and mixer controls. At the
  42  *      best you get rate adaption in the codec. We set the card up so
  43  *      that we never take completion interrupts but instead keep the card
  44  *      chasing its tail around a ring buffer. This is needed for mmap
  45  *      mode audio and happens to work rather well for non-mmap modes too.
  46  *
  47  *      The board has one output channel for PCM audio (supported) and
  48  *      a stereo line in and mono microphone input. Again these are normally
  49  *      locked to 48Khz only. Right now recording is not finished.
  50  *
  51  *      There is no midi support, no synth support. Use timidity. To get
  52  *      esd working you need to use esd -r 48000 as it won't probe 48KHz
  53  *      by default. mpg123 can't handle 48Khz only audio so use xmms.
  54  *
  55  *      Fix The Sound On Dell
  56  *
  57  *      Not everyone uses 48KHz. We know of no way to detect this reliably
  58  *      and certainly not to get the right data. If your i810 audio sounds
  59  *      stupid you may need to investigate other speeds. According to Analog
  60  *      they tend to use a 14.318MHz clock which gives you a base rate of
  61  *      41194Hz.
  62  *
  63  *      This is available via the 'ftsodell=1' option.
  64  *
  65  *      If you need to force a specific rate set the clocking= option
  66  *
  67  *      This driver is cursed. (Ben LaHaise)
  68  *
  69  *  ICH 3 caveats
  70  *      Intel errata #7 for ICH3 IO. We need to disable SMI stuff
  71  *      when codec probing. [Not Yet Done]
  72  *
  73  *  ICH 4 caveats
  74  *
  75  *      The ICH4 has the feature, that the codec ID doesn't have to be
  76  *      congruent with the IO connection.
  77  *
  78  *      Therefore, from driver version 0.23 on, there is a "codec ID" <->
  79  *      "IO register base offset" mapping (card->ac97_id_map) field.
  80  *
  81  *      Juergen "George" Sawinski (jsaw)
  82  */
  83
  84 #include <linux/module.h>
  85 #include <linux/string.h>
  86 #include <linux/ctype.h>
  87 #include <linux/ioport.h>
  88 #include <linux/sched.h>
  89 #include <linux/delay.h>
  90 #include <linux/sound.h>
  91 #include <linux/slab.h>
  92 #include <linux/soundcard.h>
  93 #include <linux/pci.h>
  94 #include <linux/interrupt.h>
  95 #include <asm/io.h>
  96 #include <asm/dma.h>
  97 #include <linux/init.h>
  98 #include <linux/poll.h>
  99 #include <linux/spinlock.h>
 100 #include <linux/smp_lock.h>
 101 #include <linux/ac97_codec.h>
 102 #include <linux/bitops.h>
 103 #include <asm/uaccess.h>
 104 #include <asm/hardirq.h>
 105
 106 #define DRIVER_VERSION "1.01"
 107
 108 #define MODULOP2(a, b) ((a) & ((b) - 1))
 109 #define MASKP2(a, b) ((a) & ~((b) - 1))
 110
 111 static int ftsodell;
 112 static int strict_clocking;
 113 static unsigned int clocking;
 114 static int spdif_locked;
 115
 116 //#define DEBUG
 117 //#define DEBUG2
 118 //#define DEBUG_INTERRUPTS
 119 //#define DEBUG_MMAP
 120 //#define DEBUG_MMIO
 121
 122 #define ADC_RUNNING     1
 123 #define DAC_RUNNING     2
 124
 125 #define I810_FMT_16BIT  1
 126 #define I810_FMT_STEREO 2
 127 #define I810_FMT_MASK   3
 128
 129 #define SPDIF_ON        0x0004
 130 #define SURR_ON         0x0010
 131 #define CENTER_LFE_ON   0x0020
 132 #define VOL_MUTED       0x8000
 133
 134 /* the 810's array of pointers to data buffers */
 135
 136 struct sg_item {
 137 #define BUSADDR_MASK    0xFFFFFFFE
 138         u32 busaddr;
 139 #define CON_IOC         0x80000000 /* interrupt on completion */
 140 #define CON_BUFPAD      0x40000000 /* pad underrun with last sample, else 0 */
 141 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
 142         u32 control;
 143 };
 144
 145 /* an instance of the i810 channel */
 146 #define SG_LEN 32
 147 struct i810_channel
 148 {
 149         /* these sg guys should probably be allocated
 150            separately as nocache. Must be 8 byte aligned */
 151         struct sg_item sg[SG_LEN];      /* 32*8 */
 152         u32 offset;                     /* 4 */
 153         u32 port;                       /* 4 */
 154         u32 used;
 155         u32 num;
 156 };
 157
 158 /*
 159  * we have 3 separate dma engines.  pcm in, pcm out, and mic.
 160  * each dma engine has controlling registers.  These goofy
 161  * names are from the datasheet, but make it easy to write
 162  * code while leafing through it.
 163  *
 164  * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2,
 165  * mic in 2, s/pdif.   Of special interest is the fact that
 166  * the upper 3 DMA engines on the ICH4 *must* be accessed
 167  * via mmio access instead of pio access.
 168  */
 169
 170 #define ENUM_ENGINE(PRE,DIG)                                                                    \
 171 enum {                                                                                          \
 172         PRE##_BASE =    0x##DIG##0,             /* Base Address */                              \
 173         PRE##_BDBAR =   0x##DIG##0,             /* Buffer Descriptor list Base Address */       \
 174         PRE##_CIV =     0x##DIG##4,             /* Current Index Value */                       \
 175         PRE##_LVI =     0x##DIG##5,             /* Last Valid Index */                          \
 176         PRE##_SR =      0x##DIG##6,             /* Status Register */                           \
 177         PRE##_PICB =    0x##DIG##8,             /* Position In Current Buffer */                \
 178         PRE##_PIV =     0x##DIG##a,             /* Prefetched Index Value */                    \
 179         PRE##_CR =      0x##DIG##b              /* Control Register */                          \
 180 }
 181
 182 ENUM_ENGINE(OFF,0);     /* Offsets */
 183 ENUM_ENGINE(PI,0);      /* PCM In */
 184 ENUM_ENGINE(PO,1);      /* PCM Out */
 185 ENUM_ENGINE(MC,2);      /* Mic In */
 186
 187 enum {
 188         GLOB_CNT =      0x2c,                   /* Global Control */
 189         GLOB_STA =      0x30,                   /* Global Status */
 190         CAS      =      0x34                    /* Codec Write Semaphore Register */
 191 };
 192
 193 ENUM_ENGINE(MC2,4);     /* Mic In 2 */
 194 ENUM_ENGINE(PI2,5);     /* PCM In 2 */
 195 ENUM_ENGINE(SP,6);      /* S/PDIF */
 196
 197 enum {
 198         SDM =           0x80                    /* SDATA_IN Map Register */
 199 };
 200
 201 /* interrupts for a dma engine */
 202 #define DMA_INT_FIFO            (1<<4)  /* fifo under/over flow */
 203 #define DMA_INT_COMPLETE        (1<<3)  /* buffer read/write complete and ioc set */
 204 #define DMA_INT_LVI             (1<<2)  /* last valid done */
 205 #define DMA_INT_CELV            (1<<1)  /* last valid is current */
 206 #define DMA_INT_DCH             (1)     /* DMA Controller Halted (happens on LVI interrupts) */
 207 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
 208
 209 /* interrupts for the whole chip */
 210 #define INT_SEC         (1<<11)
 211 #define INT_PRI         (1<<10)
 212 #define INT_MC          (1<<7)
 213 #define INT_PO          (1<<6)
 214 #define INT_PI          (1<<5)
 215 #define INT_MO          (1<<2)
 216 #define INT_NI          (1<<1)
 217 #define INT_GPI         (1<<0)
 218 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
 219
 220 /* magic numbers to protect our data structures */
 221 #define I810_CARD_MAGIC         0x5072696E /* "Prin" */
 222 #define I810_STATE_MAGIC        0x63657373 /* "cess" */
 223 #define I810_DMA_MASK           0xffffffff /* DMA buffer mask for pci_alloc_consist */
 224 #define NR_HW_CH                3
 225
 226 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
 227 #define NR_AC97                 4
 228
 229 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
 230 /* stream at a minimum for this card to be happy */
 231 static const unsigned sample_size[] = { 1, 2, 2, 4 };
 232 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
 233 /* values are one less than might be expected */
 234 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
 235
 236 enum {
 237         ICH82801AA = 0,
 238         ICH82901AB,
 239         INTEL440MX,
 240         INTELICH2,
 241         INTELICH3,
 242         INTELICH4,
 243         INTELICH5,
 244         SI7012,
 245         NVIDIA_NFORCE,
 246         AMD768,
 247         AMD8111
 248 };
 249
 250 static char * card_names[] = {
 251         "Intel ICH 82801AA",
 252         "Intel ICH 82901AB",
 253         "Intel 440MX",
 254         "Intel ICH2",
 255         "Intel ICH3",
 256         "Intel ICH4",
 257         "Intel ICH5",
 258         "SiS 7012",
 259         "NVIDIA nForce Audio",
 260         "AMD 768",
 261         "AMD-8111 IOHub"
 262 };
 263
 264 /* These are capabilities (and bugs) the chipsets _can_ have */
 265 static struct {
 266         int16_t      nr_ac97;
 267 #define CAP_MMIO                 0x0001
 268 #define CAP_20BIT_AUDIO_SUPPORT  0x0002
 269         u_int16_t flags;
 270 } card_cap[] = {
 271         {  1, 0x0000 }, /* ICH82801AA */
 272         {  1, 0x0000 }, /* ICH82901AB */
 273         {  1, 0x0000 }, /* INTEL440MX */
 274         {  1, 0x0000 }, /* INTELICH2 */
 275         {  2, 0x0000 }, /* INTELICH3 */
 276         {  3, 0x0003 }, /* INTELICH4 */
 277         {  3, 0x0003 }, /* INTELICH5 */
 278         /*@FIXME to be verified*/       {  2, 0x0000 }, /* SI7012 */
 279         /*@FIXME to be verified*/       {  2, 0x0000 }, /* NVIDIA_NFORCE */
 280         /*@FIXME to be verified*/       {  2, 0x0000 }, /* AMD768 */
 281         /*@FIXME to be verified*/       {  3, 0x0001 }, /* AMD8111 */
 282 };
 283
 284 static struct pci_device_id i810_pci_tbl [] = {
 285         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_5,
 286          PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
 287         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_5,
 288          PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
 289         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
 290          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
 291         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_4,
 292          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
 293         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_5,
 294          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
 295         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_5,
 296          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
 297         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_5,
 298          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH5},
 299         {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012,
 300          PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012},
 301         {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO,
 302          PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
 303         {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO,
 304          PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
 305         {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO,
 306          PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
 307         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7445,
 308          PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768},
 309         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AUDIO,
 310          PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111},
 311         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_5,
 312          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
 313         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_18,
 314          PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
 315
 316         {0,}
 317 };
 318
 319 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
 320
 321 #ifdef CONFIG_PM
 322 #define PM_SUSPENDED(card) (card->pm_suspended)
 323 #else
 324 #define PM_SUSPENDED(card) (0)
 325 #endif
 326
 327 /* "software" or virtual channel, an instance of opened /dev/dsp */
 328 struct i810_state {
 329         unsigned int magic;
 330         struct i810_card *card; /* Card info */
 331
 332         /* single open lock mechanism, only used for recording */
 333         struct semaphore open_sem;
 334         wait_queue_head_t open_wait;
 335
 336         /* file mode */
 337         mode_t open_mode;
 338
 339         /* virtual channel number */
 340         int virt;
 341
 342 #ifdef CONFIG_PM
 343         unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
 344 #endif
 345         struct dmabuf {
 346                 /* wave sample stuff */
 347                 unsigned int rate;
 348                 unsigned char fmt, enable, trigger;
 349
 350                 /* hardware channel */
 351                 struct i810_channel *read_channel;
 352                 struct i810_channel *write_channel;
 353
 354                 /* OSS buffer management stuff */
 355                 void *rawbuf;
 356                 dma_addr_t dma_handle;
 357                 unsigned buforder;
 358                 unsigned numfrag;
 359                 unsigned fragshift;
 360
 361                 /* our buffer acts like a circular ring */
 362                 unsigned hwptr;         /* where dma last started, updated by update_ptr */
 363                 unsigned swptr;         /* where driver last clear/filled, updated by read/write */
 364                 int count;              /* bytes to be consumed or been generated by dma machine */
 365                 unsigned total_bytes;   /* total bytes dmaed by hardware */
 366
 367                 unsigned error;         /* number of over/underruns */
 368                 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
 369
 370                 /* redundant, but makes calculations easier */
 371                 /* what the hardware uses */
 372                 unsigned dmasize;
 373                 unsigned fragsize;
 374                 unsigned fragsamples;
 375
 376                 /* what we tell the user to expect */
 377                 unsigned userfrags;
 378                 unsigned userfragsize;
 379
 380                 /* OSS stuff */
 381                 unsigned mapped:1;
 382                 unsigned ready:1;
 383                 unsigned update_flag;
 384                 unsigned ossfragsize;
 385                 unsigned ossmaxfrags;
 386                 unsigned subdivision;
 387         } dmabuf;
 388 };
 389
 390
 391 struct i810_card {
 392         unsigned int magic;
 393
 394         /* We keep i810 cards in a linked list */
 395         struct i810_card *next;
 396
 397         /* The i810 has a certain amount of cross channel interaction
 398            so we use a single per card lock */
 399         spinlock_t lock;
 400
 401         /* Control AC97 access serialization */
 402         spinlock_t ac97_lock;
 403
 404         /* PCI device stuff */
 405         struct pci_dev * pci_dev;
 406         u16 pci_id;
 407         u16 pci_id_internal; /* used to access card_cap[] */
 408 #ifdef CONFIG_PM
 409         u16 pm_suspended;
 410         u32 pm_save_state[64/sizeof(u32)];
 411         int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
 412 #endif
 413         /* soundcore stuff */
 414         int dev_audio;
 415
 416         /* structures for abstraction of hardware facilities, codecs, banks and channels*/
 417         u16    ac97_id_map[NR_AC97];
 418         struct ac97_codec *ac97_codec[NR_AC97];
 419         struct i810_state *states[NR_HW_CH];
 420         struct i810_channel *channel;   /* 1:1 to states[] but diff. lifetime */
 421         dma_addr_t chandma;
 422
 423         u16 ac97_features;
 424         u16 ac97_status;
 425         u16 channels;
 426
 427         /* hardware resources */
 428         unsigned long ac97base;
 429         unsigned long iobase;
 430         u32 irq;
 431
 432         unsigned long ac97base_mmio_phys;
 433         unsigned long iobase_mmio_phys;
 434         u_int8_t *ac97base_mmio;
 435         u_int8_t *iobase_mmio;
 436
 437         int           use_mmio;
 438
 439         /* Function support */
 440         struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
 441         struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
 442         struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
 443         void (*free_pcm_channel)(struct i810_card *, int chan);
 444
 445         /* We have a *very* long init time possibly, so use this to block */
 446         /* attempts to open our devices before we are ready (stops oops'es) */
 447         int initializing;
 448 };
 449
 450 /* extract register offset from codec struct */
 451 #define IO_REG_OFF(codec) (((struct i810_card *) codec->private_data)->ac97_id_map[codec->id])
 452
 453 #define GET_CIV(port) MODULOP2(inb((port) + OFF_CIV), SG_LEN)
 454 #define GET_LVI(port) MODULOP2(inb((port) + OFF_LVI), SG_LEN)
 455
 456 /* set LVI from CIV */
 457 #define CIV_TO_LVI(port, off) \
 458         outb(MODULOP2(GET_CIV((port)) + (off), SG_LEN), (port) + OFF_LVI)
 459
 460 static struct i810_card *devs = NULL;
 461
 462 static int i810_open_mixdev(struct inode *inode, struct file *file);
 463 static int i810_ioctl_mixdev(struct inode *inode, struct file *file,
 464                              unsigned int cmd, unsigned long arg);
 465 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
 466 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
 467 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg);
 468 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data);
 469 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg);
 470 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data);
 471
 472 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
 473 {
 474         if(card->channel[1].used==1)
 475                 return NULL;
 476         card->channel[1].used=1;
 477         return &card->channel[1];
 478 }
 479
 480 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
 481 {
 482         if(card->channel[0].used==1)
 483                 return NULL;
 484         card->channel[0].used=1;
 485         return &card->channel[0];
 486 }
 487
 488 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
 489 {
 490         if(card->channel[2].used==1)
 491                 return NULL;
 492         card->channel[2].used=1;
 493         return &card->channel[2];
 494 }
 495
 496 static void i810_free_pcm_channel(struct i810_card *card, int channel)
 497 {
 498         card->channel[channel].used=0;
 499 }
 500
 501 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
 502 {
 503         unsigned long id = 0L;
 504
 505         id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
 506         id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
 507 #ifdef DEBUG
 508         printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
 509 #endif
 510         switch ( id ) {
 511                 case 0x41445361: /* AD1886 */
 512                         if (rate == 48000) {
 513                                 return 1;
 514                         }
 515                         break;
 516                 default: /* all other codecs, until we know otherwiae */
 517                         if (rate == 48000 || rate == 44100 || rate == 32000) {
 518                                 return 1;
 519                         }
 520                         break;
 521         }
 522         return (0);
 523 }
 524
 525 /* i810_set_spdif_output
 526  *
 527  *  Configure the S/PDIF output transmitter. When we turn on
 528  *  S/PDIF, we turn off the analog output. This may not be
 529  *  the right thing to do.
 530  *
 531  *  Assumptions:
 532  *     The DSP sample rate must already be set to a supported
 533  *     S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
 534  */
 535 static int i810_set_spdif_output(struct i810_state *state, int slots, int rate)
 536 {
 537         int     vol;
 538         int     aud_reg;
 539         int     r = 0;
 540         struct ac97_codec *codec = state->card->ac97_codec[0];
 541
 542         if(!codec->codec_ops->digital) {
 543                 state->card->ac97_status &= ~SPDIF_ON;
 544         } else {
 545                 if ( slots == -1 ) { /* Turn off S/PDIF */
 546                         codec->codec_ops->digital(codec, 0, 0, 0);
 547                         /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
 548                         if ( !(state->card->ac97_status & VOL_MUTED) ) {
 549                                 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
 550                                 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
 551                         }
 552                         state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
 553                         return 0;
 554                 }
 555
 556                 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
 557                 state->card->ac97_status = vol & VOL_MUTED;
 558
 559                 r = codec->codec_ops->digital(codec, slots, rate, 0);
 560
 561                 if(r)
 562                         state->card->ac97_status |= SPDIF_ON;
 563                 else
 564                         state->card->ac97_status &= ~SPDIF_ON;
 565
 566                 /* Mute the analog output */
 567                 /* Should this only mute the PCM volume??? */
 568                 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
 569         }
 570         return r;
 571 }
 572
 573 /* i810_set_dac_channels
 574  *
 575  *  Configure the codec's multi-channel DACs
 576  *
 577  *  The logic is backwards. Setting the bit to 1 turns off the DAC.
 578  *
 579  *  What about the ICH? We currently configure it using the
 580  *  SNDCTL_DSP_CHANNELS ioctl.  If we're turnning on the DAC,
 581  *  does that imply that we want the ICH set to support
 582  *  these channels?
 583  *
 584  *  TODO:
 585  *    vailidate that the codec really supports these DACs
 586  *    before turning them on.
 587  */
 588 static void i810_set_dac_channels(struct i810_state *state, int channel)
 589 {
 590         int     aud_reg;
 591         struct ac97_codec *codec = state->card->ac97_codec[0];
 592
 593         /* No codec, no setup */
 594
 595         if(codec == NULL)
 596                 return;
 597
 598         aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
 599         aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
 600         state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
 601
 602         switch ( channel ) {
 603                 case 2: /* always enabled */
 604                         break;
 605                 case 4:
 606                         aud_reg &= ~AC97_EA_PRJ;
 607                         state->card->ac97_status |= SURR_ON;
 608                         break;
 609                 case 6:
 610                         aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
 611                         state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
 612                         break;
 613                 default:
 614                         break;
 615         }
 616         i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
 617
 618 }
 619
 620
 621 /* set playback sample rate */
 622 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
 623 {
 624         struct dmabuf *dmabuf = &state->dmabuf;
 625         u32 new_rate;
 626         struct ac97_codec *codec=state->card->ac97_codec[0];
 627
 628         if(!(state->card->ac97_features&0x0001))
 629         {
 630                 dmabuf->rate = clocking;
 631 #ifdef DEBUG
 632                 printk("Asked for %d Hz, but ac97_features says we only do %dHz.  Sorry!\n",
 633                        rate,clocking);
 634 #endif
 635                 return clocking;
 636         }
 637
 638         if (rate > 48000)
 639                 rate = 48000;
 640         if (rate < 8000)
 641                 rate = 8000;
 642         dmabuf->rate = rate;
 643
 644         /*
 645          *      Adjust for misclocked crap
 646          */
 647         rate = ( rate * clocking)/48000;
 648         if(strict_clocking && rate < 8000) {
 649                 rate = 8000;
 650                 dmabuf->rate = (rate * 48000)/clocking;
 651         }
 652
 653         new_rate=ac97_set_dac_rate(codec, rate);
 654         if(new_rate != rate) {
 655                 dmabuf->rate = (new_rate * 48000)/clocking;
 656         }
 657 #ifdef DEBUG
 658         printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
 659 #endif
 660         rate = new_rate;
 661         return dmabuf->rate;
 662 }
 663
 664 /* set recording sample rate */
 665 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
 666 {
 667         struct dmabuf *dmabuf = &state->dmabuf;
 668         u32 new_rate;
 669         struct ac97_codec *codec=state->card->ac97_codec[0];
 670
 671         if(!(state->card->ac97_features&0x0001))
 672         {
 673                 dmabuf->rate = clocking;
 674                 return clocking;
 675         }
 676
 677         if (rate > 48000)
 678                 rate = 48000;
 679         if (rate < 8000)
 680                 rate = 8000;
 681         dmabuf->rate = rate;
 682
 683         /*
 684          *      Adjust for misclocked crap
 685          */
 686
 687         rate = ( rate * clocking)/48000;
 688         if(strict_clocking && rate < 8000) {
 689                 rate = 8000;
 690                 dmabuf->rate = (rate * 48000)/clocking;
 691         }
 692
 693         new_rate = ac97_set_adc_rate(codec, rate);
 694
 695         if(new_rate != rate) {
 696                 dmabuf->rate = (new_rate * 48000)/clocking;
 697                 rate = new_rate;
 698         }
 699 #ifdef DEBUG
 700         printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
 701 #endif
 702         return dmabuf->rate;
 703 }
 704
 705 /* get current playback/recording dma buffer pointer (byte offset from LBA),
 706    called with spinlock held! */
 707
 708 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
 709 {
 710         struct dmabuf *dmabuf = &state->dmabuf;
 711         unsigned int civ, offset, port, port_picb, bytes = 2;
 712
 713         if (!dmabuf->enable)
 714                 return 0;
 715
 716         if (rec)
 717                 port = state->card->iobase + dmabuf->read_channel->port;
 718         else
 719                 port = state->card->iobase + dmabuf->write_channel->port;
 720
 721         if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) {
 722                 port_picb = port + OFF_SR;
 723                 bytes = 1;
 724         } else
 725                 port_picb = port + OFF_PICB;
 726
 727         do {
 728                 civ = GET_CIV(port);
 729                 offset = inw(port_picb);
 730                 /* Must have a delay here! */
 731                 if(offset == 0)
 732                         udelay(1);
 733                 /* Reread both registers and make sure that that total
 734                  * offset from the first reading to the second is 0.
 735                  * There is an issue with SiS hardware where it will count
 736                  * picb down to 0, then update civ to the next value,
 737                  * then set the new picb to fragsize bytes.  We can catch
 738                  * it between the civ update and the picb update, making
 739                  * it look as though we are 1 fragsize ahead of where we
 740                  * are.  The next to we get the address though, it will
 741                  * be back in the right place, and we will suddenly think
 742                  * we just went forward dmasize - fragsize bytes, causing
 743                  * totally stupid *huge* dma overrun messages.  We are
 744                  * assuming that the 1us delay is more than long enough
 745                  * that we won't have to worry about the chip still being
 746                  * out of sync with reality ;-)
 747                  */
 748         } while (civ != GET_CIV(port) || offset != inw(port_picb));
 749
 750         return (((civ + 1) * dmabuf->fragsize - (bytes * offset))
 751                 % dmabuf->dmasize);
 752 }
 753
 754 /* Stop recording (lock held) */
 755 static inline void __stop_adc(struct i810_state *state)
 756 {
 757         struct dmabuf *dmabuf = &state->dmabuf;
 758         struct i810_card *card = state->card;
 759
 760         dmabuf->enable &= ~ADC_RUNNING;
 761         outb(0, card->iobase + PI_CR);
 762         // wait for the card to acknowledge shutdown
 763         while( inb(card->iobase + PI_CR) != 0 ) ;
 764         // now clear any latent interrupt bits (like the halt bit)
 765         if(card->pci_id == PCI_DEVICE_ID_SI_7012)
 766                 outb( inb(card->iobase + PI_PICB), card->iobase + PI_PICB );
 767         else
 768                 outb( inb(card->iobase + PI_SR), card->iobase + PI_SR );
 769         outl( inl(card->iobase + GLOB_STA) & INT_PI, card->iobase + GLOB_STA);
 770 }
 771
 772 static void stop_adc(struct i810_state *state)
 773 {
 774         struct i810_card *card = state->card;
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&card->lock, flags);
 778         __stop_adc(state);
 779         spin_unlock_irqrestore(&card->lock, flags);
 780 }
 781
 782 static inline void __start_adc(struct i810_state *state)
 783 {
 784         struct dmabuf *dmabuf = &state->dmabuf;
 785
 786         if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
 787             (dmabuf->trigger & PCM_ENABLE_INPUT)) {
 788                 dmabuf->enable |= ADC_RUNNING;
 789                 // Interrupt enable, LVI enable, DMA enable
 790                 outb(0x10 | 0x04 | 0x01, state->card->iobase + PI_CR);
 791         }
 792 }
 793
 794 static void start_adc(struct i810_state *state)
 795 {
 796         struct i810_card *card = state->card;
 797         unsigned long flags;
 798
 799         spin_lock_irqsave(&card->lock, flags);
 800         __start_adc(state);
 801         spin_unlock_irqrestore(&card->lock, flags);
 802 }
 803
 804 /* stop playback (lock held) */
 805 static inline void __stop_dac(struct i810_state *state)
 806 {
 807         struct dmabuf *dmabuf = &state->dmabuf;
 808         struct i810_card *card = state->card;
 809
 810         dmabuf->enable &= ~DAC_RUNNING;
 811         outb(0, card->iobase + PO_CR);
 812         // wait for the card to acknowledge shutdown
 813         while( inb(card->iobase + PO_CR) != 0 ) ;
 814         // now clear any latent interrupt bits (like the halt bit)
 815         if(card->pci_id == PCI_DEVICE_ID_SI_7012)
 816                 outb( inb(card->iobase + PO_PICB), card->iobase + PO_PICB );
 817         else
 818                 outb( inb(card->iobase + PO_SR), card->iobase + PO_SR );
 819         outl( inl(card->iobase + GLOB_STA) & INT_PO, card->iobase + GLOB_STA);
 820 }
 821
 822 static void stop_dac(struct i810_state *state)
 823 {
 824         struct i810_card *card = state->card;
 825         unsigned long flags;
 826
 827         spin_lock_irqsave(&card->lock, flags);
 828         __stop_dac(state);
 829         spin_unlock_irqrestore(&card->lock, flags);
 830 }
 831
 832 static inline void __start_dac(struct i810_state *state)
 833 {
 834         struct dmabuf *dmabuf = &state->dmabuf;
 835
 836         if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
 837             (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
 838                 dmabuf->enable |= DAC_RUNNING;
 839                 // Interrupt enable, LVI enable, DMA enable
 840                 outb(0x10 | 0x04 | 0x01, state->card->iobase + PO_CR);
 841         }
 842 }
 843 static void start_dac(struct i810_state *state)
 844 {
 845         struct i810_card *card = state->card;
 846         unsigned long flags;
 847
 848         spin_lock_irqsave(&card->lock, flags);
 849         __start_dac(state);
 850         spin_unlock_irqrestore(&card->lock, flags);
 851 }
 852
 853 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
 854 #define DMABUF_MINORDER 1
 855
 856 /* allocate DMA buffer, playback and recording buffer should be allocated separately */
 857 static int alloc_dmabuf(struct i810_state *state)
 858 {
 859         struct dmabuf *dmabuf = &state->dmabuf;
 860         void *rawbuf= NULL;
 861         int order, size;
 862         struct page *page, *pend;
 863
 864         /* If we don't have any oss frag params, then use our default ones */
 865         if(dmabuf->ossmaxfrags == 0)
 866                 dmabuf->ossmaxfrags = 4;
 867         if(dmabuf->ossfragsize == 0)
 868                 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
 869         size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
 870
 871         if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size)
 872                 return 0;
 873         /* alloc enough to satisfy the oss params */
 874         for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
 875                 if ( (PAGE_SIZE<<order) > size )
 876                         continue;
 877                 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
 878                                                    PAGE_SIZE << order,
 879                                                    &dmabuf->dma_handle)))
 880                         break;
 881         }
 882         if (!rawbuf)
 883                 return -ENOMEM;
 884
 885
 886 #ifdef DEBUG
 887         printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
 888                PAGE_SIZE << order, order, rawbuf);
 889 #endif
 890
 891         dmabuf->ready  = dmabuf->mapped = 0;
 892         dmabuf->rawbuf = rawbuf;
 893         dmabuf->buforder = order;
 894
 895         /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
 896         pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
 897         for (page = virt_to_page(rawbuf); page <= pend; page++)
 898                 SetPageReserved(page);
 899
 900         return 0;
 901 }
 902
 903 /* free DMA buffer */
 904 static void dealloc_dmabuf(struct i810_state *state)
 905 {
 906         struct dmabuf *dmabuf = &state->dmabuf;
 907         struct page *page, *pend;
 908
 909         if (dmabuf->rawbuf) {
 910                 /* undo marking the pages as reserved */
 911                 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
 912                 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
 913                         ClearPageReserved(page);
 914                 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
 915                                     dmabuf->rawbuf, dmabuf->dma_handle);
 916         }
 917         dmabuf->rawbuf = NULL;
 918         dmabuf->mapped = dmabuf->ready = 0;
 919 }
 920
 921 static int prog_dmabuf(struct i810_state *state, unsigned rec)
 922 {
 923         struct dmabuf *dmabuf = &state->dmabuf;
 924         struct i810_channel *c;
 925         struct sg_item *sg;
 926         unsigned long flags;
 927         int ret;
 928         unsigned fragint;
 929         int i;
 930
 931         spin_lock_irqsave(&state->card->lock, flags);
 932         if(dmabuf->enable & DAC_RUNNING)
 933                 __stop_dac(state);
 934         if(dmabuf->enable & ADC_RUNNING)
 935                 __stop_adc(state);
 936         dmabuf->total_bytes = 0;
 937         dmabuf->count = dmabuf->error = 0;
 938         dmabuf->swptr = dmabuf->hwptr = 0;
 939         spin_unlock_irqrestore(&state->card->lock, flags);
 940
 941         /* allocate DMA buffer, let alloc_dmabuf determine if we are already
 942          * allocated well enough or if we should replace the current buffer
 943          * (assuming one is already allocated, if it isn't, then allocate it).
 944          */
 945         if ((ret = alloc_dmabuf(state)))
 946                 return ret;
 947
 948         /* FIXME: figure out all this OSS fragment stuff */
 949         /* I did, it now does what it should according to the OSS API.  DL */
 950         /* We may not have realloced our dmabuf, but the fragment size to
 951          * fragment number ratio may have changed, so go ahead and reprogram
 952          * things
 953          */
 954         dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
 955         dmabuf->numfrag = SG_LEN;
 956         dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
 957         dmabuf->fragsamples = dmabuf->fragsize >> 1;
 958         dmabuf->fragshift = ffs(dmabuf->fragsize) - 1;
 959         dmabuf->userfragsize = dmabuf->ossfragsize;
 960         dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
 961
 962         memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
 963
 964         if(dmabuf->ossmaxfrags == 4) {
 965                 fragint = 8;
 966         } else if (dmabuf->ossmaxfrags == 8) {
 967                 fragint = 4;
 968         } else if (dmabuf->ossmaxfrags == 16) {
 969                 fragint = 2;
 970         } else {
 971                 fragint = 1;
 972         }
 973         /*
 974          *      Now set up the ring
 975          */
 976         if(dmabuf->read_channel)
 977                 c = dmabuf->read_channel;
 978         else
 979                 c = dmabuf->write_channel;
 980         while(c != NULL) {
 981                 sg=&c->sg[0];
 982                 /*
 983                  *      Load up 32 sg entries and take an interrupt at half
 984                  *      way (we might want more interrupts later..)
 985                  */
 986
 987                 for(i=0;i<dmabuf->numfrag;i++)
 988                 {
 989                         sg->busaddr=(u32)dmabuf->dma_handle+dmabuf->fragsize*i;
 990                         // the card will always be doing 16bit stereo
 991                         sg->control=dmabuf->fragsamples;
 992                         if(state->card->pci_id == PCI_DEVICE_ID_SI_7012)
 993                                 sg->control <<= 1;
 994                         sg->control|=CON_BUFPAD;
 995                         // set us up to get IOC interrupts as often as needed to
 996                         // satisfy numfrag requirements, no more
 997                         if( ((i+1) % fragint) == 0) {
 998                                 sg->control|=CON_IOC;
 999                         }
1000                         sg++;
1001                 }
1002                 spin_lock_irqsave(&state->card->lock, flags);
1003                 outb(2, state->card->iobase+c->port+OFF_CR);   /* reset DMA machine */
1004                 while( inb(state->card->iobase+c->port+OFF_CR) & 0x02 ) ;
1005                 outl((u32)state->card->chandma +
1006                     c->num*sizeof(struct i810_channel),
1007                     state->card->iobase+c->port+OFF_BDBAR);
1008                 CIV_TO_LVI(state->card->iobase+c->port, 0);
1009
1010                 spin_unlock_irqrestore(&state->card->lock, flags);
1011
1012                 if(c != dmabuf->write_channel)
1013                         c = dmabuf->write_channel;
1014                 else
1015                         c = NULL;
1016         }
1017
1018         /* set the ready flag for the dma buffer */
1019         dmabuf->ready = 1;
1020
1021 #ifdef DEBUG
1022         printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
1023                "fragsize = %d dmasize = %d\n",
1024                dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
1025                dmabuf->fragsize, dmabuf->dmasize);
1026 #endif
1027
1028         return 0;
1029 }
1030
1031 static void __i810_update_lvi(struct i810_state *state, int rec)
1032 {
1033         struct dmabuf *dmabuf = &state->dmabuf;
1034         int x, port;
1035         int trigger;
1036         int count, fragsize;
1037         void (*start)(struct i810_state *);
1038
1039         count = dmabuf->count;
1040         port = state->card->iobase;
1041         if (rec) {
1042                 port += dmabuf->read_channel->port;
1043                 trigger = PCM_ENABLE_INPUT;
1044                 start = __start_adc;
1045                 count = dmabuf->dmasize - count;
1046         } else {
1047                 port += dmabuf->write_channel->port;
1048                 trigger = PCM_ENABLE_OUTPUT;
1049                 start = __start_dac;
1050         }
1051
1052         /* Do not process partial fragments. */
1053         fragsize = dmabuf->fragsize;
1054         if (count < fragsize)
1055                 return;
1056
1057         if (!dmabuf->enable && dmabuf->ready) {
1058                 if (!(dmabuf->trigger & trigger))
1059                         return;
1060
1061                 start(state);
1062                 while (!(inb(port + OFF_CR) & ((1<<4) | (1<<2))))
1063                         ;
1064         }
1065
1066         /* MASKP2(swptr, fragsize) - 1 is the tail of our transfer */
1067         x = MODULOP2(MASKP2(dmabuf->swptr, fragsize) - 1, dmabuf->dmasize);
1068         x >>= dmabuf->fragshift;
1069         outb(x, port + OFF_LVI);
1070 }
1071
1072 static void i810_update_lvi(struct i810_state *state, int rec)
1073 {
1074         struct dmabuf *dmabuf = &state->dmabuf;
1075         unsigned long flags;
1076
1077         if(!dmabuf->ready)
1078                 return;
1079         spin_lock_irqsave(&state->card->lock, flags);
1080         __i810_update_lvi(state, rec);
1081         spin_unlock_irqrestore(&state->card->lock, flags);
1082 }
1083
1084 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
1085 static void i810_update_ptr(struct i810_state *state)
1086 {
1087         struct dmabuf *dmabuf = &state->dmabuf;
1088         unsigned hwptr;
1089         unsigned fragmask, dmamask;
1090         int diff;
1091
1092         fragmask = MASKP2(~0, dmabuf->fragsize);
1093         dmamask = MODULOP2(~0, dmabuf->dmasize);
1094
1095         /* error handling and process wake up for ADC */
1096         if (dmabuf->enable == ADC_RUNNING) {
1097                 /* update hardware pointer */
1098                 hwptr = i810_get_dma_addr(state, 1) & fragmask;
1099                 diff = (hwptr - dmabuf->hwptr) & dmamask;
1100 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1101                 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1102 #endif
1103                 dmabuf->hwptr = hwptr;
1104                 dmabuf->total_bytes += diff;
1105                 dmabuf->count += diff;
1106                 if (dmabuf->count > dmabuf->dmasize) {
1107                         /* buffer underrun or buffer overrun */
1108                         /* this is normal for the end of a read */
1109                         /* only give an error if we went past the */
1110                         /* last valid sg entry */
1111                         if (GET_CIV(state->card->iobase + PI_BASE) !=
1112                             GET_LVI(state->card->iobase + PI_BASE)) {
1113                                 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1114                                 dmabuf->error++;
1115                         }
1116                 }
1117                 if (diff)
1118                         wake_up(&dmabuf->wait);
1119         }
1120         /* error handling and process wake up for DAC */
1121         if (dmabuf->enable == DAC_RUNNING) {
1122                 /* update hardware pointer */
1123                 hwptr = i810_get_dma_addr(state, 0) & fragmask;
1124                 diff = (hwptr - dmabuf->hwptr) & dmamask;
1125 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1126                 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1127 #endif
1128                 dmabuf->hwptr = hwptr;
1129                 dmabuf->total_bytes += diff;
1130                 dmabuf->count -= diff;
1131                 if (dmabuf->count < 0) {
1132                         /* buffer underrun or buffer overrun */
1133                         /* this is normal for the end of a write */
1134                         /* only give an error if we went past the */
1135                         /* last valid sg entry */
1136                         if (GET_CIV(state->card->iobase + PO_BASE) !=
1137                             GET_LVI(state->card->iobase + PO_BASE)) {
1138                                 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1139                                 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1140                                         "count %d\n",
1141                                         GET_CIV(state->card->iobase + PO_BASE),
1142                                         GET_LVI(state->card->iobase + PO_BASE),
1143                                         dmabuf->hwptr, dmabuf->count);
1144                                 dmabuf->error++;
1145                         }
1146                 }
1147                 if (diff)
1148                         wake_up(&dmabuf->wait);
1149         }
1150 }
1151
1152 static inline int i810_get_free_write_space(struct i810_state *state)
1153 {
1154         struct dmabuf *dmabuf = &state->dmabuf;
1155         int free;
1156
1157         i810_update_ptr(state);
1158         // catch underruns during playback
1159         if (dmabuf->count < 0) {
1160                 dmabuf->count = 0;
1161                 dmabuf->swptr = dmabuf->hwptr;
1162         }
1163         free = dmabuf->dmasize - dmabuf->count;
1164         if(free < 0)
1165                 return(0);
1166         return(free);
1167 }
1168
1169 static inline int i810_get_available_read_data(struct i810_state *state)
1170 {
1171         struct dmabuf *dmabuf = &state->dmabuf;
1172         int avail;
1173
1174         i810_update_ptr(state);
1175         // catch overruns during record
1176         if (dmabuf->count > dmabuf->dmasize) {
1177                 dmabuf->count = dmabuf->dmasize;
1178                 dmabuf->swptr = dmabuf->hwptr;
1179         }
1180         avail = dmabuf->count;
1181         if(avail < 0)
1182                 return(0);
1183         return(avail);
1184 }
1185
1186 static inline void fill_partial_frag(struct dmabuf *dmabuf)
1187 {
1188         unsigned fragsize;
1189         unsigned swptr, len;
1190
1191         fragsize = dmabuf->fragsize;
1192         swptr = dmabuf->swptr;
1193         len = fragsize - MODULOP2(dmabuf->swptr, fragsize);
1194         if (len == fragsize)
1195                 return;
1196
1197         memset(dmabuf->rawbuf + swptr, '\0', len);
1198         dmabuf->swptr = MODULOP2(swptr + len, dmabuf->dmasize);
1199         dmabuf->count += len;
1200 }
1201
1202 static int drain_dac(struct i810_state *state, int signals_allowed)
1203 {
1204         DECLARE_WAITQUEUE(wait, current);
1205         struct dmabuf *dmabuf = &state->dmabuf;
1206         unsigned long flags;
1207         unsigned long tmo;
1208         int count;
1209
1210         if (!dmabuf->ready)
1211                 return 0;
1212         if(dmabuf->mapped) {
1213                 stop_dac(state);
1214                 return 0;
1215         }
1216
1217         spin_lock_irqsave(&state->card->lock, flags);
1218
1219         fill_partial_frag(dmabuf);
1220
1221         /*
1222          * This will make sure that our LVI is correct, that our
1223          * pointer is updated, and that the DAC is running.  We
1224          * have to force the setting of dmabuf->trigger to avoid
1225          * any possible deadlocks.
1226          */
1227         dmabuf->trigger = PCM_ENABLE_OUTPUT;
1228         __i810_update_lvi(state, 0);
1229
1230         spin_unlock_irqrestore(&state->card->lock, flags);
1231
1232         add_wait_queue(&dmabuf->wait, &wait);
1233         for (;;) {
1234
1235                 spin_lock_irqsave(&state->card->lock, flags);
1236                 i810_update_ptr(state);
1237                 count = dmabuf->count;
1238
1239                 /* It seems that we have to set the current state to
1240                  * TASK_INTERRUPTIBLE every time to make the process
1241                  * really go to sleep.  This also has to be *after* the
1242                  * update_ptr() call because update_ptr is likely to
1243                  * do a wake_up() which will unset this before we ever
1244                  * try to sleep, resuling in a tight loop in this code
1245                  * instead of actually sleeping and waiting for an
1246                  * interrupt to wake us up!
1247                  */
1248                 __set_current_state(signals_allowed ?
1249                                     TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1250                 spin_unlock_irqrestore(&state->card->lock, flags);
1251
1252                 if (count <= 0)
1253                         break;
1254
1255                 if (signal_pending(current) && signals_allowed) {
1256                         break;
1257                 }
1258
1259                 /*
1260                  * set the timeout to significantly longer than it *should*
1261                  * take for the DAC to drain the DMA buffer
1262                  */
1263                 tmo = (count * HZ) / (dmabuf->rate);
1264                 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){
1265                         printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1266                         count = 0;
1267                         break;
1268                 }
1269         }
1270         set_current_state(TASK_RUNNING);
1271         remove_wait_queue(&dmabuf->wait, &wait);
1272         if(count > 0 && signal_pending(current) && signals_allowed)
1273                 return -ERESTARTSYS;
1274         stop_dac(state);
1275         return 0;
1276 }
1277
1278 static void i810_channel_interrupt(struct i810_card *card)
1279 {
1280         int i, count;
1281
1282 #ifdef DEBUG_INTERRUPTS
1283         printk("CHANNEL ");
1284 #endif
1285         for(i=0;i<NR_HW_CH;i++)
1286         {
1287                 struct i810_state *state = card->states[i];
1288                 struct i810_channel *c;
1289                 struct dmabuf *dmabuf;
1290                 unsigned long port = card->iobase;
1291                 u16 status;
1292
1293                 if(!state)
1294                         continue;
1295                 if(!state->dmabuf.ready)
1296                         continue;
1297                 dmabuf = &state->dmabuf;
1298                 if(dmabuf->enable & DAC_RUNNING) {
1299                         c=dmabuf->write_channel;
1300                 } else if(dmabuf->enable & ADC_RUNNING) {
1301                         c=dmabuf->read_channel;
1302                 } else  /* This can occur going from R/W to close */
1303                         continue;
1304
1305                 port+=c->port;
1306
1307                 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1308                         status = inw(port + OFF_PICB);
1309                 else
1310                         status = inw(port + OFF_SR);
1311
1312 #ifdef DEBUG_INTERRUPTS
1313                 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1314 #endif
1315                 if(status & DMA_INT_COMPLETE)
1316                 {
1317                         /* only wake_up() waiters if this interrupt signals
1318                          * us being beyond a userfragsize of data open or
1319                          * available, and i810_update_ptr() does that for
1320                          * us
1321                          */
1322                         i810_update_ptr(state);
1323 #ifdef DEBUG_INTERRUPTS
1324                         printk("COMP %d ", dmabuf->hwptr /
1325                                         dmabuf->fragsize);
1326 #endif
1327                 }
1328                 if(status & (DMA_INT_LVI | DMA_INT_DCH))
1329                 {
1330                         /* wake_up() unconditionally on LVI and DCH */
1331                         i810_update_ptr(state);
1332                         wake_up(&dmabuf->wait);
1333 #ifdef DEBUG_INTERRUPTS
1334                         if(status & DMA_INT_LVI)
1335                                 printk("LVI ");
1336                         if(status & DMA_INT_DCH)
1337                                 printk("DCH -");
1338 #endif
1339                         count = dmabuf->count;
1340                         if(dmabuf->enable & ADC_RUNNING)
1341                                 count = dmabuf->dmasize - count;
1342                         if (count >= (int)dmabuf->fragsize) {
1343                                 outb(inb(port+OFF_CR) | 1, port+OFF_CR);
1344 #ifdef DEBUG_INTERRUPTS
1345                                 printk(" CONTINUE ");
1346 #endif
1347                         } else {
1348                                 if (dmabuf->enable & DAC_RUNNING)
1349                                         __stop_dac(state);
1350                                 if (dmabuf->enable & ADC_RUNNING)
1351                                         __stop_adc(state);
1352                                 dmabuf->enable = 0;
1353 #ifdef DEBUG_INTERRUPTS
1354                                 printk(" STOP ");
1355 #endif
1356                         }
1357                 }
1358                 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1359                         outw(status & DMA_INT_MASK, port + OFF_PICB);
1360                 else
1361                         outw(status & DMA_INT_MASK, port + OFF_SR);
1362         }
1363 #ifdef DEBUG_INTERRUPTS
1364         printk(")\n");
1365 #endif
1366 }
1367
1368 static irqreturn_t i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1369 {
1370         struct i810_card *card = (struct i810_card *)dev_id;
1371         u32 status;
1372
1373         spin_lock(&card->lock);
1374
1375         status = inl(card->iobase + GLOB_STA);
1376
1377         if(!(status & INT_MASK))
1378         {
1379                 spin_unlock(&card->lock);
1380                 return IRQ_NONE;  /* not for us */
1381         }
1382
1383         if(status & (INT_PO|INT_PI|INT_MC))
1384                 i810_channel_interrupt(card);
1385
1386         /* clear 'em */
1387         outl(status & INT_MASK, card->iobase + GLOB_STA);
1388         spin_unlock(&card->lock);
1389         return IRQ_HANDLED;
1390 }
1391
1392 /* in this loop, dmabuf.count signifies the amount of data that is
1393    waiting to be copied to the user's buffer.  It is filled by the dma
1394    machine and drained by this loop. */
1395
1396 static ssize_t i810_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1397 {
1398         struct i810_state *state = (struct i810_state *)file->private_data;
1399         struct i810_card *card=state ? state->card : 0;
1400         struct dmabuf *dmabuf = &state->dmabuf;
1401         ssize_t ret;
1402         unsigned long flags;
1403         unsigned int swptr;
1404         int cnt;
1405         int pending;
1406         DECLARE_WAITQUEUE(waita, current);
1407
1408 #ifdef DEBUG2
1409         printk("i810_audio: i810_read called, count = %d\n", count);
1410 #endif
1411
1412         if (ppos != &file->f_pos)
1413                 return -ESPIPE;
1414         if (dmabuf->mapped)
1415                 return -ENXIO;
1416         if (dmabuf->enable & DAC_RUNNING)
1417                 return -ENODEV;
1418         if (!dmabuf->read_channel) {
1419                 dmabuf->ready = 0;
1420                 dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
1421                 if (!dmabuf->read_channel) {
1422                         return -EBUSY;
1423                 }
1424         }
1425         if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1426                 return ret;
1427         if (!access_ok(VERIFY_WRITE, buffer, count))
1428                 return -EFAULT;
1429         ret = 0;
1430
1431         pending = 0;
1432
1433         add_wait_queue(&dmabuf->wait, &waita);
1434         while (count > 0) {
1435                 set_current_state(TASK_INTERRUPTIBLE);
1436                 spin_lock_irqsave(&card->lock, flags);
1437                 if (PM_SUSPENDED(card)) {
1438                         spin_unlock_irqrestore(&card->lock, flags);
1439                         schedule();
1440                         if (signal_pending(current)) {
1441                                 if (!ret) ret = -EAGAIN;
1442                                 break;
1443                         }
1444                         continue;
1445                 }
1446                 cnt = i810_get_available_read_data(state);
1447                 swptr = dmabuf->swptr;
1448                 // this is to make the copy_to_user simpler below
1449                 if(cnt > (dmabuf->dmasize - swptr))
1450                         cnt = dmabuf->dmasize - swptr;
1451                 spin_unlock_irqrestore(&card->lock, flags);
1452
1453                 if (cnt > count)
1454                         cnt = count;
1455                 if (cnt <= 0) {
1456                         unsigned long tmo;
1457                         /*
1458                          * Don't let us deadlock.  The ADC won't start if
1459                          * dmabuf->trigger isn't set.  A call to SETTRIGGER
1460                          * could have turned it off after we set it to on
1461                          * previously.
1462                          */
1463                         dmabuf->trigger = PCM_ENABLE_INPUT;
1464                         /*
1465                          * This does three things.  Updates LVI to be correct,
1466                          * makes sure the ADC is running, and updates the
1467                          * hwptr.
1468                          */
1469                         i810_update_lvi(state,1);
1470                         if (file->f_flags & O_NONBLOCK) {
1471                                 if (!ret) ret = -EAGAIN;
1472                                 goto done;
1473                         }
1474                         /* Set the timeout to how long it would take to fill
1475                          * two of our buffers.  If we haven't been woke up
1476                          * by then, then we know something is wrong.
1477                          */
1478                         tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1479                         /* There are two situations when sleep_on_timeout returns, one is when
1480                            the interrupt is serviced correctly and the process is waked up by
1481                            ISR ON TIME. Another is when timeout is expired, which means that
1482                            either interrupt is NOT serviced correctly (pending interrupt) or it
1483                            is TOO LATE for the process to be scheduled to run (scheduler latency)
1484                            which results in a (potential) buffer overrun. And worse, there is
1485                            NOTHING we can do to prevent it. */
1486                         if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1487 #ifdef DEBUG
1488                                 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1489                                        "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1490                                        dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1491                                        dmabuf->hwptr, dmabuf->swptr);
1492 #endif
1493                                 /* a buffer overrun, we delay the recovery until next time the
1494                                    while loop begin and we REALLY have space to record */
1495                         }
1496                         if (signal_pending(current)) {
1497                                 ret = ret ? ret : -ERESTARTSYS;
1498                                 goto done;
1499                         }
1500                         continue;
1501                 }
1502
1503                 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1504                         if (!ret) ret = -EFAULT;
1505                         goto done;
1506                 }
1507
1508                 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1509
1510                 spin_lock_irqsave(&card->lock, flags);
1511
1512                 if (PM_SUSPENDED(card)) {
1513                         spin_unlock_irqrestore(&card->lock, flags);
1514                         continue;
1515                 }
1516                 dmabuf->swptr = swptr;
1517                 pending = dmabuf->count -= cnt;
1518                 spin_unlock_irqrestore(&card->lock, flags);
1519
1520                 count -= cnt;
1521                 buffer += cnt;
1522                 ret += cnt;
1523         }
1524  done:
1525         pending = dmabuf->dmasize - pending;
1526         if (dmabuf->enable || pending >= dmabuf->userfragsize)
1527                 i810_update_lvi(state, 1);
1528         set_current_state(TASK_RUNNING);
1529         remove_wait_queue(&dmabuf->wait, &waita);
1530
1531         return ret;
1532 }
1533
1534 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1535    the soundcard.  it is drained by the dma machine and filled by this loop. */
1536 static ssize_t i810_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1537 {
1538         struct i810_state *state = (struct i810_state *)file->private_data;
1539         struct i810_card *card=state ? state->card : 0;
1540         struct dmabuf *dmabuf = &state->dmabuf;
1541         ssize_t ret;
1542         unsigned long flags;
1543         unsigned int swptr = 0;
1544         int pending;
1545         int cnt;
1546         DECLARE_WAITQUEUE(waita, current);
1547
1548 #ifdef DEBUG2
1549         printk("i810_audio: i810_write called, count = %d\n", count);
1550 #endif
1551
1552         if (ppos != &file->f_pos)
1553                 return -ESPIPE;
1554         if (dmabuf->mapped)
1555                 return -ENXIO;
1556         if (dmabuf->enable & ADC_RUNNING)
1557                 return -ENODEV;
1558         if (!dmabuf->write_channel) {
1559                 dmabuf->ready = 0;
1560                 dmabuf->write_channel = card->alloc_pcm_channel(card);
1561                 if(!dmabuf->write_channel)
1562                         return -EBUSY;
1563         }
1564         if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1565                 return ret;
1566         if (!access_ok(VERIFY_READ, buffer, count))
1567                 return -EFAULT;
1568         ret = 0;
1569
1570         pending = 0;
1571
1572         add_wait_queue(&dmabuf->wait, &waita);
1573         while (count > 0) {
1574                 set_current_state(TASK_INTERRUPTIBLE);
1575                 spin_lock_irqsave(&state->card->lock, flags);
1576                 if (PM_SUSPENDED(card)) {
1577                         spin_unlock_irqrestore(&card->lock, flags);
1578                         schedule();
1579                         if (signal_pending(current)) {
1580                                 if (!ret) ret = -EAGAIN;
1581                                 break;
1582                         }
1583                         continue;
1584                 }
1585
1586                 cnt = i810_get_free_write_space(state);
1587                 swptr = dmabuf->swptr;
1588                 /* Bound the maximum size to how much we can copy to the
1589                  * dma buffer before we hit the end.  If we have more to
1590                  * copy then it will get done in a second pass of this
1591                  * loop starting from the beginning of the buffer.
1592                  */
1593                 if(cnt > (dmabuf->dmasize - swptr))
1594                         cnt = dmabuf->dmasize - swptr;
1595                 spin_unlock_irqrestore(&state->card->lock, flags);
1596
1597 #ifdef DEBUG2
1598                 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1599 #endif
1600                 if (cnt > count)
1601                         cnt = count;
1602                 if (cnt <= 0) {
1603                         unsigned long tmo;
1604                         // There is data waiting to be played
1605                         /*
1606                          * Force the trigger setting since we would
1607                          * deadlock with it set any other way
1608                          */
1609                         dmabuf->trigger = PCM_ENABLE_OUTPUT;
1610                         i810_update_lvi(state,0);
1611                         if (file->f_flags & O_NONBLOCK) {
1612                                 if (!ret) ret = -EAGAIN;
1613                                 goto ret;
1614                         }
1615                         /* Not strictly correct but works */
1616                         tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1617                         /* There are two situations when sleep_on_timeout returns, one is when
1618                            the interrupt is serviced correctly and the process is waked up by
1619                            ISR ON TIME. Another is when timeout is expired, which means that
1620                            either interrupt is NOT serviced correctly (pending interrupt) or it
1621                            is TOO LATE for the process to be scheduled to run (scheduler latency)
1622                            which results in a (potential) buffer underrun. And worse, there is
1623                            NOTHING we can do to prevent it. */
1624                         if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1625 #ifdef DEBUG
1626                                 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1627                                        "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1628                                        dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1629                                        dmabuf->hwptr, dmabuf->swptr);
1630 #endif
1631                                 /* a buffer underrun, we delay the recovery until next time the
1632                                    while loop begin and we REALLY have data to play */
1633                                 //return ret;
1634                         }
1635                         if (signal_pending(current)) {
1636                                 if (!ret) ret = -ERESTARTSYS;
1637                                 goto ret;
1638                         }
1639                         continue;
1640                 }
1641                 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1642                         if (!ret) ret = -EFAULT;
1643                         goto ret;
1644                 }
1645
1646                 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1647
1648                 spin_lock_irqsave(&state->card->lock, flags);
1649                 if (PM_SUSPENDED(card)) {
1650                         spin_unlock_irqrestore(&card->lock, flags);
1651                         continue;
1652                 }
1653
1654                 dmabuf->swptr = swptr;
1655                 pending = dmabuf->count += cnt;
1656
1657                 count -= cnt;
1658                 buffer += cnt;
1659                 ret += cnt;
1660                 spin_unlock_irqrestore(&state->card->lock, flags);
1661         }
1662 ret:
1663         if (dmabuf->enable || pending >= dmabuf->userfragsize)
1664                 i810_update_lvi(state, 0);
1665         set_current_state(TASK_RUNNING);
1666         remove_wait_queue(&dmabuf->wait, &waita);
1667
1668         return ret;
1669 }
1670
1671 /* No kernel lock - we have our own spinlock */
1672 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1673 {
1674         struct i810_state *state = (struct i810_state *)file->private_data;
1675         struct dmabuf *dmabuf = &state->dmabuf;
1676         unsigned long flags;
1677         unsigned int mask = 0;
1678
1679         if(!dmabuf->ready)
1680                 return 0;
1681         poll_wait(file, &dmabuf->wait, wait);
1682         spin_lock_irqsave(&state->card->lock, flags);
1683         if (dmabuf->enable & ADC_RUNNING ||
1684             dmabuf->trigger & PCM_ENABLE_INPUT) {
1685                 if (i810_get_available_read_data(state) >=
1686                     (signed)dmabuf->userfragsize)
1687                         mask |= POLLIN | POLLRDNORM;
1688         }
1689         if (dmabuf->enable & DAC_RUNNING ||
1690             dmabuf->trigger & PCM_ENABLE_OUTPUT) {
1691                 if (i810_get_free_write_space(state) >=
1692                     (signed)dmabuf->userfragsize)
1693                         mask |= POLLOUT | POLLWRNORM;
1694         }
1695         spin_unlock_irqrestore(&state->card->lock, flags);
1696         return mask;
1697 }
1698
1699 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1700 {
1701         struct i810_state *state = (struct i810_state *)file->private_data;
1702         struct dmabuf *dmabuf = &state->dmabuf;
1703         int ret = -EINVAL;
1704         unsigned long size;
1705
1706         lock_kernel();
1707         if (vma->vm_flags & VM_WRITE) {
1708                 if (!dmabuf->write_channel &&
1709                     (dmabuf->write_channel =
1710                      state->card->alloc_pcm_channel(state->card)) == NULL) {
1711                         ret = -EBUSY;
1712                         goto out;
1713                 }
1714         }
1715         if (vma->vm_flags & VM_READ) {
1716                 if (!dmabuf->read_channel &&
1717                     (dmabuf->read_channel =
1718                      state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1719                         ret = -EBUSY;
1720                         goto out;
1721                 }
1722         }
1723         if ((ret = prog_dmabuf(state, 0)) != 0)
1724                 goto out;
1725
1726         ret = -EINVAL;
1727         if (vma->vm_pgoff != 0)
1728                 goto out;
1729         size = vma->vm_end - vma->vm_start;
1730         if (size > (PAGE_SIZE << dmabuf->buforder))
1731                 goto out;
1732         ret = -EAGAIN;
1733         if (remap_page_range(vma, vma->vm_start, virt_to_phys(dmabuf->rawbuf),
1734                              size, vma->vm_page_prot))
1735                 goto out;
1736         dmabuf->mapped = 1;
1737         dmabuf->trigger = 0;
1738         ret = 0;
1739 #ifdef DEBUG_MMAP
1740         printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1741 #endif
1742 out:
1743         unlock_kernel();
1744         return ret;
1745 }
1746
1747 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1748 {
1749         struct i810_state *state = (struct i810_state *)file->private_data;
1750         struct i810_channel *c = NULL;
1751         struct dmabuf *dmabuf = &state->dmabuf;
1752         unsigned long flags;
1753         audio_buf_info abinfo;
1754         count_info cinfo;
1755         unsigned int i_glob_cnt;
1756         int val = 0, ret;
1757         struct ac97_codec *codec = state->card->ac97_codec[0];
1758         void __user *argp = (void __user *)arg;
1759         int __user *p = argp;
1760
1761 #ifdef DEBUG
1762         printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *p : 0);
1763 #endif
1764
1765         switch (cmd)
1766         {
1767         case OSS_GETVERSION:
1768 #ifdef DEBUG
1769                 printk("OSS_GETVERSION\n");
1770 #endif
1771                 return put_user(SOUND_VERSION, p);
1772
1773         case SNDCTL_DSP_RESET:
1774 #ifdef DEBUG
1775                 printk("SNDCTL_DSP_RESET\n");
1776 #endif
1777                 spin_lock_irqsave(&state->card->lock, flags);
1778                 if (dmabuf->enable == DAC_RUNNING) {
1779                         c = dmabuf->write_channel;
1780                         __stop_dac(state);
1781                 }
1782                 if (dmabuf->enable == ADC_RUNNING) {
1783                         c = dmabuf->read_channel;
1784                         __stop_adc(state);
1785                 }
1786                 if (c != NULL) {
1787                         outb(2, state->card->iobase+c->port+OFF_CR);   /* reset DMA machine */
1788                         while ( inb(state->card->iobase+c->port+OFF_CR) & 2 )
1789                                 cpu_relax();
1790                         outl((u32)state->card->chandma +
1791                             c->num*sizeof(struct i810_channel),
1792                             state->card->iobase+c->port+OFF_BDBAR);
1793                         CIV_TO_LVI(state->card->iobase+c->port, 0);
1794                 }
1795
1796                 spin_unlock_irqrestore(&state->card->lock, flags);
1797                 synchronize_irq(state->card->pci_dev->irq);
1798                 dmabuf->ready = 0;
1799                 dmabuf->swptr = dmabuf->hwptr = 0;
1800                 dmabuf->count = dmabuf->total_bytes = 0;
1801                 return 0;
1802
1803         case SNDCTL_DSP_SYNC:
1804 #ifdef DEBUG
1805                 printk("SNDCTL_DSP_SYNC\n");
1806 #endif
1807                 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1808                         return 0;
1809                 if((val = drain_dac(state, 1)))
1810                         return val;
1811                 dmabuf->total_bytes = 0;
1812                 return 0;
1813
1814         case SNDCTL_DSP_SPEED: /* set smaple rate */
1815 #ifdef DEBUG
1816                 printk("SNDCTL_DSP_SPEED\n");
1817 #endif
1818                 if (get_user(val, p))
1819                         return -EFAULT;
1820                 if (val >= 0) {
1821                         if (file->f_mode & FMODE_WRITE) {
1822                                 if ( (state->card->ac97_status & SPDIF_ON) ) {  /* S/PDIF Enabled */
1823                                         /* AD1886 only supports 48000, need to check that */
1824                                         if ( i810_valid_spdif_rate ( codec, val ) ) {
1825                                                 /* Set DAC rate */
1826                                                 i810_set_spdif_output ( state, -1, 0 );
1827                                                 stop_dac(state);
1828                                                 dmabuf->ready = 0;
1829                                                 spin_lock_irqsave(&state->card->lock, flags);
1830                                                 i810_set_dac_rate(state, val);
1831                                                 spin_unlock_irqrestore(&state->card->lock, flags);
1832                                                 /* Set S/PDIF transmitter rate. */
1833                                                 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1834                                                 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1835                                                         val = dmabuf->rate;
1836                                                 }
1837                                         } else { /* Not a valid rate for S/PDIF, ignore it */
1838                                                 val = dmabuf->rate;
1839                                         }
1840                                 } else {
1841                                         stop_dac(state);
1842                                         dmabuf->ready = 0;
1843                                         spin_lock_irqsave(&state->card->lock, flags);
1844                                         i810_set_dac_rate(state, val);
1845                                         spin_unlock_irqrestore(&state->card->lock, flags);
1846                                 }
1847                         }
1848                         if (file->f_mode & FMODE_READ) {
1849                                 stop_adc(state);
1850                                 dmabuf->ready = 0;
1851                                 spin_lock_irqsave(&state->card->lock, flags);
1852                                 i810_set_adc_rate(state, val);
1853                                 spin_unlock_irqrestore(&state->card->lock, flags);
1854                         }
1855                 }
1856                 return put_user(dmabuf->rate, p);
1857
1858         case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
1859 #ifdef DEBUG
1860                 printk("SNDCTL_DSP_STEREO\n");
1861 #endif
1862                 if (dmabuf->enable & DAC_RUNNING) {
1863                         stop_dac(state);
1864                 }
1865                 if (dmabuf->enable & ADC_RUNNING) {
1866                         stop_adc(state);
1867                 }
1868                 return put_user(1, p);
1869
1870         case SNDCTL_DSP_GETBLKSIZE:
1871                 if (file->f_mode & FMODE_WRITE) {
1872                         if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
1873                                 return val;
1874                 }
1875                 if (file->f_mode & FMODE_READ) {
1876                         if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
1877                                 return val;
1878                 }
1879 #ifdef DEBUG
1880                 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
1881 #endif
1882                 return put_user(dmabuf->userfragsize, p);
1883
1884         case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
1885 #ifdef DEBUG
1886                 printk("SNDCTL_DSP_GETFMTS\n");
1887 #endif
1888                 return put_user(AFMT_S16_LE, p);
1889
1890         case SNDCTL_DSP_SETFMT: /* Select sample format */
1891 #ifdef DEBUG
1892                 printk("SNDCTL_DSP_SETFMT\n");
1893 #endif
1894                 return put_user(AFMT_S16_LE, p);
1895
1896         case SNDCTL_DSP_CHANNELS:
1897 #ifdef DEBUG
1898                 printk("SNDCTL_DSP_CHANNELS\n");
1899 #endif
1900                 if (get_user(val, p))
1901                         return -EFAULT;
1902
1903                 if (val > 0) {
1904                         if (dmabuf->enable & DAC_RUNNING) {
1905                                 stop_dac(state);
1906                         }
1907                         if (dmabuf->enable & ADC_RUNNING) {
1908                                 stop_adc(state);
1909                         }
1910                 } else {
1911                         return put_user(state->card->channels, p);
1912                 }
1913
1914                 /* ICH and ICH0 only support 2 channels */
1915                 if ( state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AA_5
1916                      || state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AB_5)
1917                         return put_user(2, p);
1918
1919                 /* Multi-channel support was added with ICH2. Bits in */
1920                 /* Global Status and Global Control register are now  */
1921                 /* used to indicate this.                             */
1922
1923                 i_glob_cnt = inl(state->card->iobase + GLOB_CNT);
1924
1925                 /* Current # of channels enabled */
1926                 if ( i_glob_cnt & 0x0100000 )
1927                         ret = 4;
1928                 else if ( i_glob_cnt & 0x0200000 )
1929                         ret = 6;
1930                 else
1931                         ret = 2;
1932
1933                 switch ( val ) {
1934                         case 2: /* 2 channels is always supported */
1935                                 outl(i_glob_cnt & 0xffcfffff,
1936                                      state->card->iobase + GLOB_CNT);
1937                                 /* Do we need to change mixer settings????  */
1938                                 break;
1939                         case 4: /* Supported on some chipsets, better check first */
1940                                 if ( state->card->channels >= 4 ) {
1941                                         outl((i_glob_cnt & 0xffcfffff) | 0x100000,
1942                                               state->card->iobase + GLOB_CNT);
1943                                         /* Do we need to change mixer settings??? */
1944                                 } else {
1945                                         val = ret;
1946                                 }
1947                                 break;
1948                         case 6: /* Supported on some chipsets, better check first */
1949                                 if ( state->card->channels >= 6 ) {
1950                                         outl((i_glob_cnt & 0xffcfffff) | 0x200000,
1951                                               state->card->iobase + GLOB_CNT);
1952                                         /* Do we need to change mixer settings??? */
1953                                 } else {
1954                                         val = ret;
1955                                 }
1956                                 break;
1957                         default: /* nothing else is ever supported by the chipset */
1958                                 val = ret;
1959                                 break;
1960                 }
1961
1962                 return put_user(val, p);
1963
1964         case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
1965                 /* we update the swptr to the end of the last sg segment then return */
1966 #ifdef DEBUG
1967                 printk("SNDCTL_DSP_POST\n");
1968 #endif
1969                 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
1970                         return 0;
1971                 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
1972                         val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
1973                         dmabuf->swptr += val;
1974                         dmabuf->count += val;
1975                 }
1976                 return 0;
1977
1978         case SNDCTL_DSP_SUBDIVIDE:
1979                 if (dmabuf->subdivision)
1980                         return -EINVAL;
1981                 if (get_user(val, p))
1982                         return -EFAULT;
1983                 if (val != 1 && val != 2 && val != 4)
1984                         return -EINVAL;
1985 #ifdef DEBUG
1986                 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
1987 #endif
1988                 dmabuf->subdivision = val;
1989                 dmabuf->ready = 0;
1990                 return 0;
1991
1992         case SNDCTL_DSP_SETFRAGMENT:
1993                 if (get_user(val, p))
1994                         return -EFAULT;
1995
1996                 dmabuf->ossfragsize = 1<<(val & 0xffff);
1997                 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
1998                 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags)
1999                         return -EINVAL;
2000                 /*
2001                  * Bound the frag size into our allowed range of 256 - 4096
2002                  */
2003                 if (dmabuf->ossfragsize < 256)
2004                         dmabuf->ossfragsize = 256;
2005                 else if (dmabuf->ossfragsize > 4096)
2006                         dmabuf->ossfragsize = 4096;
2007                 /*
2008                  * The numfrags could be something reasonable, or it could
2009                  * be 0xffff meaning "Give me as much as possible".  So,
2010                  * we check the numfrags * fragsize doesn't exceed our
2011                  * 64k buffer limit, nor is it less than our 8k minimum.
2012                  * If it fails either one of these checks, then adjust the
2013                  * number of fragments, not the size of them.  It's OK if
2014                  * our number of fragments doesn't equal 32 or anything
2015                  * like our hardware based number now since we are using
2016                  * a different frag count for the hardware.  Before we get
2017                  * into this though, bound the maxfrags to avoid overflow
2018                  * issues.  A reasonable bound would be 64k / 256 since our
2019                  * maximum buffer size is 64k and our minimum frag size is
2020                  * 256.  On the other end, our minimum buffer size is 8k and
2021                  * our maximum frag size is 4k, so the lower bound should
2022                  * be 2.
2023                  */
2024
2025                 if(dmabuf->ossmaxfrags > 256)
2026                         dmabuf->ossmaxfrags = 256;
2027                 else if (dmabuf->ossmaxfrags < 2)
2028                         dmabuf->ossmaxfrags = 2;
2029
2030                 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
2031                 while (val < 8192) {
2032                     val <<= 1;
2033                     dmabuf->ossmaxfrags <<= 1;
2034                 }
2035                 while (val > 65536) {
2036                     val >>= 1;
2037                     dmabuf->ossmaxfrags >>= 1;
2038                 }
2039                 dmabuf->ready = 0;
2040 #ifdef DEBUG
2041                 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
2042                         dmabuf->ossfragsize, dmabuf->ossmaxfrags);
2043 #endif
2044
2045                 return 0;
2046
2047         case SNDCTL_DSP_GETOSPACE:
2048                 if (!(file->f_mode & FMODE_WRITE))
2049                         return -EINVAL;
2050                 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2051                         return val;
2052                 spin_lock_irqsave(&state->card->lock, flags);
2053                 i810_update_ptr(state);
2054                 abinfo.fragsize = dmabuf->userfragsize;
2055                 abinfo.fragstotal = dmabuf->userfrags;
2056                 if (dmabuf->mapped)
2057                         abinfo.bytes = dmabuf->dmasize;
2058                 else
2059                         abinfo.bytes = i810_get_free_write_space(state);
2060                 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2061                 spin_unlock_irqrestore(&state->card->lock, flags);
2062 #if defined(DEBUG) || defined(DEBUG_MMAP)
2063                 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
2064                         abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2065 #endif
2066                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2067
2068         case SNDCTL_DSP_GETOPTR:
2069                 if (!(file->f_mode & FMODE_WRITE))
2070                         return -EINVAL;
2071                 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2072                         return val;
2073                 spin_lock_irqsave(&state->card->lock, flags);
2074                 val = i810_get_free_write_space(state);
2075                 cinfo.bytes = dmabuf->total_bytes;
2076                 cinfo.ptr = dmabuf->hwptr;
2077                 cinfo.blocks = val/dmabuf->userfragsize;
2078                 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
2079                         dmabuf->count += val;
2080                         dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2081                         __i810_update_lvi(state, 0);
2082                 }
2083                 spin_unlock_irqrestore(&state->card->lock, flags);
2084 #if defined(DEBUG) || defined(DEBUG_MMAP)
2085                 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
2086                         cinfo.blocks, cinfo.ptr, dmabuf->count);
2087 #endif
2088                 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2089
2090         case SNDCTL_DSP_GETISPACE:
2091                 if (!(file->f_mode & FMODE_READ))
2092                         return -EINVAL;
2093                 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
2094                         return val;
2095                 spin_lock_irqsave(&state->card->lock, flags);
2096                 abinfo.bytes = i810_get_available_read_data(state);
2097                 abinfo.fragsize = dmabuf->userfragsize;
2098                 abinfo.fragstotal = dmabuf->userfrags;
2099                 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2100                 spin_unlock_irqrestore(&state->card->lock, flags);
2101 #if defined(DEBUG) || defined(DEBUG_MMAP)
2102                 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
2103                         abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2104 #endif
2105                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2106
2107         case SNDCTL_DSP_GETIPTR:
2108                 if (!(file->f_mode & FMODE_READ))
2109                         return -EINVAL;
2110                 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2111                         return val;
2112                 spin_lock_irqsave(&state->card->lock, flags);
2113                 val = i810_get_available_read_data(state);
2114                 cinfo.bytes = dmabuf->total_bytes;
2115                 cinfo.blocks = val/dmabuf->userfragsize;
2116                 cinfo.ptr = dmabuf->hwptr;
2117                 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) {
2118                         dmabuf->count -= val;
2119                         dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2120                         __i810_update_lvi(state, 1);
2121                 }
2122                 spin_unlock_irqrestore(&state->card->lock, flags);
2123 #if defined(DEBUG) || defined(DEBUG_MMAP)
2124                 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
2125                         cinfo.blocks, cinfo.ptr, dmabuf->count);
2126 #endif
2127                 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2128
2129         case SNDCTL_DSP_NONBLOCK:
2130 #ifdef DEBUG
2131                 printk("SNDCTL_DSP_NONBLOCK\n");
2132 #endif
2133                 file->f_flags |= O_NONBLOCK;
2134                 return 0;
2135
2136         case SNDCTL_DSP_GETCAPS:
2137 #ifdef DEBUG
2138                 printk("SNDCTL_DSP_GETCAPS\n");
2139 #endif
2140             return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
2141                             p);
2142
2143         case SNDCTL_DSP_GETTRIGGER:
2144                 val = 0;
2145 #ifdef DEBUG
2146                 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
2147 #endif
2148                 return put_user(dmabuf->trigger, p);
2149
2150         case SNDCTL_DSP_SETTRIGGER:
2151                 if (get_user(val, p))
2152                         return -EFAULT;
2153 #if defined(DEBUG) || defined(DEBUG_MMAP)
2154                 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
2155 #endif
2156                 /* silently ignore invalid PCM_ENABLE_xxx bits,
2157                  * like the other drivers do
2158                  */
2159                 if (!(file->f_mode & FMODE_READ ))
2160                         val &= ~PCM_ENABLE_INPUT;
2161                 if (!(file->f_mode & FMODE_WRITE ))
2162                         val &= ~PCM_ENABLE_OUTPUT;
2163                 if((file->f_mode & FMODE_READ) && !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
2164                         stop_adc(state);
2165                 }
2166                 if((file->f_mode & FMODE_WRITE) && !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
2167                         stop_dac(state);
2168                 }
2169                 dmabuf->trigger = val;
2170                 if((val & PCM_ENABLE_OUTPUT) && !(dmabuf->enable & DAC_RUNNING)) {
2171                         if (!dmabuf->write_channel) {
2172                                 dmabuf->ready = 0;
2173                                 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
2174                                 if (!dmabuf->write_channel)
2175                                         return -EBUSY;
2176                         }
2177                         if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
2178                                 return ret;
2179                         if (dmabuf->mapped) {
2180                                 spin_lock_irqsave(&state->card->lock, flags);
2181                                 i810_update_ptr(state);
2182                                 dmabuf->count = 0;
2183                                 dmabuf->swptr = dmabuf->hwptr;
2184                                 dmabuf->count = i810_get_free_write_space(state);
2185                                 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize;
2186                                 spin_unlock_irqrestore(&state->card->lock, flags);
2187                         }
2188                         i810_update_lvi(state, 0);
2189                         start_dac(state);
2190                 }
2191                 if((val & PCM_ENABLE_INPUT) && !(dmabuf->enable & ADC_RUNNING)) {
2192                         if (!dmabuf->read_channel) {
2193                                 dmabuf->ready = 0;
2194                                 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
2195                                 if (!dmabuf->read_channel)
2196                                         return -EBUSY;
2197                         }
2198                         if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
2199                                 return ret;
2200                         if (dmabuf->mapped) {
2201                                 spin_lock_irqsave(&state->card->lock, flags);
2202                                 i810_update_ptr(state);
2203                                 dmabuf->swptr = dmabuf->hwptr;
2204                                 dmabuf->count = 0;
2205                                 spin_unlock_irqrestore(&state->card->lock, flags);
2206                         }
2207                         i810_update_lvi(state, 1);
2208                         start_adc(state);
2209                 }
2210                 return 0;
2211
2212         case SNDCTL_DSP_SETDUPLEX:
2213 #ifdef DEBUG
2214                 printk("SNDCTL_DSP_SETDUPLEX\n");
2215 #endif
2216                 return -EINVAL;
2217
2218         case SNDCTL_DSP_GETODELAY:
2219                 if (!(file->f_mode & FMODE_WRITE))
2220                         return -EINVAL;
2221                 spin_lock_irqsave(&state->card->lock, flags);
2222                 i810_update_ptr(state);
2223                 val = dmabuf->count;
2224                 spin_unlock_irqrestore(&state->card->lock, flags);
2225 #ifdef DEBUG
2226                 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
2227 #endif
2228                 return put_user(val, p);
2229
2230         case SOUND_PCM_READ_RATE:
2231 #ifdef DEBUG
2232                 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
2233 #endif
2234                 return put_user(dmabuf->rate, p);
2235
2236         case SOUND_PCM_READ_CHANNELS:
2237 #ifdef DEBUG
2238                 printk("SOUND_PCM_READ_CHANNELS\n");
2239 #endif
2240                 return put_user(2, p);
2241
2242         case SOUND_PCM_READ_BITS:
2243 #ifdef DEBUG
2244                 printk("SOUND_PCM_READ_BITS\n");
2245 #endif
2246                 return put_user(AFMT_S16_LE, p);
2247
2248         case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
2249 #ifdef DEBUG
2250                 printk("SNDCTL_DSP_SETSPDIF\n");
2251 #endif
2252                 if (get_user(val, p))
2253                         return -EFAULT;
2254
2255                 /* Check to make sure the codec supports S/PDIF transmitter */
2256
2257                 if((state->card->ac97_features & 4)) {
2258                         /* mask out the transmitter speed bits so the user can't set them */
2259                         val &= ~0x3000;
2260
2261                         /* Add the current transmitter speed bits to the passed value */
2262                         ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2263                         val |= (ret & 0x3000);
2264
2265                         i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
2266                         if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
2267                                 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
2268                                 return -EFAULT;
2269                         }
2270                 }
2271 #ifdef DEBUG
2272                 else
2273                         printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2274 #endif
2275                 return put_user(val, p);
2276
2277         case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2278 #ifdef DEBUG
2279                 printk("SNDCTL_DSP_GETSPDIF\n");
2280 #endif
2281                 if (get_user(val, p))
2282                         return -EFAULT;
2283
2284                 /* Check to make sure the codec supports S/PDIF transmitter */
2285
2286                 if(!(state->card->ac97_features & 4)) {
2287 #ifdef DEBUG
2288                         printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2289 #endif
2290                         val = 0;
2291                 } else {
2292                         val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2293                 }
2294                 //return put_user((val & 0xcfff), p);
2295                 return put_user(val, p);
2296
2297         case SNDCTL_DSP_GETCHANNELMASK:
2298 #ifdef DEBUG
2299                 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2300 #endif
2301                 if (get_user(val, p))
2302                         return -EFAULT;
2303
2304                 /* Based on AC'97 DAC support, not ICH hardware */
2305                 val = DSP_BIND_FRONT;
2306                 if ( state->card->ac97_features & 0x0004 )
2307                         val |= DSP_BIND_SPDIF;
2308
2309                 if ( state->card->ac97_features & 0x0080 )
2310                         val |= DSP_BIND_SURR;
2311                 if ( state->card->ac97_features & 0x0140 )
2312                         val |= DSP_BIND_CENTER_LFE;
2313
2314                 return put_user(val, p);
2315
2316         case SNDCTL_DSP_BIND_CHANNEL:
2317 #ifdef DEBUG
2318                 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2319 #endif
2320                 if (get_user(val, p))
2321                         return -EFAULT;
2322                 if ( val == DSP_BIND_QUERY ) {
2323                         val = DSP_BIND_FRONT; /* Always report this as being enabled */
2324                         if ( state->card->ac97_status & SPDIF_ON )
2325                                 val |= DSP_BIND_SPDIF;
2326                         else {
2327                                 if ( state->card->ac97_status & SURR_ON )
2328                                         val |= DSP_BIND_SURR;
2329                                 if ( state->card->ac97_status & CENTER_LFE_ON )
2330                                         val |= DSP_BIND_CENTER_LFE;
2331                         }
2332                 } else {  /* Not a query, set it */
2333                         if (!(file->f_mode & FMODE_WRITE))
2334                                 return -EINVAL;
2335                         if ( dmabuf->enable == DAC_RUNNING ) {
2336                                 stop_dac(state);
2337                         }
2338                         if ( val & DSP_BIND_SPDIF ) {  /* Turn on SPDIF */
2339                                 /*  Ok, this should probably define what slots
2340                                  *  to use. For now, we'll only set it to the
2341                                  *  defaults:
2342                                  *
2343                                  *   non multichannel codec maps to slots 3&4
2344                                  *   2 channel codec maps to slots 7&8
2345                                  *   4 channel codec maps to slots 6&9
2346                                  *   6 channel codec maps to slots 10&11
2347                                  *
2348                                  *  there should be some way for the app to
2349                                  *  select the slot assignment.
2350                                  */
2351
2352                                 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2353                                 if ( !(state->card->ac97_status & SPDIF_ON) )
2354                                         val &= ~DSP_BIND_SPDIF;
2355                         } else {
2356                                 int mask;
2357                                 int channels;
2358
2359                                 /* Turn off S/PDIF if it was on */
2360                                 if ( state->card->ac97_status & SPDIF_ON )
2361                                         i810_set_spdif_output ( state, -1, 0 );
2362
2363                                 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2364                                 switch (mask) {
2365                                         case DSP_BIND_FRONT:
2366                                                 channels = 2;
2367                                                 break;
2368                                         case DSP_BIND_FRONT|DSP_BIND_SURR:
2369                                                 channels = 4;
2370                                                 break;
2371                                         case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2372                                                 channels = 6;
2373                                                 break;
2374                                         default:
2375                                                 val = DSP_BIND_FRONT;
2376                                                 channels = 2;
2377                                                 break;
2378                                 }
2379                                 i810_set_dac_channels ( state, channels );
2380
2381                                 /* check that they really got turned on */
2382                                 if (!(state->card->ac97_status & SURR_ON))
2383                                         val &= ~DSP_BIND_SURR;
2384                                 if (!(state->card->ac97_status & CENTER_LFE_ON))
2385                                         val &= ~DSP_BIND_CENTER_LFE;
2386                         }
2387                 }
2388                 return put_user(val, p);
2389
2390         case SNDCTL_DSP_MAPINBUF:
2391         case SNDCTL_DSP_MAPOUTBUF:
2392         case SNDCTL_DSP_SETSYNCRO:
2393         case SOUND_PCM_WRITE_FILTER:
2394         case SOUND_PCM_READ_FILTER:
2395 #ifdef DEBUG
2396                 printk("SNDCTL_* -EINVAL\n");
2397 #endif
2398                 return -EINVAL;
2399         }
2400         return -EINVAL;
2401 }
2402
2403 static int i810_open(struct inode *inode, struct file *file)
2404 {
2405         int i = 0;
2406         struct i810_card *card = devs;
2407         struct i810_state *state = NULL;
2408         struct dmabuf *dmabuf = NULL;
2409
2410         /* find an avaiable virtual channel (instance of /dev/dsp) */
2411         while (card != NULL) {
2412                 /*
2413                  * If we are initializing and then fail, card could go
2414                  * away unuexpectedly while we are in the for() loop.
2415                  * So, check for card on each iteration before we check
2416                  * for card->initializing to avoid a possible oops.
2417                  * This usually only matters for times when the driver is
2418                  * autoloaded by kmod.
2419                  */
2420                 for (i = 0; i < 50 && card && card->initializing; i++) {
2421                         set_current_state(TASK_UNINTERRUPTIBLE);
2422                         schedule_timeout(HZ/20);
2423                 }
2424                 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) {
2425                         if (card->states[i] == NULL) {
2426                                 state = card->states[i] = (struct i810_state *)
2427                                         kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2428                                 if (state == NULL)
2429                                         return -ENOMEM;
2430                                 memset(state, 0, sizeof(struct i810_state));
2431                                 dmabuf = &state->dmabuf;
2432                                 goto found_virt;
2433                         }
2434                 }
2435                 card = card->next;
2436         }
2437         /* no more virtual channel avaiable */
2438         if (!state)
2439                 return -ENODEV;
2440
2441 found_virt:
2442         /* initialize the virtual channel */
2443         state->virt = i;
2444         state->card = card;
2445         state->magic = I810_STATE_MAGIC;
2446         init_waitqueue_head(&dmabuf->wait);
2447         init_MUTEX(&state->open_sem);
2448         file->private_data = state;
2449         dmabuf->trigger = 0;
2450
2451         /* allocate hardware channels */
2452         if(file->f_mode & FMODE_READ) {
2453                 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2454                         kfree (card->states[i]);
2455                         card->states[i] = NULL;
2456                         return -EBUSY;
2457                 }
2458                 dmabuf->trigger |= PCM_ENABLE_INPUT;
2459                 i810_set_adc_rate(state, 8000);
2460         }
2461         if(file->f_mode & FMODE_WRITE) {
2462                 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2463                         /* make sure we free the record channel allocated above */
2464                         if(file->f_mode & FMODE_READ)
2465                                 card->free_pcm_channel(card,dmabuf->read_channel->num);
2466                         kfree (card->states[i]);
2467                         card->states[i] = NULL;
2468                         return -EBUSY;
2469                 }
2470                 /* Initialize to 8kHz?  What if we don't support 8kHz? */
2471                 /*  Let's change this to check for S/PDIF stuff */
2472
2473                 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2474                 if ( spdif_locked ) {
2475                         i810_set_dac_rate(state, spdif_locked);
2476                         i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2477                 } else {
2478                         i810_set_dac_rate(state, 8000);
2479                         /* Put the ACLink in 2 channel mode by default */
2480                         i = inl(card->iobase + GLOB_CNT);
2481                         outl(i & 0xffcfffff, card->iobase + GLOB_CNT);
2482                 }
2483         }
2484
2485         /* set default sample format. According to OSS Programmer's Guide  /dev/dsp
2486            should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2487            /dev/dspW will accept 16-bits sample, but we don't support those so we
2488            set it immediately to stereo and 16bit, which is all we do support */
2489         dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2490         dmabuf->ossfragsize = 0;
2491         dmabuf->ossmaxfrags  = 0;
2492         dmabuf->subdivision  = 0;
2493
2494         state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2495
2496         return 0;
2497 }
2498
2499 static int i810_release(struct inode *inode, struct file *file)
2500 {
2501         struct i810_state *state = (struct i810_state *)file->private_data;
2502         struct i810_card *card = state->card;
2503         struct dmabuf *dmabuf = &state->dmabuf;
2504         unsigned long flags;
2505
2506         lock_kernel();
2507
2508         /* stop DMA state machine and free DMA buffers/channels */
2509         if(dmabuf->trigger & PCM_ENABLE_OUTPUT) {
2510                 drain_dac(state, 0);
2511         }
2512         if(dmabuf->trigger & PCM_ENABLE_INPUT) {
2513                 stop_adc(state);
2514         }
2515         spin_lock_irqsave(&card->lock, flags);
2516         dealloc_dmabuf(state);
2517         if (file->f_mode & FMODE_WRITE) {
2518                 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2519         }
2520         if (file->f_mode & FMODE_READ) {
2521                 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2522         }
2523
2524         state->card->states[state->virt] = NULL;
2525         kfree(state);
2526         spin_unlock_irqrestore(&card->lock, flags);
2527         unlock_kernel();
2528
2529         return 0;
2530 }
2531
2532 static /*const*/ struct file_operations i810_audio_fops = {
2533         .owner          = THIS_MODULE,
2534         .llseek         = no_llseek,
2535         .read           = i810_read,
2536         .write          = i810_write,
2537         .poll           = i810_poll,
2538         .ioctl          = i810_ioctl,
2539         .mmap           = i810_mmap,
2540         .open           = i810_open,
2541         .release        = i810_release,
2542 };
2543
2544 /* Write AC97 codec registers */
2545
2546 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg)
2547 {
2548         struct i810_card *card = dev->private_data;
2549         int count = 100;
2550         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2551
2552         while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2553                 udelay(1);
2554
2555 #ifdef DEBUG_MMIO
2556         {
2557                 u16 ans = readw(card->ac97base_mmio + reg_set);
2558                 printk(KERN_DEBUG "i810_audio: ac97_get_mmio(%d) -> 0x%04X\n", ((int) reg_set) & 0xffff, (u32) ans);
2559                 return ans;
2560         }
2561 #else
2562         return readw(card->ac97base_mmio + reg_set);
2563 #endif
2564 }
2565
2566 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg)
2567 {
2568         struct i810_card *card = dev->private_data;
2569         int count = 100;
2570         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2571
2572         while(count-- && (inb(card->iobase + CAS) & 1))
2573                 udelay(1);
2574
2575         return inw(card->ac97base + reg_set);
2576 }
2577
2578 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data)
2579 {
2580         struct i810_card *card = dev->private_data;
2581         int count = 100;
2582         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2583
2584         while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2585                 udelay(1);
2586
2587         writew(data, card->ac97base_mmio + reg_set);
2588
2589 #ifdef DEBUG_MMIO
2590         printk(KERN_DEBUG "i810_audio: ac97_set_mmio(0x%04X, %d)\n", (u32) data, ((int) reg_set) & 0xffff);
2591 #endif
2592 }
2593
2594 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data)
2595 {
2596         struct i810_card *card = dev->private_data;
2597         int count = 100;
2598         u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2599
2600         while(count-- && (inb(card->iobase + CAS) & 1))
2601                 udelay(1);
2602
2603         outw(data, card->ac97base + reg_set);
2604 }
2605
2606 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2607 {
2608         struct i810_card *card = dev->private_data;
2609         u16 ret;
2610
2611         spin_lock(&card->ac97_lock);
2612         if (card->use_mmio) {
2613                 ret = i810_ac97_get_mmio(dev, reg);
2614         }
2615         else {
2616                 ret = i810_ac97_get_io(dev, reg);
2617         }
2618         spin_unlock(&card->ac97_lock);
2619
2620         return ret;
2621 }
2622
2623 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2624 {
2625         struct i810_card *card = dev->private_data;
2626
2627         spin_lock(&card->ac97_lock);
2628         if (card->use_mmio) {
2629                 i810_ac97_set_mmio(dev, reg, data);
2630         }
2631         else {
2632                 i810_ac97_set_io(dev, reg, data);
2633         }
2634         spin_unlock(&card->ac97_lock);
2635 }
2636
2637
2638 /* OSS /dev/mixer file operation methods */
2639
2640 static int i810_open_mixdev(struct inode *inode, struct file *file)
2641 {
2642         int i;
2643         int minor = iminor(inode);
2644         struct i810_card *card = devs;
2645
2646         for (card = devs; card != NULL; card = card->next) {
2647                 /*
2648                  * If we are initializing and then fail, card could go
2649                  * away unuexpectedly while we are in the for() loop.
2650                  * So, check for card on each iteration before we check
2651                  * for card->initializing to avoid a possible oops.
2652                  * This usually only matters for times when the driver is
2653                  * autoloaded by kmod.
2654                  */
2655                 for (i = 0; i < 50 && card && card->initializing; i++) {
2656                         set_current_state(TASK_UNINTERRUPTIBLE);
2657                         schedule_timeout(HZ/20);
2658                 }
2659                 for (i = 0; i < NR_AC97 && card && !card->initializing; i++)
2660                         if (card->ac97_codec[i] != NULL &&
2661                             card->ac97_codec[i]->dev_mixer == minor) {
2662                                 file->private_data = card->ac97_codec[i];
2663                                 return 0;
2664                         }
2665         }
2666         return -ENODEV;
2667 }
2668
2669 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2670                                 unsigned long arg)
2671 {
2672         struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2673
2674         return codec->mixer_ioctl(codec, cmd, arg);
2675 }
2676
2677 static /*const*/ struct file_operations i810_mixer_fops = {
2678         .owner          = THIS_MODULE,
2679         .llseek         = no_llseek,
2680         .ioctl          = i810_ioctl_mixdev,
2681         .open           = i810_open_mixdev,
2682 };
2683
2684 /* AC97 codec initialisation.  These small functions exist so we don't
2685    duplicate code between module init and apm resume */
2686
2687 static inline int i810_ac97_exists(struct i810_card *card, int ac97_number)
2688 {
2689         u32 reg = inl(card->iobase + GLOB_STA);
2690         switch (ac97_number) {
2691         case 0:
2692                 return reg & (1<<8);
2693         case 1:
2694                 return reg & (1<<9);
2695         case 2:
2696                 return reg & (1<<28);
2697         }
2698         return 0;
2699 }
2700
2701 static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
2702 {
2703         i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2704         i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2705                       i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2706
2707         return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
2708 }
2709
2710
2711 static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
2712 {
2713         /* Returns 0 on failure */
2714         int i;
2715
2716         if (ac97_probe_codec(codec) == 0) return 0;
2717
2718         /* power it all up */
2719         i810_ac97_set(codec, AC97_POWER_CONTROL,
2720                       i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2721
2722         /* wait for analog ready */
2723         for (i=100; i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); i--)
2724         {
2725                 set_current_state(TASK_UNINTERRUPTIBLE);
2726                 schedule_timeout(HZ/20);
2727         }
2728         return i;
2729 }
2730
2731 static int is_new_ich(u16 pci_id)
2732 {
2733         switch (pci_id) {
2734         case PCI_DEVICE_ID_INTEL_82801DB_5:
2735         case PCI_DEVICE_ID_INTEL_82801EB_5:
2736         case PCI_DEVICE_ID_INTEL_ESB_5:
2737         case PCI_DEVICE_ID_INTEL_ICH6_18:
2738                 return 1;
2739         default:
2740                 break;
2741         }
2742
2743         return 0;
2744 }
2745
2746 static inline int ich_use_mmio(struct i810_card *card)
2747 {
2748         return is_new_ich(card->pci_id) && card->use_mmio;
2749 }
2750
2751 /**
2752  *      i810_ac97_power_up_bus  -       bring up AC97 link
2753  *      @card : ICH audio device to power up
2754  *
2755  *      Bring up the ACLink AC97 codec bus
2756  */
2757
2758 static int i810_ac97_power_up_bus(struct i810_card *card)
2759 {
2760         u32 reg = inl(card->iobase + GLOB_CNT);
2761         int i;
2762         int primary_codec_id = 0;
2763
2764         if((reg&2)==0)  /* Cold required */
2765                 reg|=2;
2766         else
2767                 reg|=4; /* Warm */
2768
2769         reg&=~8;        /* ACLink on */
2770
2771         /* At this point we deassert AC_RESET # */
2772         outl(reg , card->iobase + GLOB_CNT);
2773
2774         /* We must now allow time for the Codec initialisation.
2775            600mS is the specified time */
2776
2777         for(i=0;i<10;i++)
2778         {
2779                 if((inl(card->iobase+GLOB_CNT)&4)==0)
2780                         break;
2781
2782                 set_current_state(TASK_UNINTERRUPTIBLE);
2783                 schedule_timeout(HZ/20);
2784         }
2785         if(i==10)
2786         {
2787                 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2788                 return 0;
2789         }
2790
2791         set_current_state(TASK_UNINTERRUPTIBLE);
2792         schedule_timeout(HZ/2);
2793
2794         /*
2795          *      See if the primary codec comes ready. This must happen
2796          *      before we start doing DMA stuff
2797          */
2798         /* see i810_ac97_init for the next 7 lines (jsaw) */
2799         inw(card->ac97base);
2800         if (ich_use_mmio(card)) {
2801                 primary_codec_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2802                 printk(KERN_INFO "i810_audio: Primary codec has ID %d\n",
2803                        primary_codec_id);
2804         }
2805
2806         if(! i810_ac97_exists(card, primary_codec_id))
2807         {
2808                 printk(KERN_INFO "i810_audio: Codec not ready.. wait.. ");
2809                 set_current_state(TASK_UNINTERRUPTIBLE);
2810                 schedule_timeout(HZ);   /* actually 600mS by the spec */
2811
2812                 if(i810_ac97_exists(card, primary_codec_id))
2813                         printk("OK\n");
2814                 else
2815                         printk("no response.\n");
2816         }
2817         inw(card->ac97base);
2818         return 1;
2819 }
2820
2821 static int __devinit i810_ac97_init(struct i810_card *card)
2822 {
2823         int num_ac97 = 0;
2824         int ac97_id;
2825         int total_channels = 0;
2826         int nr_ac97_max = card_cap[card->pci_id_internal].nr_ac97;
2827         struct ac97_codec *codec;
2828         u16 eid;
2829         u32 reg;
2830
2831         if(!i810_ac97_power_up_bus(card)) return 0;
2832
2833         /* Number of channels supported */
2834         /* What about the codec?  Just because the ICH supports */
2835         /* multiple channels doesn't mean the codec does.       */
2836         /* we'll have to modify this in the codec section below */
2837         /* to reflect what the codec has.                       */
2838         /* ICH and ICH0 only support 2 channels so don't bother */
2839         /* to check....                                         */
2840
2841         card->channels = 2;
2842         reg = inl(card->iobase + GLOB_STA);
2843         if ( reg & 0x0200000 )
2844                 card->channels = 6;
2845         else if ( reg & 0x0100000 )
2846                 card->channels = 4;
2847         printk(KERN_INFO "i810_audio: Audio Controller supports %d channels.\n", card->channels);
2848         printk(KERN_INFO "i810_audio: Defaulting to base 2 channel mode.\n");
2849         reg = inl(card->iobase + GLOB_CNT);
2850         outl(reg & 0xffcfffff, card->iobase + GLOB_CNT);
2851
2852         for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++)
2853                 card->ac97_codec[num_ac97] = NULL;
2854
2855         /*@FIXME I don't know, if I'm playing to safe here... (jsaw) */
2856         if ((nr_ac97_max > 2) && !card->use_mmio) nr_ac97_max = 2;
2857
2858         for (num_ac97 = 0; num_ac97 < nr_ac97_max; num_ac97++) {
2859                 /* codec reset */
2860                 printk(KERN_INFO "i810_audio: Resetting connection %d\n", num_ac97);
2861                 if (card->use_mmio) readw(card->ac97base_mmio + 0x80*num_ac97);
2862                 else inw(card->ac97base + 0x80*num_ac97);
2863
2864                 /* If we have the SDATA_IN Map Register, as on ICH4, we
2865                    do not loop thru all possible codec IDs but thru all
2866                    possible IO channels. Bit 0:1 of SDM then holds the
2867                    last codec ID spoken to.
2868                 */
2869                 if (ich_use_mmio(card)) {
2870                         ac97_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2871                         printk(KERN_INFO "i810_audio: Connection %d with codec id %d\n",
2872                                num_ac97, ac97_id);
2873                 }
2874                 else {
2875                         ac97_id = num_ac97;
2876                 }
2877
2878                 /* The ICH programmer's reference says you should   */
2879                 /* check the ready status before probing. So we chk */
2880                 /*   What do we do if it's not ready?  Wait and try */
2881                 /*   again, or abort?                               */
2882                 if (!i810_ac97_exists(card, ac97_id)) {
2883                         if(num_ac97 == 0)
2884                                 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
2885                 }
2886
2887                 if ((codec = ac97_alloc_codec()) == NULL)
2888                         return -ENOMEM;
2889
2890                 /* initialize some basic codec information, other fields will be filled
2891                    in ac97_probe_codec */
2892                 codec->private_data = card;
2893                 codec->id = ac97_id;
2894                 card->ac97_id_map[ac97_id] = num_ac97 * 0x80;
2895
2896                 if (card->use_mmio) {
2897                         codec->codec_read = i810_ac97_get_mmio;
2898                         codec->codec_write = i810_ac97_set_mmio;
2899                 }
2900                 else {
2901                         codec->codec_read = i810_ac97_get_io;
2902                         codec->codec_write = i810_ac97_set_io;
2903                 }
2904
2905                 if(!i810_ac97_probe_and_powerup(card,codec)) {
2906                         printk(KERN_ERR "i810_audio: timed out waiting for codec %d analog ready.\n", ac97_id);
2907                         ac97_release_codec(codec);
2908                         break;  /* it didn't work */
2909                 }
2910                 /* Store state information about S/PDIF transmitter */
2911                 card->ac97_status = 0;
2912
2913                 /* Don't attempt to get eid until powerup is complete */
2914                 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2915
2916                 if(eid==0xFFFF)
2917                 {
2918                         printk(KERN_WARNING "i810_audio: no codec attached ?\n");
2919                         ac97_release_codec(codec);
2920                         break;
2921                 }
2922
2923                 /* Check for an AC97 1.0 soft modem (ID1) */
2924
2925                 if(codec->modem)
2926                 {
2927                         printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", ac97_id);
2928                         ac97_release_codec(codec);
2929                         continue;
2930                 }
2931
2932                 card->ac97_features = eid;
2933
2934                 /* Now check the codec for useful features to make up for
2935                    the dumbness of the 810 hardware engine */
2936
2937                 if(!(eid&0x0001))
2938                         printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
2939                 else
2940                 {
2941                         if(!i810_ac97_enable_variable_rate(codec)) {
2942                                 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
2943                                 card->ac97_features&=~1;
2944                         }
2945                 }
2946
2947                 /* Turn on the amplifier */
2948
2949                 codec->codec_write(codec, AC97_POWER_CONTROL,
2950                          codec->codec_read(codec, AC97_POWER_CONTROL) & ~0x8000);
2951
2952                 /* Determine how many channels the codec(s) support   */
2953                 /*   - The primary codec always supports 2            */
2954                 /*   - If the codec supports AMAP, surround DACs will */
2955                 /*     automaticlly get assigned to slots.            */
2956                 /*     * Check for surround DACs and increment if     */
2957                 /*       found.                                       */
2958                 /*   - Else check if the codec is revision 2.2        */
2959                 /*     * If surround DACs exist, assign them to slots */
2960                 /*       and increment channel count.                 */
2961
2962                 /* All of this only applies to ICH2 and above. ICH    */
2963                 /* and ICH0 only support 2 channels.  ICH2 will only  */
2964                 /* support multiple codecs in a "split audio" config. */
2965                 /* as described above.                                */
2966
2967                 /* TODO: Remove all the debugging messages!           */
2968
2969                 if((eid & 0xc000) == 0) /* primary codec */
2970                         total_channels += 2;
2971
2972                 if(eid & 0x200) { /* GOOD, AMAP support */
2973                         if (eid & 0x0080) /* L/R Surround channels */
2974                                 total_channels += 2;
2975                         if (eid & 0x0140) /* LFE and Center channels */
2976                                 total_channels += 2;
2977                         printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", ac97_id, total_channels);
2978                 } else if (eid & 0x0400) {  /* this only works on 2.2 compliant codecs */
2979                         eid &= 0xffcf;
2980                         if((eid & 0xc000) != 0) {
2981                                 switch ( total_channels ) {
2982                                         case 2:
2983                                                 /* Set dsa1, dsa0 to 01 */
2984                                                 eid |= 0x0010;
2985                                                 break;
2986                                         case 4:
2987                                                 /* Set dsa1, dsa0 to 10 */
2988                                                 eid |= 0x0020;
2989                                                 break;
2990                                         case 6:
2991                                                 /* Set dsa1, dsa0 to 11 */
2992                                                 eid |= 0x0030;
2993                                                 break;
2994                                 }
2995                                 total_channels += 2;
2996                         }
2997                         i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
2998                         eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2999                         printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", ac97_id, eid);
3000                         if (eid & 0x0080) /* L/R Surround channels */
3001                                 total_channels += 2;
3002                         if (eid & 0x0140) /* LFE and Center channels */
3003                                 total_channels += 2;
3004                         printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", ac97_id, total_channels);
3005                 } else {
3006                         printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", ac97_id, total_channels);
3007                 }
3008
3009                 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
3010                         printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
3011                         ac97_release_codec(codec);
3012                         break;
3013                 }
3014
3015                 card->ac97_codec[num_ac97] = codec;
3016         }
3017
3018         /* pick the minimum of channels supported by ICHx or codec(s) */
3019         card->channels = (card->channels > total_channels)?total_channels:card->channels;
3020
3021         return num_ac97;
3022 }
3023
3024 static void __devinit i810_configure_clocking (void)
3025 {
3026         struct i810_card *card;
3027         struct i810_state *state;
3028         struct dmabuf *dmabuf;
3029         unsigned int i, offset, new_offset;
3030         unsigned long flags;
3031
3032         card = devs;
3033         /* We could try to set the clocking for multiple cards, but can you even have
3034          * more than one i810 in a machine?  Besides, clocking is global, so unless
3035          * someone actually thinks more than one i810 in a machine is possible and
3036          * decides to rewrite that little bit, setting the rate for more than one card
3037          * is a waste of time.
3038          */
3039         if(card != NULL) {
3040                 state = card->states[0] = (struct i810_state *)
3041                                         kmalloc(sizeof(struct i810_state), GFP_KERNEL);
3042                 if (state == NULL)
3043                         return;
3044                 memset(state, 0, sizeof(struct i810_state));
3045                 dmabuf = &state->dmabuf;
3046
3047                 dmabuf->write_channel = card->alloc_pcm_channel(card);
3048                 state->virt = 0;
3049                 state->card = card;
3050                 state->magic = I810_STATE_MAGIC;
3051                 init_waitqueue_head(&dmabuf->wait);
3052                 init_MUTEX(&state->open_sem);
3053                 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
3054                 dmabuf->trigger = PCM_ENABLE_OUTPUT;
3055                 i810_set_spdif_output(state, -1, 0);
3056                 i810_set_dac_channels(state, 2);
3057                 i810_set_dac_rate(state, 48000);
3058                 if(prog_dmabuf(state, 0) != 0) {
3059                         goto config_out_nodmabuf;
3060                 }
3061                 if(dmabuf->dmasize < 16384) {
3062                         goto config_out;
3063                 }
3064                 dmabuf->count = dmabuf->dmasize;
3065                 CIV_TO_LVI(card->iobase+dmabuf->write_channel->port, -1);
3066                 local_irq_save(flags);
3067                 start_dac(state);
3068                 offset = i810_get_dma_addr(state, 0);
3069                 mdelay(50);
3070                 new_offset = i810_get_dma_addr(state, 0);
3071                 stop_dac(state);
3072                 local_irq_restore(flags);
3073                 i = new_offset - offset;
3074 #ifdef DEBUG_INTERRUPTS
3075                 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
3076 #endif
3077                 if(i == 0)
3078                         goto config_out;
3079                 i = i / 4 * 20;
3080                 if (i > 48500 || i < 47500) {
3081                         clocking = clocking * clocking / i;
3082                         printk("i810_audio: setting clocking to %d\n", clocking);
3083                 }
3084 config_out:
3085                 dealloc_dmabuf(state);
3086 config_out_nodmabuf:
3087                 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
3088                 kfree(state);
3089                 card->states[0] = NULL;
3090         }
3091 }
3092
3093 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
3094    until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
3095
3096 static int __devinit i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
3097 {
3098         struct i810_card *card;
3099
3100         if (pci_enable_device(pci_dev))
3101                 return -EIO;
3102
3103         if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
3104                 printk(KERN_ERR "i810_audio: architecture does not support"
3105                        " 32bit PCI busmaster DMA\n");
3106                 return -ENODEV;
3107         }
3108
3109         if( pci_resource_start(pci_dev, 1) == 0)
3110         {
3111                 /* MMIO only ICH5 .. here be dragons .. */
3112                 printk(KERN_ERR "i810_audio: Pure MMIO interfaces not yet supported.\n");
3113                 return -ENODEV;
3114         }
3115
3116         if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
3117                 printk(KERN_ERR "i810_audio: out of memory\n");
3118                 return -ENOMEM;
3119         }
3120         memset(card, 0, sizeof(*card));
3121
3122         card->initializing = 1;
3123         card->pci_dev = pci_dev;
3124         card->pci_id = pci_id->device;
3125         card->ac97base = pci_resource_start (pci_dev, 0);
3126         card->iobase = pci_resource_start (pci_dev, 1);
3127
3128         /* if chipset could have mmio capability, check it */
3129         if (card_cap[pci_id->driver_data].flags & CAP_MMIO) {
3130                 card->ac97base_mmio_phys = pci_resource_start (pci_dev, 2);
3131                 card->iobase_mmio_phys = pci_resource_start (pci_dev, 3);
3132
3133                 if ((card->ac97base_mmio_phys) && (card->iobase_mmio_phys)) {
3134                         card->use_mmio = 1;
3135                 }
3136                 else {
3137                         card->ac97base_mmio_phys = 0;
3138                         card->iobase_mmio_phys = 0;
3139                 }
3140         }
3141
3142         card->irq = pci_dev->irq;
3143         card->next = devs;
3144         card->magic = I810_CARD_MAGIC;
3145 #ifdef CONFIG_PM
3146         card->pm_suspended=0;
3147 #endif
3148         spin_lock_init(&card->lock);
3149         spin_lock_init(&card->ac97_lock);
3150         devs = card;
3151
3152         pci_set_master(pci_dev);
3153
3154         printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, "
3155                "MEM 0x%04lx and 0x%04lx, IRQ %d\n",
3156                card_names[pci_id->driver_data],
3157                card->iobase, card->ac97base,
3158                card->ac97base_mmio_phys, card->iobase_mmio_phys,
3159                card->irq);
3160
3161         card->alloc_pcm_channel = i810_alloc_pcm_channel;
3162         card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
3163         card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
3164         card->free_pcm_channel = i810_free_pcm_channel;
3165
3166         if ((card->channel = pci_alloc_consistent(pci_dev,
3167             sizeof(struct i810_channel)*NR_HW_CH, &card->chandma)) == NULL) {
3168                 printk(KERN_ERR "i810: cannot allocate channel DMA memory\n");
3169                 goto out_mem;
3170         }
3171
3172         { /* We may dispose of this altogether some time soon, so... */
3173                 struct i810_channel *cp = card->channel;
3174
3175                 cp[0].offset = 0;
3176                 cp[0].port = 0x00;
3177                 cp[0].num = 0;
3178                 cp[1].offset = 0;
3179                 cp[1].port = 0x10;
3180                 cp[1].num = 1;
3181                 cp[2].offset = 0;
3182                 cp[2].port = 0x20;
3183                 cp[2].num = 2;
3184         }
3185
3186         /* claim our iospace and irq */
3187         request_region(card->iobase, 64, card_names[pci_id->driver_data]);
3188         request_region(card->ac97base, 256, card_names[pci_id->driver_data]);
3189
3190         if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
3191                         card_names[pci_id->driver_data], card)) {
3192                 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
3193                 goto out_pio;
3194         }
3195
3196         if (card->use_mmio) {
3197                 if (request_mem_region(card->ac97base_mmio_phys, 512, "ich_audio MMBAR")) {
3198                         if ((card->ac97base_mmio = ioremap(card->ac97base_mmio_phys, 512))) { /*@FIXME can ioremap fail? don't know (jsaw) */
3199                                 if (request_mem_region(card->iobase_mmio_phys, 256, "ich_audio MBBAR")) {
3200                                         if ((card->iobase_mmio = ioremap(card->iobase_mmio_phys, 256))) {
3201                                                 printk(KERN_INFO "i810: %s mmio at 0x%04lx and 0x%04lx\n",
3202                                                        card_names[pci_id->driver_data],
3203                                                        (unsigned long) card->ac97base_mmio,
3204                                                        (unsigned long) card->iobase_mmio);
3205                                         }
3206                                         else {
3207                                                 iounmap(card->ac97base_mmio);
3208                                                 release_mem_region(card->ac97base_mmio_phys, 512);
3209                                                 release_mem_region(card->iobase_mmio_phys, 512);
3210                                                 card->use_mmio = 0;
3211                                         }
3212                                 }
3213                                 else {
3214                                         iounmap(card->ac97base_mmio);
3215                                         release_mem_region(card->ac97base_mmio_phys, 512);
3216                                         card->use_mmio = 0;
3217                                 }
3218                         }
3219                 }
3220                 else {
3221                         card->use_mmio = 0;
3222                 }
3223         }
3224
3225         /* initialize AC97 codec and register /dev/mixer */
3226         if (i810_ac97_init(card) <= 0) {
3227                 free_irq(card->irq, card);
3228                 goto out_iospace;
3229         }
3230         pci_set_drvdata(pci_dev, card);
3231
3232         if(clocking == 0) {
3233                 clocking = 48000;
3234                 i810_configure_clocking();
3235         }
3236
3237         /* register /dev/dsp */
3238         if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
3239                 int i;
3240                 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
3241                 free_irq(card->irq, card);
3242                 for (i = 0; i < NR_AC97; i++)
3243                 if (card->ac97_codec[i] != NULL) {
3244                         unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3245                         ac97_release_codec(card->ac97_codec[i]);
3246                 }
3247                 goto out_iospace;
3248         }
3249
3250         card->initializing = 0;
3251         return 0;
3252
3253 out_iospace:
3254         if (card->use_mmio) {
3255                 iounmap(card->ac97base_mmio);
3256                 iounmap(card->iobase_mmio);
3257                 release_mem_region(card->ac97base_mmio_phys, 512);
3258                 release_mem_region(card->iobase_mmio_phys, 256);
3259         }
3260 out_pio:
3261         release_region(card->iobase, 64);
3262         release_region(card->ac97base, 256);
3263         pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3264             card->channel, card->chandma);
3265 out_mem:
3266         kfree(card);
3267         return -ENODEV;
3268 }
3269
3270 static void __devexit i810_remove(struct pci_dev *pci_dev)
3271 {
3272         int i;
3273         struct i810_card *card = pci_get_drvdata(pci_dev);
3274         /* free hardware resources */
3275         free_irq(card->irq, devs);
3276         release_region(card->iobase, 64);
3277         release_region(card->ac97base, 256);
3278         pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3279                             card->channel, card->chandma);
3280         if (card->use_mmio) {
3281                 iounmap(card->ac97base_mmio);
3282                 iounmap(card->iobase_mmio);
3283                 release_mem_region(card->ac97base_mmio_phys, 512);
3284                 release_mem_region(card->iobase_mmio_phys, 256);
3285         }
3286
3287         /* unregister audio devices */
3288         for (i = 0; i < NR_AC97; i++)
3289                 if (card->ac97_codec[i] != NULL) {
3290                         unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3291                         ac97_release_codec(card->ac97_codec[i]);
3292                         card->ac97_codec[i] = NULL;
3293                 }
3294         unregister_sound_dsp(card->dev_audio);
3295         kfree(card);
3296 }
3297
3298 #ifdef CONFIG_PM
3299 static int i810_pm_suspend(struct pci_dev *dev, u32 pm_state)
3300 {
3301         struct i810_card *card = pci_get_drvdata(dev);
3302         struct i810_state *state;
3303         unsigned long flags;
3304         struct dmabuf *dmabuf;
3305         int i,num_ac97;
3306 #ifdef DEBUG
3307         printk("i810_audio: i810_pm_suspend called\n");
3308 #endif
3309         if(!card) return 0;
3310         spin_lock_irqsave(&card->lock, flags);
3311         card->pm_suspended=1;
3312         for(i=0;i<NR_HW_CH;i++) {
3313                 state = card->states[i];
3314                 if(!state) continue;
3315                 /* this happens only if there are open files */
3316                 dmabuf = &state->dmabuf;
3317                 if(dmabuf->enable & DAC_RUNNING ||
3318                    (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
3319                         state->pm_saved_dac_rate=dmabuf->rate;
3320                         stop_dac(state);
3321                 } else {
3322                         state->pm_saved_dac_rate=0;
3323                 }
3324                 if(dmabuf->enable & ADC_RUNNING) {
3325                         state->pm_saved_adc_rate=dmabuf->rate;
3326                         stop_adc(state);
3327                 } else {
3328                         state->pm_saved_adc_rate=0;
3329                 }
3330                 dmabuf->ready = 0;
3331                 dmabuf->swptr = dmabuf->hwptr = 0;
3332                 dmabuf->count = dmabuf->total_bytes = 0;
3333         }
3334
3335         spin_unlock_irqrestore(&card->lock, flags);
3336
3337         /* save mixer settings */
3338         for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3339                 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3340                 if(!codec) continue;
3341                 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3342                         if((supported_mixer(codec,i)) &&
3343                            (codec->read_mixer)) {
3344                                 card->pm_saved_mixer_settings[i][num_ac97]=
3345                                         codec->read_mixer(codec,i);
3346                         }
3347                 }
3348         }
3349         pci_save_state(dev,card->pm_save_state); /* XXX do we need this? */
3350         pci_disable_device(dev); /* disable busmastering */
3351         pci_set_power_state(dev,3); /* Zzz. */
3352
3353         return 0;
3354 }
3355
3356
3357 static int i810_pm_resume(struct pci_dev *dev)
3358 {
3359         int num_ac97,i=0;
3360         struct i810_card *card=pci_get_drvdata(dev);
3361         pci_enable_device(dev);
3362         pci_restore_state (dev,card->pm_save_state);
3363
3364         /* observation of a toshiba portege 3440ct suggests that the
3365            hardware has to be more or less completely reinitialized from
3366            scratch after an apm suspend.  Works For Me.   -dan */
3367
3368         i810_ac97_power_up_bus(card);
3369
3370         for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3371                 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3372                 /* check they haven't stolen the hardware while we were
3373                    away */
3374                 if(!codec || !i810_ac97_exists(card,num_ac97)) {
3375                         if(num_ac97) continue;
3376                         else BUG();
3377                 }
3378                 if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
3379
3380                 if((card->ac97_features&0x0001)) {
3381                         /* at probe time we found we could do variable
3382                            rates, but APM suspend has made it forget
3383                            its magical powers */
3384                         if(!i810_ac97_enable_variable_rate(codec)) BUG();
3385                 }
3386                 /* we lost our mixer settings, so restore them */
3387                 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3388                         if(supported_mixer(codec,i)){
3389                                 int val=card->
3390                                         pm_saved_mixer_settings[i][num_ac97];
3391                                 codec->mixer_state[i]=val;
3392                                 codec->write_mixer(codec,i,
3393                                                    (val  & 0xff) ,
3394                                                    ((val >> 8)  & 0xff) );
3395                         }
3396                 }
3397         }
3398
3399         /* we need to restore the sample rate from whatever it was */
3400         for(i=0;i<NR_HW_CH;i++) {
3401                 struct i810_state * state=card->states[i];
3402                 if(state) {
3403                         if(state->pm_saved_adc_rate)
3404                                 i810_set_adc_rate(state,state->pm_saved_adc_rate);
3405                         if(state->pm_saved_dac_rate)
3406                                 i810_set_dac_rate(state,state->pm_saved_dac_rate);
3407                 }
3408         }
3409
3410
3411         card->pm_suspended = 0;
3412
3413         /* any processes that were reading/writing during the suspend
3414            probably ended up here */
3415         for(i=0;i<NR_HW_CH;i++) {
3416                 struct i810_state *state = card->states[i];
3417                 if(state) wake_up(&state->dmabuf.wait);
3418         }
3419
3420         return 0;
3421 }
3422 #endif /* CONFIG_PM */
3423
3424 MODULE_AUTHOR("");
3425 MODULE_DESCRIPTION("Intel 810 audio support");
3426 MODULE_LICENSE("GPL");
3427 MODULE_PARM(ftsodell, "i");
3428 MODULE_PARM(clocking, "i");
3429 MODULE_PARM(strict_clocking, "i");
3430 MODULE_PARM(spdif_locked, "i");
3431
3432 #define I810_MODULE_NAME "intel810_audio"
3433
3434 static struct pci_driver i810_pci_driver = {
3435         .name           = I810_MODULE_NAME,
3436         .id_table       = i810_pci_tbl,
3437         .probe          = i810_probe,
3438         .remove         = __devexit_p(i810_remove),
3439 #ifdef CONFIG_PM
3440         .suspend        = i810_pm_suspend,
3441         .resume         = i810_pm_resume,
3442 #endif /* CONFIG_PM */
3443 };
3444
3445
3446 static int __init i810_init_module (void)
3447 {
3448         printk(KERN_INFO "Intel 810 + AC97 Audio, version "
3449                DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
3450
3451         if (!pci_register_driver(&i810_pci_driver)) {
3452                 pci_unregister_driver(&i810_pci_driver);
3453                 return -ENODEV;
3454         }
3455         if(ftsodell != 0) {
3456                 printk("i810_audio: ftsodell is now a deprecated option.\n");
3457         }
3458         if(spdif_locked > 0 ) {
3459                 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
3460                         printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
3461                 } else {
3462                         printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n");
3463                         spdif_locked = 0;
3464                 }
3465         }
3466
3467         return 0;
3468 }
3469
3470 static void __exit i810_cleanup_module (void)
3471 {
3472         pci_unregister_driver(&i810_pci_driver);
3473 }
3474
3475 module_init(i810_init_module);
3476 module_exit(i810_cleanup_module);
3477
3478 /*
3479 Local Variables:
3480 c-basic-offset: 8
3481 End:
3482 */