sound/oss/swarm_cs4297a.c

   1 /*******************************************************************************
   2 *
   3 *      "swarm_cs4297a.c" --  Cirrus Logic-Crystal CS4297a linux audio driver.
   4 *
   5 *      Copyright (C) 2001  Broadcom Corporation.
   6 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   7 *            -- adapted from drivers by Thomas Sailer,
   8 *            -- but don't bug him; Problems should go to:
   9 *            -- tom woller (twoller@crystal.cirrus.com) or
  10 *               (audio@crystal.cirrus.com).
  11 *            -- adapted from cs4281 PCI driver for cs4297a on
  12 *               BCM1250 Synchronous Serial interface
  13 *               (kwalker@broadcom.com)
  14 *
  15 *      This program is free software; you can redistribute it and/or modify
  16 *      it under the terms of the GNU General Public License as published by
  17 *      the Free Software Foundation; either version 2 of the License, or
  18 *      (at your option) any later version.
  19 *
  20 *      This program is distributed in the hope that it will be useful,
  21 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 *      GNU General Public License for more details.
  24 *
  25 *      You should have received a copy of the GNU General Public License
  26 *      along with this program; if not, write to the Free Software
  27 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28 *
  29 * Module command line parameters:
  30 *   none
  31 *
  32 *  Supported devices:
  33 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  34 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  35 *  /dev/midi   simple MIDI UART interface, no ioctl
  36 *
  37 * Modification History
  38 * 08/20/00 trw - silence and no stopping DAC until release
  39 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  40 * 09/18/00 trw - added 16bit only record with conversion
  41 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  42 *                capture/playback rates)
  43 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  44 *                libOSSm.so)
  45 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  46 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  47 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  48 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  49 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  50 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  51 * 12/08/00 trw - added PM support.
  52 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  53 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  54 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  55 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  56 *                defaultorder-100 as power of 2 for the buffer size. example:
  57 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  58 *
  59 *******************************************************************************/
  60
  61 #include <linux/list.h>
  62 #include <linux/module.h>
  63 #include <linux/string.h>
  64 #include <linux/ioport.h>
  65 #include <linux/sched.h>
  66 #include <linux/delay.h>
  67 #include <linux/sound.h>
  68 #include <linux/slab.h>
  69 #include <linux/soundcard.h>
  70 #include <linux/ac97_codec.h>
  71 #include <linux/pci.h>
  72 #include <linux/bitops.h>
  73 #include <asm/io.h>
  74 #include <asm/dma.h>
  75 #include <linux/init.h>
  76 #include <linux/poll.h>
  77 #include <linux/smp_lock.h>
  78 #include <linux/wrapper.h>
  79 #include <asm/uaccess.h>
  80 #include <asm/hardirq.h>
  81
  82 #include <asm/sibyte/sb1250_regs.h>
  83 #include <asm/sibyte/sb1250_int.h>
  84 #include <asm/sibyte/sb1250_dma.h>
  85 #include <asm/sibyte/sb1250_scd.h>
  86 #include <asm/sibyte/sb1250_syncser.h>
  87 #include <asm/sibyte/sb1250_mac.h>
  88 #include <asm/sibyte/sb1250.h>
  89 #include <asm/sibyte/64bit.h>
  90
  91 struct cs4297a_state;
  92
  93 static void stop_dac(struct cs4297a_state *s);
  94 static void stop_adc(struct cs4297a_state *s);
  95 static void start_dac(struct cs4297a_state *s);
  96 static void start_adc(struct cs4297a_state *s);
  97 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  98
  99 // ---------------------------------------------------------------------
 100
 101 #define CS4297a_MAGIC           0xf00beef1
 102
 103 // buffer order determines the size of the dma buffer for the driver.
 104 // under Linux, a smaller buffer allows more responsiveness from many of the
 105 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 106 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 107 // rather than 64k as some of the games work more responsively.
 108 // log base 2( buff sz = 32k).
 109
 110 //static unsigned long defaultorder = 3;
 111 //MODULE_PARM(defaultorder, "i");
 112
 113 //
 114 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 115 //
 116 #define CSDEBUG 0
 117 #if CSDEBUG
 118 #define CSDEBUG_INTERFACE 1
 119 #else
 120 #undef CSDEBUG_INTERFACE
 121 #endif
 122 //
 123 // cs_debugmask areas
 124 //
 125 #define CS_INIT         0x00000001      // initialization and probe functions
 126 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 127 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 128 #define CS_FUNCTION     0x00000008      // enter/leave functions
 129 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 130 #define CS_WAVE_READ    0x00000020      // read information for wave
 131 #define CS_AC97         0x00000040      // AC97 register access
 132 #define CS_DESCR        0x00000080      // descriptor management
 133 #define CS_OPEN         0x00000400      // all open functions in the driver
 134 #define CS_RELEASE      0x00000800      // all release functions in the driver
 135 #define CS_PARMS        0x00001000      // functional and operational parameters
 136 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 137 #define CS_TMP          0x10000000      // tmp debug mask bit
 138
 139 //
 140 // CSDEBUG is usual mode is set to 1, then use the
 141 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 142 // Debug level of 1 has been defined to be kernel errors and info
 143 // that should be printed on any released driver.
 144 //
 145 #if CSDEBUG
 146 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 147 #else
 148 #define CS_DBGOUT(mask,level,x)
 149 #endif
 150
 151 #if CSDEBUG
 152 static unsigned long cs_debuglevel = 4; // levels range from 1-9
 153 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
 154 MODULE_PARM(cs_debuglevel, "i");
 155 MODULE_PARM(cs_debugmask, "i");
 156 #endif
 157 #define CS_TRUE         1
 158 #define CS_FALSE        0
 159
 160 #define CS_TYPE_ADC 0
 161 #define CS_TYPE_DAC 1
 162
 163 #define SER_BASE    (A_SER_BASE_1 + KSEG1)
 164 #define SS_CSR(t)   (SER_BASE+t)
 165 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
 166 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
 167
 168 #define FRAME_BYTES            32
 169 #define FRAME_SAMPLE_BYTES      4
 170
 171 /* Should this be variable? */
 172 #define SAMPLE_BUF_SIZE        (16*1024)
 173 #define SAMPLE_FRAME_COUNT     (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
 174 /* The driver can explode/shrink the frames to/from a smaller sample
 175    buffer */
 176 #define DMA_BLOAT_FACTOR       1
 177 #define DMA_DESCR              (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
 178 #define DMA_BUF_SIZE           (DMA_DESCR * FRAME_BYTES)
 179
 180 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
 181 #define DMA_INT_CNT            ((1 << S_DMA_INT_PKTCNT) - 1)
 182
 183 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
 184 #define REG_LATENCY            150
 185
 186 #define FRAME_TX_US             20
 187
 188 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
 189
 190 static const char invalid_magic[] =
 191     KERN_CRIT "cs4297a: invalid magic value\n";
 192
 193 #define VALIDATE_STATE(s)                          \
 194 ({                                                 \
 195         if (!(s) || (s)->magic != CS4297a_MAGIC) { \
 196                 printk(invalid_magic);             \
 197                 return -ENXIO;                     \
 198         }                                          \
 199 })
 200
 201 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
 202
 203 typedef struct serdma_descr_s {
 204         u64 descr_a;
 205         u64 descr_b;
 206 } serdma_descr_t;
 207
 208 typedef unsigned long paddr_t;
 209
 210 typedef struct serdma_s {
 211         unsigned         ringsz;
 212         serdma_descr_t  *descrtab;
 213         serdma_descr_t  *descrtab_end;
 214         paddr_t          descrtab_phys;
 215
 216         serdma_descr_t  *descr_add;
 217         serdma_descr_t  *descr_rem;
 218
 219         u64  *dma_buf;           // buffer for DMA contents (frames)
 220         paddr_t          dma_buf_phys;
 221         u16  *sample_buf;               // tmp buffer for sample conversions
 222         u16  *sb_swptr;
 223         u16  *sb_hwptr;
 224         u16  *sb_end;
 225
 226         dma_addr_t dmaaddr;
 227 //        unsigned buforder;    // Log base 2 of 'dma_buf' size in bytes..
 228         unsigned numfrag;       // # of 'fragments' in the buffer.
 229         unsigned fragshift;     // Log base 2 of fragment size.
 230         unsigned hwptr, swptr;
 231         unsigned total_bytes;   // # bytes process since open.
 232         unsigned blocks;        // last returned blocks value GETOPTR
 233         unsigned wakeup;        // interrupt occurred on block
 234         int count;
 235         unsigned underrun;      // underrun flag
 236         unsigned error; // over/underrun
 237         wait_queue_head_t wait;
 238         wait_queue_head_t reg_wait;
 239         // redundant, but makes calculations easier
 240         unsigned fragsize;      // 2**fragshift..
 241         unsigned sbufsz;        // 2**buforder.
 242         unsigned fragsamples;
 243         // OSS stuff
 244         unsigned mapped:1;      // Buffer mapped in cs4297a_mmap()?
 245         unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 246         unsigned endcleared:1;
 247         unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 248         unsigned ossfragshift;
 249         int ossmaxfrags;
 250         unsigned subdivision;
 251 } serdma_t;
 252
 253 struct cs4297a_state {
 254         // magic
 255         unsigned int magic;
 256
 257         struct list_head list;
 258
 259         // soundcore stuff
 260         int dev_audio;
 261         int dev_mixer;
 262
 263         // hardware resources
 264         unsigned int irq;
 265
 266         struct {
 267                 unsigned int rx_ovrrn; /* FIFO */
 268                 unsigned int rx_overflow; /* staging buffer */
 269                 unsigned int tx_underrun;
 270                 unsigned int rx_bad;
 271                 unsigned int rx_good;
 272         } stats;
 273
 274         // mixer registers
 275         struct {
 276                 unsigned short vol[10];
 277                 unsigned int recsrc;
 278                 unsigned int modcnt;
 279                 unsigned short micpreamp;
 280         } mix;
 281
 282         // wave stuff
 283         struct properties {
 284                 unsigned fmt;
 285                 unsigned fmt_original;  // original requested format
 286                 unsigned channels;
 287                 unsigned rate;
 288         } prop_dac, prop_adc;
 289         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 290         unsigned ena;
 291         spinlock_t lock;
 292         struct semaphore open_sem;
 293         struct semaphore open_sem_adc;
 294         struct semaphore open_sem_dac;
 295         mode_t open_mode;
 296         wait_queue_head_t open_wait;
 297         wait_queue_head_t open_wait_adc;
 298         wait_queue_head_t open_wait_dac;
 299
 300         dma_addr_t dmaaddr_sample_buf;
 301         unsigned buforder_sample_buf;   // Log base 2 of 'dma_buf' size in bytes..
 302
 303         serdma_t dma_dac, dma_adc;
 304
 305         volatile u16 read_value;
 306         volatile u16 read_reg;
 307         volatile u64 reg_request;
 308 };
 309
 310 #if 1
 311 #define prog_codec(a,b)
 312 #define dealloc_dmabuf(a,b);
 313 #endif
 314
 315 static int prog_dmabuf_adc(struct cs4297a_state *s)
 316 {
 317         s->dma_adc.ready = 1;
 318         return 0;
 319 }
 320
 321
 322 static int prog_dmabuf_dac(struct cs4297a_state *s)
 323 {
 324         s->dma_dac.ready = 1;
 325         return 0;
 326 }
 327
 328 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
 329                           unsigned len, unsigned char c)
 330 {
 331         if (bptr + len > bsize) {
 332                 unsigned x = bsize - bptr;
 333                 memset(((char *) buf) + bptr, c, x);
 334                 bptr = 0;
 335                 len -= x;
 336         }
 337         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
 338                 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
 339                         (unsigned)c, (unsigned)((char *) buf) + bptr, len));
 340         memset(((char *) buf) + bptr, c, len);
 341 }
 342
 343 #if CSDEBUG
 344
 345 // DEBUG ROUTINES
 346
 347 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 348 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 349 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 350 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 351
 352 static void cs_printioctl(unsigned int x)
 353 {
 354         unsigned int i;
 355         unsigned char vidx;
 356         // Index of mixtable1[] member is Device ID
 357         // and must be <= SOUND_MIXER_NRDEVICES.
 358         // Value of array member is index into s->mix.vol[]
 359         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 360                 [SOUND_MIXER_PCM] = 1,  // voice
 361                 [SOUND_MIXER_LINE1] = 2,        // AUX
 362                 [SOUND_MIXER_CD] = 3,   // CD
 363                 [SOUND_MIXER_LINE] = 4, // Line
 364                 [SOUND_MIXER_SYNTH] = 5,        // FM
 365                 [SOUND_MIXER_MIC] = 6,  // Mic
 366                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 367                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 368                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 369         };
 370
 371         switch (x) {
 372         case SOUND_MIXER_CS_GETDBGMASK:
 373                 CS_DBGOUT(CS_IOCTL, 4,
 374                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 375                 break;
 376         case SOUND_MIXER_CS_GETDBGLEVEL:
 377                 CS_DBGOUT(CS_IOCTL, 4,
 378                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 379                 break;
 380         case SOUND_MIXER_CS_SETDBGMASK:
 381                 CS_DBGOUT(CS_IOCTL, 4,
 382                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 383                 break;
 384         case SOUND_MIXER_CS_SETDBGLEVEL:
 385                 CS_DBGOUT(CS_IOCTL, 4,
 386                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 387                 break;
 388         case OSS_GETVERSION:
 389                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 390                 break;
 391         case SNDCTL_DSP_SYNC:
 392                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 393                 break;
 394         case SNDCTL_DSP_SETDUPLEX:
 395                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 396                 break;
 397         case SNDCTL_DSP_GETCAPS:
 398                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 399                 break;
 400         case SNDCTL_DSP_RESET:
 401                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 402                 break;
 403         case SNDCTL_DSP_SPEED:
 404                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 405                 break;
 406         case SNDCTL_DSP_STEREO:
 407                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 408                 break;
 409         case SNDCTL_DSP_CHANNELS:
 410                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 411                 break;
 412         case SNDCTL_DSP_GETFMTS:
 413                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 414                 break;
 415         case SNDCTL_DSP_SETFMT:
 416                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 417                 break;
 418         case SNDCTL_DSP_POST:
 419                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 420                 break;
 421         case SNDCTL_DSP_GETTRIGGER:
 422                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 423                 break;
 424         case SNDCTL_DSP_SETTRIGGER:
 425                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 426                 break;
 427         case SNDCTL_DSP_GETOSPACE:
 428                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 429                 break;
 430         case SNDCTL_DSP_GETISPACE:
 431                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 432                 break;
 433         case SNDCTL_DSP_NONBLOCK:
 434                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 435                 break;
 436         case SNDCTL_DSP_GETODELAY:
 437                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 438                 break;
 439         case SNDCTL_DSP_GETIPTR:
 440                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 441                 break;
 442         case SNDCTL_DSP_GETOPTR:
 443                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 444                 break;
 445         case SNDCTL_DSP_GETBLKSIZE:
 446                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 447                 break;
 448         case SNDCTL_DSP_SETFRAGMENT:
 449                 CS_DBGOUT(CS_IOCTL, 4,
 450                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 451                 break;
 452         case SNDCTL_DSP_SUBDIVIDE:
 453                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 454                 break;
 455         case SOUND_PCM_READ_RATE:
 456                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 457                 break;
 458         case SOUND_PCM_READ_CHANNELS:
 459                 CS_DBGOUT(CS_IOCTL, 4,
 460                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 461                 break;
 462         case SOUND_PCM_READ_BITS:
 463                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 464                 break;
 465         case SOUND_PCM_WRITE_FILTER:
 466                 CS_DBGOUT(CS_IOCTL, 4,
 467                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 468                 break;
 469         case SNDCTL_DSP_SETSYNCRO:
 470                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 471                 break;
 472         case SOUND_PCM_READ_FILTER:
 473                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 474                 break;
 475         case SOUND_MIXER_PRIVATE1:
 476                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 477                 break;
 478         case SOUND_MIXER_PRIVATE2:
 479                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 480                 break;
 481         case SOUND_MIXER_PRIVATE3:
 482                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 483                 break;
 484         case SOUND_MIXER_PRIVATE4:
 485                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 486                 break;
 487         case SOUND_MIXER_PRIVATE5:
 488                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 489                 break;
 490         case SOUND_MIXER_INFO:
 491                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 492                 break;
 493         case SOUND_OLD_MIXER_INFO:
 494                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 495                 break;
 496
 497         default:
 498                 switch (_IOC_NR(x)) {
 499                 case SOUND_MIXER_VOLUME:
 500                         CS_DBGOUT(CS_IOCTL, 4,
 501                                   printk("SOUND_MIXER_VOLUME:\n"));
 502                         break;
 503                 case SOUND_MIXER_SPEAKER:
 504                         CS_DBGOUT(CS_IOCTL, 4,
 505                                   printk("SOUND_MIXER_SPEAKER:\n"));
 506                         break;
 507                 case SOUND_MIXER_RECLEV:
 508                         CS_DBGOUT(CS_IOCTL, 4,
 509                                   printk("SOUND_MIXER_RECLEV:\n"));
 510                         break;
 511                 case SOUND_MIXER_MIC:
 512                         CS_DBGOUT(CS_IOCTL, 4,
 513                                   printk("SOUND_MIXER_MIC:\n"));
 514                         break;
 515                 case SOUND_MIXER_SYNTH:
 516                         CS_DBGOUT(CS_IOCTL, 4,
 517                                   printk("SOUND_MIXER_SYNTH:\n"));
 518                         break;
 519                 case SOUND_MIXER_RECSRC:
 520                         CS_DBGOUT(CS_IOCTL, 4,
 521                                   printk("SOUND_MIXER_RECSRC:\n"));
 522                         break;
 523                 case SOUND_MIXER_DEVMASK:
 524                         CS_DBGOUT(CS_IOCTL, 4,
 525                                   printk("SOUND_MIXER_DEVMASK:\n"));
 526                         break;
 527                 case SOUND_MIXER_RECMASK:
 528                         CS_DBGOUT(CS_IOCTL, 4,
 529                                   printk("SOUND_MIXER_RECMASK:\n"));
 530                         break;
 531                 case SOUND_MIXER_STEREODEVS:
 532                         CS_DBGOUT(CS_IOCTL, 4,
 533                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 534                         break;
 535                 case SOUND_MIXER_CAPS:
 536                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 537                         break;
 538                 default:
 539                         i = _IOC_NR(x);
 540                         if (i >= SOUND_MIXER_NRDEVICES
 541                             || !(vidx = mixtable1[i])) {
 542                                 CS_DBGOUT(CS_IOCTL, 4, printk
 543                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 544                                                 x, i));
 545                         } else {
 546                                 CS_DBGOUT(CS_IOCTL, 4, printk
 547                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 548                                                 x, i));
 549                         }
 550                         break;
 551                 }
 552         }
 553 }
 554 #endif
 555
 556
 557 static int ser_init(struct cs4297a_state *s)
 558 {
 559         int i;
 560
 561         CS_DBGOUT(CS_INIT, 2,
 562                   printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
 563
 564         out64(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
 565
 566         out64(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
 567         out64(32, SS_CSR(R_SER_MINFRM_SZ));
 568         out64(32, SS_CSR(R_SER_MAXFRM_SZ));
 569
 570         out64(1, SS_CSR(R_SER_TX_RD_THRSH));
 571         out64(4, SS_CSR(R_SER_TX_WR_THRSH));
 572         out64(8, SS_CSR(R_SER_RX_RD_THRSH));
 573
 574         /* This looks good from experimentation */
 575         out64((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
 576                M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
 577               SS_CSR(R_SER_LINE_MODE));
 578
 579         /* This looks good from experimentation */
 580         out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 581               SS_TXTBL(0));
 582         out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 583               SS_TXTBL(1));
 584         out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 585               SS_TXTBL(2));
 586         out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
 587               M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
 588
 589         out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 590               SS_RXTBL(0));
 591         out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 592               SS_RXTBL(1));
 593         out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 594               SS_RXTBL(2));
 595         out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
 596               M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
 597
 598         for (i=4; i<16; i++) {
 599                 /* Just in case... */
 600                 out64(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
 601                 out64(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int init_serdma(serdma_t *dma)
 608 {
 609         CS_DBGOUT(CS_INIT, 2,
 610                   printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
 611                          DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
 612
 613         /* Descriptors */
 614         dma->ringsz = DMA_DESCR;
 615         dma->descrtab = kmalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
 616         if (!dma->descrtab) {
 617                 printk(KERN_ERR "cs4297a: kmalloc descrtab failed\n");
 618                 return -1;
 619         }
 620         memset(dma->descrtab, 0, dma->ringsz * sizeof(serdma_descr_t));
 621         dma->descrtab_end = dma->descrtab + dma->ringsz;
 622         /* XXX bloddy mess, use proper DMA API here ...  */
 623         dma->descrtab_phys = PHYSADDR((int)dma->descrtab);
 624         dma->descr_add = dma->descr_rem = dma->descrtab;
 625
 626         /* Frame buffer area */
 627         dma->dma_buf = kmalloc(DMA_BUF_SIZE, GFP_KERNEL);
 628         if (!dma->dma_buf) {
 629                 printk(KERN_ERR "cs4297a: kmalloc dma_buf failed\n");
 630                 kfree(dma->descrtab);
 631                 return -1;
 632         }
 633         memset(dma->dma_buf, 0, DMA_BUF_SIZE);
 634         dma->dma_buf_phys = PHYSADDR((int)dma->dma_buf);
 635
 636         /* Samples buffer area */
 637         dma->sbufsz = SAMPLE_BUF_SIZE;
 638         dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
 639         if (!dma->sample_buf) {
 640                 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
 641                 kfree(dma->descrtab);
 642                 kfree(dma->dma_buf);
 643                 return -1;
 644         }
 645         dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
 646         dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
 647         dma->fragsize = dma->sbufsz >> 1;
 648
 649         CS_DBGOUT(CS_INIT, 4,
 650                   printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
 651                          (int)dma->descrtab, (int)dma->dma_buf,
 652                          (int)dma->sample_buf));
 653
 654         return 0;
 655 }
 656
 657 static int dma_init(struct cs4297a_state *s)
 658 {
 659         int i;
 660
 661         CS_DBGOUT(CS_INIT, 2,
 662                   printk(KERN_INFO "cs4297a: Setting up DMA\n"));
 663
 664         if (init_serdma(&s->dma_adc) ||
 665             init_serdma(&s->dma_dac))
 666                 return -1;
 667
 668         if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
 669             in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
 670                 panic("DMA state corrupted?!");
 671         }
 672
 673         /* Initialize now - the descr/buffer pairings will never
 674            change... */
 675         for (i=0; i<DMA_DESCR; i++) {
 676                 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
 677                         (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
 678                 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
 679                 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
 680                         (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
 681                 s->dma_adc.descrtab[i].descr_b = 0;
 682         }
 683
 684         out64((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
 685                V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
 686               SS_CSR(R_SER_DMA_CONFIG0_RX));
 687         out64(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
 688         out64(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
 689
 690         out64(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
 691         out64(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
 692         out64(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
 693
 694         /* Prep the receive DMA descriptor ring */
 695         out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 696
 697         out64(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
 698
 699         out64((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
 700               SS_CSR(R_SER_INT_MASK));
 701
 702         /* Enable the rx/tx; let the codec warm up to the sync and
 703            start sending good frames before the receive FIFO is
 704            enabled */
 705         out64(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 706         udelay(1000);
 707         out64(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 708
 709         /* XXXKW is this magic? (the "1" part) */
 710         while ((in64(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
 711                 ;
 712
 713         CS_DBGOUT(CS_INIT, 4,
 714                   printk(KERN_INFO "cs4297a: status: %08x\n",
 715                          (unsigned int)(in64(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
 716
 717         return 0;
 718 }
 719
 720 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
 721 {
 722         serdma_t *d = &s->dma_dac;
 723         u64 *data_p;
 724         unsigned swptr;
 725         int flags;
 726         serdma_descr_t *descr;
 727
 728         if (s->reg_request) {
 729                 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
 730                 return -1;
 731         }
 732
 733         if (s->ena & FMODE_WRITE) {
 734                 /* Since a writer has the DSP open, we have to mux the
 735                    request in */
 736                 s->reg_request = data;
 737                 interruptible_sleep_on(&s->dma_dac.reg_wait);
 738                 /* XXXKW how can I deal with the starvation case where
 739                    the opener isn't writing? */
 740         } else {
 741                 /* Be safe when changing ring pointers */
 742                 spin_lock_irqsave(&s->lock, flags);
 743                 if (d->hwptr != d->swptr) {
 744                         printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
 745                                d->hwptr, d->swptr);
 746                         spin_unlock_irqrestore(&s->lock, flags);
 747                         return -1;
 748                 }
 749                 swptr = d->swptr;
 750                 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
 751                 spin_unlock_irqrestore(&s->lock, flags);
 752
 753                 descr = &d->descrtab[swptr];
 754                 data_p = &d->dma_buf[swptr * 4];
 755                 *data_p = data;
 756                 out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
 757                 CS_DBGOUT(CS_DESCR, 4,
 758                           printk(KERN_INFO "cs4297a: add_tx  %p (%x -> %x)\n",
 759                                  data_p, swptr, d->hwptr));
 760         }
 761
 762         CS_DBGOUT(CS_FUNCTION, 6,
 763                   printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
 764
 765         return 0;
 766 }
 767
 768 //****************************************************************************
 769 // "cs4297a_read_ac97" -- Reads an AC97 register
 770 //****************************************************************************
 771 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
 772                             u32 * value)
 773 {
 774         CS_DBGOUT(CS_AC97, 1,
 775                   printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
 776         if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
 777                 return -1;
 778
 779         interruptible_sleep_on(&s->dma_adc.reg_wait);
 780         *value = s->read_value;
 781         CS_DBGOUT(CS_AC97, 2,
 782                   printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
 783
 784         return 0;
 785 }
 786
 787
 788 //****************************************************************************
 789 // "cs4297a_write_ac97()"-- writes an AC97 register
 790 //****************************************************************************
 791 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
 792                              u32 value)
 793 {
 794         CS_DBGOUT(CS_AC97, 1,
 795                   printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
 796         return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
 797 }
 798
 799 static void stop_dac(struct cs4297a_state *s)
 800 {
 801         unsigned long flags;
 802
 803         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
 804         spin_lock_irqsave(&s->lock, flags);
 805         s->ena &= ~FMODE_WRITE;
 806 #if 0
 807         /* XXXKW what do I really want here?  My theory for now is
 808            that I just flip the "ena" bit, and the interrupt handler
 809            will stop processing the xmit channel */
 810         out64((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
 811               SS_CSR(R_SER_DMA_ENABLE));
 812 #endif
 813
 814         spin_unlock_irqrestore(&s->lock, flags);
 815 }
 816
 817
 818 static void start_dac(struct cs4297a_state *s)
 819 {
 820         unsigned long flags;
 821
 822         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
 823         spin_lock_irqsave(&s->lock, flags);
 824         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
 825                                         (s->dma_dac.count > 0
 826                                         && s->dma_dac.ready))) {
 827                 s->ena |= FMODE_WRITE;
 828                 /* XXXKW what do I really want here?  My theory for
 829                    now is that I just flip the "ena" bit, and the
 830                    interrupt handler will start processing the xmit
 831                    channel */
 832
 833                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
 834                         "cs4297a: start_dac(): start dma\n"));
 835
 836         }
 837         spin_unlock_irqrestore(&s->lock, flags);
 838         CS_DBGOUT(CS_FUNCTION, 3,
 839                   printk(KERN_INFO "cs4297a: start_dac()-\n"));
 840 }
 841
 842
 843 static void stop_adc(struct cs4297a_state *s)
 844 {
 845         unsigned long flags;
 846
 847         CS_DBGOUT(CS_FUNCTION, 3,
 848                   printk(KERN_INFO "cs4297a: stop_adc()+\n"));
 849
 850         spin_lock_irqsave(&s->lock, flags);
 851         s->ena &= ~FMODE_READ;
 852
 853         if (s->conversion == 1) {
 854                 s->conversion = 0;
 855                 s->prop_adc.fmt = s->prop_adc.fmt_original;
 856         }
 857         /* Nothing to do really, I need to keep the DMA going
 858            XXXKW when do I get here, and is there more I should do? */
 859         spin_unlock_irqrestore(&s->lock, flags);
 860         CS_DBGOUT(CS_FUNCTION, 3,
 861                   printk(KERN_INFO "cs4297a: stop_adc()-\n"));
 862 }
 863
 864
 865 static void start_adc(struct cs4297a_state *s)
 866 {
 867         unsigned long flags;
 868
 869         CS_DBGOUT(CS_FUNCTION, 2,
 870                   printk(KERN_INFO "cs4297a: start_adc()+\n"));
 871
 872         if (!(s->ena & FMODE_READ) &&
 873             (s->dma_adc.mapped || s->dma_adc.count <=
 874              (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
 875             && s->dma_adc.ready) {
 876                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
 877                         //
 878                         // now only use 16 bit capture, due to truncation issue
 879                         // in the chip, noticable distortion occurs.
 880                         // allocate buffer and then convert from 16 bit to
 881                         // 8 bit for the user buffer.
 882                         //
 883                         s->prop_adc.fmt_original = s->prop_adc.fmt;
 884                         if (s->prop_adc.fmt & AFMT_S8) {
 885                                 s->prop_adc.fmt &= ~AFMT_S8;
 886                                 s->prop_adc.fmt |= AFMT_S16_LE;
 887                         }
 888                         if (s->prop_adc.fmt & AFMT_U8) {
 889                                 s->prop_adc.fmt &= ~AFMT_U8;
 890                                 s->prop_adc.fmt |= AFMT_U16_LE;
 891                         }
 892                         //
 893                         // prog_dmabuf_adc performs a stop_adc() but that is
 894                         // ok since we really haven't started the DMA yet.
 895                         //
 896                         prog_codec(s, CS_TYPE_ADC);
 897
 898                         prog_dmabuf_adc(s);
 899                         s->conversion = 1;
 900                 }
 901                 spin_lock_irqsave(&s->lock, flags);
 902                 s->ena |= FMODE_READ;
 903                 /* Nothing to do really, I am probably already
 904                    DMAing...  XXXKW when do I get here, and is there
 905                    more I should do? */
 906                 spin_unlock_irqrestore(&s->lock, flags);
 907
 908                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
 909                          "cs4297a: start_adc(): start adc\n"));
 910         }
 911         CS_DBGOUT(CS_FUNCTION, 2,
 912                   printk(KERN_INFO "cs4297a: start_adc()-\n"));
 913
 914 }
 915
 916
 917 // call with spinlock held!
 918 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
 919 {
 920         int good_diff, diff, diff2;
 921         u64 *data_p, data;
 922         u32 *s_ptr;
 923         unsigned hwptr;
 924         u32 status;
 925         serdma_t *d;
 926         serdma_descr_t *descr;
 927
 928         // update ADC pointer
 929         status = intflag ? in64(SS_CSR(R_SER_STATUS)) : 0;
 930
 931         if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
 932                 d = &s->dma_adc;
 933                 hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
 934                                      d->descrtab_phys) / sizeof(serdma_descr_t));
 935
 936                 if (s->ena & FMODE_READ) {
 937                         CS_DBGOUT(CS_FUNCTION, 2,
 938                                   printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
 939                                          d->swptr, d->hwptr, hwptr, intflag));
 940                         /* Number of DMA buffers available for software: */
 941                         diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
 942                         d->hwptr = hwptr;
 943                         good_diff = 0;
 944                         s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
 945                         descr = &d->descrtab[d->swptr];
 946                         while (diff2--) {
 947                                 u64 data = *(u64 *)s_ptr;
 948                                 u64 descr_a;
 949                                 u16 left, right;
 950                                 descr_a = descr->descr_a;
 951                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
 952                                 if ((descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((int)s_ptr)) {
 953                                         printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
 954                                 }
 955                                 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
 956                                     (!(descr_a & M_DMA_SERRX_SOP)) ||
 957                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
 958                                         s->stats.rx_bad++;
 959                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
 960                                         continue;
 961                                 }
 962                                 s->stats.rx_good++;
 963                                 if ((data >> 61) == 7) {
 964                                         s->read_value = (data >> 12) & 0xffff;
 965                                         s->read_reg = (data >> 40) & 0x7f;
 966                                         wake_up(&d->reg_wait);
 967                                 }
 968                                 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
 969                                         s->stats.rx_overflow++;
 970                                         printk(KERN_DEBUG "cs4297a: RX overflow\n");
 971                                         continue;
 972                                 }
 973                                 good_diff++;
 974                                 left = ((s_ptr[1] & 0xff) << 8) | ((s_ptr[2] >> 24) & 0xff);
 975                                 right = (s_ptr[2] >> 4) & 0xffff;
 976                                 *d->sb_hwptr++ = left;
 977                                 *d->sb_hwptr++ = right;
 978                                 if (d->sb_hwptr == d->sb_end)
 979                                         d->sb_hwptr = d->sample_buf;
 980                                 descr++;
 981                                 if (descr == d->descrtab_end) {
 982                                         descr = d->descrtab;
 983                                         s_ptr = (u32 *)s->dma_adc.dma_buf;
 984                                 } else {
 985                                         s_ptr += 8;
 986                                 }
 987                         }
 988                         d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
 989                         d->count += good_diff * FRAME_SAMPLE_BYTES;
 990                         if (d->count > d->sbufsz) {
 991                                 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
 992                         }
 993                         d->swptr = (d->swptr + diff) % d->ringsz;
 994                         out64(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 995                         if (d->mapped) {
 996                                 if (d->count >= (signed) d->fragsize)
 997                                         wake_up(&d->wait);
 998                         } else {
 999                                 if (d->count > 0) {
1000                                         CS_DBGOUT(CS_WAVE_READ, 4,
1001                                                   printk(KERN_INFO
1002                                                          "cs4297a: update count -> %d\n", d->count));
1003                                         wake_up(&d->wait);
1004                                 }
1005                         }
1006                 } else {
1007                         /* Receive is going even if no one is
1008                            listening (for register accesses and to
1009                            avoid FIFO overrun) */
1010                         diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1011                         if (!diff) {
1012                                 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1013                         }
1014
1015                         descr = &d->descrtab[d->swptr];
1016                         data_p = &d->dma_buf[d->swptr*4];
1017
1018                         /* Force this to happen at least once; I got
1019                            here because of an interrupt, so there must
1020                            be a buffer to process. */
1021                         do {
1022                                 data = *data_p;
1023                                 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((int)data_p)) {
1024                                         printk(KERN_ERR "cs4297a: RX Bad address %d (%x %x)\n", d->swptr,
1025                                                (int)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1026                                                (int)PHYSADDR((int)data_p));
1027                                 }
1028                                 if (!(data & (1LL << 63)) ||
1029                                     !(descr->descr_a & M_DMA_SERRX_SOP) ||
1030                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1031                                         s->stats.rx_bad++;
1032                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1033                                 } else {
1034                                         s->stats.rx_good++;
1035                                         if ((data >> 61) == 7) {
1036                                                 s->read_value = (data >> 12) & 0xffff;
1037                                                 s->read_reg = (data >> 40) & 0x7f;
1038                                                 wake_up(&d->reg_wait);
1039                                         }
1040                                 }
1041                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
1042                                 descr++;
1043                                 d->swptr++;
1044                                 data_p += 4;
1045                                 if (descr == d->descrtab_end) {
1046                                         descr = d->descrtab;
1047                                         d->swptr = 0;
1048                                         data_p = d->dma_buf;
1049                                 }
1050                                 out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1051                         } while (--diff);
1052                         d->hwptr = hwptr;
1053
1054                         CS_DBGOUT(CS_DESCR, 6,
1055                                   printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1056                 }
1057
1058                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1059                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1060                                 (unsigned)s, d->hwptr,
1061                                 d->total_bytes, d->count));
1062         }
1063
1064         /* XXXKW worry about s->reg_request -- there is a starvation
1065            case if s->ena has FMODE_WRITE on, but the client isn't
1066            doing writes */
1067
1068         // update DAC pointer
1069         //
1070         // check for end of buffer, means that we are going to wait for another interrupt
1071         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1072         //
1073         if (s->ena & FMODE_WRITE) {
1074                 serdma_t *d = &s->dma_dac;
1075                 hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1076                                      d->descrtab_phys) / sizeof(serdma_descr_t));
1077                 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1078                 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1079                                                    "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1080                                                    d->hwptr, hwptr, d->swptr, diff, d->count));
1081                 d->hwptr = hwptr;
1082                 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1083                 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1084                 if (d->mapped) {
1085                         d->count += diff * FRAME_SAMPLE_BYTES;
1086                         if (d->count >= d->fragsize) {
1087                                 d->wakeup = 1;
1088                                 wake_up(&d->wait);
1089                                 if (d->count > d->sbufsz)
1090                                         d->count &= d->sbufsz - 1;
1091                         }
1092                 } else {
1093                         d->count -= diff * FRAME_SAMPLE_BYTES;
1094                         if (d->count <= 0) {
1095                                 //
1096                                 // fill with silence, and do not shut down the DAC.
1097                                 // Continue to play silence until the _release.
1098                                 //
1099                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1100                                         "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1101                                                 (unsigned)(s->prop_dac.fmt &
1102                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1103                                                 (unsigned)d->dma_buf,
1104                                                 d->ringsz));
1105                                 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1106                                 if (d->count < 0) {
1107                                         d->underrun = 1;
1108                                         s->stats.tx_underrun++;
1109                                         d->count = 0;
1110                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1111                                          "cs4297a: cs4297a_update_ptr(): underrun\n"));
1112                                 }
1113                         } else if (d->count <=
1114                                    (signed) d->fragsize
1115                                    && !d->endcleared) {
1116                           /* XXXKW what is this for? */
1117                                 clear_advance(d->dma_buf,
1118                                               d->sbufsz,
1119                                               d->swptr,
1120                                               d->fragsize,
1121                                               0);
1122                                 d->endcleared = 1;
1123                         }
1124                         if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1125                         {
1126                                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1127                                           printk(KERN_INFO
1128                                                  "cs4297a: update count -> %d\n", d->count));
1129                                 wake_up(&d->wait);
1130                         }
1131                 }
1132                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1133                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1134                                 (unsigned) s, d->hwptr,
1135                                 d->total_bytes, d->count));
1136         }
1137 }
1138
1139 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1140                        unsigned long arg)
1141 {
1142         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1143         // Value of array member is recording source Device ID Mask.
1144         static const unsigned int mixer_src[8] = {
1145                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1146                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1147         };
1148
1149         // Index of mixtable1[] member is Device ID
1150         // and must be <= SOUND_MIXER_NRDEVICES.
1151         // Value of array member is index into s->mix.vol[]
1152         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1153                 [SOUND_MIXER_PCM] = 1,  // voice
1154                 [SOUND_MIXER_LINE1] = 2,        // AUX
1155                 [SOUND_MIXER_CD] = 3,   // CD
1156                 [SOUND_MIXER_LINE] = 4, // Line
1157                 [SOUND_MIXER_SYNTH] = 5,        // FM
1158                 [SOUND_MIXER_MIC] = 6,  // Mic
1159                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
1160                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
1161                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
1162         };
1163
1164         static const unsigned mixreg[] = {
1165                 AC97_PCMOUT_VOL,
1166                 AC97_AUX_VOL,
1167                 AC97_CD_VOL,
1168                 AC97_LINEIN_VOL
1169         };
1170         unsigned char l, r, rl, rr, vidx;
1171         unsigned char attentbl[11] =
1172             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1173         unsigned temp1;
1174         int i, val;
1175
1176         VALIDATE_STATE(s);
1177         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1178                  "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1179                          (unsigned) s, cmd));
1180 #if CSDEBUG
1181         cs_printioctl(cmd);
1182 #endif
1183 #if CSDEBUG_INTERFACE
1184
1185         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1186             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1187             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1188             (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1189         {
1190                 switch (cmd) {
1191
1192                 case SOUND_MIXER_CS_GETDBGMASK:
1193                         return put_user(cs_debugmask,
1194                                         (unsigned long *) arg);
1195
1196                 case SOUND_MIXER_CS_GETDBGLEVEL:
1197                         return put_user(cs_debuglevel,
1198                                         (unsigned long *) arg);
1199
1200                 case SOUND_MIXER_CS_SETDBGMASK:
1201                         if (get_user(val, (unsigned long *) arg))
1202                                 return -EFAULT;
1203                         cs_debugmask = val;
1204                         return 0;
1205
1206                 case SOUND_MIXER_CS_SETDBGLEVEL:
1207                         if (get_user(val, (unsigned long *) arg))
1208                                 return -EFAULT;
1209                         cs_debuglevel = val;
1210                         return 0;
1211                 default:
1212                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1213                                 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1214                         return 0;
1215                 }
1216         }
1217 #endif
1218
1219         if (cmd == SOUND_MIXER_PRIVATE1) {
1220                 return -EINVAL;
1221         }
1222         if (cmd == SOUND_MIXER_PRIVATE2) {
1223                 // enable/disable/query spatializer
1224                 if (get_user(val, (int *) arg))
1225                         return -EFAULT;
1226                 if (val != -1) {
1227                         temp1 = (val & 0x3f) >> 2;
1228                         cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1229                         cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1230                                          &temp1);
1231                         cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1232                                           temp1 | 0x2000);
1233                 }
1234                 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1235                 return put_user((temp1 << 2) | 3, (int *) arg);
1236         }
1237         if (cmd == SOUND_MIXER_INFO) {
1238                 mixer_info info;
1239                 memset(&info, 0, sizeof(info));
1240                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1241                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1242                 info.modify_counter = s->mix.modcnt;
1243                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1244                         return -EFAULT;
1245                 return 0;
1246         }
1247         if (cmd == SOUND_OLD_MIXER_INFO) {
1248                 _old_mixer_info info;
1249                 memset(&info, 0, sizeof(info));
1250                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1251                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1252                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1253                         return -EFAULT;
1254                 return 0;
1255         }
1256         if (cmd == OSS_GETVERSION)
1257                 return put_user(SOUND_VERSION, (int *) arg);
1258
1259         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1260                 return -EINVAL;
1261
1262         // If ioctl has only the SIOC_READ bit(bit 31)
1263         // on, process the only-read commands.
1264         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1265                 switch (_IOC_NR(cmd)) {
1266                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1267                         cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1268                                          &temp1);
1269                         return put_user(mixer_src[temp1 & 7], (int *) arg);
1270
1271                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
1272                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1273                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1274                                         (int *) arg);
1275
1276                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
1277                         return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1278                                         (int *) arg);
1279
1280                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
1281                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1282                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1283                                         (int *) arg);
1284
1285                 case SOUND_MIXER_CAPS:
1286                         return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1287
1288                 default:
1289                         i = _IOC_NR(cmd);
1290                         if (i >= SOUND_MIXER_NRDEVICES
1291                             || !(vidx = mixtable1[i]))
1292                                 return -EINVAL;
1293                         return put_user(s->mix.vol[vidx - 1], (int *) arg);
1294                 }
1295         }
1296         // If ioctl doesn't have both the SIOC_READ and
1297         // the SIOC_WRITE bit set, return invalid.
1298         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1299                 return -EINVAL;
1300
1301         // Increment the count of volume writes.
1302         s->mix.modcnt++;
1303
1304         // Isolate the command; it must be a write.
1305         switch (_IOC_NR(cmd)) {
1306
1307         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1308                 if (get_user(val, (int *) arg))
1309                         return -EFAULT;
1310                 i = hweight32(val);     // i = # bits on in val.
1311                 if (i != 1)     // One & only 1 bit must be on.
1312                         return 0;
1313                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1314                         if (val == mixer_src[i]) {
1315                                 temp1 = (i << 8) | i;
1316                                 cs4297a_write_ac97(s,
1317                                                   AC97_RECORD_SELECT,
1318                                                   temp1);
1319                                 return 0;
1320                         }
1321                 }
1322                 return 0;
1323
1324         case SOUND_MIXER_VOLUME:
1325                 if (get_user(val, (int *) arg))
1326                         return -EFAULT;
1327                 l = val & 0xff;
1328                 if (l > 100)
1329                         l = 100;        // Max soundcard.h vol is 100.
1330                 if (l < 6) {
1331                         rl = 63;
1332                         l = 0;
1333                 } else
1334                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
1335
1336                 r = (val >> 8) & 0xff;
1337                 if (r > 100)
1338                         r = 100;        // Max right volume is 100, too
1339                 if (r < 6) {
1340                         rr = 63;
1341                         r = 0;
1342                 } else
1343                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
1344
1345                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
1346                         temp1 = 0x8000; //  turn on the mute bit.
1347                 else
1348                         temp1 = 0;
1349
1350                 temp1 |= (rl << 8) | rr;
1351
1352                 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1353                 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1354
1355 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1356                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1357 #else
1358                 s->mix.vol[8] = val;
1359 #endif
1360                 return put_user(s->mix.vol[8], (int *) arg);
1361
1362         case SOUND_MIXER_SPEAKER:
1363                 if (get_user(val, (int *) arg))
1364                         return -EFAULT;
1365                 l = val & 0xff;
1366                 if (l > 100)
1367                         l = 100;
1368                 if (l < 3) {
1369                         rl = 0;
1370                         l = 0;
1371                 } else {
1372                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
1373                         l = (rl * 13 + 5) / 2;
1374                 }
1375
1376                 if (rl < 3) {
1377                         temp1 = 0x8000;
1378                         rl = 0;
1379                 } else
1380                         temp1 = 0;
1381                 rl = 15 - rl;   // Convert volume to attenuation.
1382                 temp1 |= rl << 1;
1383                 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1384
1385 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1386                 s->mix.vol[6] = l << 8;
1387 #else
1388                 s->mix.vol[6] = val;
1389 #endif
1390                 return put_user(s->mix.vol[6], (int *) arg);
1391
1392         case SOUND_MIXER_RECLEV:
1393                 if (get_user(val, (int *) arg))
1394                         return -EFAULT;
1395                 l = val & 0xff;
1396                 if (l > 100)
1397                         l = 100;
1398                 r = (val >> 8) & 0xff;
1399                 if (r > 100)
1400                         r = 100;
1401                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
1402                 rr = (r * 2 - 5) / 13;
1403                 if (rl < 3 && rr < 3)
1404                         temp1 = 0x8000;
1405                 else
1406                         temp1 = 0;
1407
1408                 temp1 = temp1 | (rl << 8) | rr;
1409                 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1410
1411 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1412                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1413 #else
1414                 s->mix.vol[7] = val;
1415 #endif
1416                 return put_user(s->mix.vol[7], (int *) arg);
1417
1418         case SOUND_MIXER_MIC:
1419                 if (get_user(val, (int *) arg))
1420                         return -EFAULT;
1421                 l = val & 0xff;
1422                 if (l > 100)
1423                         l = 100;
1424                 if (l < 1) {
1425                         l = 0;
1426                         rl = 0;
1427                 } else {
1428                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
1429                         l = (rl * 16 + 4) / 5;
1430                 }
1431                 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1432                 temp1 &= 0x40;  // Isolate 20db gain bit.
1433                 if (rl < 3) {
1434                         temp1 |= 0x8000;
1435                         rl = 0;
1436                 }
1437                 rl = 31 - rl;   // Convert volume to attenuation.
1438                 temp1 |= rl;
1439                 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1440
1441 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1442                 s->mix.vol[5] = val << 8;
1443 #else
1444                 s->mix.vol[5] = val;
1445 #endif
1446                 return put_user(s->mix.vol[5], (int *) arg);
1447
1448
1449         case SOUND_MIXER_SYNTH:
1450                 if (get_user(val, (int *) arg))
1451                         return -EFAULT;
1452                 l = val & 0xff;
1453                 if (l > 100)
1454                         l = 100;
1455                 if (get_user(val, (int *) arg))
1456                         return -EFAULT;
1457                 r = (val >> 8) & 0xff;
1458                 if (r > 100)
1459                         r = 100;
1460                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
1461                 rr = (r * 2 - 11) / 3;
1462                 if (rl < 3)     // If l is low, turn on
1463                         temp1 = 0x0080; //  the mute bit.
1464                 else
1465                         temp1 = 0;
1466
1467                 rl = 63 - rl;   // Convert vol to attenuation.
1468 //              writel(temp1 | rl, s->pBA0 + FMLVC);
1469                 if (rr < 3)     //  If rr is low, turn on
1470                         temp1 = 0x0080; //   the mute bit.
1471                 else
1472                         temp1 = 0;
1473                 rr = 63 - rr;   // Convert vol to attenuation.
1474 //              writel(temp1 | rr, s->pBA0 + FMRVC);
1475
1476 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1477                 s->mix.vol[4] = (r << 8) | l;
1478 #else
1479                 s->mix.vol[4] = val;
1480 #endif
1481                 return put_user(s->mix.vol[4], (int *) arg);
1482
1483
1484         default:
1485                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1486                         "cs4297a: mixer_ioctl(): default\n"));
1487
1488                 i = _IOC_NR(cmd);
1489                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1490                         return -EINVAL;
1491                 if (get_user(val, (int *) arg))
1492                         return -EFAULT;
1493                 l = val & 0xff;
1494                 if (l > 100)
1495                         l = 100;
1496                 if (l < 1) {
1497                         l = 0;
1498                         rl = 31;
1499                 } else
1500                         rl = (attentbl[(l * 10) / 100]) >> 1;
1501
1502                 r = (val >> 8) & 0xff;
1503                 if (r > 100)
1504                         r = 100;
1505                 if (r < 1) {
1506                         r = 0;
1507                         rr = 31;
1508                 } else
1509                         rr = (attentbl[(r * 10) / 100]) >> 1;
1510                 if ((rl > 30) && (rr > 30))
1511                         temp1 = 0x8000;
1512                 else
1513                         temp1 = 0;
1514                 temp1 = temp1 | (rl << 8) | rr;
1515                 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1516
1517 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1518                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1519 #else
1520                 s->mix.vol[vidx - 1] = val;
1521 #endif
1522                 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1523         }
1524 }
1525
1526
1527 // ---------------------------------------------------------------------
1528
1529 static loff_t cs4297a_llseek(struct file *file, loff_t offset, int origin)
1530 {
1531         return -ESPIPE;
1532 }
1533
1534
1535 // ---------------------------------------------------------------------
1536
1537 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1538 {
1539         int minor = iminor(inode);
1540         struct cs4297a_state *s=NULL;
1541         struct list_head *entry;
1542
1543         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1544                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1545
1546         list_for_each(entry, &cs4297a_devs)
1547         {
1548                 s = list_entry(entry, struct cs4297a_state, list);
1549                 if(s->dev_mixer == minor)
1550                         break;
1551         }
1552         if (!s)
1553         {
1554                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1555                         printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1556                 return -ENODEV;
1557         }
1558         VALIDATE_STATE(s);
1559         file->private_data = s;
1560
1561         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1562                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1563
1564         return 0;
1565 }
1566
1567
1568 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1569 {
1570         struct cs4297a_state *s =
1571             (struct cs4297a_state *) file->private_data;
1572
1573         VALIDATE_STATE(s);
1574         return 0;
1575 }
1576
1577
1578 static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1579                                unsigned int cmd, unsigned long arg)
1580 {
1581         return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1582                            arg);
1583 }
1584
1585
1586 // ******************************************************************************************
1587 //   Mixer file operations struct.
1588 // ******************************************************************************************
1589 static /*const */ struct file_operations cs4297a_mixer_fops = {
1590         .owner          = THIS_MODULE,
1591         .llseek         = cs4297a_llseek,
1592         .ioctl          = cs4297a_ioctl_mixdev,
1593         .open           = cs4297a_open_mixdev,
1594         .release        = cs4297a_release_mixdev,
1595 };
1596
1597 // ---------------------------------------------------------------------
1598
1599
1600 static int drain_adc(struct cs4297a_state *s, int nonblock)
1601 {
1602         /* This routine serves no purpose currently - any samples
1603            sitting in the receive queue will just be processed by the
1604            background consumer.  This would be different if DMA
1605            actually stopped when there were no clients. */
1606         return 0;
1607 }
1608
1609 static int drain_dac(struct cs4297a_state *s, int nonblock)
1610 {
1611         DECLARE_WAITQUEUE(wait, current);
1612         unsigned long flags;
1613         unsigned hwptr;
1614         unsigned tmo;
1615         int count;
1616
1617         if (s->dma_dac.mapped)
1618                 return 0;
1619         if (nonblock)
1620                 return -EBUSY;
1621         add_wait_queue(&s->dma_dac.wait, &wait);
1622         while ((count = in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1623                (s->dma_dac.count > 0)) {
1624                 if (!signal_pending(current)) {
1625                         set_current_state(TASK_INTERRUPTIBLE);
1626                         /* XXXKW is this calculation working? */
1627                         tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1628                         schedule_timeout(tmo + 1);
1629                 } else {
1630                         /* XXXKW do I care if there is a signal pending? */
1631                 }
1632         }
1633         spin_lock_irqsave(&s->lock, flags);
1634         /* Reset the bookkeeping */
1635         hwptr = (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1636                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1637         s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1638         spin_unlock_irqrestore(&s->lock, flags);
1639         remove_wait_queue(&s->dma_dac.wait, &wait);
1640         current->state = TASK_RUNNING;
1641         return 0;
1642 }
1643
1644
1645 // ---------------------------------------------------------------------
1646
1647 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1648                            loff_t * ppos)
1649 {
1650         struct cs4297a_state *s =
1651             (struct cs4297a_state *) file->private_data;
1652         ssize_t ret;
1653         unsigned long flags;
1654         int cnt, count_fr, cnt_by;
1655         unsigned copied = 0;
1656
1657         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1658                   printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1659
1660         VALIDATE_STATE(s);
1661         if (ppos != &file->f_pos)
1662                 return -ESPIPE;
1663         if (s->dma_adc.mapped)
1664                 return -ENXIO;
1665         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1666                 return ret;
1667         if (!access_ok(VERIFY_WRITE, buffer, count))
1668                 return -EFAULT;
1669         ret = 0;
1670 //
1671 // "count" is the amount of bytes to read (from app), is decremented each loop
1672 //      by the amount of bytes that have been returned to the user buffer.
1673 // "cnt" is the running total of each read from the buffer (changes each loop)
1674 // "buffer" points to the app's buffer
1675 // "ret" keeps a running total of the amount of bytes that have been copied
1676 //      to the user buffer.
1677 // "copied" is the total bytes copied into the user buffer for each loop.
1678 //
1679         while (count > 0) {
1680                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1681                         "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1682                                 count, s->dma_adc.count,
1683                                 s->dma_adc.swptr, s->dma_adc.hwptr));
1684                 spin_lock_irqsave(&s->lock, flags);
1685
1686                 /* cnt will be the number of available samples (16-bit
1687                    stereo); it starts out as the maxmimum consequetive
1688                    samples */
1689                 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1690                 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1691
1692                 // dma_adc.count is the current total bytes that have not been read.
1693                 // if the amount of unread bytes from the current sw pointer to the
1694                 // end of the buffer is greater than the current total bytes that
1695                 // have not been read, then set the "cnt" (unread bytes) to the
1696                 // amount of unread bytes.
1697
1698                 if (count_fr < cnt)
1699                         cnt = count_fr;
1700                 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1701                 spin_unlock_irqrestore(&s->lock, flags);
1702                 //
1703                 // if we are converting from 8/16 then we need to copy
1704                 // twice the number of 16 bit bytes then 8 bit bytes.
1705                 //
1706                 if (s->conversion) {
1707                         if (cnt_by > (count * 2)) {
1708                                 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1709                                 cnt_by = count * 2;
1710                         }
1711                 } else {
1712                         if (cnt_by > count) {
1713                                 cnt = count / FRAME_SAMPLE_BYTES;
1714                                 cnt_by = count;
1715                         }
1716                 }
1717                 //
1718                 // "cnt" NOW is the smaller of the amount that will be read,
1719                 // and the amount that is requested in this read (or partial).
1720                 // if there are no bytes in the buffer to read, then start the
1721                 // ADC and wait for the interrupt handler to wake us up.
1722                 //
1723                 if (cnt <= 0) {
1724
1725                         // start up the dma engine and then continue back to the top of
1726                         // the loop when wake up occurs.
1727                         start_adc(s);
1728                         if (file->f_flags & O_NONBLOCK)
1729                                 return ret ? ret : -EAGAIN;
1730                         interruptible_sleep_on(&s->dma_adc.wait);
1731                         if (signal_pending(current))
1732                                 return ret ? ret : -ERESTARTSYS;
1733                         continue;
1734                 }
1735                 // there are bytes in the buffer to read.
1736                 // copy from the hw buffer over to the user buffer.
1737                 // user buffer is designated by "buffer"
1738                 // virtual address to copy from is dma_buf+swptr
1739                 // the "cnt" is the number of bytes to read.
1740
1741                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1742                         "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1743                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1744                          " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1745                                  s->dma_adc.sbufsz, s->dma_adc.count,
1746                                  (unsigned) buffer, ret));
1747
1748                 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1749                         return ret ? ret : -EFAULT;
1750                 copied = cnt_by;
1751
1752                 /* Return the descriptors */
1753                 spin_lock_irqsave(&s->lock, flags);
1754                 CS_DBGOUT(CS_FUNCTION, 2,
1755                           printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1756                 s->dma_adc.count -= cnt_by;
1757                 s->dma_adc.sb_swptr += cnt * 2;
1758                 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1759                         s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1760                 spin_unlock_irqrestore(&s->lock, flags);
1761                 count -= copied;
1762                 buffer += copied;
1763                 ret += copied;
1764                 start_adc(s);
1765         }
1766         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1767                   printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1768         return ret;
1769 }
1770
1771
1772 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1773                             size_t count, loff_t * ppos)
1774 {
1775         struct cs4297a_state *s =
1776             (struct cs4297a_state *) file->private_data;
1777         ssize_t ret;
1778         unsigned long flags;
1779         unsigned swptr, hwptr;
1780         int cnt;
1781
1782         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1783                   printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1784                          count));
1785         VALIDATE_STATE(s);
1786
1787         if (ppos != &file->f_pos)
1788                 return -ESPIPE;
1789         if (s->dma_dac.mapped)
1790                 return -ENXIO;
1791         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1792                 return ret;
1793         if (!access_ok(VERIFY_READ, buffer, count))
1794                 return -EFAULT;
1795         ret = 0;
1796         while (count > 0) {
1797                 serdma_t *d = &s->dma_dac;
1798                 int copy_cnt;
1799                 u32 *s_tmpl;
1800                 u32 *t_tmpl;
1801                 u32 left, right;
1802                 /* XXXKW check system endian here ... */
1803                 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1804
1805                 /* XXXXXX this is broken for BLOAT_FACTOR */
1806                 spin_lock_irqsave(&s->lock, flags);
1807                 if (d->count < 0) {
1808                         d->count = 0;
1809                         d->swptr = d->hwptr;
1810                 }
1811                 if (d->underrun) {
1812                         d->underrun = 0;
1813                         hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1814                                              d->descrtab_phys) / sizeof(serdma_descr_t));
1815                         d->swptr = d->hwptr = hwptr;
1816                 }
1817                 swptr = d->swptr;
1818                 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1819                 /* Will this write fill up the buffer? */
1820                 if (d->count + cnt > d->sbufsz)
1821                         cnt = d->sbufsz - d->count;
1822                 spin_unlock_irqrestore(&s->lock, flags);
1823                 if (cnt > count)
1824                         cnt = count;
1825                 if (cnt <= 0) {
1826                         start_dac(s);
1827                         if (file->f_flags & O_NONBLOCK)
1828                                 return ret ? ret : -EAGAIN;
1829                         interruptible_sleep_on(&d->wait);
1830                         if (signal_pending(current))
1831                                 return ret ? ret : -ERESTARTSYS;
1832                         continue;
1833                 }
1834                 if (copy_from_user(d->sample_buf, buffer, cnt))
1835                         return ret ? ret : -EFAULT;
1836
1837                 copy_cnt = cnt;
1838                 s_tmpl = (u32 *)d->sample_buf;
1839                 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1840
1841                 /* XXXKW assuming 16-bit stereo! */
1842                 do {
1843                         t_tmpl[0] = 0x98000000;
1844                         left = s_tmpl[0] >> 16;
1845                         if (left & 0x8000)
1846                                 left |= 0xf0000;
1847                         right = s_tmpl[0] & 0xffff;
1848                         if (right & 0x8000)
1849                                 right |= 0xf0000;
1850                         if (swap) {
1851                           t_tmpl[1] = left & 0xff;
1852                           t_tmpl[2] = ((left & 0xff00) << 16) | ((right & 0xff) << 12) |
1853                               ((right & 0xff00) >> 4);
1854                         } else {
1855                           t_tmpl[1] = left >> 8;
1856                           t_tmpl[2] = ((left & 0xff) << 24) | (right << 4);
1857                         }
1858                         s_tmpl++;
1859                         t_tmpl += 8;
1860                         copy_cnt -= 4;
1861                 } while (copy_cnt);
1862
1863                 /* Mux in any pending read/write accesses */
1864                 if (s->reg_request) {
1865                         *(u64 *)(d->dma_buf + (swptr * 4)) |= s->reg_request;
1866                         s->reg_request = 0;
1867                         wake_up(&s->dma_dac.reg_wait);
1868                 }
1869
1870                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1871                           printk(KERN_INFO
1872                                  "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1873
1874                 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1875                 out64(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1876                 spin_lock_irqsave(&s->lock, flags);
1877                 d->swptr = swptr;
1878                 d->count += cnt;
1879                 d->endcleared = 0;
1880                 spin_unlock_irqrestore(&s->lock, flags);
1881                 count -= cnt;
1882                 buffer += cnt;
1883                 ret += cnt;
1884                 start_dac(s);
1885         }
1886         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1887                   printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1888         return ret;
1889 }
1890
1891
1892 static unsigned int cs4297a_poll(struct file *file,
1893                                 struct poll_table_struct *wait)
1894 {
1895         struct cs4297a_state *s =
1896             (struct cs4297a_state *) file->private_data;
1897         unsigned long flags;
1898         unsigned int mask = 0;
1899
1900         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1901                   printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1902         VALIDATE_STATE(s);
1903         if (file->f_mode & FMODE_WRITE) {
1904                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1905                           printk(KERN_INFO
1906                                  "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1907                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1908                         return 0;
1909                 poll_wait(file, &s->dma_dac.wait, wait);
1910         }
1911         if (file->f_mode & FMODE_READ) {
1912                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1913                           printk(KERN_INFO
1914                                  "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1915                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1916                         return 0;
1917                 poll_wait(file, &s->dma_adc.wait, wait);
1918         }
1919         spin_lock_irqsave(&s->lock, flags);
1920         cs4297a_update_ptr(s,CS_FALSE);
1921         if (file->f_mode & FMODE_WRITE) {
1922                 if (s->dma_dac.mapped) {
1923                         if (s->dma_dac.count >=
1924                             (signed) s->dma_dac.fragsize) {
1925                                 if (s->dma_dac.wakeup)
1926                                         mask |= POLLOUT | POLLWRNORM;
1927                                 else
1928                                         mask = 0;
1929                                 s->dma_dac.wakeup = 0;
1930                         }
1931                 } else {
1932                         if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1933                                 mask |= POLLOUT | POLLWRNORM;
1934                 }
1935         } else if (file->f_mode & FMODE_READ) {
1936                 if (s->dma_adc.mapped) {
1937                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1938                                 mask |= POLLIN | POLLRDNORM;
1939                 } else {
1940                         if (s->dma_adc.count > 0)
1941                                 mask |= POLLIN | POLLRDNORM;
1942                 }
1943         }
1944         spin_unlock_irqrestore(&s->lock, flags);
1945         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1946                   printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1947                          mask));
1948         return mask;
1949 }
1950
1951
1952 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1953 {
1954         /* XXXKW currently no mmap support */
1955         return -EINVAL;
1956         return 0;
1957 }
1958
1959
1960 static int cs4297a_ioctl(struct inode *inode, struct file *file,
1961                         unsigned int cmd, unsigned long arg)
1962 {
1963         struct cs4297a_state *s =
1964             (struct cs4297a_state *) file->private_data;
1965         unsigned long flags;
1966         audio_buf_info abinfo;
1967         count_info cinfo;
1968         int val, mapped, ret;
1969
1970         CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1971                  "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1972                          (unsigned) file, cmd));
1973 #if CSDEBUG
1974         cs_printioctl(cmd);
1975 #endif
1976         VALIDATE_STATE(s);
1977         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1978             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1979         switch (cmd) {
1980         case OSS_GETVERSION:
1981                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1982                         "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1983                                  SOUND_VERSION));
1984                 return put_user(SOUND_VERSION, (int *) arg);
1985
1986         case SNDCTL_DSP_SYNC:
1987                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1988                          "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1989                 if (file->f_mode & FMODE_WRITE)
1990                         return drain_dac(s,
1991                                          0 /*file->f_flags & O_NONBLOCK */
1992                                          );
1993                 return 0;
1994
1995         case SNDCTL_DSP_SETDUPLEX:
1996                 return 0;
1997
1998         case SNDCTL_DSP_GETCAPS:
1999                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
2000                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
2001                                 (int *) arg);
2002
2003         case SNDCTL_DSP_RESET:
2004                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2005                          "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
2006                 if (file->f_mode & FMODE_WRITE) {
2007                         stop_dac(s);
2008                         synchronize_irq();
2009                         s->dma_dac.count = s->dma_dac.total_bytes =
2010                                 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2011                         s->dma_dac.swptr = s->dma_dac.hwptr =
2012                                 (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2013                                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2014                 }
2015                 if (file->f_mode & FMODE_READ) {
2016                         stop_adc(s);
2017                         synchronize_irq();
2018                         s->dma_adc.count = s->dma_adc.total_bytes =
2019                                 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2020                         s->dma_adc.swptr = s->dma_adc.hwptr =
2021                                 (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2022                                        s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2023                 }
2024                 return 0;
2025
2026         case SNDCTL_DSP_SPEED:
2027                 if (get_user(val, (int *) arg))
2028                         return -EFAULT;
2029                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2030                          "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2031                 val = 48000;
2032                 return put_user(val, (int *) arg);
2033
2034         case SNDCTL_DSP_STEREO:
2035                 if (get_user(val, (int *) arg))
2036                         return -EFAULT;
2037                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2038                          "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2039                 if (file->f_mode & FMODE_READ) {
2040                         stop_adc(s);
2041                         s->dma_adc.ready = 0;
2042                         s->prop_adc.channels = val ? 2 : 1;
2043                 }
2044                 if (file->f_mode & FMODE_WRITE) {
2045                         stop_dac(s);
2046                         s->dma_dac.ready = 0;
2047                         s->prop_dac.channels = val ? 2 : 1;
2048                 }
2049                 return 0;
2050
2051         case SNDCTL_DSP_CHANNELS:
2052                 if (get_user(val, (int *) arg))
2053                         return -EFAULT;
2054                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2055                          "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2056                                  val));
2057                 if (val != 0) {
2058                         if (file->f_mode & FMODE_READ) {
2059                                 stop_adc(s);
2060                                 s->dma_adc.ready = 0;
2061                                 if (val >= 2)
2062                                         s->prop_adc.channels = 2;
2063                                 else
2064                                         s->prop_adc.channels = 1;
2065                         }
2066                         if (file->f_mode & FMODE_WRITE) {
2067                                 stop_dac(s);
2068                                 s->dma_dac.ready = 0;
2069                                 if (val >= 2)
2070                                         s->prop_dac.channels = 2;
2071                                 else
2072                                         s->prop_dac.channels = 1;
2073                         }
2074                 }
2075
2076                 if (file->f_mode & FMODE_WRITE)
2077                         val = s->prop_dac.channels;
2078                 else if (file->f_mode & FMODE_READ)
2079                         val = s->prop_adc.channels;
2080
2081                 return put_user(val, (int *) arg);
2082
2083         case SNDCTL_DSP_GETFMTS:        // Returns a mask
2084                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2085                         "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2086                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2087                                  AFMT_U8));
2088                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2089                                 AFMT_U8, (int *) arg);
2090
2091         case SNDCTL_DSP_SETFMT:
2092                 if (get_user(val, (int *) arg))
2093                         return -EFAULT;
2094                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2095                          "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2096                                  val));
2097                 if (val != AFMT_QUERY) {
2098                         if (file->f_mode & FMODE_READ) {
2099                                 stop_adc(s);
2100                                 s->dma_adc.ready = 0;
2101                                 if (val != AFMT_S16_LE
2102                                     && val != AFMT_U16_LE && val != AFMT_S8
2103                                     && val != AFMT_U8)
2104                                         val = AFMT_U8;
2105                                 s->prop_adc.fmt = val;
2106                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2107                         }
2108                         if (file->f_mode & FMODE_WRITE) {
2109                                 stop_dac(s);
2110                                 s->dma_dac.ready = 0;
2111                                 if (val != AFMT_S16_LE
2112                                     && val != AFMT_U16_LE && val != AFMT_S8
2113                                     && val != AFMT_U8)
2114                                         val = AFMT_U8;
2115                                 s->prop_dac.fmt = val;
2116                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2117                         }
2118                 } else {
2119                         if (file->f_mode & FMODE_WRITE)
2120                                 val = s->prop_dac.fmt_original;
2121                         else if (file->f_mode & FMODE_READ)
2122                                 val = s->prop_adc.fmt_original;
2123                 }
2124                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2125                   "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2126                         val));
2127                 return put_user(val, (int *) arg);
2128
2129         case SNDCTL_DSP_POST:
2130                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2131                          "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2132                 return 0;
2133
2134         case SNDCTL_DSP_GETTRIGGER:
2135                 val = 0;
2136                 if (file->f_mode & s->ena & FMODE_READ)
2137                         val |= PCM_ENABLE_INPUT;
2138                 if (file->f_mode & s->ena & FMODE_WRITE)
2139                         val |= PCM_ENABLE_OUTPUT;
2140                 return put_user(val, (int *) arg);
2141
2142         case SNDCTL_DSP_SETTRIGGER:
2143                 if (get_user(val, (int *) arg))
2144                         return -EFAULT;
2145                 if (file->f_mode & FMODE_READ) {
2146                         if (val & PCM_ENABLE_INPUT) {
2147                                 if (!s->dma_adc.ready
2148                                     && (ret = prog_dmabuf_adc(s)))
2149                                         return ret;
2150                                 start_adc(s);
2151                         } else
2152                                 stop_adc(s);
2153                 }
2154                 if (file->f_mode & FMODE_WRITE) {
2155                         if (val & PCM_ENABLE_OUTPUT) {
2156                                 if (!s->dma_dac.ready
2157                                     && (ret = prog_dmabuf_dac(s)))
2158                                         return ret;
2159                                 start_dac(s);
2160                         } else
2161                                 stop_dac(s);
2162                 }
2163                 return 0;
2164
2165         case SNDCTL_DSP_GETOSPACE:
2166                 if (!(file->f_mode & FMODE_WRITE))
2167                         return -EINVAL;
2168                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2169                         return val;
2170                 spin_lock_irqsave(&s->lock, flags);
2171                 cs4297a_update_ptr(s,CS_FALSE);
2172                 abinfo.fragsize = s->dma_dac.fragsize;
2173                 if (s->dma_dac.mapped)
2174                         abinfo.bytes = s->dma_dac.sbufsz;
2175                 else
2176                         abinfo.bytes =
2177                             s->dma_dac.sbufsz - s->dma_dac.count;
2178                 abinfo.fragstotal = s->dma_dac.numfrag;
2179                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2180                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2181                         "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2182                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2183                                 abinfo.fragments));
2184                 spin_unlock_irqrestore(&s->lock, flags);
2185                 return copy_to_user((void *) arg, &abinfo,
2186                                     sizeof(abinfo)) ? -EFAULT : 0;
2187
2188         case SNDCTL_DSP_GETISPACE:
2189                 if (!(file->f_mode & FMODE_READ))
2190                         return -EINVAL;
2191                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2192                         return val;
2193                 spin_lock_irqsave(&s->lock, flags);
2194                 cs4297a_update_ptr(s,CS_FALSE);
2195                 if (s->conversion) {
2196                         abinfo.fragsize = s->dma_adc.fragsize / 2;
2197                         abinfo.bytes = s->dma_adc.count / 2;
2198                         abinfo.fragstotal = s->dma_adc.numfrag;
2199                         abinfo.fragments =
2200                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
2201                 } else {
2202                         abinfo.fragsize = s->dma_adc.fragsize;
2203                         abinfo.bytes = s->dma_adc.count;
2204                         abinfo.fragstotal = s->dma_adc.numfrag;
2205                         abinfo.fragments =
2206                             abinfo.bytes >> s->dma_adc.fragshift;
2207                 }
2208                 spin_unlock_irqrestore(&s->lock, flags);
2209                 return copy_to_user((void *) arg, &abinfo,
2210                                     sizeof(abinfo)) ? -EFAULT : 0;
2211
2212         case SNDCTL_DSP_NONBLOCK:
2213                 file->f_flags |= O_NONBLOCK;
2214                 return 0;
2215
2216         case SNDCTL_DSP_GETODELAY:
2217                 if (!(file->f_mode & FMODE_WRITE))
2218                         return -EINVAL;
2219                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2220                         return 0;
2221                 spin_lock_irqsave(&s->lock, flags);
2222                 cs4297a_update_ptr(s,CS_FALSE);
2223                 val = s->dma_dac.count;
2224                 spin_unlock_irqrestore(&s->lock, flags);
2225                 return put_user(val, (int *) arg);
2226
2227         case SNDCTL_DSP_GETIPTR:
2228                 if (!(file->f_mode & FMODE_READ))
2229                         return -EINVAL;
2230                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2231                         return 0;
2232                 spin_lock_irqsave(&s->lock, flags);
2233                 cs4297a_update_ptr(s,CS_FALSE);
2234                 cinfo.bytes = s->dma_adc.total_bytes;
2235                 if (s->dma_adc.mapped) {
2236                         cinfo.blocks =
2237                             (cinfo.bytes >> s->dma_adc.fragshift) -
2238                             s->dma_adc.blocks;
2239                         s->dma_adc.blocks =
2240                             cinfo.bytes >> s->dma_adc.fragshift;
2241                 } else {
2242                         if (s->conversion) {
2243                                 cinfo.blocks =
2244                                     s->dma_adc.count /
2245                                     2 >> (s->dma_adc.fragshift - 1);
2246                         } else
2247                                 cinfo.blocks =
2248                                     s->dma_adc.count >> s->dma_adc.
2249                                     fragshift;
2250                 }
2251                 if (s->conversion)
2252                         cinfo.ptr = s->dma_adc.hwptr / 2;
2253                 else
2254                         cinfo.ptr = s->dma_adc.hwptr;
2255                 if (s->dma_adc.mapped)
2256                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
2257                 spin_unlock_irqrestore(&s->lock, flags);
2258                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2259
2260         case SNDCTL_DSP_GETOPTR:
2261                 if (!(file->f_mode & FMODE_WRITE))
2262                         return -EINVAL;
2263                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2264                         return 0;
2265                 spin_lock_irqsave(&s->lock, flags);
2266                 cs4297a_update_ptr(s,CS_FALSE);
2267                 cinfo.bytes = s->dma_dac.total_bytes;
2268                 if (s->dma_dac.mapped) {
2269                         cinfo.blocks =
2270                             (cinfo.bytes >> s->dma_dac.fragshift) -
2271                             s->dma_dac.blocks;
2272                         s->dma_dac.blocks =
2273                             cinfo.bytes >> s->dma_dac.fragshift;
2274                 } else {
2275                         cinfo.blocks =
2276                             s->dma_dac.count >> s->dma_dac.fragshift;
2277                 }
2278                 cinfo.ptr = s->dma_dac.hwptr;
2279                 if (s->dma_dac.mapped)
2280                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
2281                 spin_unlock_irqrestore(&s->lock, flags);
2282                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2283
2284         case SNDCTL_DSP_GETBLKSIZE:
2285                 if (file->f_mode & FMODE_WRITE) {
2286                         if ((val = prog_dmabuf_dac(s)))
2287                                 return val;
2288                         return put_user(s->dma_dac.fragsize, (int *) arg);
2289                 }
2290                 if ((val = prog_dmabuf_adc(s)))
2291                         return val;
2292                 if (s->conversion)
2293                         return put_user(s->dma_adc.fragsize / 2,
2294                                         (int *) arg);
2295                 else
2296                         return put_user(s->dma_adc.fragsize, (int *) arg);
2297
2298         case SNDCTL_DSP_SETFRAGMENT:
2299                 if (get_user(val, (int *) arg))
2300                         return -EFAULT;
2301                 return 0;       // Say OK, but do nothing.
2302
2303         case SNDCTL_DSP_SUBDIVIDE:
2304                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2305                     || (file->f_mode & FMODE_WRITE
2306                         && s->dma_dac.subdivision)) return -EINVAL;
2307                 if (get_user(val, (int *) arg))
2308                         return -EFAULT;
2309                 if (val != 1 && val != 2 && val != 4)
2310                         return -EINVAL;
2311                 if (file->f_mode & FMODE_READ)
2312                         s->dma_adc.subdivision = val;
2313                 else if (file->f_mode & FMODE_WRITE)
2314                         s->dma_dac.subdivision = val;
2315                 return 0;
2316
2317         case SOUND_PCM_READ_RATE:
2318                 if (file->f_mode & FMODE_READ)
2319                         return put_user(s->prop_adc.rate, (int *) arg);
2320                 else if (file->f_mode & FMODE_WRITE)
2321                         return put_user(s->prop_dac.rate, (int *) arg);
2322
2323         case SOUND_PCM_READ_CHANNELS:
2324                 if (file->f_mode & FMODE_READ)
2325                         return put_user(s->prop_adc.channels, (int *) arg);
2326                 else if (file->f_mode & FMODE_WRITE)
2327                         return put_user(s->prop_dac.channels, (int *) arg);
2328
2329         case SOUND_PCM_READ_BITS:
2330                 if (file->f_mode & FMODE_READ)
2331                         return
2332                             put_user(
2333                                      (s->prop_adc.
2334                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2335                                      (int *) arg);
2336                 else if (file->f_mode & FMODE_WRITE)
2337                         return
2338                             put_user(
2339                                      (s->prop_dac.
2340                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2341                                      (int *) arg);
2342
2343         case SOUND_PCM_WRITE_FILTER:
2344         case SNDCTL_DSP_SETSYNCRO:
2345         case SOUND_PCM_READ_FILTER:
2346                 return -EINVAL;
2347         }
2348         return mixer_ioctl(s, cmd, arg);
2349 }
2350
2351
2352 static int cs4297a_release(struct inode *inode, struct file *file)
2353 {
2354         struct cs4297a_state *s =
2355             (struct cs4297a_state *) file->private_data;
2356
2357         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2358                  "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2359                          (unsigned) inode, (unsigned) file, file->f_mode));
2360         VALIDATE_STATE(s);
2361
2362         if (file->f_mode & FMODE_WRITE) {
2363                 drain_dac(s, file->f_flags & O_NONBLOCK);
2364                 down(&s->open_sem_dac);
2365                 stop_dac(s);
2366                 dealloc_dmabuf(s, &s->dma_dac);
2367                 s->open_mode &= ~FMODE_WRITE;
2368                 up(&s->open_sem_dac);
2369                 wake_up(&s->open_wait_dac);
2370         }
2371         if (file->f_mode & FMODE_READ) {
2372                 drain_adc(s, file->f_flags & O_NONBLOCK);
2373                 down(&s->open_sem_adc);
2374                 stop_adc(s);
2375                 dealloc_dmabuf(s, &s->dma_adc);
2376                 s->open_mode &= ~FMODE_READ;
2377                 up(&s->open_sem_adc);
2378                 wake_up(&s->open_wait_adc);
2379         }
2380         return 0;
2381 }
2382
2383 static int cs4297a_open(struct inode *inode, struct file *file)
2384 {
2385         int minor = iminor(inode);
2386         struct cs4297a_state *s=NULL;
2387         struct list_head *entry;
2388
2389         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2390                 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2391                         (unsigned) inode, (unsigned) file, file->f_mode));
2392         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2393                 "cs4297a: status = %08x\n", (int)in64(SS_CSR(R_SER_STATUS_DEBUG))));
2394
2395         list_for_each(entry, &cs4297a_devs)
2396         {
2397                 s = list_entry(entry, struct cs4297a_state, list);
2398
2399                 if (!((s->dev_audio ^ minor) & ~0xf))
2400                         break;
2401         }
2402         if (entry == &cs4297a_devs)
2403                 return -ENODEV;
2404         if (!s) {
2405                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2406                         "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2407                 return -ENODEV;
2408         }
2409         VALIDATE_STATE(s);
2410         file->private_data = s;
2411
2412         // wait for device to become free
2413         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2414                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2415                          "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2416                 return -ENODEV;
2417         }
2418         if (file->f_mode & FMODE_WRITE) {
2419                 if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2420                         printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2421                         while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2422                                 ;
2423                 }
2424
2425                 down(&s->open_sem_dac);
2426                 while (s->open_mode & FMODE_WRITE) {
2427                         if (file->f_flags & O_NONBLOCK) {
2428                                 up(&s->open_sem_dac);
2429                                 return -EBUSY;
2430                         }
2431                         up(&s->open_sem_dac);
2432                         interruptible_sleep_on(&s->open_wait_dac);
2433
2434                         if (signal_pending(current)) {
2435                                 printk("open - sig pending\n");
2436                                 return -ERESTARTSYS;
2437                         }
2438                         down(&s->open_sem_dac);
2439                 }
2440         }
2441         if (file->f_mode & FMODE_READ) {
2442                 down(&s->open_sem_adc);
2443                 while (s->open_mode & FMODE_READ) {
2444                         if (file->f_flags & O_NONBLOCK) {
2445                                 up(&s->open_sem_adc);
2446                                 return -EBUSY;
2447                         }
2448                         up(&s->open_sem_adc);
2449                         interruptible_sleep_on(&s->open_wait_adc);
2450
2451                         if (signal_pending(current)) {
2452                                 printk("open - sig pending\n");
2453                                 return -ERESTARTSYS;
2454                         }
2455                         down(&s->open_sem_adc);
2456                 }
2457         }
2458         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2459         if (file->f_mode & FMODE_READ) {
2460                 s->prop_adc.fmt = AFMT_S16_BE;
2461                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2462                 s->prop_adc.channels = 2;
2463                 s->prop_adc.rate = 48000;
2464                 s->conversion = 0;
2465                 s->ena &= ~FMODE_READ;
2466                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2467                     s->dma_adc.subdivision = 0;
2468                 up(&s->open_sem_adc);
2469
2470                 if (prog_dmabuf_adc(s)) {
2471                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2472                                 "cs4297a: adc Program dmabufs failed.\n"));
2473                         cs4297a_release(inode, file);
2474                         return -ENOMEM;
2475                 }
2476         }
2477         if (file->f_mode & FMODE_WRITE) {
2478                 s->prop_dac.fmt = AFMT_S16_BE;
2479                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2480                 s->prop_dac.channels = 2;
2481                 s->prop_dac.rate = 48000;
2482                 s->conversion = 0;
2483                 s->ena &= ~FMODE_WRITE;
2484                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2485                     s->dma_dac.subdivision = 0;
2486                 up(&s->open_sem_dac);
2487
2488                 if (prog_dmabuf_dac(s)) {
2489                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2490                                 "cs4297a: dac Program dmabufs failed.\n"));
2491                         cs4297a_release(inode, file);
2492                         return -ENOMEM;
2493                 }
2494         }
2495         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2496                   printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2497         return 0;
2498 }
2499
2500
2501 // ******************************************************************************************
2502 //   Wave (audio) file operations struct.
2503 // ******************************************************************************************
2504 static /*const */ struct file_operations cs4297a_audio_fops = {
2505         .owner          = THIS_MODULE,
2506         .llseek         = cs4297a_llseek,
2507         .read           = cs4297a_read,
2508         .write          = cs4297a_write,
2509         .poll           = cs4297a_poll,
2510         .ioctl          = cs4297a_ioctl,
2511         .mmap           = cs4297a_mmap,
2512         .open           = cs4297a_open,
2513         .release        = cs4297a_release,
2514 };
2515
2516 static irqreturn_t cs4297a_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2517 {
2518         struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2519         u32 status;
2520
2521         status = in64(SS_CSR(R_SER_STATUS_DEBUG));
2522
2523         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2524                  "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2525
2526 #if 0
2527         /* XXXKW what check *should* be done here? */
2528         if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2529                 status = in64(SS_CSR(R_SER_STATUS));
2530                 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2531                 return IRQ_HANDLED;
2532         }
2533 #endif
2534
2535         if (status & M_SYNCSER_RX_SYNC_ERR) {
2536                 status = in64(SS_CSR(R_SER_STATUS));
2537                 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2538                 return IRQ_HANDLED;
2539         }
2540
2541         if (status & M_SYNCSER_RX_OVERRUN) {
2542                 int newptr, i;
2543                 s->stats.rx_ovrrn++;
2544                 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2545
2546                 /* Fix things up: get the receive descriptor pool
2547                    clean and give them back to the hardware */
2548                 while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2549                         ;
2550                 newptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2551                                      s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2552                 for (i=0; i<DMA_DESCR; i++) {
2553                         s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2554                 }
2555                 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2556                 s->dma_adc.count = 0;
2557                 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2558                 out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2559         }
2560
2561         spin_lock(&s->lock);
2562         cs4297a_update_ptr(s,CS_TRUE);
2563         spin_unlock(&s->lock);
2564
2565         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2566                   "cs4297a: cs4297a_interrupt()-\n"));
2567         return IRQ_HANDLED;
2568 }
2569
2570 static struct initvol {
2571         int mixch;
2572         int vol;
2573 } initvol[] __initdata = {
2574
2575         {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2576         {SOUND_MIXER_WRITE_PCM, 0x4040},
2577         {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2578         {SOUND_MIXER_WRITE_CD, 0x4040},
2579         {SOUND_MIXER_WRITE_LINE, 0x4040},
2580         {SOUND_MIXER_WRITE_LINE1, 0x4040},
2581         {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2582         {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2583         {SOUND_MIXER_WRITE_MIC, 0x0000}
2584 };
2585
2586 static int __init cs4297a_init(void)
2587 {
2588         struct cs4297a_state *s;
2589         u64 cfg;
2590         u32 pwr, id;
2591         mm_segment_t fs;
2592         int rval, mdio_val;
2593
2594         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2595                 "cs4297a: cs4297a_init_module()+ \n"));
2596
2597         mdio_val = in64(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2598                 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2599
2600         /* Check syscfg for synchronous serial on port 1 */
2601         cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG);
2602         if (!(cfg & M_SYS_SER1_ENABLE)) {
2603                 out64(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2604                 cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG);
2605                 if (!(cfg & M_SYS_SER1_ENABLE)) {
2606                   printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2607                   return -1;
2608                 }
2609
2610                 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2611
2612                 /* Force the codec (on SWARM) to reset by clearing
2613                    GENO, preserving MDIO (no effect on CSWARM) */
2614                 out64(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2615                 udelay(10);
2616         }
2617
2618         /* Now set GENO */
2619         out64(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2620         /* Give the codec some time to finish resetting (start the bit clock) */
2621         udelay(100);
2622
2623         if (!(s = kmalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2624                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2625                       "cs4297a: probe() no memory for state struct.\n"));
2626                 return -1;
2627         }
2628         memset(s, 0, sizeof(struct cs4297a_state));
2629         s->magic = CS4297a_MAGIC;
2630         init_waitqueue_head(&s->dma_adc.wait);
2631         init_waitqueue_head(&s->dma_dac.wait);
2632         init_waitqueue_head(&s->dma_adc.reg_wait);
2633         init_waitqueue_head(&s->dma_dac.reg_wait);
2634         init_waitqueue_head(&s->open_wait);
2635         init_waitqueue_head(&s->open_wait_adc);
2636         init_waitqueue_head(&s->open_wait_dac);
2637         init_MUTEX(&s->open_sem_adc);
2638         init_MUTEX(&s->open_sem_dac);
2639         spin_lock_init(&s->lock);
2640
2641         s->irq = K_INT_SER_1;
2642
2643         if (request_irq
2644             (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2645                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2646                           printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2647                 goto err_irq;
2648         }
2649         if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2650             0) {
2651                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2652                          "cs4297a: probe() register_sound_dsp() failed.\n"));
2653                 goto err_dev1;
2654         }
2655         if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2656             0) {
2657                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2658                          "cs4297a: probe() register_sound_mixer() failed.\n"));
2659                 goto err_dev2;
2660         }
2661
2662         if (ser_init(s) || dma_init(s)) {
2663                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2664                          "cs4297a: ser_init failed.\n"));
2665                 goto err_dev3;
2666         }
2667
2668         do {
2669                 udelay(4000);
2670                 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2671         } while (!rval && (pwr != 0xf));
2672
2673         if (!rval) {
2674                 fs = get_fs();
2675                 set_fs(KERNEL_DS);
2676 #if 0
2677                 val = SOUND_MASK_LINE;
2678                 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2679                 for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
2680                         val = initvol[i].vol;
2681                         mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2682                 }
2683 //                cs4297a_write_ac97(s, 0x18, 0x0808);
2684 #else
2685                 //                cs4297a_write_ac97(s, 0x5e, 0x180);
2686                 cs4297a_write_ac97(s, 0x02, 0x0808);
2687                 cs4297a_write_ac97(s, 0x18, 0x0808);
2688 #endif
2689                 set_fs(fs);
2690
2691                 list_add(&s->list, &cs4297a_devs);
2692
2693                 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2694
2695                 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2696
2697                 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2698                           printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2699
2700                 return 0;
2701         }
2702
2703  err_dev3:
2704         unregister_sound_mixer(s->dev_mixer);
2705  err_dev2:
2706         unregister_sound_dsp(s->dev_audio);
2707  err_dev1:
2708         free_irq(s->irq, s);
2709  err_irq:
2710         kfree(s);
2711
2712         printk(KERN_INFO "cs4297a: initialization failed\n");
2713
2714         return -1;
2715 }
2716
2717 static void __exit cs4297a_cleanup(void)
2718 {
2719         /*
2720           XXXKW
2721            disable_irq, free_irq
2722            drain DMA queue
2723            disable DMA
2724            disable TX/RX
2725            free memory
2726         */
2727         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2728                   printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2729 }
2730
2731 // ---------------------------------------------------------------------
2732
2733 EXPORT_NO_SYMBOLS;
2734
2735 MODULE_AUTHOR("Kip Walker, kwalker@broadcom.com");
2736 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2737
2738 // ---------------------------------------------------------------------
2739
2740 module_init(cs4297a_init);
2741 module_exit(cs4297a_cleanup);