sound/pci/au88x0/au88x0_core.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify
   3  *  it under the terms of the GNU General Public License as published by
   4  *  the Free Software Foundation; either version 2 of the License, or
   5  *  (at your option) any later version.
   6  *
   7  *  This program is distributed in the hope that it will be useful,
   8  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *  GNU Library General Public License for more details.
  11  *
  12  *  You should have received a copy of the GNU General Public License
  13  *  along with this program; if not, write to the Free Software
  14  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  15  */
  16
  17 /*
  18     Vortex core low level functions.
  19
  20  Author: Manuel Jander (mjander@users.sourceforge.cl)
  21  These functions are mainly the result of translations made
  22  from the original disassembly of the au88x0 binary drivers,
  23  written by Aureal before they went down.
  24  Many thanks to the Jeff Muizelar, Kester Maddock, and whoever
  25  contributed to the OpenVortex project.
  26  The author of this file, put the few available pieces together
  27  and translated the rest of the riddle (Mix, Src and connection stuff).
  28  Some things are still to be discovered, and their meanings are unclear.
  29
  30  Some of these functions aren't intended to be really used, rather
  31  to help to understand how does the AU88X0 chips work. Keep them in, because
  32  they could be used somewhere in the future.
  33
  34  This code hasn't been tested or proof read thoroughly. If you wanna help,
  35  take a look at the AU88X0 assembly and check if this matches.
  36  Functions tested ok so far are (they show the desired effect
  37  at least):
  38    vortex_routes(); (1 bug fixed).
  39    vortex_adb_addroute();
  40    vortex_adb_addroutes();
  41    vortex_connect_codecplay();
  42    vortex_src_flushbuffers();
  43    vortex_adbdma_setmode();  note: still some unknown arguments!
  44    vortex_adbdma_startfifo();
  45    vortex_adbdma_stopfifo();
  46    vortex_fifo_setadbctrl(); note: still some unknown arguments!
  47    vortex_mix_setinputvolumebyte();
  48    vortex_mix_enableinput();
  49    vortex_mixer_addWTD(); (fixed)
  50    vortex_connection_adbdma_src_src();
  51    vortex_connection_adbdma_src();
  52    vortex_src_change_convratio();
  53    vortex_src_addWTD(); (fixed)
  54
  55  History:
  56
  57  01-03-2003 First revision.
  58  01-21-2003 Some bug fixes.
  59  17-02-2003 many bugfixes after a big versioning mess.
  60  18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy !
  61                          (2 hours later...) I cant believe it! Im really lucky today.
  62                          Now the SRC is working too! Yeah! XMMS works !
  63  20-02-2003 First steps into the ALSA world.
  64  28-02-2003 As my birthday present, i discovered how the DMA buffer pages really
  65             work :-). It was all wrong.
  66  12-03-2003 ALSA driver starts working (2 channels).
  67  16-03-2003 More srcblock_setupchannel discoveries.
  68  12-04-2003 AU8830 playback support. Recording in the works.
  69  17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording
  70                         works now, but chipn' dale effect is still there.
  71  16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely
  72             into au88x0_pcm.c .
  73  06-06-2003 Buffer shifter bugfix. Mixer volume fix.
  74  07-12-2003 A3D routing finally fixed. Believed to be OK.
  75
  76 */
  77
  78 #include "au88x0.h"
  79 #include "au88x0_a3d.h"
  80 #include <linux/delay.h>
  81
  82 /*  MIXER (CAsp4Mix.s and CAsp4Mixer.s) */
  83
  84 // FIXME: get rid of this.
  85 static int mchannels[NR_MIXIN];
  86 static int rampchs[NR_MIXIN];
  87
  88 static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
  89 {
  90         hwwrite(vortex->mmio, VORTEX_MIXER_SR,
  91                 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
  92 }
  93 static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
  94 {
  95         hwwrite(vortex->mmio, VORTEX_MIXER_SR,
  96                 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
  97 }
  98
  99 #if 0
 100 static void
 101 vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
 102                          unsigned char channel)
 103 {
 104         hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
 105                 0x80);
 106         hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
 107                 0x80);
 108 }
 109
 110 static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
 111 {
 112         int a;
 113         a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
 114         //FP2LinearFrac(a);
 115         return (a);
 116 }
 117
 118 static int
 119 vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
 120                           int channel, int *vol)
 121 {
 122         int a;
 123         if (!(mchannels[mix] & (1 << channel)))
 124                 return 0;
 125         a = hwread(vortex->mmio,
 126                    VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
 127         /*
 128            if (rampchs[mix] == 0)
 129            a = FP2LinearFrac(a);
 130            else
 131            a = FP2LinearFracWT(a);
 132          */
 133         *vol = a;
 134         return (0);
 135 }
 136
 137 static unsigned int vortex_mix_boost6db(unsigned char vol)
 138 {
 139         return (vol + 8);       /* WOW! what a complex function! */
 140 }
 141
 142 static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
 143 {
 144         int ch;
 145         char a;
 146         // This function is intended for ramping down only (see vortex_disableinput()).
 147         for (ch = 0; ch < 0x20; ch++) {
 148                 if (((1 << ch) & rampchs[mix]) == 0)
 149                         continue;
 150                 a = hwread(vortex->mmio,
 151                            VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
 152                 if (a > -126) {
 153                         a -= 2;
 154                         hwwrite(vortex->mmio,
 155                                 VORTEX_MIX_INVOL_A +
 156                                 (((mix << 5) + ch) << 2), a);
 157                         hwwrite(vortex->mmio,
 158                                 VORTEX_MIX_INVOL_B +
 159                                 (((mix << 5) + ch) << 2), a);
 160                 } else
 161                         vortex_mix_killinput(vortex, mix, ch);
 162         }
 163 }
 164
 165 static int
 166 vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
 167 {
 168         int addr, temp;
 169         if (mixin >= 0)
 170                 addr = mixin;
 171         else
 172                 addr = mixin + 3;
 173         addr = ((mix << 3) + (addr >> 2)) << 2;
 174         temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
 175         return ((temp >> (mixin & 3)) & 1);
 176 }
 177 #endif
 178 static void
 179 vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
 180                          unsigned char vol)
 181 {
 182         int temp;
 183         hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
 184         if (1) {                /*if (this_10) */
 185                 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
 186                 if ((temp != 0x80) || (vol == 0x80))
 187                         return;
 188         }
 189         hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
 190 }
 191
 192 static void
 193 vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
 194                               int mixin, unsigned char vol)
 195 {
 196         int temp;
 197
 198         hwwrite(vortex->mmio,
 199                 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
 200         if (1) {                /* this_10, initialized to 1. */
 201                 temp =
 202                     hwread(vortex->mmio,
 203                            VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
 204                 if ((temp != 0x80) || (vol == 0x80))
 205                         return;
 206         }
 207         hwwrite(vortex->mmio,
 208                 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
 209 }
 210
 211 static void
 212 vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
 213 {
 214         int temp, addr;
 215
 216         if (mixin < 0)
 217                 addr = (mixin + 3);
 218         else
 219                 addr = mixin;
 220         addr = ((mix << 3) + (addr >> 2)) << 2;
 221         temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
 222         if (en)
 223                 temp |= (1 << (mixin & 3));
 224         else
 225                 temp &= ~(1 << (mixin & 3));
 226         /* Mute input. Astatic void crackling? */
 227         hwwrite(vortex->mmio,
 228                 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
 229         /* Looks like clear buffer. */
 230         hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
 231         hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
 232         /* Write enable bit. */
 233         hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
 234 }
 235
 236 static void
 237 vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
 238 {
 239         rampchs[mix] &= ~(1 << mixin);
 240         vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
 241         mchannels[mix] &= ~(1 << mixin);
 242         vortex_mix_setenablebit(vortex, mix, mixin, 0);
 243 }
 244
 245 static void
 246 vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
 247 {
 248         vortex_mix_killinput(vortex, mix, mixin);
 249         if ((mchannels[mix] & (1 << mixin)) == 0) {
 250                 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);        /*0x80 : mute */
 251                 mchannels[mix] |= (1 << mixin);
 252         }
 253         vortex_mix_setenablebit(vortex, mix, mixin, 1);
 254 }
 255
 256 static void
 257 vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
 258                         int ramp)
 259 {
 260         if (ramp) {
 261                 rampchs[mix] |= (1 << channel);
 262                 // Register callback.
 263                 //vortex_mix_startrampvolume(vortex);
 264                 vortex_mix_killinput(vortex, mix, channel);
 265         } else
 266                 vortex_mix_killinput(vortex, mix, channel);
 267 }
 268
 269 static int
 270 vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
 271 {
 272         int temp, lifeboat = 0, prev;
 273
 274         temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
 275         if ((temp & (1 << ch)) == 0) {
 276                 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
 277                 vortex_mixer_en_sr(vortex, ch);
 278                 return 1;
 279         }
 280         prev = VORTEX_MIXER_CHNBASE + (ch << 2);
 281         temp = hwread(vortex->mmio, prev);
 282         while (temp & 0x10) {
 283                 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
 284                 temp = hwread(vortex->mmio, prev);
 285                 //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp);
 286                 if ((++lifeboat) > 0xf) {
 287                         printk(KERN_ERR
 288                                "vortex_mixer_addWTD: lifeboat overflow\n");
 289                         return 0;
 290                 }
 291         }
 292         hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
 293         hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
 294         return 1;
 295 }
 296
 297 static int
 298 vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
 299 {
 300         int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
 301         //int esp1f=edi(while)=src, esp10=ch;
 302
 303         eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
 304         if (((1 << ch) & eax) == 0) {
 305                 printk(KERN_ERR "mix ALARM %x\n", eax);
 306                 return 0;
 307         }
 308         ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
 309         esp18 = hwread(vortex->mmio, ebp);
 310         if (esp18 & 0x10) {
 311                 ebx = (esp18 & 0xf);
 312                 if (mix == ebx) {
 313                         ebx = VORTEX_MIXER_RTBASE + (mix << 2);
 314                         edx = hwread(vortex->mmio, ebx);
 315                         //7b60
 316                         hwwrite(vortex->mmio, ebp, edx);
 317                         hwwrite(vortex->mmio, ebx, 0);
 318                 } else {
 319                         //7ad3
 320                         edx =
 321                             hwread(vortex->mmio,
 322                                    VORTEX_MIXER_RTBASE + (ebx << 2));
 323                         //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
 324                         while ((edx & 0xf) != mix) {
 325                                 if ((esi) > 0xf) {
 326                                         printk(KERN_ERR
 327                                                "vortex: mixdelWTD: error lifeboat overflow\n");
 328                                         return 0;
 329                                 }
 330                                 esp14 = ebx;
 331                                 ebx = edx & 0xf;
 332                                 ebp = ebx << 2;
 333                                 edx =
 334                                     hwread(vortex->mmio,
 335                                            VORTEX_MIXER_RTBASE + ebp);
 336                                 //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx);
 337                                 esi++;
 338                         }
 339                         //7b30
 340                         ebp = ebx << 2;
 341                         if (edx & 0x10) {       /* Delete entry in between others */
 342                                 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
 343                                 edx = hwread(vortex->mmio, ebx);
 344                                 //7b60
 345                                 hwwrite(vortex->mmio,
 346                                         VORTEX_MIXER_RTBASE + ebp, edx);
 347                                 hwwrite(vortex->mmio, ebx, 0);
 348                                 //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
 349                         } else {        /* Delete last entry */
 350                                 //7b83
 351                                 if (esp14 == -1)
 352                                         hwwrite(vortex->mmio,
 353                                                 VORTEX_MIXER_CHNBASE +
 354                                                 (ch << 2), esp18 & 0xef);
 355                                 else {
 356                                         ebx = (0xffffffe0 & edx) | (0xf & ebx);
 357                                         hwwrite(vortex->mmio,
 358                                                 VORTEX_MIXER_RTBASE +
 359                                                 (esp14 << 2), ebx);
 360                                         //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
 361                                 }
 362                                 hwwrite(vortex->mmio,
 363                                         VORTEX_MIXER_RTBASE + ebp, 0);
 364                                 return 1;
 365                         }
 366                 }
 367         } else {
 368                 //printk(KERN_INFO "removed last mix\n");
 369                 //7be0
 370                 vortex_mixer_dis_sr(vortex, ch);
 371                 hwwrite(vortex->mmio, ebp, 0);
 372         }
 373         return 1;
 374 }
 375
 376 static void vortex_mixer_init(vortex_t * vortex)
 377 {
 378         unsigned long addr;
 379         int x;
 380
 381         // FIXME: get rid of this crap.
 382         memset(mchannels, 0, NR_MIXOUT * sizeof(int));
 383         memset(rampchs, 0, NR_MIXOUT * sizeof(int));
 384
 385         addr = VORTEX_MIX_SMP + 0x17c;
 386         for (x = 0x5f; x >= 0; x--) {
 387                 hwwrite(vortex->mmio, addr, 0);
 388                 addr -= 4;
 389         }
 390         addr = VORTEX_MIX_ENIN + 0x1fc;
 391         for (x = 0x7f; x >= 0; x--) {
 392                 hwwrite(vortex->mmio, addr, 0);
 393                 addr -= 4;
 394         }
 395         addr = VORTEX_MIX_SMP + 0x17c;
 396         for (x = 0x5f; x >= 0; x--) {
 397                 hwwrite(vortex->mmio, addr, 0);
 398                 addr -= 4;
 399         }
 400         addr = VORTEX_MIX_INVOL_A + 0x7fc;
 401         for (x = 0x1ff; x >= 0; x--) {
 402                 hwwrite(vortex->mmio, addr, 0x80);
 403                 addr -= 4;
 404         }
 405         addr = VORTEX_MIX_VOL_A + 0x3c;
 406         for (x = 0xf; x >= 0; x--) {
 407                 hwwrite(vortex->mmio, addr, 0x80);
 408                 addr -= 4;
 409         }
 410         addr = VORTEX_MIX_INVOL_B + 0x7fc;
 411         for (x = 0x1ff; x >= 0; x--) {
 412                 hwwrite(vortex->mmio, addr, 0x80);
 413                 addr -= 4;
 414         }
 415         addr = VORTEX_MIX_VOL_B + 0x3c;
 416         for (x = 0xf; x >= 0; x--) {
 417                 hwwrite(vortex->mmio, addr, 0x80);
 418                 addr -= 4;
 419         }
 420         addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
 421         for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
 422                 hwwrite(vortex->mmio, addr, 0x0);
 423                 addr -= 4;
 424         }
 425         hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
 426
 427         /* Set clipping ceiling (this may be all wrong). */
 428         /*
 429         for (x = 0; x > 0x80; x++) {
 430                 hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff);
 431         }
 432         */
 433         /*
 434            call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____
 435            Register ISR callback for volume smooth fade out.
 436            Maybe this avoids clicks when press "stop" ?
 437          */
 438 }
 439
 440 /*  SRC (CAsp4Src.s and CAsp4SrcBlock) */
 441
 442 static void vortex_src_en_sr(vortex_t * vortex, int channel)
 443 {
 444         hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
 445                 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
 446 }
 447
 448 static void vortex_src_dis_sr(vortex_t * vortex, int channel)
 449 {
 450         hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
 451                 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
 452 }
 453
 454 static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
 455 {
 456         int i;
 457
 458         for (i = 0x1f; i >= 0; i--)
 459                 hwwrite(vortex->mmio,
 460                         VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
 461         hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
 462         hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
 463 }
 464
 465 static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
 466 {
 467         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
 468         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
 469         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
 470 }
 471
 472 static void
 473 vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
 474 {
 475         int temp;
 476
 477         temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
 478         if (en)
 479                 temp |= 1 << src;
 480         else
 481                 temp &= ~(1 << src);
 482         hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
 483 }
 484
 485 static int
 486 vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
 487 {
 488         int temp, lifeboat = 0;
 489
 490         do {
 491                 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
 492                 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
 493                 if ((++lifeboat) > 0x9) {
 494                         printk(KERN_ERR "Vortex: Src cvr fail\n");
 495                         break;
 496                 }
 497         }
 498         while (temp != ratio);
 499         return temp;
 500 }
 501
 502 #if 0
 503 static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
 504 {
 505         int temp;
 506
 507         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
 508         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
 509         temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
 510         if (temp & 0x200)
 511                 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
 512                         temp & ~0x200L);
 513 }
 514
 515 static void
 516 vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
 517 {
 518         int temp, a;
 519
 520         if ((ratio & 0x10000) && (ratio != 0x10000)) {
 521                 if (ratio & 0x3fff)
 522                         a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
 523                 else
 524                         a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
 525         } else
 526                 a = 0xc;
 527         temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
 528         if (((temp >> 4) & 0xf) != a)
 529                 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
 530                         (temp & 0xf) | ((a & 0xf) << 4));
 531
 532         vortex_src_persist_convratio(vortex, src, ratio);
 533 }
 534
 535 static int
 536 vortex_src_checkratio(vortex_t * vortex, unsigned char src,
 537                       unsigned int desired_ratio)
 538 {
 539         int hw_ratio, lifeboat = 0;
 540
 541         hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
 542
 543         while (hw_ratio != desired_ratio) {
 544                 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
 545
 546                 if ((lifeboat++) > 15) {
 547                         printk(KERN_ERR "Vortex: could not set src-%d from %d to %d\n",
 548                                src, hw_ratio, desired_ratio);
 549                         break;
 550                 }
 551         }
 552
 553         return hw_ratio;
 554 }
 555
 556 #endif
 557 /*
 558  Objective: Set samplerate for given SRC module.
 559  Arguments:
 560         card:   pointer to vortex_t strcut.
 561         src:    Integer index of the SRC module.
 562         cr:             Current sample rate conversion factor.
 563         b:              unknown 16 bit value.
 564         sweep:  Enable Samplerate fade from cr toward tr flag.
 565         dirplay: 1: playback, 0: recording.
 566         sl:             Slow Lock flag.
 567         tr:             Target samplerate conversion.
 568         thsource: Throttle source flag (no idea what that means).
 569 */
 570 static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
 571                         unsigned int cr, unsigned int b, int sweep, int d,
 572                         int dirplay, int sl, unsigned int tr, int thsource)
 573 {
 574         // noplayback: d=2,4,7,0xa,0xb when using first 2 src's.
 575         // c: enables pitch sweep.
 576         // looks like g is c related. Maybe g is a sweep parameter ?
 577         // g = cvr
 578         // dirplay: 0 = recording, 1 = playback
 579         // d = src hw index.
 580
 581         int esi, ebp = 0, esp10;
 582
 583         vortex_src_flushbuffers(card, src);
 584
 585         if (sweep) {
 586                 if ((tr & 0x10000) && (tr != 0x10000)) {
 587                         tr = 0;
 588                         esi = 0x7;
 589                 } else {
 590                         if ((((short)tr) < 0) && (tr != 0x8000)) {
 591                                 tr = 0;
 592                                 esi = 0x8;
 593                         } else {
 594                                 tr = 1;
 595                                 esi = 0xc;
 596                         }
 597                 }
 598         } else {
 599                 if ((cr & 0x10000) && (cr != 0x10000)) {
 600                         tr = 0; /*ebx = 0 */
 601                         esi = 0x11 - ((cr >> 0xe) & 7);
 602                         if (cr & 0x3fff)
 603                                 esi -= 1;
 604                         else
 605                                 esi -= 2;
 606                 } else {
 607                         tr = 1;
 608                         esi = 0xc;
 609                 }
 610         }
 611         vortex_src_cleardrift(card, src);
 612         vortex_src_set_throttlesource(card, src, thsource);
 613
 614         if ((dirplay == 0) && (sweep == 0)) {
 615                 if (tr)
 616                         esp10 = 0xf;
 617                 else
 618                         esp10 = 0xc;
 619                 ebp = 0;
 620         } else {
 621                 if (tr)
 622                         ebp = 0xf;
 623                 else
 624                         ebp = 0xc;
 625                 esp10 = 0;
 626         }
 627         hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
 628                 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
 629         /* 0xc0   esi=0xc c=f=0 d=0 */
 630         vortex_src_persist_convratio(card, src, cr);
 631         hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
 632         /* 0   b=0 */
 633         hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
 634                 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
 635         /* 0x30f00 e=g=1 esp10=0 ebp=f */
 636         //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp);
 637 }
 638
 639 static void vortex_srcblock_init(vortex_t * vortex)
 640 {
 641         unsigned long addr;
 642         int x;
 643         hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
 644         /*
 645            for (x=0; x<0x10; x++) {
 646            vortex_src_init(&vortex_src[x], x);
 647            }
 648          */
 649         //addr = 0xcc3c;
 650         //addr = 0x26c3c;
 651         addr = VORTEX_SRC_RTBASE + 0x3c;
 652         for (x = 0xf; x >= 0; x--) {
 653                 hwwrite(vortex->mmio, addr, 0);
 654                 addr -= 4;
 655         }
 656         //addr = 0xcc94;
 657         //addr = 0x26c94;
 658         addr = VORTEX_SRC_CHNBASE + 0x54;
 659         for (x = 0x15; x >= 0; x--) {
 660                 hwwrite(vortex->mmio, addr, 0);
 661                 addr -= 4;
 662         }
 663 }
 664
 665 static int
 666 vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
 667 {
 668         int temp, lifeboat = 0, prev;
 669         // esp13 = src
 670
 671         temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
 672         if ((temp & (1 << ch)) == 0) {
 673                 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
 674                 vortex_src_en_sr(vortex, ch);
 675                 return 1;
 676         }
 677         prev = VORTEX_SRC_CHNBASE + (ch << 2);  /*ebp */
 678         temp = hwread(vortex->mmio, prev);
 679         //while (temp & NR_SRC) {
 680         while (temp & 0x10) {
 681                 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */
 682                 //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/
 683                 temp = hwread(vortex->mmio, prev);
 684                 //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp);
 685                 if ((++lifeboat) > 0xf) {
 686                         printk(KERN_ERR
 687                                "vortex_src_addWTD: lifeboat overflow\n");
 688                         return 0;
 689                 }
 690         }
 691         hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
 692         //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC);
 693         hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
 694         return 1;
 695 }
 696
 697 static int
 698 vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
 699 {
 700         int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
 701         //int esp1f=edi(while)=src, esp10=ch;
 702
 703         eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
 704         if (((1 << ch) & eax) == 0) {
 705                 printk(KERN_ERR "src alarm\n");
 706                 return 0;
 707         }
 708         ebp = VORTEX_SRC_CHNBASE + (ch << 2);
 709         esp18 = hwread(vortex->mmio, ebp);
 710         if (esp18 & 0x10) {
 711                 ebx = (esp18 & 0xf);
 712                 if (src == ebx) {
 713                         ebx = VORTEX_SRC_RTBASE + (src << 2);
 714                         edx = hwread(vortex->mmio, ebx);
 715                         //7b60
 716                         hwwrite(vortex->mmio, ebp, edx);
 717                         hwwrite(vortex->mmio, ebx, 0);
 718                 } else {
 719                         //7ad3
 720                         edx =
 721                             hwread(vortex->mmio,
 722                                    VORTEX_SRC_RTBASE + (ebx << 2));
 723                         //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
 724                         while ((edx & 0xf) != src) {
 725                                 if ((esi) > 0xf) {
 726                                         printk
 727                                             ("vortex: srcdelWTD: error, lifeboat overflow\n");
 728                                         return 0;
 729                                 }
 730                                 esp14 = ebx;
 731                                 ebx = edx & 0xf;
 732                                 ebp = ebx << 2;
 733                                 edx =
 734                                     hwread(vortex->mmio,
 735                                            VORTEX_SRC_RTBASE + ebp);
 736                                 //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx);
 737                                 esi++;
 738                         }
 739                         //7b30
 740                         ebp = ebx << 2;
 741                         if (edx & 0x10) {       /* Delete entry in between others */
 742                                 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
 743                                 edx = hwread(vortex->mmio, ebx);
 744                                 //7b60
 745                                 hwwrite(vortex->mmio,
 746                                         VORTEX_SRC_RTBASE + ebp, edx);
 747                                 hwwrite(vortex->mmio, ebx, 0);
 748                                 //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
 749                         } else {        /* Delete last entry */
 750                                 //7b83
 751                                 if (esp14 == -1)
 752                                         hwwrite(vortex->mmio,
 753                                                 VORTEX_SRC_CHNBASE +
 754                                                 (ch << 2), esp18 & 0xef);
 755                                 else {
 756                                         ebx = (0xffffffe0 & edx) | (0xf & ebx);
 757                                         hwwrite(vortex->mmio,
 758                                                 VORTEX_SRC_RTBASE +
 759                                                 (esp14 << 2), ebx);
 760                                         //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
 761                                 }
 762                                 hwwrite(vortex->mmio,
 763                                         VORTEX_SRC_RTBASE + ebp, 0);
 764                                 return 1;
 765                         }
 766                 }
 767         } else {
 768                 //7be0
 769                 vortex_src_dis_sr(vortex, ch);
 770                 hwwrite(vortex->mmio, ebp, 0);
 771         }
 772         return 1;
 773 }
 774
 775  /*FIFO*/ static void
 776 vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
 777 {
 778         for (x--; x >= 0; x--)
 779                 hwwrite(vortex->mmio,
 780                         VORTEX_FIFO_ADBDATA +
 781                         (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
 782 }
 783
 784 #if 0
 785 static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
 786 {
 787         vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
 788 #ifdef CHIP_AU8820
 789         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
 790                 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
 791 #else
 792         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
 793                 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
 794 #endif
 795 }
 796 #endif
 797 static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
 798 {
 799         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
 800                 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
 801                  0xffffffef) | ((1 & en) << 4) | FIFO_U1);
 802 }
 803
 804 static void
 805 vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int b, int priority,
 806                        int empty, int valid, int f)
 807 {
 808         int temp, lifeboat = 0;
 809         //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
 810         int this_4 = 0x2;
 811         /* f seems priority related.
 812          * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
 813          * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
 814          * is never called, thus the f related bits remain a mystery for now.
 815          */
 816         do {
 817                 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
 818                 if (lifeboat++ > 0xbb8) {
 819                         printk(KERN_ERR
 820                                "Vortex: vortex_fifo_setadbctrl fail\n");
 821                         break;
 822                 }
 823         }
 824         while (temp & FIFO_RDONLY);
 825
 826         // AU8830 semes to take some special care about fifo content (data).
 827         // But i'm just to lazy to translate that :)
 828         if (valid) {
 829                 if ((temp & FIFO_VALID) == 0) {
 830                         //this_8[fifo] = 0;
 831                         vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);      // this_4
 832 #ifdef CHIP_AU8820
 833                         temp = (this_4 & 0x1f) << 0xb;
 834 #else
 835                         temp = (this_4 & 0x3f) << 0xc;
 836 #endif
 837                         temp = (temp & 0xfffffffd) | ((b & 1) << 1);
 838                         temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
 839                         temp = (temp & 0xffffffef) | ((valid & 1) << 4);
 840                         temp |= FIFO_U1;
 841                         temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
 842 #ifdef CHIP_AU8820
 843                         temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
 844 #endif
 845 #ifdef CHIP_AU8830
 846                         temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
 847                         temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
 848 #endif
 849 #ifdef CHIP_AU8810
 850                         temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
 851                         temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
 852 #endif
 853                 }
 854         } else {
 855                 if (temp & FIFO_VALID) {
 856 #ifdef CHIP_AU8820
 857                         temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
 858 #endif
 859 #ifdef CHIP_AU8830
 860                         temp =
 861                             ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
 862 #endif
 863 #ifdef CHIP_AU8810
 864                         temp =
 865                             ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
 866 #endif
 867                 } else
 868                         /*if (this_8[fifo]) */
 869                         vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
 870         }
 871         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
 872         hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
 873 }
 874
 875 #ifndef CHIP_AU8810
 876 static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
 877 {
 878         if (x < 1)
 879                 return;
 880         for (x--; x >= 0; x--)
 881                 hwwrite(vortex->mmio,
 882                         VORTEX_FIFO_WTDATA +
 883                         (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
 884 }
 885
 886 static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
 887 {
 888         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
 889 #ifdef CHIP_AU8820
 890         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
 891                 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
 892 #else
 893         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
 894                 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
 895 #endif
 896 }
 897
 898 static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
 899 {
 900         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
 901                 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
 902                  0xffffffef) | ((en & 1) << 4) | FIFO_U1);
 903 }
 904
 905 static void
 906 vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
 907                       int empty, int valid, int f)
 908 {
 909         int temp = 0, lifeboat = 0;
 910         int this_4 = 2;
 911
 912         do {
 913                 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
 914                 if (lifeboat++ > 0xbb8) {
 915                         printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail\n");
 916                         break;
 917                 }
 918         }
 919         while (temp & FIFO_RDONLY);
 920
 921         if (valid) {
 922                 if ((temp & FIFO_VALID) == 0) {
 923                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);       // this_4
 924 #ifdef CHIP_AU8820
 925                         temp = (this_4 & 0x1f) << 0xb;
 926 #else
 927                         temp = (this_4 & 0x3f) << 0xc;
 928 #endif
 929                         temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
 930                         temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
 931                         temp = (temp & 0xffffffef) | ((valid & 1) << 4);
 932                         temp |= FIFO_U1;
 933                         temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
 934 #ifdef CHIP_AU8820
 935                         temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
 936 #endif
 937 #ifdef CHIP_AU8830
 938                         temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
 939                         temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
 940 #endif
 941 #ifdef CHIP_AU8810
 942                         temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
 943                         temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
 944 #endif
 945                 }
 946         } else {
 947                 if (temp & FIFO_VALID) {
 948 #ifdef CHIP_AU8820
 949                         temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
 950 #endif
 951 #ifdef CHIP_AU8830
 952                         temp =
 953                             ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
 954 #endif
 955 #ifdef CHIP_AU8810
 956                         temp =
 957                             ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
 958 #endif
 959                 } else
 960                         /*if (this_8[fifo]) */
 961                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
 962         }
 963         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
 964         hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
 965
 966 /*
 967     do {
 968                 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
 969                 if (lifeboat++ > 0xbb8) {
 970                         printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail (hanging)\n");
 971                         break;
 972                 }
 973     } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF));
 974
 975
 976         if (valid) {
 977                 if (temp & FIFO_VALID) {
 978                         temp = 0x40000;
 979                         //temp |= 0x08000000;
 980                         //temp |= 0x10000000;
 981                         //temp |= 0x04000000;
 982                         //temp |= 0x00400000;
 983                         temp |= 0x1c400000;
 984                         temp &= 0xFFFFFFF3;
 985                         temp &= 0xFFFFFFEF;
 986                         temp |= (valid & 1) << 4;
 987                         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
 988                         return;
 989                 } else {
 990                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
 991                         return;
 992                 }
 993         } else {
 994                 temp &= 0xffffffef;
 995                 temp |= 0x08000000;
 996                 temp |= 0x10000000;
 997                 temp |= 0x04000000;
 998                 temp |= 0x00400000;
 999                 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1000                 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
1001                 //((temp >> 6) & 0x3f)
1002
1003                 priority = 0;
1004                 if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0)
1005                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
1006                 valid = 0xfb;
1007                 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1008                 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1009                 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1010                 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1011                 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1012                 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1013         }
1014
1015         */
1016
1017         /*
1018            temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1019            temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1020            temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1021            temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1022            temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1023            #ifdef FIFO_BITS
1024            temp = temp | FIFO_BITS | 40000;
1025            #endif
1026            // 0x1c440010, 0x1c400000
1027            hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1028          */
1029 }
1030
1031 #endif
1032 static void vortex_fifo_init(vortex_t * vortex)
1033 {
1034         int x;
1035         unsigned long addr;
1036
1037         /* ADB DMA channels fifos. */
1038         addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
1039         for (x = NR_ADB - 1; x >= 0; x--) {
1040                 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
1041                 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
1042                         printk(KERN_ERR "bad adb fifo reset!");
1043                 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
1044                 addr -= 4;
1045         }
1046
1047 #ifndef CHIP_AU8810
1048         /* WT DMA channels fifos. */
1049         addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
1050         for (x = NR_WT - 1; x >= 0; x--) {
1051                 hwwrite(vortex->mmio, addr, FIFO_U0);
1052                 if (hwread(vortex->mmio, addr) != FIFO_U0)
1053                         printk(KERN_ERR
1054                                "bad wt fifo reset (0x%08lx, 0x%08x)!\n",
1055                                addr, hwread(vortex->mmio, addr));
1056                 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
1057                 addr -= 4;
1058         }
1059 #endif
1060         /* trigger... */
1061 #ifdef CHIP_AU8820
1062         hwwrite(vortex->mmio, 0xf8c0, 0xd03);   //0x0843 0xd6b
1063 #else
1064 #ifdef CHIP_AU8830
1065         hwwrite(vortex->mmio, 0x17000, 0x61);   /* wt a */
1066         hwwrite(vortex->mmio, 0x17004, 0x61);   /* wt b */
1067 #endif
1068         hwwrite(vortex->mmio, 0x17008, 0x61);   /* adb */
1069 #endif
1070 }
1071
1072 /* ADBDMA */
1073
1074 static void vortex_adbdma_init(vortex_t * vortex)
1075 {
1076 }
1077
1078 static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
1079 {
1080         stream_t *dma = &vortex->dma_adb[adbdma];
1081
1082         hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1083                 dma->dma_ctrl);
1084 }
1085
1086 static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
1087 {
1088         stream_t *dma = &vortex->dma_adb[adbdma];
1089         //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2))));
1090         hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
1091                 sb << ((0xf - (adbdma & 0xf)) * 2));
1092         dma->period_real = dma->period_virt = sb;
1093 }
1094
1095 static void
1096 vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
1097                          snd_pcm_sgbuf_t * sgbuf, int psize, int count)
1098 {
1099         stream_t *dma = &vortex->dma_adb[adbdma];
1100
1101         if (sgbuf == NULL) {
1102                 printk(KERN_INFO "vortex: FATAL: sgbuf is NULL!\n");
1103                 return;
1104         }
1105         //printk(KERN_INFO "vortex: page count = %d, tblcount = %d\n", count, sgbuf->tblsize);
1106
1107         dma->period_bytes = psize;
1108         dma->nr_periods = count;
1109         dma->sgbuf = sgbuf;
1110
1111         dma->cfg0 = 0;
1112         dma->cfg1 = 0;
1113         switch (count) {
1114                 /* Four or more pages */
1115         default:
1116         case 4:
1117                 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
1118                 hwwrite(vortex->mmio,
1119                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
1120                         snd_sgbuf_get_addr(sgbuf, psize * 3));
1121                 /* 3 pages */
1122         case 3:
1123                 dma->cfg0 |= 0x12000000;
1124                 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1125                 hwwrite(vortex->mmio,
1126                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
1127                         snd_sgbuf_get_addr(sgbuf, psize * 2));
1128                 /* 2 pages */
1129         case 2:
1130                 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
1131                 hwwrite(vortex->mmio,
1132                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
1133                         snd_sgbuf_get_addr(sgbuf, psize));
1134                 /* 1 page */
1135         case 1:
1136                 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1137                 hwwrite(vortex->mmio,
1138                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
1139                         snd_sgbuf_get_addr(sgbuf, 0));
1140                 break;
1141         }
1142         //printk("vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n", dma->cfg0, dma->cfg1);
1143         hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
1144         hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1145
1146         vortex_adbdma_setfirstbuffer(vortex, adbdma);
1147         vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
1148 }
1149
1150 static void
1151 vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
1152                       int fmt, int d, unsigned long offset)
1153 {
1154         stream_t *dma = &vortex->dma_adb[adbdma];
1155
1156         dma->dma_unknown = d;
1157         dma->dma_ctrl =
1158             ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1159         /* Enable PCMOUT interrupts. */
1160         dma->dma_ctrl =
1161             (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1162
1163         dma->dma_ctrl =
1164             (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1165         dma->dma_ctrl =
1166             (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1167
1168         hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1169                 dma->dma_ctrl);
1170         hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
1171 }
1172
1173 static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
1174 {
1175         stream_t *dma = &vortex->dma_adb[adbdma];
1176         int page, p, pp, delta, i;
1177
1178         page =
1179             (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
1180              ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1181         if (dma->nr_periods >= 4)
1182                 delta = (page - dma->period_real) & 3;
1183         else {
1184                 delta = (page - dma->period_real);
1185                 if (delta < 0)
1186                         delta += dma->nr_periods;
1187         }
1188         if (delta == 0)
1189                 return 0;
1190
1191         /* refresh hw page table */
1192         if (dma->nr_periods > 4) {
1193                 for (i = 0; i < delta; i++) {
1194                         /* p: audio buffer page index */
1195                         p = dma->period_virt + i + 4;
1196                         if (p >= dma->nr_periods)
1197                                 p -= dma->nr_periods;
1198                         /* pp: hardware DMA page index. */
1199                         pp = dma->period_real + i;
1200                         if (pp >= 4)
1201                                 pp -= 4;
1202                         //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
1203                         hwwrite(vortex->mmio,
1204                                 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1205                                 snd_sgbuf_get_addr(dma->sgbuf,
1206                                 dma->period_bytes * p));
1207                         /* Force write thru cache. */
1208                         hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
1209                                (((adbdma << 2) + pp) << 2));
1210                 }
1211         }
1212         dma->period_virt += delta;
1213         dma->period_real = page;
1214         if (dma->period_virt >= dma->nr_periods)
1215                 dma->period_virt -= dma->nr_periods;
1216         if (delta != 1)
1217                 printk(KERN_INFO "vortex: %d virt=%d, real=%d, delta=%d\n",
1218                        adbdma, dma->period_virt, dma->period_real, delta);
1219
1220         return delta;
1221 }
1222
1223 static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1224 {
1225         stream_t *dma = &vortex->dma_adb[adbdma];
1226         int temp;
1227
1228         temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1229         temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK);
1230         return (temp);
1231 }
1232
1233 static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
1234 {
1235         int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ;
1236         stream_t *dma = &vortex->dma_adb[adbdma];
1237
1238         switch (dma->fifo_status) {
1239         case FIFO_START:
1240                 vortex_fifo_setadbvalid(vortex, adbdma,
1241                                         dma->fifo_enabled ? 1 : 0);
1242                 break;
1243         case FIFO_STOP:
1244                 this_8 = 1;
1245                 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1246                         dma->dma_ctrl);
1247                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1248                                        this_4, this_8,
1249                                        dma->fifo_enabled ? 1 : 0, 0);
1250                 break;
1251         case FIFO_PAUSE:
1252                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1253                                        this_4, this_8,
1254                                        dma->fifo_enabled ? 1 : 0, 0);
1255                 break;
1256         }
1257         dma->fifo_status = FIFO_START;
1258 }
1259
1260 static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
1261 {
1262         stream_t *dma = &vortex->dma_adb[adbdma];
1263
1264         int this_8 = 1, this_4 = 0;
1265         switch (dma->fifo_status) {
1266         case FIFO_STOP:
1267                 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1268                         dma->dma_ctrl);
1269                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1270                                        this_4, this_8,
1271                                        dma->fifo_enabled ? 1 : 0, 0);
1272                 break;
1273         case FIFO_PAUSE:
1274                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1275                                        this_4, this_8,
1276                                        dma->fifo_enabled ? 1 : 0, 0);
1277                 break;
1278         }
1279         dma->fifo_status = FIFO_START;
1280 }
1281
1282 static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
1283 {
1284         stream_t *dma = &vortex->dma_adb[adbdma];
1285
1286         int this_8 = 0, this_4 = 0;
1287         switch (dma->fifo_status) {
1288         case FIFO_START:
1289                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1290                                        this_4, this_8, 0, 0);
1291                 break;
1292         case FIFO_STOP:
1293                 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1294                         dma->dma_ctrl);
1295                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1296                                        this_4, this_8, 0, 0);
1297                 break;
1298         }
1299         dma->fifo_status = FIFO_PAUSE;
1300 }
1301
1302 #if 0                           // Using pause instead
1303 static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
1304 {
1305         stream_t *dma = &vortex->dma_adb[adbdma];
1306
1307         int this_4 = 0, this_8 = 0;
1308         if (dma->fifo_status == FIFO_START)
1309                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1310                                        this_4, this_8, 0, 0);
1311         else if (dma->fifo_status == FIFO_STOP)
1312                 return;
1313         dma->fifo_status = FIFO_STOP;
1314         dma->fifo_enabled = 0;
1315 }
1316
1317 #endif
1318 /* WTDMA */
1319
1320 #ifndef CHIP_AU8810
1321 static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
1322 {
1323         //int this_7c=dma_ctrl;
1324         stream_t *dma = &vortex->dma_wt[wtdma];
1325
1326         hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1327 }
1328
1329 static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
1330 {
1331         stream_t *dma = &vortex->dma_wt[wtdma];
1332         //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2)));
1333         hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
1334                 sb << ((0xf - (wtdma & 0xf)) * 2));
1335         dma->period_real = dma->period_virt = sb;
1336 }
1337
1338 static void
1339 vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
1340                         snd_pcm_sgbuf_t * sgbuf, int psize, int count)
1341 {
1342         stream_t *dma = &vortex->dma_wt[wtdma];
1343
1344         dma->period_bytes = psize;
1345         dma->nr_periods = count;
1346         dma->sgbuf = sgbuf;
1347
1348         psize--;
1349
1350         dma->cfg0 = 0;
1351         dma->cfg1 = 0;
1352         switch (count) {
1353                 /* Four or more pages */
1354         default:
1355         case 4:
1356                 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | psize;
1357                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1358                         snd_sgbuf_get_addr(sgbuf, psize * 3));
1359                 /* 3 pages */
1360         case 3:
1361                 dma->cfg0 |= 0x12000000;
1362                 dma->cfg1 |= 0x80000000 | 0x40000000 | (psize << 0xc);
1363                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1364                         snd_sgbuf_get_addr(sgbuf, psize * 2));
1365                 /* 2 pages */
1366         case 2:
1367                 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | psize;
1368                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1369                         snd_sgbuf_get_addr(sgbuf, psize));
1370                 /* 1 page */
1371         case 1:
1372                 dma->cfg0 |= 0x80000000 | 0x40000000 | (psize << 0xc);
1373                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1374                         snd_sgbuf_get_addr(sgbuf, 0));
1375                 break;
1376         }
1377         hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1378         hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1379
1380         vortex_wtdma_setfirstbuffer(vortex, wtdma);
1381         vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
1382 }
1383
1384 static void
1385 vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
1386                      /*int e, */ unsigned long offset)
1387 {
1388         stream_t *dma = &vortex->dma_wt[wtdma];
1389
1390         //dma->this_08 = e;
1391         dma->dma_unknown = d;
1392         dma->dma_ctrl = 0;
1393         dma->dma_ctrl =
1394             ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1395         /* PCMOUT interrupt */
1396         dma->dma_ctrl =
1397             (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1398         /* Always playback. */
1399         dma->dma_ctrl |= (1 << DIR_SHIFT);
1400         /* Audio Format */
1401         dma->dma_ctrl =
1402             (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1403         /* Write into hardware */
1404         hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1405 }
1406
1407 static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
1408 {
1409         stream_t *dma = &vortex->dma_wt[wtdma];
1410         int page, p, pp, delta, i;
1411
1412         page =
1413             (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) &
1414              WT_SUBBUF_MASK)
1415             >> WT_SUBBUF_SHIFT;
1416         if (dma->nr_periods >= 4)
1417                 delta = (page - dma->period_real) & 3;
1418         else {
1419                 delta = (page - dma->period_real);
1420                 if (delta < 0)
1421                         delta += dma->nr_periods;
1422         }
1423         if (delta == 0)
1424                 return 0;
1425
1426         /* refresh hw page table */
1427         if (dma->nr_periods > 4) {
1428                 for (i = 0; i < delta; i++) {
1429                         /* p: audio buffer page index */
1430                         p = dma->period_virt + i + 4;
1431                         if (p >= dma->nr_periods)
1432                                 p -= dma->nr_periods;
1433                         /* pp: hardware DMA page index. */
1434                         pp = dma->period_real + i;
1435                         if (pp >= 4)
1436                                 pp -= 4;
1437                         hwwrite(vortex->mmio,
1438                                 VORTEX_WTDMA_BUFBASE +
1439                                 (((wtdma << 2) + pp) << 2),
1440                                 snd_sgbuf_get_addr(dma->sgbuf, dma->period_bytes * p));
1441                         /* Force write thru cache. */
1442                         hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
1443                                (((wtdma << 2) + pp) << 2));
1444                 }
1445         }
1446         dma->period_virt += delta;
1447         if (dma->period_virt >= dma->nr_periods)
1448                 dma->period_virt -= dma->nr_periods;
1449         dma->period_real = page;
1450
1451         if (delta != 1)
1452                 printk(KERN_WARNING "vortex: wt virt = %d, delta = %d\n",
1453                        dma->period_virt, delta);
1454
1455         return delta;
1456 }
1457
1458 #if 0
1459 static void
1460 vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
1461 {
1462         int temp;
1463         temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1464         *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1465         *pos = temp & POS_MASK;
1466 }
1467
1468 static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
1469 {
1470         return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
1471                  POS_SHIFT) & POS_MASK);
1472 }
1473 #endif
1474 static int inline vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1475 {
1476         stream_t *dma = &vortex->dma_wt[wtdma];
1477         int temp;
1478
1479         temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1480         //temp = (temp & POS_MASK) + (((temp>>WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK)*(dma->cfg0&POS_MASK));
1481         temp = (temp & POS_MASK) + ((dma->period_virt) * (dma->period_bytes));
1482         return temp;
1483 }
1484
1485 static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
1486 {
1487         stream_t *dma = &vortex->dma_wt[wtdma];
1488         int this_8 = 0, this_4 = 0;
1489
1490         switch (dma->fifo_status) {
1491         case FIFO_START:
1492                 vortex_fifo_setwtvalid(vortex, wtdma,
1493                                        dma->fifo_enabled ? 1 : 0);
1494                 break;
1495         case FIFO_STOP:
1496                 this_8 = 1;
1497                 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1498                         dma->dma_ctrl);
1499                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1500                                       this_4, this_8,
1501                                       dma->fifo_enabled ? 1 : 0, 0);
1502                 break;
1503         case FIFO_PAUSE:
1504                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1505                                       this_4, this_8,
1506                                       dma->fifo_enabled ? 1 : 0, 0);
1507                 break;
1508         }
1509         dma->fifo_status = FIFO_START;
1510 }
1511
1512 static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
1513 {
1514         stream_t *dma = &vortex->dma_wt[wtdma];
1515
1516         int this_8 = 0, this_4 = 0;
1517         switch (dma->fifo_status) {
1518         case FIFO_STOP:
1519                 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1520                         dma->dma_ctrl);
1521                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1522                                       this_4, this_8,
1523                                       dma->fifo_enabled ? 1 : 0, 0);
1524                 break;
1525         case FIFO_PAUSE:
1526                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1527                                       this_4, this_8,
1528                                       dma->fifo_enabled ? 1 : 0, 0);
1529                 break;
1530         }
1531         dma->fifo_status = FIFO_START;
1532 }
1533
1534 static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
1535 {
1536         stream_t *dma = &vortex->dma_wt[wtdma];
1537
1538         int this_8 = 0, this_4 = 0;
1539         switch (dma->fifo_status) {
1540         case FIFO_START:
1541                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1542                                       this_4, this_8, 0, 0);
1543                 break;
1544         case FIFO_STOP:
1545                 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1546                         dma->dma_ctrl);
1547                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1548                                       this_4, this_8, 0, 0);
1549                 break;
1550         }
1551         dma->fifo_status = FIFO_PAUSE;
1552 }
1553
1554 static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
1555 {
1556         stream_t *dma = &vortex->dma_wt[wtdma];
1557
1558         int this_4 = 0, this_8 = 0;
1559         if (dma->fifo_status == FIFO_START)
1560                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1561                                       this_4, this_8, 0, 0);
1562         else if (dma->fifo_status == FIFO_STOP)
1563                 return;
1564         dma->fifo_status = FIFO_STOP;
1565         dma->fifo_enabled = 0;
1566 }
1567
1568 #endif
1569 /* ADB Routes */
1570
1571 typedef int ADBRamLink;
1572 static void vortex_adb_init(vortex_t * vortex)
1573 {
1574         int i;
1575         /* it looks like we are writing more than we need to...
1576          * if we write what we are supposed to it breaks things... */
1577         hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
1578         for (i = 0; i < VORTEX_ADB_RTBASE_SIZE; i++)
1579                 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
1580                         hwread(vortex->mmio,
1581                                VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
1582         for (i = 0; i < VORTEX_ADB_CHNBASE_SIZE; i++) {
1583                 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
1584                         hwread(vortex->mmio,
1585                                VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
1586         }
1587 }
1588
1589 static void vortex_adb_en_sr(vortex_t * vortex, int channel)
1590 {
1591         hwwrite(vortex->mmio, VORTEX_ADB_SR,
1592                 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
1593 }
1594
1595 static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
1596 {
1597         hwwrite(vortex->mmio, VORTEX_ADB_SR,
1598                 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
1599 }
1600
1601 static void
1602 vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
1603                      ADBRamLink * route, int rnum)
1604 {
1605         int temp, prev, lifeboat = 0;
1606
1607         if ((rnum <= 0) || (route == NULL))
1608                 return;
1609         /* Write last routes. */
1610         rnum--;
1611         hwwrite(vortex->mmio,
1612                 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
1613                 ROUTE_MASK);
1614         while (rnum > 0) {
1615                 hwwrite(vortex->mmio,
1616                         VORTEX_ADB_RTBASE +
1617                         ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
1618                 rnum--;
1619         }
1620         /* Write first route. */
1621         temp =
1622             hwread(vortex->mmio,
1623                    VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1624         if (temp == ADB_MASK) {
1625                 /* First entry on this channel. */
1626                 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1627                         route[0]);
1628                 vortex_adb_en_sr(vortex, channel);
1629                 return;
1630         }
1631         /* Not first entry on this channel. Need to link. */
1632         do {
1633                 prev = temp;
1634                 temp =
1635                     hwread(vortex->mmio,
1636                            VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
1637                 if ((lifeboat++) > ADB_MASK) {
1638                         printk(KERN_ERR
1639                                "vortex_adb_addroutes: unending route! 0x%x\n",
1640                                *route);
1641                         return;
1642                 }
1643         }
1644         while (temp != ADB_MASK);
1645         hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
1646 }
1647
1648 static void
1649 vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
1650                      ADBRamLink route0, ADBRamLink route1)
1651 {
1652         int temp, lifeboat = 0, prev;
1653
1654         /* Find route. */
1655         temp =
1656             hwread(vortex->mmio,
1657                    VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1658         if (temp == (route0 & ADB_MASK)) {
1659                 temp =
1660                     hwread(vortex->mmio,
1661                            VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
1662                 if ((temp & ADB_MASK) == ADB_MASK)
1663                         vortex_adb_dis_sr(vortex, channel);
1664                 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1665                         temp);
1666                 return;
1667         }
1668         do {
1669                 prev = temp;
1670                 temp =
1671                     hwread(vortex->mmio,
1672                            VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
1673                 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
1674                         printk(KERN_ERR
1675                                "vortex_adb_delroutes: route not found! 0x%x\n",
1676                                route0);
1677                         return;
1678                 }
1679         }
1680         while (temp != (route0 & ADB_MASK));
1681         temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1682         if ((temp & ADB_MASK) == route1)
1683                 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1684         /* Make bridge over deleted route. */
1685         hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
1686 }
1687
1688 static void
1689 vortex_route(vortex_t * vortex, int en, unsigned char channel,
1690              unsigned char source, unsigned char dest)
1691 {
1692         ADBRamLink route;
1693
1694         route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1695         if (en) {
1696                 vortex_adb_addroutes(vortex, channel, &route, 1);
1697                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1698                     && (source >= OFFSET_SRCOUT))
1699                         vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1700                                           channel);
1701                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1702                          && (source >= OFFSET_MIXOUT))
1703                         vortex_mixer_addWTD(vortex,
1704                                             (source - OFFSET_MIXOUT), channel);
1705         } else {
1706                 vortex_adb_delroutes(vortex, channel, route, route);
1707                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1708                     && (source >= OFFSET_SRCOUT))
1709                         vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1710                                           channel);
1711                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1712                          && (source >= OFFSET_MIXOUT))
1713                         vortex_mixer_delWTD(vortex,
1714                                             (source - OFFSET_MIXOUT), channel);
1715         }
1716 }
1717
1718 #if 0
1719 static void
1720 vortex_routes(vortex_t * vortex, int en, unsigned char channel,
1721               unsigned char source, unsigned char dest0, unsigned char dest1)
1722 {
1723         ADBRamLink route[2];
1724
1725         route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
1726         route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
1727
1728         if (en) {
1729                 vortex_adb_addroutes(vortex, channel, route, 2);
1730                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1731                     && (source >= (OFFSET_SRCOUT)))
1732                         vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1733                                           channel);
1734                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1735                          && (source >= (OFFSET_MIXOUT)))
1736                         vortex_mixer_addWTD(vortex,
1737                                             (source - OFFSET_MIXOUT), channel);
1738         } else {
1739                 vortex_adb_delroutes(vortex, channel, route[0], route[1]);
1740                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1741                     && (source >= (OFFSET_SRCOUT)))
1742                         vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1743                                           channel);
1744                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1745                          && (source >= (OFFSET_MIXOUT)))
1746                         vortex_mixer_delWTD(vortex,
1747                                             (source - OFFSET_MIXOUT), channel);
1748         }
1749 }
1750
1751 #endif
1752 /* Route two sources to same target. Sources must be of same class !!! */
1753 static void
1754 vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
1755                 unsigned char source0, unsigned char source1,
1756                 unsigned char dest)
1757 {
1758         ADBRamLink route[2];
1759
1760         route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1761         route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1762
1763         if (dest < 0x10)
1764                 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20);      /* fifo A */
1765
1766         if (en) {
1767                 vortex_adb_addroutes(vortex, ch, route, 2);
1768                 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1769                     && (source0 >= OFFSET_SRCOUT)) {
1770                         vortex_src_addWTD(vortex,
1771                                           (source0 - OFFSET_SRCOUT), ch);
1772                         vortex_src_addWTD(vortex,
1773                                           (source1 - OFFSET_SRCOUT), ch);
1774                 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1775                            && (source0 >= OFFSET_MIXOUT)) {
1776                         vortex_mixer_addWTD(vortex,
1777                                             (source0 - OFFSET_MIXOUT), ch);
1778                         vortex_mixer_addWTD(vortex,
1779                                             (source1 - OFFSET_MIXOUT), ch);
1780                 }
1781         } else {
1782                 vortex_adb_delroutes(vortex, ch, route[0], route[1]);
1783                 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1784                     && (source0 >= OFFSET_SRCOUT)) {
1785                         vortex_src_delWTD(vortex,
1786                                           (source0 - OFFSET_SRCOUT), ch);
1787                         vortex_src_delWTD(vortex,
1788                                           (source1 - OFFSET_SRCOUT), ch);
1789                 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1790                            && (source0 >= OFFSET_MIXOUT)) {
1791                         vortex_mixer_delWTD(vortex,
1792                                             (source0 - OFFSET_MIXOUT), ch);
1793                         vortex_mixer_delWTD(vortex,
1794                                             (source1 - OFFSET_MIXOUT), ch);
1795                 }
1796         }
1797 }
1798
1799 /* Connection stuff */
1800
1801 // Connect adbdma to src('s).
1802 static void
1803 vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
1804                              unsigned char adbdma, unsigned char src)
1805 {
1806         vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
1807 }
1808
1809 // Connect SRC to mixin.
1810 static void
1811 vortex_connection_src_mixin(vortex_t * vortex, int en,
1812                             unsigned char channel, unsigned char src,
1813                             unsigned char mixin)
1814 {
1815         vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
1816 }
1817
1818 // Connect mixin with mix output.
1819 static void
1820 vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
1821                             unsigned char mix, int a)
1822 {
1823         if (en) {
1824                 vortex_mix_enableinput(vortex, mix, mixin);
1825                 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN);        // added to original code.
1826         } else
1827                 vortex_mix_disableinput(vortex, mix, mixin, a);
1828 }
1829
1830 // Connect absolut address to mixin.
1831 static void
1832 vortex_connection_adb_mixin(vortex_t * vortex, int en,
1833                             unsigned char channel, unsigned char source,
1834                             unsigned char mixin)
1835 {
1836         vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
1837 }
1838
1839 static void
1840 vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
1841                              unsigned char src, unsigned char adbdma)
1842 {
1843         vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
1844 }
1845
1846 static void
1847 vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
1848                                  unsigned char ch, unsigned char src0,
1849                                  unsigned char src1, unsigned char adbdma)
1850 {
1851
1852         vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
1853                         ADB_DMA(adbdma));
1854 }
1855
1856 // mix to absolut address.
1857 static void
1858 vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
1859                           unsigned char mix, unsigned char dest)
1860 {
1861         vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
1862         vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN);    // added to original code.
1863 }
1864
1865 // mixer to src.
1866 static void
1867 vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
1868                           unsigned char mix, unsigned char src)
1869 {
1870         vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
1871         vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN);    // added to original code.
1872 }
1873
1874 #if 0
1875 static void
1876 vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
1877                                  unsigned char channel,
1878                                  unsigned char adbdma, unsigned char src0,
1879                                  unsigned char src1)
1880 {
1881         vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
1882                       ADB_SRCIN(src0), ADB_SRCIN(src1));
1883 }
1884
1885 // Connect two mix to AdbDma.
1886 static void
1887 vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
1888                                  unsigned char ch, unsigned char mix0,
1889                                  unsigned char mix1, unsigned char adbdma)
1890 {
1891
1892         ADBRamLink routes[2];
1893         routes[0] =
1894             (((mix0 +
1895                OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
1896         routes[1] =
1897             (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
1898                                                                    0x20) &
1899                                                                   ADB_MASK);
1900         if (en) {
1901                 vortex_adb_addroutes(vortex, ch, routes, 0x2);
1902                 vortex_mixer_addWTD(vortex, mix0, ch);
1903                 vortex_mixer_addWTD(vortex, mix1, ch);
1904         } else {
1905                 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
1906                 vortex_mixer_delWTD(vortex, mix0, ch);
1907                 vortex_mixer_delWTD(vortex, mix1, ch);
1908         }
1909 }
1910 #endif
1911
1912 /* CODEC connect. */
1913
1914 static void
1915 vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
1916 {
1917 #ifdef CHIP_AU8820
1918         vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1919         vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1920 #else
1921 #if 1
1922         // Connect front channels through EQ.
1923         vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
1924         vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
1925         vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
1926         vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
1927
1928         /* Check if reg 0x28 has SDAC bit set. */
1929         if (VORTEX_IS_QUAD(vortex)) {
1930                 /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */
1931                 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
1932                                           ADB_CODECOUT(0 + 4));
1933                 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
1934                                           ADB_CODECOUT(1 + 4));
1935                 //printk("SDAC detected ");
1936         }
1937 #else
1938         // Use plain direct output to codec.
1939         vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1940         vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1941 #endif
1942 #endif
1943 }
1944
1945 static void
1946 vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
1947                         unsigned char mixin1)
1948 {
1949         /*
1950            Enable: 0x1, 0x1
1951            Channel: 0x11, 0x11
1952            ADB Source address: 0x48, 0x49
1953            Destination Asp4Topology_0x9c,0x98
1954          */
1955         vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
1956         vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
1957 }
1958
1959 // Higher level ADB audio path (de)allocator.
1960
1961 /* Resource manager */
1962 static int resnum[VORTEX_RESOURCE_LAST] =
1963     { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
1964 /*
1965  Checkout/Checkin resource of given type.
1966  resmap: resource map to be used. If NULL means that we want to allocate
1967  a DMA resource (root of all other resources of a dma channel).
1968  out: Mean checkout if != 0. Else mean Checkin resource.
1969  restype: Indicates type of resource to be checked in or out.
1970 */
1971 static char
1972 vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
1973 {
1974         int i, qty = resnum[restype], resinuse = 0;
1975
1976         if (out) {
1977                 /* Gather used resources by all streams. */
1978                 for (i = 0; i < NR_ADB; i++) {
1979                         resinuse |= vortex->dma_adb[i].resources[restype];
1980                 }
1981                 resinuse |= vortex->fixed_res[restype];
1982                 /* Find and take free resource. */
1983                 for (i = 0; i < qty; i++) {
1984                         if ((resinuse & (1 << i)) == 0) {
1985                                 if (resmap != NULL)
1986                                         resmap[restype] |= (1 << i);
1987                                 else
1988                                         vortex->dma_adb[i].resources[restype] |= (1 << i);
1989                                 //printk("vortex: ResManager: type %d out %d\n", restype, i);
1990                                 return i;
1991                         }
1992                 }
1993         } else {
1994                 if (resmap == NULL)
1995                         return -EINVAL;
1996                 /* Checkin first resource of type restype. */
1997                 for (i = 0; i < qty; i++) {
1998                         if (resmap[restype] & (1 << i)) {
1999                                 resmap[restype] &= ~(1 << i);
2000                                 //printk("vortex: ResManager: type %d in %d\n",restype, i);
2001                                 return i;
2002                         }
2003                 }
2004         }
2005         printk("vortex: FATAL: ResManager: resource type %d exhausted.\n", restype);
2006         return -ENOMEM;
2007 }
2008
2009 /* Default Connections  */
2010 static void vortex_connect_default(vortex_t * vortex, int en)
2011 {
2012         // FIXME: check if checkout was succesful.
2013         // Connect AC97 codec.
2014         vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2015                                   VORTEX_RESOURCE_MIXOUT);
2016         vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2017                                   VORTEX_RESOURCE_MIXOUT);
2018         if (VORTEX_IS_QUAD(vortex)) {
2019                 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2020                                           VORTEX_RESOURCE_MIXOUT);
2021                 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2022                                           VORTEX_RESOURCE_MIXOUT);
2023         }
2024         vortex_connect_codecplay(vortex, en, vortex->mixplayb);
2025
2026         vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2027                                   VORTEX_RESOURCE_MIXIN);
2028         vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2029                                   VORTEX_RESOURCE_MIXIN);
2030         vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
2031
2032         // Connect SPDIF
2033 #ifndef CHIP_AU8820
2034         vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2035                                   VORTEX_RESOURCE_MIXOUT);
2036         vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2037                                   VORTEX_RESOURCE_MIXOUT);
2038         vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
2039                                   ADB_SPDIFOUT(0));
2040         vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
2041                                   ADB_SPDIFOUT(1));
2042 #endif
2043         // Connect WT
2044 #ifndef CHIP_AU8810
2045         vortex_wt_connect(vortex, en);
2046 #endif
2047         // A3D (crosstalk canceler and A3D slices).
2048 #ifndef CHIP_AU8820
2049         vortex_Vort3D_connect(vortex, en);
2050 #endif
2051         // Connect I2S
2052
2053         // Connect DSP interface for SQ3500 turbo (not here i think...)
2054
2055         // Connect AC98 modem codec
2056
2057         /* Fast Play Workaround. Revision 0xFE does not seem to need it. */
2058         printk(KERN_INFO "vortex: revision = 0x%x, device = %d\n", vortex->rev, vortex->device);
2059         if (IS_BAD_CHIP(vortex)) {
2060                 printk(KERN_INFO "vortex: Erratum workaround enabled.\n");
2061  #ifndef CHIP_AU8820
2062                 vortex->fixed_res[VORTEX_RESOURCE_DMA] = 0x00000001;
2063  #endif
2064                 // Channel swapping workaround. We are nuking registers somewhere, or
2065                 // its a hardware bug.
2066                 vortex->fixed_res[VORTEX_RESOURCE_SRC] = 0x00000001;
2067         }
2068 }
2069
2070 /*
2071   Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
2072   are deallocated.
2073   dma: DMA engine routes to be deallocated when dma >= 0.
2074   nr_ch: Number of channels to be de/allocated.
2075   dir: direction of stream. Uses same values as substream->stream.
2076   type: Type of audio output/source (codec, spdif, i2s, dsp, etc)
2077   Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
2078 */
2079 static int
2080 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type)
2081 {
2082         stream_t *stream;
2083         int i, en;
2084
2085         if ((nr_ch == 3)
2086             || ((dir == SNDRV_PCM_STREAM_CAPTURE) && (nr_ch > 2)))
2087                 return -EBUSY;
2088
2089         spin_lock(&vortex->lock);
2090         if (dma >= 0) {
2091                 en = 0;
2092                 vortex_adb_checkinout(vortex,
2093                                       vortex->dma_adb[dma].resources, en,
2094                                       VORTEX_RESOURCE_DMA);
2095         } else {
2096                 en = 1;
2097                 if ((dma =
2098                      vortex_adb_checkinout(vortex, NULL, en,
2099                                            VORTEX_RESOURCE_DMA)) < 0)
2100                         return -EBUSY;
2101         }
2102
2103         stream = &vortex->dma_adb[dma];
2104         stream->dma = dma;
2105         stream->dir = dir;
2106         stream->type = type;
2107
2108         // FIXME: check for success of checkout or checkin.
2109         /* PLAYBACK ROUTES. */
2110         if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
2111                 int src[4], mix[4], ch_top;
2112 #ifndef CHIP_AU8820
2113                 int a3d = 0;
2114 #endif
2115                 /* Get SRC and MIXER hardware resources. */
2116                 if (stream->type != VORTEX_PCM_SPDIF) {
2117                         for (i = 0; i < nr_ch; i++) {
2118                                 if ((src[i] = vortex_adb_checkinout(vortex,
2119                                                            stream->resources, en,
2120                                                            VORTEX_RESOURCE_SRC)) < 0) {
2121                                         memset(stream->resources, 0,
2122                                                sizeof(unsigned char) *
2123                                                VORTEX_RESOURCE_LAST);
2124                                         return -EBUSY;
2125                                 }
2126                                 if (stream->type != VORTEX_PCM_A3D) {
2127                                         if ((mix[i] = vortex_adb_checkinout(vortex,
2128                                                                    stream->resources,
2129                                                                    en,
2130                                                                    VORTEX_RESOURCE_MIXIN)) < 0) {
2131                                                 memset(stream->resources,
2132                                                        0,
2133                                                        sizeof(unsigned char) * VORTEX_RESOURCE_LAST);
2134                                                 return -EBUSY;
2135                                         }
2136                                 }
2137                         }
2138                 }
2139 #ifndef CHIP_AU8820
2140                 if (stream->type == VORTEX_PCM_A3D) {
2141                         if ((a3d =
2142                              vortex_adb_checkinout(vortex,
2143                                                    stream->resources, en,
2144                                                    VORTEX_RESOURCE_A3D)) < 0) {
2145                                 memset(stream->resources, 0,
2146                                        sizeof(unsigned char) *
2147                                        VORTEX_RESOURCE_LAST);
2148                                 printk("vortex: out of A3D sources. Sorry\n");
2149                                 return -EBUSY;
2150                         }
2151                         /* (De)Initialize A3D hardware source. */
2152                         vortex_Vort3D_InitializeSource(&(vortex->a3d[a3d]), en);
2153                 }
2154                 /* Make SPDIF out exclusive to "spdif" device when in use. */
2155                 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
2156                         vortex_route(vortex, 0, 0x14,
2157                                      ADB_MIXOUT(vortex->mixspdif[0]),
2158                                      ADB_SPDIFOUT(0));
2159                         vortex_route(vortex, 0, 0x14,
2160                                      ADB_MIXOUT(vortex->mixspdif[1]),
2161                                      ADB_SPDIFOUT(1));
2162                 }
2163 #endif
2164                 /* Make playback routes. */
2165                 for (i = 0; i < nr_ch; i++) {
2166                         if (stream->type == VORTEX_PCM_ADB) {
2167                                 vortex_connection_adbdma_src(vortex, en,
2168                                                              src[nr_ch - 1],
2169                                                              //src[0],
2170                                                              dma,
2171                                                              src[i]);
2172                                 vortex_connection_src_mixin(vortex, en,
2173                                                             0x11, src[i],
2174                                                             mix[i]);
2175                                 vortex_connection_mixin_mix(vortex, en,
2176                                                             mix[i],
2177                                                             MIX_PLAYB(i), 0);
2178 #ifndef CHIP_AU8820
2179                                 vortex_connection_mixin_mix(vortex, en,
2180                                                             mix[i],
2181                                                             MIX_SPDIF(i % 2), 0);
2182                                 vortex_mix_setinputvolumebyte(vortex,
2183                                                               MIX_SPDIF(i % 2),
2184                                                               mix[i],
2185                                                               MIX_DEFIGAIN);
2186 #endif
2187                         }
2188 #ifndef CHIP_AU8820
2189                         if (stream->type == VORTEX_PCM_A3D) {
2190                                 vortex_connection_adbdma_src(vortex, en,
2191                                                              src[0],
2192                                                                  dma,
2193                                                              src[i]);
2194                                 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
2195                                 /* XTalk test. */
2196                                 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
2197                                 //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9));
2198                         }
2199                         if (stream->type == VORTEX_PCM_SPDIF)
2200                                 vortex_route(vortex, en, 0x14,
2201                                              ADB_DMA(stream->dma),
2202                                              ADB_SPDIFOUT(i));
2203 #endif
2204                 }
2205                 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
2206                         ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
2207                         for (i = nr_ch; i < ch_top; i++) {
2208                                 vortex_connection_mixin_mix(vortex, en,
2209                                                             mix[i % nr_ch],
2210                                                             MIX_PLAYB(i), 0);
2211 #ifndef CHIP_AU8820
2212                                 vortex_connection_mixin_mix(vortex, en,
2213                                                             mix[i % nr_ch],
2214                                                             MIX_SPDIF(i % 2),
2215                                                                 0);
2216                                 vortex_mix_setinputvolumebyte(vortex,
2217                                                               MIX_SPDIF(i % 2),
2218                                                               mix[i % nr_ch],
2219                                                               MIX_DEFIGAIN);
2220 #endif
2221                         }
2222                 }
2223 #ifndef CHIP_AU8820
2224                 else {
2225                         if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
2226                                 vortex_route(vortex, en, 0x14,
2227                                              ADB_DMA(stream->dma),
2228                                              ADB_SPDIFOUT(1));
2229                 }
2230                 /* Reconnect SPDIF out when "spdif" device is down. */
2231                 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
2232                         vortex_route(vortex, 1, 0x14,
2233                                      ADB_MIXOUT(vortex->mixspdif[0]),
2234                                      ADB_SPDIFOUT(0));
2235                         vortex_route(vortex, 1, 0x14,
2236                                      ADB_MIXOUT(vortex->mixspdif[1]),
2237                                      ADB_SPDIFOUT(1));
2238                 }
2239 #endif
2240                 /* CAPTURE ROUTES. */
2241         } else {
2242                 int src[2], mix[2];
2243
2244                 /* Get SRC and MIXER hardware resources. */
2245                 for (i = 0; i < nr_ch; i++) {
2246                         if ((mix[i] =
2247                              vortex_adb_checkinout(vortex,
2248                                                    stream->resources, en,
2249                                                    VORTEX_RESOURCE_MIXOUT))
2250                             < 0) {
2251                                 memset(stream->resources, 0,
2252                                        sizeof(unsigned char) *
2253                                        VORTEX_RESOURCE_LAST);
2254                                 return -EBUSY;
2255                         }
2256                         if ((src[i] =
2257                              vortex_adb_checkinout(vortex,
2258                                                    stream->resources, en,
2259                                                    VORTEX_RESOURCE_SRC)) < 0) {
2260                                 memset(stream->resources, 0,
2261                                        sizeof(unsigned char) *
2262                                        VORTEX_RESOURCE_LAST);
2263                                 return -EBUSY;
2264                         }
2265                 }
2266
2267                 /* Make capture routes. */
2268                 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
2269                 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
2270                 if (nr_ch == 1) {
2271                         vortex_connection_mixin_mix(vortex, en,
2272                                                     MIX_CAPT(1), mix[0], 0);
2273                         vortex_connection_src_adbdma(vortex, en,
2274                                                      src[nr_ch - 1],
2275                                                      src[0], dma);
2276                 } else {
2277                         vortex_connection_mixin_mix(vortex, en,
2278                                                     MIX_CAPT(1), mix[1], 0);
2279                         vortex_connection_mix_src(vortex, en, 0x11, mix[1],
2280                                                   src[1]);
2281                         vortex_connection_src_src_adbdma(vortex, en,
2282                                                          src[0], src[0],
2283                                                          src[1], dma);
2284                 }
2285         }
2286         vortex->dma_adb[dma].nr_ch = nr_ch;
2287         spin_unlock(&vortex->lock);
2288
2289 #if 0
2290         /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */
2291         if (nr_ch < 4) {
2292                 /* Copy stereo to rear channel (surround) */
2293                 snd_ac97_write_cache(vortex->codec,
2294                                      AC97_SIGMATEL_DAC2INVERT,
2295                                      snd_ac97_read(vortex->codec,
2296                                                    AC97_SIGMATEL_DAC2INVERT)
2297                                      | 4);
2298         } else {
2299                 /* Allow separate front and rear channels. */
2300                 snd_ac97_write_cache(vortex->codec,
2301                                      AC97_SIGMATEL_DAC2INVERT,
2302                                      snd_ac97_read(vortex->codec,
2303                                                    AC97_SIGMATEL_DAC2INVERT)
2304                                      & ~((u32)
2305                                          4));
2306         }
2307 #endif
2308         return dma;
2309 }
2310
2311 /*
2312  Set the SampleRate of the SRC's attached to the given DMA engine.
2313  */
2314 static void
2315 vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
2316 {
2317         stream_t *stream = &(vortex->dma_adb[adbdma]);
2318         int i, cvrt;
2319
2320         /* dir=1:play ; dir=0:rec */
2321         if (dir)
2322                 cvrt = SRC_RATIO(rate, 48000);
2323         else
2324                 cvrt = SRC_RATIO(48000, rate);
2325
2326         /* Setup SRC's */
2327         for (i = 0; i < NR_SRC; i++) {
2328                 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
2329                         vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
2330         }
2331 }
2332
2333 // Timer and ISR functions.
2334
2335 static void vortex_settimer(vortex_t * vortex, int period)
2336 {
2337         //set the timer period to <period> 48000ths of a second.
2338         hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
2339 }
2340
2341 #if 0
2342 static void vortex_enable_timer_int(vortex_t * card)
2343 {
2344         hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2345                 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
2346 }
2347
2348 static void vortex_disable_timer_int(vortex_t * card)
2349 {
2350         hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2351                 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
2352 }
2353
2354 #endif
2355 static void vortex_enable_int(vortex_t * card)
2356 {
2357         // CAsp4ISR__EnableVortexInt_void_
2358         hwwrite(card->mmio, VORTEX_CTRL,
2359                 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
2360         hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2361                 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
2362 }
2363
2364 static void vortex_disable_int(vortex_t * card)
2365 {
2366         hwwrite(card->mmio, VORTEX_CTRL,
2367                 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
2368 }
2369
2370 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2371 {
2372         vortex_t *vortex = snd_magic_cast(vortex_t, dev_id, return IRQ_NONE);
2373         int i, handled;
2374         u32 source;
2375
2376         //check if the interrupt is ours.
2377         if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
2378                 return IRQ_NONE;
2379
2380         // This is the Interrrupt Enable flag we set before (consistency check).
2381         if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
2382                 return IRQ_NONE;
2383
2384         source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2385         // Reset IRQ flags.
2386         hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
2387         hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2388         // Is at least one IRQ flag set?
2389         if (source == 0) {
2390                 printk(KERN_ERR "vortex: missing irq source\n");
2391                 return IRQ_NONE;
2392         }
2393
2394         handled = 0;
2395         // Attend every interrupt source.
2396         if (unlikely(source & IRQ_ERR_MASK)) {
2397                 if (source & IRQ_FATAL) {
2398                         printk(KERN_ERR "vortex: IRQ fatal error\n");
2399                 }
2400                 if (source & IRQ_PARITY) {
2401                         printk(KERN_ERR "vortex: IRQ parity error\n");
2402                 }
2403                 if (source & IRQ_REG) {
2404                         printk(KERN_ERR "vortex: IRQ reg error\n");
2405                 }
2406                 if (source & IRQ_FIFO) {
2407                         printk(KERN_ERR "vortex: IRQ fifo error\n");
2408                 }
2409                 if (source & IRQ_DMA) {
2410                         printk(KERN_ERR "vortex: IRQ dma error\n");
2411                 }
2412                 handled = 1;
2413         }
2414         if (source & IRQ_PCMOUT) {
2415                 /* ALSA period acknowledge. */
2416                 for (i = 0; i < NR_ADB; i++) {
2417                         if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2418                                 if (vortex_adbdma_bufshift(vortex, i)) ;
2419                                 snd_pcm_period_elapsed(vortex->dma_adb[i].
2420                                                        substream);
2421                         }
2422                 }
2423 #ifndef CHIP_AU8810
2424                 for (i = 0; i < NR_WT; i++) {
2425                         if (vortex->dma_wt[i].fifo_status == FIFO_START) {
2426                                 if (vortex_wtdma_bufshift(vortex, i)) ;
2427                                 snd_pcm_period_elapsed(vortex->dma_wt[i].
2428                                                        substream);
2429                         }
2430                 }
2431 #endif
2432                 handled = 1;
2433         }
2434         //Acknowledge the Timer interrupt
2435         if (source & IRQ_TIMER) {
2436                 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2437                 handled = 1;
2438         }
2439         if (source & IRQ_MIDI) {
2440                 snd_mpu401_uart_interrupt(vortex->irq,
2441                                           vortex->rmidi->private_data, regs);
2442                 handled = 1;
2443         }
2444
2445         if (!handled) {
2446                 printk(KERN_ERR "vortex: unknown irq source %x\n", source);
2447         }
2448         return IRQ_RETVAL(handled);
2449 }
2450
2451 /* Codec */
2452
2453 #define POLL_COUNT 1000
2454 static void vortex_codec_init(vortex_t * vortex)
2455 {
2456         int i;
2457
2458         for (i = 0; i < 32; i++) {
2459                 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), 0);
2460                 udelay(2000);
2461         }
2462         if (0) {
2463                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
2464                 udelay(1000);
2465                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2466                 udelay(1000);
2467         } else {
2468                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2469                 udelay(2000);
2470                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2471                 udelay(2000);
2472                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
2473                 udelay(2000);
2474                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2475                 udelay(2000);
2476                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2477                 udelay(2000);
2478                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2479         }
2480         for (i = 0; i < 32; i++) {
2481                 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), 0);
2482                 udelay(5000);
2483         }
2484         hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
2485         udelay(1000);
2486         /* Enable codec channels 0 and 1. */
2487         hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2488                 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
2489 }
2490
2491 static void
2492 vortex_codec_write(ac97_t * codec, unsigned short addr, unsigned short data)
2493 {
2494
2495         vortex_t *card = (vortex_t *) codec->private_data;
2496         unsigned long flags;
2497         unsigned int lifeboat = 0;
2498         spin_lock_irqsave(&card->lock, flags);
2499
2500         /* wait for transactions to clear */
2501         while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2502                 udelay(100);
2503                 if (lifeboat++ > POLL_COUNT) {
2504                         printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
2505                         spin_unlock_irqrestore(&card->lock, flags);
2506                         return;
2507                 }
2508         }
2509         /* write register */
2510         hwwrite(card->mmio, VORTEX_CODEC_IO,
2511                 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2512                 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
2513                 VORTEX_CODEC_WRITE);
2514
2515         /* Flush Caches. */
2516         hwread(card->mmio, VORTEX_CODEC_IO);
2517
2518         spin_unlock_irqrestore(&card->lock, flags);
2519 }
2520
2521 static unsigned short vortex_codec_read(ac97_t * codec, unsigned short addr)
2522 {
2523
2524         vortex_t *card = (vortex_t *) codec->private_data;
2525         u32 read_addr, data;
2526         unsigned long flags;
2527         unsigned lifeboat = 0;
2528
2529         spin_lock_irqsave(&card->lock, flags);
2530
2531         /* wait for transactions to clear */
2532         while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2533                 udelay(100);
2534                 if (lifeboat++ > POLL_COUNT) {
2535                         printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
2536                         spin_unlock_irqrestore(&card->lock, flags);
2537                         return 0xffff;
2538                 }
2539         }
2540         /* set up read address */
2541         read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK);
2542         hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
2543
2544         /* wait for address */
2545         {
2546                 udelay(100);
2547                 data = hwread(card->mmio, VORTEX_CODEC_IO);
2548                 if (lifeboat++ > POLL_COUNT) {
2549                         printk(KERN_ERR "vortex: ac97 address never arrived\n");
2550                         spin_unlock_irqrestore(&card->lock, flags);
2551                         return 0xffff;
2552                 }
2553         }
2554         while ((data & VORTEX_CODEC_ADDMASK) !=
2555                (addr << VORTEX_CODEC_ADDSHIFT)) ;
2556
2557         /* Unlock. */
2558         spin_unlock_irqrestore(&card->lock, flags);
2559
2560         /* return data. */
2561         return (u16) (data & VORTEX_CODEC_DATMASK);
2562 }
2563
2564 /* SPDIF support  */
2565
2566 static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
2567 {
2568         int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
2569
2570         /* CAsp4Spdif::InitializeSpdifHardware(void) */
2571         hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
2572                 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
2573         //for (i=0x291D4; i<0x29200; i+=4)
2574         for (i = 0; i < 11; i++)
2575                 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
2576         //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000);
2577         hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2578                 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
2579
2580         /* CAsp4Spdif::ProgramSRCInHardware(enum  SPDIF_SR,enum  SPDIFMODE) */
2581         if (this_04 && this_08) {
2582                 int edi;
2583
2584                 i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
2585                 if (i > 0x800) {
2586                         if (i < 0x1ffff)
2587                                 edi = (i >> 1);
2588                         else
2589                                 edi = 0x1ffff;
2590                 } else {
2591                         i = edi = 0x800;
2592                 }
2593                 /* this_04 and this_08 are the CASp4Src's (samplerate converters) */
2594                 vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
2595                                         this_0c, 1, 0, edi, 1);
2596                 vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
2597                                         this_0c, 1, 0, edi, 1);
2598         }
2599
2600         i = spdif_sr;
2601         spdif_sr |= 0x8c;
2602         switch (i) {
2603         case 32000:
2604                 this_38 &= 0xFFFFFFFE;
2605                 this_38 &= 0xFFFFFFFD;
2606                 this_38 &= 0xF3FFFFFF;
2607                 this_38 |= 0x03000000;  /* set 32khz samplerate */
2608                 this_38 &= 0xFFFFFF3F;
2609                 spdif_sr &= 0xFFFFFFFD;
2610                 spdif_sr |= 1;
2611                 break;
2612         case 44100:
2613                 this_38 &= 0xFFFFFFFE;
2614                 this_38 &= 0xFFFFFFFD;
2615                 this_38 &= 0xF0FFFFFF;
2616                 this_38 |= 0x03000000;
2617                 this_38 &= 0xFFFFFF3F;
2618                 spdif_sr &= 0xFFFFFFFC;
2619                 break;
2620         case 48000:
2621                 if (spdif_mode == 1) {
2622                         this_38 &= 0xFFFFFFFE;
2623                         this_38 &= 0xFFFFFFFD;
2624                         this_38 &= 0xF2FFFFFF;
2625                         this_38 |= 0x02000000;  /* set 48khz samplerate */
2626                         this_38 &= 0xFFFFFF3F;
2627                 } else {
2628                         /* J. Gordon Wolfe: I think this stuff is for AC3 */
2629                         this_38 |= 0x00000003;
2630                         this_38 &= 0xFFFFFFBF;
2631                         this_38 |= 0x80;
2632                 }
2633                 spdif_sr |= 2;
2634                 spdif_sr &= 0xFFFFFFFE;
2635                 break;
2636
2637         }
2638         /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit
2639            registers. seems to be for the standard IEC/SPDIF initialization
2640            stuff */
2641         hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
2642         hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
2643         hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
2644 }
2645
2646 /* Initialization */
2647
2648 static int vortex_core_init(vortex_t * vortex)
2649 {
2650
2651         printk(KERN_INFO "Vortex: init.... ");
2652         /* Hardware Init. */
2653         hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
2654         udelay(5000);
2655         hwwrite(vortex->mmio, VORTEX_CTRL,
2656                 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
2657         udelay(5000);
2658         /* Reset IRQ flags */
2659         hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
2660         hwread(vortex->mmio, VORTEX_IRQ_STAT);
2661
2662         vortex_codec_init(vortex);
2663
2664 #ifdef CHIP_AU8830
2665         hwwrite(vortex->mmio, VORTEX_CTRL,
2666                 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
2667 #endif
2668
2669         /* Init audio engine. */
2670         vortex_adbdma_init(vortex);
2671         hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58
2672         vortex_adb_init(vortex);
2673         /* Init processing blocks. */
2674         vortex_fifo_init(vortex);
2675         vortex_mixer_init(vortex);
2676         vortex_srcblock_init(vortex);
2677 #ifndef CHIP_AU8820
2678         vortex_eq_init(vortex);
2679         vortex_spdif_init(vortex, 48000, 1);
2680         vortex_Vort3D(vortex, 1);
2681 #endif
2682 #ifndef CHIP_AU8810
2683         vortex_wt_init(vortex);
2684 #endif
2685         // Moved to au88x0.c
2686         //vortex_connect_default(vortex, 1);
2687
2688         vortex_settimer(vortex, 0x90);
2689         // Enable Interrupts.
2690         // vortex_enable_int() must be first !!
2691         //  hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2692         // vortex_enable_int(vortex);
2693         //vortex_enable_timer_int(vortex);
2694         //vortex_disable_timer_int(vortex);
2695
2696         printk(KERN_INFO "done.\n");
2697         spin_lock_init(&vortex->lock);
2698
2699         return 0;
2700 }
2701
2702 static int vortex_core_shutdown(vortex_t * vortex)
2703 {
2704
2705         printk(KERN_INFO "Vortex: shutdown...");
2706 #ifndef CHIP_AU8820
2707         vortex_eq_free(vortex);
2708         vortex_Vort3D(vortex, 0);
2709 #endif
2710         //vortex_disable_timer_int(vortex);
2711         vortex_disable_int(vortex);
2712         vortex_connect_default(vortex, 0);
2713         /* Reset all DMA fifos. */
2714         vortex_fifo_init(vortex);
2715         /* Erase all audio routes. */
2716         vortex_adb_init(vortex);
2717
2718         /* Disable MPU401 */
2719         //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI);
2720         //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN);
2721
2722         hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2723         hwwrite(vortex->mmio, VORTEX_CTRL, 0);
2724         udelay(5000);
2725         hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
2726
2727         printk(KERN_INFO "done.\n");
2728         return 0;
2729 }
2730
2731 /* Alsa support. */
2732
2733 static int vortex_alsafmt_aspfmt(int alsafmt)
2734 {
2735         int fmt;
2736
2737         switch (alsafmt) {
2738         case SNDRV_PCM_FORMAT_U8:
2739                 fmt = 0x1;
2740                 break;
2741         case SNDRV_PCM_FORMAT_MU_LAW:
2742                 fmt = 0x2;
2743                 break;
2744         case SNDRV_PCM_FORMAT_A_LAW:
2745                 fmt = 0x3;
2746                 break;
2747         case SNDRV_PCM_FORMAT_SPECIAL:
2748                 fmt = 0x4;      /* guess. */
2749                 break;
2750         case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
2751                 fmt = 0x5;      /* guess. */
2752                 break;
2753         case SNDRV_PCM_FORMAT_S16_LE:
2754                 fmt = 0x8;
2755                 break;
2756         case SNDRV_PCM_FORMAT_S16_BE:
2757                 fmt = 0x9;      /* check this... */
2758                 break;
2759         default:
2760                 fmt = 0x8;
2761                 printk(KERN_ERR "vortex: format unsupported %d\n", alsafmt);
2762                 break;
2763         }
2764         return fmt;
2765 }
2766
2767 /* Some not yet useful translations. */
2768 #if 0
2769 typedef enum {
2770         ASPFMTLINEAR16 = 0,     /* 0x8 */
2771         ASPFMTLINEAR8,          /* 0x1 */
2772         ASPFMTULAW,             /* 0x2 */
2773         ASPFMTALAW,             /* 0x3 */
2774         ASPFMTSPORT,            /* ? */
2775         ASPFMTSPDIF,            /* ? */
2776 } ASPENCODING;
2777
2778 static int
2779 vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
2780 {
2781         int a, this_194;
2782
2783         if ((bits != 8) || (bits != 16))
2784                 return -1;
2785
2786         switch (encod) {
2787         case 0:
2788                 if (bits == 0x10)
2789                         a = 8;  // 16 bit
2790                 break;
2791         case 1:
2792                 if (bits == 8)
2793                         a = 1;  // 8 bit
2794                 break;
2795         case 2:
2796                 a = 2;          // U_LAW
2797                 break;
2798         case 3:
2799                 a = 3;          // A_LAW
2800                 break;
2801         }
2802         switch (nch) {
2803         case 1:
2804                 this_194 = 0;
2805                 break;
2806         case 2:
2807                 this_194 = 1;
2808                 break;
2809         case 4:
2810                 this_194 = 1;
2811                 break;
2812         case 6:
2813                 this_194 = 1;
2814                 break;
2815         }
2816         return (a);
2817 }
2818
2819 static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
2820 {
2821         short int d, this_148;
2822
2823         d = ((bits >> 3) * nch);
2824         this_148 = 0xbb80 / d;
2825 }
2826 #endif