sound/pci/au88x0/au88x0_core.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify
   3  *  it under the terms of the GNU General Public License as published by
   4  *  the Free Software Foundation; either version 2 of the License, or
   5  *  (at your option) any later version.
   6  *
   7  *  This program is distributed in the hope that it will be useful,
   8  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *  GNU Library General Public License for more details.
  11  *
  12  *  You should have received a copy of the GNU General Public License
  13  *  along with this program; if not, write to the Free Software
  14  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  15  */
  16
  17 /*
  18     Vortex core low level functions.
  19
  20  Author: Manuel Jander (mjander@users.sourceforge.cl)
  21  These functions are mainly the result of translations made
  22  from the original disassembly of the au88x0 binary drivers,
  23  written by Aureal before they went down.
  24  Many thanks to the Jeff Muizelar, Kester Maddock, and whoever
  25  contributed to the OpenVortex project.
  26  The author of this file, put the few available pieces together
  27  and translated the rest of the riddle (Mix, Src and connection stuff).
  28  Some things are still to be discovered, and their meanings are unclear.
  29
  30  Some of these functions aren't intended to be really used, rather
  31  to help to understand how does the AU88X0 chips work. Keep them in, because
  32  they could be used somewhere in the future.
  33
  34  This code hasn't been tested or proof read thoroughly. If you wanna help,
  35  take a look at the AU88X0 assembly and check if this matches.
  36  Functions tested ok so far are (they show the desired effect
  37  at least):
  38    vortex_routes(); (1 bug fixed).
  39    vortex_adb_addroute();
  40    vortex_adb_addroutes();
  41    vortex_connect_codecplay();
  42    vortex_src_flushbuffers();
  43    vortex_adbdma_setmode();  note: still some unknown arguments!
  44    vortex_adbdma_startfifo();
  45    vortex_adbdma_stopfifo();
  46    vortex_fifo_setadbctrl(); note: still some unknown arguments!
  47    vortex_mix_setinputvolumebyte();
  48    vortex_mix_enableinput();
  49    vortex_mixer_addWTD(); (fixed)
  50    vortex_connection_adbdma_src_src();
  51    vortex_connection_adbdma_src();
  52    vortex_src_change_convratio();
  53    vortex_src_addWTD(); (fixed)
  54
  55  History:
  56
  57  01-03-2003 First revision.
  58  01-21-2003 Some bug fixes.
  59  17-02-2003 many bugfixes after a big versioning mess.
  60  18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy !
  61                          (2 hours later...) I cant believe it! Im really lucky today.
  62                          Now the SRC is working too! Yeah! XMMS works !
  63  20-02-2003 First steps into the ALSA world.
  64  28-02-2003 As my birthday present, i discovered how the DMA buffer pages really
  65             work :-). It was all wrong.
  66  12-03-2003 ALSA driver starts working (2 channels).
  67  16-03-2003 More srcblock_setupchannel discoveries.
  68  12-04-2003 AU8830 playback support. Recording in the works.
  69  17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording
  70                         works now, but chipn' dale effect is still there.
  71  16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely
  72             into au88x0_pcm.c .
  73  06-06-2003 Buffer shifter bugfix. Mixer volume fix.
  74  07-12-2003 A3D routing finally fixed. Believed to be OK.
  75  25-03-2004 Many thanks to Claudia, for such valuable bug reports.
  76
  77 */
  78
  79 #include "au88x0.h"
  80 #include "au88x0_a3d.h"
  81 #include <linux/delay.h>
  82
  83 /*  MIXER (CAsp4Mix.s and CAsp4Mixer.s) */
  84
  85 // FIXME: get rid of this.
  86 static int mchannels[NR_MIXIN];
  87 static int rampchs[NR_MIXIN];
  88
  89 static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
  90 {
  91         hwwrite(vortex->mmio, VORTEX_MIXER_SR,
  92                 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
  93 }
  94 static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
  95 {
  96         hwwrite(vortex->mmio, VORTEX_MIXER_SR,
  97                 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
  98 }
  99
 100 #if 0
 101 static void
 102 vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
 103                          unsigned char channel)
 104 {
 105         hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
 106                 0x80);
 107         hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
 108                 0x80);
 109 }
 110
 111 static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
 112 {
 113         int a;
 114         a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
 115         //FP2LinearFrac(a);
 116         return (a);
 117 }
 118
 119 static int
 120 vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
 121                           int channel, int *vol)
 122 {
 123         int a;
 124         if (!(mchannels[mix] & (1 << channel)))
 125                 return 0;
 126         a = hwread(vortex->mmio,
 127                    VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
 128         /*
 129            if (rampchs[mix] == 0)
 130            a = FP2LinearFrac(a);
 131            else
 132            a = FP2LinearFracWT(a);
 133          */
 134         *vol = a;
 135         return (0);
 136 }
 137
 138 static unsigned int vortex_mix_boost6db(unsigned char vol)
 139 {
 140         return (vol + 8);       /* WOW! what a complex function! */
 141 }
 142
 143 static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
 144 {
 145         int ch;
 146         char a;
 147         // This function is intended for ramping down only (see vortex_disableinput()).
 148         for (ch = 0; ch < 0x20; ch++) {
 149                 if (((1 << ch) & rampchs[mix]) == 0)
 150                         continue;
 151                 a = hwread(vortex->mmio,
 152                            VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
 153                 if (a > -126) {
 154                         a -= 2;
 155                         hwwrite(vortex->mmio,
 156                                 VORTEX_MIX_INVOL_A +
 157                                 (((mix << 5) + ch) << 2), a);
 158                         hwwrite(vortex->mmio,
 159                                 VORTEX_MIX_INVOL_B +
 160                                 (((mix << 5) + ch) << 2), a);
 161                 } else
 162                         vortex_mix_killinput(vortex, mix, ch);
 163         }
 164 }
 165
 166 static int
 167 vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
 168 {
 169         int addr, temp;
 170         if (mixin >= 0)
 171                 addr = mixin;
 172         else
 173                 addr = mixin + 3;
 174         addr = ((mix << 3) + (addr >> 2)) << 2;
 175         temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
 176         return ((temp >> (mixin & 3)) & 1);
 177 }
 178 #endif
 179 static void
 180 vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
 181                          unsigned char vol)
 182 {
 183         int temp;
 184         hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
 185         if (1) {                /*if (this_10) */
 186                 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
 187                 if ((temp != 0x80) || (vol == 0x80))
 188                         return;
 189         }
 190         hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
 191 }
 192
 193 static void
 194 vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
 195                               int mixin, unsigned char vol)
 196 {
 197         int temp;
 198
 199         hwwrite(vortex->mmio,
 200                 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
 201         if (1) {                /* this_10, initialized to 1. */
 202                 temp =
 203                     hwread(vortex->mmio,
 204                            VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
 205                 if ((temp != 0x80) || (vol == 0x80))
 206                         return;
 207         }
 208         hwwrite(vortex->mmio,
 209                 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
 210 }
 211
 212 static void
 213 vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
 214 {
 215         int temp, addr;
 216
 217         if (mixin < 0)
 218                 addr = (mixin + 3);
 219         else
 220                 addr = mixin;
 221         addr = ((mix << 3) + (addr >> 2)) << 2;
 222         temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
 223         if (en)
 224                 temp |= (1 << (mixin & 3));
 225         else
 226                 temp &= ~(1 << (mixin & 3));
 227         /* Mute input. Astatic void crackling? */
 228         hwwrite(vortex->mmio,
 229                 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
 230         /* Looks like clear buffer. */
 231         hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
 232         hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
 233         /* Write enable bit. */
 234         hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
 235 }
 236
 237 static void
 238 vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
 239 {
 240         rampchs[mix] &= ~(1 << mixin);
 241         vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
 242         mchannels[mix] &= ~(1 << mixin);
 243         vortex_mix_setenablebit(vortex, mix, mixin, 0);
 244 }
 245
 246 static void
 247 vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
 248 {
 249         vortex_mix_killinput(vortex, mix, mixin);
 250         if ((mchannels[mix] & (1 << mixin)) == 0) {
 251                 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);        /*0x80 : mute */
 252                 mchannels[mix] |= (1 << mixin);
 253         }
 254         vortex_mix_setenablebit(vortex, mix, mixin, 1);
 255 }
 256
 257 static void
 258 vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
 259                         int ramp)
 260 {
 261         if (ramp) {
 262                 rampchs[mix] |= (1 << channel);
 263                 // Register callback.
 264                 //vortex_mix_startrampvolume(vortex);
 265                 vortex_mix_killinput(vortex, mix, channel);
 266         } else
 267                 vortex_mix_killinput(vortex, mix, channel);
 268 }
 269
 270 static int
 271 vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
 272 {
 273         int temp, lifeboat = 0, prev;
 274
 275         temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
 276         if ((temp & (1 << ch)) == 0) {
 277                 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
 278                 vortex_mixer_en_sr(vortex, ch);
 279                 return 1;
 280         }
 281         prev = VORTEX_MIXER_CHNBASE + (ch << 2);
 282         temp = hwread(vortex->mmio, prev);
 283         while (temp & 0x10) {
 284                 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
 285                 temp = hwread(vortex->mmio, prev);
 286                 //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp);
 287                 if ((++lifeboat) > 0xf) {
 288                         printk(KERN_ERR
 289                                "vortex_mixer_addWTD: lifeboat overflow\n");
 290                         return 0;
 291                 }
 292         }
 293         hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
 294         hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
 295         return 1;
 296 }
 297
 298 static int
 299 vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
 300 {
 301         int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
 302         //int esp1f=edi(while)=src, esp10=ch;
 303
 304         eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
 305         if (((1 << ch) & eax) == 0) {
 306                 printk(KERN_ERR "mix ALARM %x\n", eax);
 307                 return 0;
 308         }
 309         ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
 310         esp18 = hwread(vortex->mmio, ebp);
 311         if (esp18 & 0x10) {
 312                 ebx = (esp18 & 0xf);
 313                 if (mix == ebx) {
 314                         ebx = VORTEX_MIXER_RTBASE + (mix << 2);
 315                         edx = hwread(vortex->mmio, ebx);
 316                         //7b60
 317                         hwwrite(vortex->mmio, ebp, edx);
 318                         hwwrite(vortex->mmio, ebx, 0);
 319                 } else {
 320                         //7ad3
 321                         edx =
 322                             hwread(vortex->mmio,
 323                                    VORTEX_MIXER_RTBASE + (ebx << 2));
 324                         //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
 325                         while ((edx & 0xf) != mix) {
 326                                 if ((esi) > 0xf) {
 327                                         printk(KERN_ERR
 328                                                "vortex: mixdelWTD: error lifeboat overflow\n");
 329                                         return 0;
 330                                 }
 331                                 esp14 = ebx;
 332                                 ebx = edx & 0xf;
 333                                 ebp = ebx << 2;
 334                                 edx =
 335                                     hwread(vortex->mmio,
 336                                            VORTEX_MIXER_RTBASE + ebp);
 337                                 //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx);
 338                                 esi++;
 339                         }
 340                         //7b30
 341                         ebp = ebx << 2;
 342                         if (edx & 0x10) {       /* Delete entry in between others */
 343                                 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
 344                                 edx = hwread(vortex->mmio, ebx);
 345                                 //7b60
 346                                 hwwrite(vortex->mmio,
 347                                         VORTEX_MIXER_RTBASE + ebp, edx);
 348                                 hwwrite(vortex->mmio, ebx, 0);
 349                                 //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
 350                         } else {        /* Delete last entry */
 351                                 //7b83
 352                                 if (esp14 == -1)
 353                                         hwwrite(vortex->mmio,
 354                                                 VORTEX_MIXER_CHNBASE +
 355                                                 (ch << 2), esp18 & 0xef);
 356                                 else {
 357                                         ebx = (0xffffffe0 & edx) | (0xf & ebx);
 358                                         hwwrite(vortex->mmio,
 359                                                 VORTEX_MIXER_RTBASE +
 360                                                 (esp14 << 2), ebx);
 361                                         //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
 362                                 }
 363                                 hwwrite(vortex->mmio,
 364                                         VORTEX_MIXER_RTBASE + ebp, 0);
 365                                 return 1;
 366                         }
 367                 }
 368         } else {
 369                 //printk(KERN_INFO "removed last mix\n");
 370                 //7be0
 371                 vortex_mixer_dis_sr(vortex, ch);
 372                 hwwrite(vortex->mmio, ebp, 0);
 373         }
 374         return 1;
 375 }
 376
 377 static void vortex_mixer_init(vortex_t * vortex)
 378 {
 379         unsigned long addr;
 380         int x;
 381
 382         // FIXME: get rid of this crap.
 383         memset(mchannels, 0, NR_MIXOUT * sizeof(int));
 384         memset(rampchs, 0, NR_MIXOUT * sizeof(int));
 385
 386         addr = VORTEX_MIX_SMP + 0x17c;
 387         for (x = 0x5f; x >= 0; x--) {
 388                 hwwrite(vortex->mmio, addr, 0);
 389                 addr -= 4;
 390         }
 391         addr = VORTEX_MIX_ENIN + 0x1fc;
 392         for (x = 0x7f; x >= 0; x--) {
 393                 hwwrite(vortex->mmio, addr, 0);
 394                 addr -= 4;
 395         }
 396         addr = VORTEX_MIX_SMP + 0x17c;
 397         for (x = 0x5f; x >= 0; x--) {
 398                 hwwrite(vortex->mmio, addr, 0);
 399                 addr -= 4;
 400         }
 401         addr = VORTEX_MIX_INVOL_A + 0x7fc;
 402         for (x = 0x1ff; x >= 0; x--) {
 403                 hwwrite(vortex->mmio, addr, 0x80);
 404                 addr -= 4;
 405         }
 406         addr = VORTEX_MIX_VOL_A + 0x3c;
 407         for (x = 0xf; x >= 0; x--) {
 408                 hwwrite(vortex->mmio, addr, 0x80);
 409                 addr -= 4;
 410         }
 411         addr = VORTEX_MIX_INVOL_B + 0x7fc;
 412         for (x = 0x1ff; x >= 0; x--) {
 413                 hwwrite(vortex->mmio, addr, 0x80);
 414                 addr -= 4;
 415         }
 416         addr = VORTEX_MIX_VOL_B + 0x3c;
 417         for (x = 0xf; x >= 0; x--) {
 418                 hwwrite(vortex->mmio, addr, 0x80);
 419                 addr -= 4;
 420         }
 421         addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
 422         for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
 423                 hwwrite(vortex->mmio, addr, 0x0);
 424                 addr -= 4;
 425         }
 426         hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
 427
 428         /* Set clipping ceiling (this may be all wrong). */
 429         /*
 430         for (x = 0; x > 0x80; x++) {
 431                 hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff);
 432         }
 433         */
 434         /*
 435            call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____
 436            Register ISR callback for volume smooth fade out.
 437            Maybe this avoids clicks when press "stop" ?
 438          */
 439 }
 440
 441 /*  SRC (CAsp4Src.s and CAsp4SrcBlock) */
 442
 443 static void vortex_src_en_sr(vortex_t * vortex, int channel)
 444 {
 445         hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
 446                 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
 447 }
 448
 449 static void vortex_src_dis_sr(vortex_t * vortex, int channel)
 450 {
 451         hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
 452                 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
 453 }
 454
 455 static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
 456 {
 457         int i;
 458
 459         for (i = 0x1f; i >= 0; i--)
 460                 hwwrite(vortex->mmio,
 461                         VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
 462         hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
 463         hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
 464 }
 465
 466 static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
 467 {
 468         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
 469         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
 470         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
 471 }
 472
 473 static void
 474 vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
 475 {
 476         int temp;
 477
 478         temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
 479         if (en)
 480                 temp |= 1 << src;
 481         else
 482                 temp &= ~(1 << src);
 483         hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
 484 }
 485
 486 static int
 487 vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
 488 {
 489         int temp, lifeboat = 0;
 490
 491         do {
 492                 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
 493                 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
 494                 if ((++lifeboat) > 0x9) {
 495                         printk(KERN_ERR "Vortex: Src cvr fail\n");
 496                         break;
 497                 }
 498         }
 499         while (temp != ratio);
 500         return temp;
 501 }
 502
 503 #if 0
 504 static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
 505 {
 506         int temp;
 507
 508         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
 509         hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
 510         temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
 511         if (temp & 0x200)
 512                 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
 513                         temp & ~0x200L);
 514 }
 515
 516 static void
 517 vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
 518 {
 519         int temp, a;
 520
 521         if ((ratio & 0x10000) && (ratio != 0x10000)) {
 522                 if (ratio & 0x3fff)
 523                         a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
 524                 else
 525                         a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
 526         } else
 527                 a = 0xc;
 528         temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
 529         if (((temp >> 4) & 0xf) != a)
 530                 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
 531                         (temp & 0xf) | ((a & 0xf) << 4));
 532
 533         vortex_src_persist_convratio(vortex, src, ratio);
 534 }
 535
 536 static int
 537 vortex_src_checkratio(vortex_t * vortex, unsigned char src,
 538                       unsigned int desired_ratio)
 539 {
 540         int hw_ratio, lifeboat = 0;
 541
 542         hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
 543
 544         while (hw_ratio != desired_ratio) {
 545                 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
 546
 547                 if ((lifeboat++) > 15) {
 548                         printk(KERN_ERR "Vortex: could not set src-%d from %d to %d\n",
 549                                src, hw_ratio, desired_ratio);
 550                         break;
 551                 }
 552         }
 553
 554         return hw_ratio;
 555 }
 556
 557 #endif
 558 /*
 559  Objective: Set samplerate for given SRC module.
 560  Arguments:
 561         card:   pointer to vortex_t strcut.
 562         src:    Integer index of the SRC module.
 563         cr:             Current sample rate conversion factor.
 564         b:              unknown 16 bit value.
 565         sweep:  Enable Samplerate fade from cr toward tr flag.
 566         dirplay: 1: playback, 0: recording.
 567         sl:             Slow Lock flag.
 568         tr:             Target samplerate conversion.
 569         thsource: Throttle source flag (no idea what that means).
 570 */
 571 static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
 572                         unsigned int cr, unsigned int b, int sweep, int d,
 573                         int dirplay, int sl, unsigned int tr, int thsource)
 574 {
 575         // noplayback: d=2,4,7,0xa,0xb when using first 2 src's.
 576         // c: enables pitch sweep.
 577         // looks like g is c related. Maybe g is a sweep parameter ?
 578         // g = cvr
 579         // dirplay: 0 = recording, 1 = playback
 580         // d = src hw index.
 581
 582         int esi, ebp = 0, esp10;
 583
 584         vortex_src_flushbuffers(card, src);
 585
 586         if (sweep) {
 587                 if ((tr & 0x10000) && (tr != 0x10000)) {
 588                         tr = 0;
 589                         esi = 0x7;
 590                 } else {
 591                         if ((((short)tr) < 0) && (tr != 0x8000)) {
 592                                 tr = 0;
 593                                 esi = 0x8;
 594                         } else {
 595                                 tr = 1;
 596                                 esi = 0xc;
 597                         }
 598                 }
 599         } else {
 600                 if ((cr & 0x10000) && (cr != 0x10000)) {
 601                         tr = 0; /*ebx = 0 */
 602                         esi = 0x11 - ((cr >> 0xe) & 7);
 603                         if (cr & 0x3fff)
 604                                 esi -= 1;
 605                         else
 606                                 esi -= 2;
 607                 } else {
 608                         tr = 1;
 609                         esi = 0xc;
 610                 }
 611         }
 612         vortex_src_cleardrift(card, src);
 613         vortex_src_set_throttlesource(card, src, thsource);
 614
 615         if ((dirplay == 0) && (sweep == 0)) {
 616                 if (tr)
 617                         esp10 = 0xf;
 618                 else
 619                         esp10 = 0xc;
 620                 ebp = 0;
 621         } else {
 622                 if (tr)
 623                         ebp = 0xf;
 624                 else
 625                         ebp = 0xc;
 626                 esp10 = 0;
 627         }
 628         hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
 629                 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
 630         /* 0xc0   esi=0xc c=f=0 d=0 */
 631         vortex_src_persist_convratio(card, src, cr);
 632         hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
 633         /* 0   b=0 */
 634         hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
 635                 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
 636         /* 0x30f00 e=g=1 esp10=0 ebp=f */
 637         //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp);
 638 }
 639
 640 static void vortex_srcblock_init(vortex_t * vortex)
 641 {
 642         unsigned long addr;
 643         int x;
 644         hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
 645         /*
 646            for (x=0; x<0x10; x++) {
 647            vortex_src_init(&vortex_src[x], x);
 648            }
 649          */
 650         //addr = 0xcc3c;
 651         //addr = 0x26c3c;
 652         addr = VORTEX_SRC_RTBASE + 0x3c;
 653         for (x = 0xf; x >= 0; x--) {
 654                 hwwrite(vortex->mmio, addr, 0);
 655                 addr -= 4;
 656         }
 657         //addr = 0xcc94;
 658         //addr = 0x26c94;
 659         addr = VORTEX_SRC_CHNBASE + 0x54;
 660         for (x = 0x15; x >= 0; x--) {
 661                 hwwrite(vortex->mmio, addr, 0);
 662                 addr -= 4;
 663         }
 664 }
 665
 666 static int
 667 vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
 668 {
 669         int temp, lifeboat = 0, prev;
 670         // esp13 = src
 671
 672         temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
 673         if ((temp & (1 << ch)) == 0) {
 674                 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
 675                 vortex_src_en_sr(vortex, ch);
 676                 return 1;
 677         }
 678         prev = VORTEX_SRC_CHNBASE + (ch << 2);  /*ebp */
 679         temp = hwread(vortex->mmio, prev);
 680         //while (temp & NR_SRC) {
 681         while (temp & 0x10) {
 682                 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */
 683                 //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/
 684                 temp = hwread(vortex->mmio, prev);
 685                 //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp);
 686                 if ((++lifeboat) > 0xf) {
 687                         printk(KERN_ERR
 688                                "vortex_src_addWTD: lifeboat overflow\n");
 689                         return 0;
 690                 }
 691         }
 692         hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
 693         //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC);
 694         hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
 695         return 1;
 696 }
 697
 698 static int
 699 vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
 700 {
 701         int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
 702         //int esp1f=edi(while)=src, esp10=ch;
 703
 704         eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
 705         if (((1 << ch) & eax) == 0) {
 706                 printk(KERN_ERR "src alarm\n");
 707                 return 0;
 708         }
 709         ebp = VORTEX_SRC_CHNBASE + (ch << 2);
 710         esp18 = hwread(vortex->mmio, ebp);
 711         if (esp18 & 0x10) {
 712                 ebx = (esp18 & 0xf);
 713                 if (src == ebx) {
 714                         ebx = VORTEX_SRC_RTBASE + (src << 2);
 715                         edx = hwread(vortex->mmio, ebx);
 716                         //7b60
 717                         hwwrite(vortex->mmio, ebp, edx);
 718                         hwwrite(vortex->mmio, ebx, 0);
 719                 } else {
 720                         //7ad3
 721                         edx =
 722                             hwread(vortex->mmio,
 723                                    VORTEX_SRC_RTBASE + (ebx << 2));
 724                         //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
 725                         while ((edx & 0xf) != src) {
 726                                 if ((esi) > 0xf) {
 727                                         printk
 728                                             ("vortex: srcdelWTD: error, lifeboat overflow\n");
 729                                         return 0;
 730                                 }
 731                                 esp14 = ebx;
 732                                 ebx = edx & 0xf;
 733                                 ebp = ebx << 2;
 734                                 edx =
 735                                     hwread(vortex->mmio,
 736                                            VORTEX_SRC_RTBASE + ebp);
 737                                 //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx);
 738                                 esi++;
 739                         }
 740                         //7b30
 741                         ebp = ebx << 2;
 742                         if (edx & 0x10) {       /* Delete entry in between others */
 743                                 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
 744                                 edx = hwread(vortex->mmio, ebx);
 745                                 //7b60
 746                                 hwwrite(vortex->mmio,
 747                                         VORTEX_SRC_RTBASE + ebp, edx);
 748                                 hwwrite(vortex->mmio, ebx, 0);
 749                                 //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
 750                         } else {        /* Delete last entry */
 751                                 //7b83
 752                                 if (esp14 == -1)
 753                                         hwwrite(vortex->mmio,
 754                                                 VORTEX_SRC_CHNBASE +
 755                                                 (ch << 2), esp18 & 0xef);
 756                                 else {
 757                                         ebx = (0xffffffe0 & edx) | (0xf & ebx);
 758                                         hwwrite(vortex->mmio,
 759                                                 VORTEX_SRC_RTBASE +
 760                                                 (esp14 << 2), ebx);
 761                                         //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
 762                                 }
 763                                 hwwrite(vortex->mmio,
 764                                         VORTEX_SRC_RTBASE + ebp, 0);
 765                                 return 1;
 766                         }
 767                 }
 768         } else {
 769                 //7be0
 770                 vortex_src_dis_sr(vortex, ch);
 771                 hwwrite(vortex->mmio, ebp, 0);
 772         }
 773         return 1;
 774 }
 775
 776  /*FIFO*/
 777
 778 static void
 779 vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
 780 {
 781         for (x--; x >= 0; x--)
 782                 hwwrite(vortex->mmio,
 783                         VORTEX_FIFO_ADBDATA +
 784                         (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
 785 }
 786
 787 #if 0
 788 static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
 789 {
 790         vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
 791 #ifdef CHIP_AU8820
 792         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
 793                 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
 794 #else
 795         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
 796                 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
 797 #endif
 798 }
 799 #endif
 800 static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
 801 {
 802         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
 803                 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
 804                  0xffffffef) | ((1 & en) << 4) | FIFO_U1);
 805 }
 806
 807 static void
 808 vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int b, int priority,
 809                        int empty, int valid, int f)
 810 {
 811         int temp, lifeboat = 0;
 812         //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
 813         int this_4 = 0x2;
 814         /* f seems priority related.
 815          * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
 816          * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
 817          * is never called, thus the f related bits remain a mystery for now.
 818          */
 819         do {
 820                 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
 821                 if (lifeboat++ > 0xbb8) {
 822                         printk(KERN_ERR
 823                                "Vortex: vortex_fifo_setadbctrl fail\n");
 824                         break;
 825                 }
 826         }
 827         while (temp & FIFO_RDONLY);
 828
 829         // AU8830 semes to take some special care about fifo content (data).
 830         // But i'm just to lazy to translate that :)
 831         if (valid) {
 832                 if ((temp & FIFO_VALID) == 0) {
 833                         //this_8[fifo] = 0;
 834                         vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);      // this_4
 835 #ifdef CHIP_AU8820
 836                         temp = (this_4 & 0x1f) << 0xb;
 837 #else
 838                         temp = (this_4 & 0x3f) << 0xc;
 839 #endif
 840                         temp = (temp & 0xfffffffd) | ((b & 1) << 1);
 841                         temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
 842                         temp = (temp & 0xffffffef) | ((valid & 1) << 4);
 843                         temp |= FIFO_U1;
 844                         temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
 845 #ifdef CHIP_AU8820
 846                         temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
 847 #endif
 848 #ifdef CHIP_AU8830
 849                         temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
 850                         temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
 851 #endif
 852 #ifdef CHIP_AU8810
 853                         temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
 854                         temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
 855 #endif
 856                 }
 857         } else {
 858                 if (temp & FIFO_VALID) {
 859 #ifdef CHIP_AU8820
 860                         temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
 861 #endif
 862 #ifdef CHIP_AU8830
 863                         temp =
 864                             ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
 865 #endif
 866 #ifdef CHIP_AU8810
 867                         temp =
 868                             ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
 869 #endif
 870                 } else
 871                         /*if (this_8[fifo]) */
 872                         vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
 873         }
 874         hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
 875         hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
 876 }
 877
 878 #ifndef CHIP_AU8810
 879 static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
 880 {
 881         if (x < 1)
 882                 return;
 883         for (x--; x >= 0; x--)
 884                 hwwrite(vortex->mmio,
 885                         VORTEX_FIFO_WTDATA +
 886                         (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
 887 }
 888
 889 static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
 890 {
 891         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
 892 #ifdef CHIP_AU8820
 893         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
 894                 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
 895 #else
 896         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
 897                 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
 898 #endif
 899 }
 900
 901 static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
 902 {
 903         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
 904                 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
 905                  0xffffffef) | ((en & 1) << 4) | FIFO_U1);
 906 }
 907
 908 static void
 909 vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
 910                       int empty, int valid, int f)
 911 {
 912         int temp = 0, lifeboat = 0;
 913         int this_4 = 2;
 914
 915         do {
 916                 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
 917                 if (lifeboat++ > 0xbb8) {
 918                         printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail\n");
 919                         break;
 920                 }
 921         }
 922         while (temp & FIFO_RDONLY);
 923
 924         if (valid) {
 925                 if ((temp & FIFO_VALID) == 0) {
 926                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);       // this_4
 927 #ifdef CHIP_AU8820
 928                         temp = (this_4 & 0x1f) << 0xb;
 929 #else
 930                         temp = (this_4 & 0x3f) << 0xc;
 931 #endif
 932                         temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
 933                         temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
 934                         temp = (temp & 0xffffffef) | ((valid & 1) << 4);
 935                         temp |= FIFO_U1;
 936                         temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
 937 #ifdef CHIP_AU8820
 938                         temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
 939 #endif
 940 #ifdef CHIP_AU8830
 941                         temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
 942                         temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
 943 #endif
 944 #ifdef CHIP_AU8810
 945                         temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
 946                         temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
 947 #endif
 948                 }
 949         } else {
 950                 if (temp & FIFO_VALID) {
 951 #ifdef CHIP_AU8820
 952                         temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
 953 #endif
 954 #ifdef CHIP_AU8830
 955                         temp =
 956                             ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
 957 #endif
 958 #ifdef CHIP_AU8810
 959                         temp =
 960                             ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
 961 #endif
 962                 } else
 963                         /*if (this_8[fifo]) */
 964                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
 965         }
 966         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
 967         hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
 968
 969 /*
 970     do {
 971                 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
 972                 if (lifeboat++ > 0xbb8) {
 973                         printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail (hanging)\n");
 974                         break;
 975                 }
 976     } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF));
 977
 978
 979         if (valid) {
 980                 if (temp & FIFO_VALID) {
 981                         temp = 0x40000;
 982                         //temp |= 0x08000000;
 983                         //temp |= 0x10000000;
 984                         //temp |= 0x04000000;
 985                         //temp |= 0x00400000;
 986                         temp |= 0x1c400000;
 987                         temp &= 0xFFFFFFF3;
 988                         temp &= 0xFFFFFFEF;
 989                         temp |= (valid & 1) << 4;
 990                         hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
 991                         return;
 992                 } else {
 993                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
 994                         return;
 995                 }
 996         } else {
 997                 temp &= 0xffffffef;
 998                 temp |= 0x08000000;
 999                 temp |= 0x10000000;
1000                 temp |= 0x04000000;
1001                 temp |= 0x00400000;
1002                 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1003                 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
1004                 //((temp >> 6) & 0x3f)
1005
1006                 priority = 0;
1007                 if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0)
1008                         vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
1009                 valid = 0xfb;
1010                 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1011                 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1012                 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1013                 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1014                 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1015                 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1016         }
1017
1018         */
1019
1020         /*
1021            temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1022            temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1023            temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1024            temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1025            temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1026            #ifdef FIFO_BITS
1027            temp = temp | FIFO_BITS | 40000;
1028            #endif
1029            // 0x1c440010, 0x1c400000
1030            hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1031          */
1032 }
1033
1034 #endif
1035 static void vortex_fifo_init(vortex_t * vortex)
1036 {
1037         int x;
1038         unsigned long addr;
1039
1040         /* ADB DMA channels fifos. */
1041         addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
1042         for (x = NR_ADB - 1; x >= 0; x--) {
1043                 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
1044                 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
1045                         printk(KERN_ERR "bad adb fifo reset!");
1046                 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
1047                 addr -= 4;
1048         }
1049
1050 #ifndef CHIP_AU8810
1051         /* WT DMA channels fifos. */
1052         addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
1053         for (x = NR_WT - 1; x >= 0; x--) {
1054                 hwwrite(vortex->mmio, addr, FIFO_U0);
1055                 if (hwread(vortex->mmio, addr) != FIFO_U0)
1056                         printk(KERN_ERR
1057                                "bad wt fifo reset (0x%08lx, 0x%08x)!\n",
1058                                addr, hwread(vortex->mmio, addr));
1059                 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
1060                 addr -= 4;
1061         }
1062 #endif
1063         /* trigger... */
1064 #ifdef CHIP_AU8820
1065         hwwrite(vortex->mmio, 0xf8c0, 0xd03);   //0x0843 0xd6b
1066 #else
1067 #ifdef CHIP_AU8830
1068         hwwrite(vortex->mmio, 0x17000, 0x61);   /* wt a */
1069         hwwrite(vortex->mmio, 0x17004, 0x61);   /* wt b */
1070 #endif
1071         hwwrite(vortex->mmio, 0x17008, 0x61);   /* adb */
1072 #endif
1073 }
1074
1075 /* ADBDMA */
1076
1077 static void vortex_adbdma_init(vortex_t * vortex)
1078 {
1079 }
1080
1081 static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
1082 {
1083         stream_t *dma = &vortex->dma_adb[adbdma];
1084
1085         hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1086                 dma->dma_ctrl);
1087 }
1088
1089 static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
1090 {
1091         stream_t *dma = &vortex->dma_adb[adbdma];
1092         //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2))));
1093         hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
1094                 sb << ((0xf - (adbdma & 0xf)) * 2));
1095         dma->period_real = dma->period_virt = sb;
1096 }
1097
1098 static void
1099 vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
1100                          snd_pcm_sgbuf_t * sgbuf, int psize, int count)
1101 {
1102         stream_t *dma = &vortex->dma_adb[adbdma];
1103
1104         if (sgbuf == NULL) {
1105                 printk(KERN_INFO "vortex: FATAL: sgbuf is NULL!\n");
1106                 return;
1107         }
1108         //printk(KERN_INFO "vortex: page count = %d, tblcount = %d\n", count, sgbuf->tblsize);
1109
1110         dma->period_bytes = psize;
1111         dma->nr_periods = count;
1112         dma->sgbuf = sgbuf;
1113
1114         dma->cfg0 = 0;
1115         dma->cfg1 = 0;
1116         switch (count) {
1117                 /* Four or more pages */
1118         default:
1119         case 4:
1120                 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
1121                 hwwrite(vortex->mmio,
1122                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
1123                         snd_sgbuf_get_addr(sgbuf, psize * 3));
1124                 /* 3 pages */
1125         case 3:
1126                 dma->cfg0 |= 0x12000000;
1127                 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1128                 hwwrite(vortex->mmio,
1129                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
1130                         snd_sgbuf_get_addr(sgbuf, psize * 2));
1131                 /* 2 pages */
1132         case 2:
1133                 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
1134                 hwwrite(vortex->mmio,
1135                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
1136                         snd_sgbuf_get_addr(sgbuf, psize));
1137                 /* 1 page */
1138         case 1:
1139                 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1140                 hwwrite(vortex->mmio,
1141                         VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
1142                         snd_sgbuf_get_addr(sgbuf, 0));
1143                 break;
1144         }
1145         //printk("vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n", dma->cfg0, dma->cfg1);
1146         hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
1147         hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1148
1149         vortex_adbdma_setfirstbuffer(vortex, adbdma);
1150         vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
1151 }
1152
1153 static void
1154 vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
1155                       int fmt, int d, unsigned long offset)
1156 {
1157         stream_t *dma = &vortex->dma_adb[adbdma];
1158
1159         dma->dma_unknown = d;
1160         dma->dma_ctrl =
1161             ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1162         /* Enable PCMOUT interrupts. */
1163         dma->dma_ctrl =
1164             (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1165
1166         dma->dma_ctrl =
1167             (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1168         dma->dma_ctrl =
1169             (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1170
1171         hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1172                 dma->dma_ctrl);
1173         hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
1174 }
1175
1176 static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
1177 {
1178         stream_t *dma = &vortex->dma_adb[adbdma];
1179         int page, p, pp, delta, i;
1180
1181         page =
1182             (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
1183              ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1184         if (dma->nr_periods >= 4)
1185                 delta = (page - dma->period_real) & 3;
1186         else {
1187                 delta = (page - dma->period_real);
1188                 if (delta < 0)
1189                         delta += dma->nr_periods;
1190         }
1191         if (delta == 0)
1192                 return 0;
1193
1194         /* refresh hw page table */
1195         if (dma->nr_periods > 4) {
1196                 for (i = 0; i < delta; i++) {
1197                         /* p: audio buffer page index */
1198                         p = dma->period_virt + i + 4;
1199                         if (p >= dma->nr_periods)
1200                                 p -= dma->nr_periods;
1201                         /* pp: hardware DMA page index. */
1202                         pp = dma->period_real + i;
1203                         if (pp >= 4)
1204                                 pp -= 4;
1205                         //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
1206                         hwwrite(vortex->mmio,
1207                                 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1208                                 snd_sgbuf_get_addr(dma->sgbuf,
1209                                 dma->period_bytes * p));
1210                         /* Force write thru cache. */
1211                         hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
1212                                (((adbdma << 2) + pp) << 2));
1213                 }
1214         }
1215         dma->period_virt += delta;
1216         dma->period_real = page;
1217         if (dma->period_virt >= dma->nr_periods)
1218                 dma->period_virt -= dma->nr_periods;
1219         if (delta != 1)
1220                 printk(KERN_INFO "vortex: %d virt=%d, real=%d, delta=%d\n",
1221                        adbdma, dma->period_virt, dma->period_real, delta);
1222
1223         return delta;
1224 }
1225
1226 static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1227 {
1228         stream_t *dma = &vortex->dma_adb[adbdma];
1229         int temp;
1230
1231         temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1232         temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK);
1233         return (temp);
1234 }
1235
1236 static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
1237 {
1238         int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ;
1239         stream_t *dma = &vortex->dma_adb[adbdma];
1240
1241         switch (dma->fifo_status) {
1242         case FIFO_START:
1243                 vortex_fifo_setadbvalid(vortex, adbdma,
1244                                         dma->fifo_enabled ? 1 : 0);
1245                 break;
1246         case FIFO_STOP:
1247                 this_8 = 1;
1248                 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1249                         dma->dma_ctrl);
1250                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1251                                        this_4, this_8,
1252                                        dma->fifo_enabled ? 1 : 0, 0);
1253                 break;
1254         case FIFO_PAUSE:
1255                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1256                                        this_4, this_8,
1257                                        dma->fifo_enabled ? 1 : 0, 0);
1258                 break;
1259         }
1260         dma->fifo_status = FIFO_START;
1261 }
1262
1263 static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
1264 {
1265         stream_t *dma = &vortex->dma_adb[adbdma];
1266
1267         int this_8 = 1, this_4 = 0;
1268         switch (dma->fifo_status) {
1269         case FIFO_STOP:
1270                 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1271                         dma->dma_ctrl);
1272                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1273                                        this_4, this_8,
1274                                        dma->fifo_enabled ? 1 : 0, 0);
1275                 break;
1276         case FIFO_PAUSE:
1277                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1278                                        this_4, this_8,
1279                                        dma->fifo_enabled ? 1 : 0, 0);
1280                 break;
1281         }
1282         dma->fifo_status = FIFO_START;
1283 }
1284
1285 static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
1286 {
1287         stream_t *dma = &vortex->dma_adb[adbdma];
1288
1289         int this_8 = 0, this_4 = 0;
1290         switch (dma->fifo_status) {
1291         case FIFO_START:
1292                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1293                                        this_4, this_8, 0, 0);
1294                 break;
1295         case FIFO_STOP:
1296                 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1297                         dma->dma_ctrl);
1298                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1299                                        this_4, this_8, 0, 0);
1300                 break;
1301         }
1302         dma->fifo_status = FIFO_PAUSE;
1303 }
1304
1305 #if 0                           // Using pause instead
1306 static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
1307 {
1308         stream_t *dma = &vortex->dma_adb[adbdma];
1309
1310         int this_4 = 0, this_8 = 0;
1311         if (dma->fifo_status == FIFO_START)
1312                 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1313                                        this_4, this_8, 0, 0);
1314         else if (dma->fifo_status == FIFO_STOP)
1315                 return;
1316         dma->fifo_status = FIFO_STOP;
1317         dma->fifo_enabled = 0;
1318 }
1319
1320 #endif
1321 /* WTDMA */
1322
1323 #ifndef CHIP_AU8810
1324 static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
1325 {
1326         //int this_7c=dma_ctrl;
1327         stream_t *dma = &vortex->dma_wt[wtdma];
1328
1329         hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1330 }
1331
1332 static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
1333 {
1334         stream_t *dma = &vortex->dma_wt[wtdma];
1335         //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2)));
1336         hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
1337                 sb << ((0xf - (wtdma & 0xf)) * 2));
1338         dma->period_real = dma->period_virt = sb;
1339 }
1340
1341 static void
1342 vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
1343                         snd_pcm_sgbuf_t * sgbuf, int psize, int count)
1344 {
1345         stream_t *dma = &vortex->dma_wt[wtdma];
1346
1347         dma->period_bytes = psize;
1348         dma->nr_periods = count;
1349         dma->sgbuf = sgbuf;
1350
1351         dma->cfg0 = 0;
1352         dma->cfg1 = 0;
1353         switch (count) {
1354                 /* Four or more pages */
1355         default:
1356         case 4:
1357                 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
1358                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc,
1359                         snd_sgbuf_get_addr(sgbuf, psize * 3));
1360                 /* 3 pages */
1361         case 3:
1362                 dma->cfg0 |= 0x12000000;
1363                 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1364                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4)  + 0x8,
1365                         snd_sgbuf_get_addr(sgbuf, psize * 2));
1366                 /* 2 pages */
1367         case 2:
1368                 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
1369                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4,
1370                         snd_sgbuf_get_addr(sgbuf, psize));
1371                 /* 1 page */
1372         case 1:
1373                 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1374                 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1375                         snd_sgbuf_get_addr(sgbuf, 0));
1376                 break;
1377         }
1378         hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1379         hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1380
1381         vortex_wtdma_setfirstbuffer(vortex, wtdma);
1382         vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
1383 }
1384
1385 static void
1386 vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
1387                      /*int e, */ unsigned long offset)
1388 {
1389         stream_t *dma = &vortex->dma_wt[wtdma];
1390
1391         //dma->this_08 = e;
1392         dma->dma_unknown = d;
1393         dma->dma_ctrl = 0;
1394         dma->dma_ctrl =
1395             ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1396         /* PCMOUT interrupt */
1397         dma->dma_ctrl =
1398             (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1399         /* Always playback. */
1400         dma->dma_ctrl |= (1 << DIR_SHIFT);
1401         /* Audio Format */
1402         dma->dma_ctrl =
1403             (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1404         /* Write into hardware */
1405         hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1406 }
1407
1408 static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
1409 {
1410         stream_t *dma = &vortex->dma_wt[wtdma];
1411         int page, p, pp, delta, i;
1412
1413         page =
1414             (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) &
1415              WT_SUBBUF_MASK)
1416             >> WT_SUBBUF_SHIFT;
1417         if (dma->nr_periods >= 4)
1418                 delta = (page - dma->period_real) & 3;
1419         else {
1420                 delta = (page - dma->period_real);
1421                 if (delta < 0)
1422                         delta += dma->nr_periods;
1423         }
1424         if (delta == 0)
1425                 return 0;
1426
1427         /* refresh hw page table */
1428         if (dma->nr_periods > 4) {
1429                 for (i = 0; i < delta; i++) {
1430                         /* p: audio buffer page index */
1431                         p = dma->period_virt + i + 4;
1432                         if (p >= dma->nr_periods)
1433                                 p -= dma->nr_periods;
1434                         /* pp: hardware DMA page index. */
1435                         pp = dma->period_real + i;
1436                         if (pp >= 4)
1437                                 pp -= 4;
1438                         hwwrite(vortex->mmio,
1439                                 VORTEX_WTDMA_BUFBASE +
1440                                 (((wtdma << 2) + pp) << 2),
1441                                 snd_sgbuf_get_addr(dma->sgbuf, dma->period_bytes * p));
1442                         /* Force write thru cache. */
1443                         hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
1444                                (((wtdma << 2) + pp) << 2));
1445                 }
1446         }
1447         dma->period_virt += delta;
1448         if (dma->period_virt >= dma->nr_periods)
1449                 dma->period_virt -= dma->nr_periods;
1450         dma->period_real = page;
1451
1452         if (delta != 1)
1453                 printk(KERN_WARNING "vortex: wt virt = %d, delta = %d\n",
1454                        dma->period_virt, delta);
1455
1456         return delta;
1457 }
1458
1459 #if 0
1460 static void
1461 vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
1462 {
1463         int temp;
1464         temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1465         *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1466         *pos = temp & POS_MASK;
1467 }
1468
1469 static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
1470 {
1471         return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
1472                  POS_SHIFT) & POS_MASK);
1473 }
1474 #endif
1475 static int inline vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1476 {
1477         stream_t *dma = &vortex->dma_wt[wtdma];
1478         int temp;
1479
1480         temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1481         //temp = (temp & POS_MASK) + (((temp>>WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK)*(dma->cfg0&POS_MASK));
1482         temp = (temp & POS_MASK) + ((dma->period_virt) * (dma->period_bytes));
1483         return temp;
1484 }
1485
1486 static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
1487 {
1488         stream_t *dma = &vortex->dma_wt[wtdma];
1489         int this_8 = 0, this_4 = 0;
1490
1491         switch (dma->fifo_status) {
1492         case FIFO_START:
1493                 vortex_fifo_setwtvalid(vortex, wtdma,
1494                                        dma->fifo_enabled ? 1 : 0);
1495                 break;
1496         case FIFO_STOP:
1497                 this_8 = 1;
1498                 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1499                         dma->dma_ctrl);
1500                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1501                                       this_4, this_8,
1502                                       dma->fifo_enabled ? 1 : 0, 0);
1503                 break;
1504         case FIFO_PAUSE:
1505                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1506                                       this_4, this_8,
1507                                       dma->fifo_enabled ? 1 : 0, 0);
1508                 break;
1509         }
1510         dma->fifo_status = FIFO_START;
1511 }
1512
1513 static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
1514 {
1515         stream_t *dma = &vortex->dma_wt[wtdma];
1516
1517         int this_8 = 0, this_4 = 0;
1518         switch (dma->fifo_status) {
1519         case FIFO_STOP:
1520                 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1521                         dma->dma_ctrl);
1522                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1523                                       this_4, this_8,
1524                                       dma->fifo_enabled ? 1 : 0, 0);
1525                 break;
1526         case FIFO_PAUSE:
1527                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1528                                       this_4, this_8,
1529                                       dma->fifo_enabled ? 1 : 0, 0);
1530                 break;
1531         }
1532         dma->fifo_status = FIFO_START;
1533 }
1534
1535 static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
1536 {
1537         stream_t *dma = &vortex->dma_wt[wtdma];
1538
1539         int this_8 = 0, this_4 = 0;
1540         switch (dma->fifo_status) {
1541         case FIFO_START:
1542                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1543                                       this_4, this_8, 0, 0);
1544                 break;
1545         case FIFO_STOP:
1546                 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1547                         dma->dma_ctrl);
1548                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1549                                       this_4, this_8, 0, 0);
1550                 break;
1551         }
1552         dma->fifo_status = FIFO_PAUSE;
1553 }
1554
1555 static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
1556 {
1557         stream_t *dma = &vortex->dma_wt[wtdma];
1558
1559         int this_4 = 0, this_8 = 0;
1560         if (dma->fifo_status == FIFO_START)
1561                 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1562                                       this_4, this_8, 0, 0);
1563         else if (dma->fifo_status == FIFO_STOP)
1564                 return;
1565         dma->fifo_status = FIFO_STOP;
1566         dma->fifo_enabled = 0;
1567 }
1568
1569 #endif
1570 /* ADB Routes */
1571
1572 typedef int ADBRamLink;
1573 static void vortex_adb_init(vortex_t * vortex)
1574 {
1575         int i;
1576         /* it looks like we are writing more than we need to...
1577          * if we write what we are supposed to it breaks things... */
1578         hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
1579         for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++)
1580                 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
1581                         hwread(vortex->mmio,
1582                                VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
1583         for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) {
1584                 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
1585                         hwread(vortex->mmio,
1586                                VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
1587         }
1588 }
1589
1590 static void vortex_adb_en_sr(vortex_t * vortex, int channel)
1591 {
1592         hwwrite(vortex->mmio, VORTEX_ADB_SR,
1593                 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
1594 }
1595
1596 static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
1597 {
1598         hwwrite(vortex->mmio, VORTEX_ADB_SR,
1599                 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
1600 }
1601
1602 static void
1603 vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
1604                      ADBRamLink * route, int rnum)
1605 {
1606         int temp, prev, lifeboat = 0;
1607
1608         if ((rnum <= 0) || (route == NULL))
1609                 return;
1610         /* Write last routes. */
1611         rnum--;
1612         hwwrite(vortex->mmio,
1613                 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
1614                 ROUTE_MASK);
1615         while (rnum > 0) {
1616                 hwwrite(vortex->mmio,
1617                         VORTEX_ADB_RTBASE +
1618                         ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
1619                 rnum--;
1620         }
1621         /* Write first route. */
1622         temp =
1623             hwread(vortex->mmio,
1624                    VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1625         if (temp == ADB_MASK) {
1626                 /* First entry on this channel. */
1627                 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1628                         route[0]);
1629                 vortex_adb_en_sr(vortex, channel);
1630                 return;
1631         }
1632         /* Not first entry on this channel. Need to link. */
1633         do {
1634                 prev = temp;
1635                 temp =
1636                     hwread(vortex->mmio,
1637                            VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
1638                 if ((lifeboat++) > ADB_MASK) {
1639                         printk(KERN_ERR
1640                                "vortex_adb_addroutes: unending route! 0x%x\n",
1641                                *route);
1642                         return;
1643                 }
1644         }
1645         while (temp != ADB_MASK);
1646         hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
1647 }
1648
1649 static void
1650 vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
1651                      ADBRamLink route0, ADBRamLink route1)
1652 {
1653         int temp, lifeboat = 0, prev;
1654
1655         /* Find route. */
1656         temp =
1657             hwread(vortex->mmio,
1658                    VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1659         if (temp == (route0 & ADB_MASK)) {
1660                 temp =
1661                     hwread(vortex->mmio,
1662                            VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
1663                 if ((temp & ADB_MASK) == ADB_MASK)
1664                         vortex_adb_dis_sr(vortex, channel);
1665                 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1666                         temp);
1667                 return;
1668         }
1669         do {
1670                 prev = temp;
1671                 temp =
1672                     hwread(vortex->mmio,
1673                            VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
1674                 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
1675                         printk(KERN_ERR
1676                                "vortex_adb_delroutes: route not found! 0x%x\n",
1677                                route0);
1678                         return;
1679                 }
1680         }
1681         while (temp != (route0 & ADB_MASK));
1682         temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1683         if ((temp & ADB_MASK) == route1)
1684                 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1685         /* Make bridge over deleted route. */
1686         hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
1687 }
1688
1689 static void
1690 vortex_route(vortex_t * vortex, int en, unsigned char channel,
1691              unsigned char source, unsigned char dest)
1692 {
1693         ADBRamLink route;
1694
1695         route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1696         if (en) {
1697                 vortex_adb_addroutes(vortex, channel, &route, 1);
1698                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1699                     && (source >= OFFSET_SRCOUT))
1700                         vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1701                                           channel);
1702                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1703                          && (source >= OFFSET_MIXOUT))
1704                         vortex_mixer_addWTD(vortex,
1705                                             (source - OFFSET_MIXOUT), channel);
1706         } else {
1707                 vortex_adb_delroutes(vortex, channel, route, route);
1708                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1709                     && (source >= OFFSET_SRCOUT))
1710                         vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1711                                           channel);
1712                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1713                          && (source >= OFFSET_MIXOUT))
1714                         vortex_mixer_delWTD(vortex,
1715                                             (source - OFFSET_MIXOUT), channel);
1716         }
1717 }
1718
1719 #if 0
1720 static void
1721 vortex_routes(vortex_t * vortex, int en, unsigned char channel,
1722               unsigned char source, unsigned char dest0, unsigned char dest1)
1723 {
1724         ADBRamLink route[2];
1725
1726         route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
1727         route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
1728
1729         if (en) {
1730                 vortex_adb_addroutes(vortex, channel, route, 2);
1731                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1732                     && (source >= (OFFSET_SRCOUT)))
1733                         vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1734                                           channel);
1735                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1736                          && (source >= (OFFSET_MIXOUT)))
1737                         vortex_mixer_addWTD(vortex,
1738                                             (source - OFFSET_MIXOUT), channel);
1739         } else {
1740                 vortex_adb_delroutes(vortex, channel, route[0], route[1]);
1741                 if ((source < (OFFSET_SRCOUT + NR_SRC))
1742                     && (source >= (OFFSET_SRCOUT)))
1743                         vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1744                                           channel);
1745                 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1746                          && (source >= (OFFSET_MIXOUT)))
1747                         vortex_mixer_delWTD(vortex,
1748                                             (source - OFFSET_MIXOUT), channel);
1749         }
1750 }
1751
1752 #endif
1753 /* Route two sources to same target. Sources must be of same class !!! */
1754 static void
1755 vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
1756                 unsigned char source0, unsigned char source1,
1757                 unsigned char dest)
1758 {
1759         ADBRamLink route[2];
1760
1761         route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1762         route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1763
1764         if (dest < 0x10)
1765                 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20);      /* fifo A */
1766
1767         if (en) {
1768                 vortex_adb_addroutes(vortex, ch, route, 2);
1769                 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1770                     && (source0 >= OFFSET_SRCOUT)) {
1771                         vortex_src_addWTD(vortex,
1772                                           (source0 - OFFSET_SRCOUT), ch);
1773                         vortex_src_addWTD(vortex,
1774                                           (source1 - OFFSET_SRCOUT), ch);
1775                 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1776                            && (source0 >= OFFSET_MIXOUT)) {
1777                         vortex_mixer_addWTD(vortex,
1778                                             (source0 - OFFSET_MIXOUT), ch);
1779                         vortex_mixer_addWTD(vortex,
1780                                             (source1 - OFFSET_MIXOUT), ch);
1781                 }
1782         } else {
1783                 vortex_adb_delroutes(vortex, ch, route[0], route[1]);
1784                 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1785                     && (source0 >= OFFSET_SRCOUT)) {
1786                         vortex_src_delWTD(vortex,
1787                                           (source0 - OFFSET_SRCOUT), ch);
1788                         vortex_src_delWTD(vortex,
1789                                           (source1 - OFFSET_SRCOUT), ch);
1790                 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1791                            && (source0 >= OFFSET_MIXOUT)) {
1792                         vortex_mixer_delWTD(vortex,
1793                                             (source0 - OFFSET_MIXOUT), ch);
1794                         vortex_mixer_delWTD(vortex,
1795                                             (source1 - OFFSET_MIXOUT), ch);
1796                 }
1797         }
1798 }
1799
1800 /* Connection stuff */
1801
1802 // Connect adbdma to src('s).
1803 static void
1804 vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
1805                              unsigned char adbdma, unsigned char src)
1806 {
1807         vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
1808 }
1809
1810 // Connect SRC to mixin.
1811 static void
1812 vortex_connection_src_mixin(vortex_t * vortex, int en,
1813                             unsigned char channel, unsigned char src,
1814                             unsigned char mixin)
1815 {
1816         vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
1817 }
1818
1819 // Connect mixin with mix output.
1820 static void
1821 vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
1822                             unsigned char mix, int a)
1823 {
1824         if (en) {
1825                 vortex_mix_enableinput(vortex, mix, mixin);
1826                 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN);        // added to original code.
1827         } else
1828                 vortex_mix_disableinput(vortex, mix, mixin, a);
1829 }
1830
1831 // Connect absolut address to mixin.
1832 static void
1833 vortex_connection_adb_mixin(vortex_t * vortex, int en,
1834                             unsigned char channel, unsigned char source,
1835                             unsigned char mixin)
1836 {
1837         vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
1838 }
1839
1840 static void
1841 vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
1842                              unsigned char src, unsigned char adbdma)
1843 {
1844         vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
1845 }
1846
1847 static void
1848 vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
1849                                  unsigned char ch, unsigned char src0,
1850                                  unsigned char src1, unsigned char adbdma)
1851 {
1852
1853         vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
1854                         ADB_DMA(adbdma));
1855 }
1856
1857 // mix to absolut address.
1858 static void
1859 vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
1860                           unsigned char mix, unsigned char dest)
1861 {
1862         vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
1863         vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN);    // added to original code.
1864 }
1865
1866 // mixer to src.
1867 static void
1868 vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
1869                           unsigned char mix, unsigned char src)
1870 {
1871         vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
1872         vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN);    // added to original code.
1873 }
1874
1875 #if 0
1876 static void
1877 vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
1878                                  unsigned char channel,
1879                                  unsigned char adbdma, unsigned char src0,
1880                                  unsigned char src1)
1881 {
1882         vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
1883                       ADB_SRCIN(src0), ADB_SRCIN(src1));
1884 }
1885
1886 // Connect two mix to AdbDma.
1887 static void
1888 vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
1889                                  unsigned char ch, unsigned char mix0,
1890                                  unsigned char mix1, unsigned char adbdma)
1891 {
1892
1893         ADBRamLink routes[2];
1894         routes[0] =
1895             (((mix0 +
1896                OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
1897         routes[1] =
1898             (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
1899                                                                    0x20) &
1900                                                                   ADB_MASK);
1901         if (en) {
1902                 vortex_adb_addroutes(vortex, ch, routes, 0x2);
1903                 vortex_mixer_addWTD(vortex, mix0, ch);
1904                 vortex_mixer_addWTD(vortex, mix1, ch);
1905         } else {
1906                 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
1907                 vortex_mixer_delWTD(vortex, mix0, ch);
1908                 vortex_mixer_delWTD(vortex, mix1, ch);
1909         }
1910 }
1911 #endif
1912
1913 /* CODEC connect. */
1914
1915 static void
1916 vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
1917 {
1918 #ifdef CHIP_AU8820
1919         vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1920         vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1921 #else
1922 #if 1
1923         // Connect front channels through EQ.
1924         vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
1925         vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
1926         /* Lower volume, since EQ has some gain. */
1927         vortex_mix_setvolumebyte(vortex, mixers[0], 0);
1928         vortex_mix_setvolumebyte(vortex, mixers[1], 0);
1929         vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
1930         vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
1931
1932         /* Check if reg 0x28 has SDAC bit set. */
1933         if (VORTEX_IS_QUAD(vortex)) {
1934                 /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */
1935                 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
1936                                           ADB_CODECOUT(0 + 4));
1937                 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
1938                                           ADB_CODECOUT(1 + 4));
1939                 //printk("SDAC detected ");
1940         }
1941 #else
1942         // Use plain direct output to codec.
1943         vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1944         vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1945 #endif
1946 #endif
1947 }
1948
1949 static void
1950 vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
1951                         unsigned char mixin1)
1952 {
1953         /*
1954            Enable: 0x1, 0x1
1955            Channel: 0x11, 0x11
1956            ADB Source address: 0x48, 0x49
1957            Destination Asp4Topology_0x9c,0x98
1958          */
1959         vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
1960         vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
1961 }
1962
1963 // Higher level ADB audio path (de)allocator.
1964
1965 /* Resource manager */
1966 static int resnum[VORTEX_RESOURCE_LAST] =
1967     { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
1968 /*
1969  Checkout/Checkin resource of given type.
1970  resmap: resource map to be used. If NULL means that we want to allocate
1971  a DMA resource (root of all other resources of a dma channel).
1972  out: Mean checkout if != 0. Else mean Checkin resource.
1973  restype: Indicates type of resource to be checked in or out.
1974 */
1975 static char
1976 vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
1977 {
1978         int i, qty = resnum[restype], resinuse = 0;
1979
1980         if (out) {
1981                 /* Gather used resources by all streams. */
1982                 for (i = 0; i < NR_ADB; i++) {
1983                         resinuse |= vortex->dma_adb[i].resources[restype];
1984                 }
1985                 resinuse |= vortex->fixed_res[restype];
1986                 /* Find and take free resource. */
1987                 for (i = 0; i < qty; i++) {
1988                         if ((resinuse & (1 << i)) == 0) {
1989                                 if (resmap != NULL)
1990                                         resmap[restype] |= (1 << i);
1991                                 else
1992                                         vortex->dma_adb[i].resources[restype] |= (1 << i);
1993                                 //printk("vortex: ResManager: type %d out %d\n", restype, i);
1994                                 return i;
1995                         }
1996                 }
1997         } else {
1998                 if (resmap == NULL)
1999                         return -EINVAL;
2000                 /* Checkin first resource of type restype. */
2001                 for (i = 0; i < qty; i++) {
2002                         if (resmap[restype] & (1 << i)) {
2003                                 resmap[restype] &= ~(1 << i);
2004                                 //printk("vortex: ResManager: type %d in %d\n",restype, i);
2005                                 return i;
2006                         }
2007                 }
2008         }
2009         printk("vortex: FATAL: ResManager: resource type %d exhausted.\n", restype);
2010         return -ENOMEM;
2011 }
2012
2013 /* Default Connections  */
2014 static int
2015 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type);
2016
2017 static void vortex_connect_default(vortex_t * vortex, int en)
2018 {
2019         // Connect AC97 codec.
2020         vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2021                                   VORTEX_RESOURCE_MIXOUT);
2022         vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2023                                   VORTEX_RESOURCE_MIXOUT);
2024         if (VORTEX_IS_QUAD(vortex)) {
2025                 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2026                                           VORTEX_RESOURCE_MIXOUT);
2027                 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2028                                           VORTEX_RESOURCE_MIXOUT);
2029         }
2030         vortex_connect_codecplay(vortex, en, vortex->mixplayb);
2031
2032         vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2033                                   VORTEX_RESOURCE_MIXIN);
2034         vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2035                                   VORTEX_RESOURCE_MIXIN);
2036         vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
2037
2038         // Connect SPDIF
2039 #ifndef CHIP_AU8820
2040         vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2041                                   VORTEX_RESOURCE_MIXOUT);
2042         vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2043                                   VORTEX_RESOURCE_MIXOUT);
2044         vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
2045                                   ADB_SPDIFOUT(0));
2046         vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
2047                                   ADB_SPDIFOUT(1));
2048 #endif
2049         // Connect WT
2050 #ifndef CHIP_AU8810
2051         vortex_wt_connect(vortex, en);
2052 #endif
2053         // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now.
2054 #ifndef CHIP_AU8820
2055         vortex_Vort3D_connect(vortex, en);
2056 #endif
2057         // Connect I2S
2058
2059         // Connect DSP interface for SQ3500 turbo (not here i think...)
2060
2061         // Connect AC98 modem codec
2062
2063 }
2064
2065 /*
2066   Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
2067   are deallocated.
2068   dma: DMA engine routes to be deallocated when dma >= 0.
2069   nr_ch: Number of channels to be de/allocated.
2070   dir: direction of stream. Uses same values as substream->stream.
2071   type: Type of audio output/source (codec, spdif, i2s, dsp, etc)
2072   Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
2073 */
2074 static int
2075 vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type)
2076 {
2077         stream_t *stream;
2078         int i, en;
2079
2080         if ((nr_ch == 3)
2081             || ((dir == SNDRV_PCM_STREAM_CAPTURE) && (nr_ch > 2)))
2082                 return -EBUSY;
2083
2084         spin_lock(&vortex->lock);
2085         if (dma >= 0) {
2086                 en = 0;
2087                 vortex_adb_checkinout(vortex,
2088                                       vortex->dma_adb[dma].resources, en,
2089                                       VORTEX_RESOURCE_DMA);
2090         } else {
2091                 en = 1;
2092                 if ((dma =
2093                      vortex_adb_checkinout(vortex, NULL, en,
2094                                            VORTEX_RESOURCE_DMA)) < 0)
2095                         return -EBUSY;
2096         }
2097
2098         stream = &vortex->dma_adb[dma];
2099         stream->dma = dma;
2100         stream->dir = dir;
2101         stream->type = type;
2102
2103         /* PLAYBACK ROUTES. */
2104         if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
2105                 int src[4], mix[4], ch_top;
2106 #ifndef CHIP_AU8820
2107                 int a3d = 0;
2108 #endif
2109                 /* Get SRC and MIXER hardware resources. */
2110                 if (stream->type != VORTEX_PCM_SPDIF) {
2111                         for (i = 0; i < nr_ch; i++) {
2112                                 if ((src[i] = vortex_adb_checkinout(vortex,
2113                                                            stream->resources, en,
2114                                                            VORTEX_RESOURCE_SRC)) < 0) {
2115                                         memset(stream->resources, 0,
2116                                                sizeof(unsigned char) *
2117                                                VORTEX_RESOURCE_LAST);
2118                                         return -EBUSY;
2119                                 }
2120                                 if (stream->type != VORTEX_PCM_A3D) {
2121                                         if ((mix[i] = vortex_adb_checkinout(vortex,
2122                                                                    stream->resources,
2123                                                                    en,
2124                                                                    VORTEX_RESOURCE_MIXIN)) < 0) {
2125                                                 memset(stream->resources,
2126                                                        0,
2127                                                        sizeof(unsigned char) * VORTEX_RESOURCE_LAST);
2128                                                 return -EBUSY;
2129                                         }
2130                                 }
2131                         }
2132                 }
2133 #ifndef CHIP_AU8820
2134                 if (stream->type == VORTEX_PCM_A3D) {
2135                         if ((a3d =
2136                              vortex_adb_checkinout(vortex,
2137                                                    stream->resources, en,
2138                                                    VORTEX_RESOURCE_A3D)) < 0) {
2139                                 memset(stream->resources, 0,
2140                                        sizeof(unsigned char) *
2141                                        VORTEX_RESOURCE_LAST);
2142                                 printk("vortex: out of A3D sources. Sorry\n");
2143                                 return -EBUSY;
2144                         }
2145                         /* (De)Initialize A3D hardware source. */
2146                         vortex_Vort3D_InitializeSource(&(vortex->a3d[a3d]), en);
2147                 }
2148                 /* Make SPDIF out exclusive to "spdif" device when in use. */
2149                 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
2150                         vortex_route(vortex, 0, 0x14,
2151                                      ADB_MIXOUT(vortex->mixspdif[0]),
2152                                      ADB_SPDIFOUT(0));
2153                         vortex_route(vortex, 0, 0x14,
2154                                      ADB_MIXOUT(vortex->mixspdif[1]),
2155                                      ADB_SPDIFOUT(1));
2156                 }
2157 #endif
2158                 /* Make playback routes. */
2159                 for (i = 0; i < nr_ch; i++) {
2160                         if (stream->type == VORTEX_PCM_ADB) {
2161                                 vortex_connection_adbdma_src(vortex, en,
2162                                                              src[nr_ch - 1],
2163                                                              dma,
2164                                                              src[i]);
2165                                 vortex_connection_src_mixin(vortex, en,
2166                                                             0x11, src[i],
2167                                                             mix[i]);
2168                                 vortex_connection_mixin_mix(vortex, en,
2169                                                             mix[i],
2170                                                             MIX_PLAYB(i), 0);
2171 #ifndef CHIP_AU8820
2172                                 vortex_connection_mixin_mix(vortex, en,
2173                                                             mix[i],
2174                                                             MIX_SPDIF(i % 2), 0);
2175                                 vortex_mix_setinputvolumebyte(vortex,
2176                                                               MIX_SPDIF(i % 2),
2177                                                               mix[i],
2178                                                               MIX_DEFIGAIN);
2179 #endif
2180                         }
2181 #ifndef CHIP_AU8820
2182                         if (stream->type == VORTEX_PCM_A3D) {
2183                                 vortex_connection_adbdma_src(vortex, en,
2184                                                              src[nr_ch - 1],
2185                                                                  dma,
2186                                                              src[i]);
2187                                 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
2188                                 /* XTalk test. */
2189                                 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
2190                                 //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9));
2191                         }
2192                         if (stream->type == VORTEX_PCM_SPDIF)
2193                                 vortex_route(vortex, en, 0x14,
2194                                              ADB_DMA(stream->dma),
2195                                              ADB_SPDIFOUT(i));
2196 #endif
2197                 }
2198                 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
2199                         ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
2200                         for (i = nr_ch; i < ch_top; i++) {
2201                                 vortex_connection_mixin_mix(vortex, en,
2202                                                             mix[i % nr_ch],
2203                                                             MIX_PLAYB(i), 0);
2204 #ifndef CHIP_AU8820
2205                                 vortex_connection_mixin_mix(vortex, en,
2206                                                             mix[i % nr_ch],
2207                                                             MIX_SPDIF(i % 2),
2208                                                                 0);
2209                                 vortex_mix_setinputvolumebyte(vortex,
2210                                                               MIX_SPDIF(i % 2),
2211                                                               mix[i % nr_ch],
2212                                                               MIX_DEFIGAIN);
2213 #endif
2214                         }
2215                 }
2216 #ifndef CHIP_AU8820
2217                 else {
2218                         if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
2219                                 vortex_route(vortex, en, 0x14,
2220                                              ADB_DMA(stream->dma),
2221                                              ADB_SPDIFOUT(1));
2222                 }
2223                 /* Reconnect SPDIF out when "spdif" device is down. */
2224                 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
2225                         vortex_route(vortex, 1, 0x14,
2226                                      ADB_MIXOUT(vortex->mixspdif[0]),
2227                                      ADB_SPDIFOUT(0));
2228                         vortex_route(vortex, 1, 0x14,
2229                                      ADB_MIXOUT(vortex->mixspdif[1]),
2230                                      ADB_SPDIFOUT(1));
2231                 }
2232 #endif
2233         /* CAPTURE ROUTES. */
2234         } else {
2235                 int src[2], mix[2];
2236
2237                 /* Get SRC and MIXER hardware resources. */
2238                 for (i = 0; i < nr_ch; i++) {
2239                         if ((mix[i] =
2240                              vortex_adb_checkinout(vortex,
2241                                                    stream->resources, en,
2242                                                    VORTEX_RESOURCE_MIXOUT))
2243                             < 0) {
2244                                 memset(stream->resources, 0,
2245                                        sizeof(unsigned char) *
2246                                        VORTEX_RESOURCE_LAST);
2247                                 return -EBUSY;
2248                         }
2249                         if ((src[i] =
2250                              vortex_adb_checkinout(vortex,
2251                                                    stream->resources, en,
2252                                                    VORTEX_RESOURCE_SRC)) < 0) {
2253                                 memset(stream->resources, 0,
2254                                        sizeof(unsigned char) *
2255                                        VORTEX_RESOURCE_LAST);
2256                                 return -EBUSY;
2257                         }
2258                 }
2259
2260                 /* Make capture routes. */
2261                 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
2262                 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
2263                 if (nr_ch == 1) {
2264                         vortex_connection_mixin_mix(vortex, en,
2265                                                     MIX_CAPT(1), mix[0], 0);
2266                         vortex_connection_src_adbdma(vortex, en,
2267                                                      src[0],
2268                                                      src[0], dma);
2269                 } else {
2270                         vortex_connection_mixin_mix(vortex, en,
2271                                                     MIX_CAPT(1), mix[1], 0);
2272                         vortex_connection_mix_src(vortex, en, 0x11, mix[1],
2273                                                   src[1]);
2274                         vortex_connection_src_src_adbdma(vortex, en,
2275                                                          src[1], src[0],
2276                                                          src[1], dma);
2277                 }
2278         }
2279         vortex->dma_adb[dma].nr_ch = nr_ch;
2280         spin_unlock(&vortex->lock);
2281
2282 #if 0
2283         /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */
2284         if (nr_ch < 4) {
2285                 /* Copy stereo to rear channel (surround) */
2286                 snd_ac97_write_cache(vortex->codec,
2287                                      AC97_SIGMATEL_DAC2INVERT,
2288                                      snd_ac97_read(vortex->codec,
2289                                                    AC97_SIGMATEL_DAC2INVERT)
2290                                      | 4);
2291         } else {
2292                 /* Allow separate front and rear channels. */
2293                 snd_ac97_write_cache(vortex->codec,
2294                                      AC97_SIGMATEL_DAC2INVERT,
2295                                      snd_ac97_read(vortex->codec,
2296                                                    AC97_SIGMATEL_DAC2INVERT)
2297                                      & ~((u32)
2298                                          4));
2299         }
2300 #endif
2301         return dma;
2302 }
2303
2304 /*
2305  Set the SampleRate of the SRC's attached to the given DMA engine.
2306  */
2307 static void
2308 vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
2309 {
2310         stream_t *stream = &(vortex->dma_adb[adbdma]);
2311         int i, cvrt;
2312
2313         /* dir=1:play ; dir=0:rec */
2314         if (dir)
2315                 cvrt = SRC_RATIO(rate, 48000);
2316         else
2317                 cvrt = SRC_RATIO(48000, rate);
2318
2319         /* Setup SRC's */
2320         for (i = 0; i < NR_SRC; i++) {
2321                 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
2322                         vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
2323         }
2324 }
2325
2326 // Timer and ISR functions.
2327
2328 static void vortex_settimer(vortex_t * vortex, int period)
2329 {
2330         //set the timer period to <period> 48000ths of a second.
2331         hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
2332 }
2333
2334 #if 0
2335 static void vortex_enable_timer_int(vortex_t * card)
2336 {
2337         hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2338                 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
2339 }
2340
2341 static void vortex_disable_timer_int(vortex_t * card)
2342 {
2343         hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2344                 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
2345 }
2346
2347 #endif
2348 static void vortex_enable_int(vortex_t * card)
2349 {
2350         // CAsp4ISR__EnableVortexInt_void_
2351         hwwrite(card->mmio, VORTEX_CTRL,
2352                 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
2353         hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2354                 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
2355 }
2356
2357 static void vortex_disable_int(vortex_t * card)
2358 {
2359         hwwrite(card->mmio, VORTEX_CTRL,
2360                 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
2361 }
2362
2363 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2364 {
2365         vortex_t *vortex = snd_magic_cast(vortex_t, dev_id, return IRQ_NONE);
2366         int i, handled;
2367         u32 source;
2368
2369         //check if the interrupt is ours.
2370         if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
2371                 return IRQ_NONE;
2372
2373         // This is the Interrrupt Enable flag we set before (consistency check).
2374         if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
2375                 return IRQ_NONE;
2376
2377         source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2378         // Reset IRQ flags.
2379         hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
2380         hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2381         // Is at least one IRQ flag set?
2382         if (source == 0) {
2383                 printk(KERN_ERR "vortex: missing irq source\n");
2384                 return IRQ_NONE;
2385         }
2386
2387         handled = 0;
2388         // Attend every interrupt source.
2389         if (unlikely(source & IRQ_ERR_MASK)) {
2390                 if (source & IRQ_FATAL) {
2391                         printk(KERN_ERR "vortex: IRQ fatal error\n");
2392                 }
2393                 if (source & IRQ_PARITY) {
2394                         printk(KERN_ERR "vortex: IRQ parity error\n");
2395                 }
2396                 if (source & IRQ_REG) {
2397                         printk(KERN_ERR "vortex: IRQ reg error\n");
2398                 }
2399                 if (source & IRQ_FIFO) {
2400                         printk(KERN_ERR "vortex: IRQ fifo error\n");
2401                 }
2402                 if (source & IRQ_DMA) {
2403                         printk(KERN_ERR "vortex: IRQ dma error\n");
2404                 }
2405                 handled = 1;
2406         }
2407         if (source & IRQ_PCMOUT) {
2408                 /* ALSA period acknowledge. */
2409                 for (i = 0; i < NR_ADB; i++) {
2410                         if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2411                                 if (vortex_adbdma_bufshift(vortex, i)) ;
2412                                 snd_pcm_period_elapsed(vortex->dma_adb[i].
2413                                                        substream);
2414                         }
2415                 }
2416 #ifndef CHIP_AU8810
2417                 for (i = 0; i < NR_WT; i++) {
2418                         if (vortex->dma_wt[i].fifo_status == FIFO_START) {
2419                                 if (vortex_wtdma_bufshift(vortex, i)) ;
2420                                 snd_pcm_period_elapsed(vortex->dma_wt[i].
2421                                                        substream);
2422                         }
2423                 }
2424 #endif
2425                 handled = 1;
2426         }
2427         //Acknowledge the Timer interrupt
2428         if (source & IRQ_TIMER) {
2429                 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2430                 handled = 1;
2431         }
2432         if (source & IRQ_MIDI) {
2433                 snd_mpu401_uart_interrupt(vortex->irq,
2434                                           vortex->rmidi->private_data, regs);
2435                 handled = 1;
2436         }
2437
2438         if (!handled) {
2439                 printk(KERN_ERR "vortex: unknown irq source %x\n", source);
2440         }
2441         return IRQ_RETVAL(handled);
2442 }
2443
2444 /* Codec */
2445
2446 #define POLL_COUNT 1000
2447 static void vortex_codec_init(vortex_t * vortex)
2448 {
2449         int i;
2450
2451         for (i = 0; i < 32; i++) {
2452                 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), 0);
2453                 udelay(2000);
2454         }
2455         if (0) {
2456                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
2457                 udelay(1000);
2458                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2459                 udelay(1000);
2460         } else {
2461                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2462                 udelay(2000);
2463                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2464                 udelay(2000);
2465                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
2466                 udelay(2000);
2467                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2468                 udelay(2000);
2469                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2470                 udelay(2000);
2471                 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2472         }
2473         for (i = 0; i < 32; i++) {
2474                 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), 0);
2475                 udelay(5000);
2476         }
2477         hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
2478         udelay(1000);
2479         /* Enable codec channels 0 and 1. */
2480         hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2481                 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
2482 }
2483
2484 static void
2485 vortex_codec_write(ac97_t * codec, unsigned short addr, unsigned short data)
2486 {
2487
2488         vortex_t *card = (vortex_t *) codec->private_data;
2489         unsigned long flags;
2490         unsigned int lifeboat = 0;
2491         spin_lock_irqsave(&card->lock, flags);
2492
2493         /* wait for transactions to clear */
2494         while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2495                 udelay(100);
2496                 if (lifeboat++ > POLL_COUNT) {
2497                         printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
2498                         spin_unlock_irqrestore(&card->lock, flags);
2499                         return;
2500                 }
2501         }
2502         /* write register */
2503         hwwrite(card->mmio, VORTEX_CODEC_IO,
2504                 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2505                 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
2506                 VORTEX_CODEC_WRITE);
2507
2508         /* Flush Caches. */
2509         hwread(card->mmio, VORTEX_CODEC_IO);
2510
2511         spin_unlock_irqrestore(&card->lock, flags);
2512 }
2513
2514 static unsigned short vortex_codec_read(ac97_t * codec, unsigned short addr)
2515 {
2516
2517         vortex_t *card = (vortex_t *) codec->private_data;
2518         u32 read_addr, data;
2519         unsigned long flags;
2520         unsigned lifeboat = 0;
2521
2522         spin_lock_irqsave(&card->lock, flags);
2523
2524         /* wait for transactions to clear */
2525         while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2526                 udelay(100);
2527                 if (lifeboat++ > POLL_COUNT) {
2528                         printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
2529                         spin_unlock_irqrestore(&card->lock, flags);
2530                         return 0xffff;
2531                 }
2532         }
2533         /* set up read address */
2534         read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK);
2535         hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
2536
2537         /* wait for address */
2538         {
2539                 udelay(100);
2540                 data = hwread(card->mmio, VORTEX_CODEC_IO);
2541                 if (lifeboat++ > POLL_COUNT) {
2542                         printk(KERN_ERR "vortex: ac97 address never arrived\n");
2543                         spin_unlock_irqrestore(&card->lock, flags);
2544                         return 0xffff;
2545                 }
2546         }
2547         while ((data & VORTEX_CODEC_ADDMASK) !=
2548                (addr << VORTEX_CODEC_ADDSHIFT)) ;
2549
2550         /* Unlock. */
2551         spin_unlock_irqrestore(&card->lock, flags);
2552
2553         /* return data. */
2554         return (u16) (data & VORTEX_CODEC_DATMASK);
2555 }
2556
2557 /* SPDIF support  */
2558
2559 static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
2560 {
2561         int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
2562
2563         /* CAsp4Spdif::InitializeSpdifHardware(void) */
2564         hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
2565                 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
2566         //for (i=0x291D4; i<0x29200; i+=4)
2567         for (i = 0; i < 11; i++)
2568                 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
2569         //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000);
2570         hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2571                 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
2572
2573         /* CAsp4Spdif::ProgramSRCInHardware(enum  SPDIF_SR,enum  SPDIFMODE) */
2574         if (this_04 && this_08) {
2575                 int edi;
2576
2577                 i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
2578                 if (i > 0x800) {
2579                         if (i < 0x1ffff)
2580                                 edi = (i >> 1);
2581                         else
2582                                 edi = 0x1ffff;
2583                 } else {
2584                         i = edi = 0x800;
2585                 }
2586                 /* this_04 and this_08 are the CASp4Src's (samplerate converters) */
2587                 vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
2588                                         this_0c, 1, 0, edi, 1);
2589                 vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
2590                                         this_0c, 1, 0, edi, 1);
2591         }
2592
2593         i = spdif_sr;
2594         spdif_sr |= 0x8c;
2595         switch (i) {
2596         case 32000:
2597                 this_38 &= 0xFFFFFFFE;
2598                 this_38 &= 0xFFFFFFFD;
2599                 this_38 &= 0xF3FFFFFF;
2600                 this_38 |= 0x03000000;  /* set 32khz samplerate */
2601                 this_38 &= 0xFFFFFF3F;
2602                 spdif_sr &= 0xFFFFFFFD;
2603                 spdif_sr |= 1;
2604                 break;
2605         case 44100:
2606                 this_38 &= 0xFFFFFFFE;
2607                 this_38 &= 0xFFFFFFFD;
2608                 this_38 &= 0xF0FFFFFF;
2609                 this_38 |= 0x03000000;
2610                 this_38 &= 0xFFFFFF3F;
2611                 spdif_sr &= 0xFFFFFFFC;
2612                 break;
2613         case 48000:
2614                 if (spdif_mode == 1) {
2615                         this_38 &= 0xFFFFFFFE;
2616                         this_38 &= 0xFFFFFFFD;
2617                         this_38 &= 0xF2FFFFFF;
2618                         this_38 |= 0x02000000;  /* set 48khz samplerate */
2619                         this_38 &= 0xFFFFFF3F;
2620                 } else {
2621                         /* J. Gordon Wolfe: I think this stuff is for AC3 */
2622                         this_38 |= 0x00000003;
2623                         this_38 &= 0xFFFFFFBF;
2624                         this_38 |= 0x80;
2625                 }
2626                 spdif_sr |= 2;
2627                 spdif_sr &= 0xFFFFFFFE;
2628                 break;
2629
2630         }
2631         /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit
2632            registers. seems to be for the standard IEC/SPDIF initialization
2633            stuff */
2634         hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
2635         hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
2636         hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
2637 }
2638
2639 /* Initialization */
2640
2641 static int vortex_core_init(vortex_t * vortex)
2642 {
2643
2644         printk(KERN_INFO "Vortex: init.... ");
2645         /* Hardware Init. */
2646         hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
2647         udelay(5000);
2648         hwwrite(vortex->mmio, VORTEX_CTRL,
2649                 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
2650         udelay(5000);
2651         /* Reset IRQ flags */
2652         hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
2653         hwread(vortex->mmio, VORTEX_IRQ_STAT);
2654
2655         vortex_codec_init(vortex);
2656
2657 #ifdef CHIP_AU8830
2658         hwwrite(vortex->mmio, VORTEX_CTRL,
2659                 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
2660 #endif
2661
2662         /* Init audio engine. */
2663         vortex_adbdma_init(vortex);
2664         hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58
2665         vortex_adb_init(vortex);
2666         /* Init processing blocks. */
2667         vortex_fifo_init(vortex);
2668         vortex_mixer_init(vortex);
2669         vortex_srcblock_init(vortex);
2670 #ifndef CHIP_AU8820
2671         vortex_eq_init(vortex);
2672         vortex_spdif_init(vortex, 48000, 1);
2673         vortex_Vort3D(vortex, 1);
2674 #endif
2675 #ifndef CHIP_AU8810
2676         vortex_wt_init(vortex);
2677 #endif
2678         // Moved to au88x0.c
2679         //vortex_connect_default(vortex, 1);
2680
2681         vortex_settimer(vortex, 0x90);
2682         // Enable Interrupts.
2683         // vortex_enable_int() must be first !!
2684         //  hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2685         // vortex_enable_int(vortex);
2686         //vortex_enable_timer_int(vortex);
2687         //vortex_disable_timer_int(vortex);
2688
2689         printk(KERN_INFO "done.\n");
2690         spin_lock_init(&vortex->lock);
2691
2692         return 0;
2693 }
2694
2695 static int vortex_core_shutdown(vortex_t * vortex)
2696 {
2697
2698         printk(KERN_INFO "Vortex: shutdown...");
2699 #ifndef CHIP_AU8820
2700         vortex_eq_free(vortex);
2701         vortex_Vort3D(vortex, 0);
2702 #endif
2703         //vortex_disable_timer_int(vortex);
2704         vortex_disable_int(vortex);
2705         vortex_connect_default(vortex, 0);
2706         /* Reset all DMA fifos. */
2707         vortex_fifo_init(vortex);
2708         /* Erase all audio routes. */
2709         vortex_adb_init(vortex);
2710
2711         /* Disable MPU401 */
2712         //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI);
2713         //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN);
2714
2715         hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2716         hwwrite(vortex->mmio, VORTEX_CTRL, 0);
2717         udelay(5000);
2718         hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
2719
2720         printk(KERN_INFO "done.\n");
2721         return 0;
2722 }
2723
2724 /* Alsa support. */
2725
2726 static int vortex_alsafmt_aspfmt(int alsafmt)
2727 {
2728         int fmt;
2729
2730         switch (alsafmt) {
2731         case SNDRV_PCM_FORMAT_U8:
2732                 fmt = 0x1;
2733                 break;
2734         case SNDRV_PCM_FORMAT_MU_LAW:
2735                 fmt = 0x2;
2736                 break;
2737         case SNDRV_PCM_FORMAT_A_LAW:
2738                 fmt = 0x3;
2739                 break;
2740         case SNDRV_PCM_FORMAT_SPECIAL:
2741                 fmt = 0x4;      /* guess. */
2742                 break;
2743         case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
2744                 fmt = 0x5;      /* guess. */
2745                 break;
2746         case SNDRV_PCM_FORMAT_S16_LE:
2747                 fmt = 0x8;
2748                 break;
2749         case SNDRV_PCM_FORMAT_S16_BE:
2750                 fmt = 0x9;      /* check this... */
2751                 break;
2752         default:
2753                 fmt = 0x8;
2754                 printk(KERN_ERR "vortex: format unsupported %d\n", alsafmt);
2755                 break;
2756         }
2757         return fmt;
2758 }
2759
2760 /* Some not yet useful translations. */
2761 #if 0
2762 typedef enum {
2763         ASPFMTLINEAR16 = 0,     /* 0x8 */
2764         ASPFMTLINEAR8,          /* 0x1 */
2765         ASPFMTULAW,             /* 0x2 */
2766         ASPFMTALAW,             /* 0x3 */
2767         ASPFMTSPORT,            /* ? */
2768         ASPFMTSPDIF,            /* ? */
2769 } ASPENCODING;
2770
2771 static int
2772 vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
2773 {
2774         int a, this_194;
2775
2776         if ((bits != 8) || (bits != 16))
2777                 return -1;
2778
2779         switch (encod) {
2780         case 0:
2781                 if (bits == 0x10)
2782                         a = 8;  // 16 bit
2783                 break;
2784         case 1:
2785                 if (bits == 8)
2786                         a = 1;  // 8 bit
2787                 break;
2788         case 2:
2789                 a = 2;          // U_LAW
2790                 break;
2791         case 3:
2792                 a = 3;          // A_LAW
2793                 break;
2794         }
2795         switch (nch) {
2796         case 1:
2797                 this_194 = 0;
2798                 break;
2799         case 2:
2800                 this_194 = 1;
2801                 break;
2802         case 4:
2803                 this_194 = 1;
2804                 break;
2805         case 6:
2806                 this_194 = 1;
2807                 break;
2808         }
2809         return (a);
2810 }
2811
2812 static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
2813 {
2814         short int d, this_148;
2815
2816         d = ((bits >> 3) * nch);
2817         this_148 = 0xbb80 / d;
2818 }
2819 #endif