sound/pci/cmipci.c

   1 /*
   2  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   3  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program; if not, write to the Free Software
  17  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 /* Does not work. Warning may block system in capture mode */
  21 /* #define USE_VAR48KRATE */
  22
  23 #include <sound/driver.h>
  24 #include <asm/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/init.h>
  28 #include <linux/pci.h>
  29 #include <linux/slab.h>
  30 #include <linux/gameport.h>
  31 #include <linux/moduleparam.h>
  32 #include <sound/core.h>
  33 #include <sound/info.h>
  34 #include <sound/control.h>
  35 #include <sound/pcm.h>
  36 #include <sound/rawmidi.h>
  37 #include <sound/mpu401.h>
  38 #include <sound/opl3.h>
  39 #include <sound/sb.h>
  40 #include <sound/asoundef.h>
  41 #include <sound/initval.h>
  42
  43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  45 MODULE_LICENSE("GPL");
  46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
  47                 "{C-Media,CMI8738B},"
  48                 "{C-Media,CMI8338A},"
  49                 "{C-Media,CMI8338B}}");
  50
  51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  52 #define SUPPORT_JOYSTICK 1
  53 #endif
  54
  55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  58 static long mpu_port[SNDRV_CARDS];
  59 static long fm_port[SNDRV_CARDS];
  60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  61 #ifdef SUPPORT_JOYSTICK
  62 static int joystick_port[SNDRV_CARDS];
  63 #endif
  64 static int boot_devs;
  65
  66 module_param_array(index, int, boot_devs, 0444);
  67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  68 module_param_array(id, charp, boot_devs, 0444);
  69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  70 module_param_array(enable, bool, boot_devs, 0444);
  71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  72 module_param_array(mpu_port, long, boot_devs, 0444);
  73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  74 module_param_array(fm_port, long, boot_devs, 0444);
  75 MODULE_PARM_DESC(fm_port, "FM port.");
  76 module_param_array(soft_ac3, bool, boot_devs, 0444);
  77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
  78 #ifdef SUPPORT_JOYSTICK
  79 module_param_array(joystick_port, int, boot_devs, 0444);
  80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  81 #endif
  82
  83 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
  84 #define PCI_DEVICE_ID_CMEDIA_CM8738     0x0111
  85 #endif
  86 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
  87 #define PCI_DEVICE_ID_CMEDIA_CM8738B    0x0112
  88 #endif
  89
  90 /*
  91  * CM8x38 registers definition
  92  */
  93
  94 #define CM_REG_FUNCTRL0         0x00
  95 #define CM_RST_CH1              0x00080000
  96 #define CM_RST_CH0              0x00040000
  97 #define CM_CHEN1                0x00020000      /* ch1: enable */
  98 #define CM_CHEN0                0x00010000      /* ch0: enable */
  99 #define CM_PAUSE1               0x00000008      /* ch1: pause */
 100 #define CM_PAUSE0               0x00000004      /* ch0: pause */
 101 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
 102 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
 103
 104 #define CM_REG_FUNCTRL1         0x04
 105 #define CM_ASFC_MASK            0x0000E000      /* ADC sampling frequency */
 106 #define CM_ASFC_SHIFT           13
 107 #define CM_DSFC_MASK            0x00001C00      /* DAC sampling frequency */
 108 #define CM_DSFC_SHIFT           10
 109 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
 110 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
 111 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/OUT -> IN loopback */
 112 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
 113 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
 114 #define CM_BREQ                 0x00000010      /* bus master enabled */
 115 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
 116 #define CM_UART_EN              0x00000004      /* UART */
 117 #define CM_JYSTK_EN             0x00000002      /* joy stick */
 118
 119 #define CM_REG_CHFORMAT         0x08
 120
 121 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 122 #define CM_CHB3D                0x20000000      /* 4 channels */
 123
 124 #define CM_CHIP_MASK1           0x1f000000
 125 #define CM_CHIP_037             0x01000000
 126
 127 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 128 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 129 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 130 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 131
 132 #define CM_ADCBITLEN_MASK       0x0000C000
 133 #define CM_ADCBITLEN_16         0x00000000
 134 #define CM_ADCBITLEN_15         0x00004000
 135 #define CM_ADCBITLEN_14         0x00008000
 136 #define CM_ADCBITLEN_13         0x0000C000
 137
 138 #define CM_ADCDACLEN_MASK       0x00003000
 139 #define CM_ADCDACLEN_060        0x00000000
 140 #define CM_ADCDACLEN_066        0x00001000
 141 #define CM_ADCDACLEN_130        0x00002000
 142 #define CM_ADCDACLEN_280        0x00003000
 143
 144 #define CM_CH1_SRATE_176K       0x00000800
 145 #define CM_CH1_SRATE_88K        0x00000400
 146 #define CM_CH0_SRATE_176K       0x00000200
 147 #define CM_CH0_SRATE_88K        0x00000100
 148
 149 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 150
 151 #define CM_CH1FMT_MASK          0x0000000C
 152 #define CM_CH1FMT_SHIFT         2
 153 #define CM_CH0FMT_MASK          0x00000003
 154 #define CM_CH0FMT_SHIFT         0
 155
 156 #define CM_REG_INT_HLDCLR       0x0C
 157 #define CM_CHIP_MASK2           0xff000000
 158 #define CM_CHIP_039             0x04000000
 159 #define CM_CHIP_039_6CH         0x01000000
 160 #define CM_TDMA_INT_EN          0x00040000
 161 #define CM_CH1_INT_EN           0x00020000
 162 #define CM_CH0_INT_EN           0x00010000
 163 #define CM_INT_HOLD             0x00000002
 164 #define CM_INT_CLEAR            0x00000001
 165
 166 #define CM_REG_INT_STATUS       0x10
 167 #define CM_INTR                 0x80000000
 168 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 169 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 170 #define CM_UARTINT              0x00010000
 171 #define CM_LTDMAINT             0x00008000
 172 #define CM_HTDMAINT             0x00004000
 173 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 174 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 175 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 176 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 177 #define CM_CH1BUSY              0x00000008
 178 #define CM_CH0BUSY              0x00000004
 179 #define CM_CHINT1               0x00000002
 180 #define CM_CHINT0               0x00000001
 181
 182 #define CM_REG_LEGACY_CTRL      0x14
 183 #define CM_NXCHG                0x80000000      /* h/w multi channels? */
 184 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 185 #define CM_VMPU_330             0x00000000
 186 #define CM_VMPU_320             0x20000000
 187 #define CM_VMPU_310             0x40000000
 188 #define CM_VMPU_300             0x60000000
 189 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 190 #define CM_VSBSEL_220           0x00000000
 191 #define CM_VSBSEL_240           0x04000000
 192 #define CM_VSBSEL_260           0x08000000
 193 #define CM_VSBSEL_280           0x0C000000
 194 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 195 #define CM_FMSEL_388            0x00000000
 196 #define CM_FMSEL_3C8            0x01000000
 197 #define CM_FMSEL_3E0            0x02000000
 198 #define CM_FMSEL_3E8            0x03000000
 199 #define CM_ENSPDOUT             0x00800000      /* enable XPDIF/OUT to I/O interface */
 200 #define CM_SPDCOPYRHT           0x00400000      /* set copyright spdif in/out */
 201 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 202 #define CM_SETRETRY             0x00010000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 203 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 204 #define CM_LINE_AS_BASS         0x00006000      /* use line-in as bass */
 205
 206 #define CM_REG_MISC_CTRL        0x18
 207 #define CM_PWD                  0x80000000
 208 #define CM_RESET                0x40000000
 209 #define CM_SFIL_MASK            0x30000000
 210 #define CM_TXVX                 0x08000000
 211 #define CM_N4SPK3D              0x04000000      /* 4ch output */
 212 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 213 #define CM_SPDIF48K             0x01000000      /* write */
 214 #define CM_SPATUS48K            0x01000000      /* read */
 215 #define CM_ENDBDAC              0x00800000      /* enable dual dac */
 216 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 217 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 218 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-IN -> int. OUT */
 219 #define CM_FM_EN                0x00080000      /* enalbe FM */
 220 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 221 #define CM_VIDWPDSB             0x00010000
 222 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 223 #define CM_MASK_EN              0x00004000
 224 #define CM_VIDWPPRT             0x00002000
 225 #define CM_SFILENB              0x00001000
 226 #define CM_MMODE_MASK           0x00000E00
 227 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 228 #define CM_ENCENTER             0x00000080
 229 #define CM_FLINKON              0x00000040
 230 #define CM_FLINKOFF             0x00000020
 231 #define CM_MIDSMP               0x00000010
 232 #define CM_UPDDMA_MASK          0x0000000C
 233 #define CM_TWAIT_MASK           0x00000003
 234
 235         /* byte */
 236 #define CM_REG_MIXER0           0x20
 237
 238 #define CM_REG_SB16_DATA        0x22
 239 #define CM_REG_SB16_ADDR        0x23
 240
 241 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 242 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 243 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 244 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 245
 246 #define CM_REG_MIXER1           0x24
 247 #define CM_FMMUTE               0x80    /* mute FM */
 248 #define CM_FMMUTE_SHIFT         7
 249 #define CM_WSMUTE               0x40    /* mute PCM */
 250 #define CM_WSMUTE_SHIFT         6
 251 #define CM_SPK4                 0x20    /* lin-in -> rear line out */
 252 #define CM_SPK4_SHIFT           5
 253 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 254 #define CM_REAR2FRONT_SHIFT     4
 255 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 256 #define CM_WAVEINL_SHIFT        3
 257 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 258 #define CM_WAVEINR_SHIFT        2
 259 #define CM_X3DEN                0x02    /* 3D surround enable */
 260 #define CM_X3DEN_SHIFT          1
 261 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 262 #define CM_CDPLAY_SHIFT         0
 263
 264 #define CM_REG_MIXER2           0x25
 265 #define CM_RAUXREN              0x80    /* AUX right capture */
 266 #define CM_RAUXREN_SHIFT        7
 267 #define CM_RAUXLEN              0x40    /* AUX left capture */
 268 #define CM_RAUXLEN_SHIFT        6
 269 #define CM_VAUXRM               0x20    /* AUX right mute */
 270 #define CM_VAUXRM_SHIFT         5
 271 #define CM_VAUXLM               0x10    /* AUX left mute */
 272 #define CM_VAUXLM_SHIFT         4
 273 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 274 #define CM_VADMIC_SHIFT         1
 275 #define CM_MICGAINZ             0x01    /* mic boost */
 276 #define CM_MICGAINZ_SHIFT       0
 277
 278 #define CM_REG_AUX_VOL          0x26
 279 #define CM_VAUXL_MASK           0xf0
 280 #define CM_VAUXR_MASK           0x0f
 281
 282 #define CM_REG_MISC             0x27
 283 #define CM_XGPO1                0x20
 284 // #define CM_XGPBIO            0x04
 285 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 286 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 287 #define CM_SPDVALID             0x02    /* spdif input valid check */
 288 #define CM_DMAUTO               0x01
 289
 290 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 291 /*
 292  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 293  * or identical with AC97 codec?
 294  */
 295 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 296
 297 /*
 298  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 299  */
 300 #define CM_REG_MPU_PCI          0x40
 301
 302 /*
 303  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 304  */
 305 #define CM_REG_FM_PCI           0x50
 306
 307 /*
 308  * for CMI-8338 .. this is not valid for CMI-8738.
 309  */
 310 #define CM_REG_EXTENT_IND       0xf0
 311 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 312 #define CM_VPHONE_SHIFT         5
 313 #define CM_VPHOM                0x10    /* Phone mute control */
 314 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 315 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 316 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 317
 318 /*
 319  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 320  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 321  * unit (readonly?).
 322  */
 323 #define CM_REG_PLL              0xf8
 324
 325 /*
 326  * extended registers
 327  */
 328 #define CM_REG_CH0_FRAME1       0x80    /* base address */
 329 #define CM_REG_CH0_FRAME2       0x84
 330 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 331 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 332
 333 /*
 334  * size of i/o region
 335  */
 336 #define CM_EXTENT_CODEC   0x100
 337 #define CM_EXTENT_MIDI    0x2
 338 #define CM_EXTENT_SYNTH   0x4
 339
 340
 341 /*
 342  * pci ids
 343  */
 344 #ifndef PCI_VENDOR_ID_CMEDIA
 345 #define PCI_VENDOR_ID_CMEDIA         0x13F6
 346 #endif
 347 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
 348 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
 349 #endif
 350 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
 351 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
 352 #endif
 353 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
 354 #define PCI_DEVICE_ID_CMEDIA_CM8738  0x0111
 355 #endif
 356 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
 357 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
 358 #endif
 359
 360 /*
 361  * channels for playback / capture
 362  */
 363 #define CM_CH_PLAY      0
 364 #define CM_CH_CAPT      1
 365
 366 /*
 367  * flags to check device open/close
 368  */
 369 #define CM_OPEN_NONE    0
 370 #define CM_OPEN_CH_MASK 0x01
 371 #define CM_OPEN_DAC     0x10
 372 #define CM_OPEN_ADC     0x20
 373 #define CM_OPEN_SPDIF   0x40
 374 #define CM_OPEN_MCHAN   0x80
 375 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 376 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 377 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 378 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 379 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 380 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 381
 382
 383 #if CM_CH_PLAY == 1
 384 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 385 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 386 #define CM_CAPTURE_SPDF         CM_SPDF_0
 387 #else
 388 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 389 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 390 #define CM_CAPTURE_SPDF         CM_SPDF_1
 391 #endif
 392
 393
 394 /*
 395  * driver data
 396  */
 397
 398 typedef struct snd_stru_cmipci cmipci_t;
 399 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
 400
 401 struct snd_stru_cmipci_pcm {
 402         snd_pcm_substream_t *substream;
 403         int running;            /* dac/adc running? */
 404         unsigned int dma_size;  /* in frames */
 405         unsigned int period_size;       /* in frames */
 406         unsigned int offset;    /* physical address of the buffer */
 407         unsigned int fmt;       /* format bits */
 408         int ch;                 /* channel (0/1) */
 409         unsigned int is_dac;            /* is dac? */
 410         int bytes_per_frame;
 411         int shift;
 412 };
 413
 414 /* mixer elements toggled/resumed during ac3 playback */
 415 struct cmipci_mixer_auto_switches {
 416         const char *name;       /* switch to toggle */
 417         int toggle_on;          /* value to change when ac3 mode */
 418 };
 419 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 420         {"PCM Playback Switch", 0},
 421         {"IEC958 Output Switch", 1},
 422         {"IEC958 Mix Analog", 0},
 423         // {"IEC958 Out To DAC", 1}, // no longer used
 424         {"IEC958 Loop", 0},
 425 };
 426 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 427
 428 struct snd_stru_cmipci {
 429         snd_card_t *card;
 430
 431         struct pci_dev *pci;
 432         unsigned int device;    /* device ID */
 433         int irq;
 434
 435         unsigned long iobase;
 436         unsigned int ctrl;      /* FUNCTRL0 current value */
 437
 438         snd_pcm_t *pcm;         /* DAC/ADC PCM */
 439         snd_pcm_t *pcm2;        /* 2nd DAC */
 440         snd_pcm_t *pcm_spdif;   /* SPDIF */
 441
 442         int chip_version;
 443         int max_channels;
 444         unsigned int has_dual_dac: 1;
 445         unsigned int can_ac3_sw: 1;
 446         unsigned int can_ac3_hw: 1;
 447         unsigned int can_multi_ch: 1;
 448         unsigned int do_soft_ac3: 1;
 449
 450         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 451         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 452         int spdif_counter;      /* for software AC3 */
 453
 454         unsigned int dig_status;
 455         unsigned int dig_pcm_status;
 456
 457         snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
 458
 459         int opened[2];  /* open mode */
 460         struct semaphore open_mutex;
 461
 462         int mixer_insensitive: 1;
 463         snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
 464         int mixer_res_status[CM_SAVED_MIXERS];
 465
 466         opl3_t *opl3;
 467         snd_hwdep_t *opl3hwdep;
 468
 469         cmipci_pcm_t channel[2];        /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 470
 471         /* external MIDI */
 472         snd_rawmidi_t *rmidi;
 473
 474 #ifdef SUPPORT_JOYSTICK
 475         struct gameport gameport;
 476         struct resource *res_joystick;
 477 #endif
 478
 479         spinlock_t reg_lock;
 480 };
 481
 482
 483 /* read/write operations for dword register */
 484 inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
 485 {
 486         outl(data, cm->iobase + cmd);
 487 }
 488 inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
 489 {
 490         return inl(cm->iobase + cmd);
 491 }
 492
 493 /* read/write operations for word register */
 494 inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
 495 {
 496         outw(data, cm->iobase + cmd);
 497 }
 498 inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
 499 {
 500         return inw(cm->iobase + cmd);
 501 }
 502
 503 /* read/write operations for byte register */
 504 inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
 505 {
 506         outb(data, cm->iobase + cmd);
 507 }
 508
 509 inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
 510 {
 511         return inb(cm->iobase + cmd);
 512 }
 513
 514 /* bit operations for dword register */
 515 static void snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
 516 {
 517         unsigned int val;
 518         val = inl(cm->iobase + cmd);
 519         val |= flag;
 520         outl(val, cm->iobase + cmd);
 521 }
 522
 523 static void snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
 524 {
 525         unsigned int val;
 526         val = inl(cm->iobase + cmd);
 527         val &= ~flag;
 528         outl(val, cm->iobase + cmd);
 529 }
 530
 531 #if 0 // not used
 532 /* bit operations for byte register */
 533 static void snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
 534 {
 535         unsigned char val;
 536         val = inb(cm->iobase + cmd);
 537         val |= flag;
 538         outb(val, cm->iobase + cmd);
 539 }
 540
 541 static void snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
 542 {
 543         unsigned char val;
 544         val = inb(cm->iobase + cmd);
 545         val &= ~flag;
 546         outb(val, cm->iobase + cmd);
 547 }
 548 #endif
 549
 550
 551 /*
 552  * PCM interface
 553  */
 554
 555 /*
 556  * calculate frequency
 557  */
 558
 559 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 560
 561 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 562 {
 563         unsigned int i;
 564         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 565                 if (rates[i] == rate)
 566                         return i;
 567         }
 568         snd_BUG();
 569         return 0;
 570 }
 571
 572 #ifdef USE_VAR48KRATE
 573 /*
 574  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 575  * does it this way .. maybe not.  Never get any information from C-Media about
 576  * that <werner@suse.de>.
 577  */
 578 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 579 {
 580         unsigned int delta, tolerance;
 581         int xm, xn, xr;
 582
 583         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 584                 rate <<= 1;
 585         *n = -1;
 586         if (*r > 0xff)
 587                 goto out;
 588         tolerance = rate*CM_TOLERANCE_RATE;
 589
 590         for (xn = (1+2); xn < (0x1f+2); xn++) {
 591                 for (xm = (1+2); xm < (0xff+2); xm++) {
 592                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 593
 594                         if (xr < rate)
 595                                 delta = rate - xr;
 596                         else
 597                                 delta = xr - rate;
 598
 599                         /*
 600                          * If we found one, remember this,
 601                          * and try to find a closer one
 602                          */
 603                         if (delta < tolerance) {
 604                                 tolerance = delta;
 605                                 *m = xm - 2;
 606                                 *n = xn - 2;
 607                         }
 608                 }
 609         }
 610 out:
 611         return (*n > -1);
 612 }
 613
 614 /*
 615  * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
 616  * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
 617  * at the register CM_REG_FUNCTRL1 (0x04).
 618  * Problem: other ways are also possible (any information about that?)
 619  */
 620 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
 621 {
 622         unsigned int reg = CM_REG_PLL + slot;
 623         /*
 624          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 625          * for DSFC/ASFC (000 upto 111).
 626          */
 627
 628         /* FIXME: Init (Do we've to set an other register first before programming?) */
 629
 630         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 631         snd_cmipci_write_b(cm, reg, rate>>8);
 632         snd_cmipci_write_b(cm, reg, rate&0xff);
 633
 634         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 635 }
 636 #endif /* USE_VAR48KRATE */
 637
 638 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
 639                                 snd_pcm_hw_params_t * hw_params)
 640 {
 641         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 642 }
 643
 644 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
 645                                           snd_pcm_hw_params_t * hw_params)
 646 {
 647         cmipci_t *cm = snd_pcm_substream_chip(substream);
 648         if (params_channels(hw_params) > 2) {
 649                 down(&cm->open_mutex);
 650                 if (cm->opened[CM_CH_PLAY]) {
 651                         up(&cm->open_mutex);
 652                         return -EBUSY;
 653                 }
 654                 /* reserve the channel A */
 655                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 656                 up(&cm->open_mutex);
 657         }
 658         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 659 }
 660
 661 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
 662 {
 663         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 664         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 665         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 666         udelay(10);
 667 }
 668
 669 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
 670 {
 671         return snd_pcm_lib_free_pages(substream);
 672 }
 673
 674
 675 /*
 676  */
 677
 678 static unsigned int hw_channels[] = {1, 2, 4, 5, 6};
 679 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
 680         .count = 3,
 681         .list = hw_channels,
 682         .mask = 0,
 683 };
 684 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
 685         .count = 5,
 686         .list = hw_channels,
 687         .mask = 0,
 688 };
 689
 690 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
 691 {
 692         if (channels > 2) {
 693                 if (! cm->can_multi_ch)
 694                         return -EINVAL;
 695                 if (rec->fmt != 0x03) /* stereo 16bit only */
 696                         return -EINVAL;
 697
 698                 spin_lock_irq(&cm->reg_lock);
 699                 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 700                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 701                 if (channels > 4) {
 702                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 703                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 704                 } else {
 705                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 706                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 707                 }
 708                 if (channels == 6) {
 709                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 710                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 711                 } else {
 712                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 713                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 714                 }
 715                 spin_unlock_irq(&cm->reg_lock);
 716
 717         } else {
 718                 if (cm->can_multi_ch) {
 719                         spin_lock_irq(&cm->reg_lock);
 720                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 721                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 722                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 723                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 724                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 725                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 726                         spin_unlock_irq(&cm->reg_lock);
 727                 }
 728         }
 729         return 0;
 730 }
 731
 732
 733 /*
 734  * prepare playback/capture channel
 735  * channel to be used must have been set in rec->ch.
 736  */
 737 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
 738                                  snd_pcm_substream_t *substream)
 739 {
 740         unsigned int reg, freq, val;
 741         snd_pcm_runtime_t *runtime = substream->runtime;
 742
 743         rec->fmt = 0;
 744         rec->shift = 0;
 745         if (snd_pcm_format_width(runtime->format) >= 16) {
 746                 rec->fmt |= 0x02;
 747                 if (snd_pcm_format_width(runtime->format) > 16)
 748                         rec->shift++; /* 24/32bit */
 749         }
 750         if (runtime->channels > 1)
 751                 rec->fmt |= 0x01;
 752         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 753                 snd_printd("cannot set dac channels\n");
 754                 return -EINVAL;
 755         }
 756
 757         rec->offset = runtime->dma_addr;
 758         /* buffer and period sizes in frame */
 759         rec->dma_size = runtime->buffer_size << rec->shift;
 760         rec->period_size = runtime->period_size << rec->shift;
 761         if (runtime->channels > 2) {
 762                 /* multi-channels */
 763                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 764                 rec->period_size = (rec->period_size * runtime->channels) / 2;
 765         }
 766
 767         spin_lock_irq(&cm->reg_lock);
 768
 769         /* set buffer address */
 770         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 771         snd_cmipci_write(cm, reg, rec->offset);
 772         /* program sample counts */
 773         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 774         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 775         snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
 776
 777         /* set adc/dac flag */
 778         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 779         if (rec->is_dac)
 780                 cm->ctrl &= ~val;
 781         else
 782                 cm->ctrl |= val;
 783         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 784         //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
 785
 786         /* set sample rate */
 787         freq = snd_cmipci_rate_freq(runtime->rate);
 788         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 789         if (rec->ch) {
 790                 val &= ~CM_ASFC_MASK;
 791                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 792         } else {
 793                 val &= ~CM_DSFC_MASK;
 794                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 795         }
 796         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 797         //snd_printd("cmipci: functrl1 = %08x\n", val);
 798
 799         /* set format */
 800         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 801         if (rec->ch) {
 802                 val &= ~CM_CH1FMT_MASK;
 803                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 804         } else {
 805                 val &= ~CM_CH0FMT_MASK;
 806                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 807         }
 808         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 809         //snd_printd("cmipci: chformat = %08x\n", val);
 810
 811         rec->running = 0;
 812         spin_unlock_irq(&cm->reg_lock);
 813
 814         return 0;
 815 }
 816
 817 /*
 818  * PCM trigger/stop
 819  */
 820 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
 821                                  snd_pcm_substream_t *substream, int cmd)
 822 {
 823         unsigned int inthld, chen, reset, pause;
 824         int result = 0;
 825
 826         inthld = CM_CH0_INT_EN << rec->ch;
 827         chen = CM_CHEN0 << rec->ch;
 828         reset = CM_RST_CH0 << rec->ch;
 829         pause = CM_PAUSE0 << rec->ch;
 830
 831         spin_lock(&cm->reg_lock);
 832         switch (cmd) {
 833         case SNDRV_PCM_TRIGGER_START:
 834                 rec->running = 1;
 835                 /* set interrupt */
 836                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 837                 cm->ctrl |= chen;
 838                 /* enable channel */
 839                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 840                 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
 841                 break;
 842         case SNDRV_PCM_TRIGGER_STOP:
 843                 rec->running = 0;
 844                 /* disable interrupt */
 845                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 846                 /* reset */
 847                 cm->ctrl &= ~chen;
 848                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 849                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 850                 break;
 851         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 852                 cm->ctrl |= pause;
 853                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 854                 break;
 855         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 856                 cm->ctrl &= ~pause;
 857                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 858                 break;
 859         default:
 860                 result = -EINVAL;
 861                 break;
 862         }
 863         spin_unlock(&cm->reg_lock);
 864         return result;
 865 }
 866
 867 /*
 868  * return the current pointer
 869  */
 870 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
 871                                           snd_pcm_substream_t *substream)
 872 {
 873         size_t ptr;
 874         unsigned int reg;
 875         if (!rec->running)
 876                 return 0;
 877 #if 1 // this seems better..
 878         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 879         ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
 880         ptr >>= rec->shift;
 881 #else
 882         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 883         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 884         ptr = bytes_to_frames(substream->runtime, ptr);
 885 #endif
 886         if (substream->runtime->channels > 2)
 887                 ptr = (ptr * 2) / substream->runtime->channels;
 888         return ptr;
 889 }
 890
 891 /*
 892  * playback
 893  */
 894
 895 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
 896                                        int cmd)
 897 {
 898         cmipci_t *cm = snd_pcm_substream_chip(substream);
 899         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
 900 }
 901
 902 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
 903 {
 904         cmipci_t *cm = snd_pcm_substream_chip(substream);
 905         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 906 }
 907
 908
 909
 910 /*
 911  * capture
 912  */
 913
 914 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
 915                                      int cmd)
 916 {
 917         cmipci_t *cm = snd_pcm_substream_chip(substream);
 918         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
 919 }
 920
 921 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
 922 {
 923         cmipci_t *cm = snd_pcm_substream_chip(substream);
 924         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 925 }
 926
 927
 928 /*
 929  * hw preparation for spdif
 930  */
 931
 932 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
 933                                          snd_ctl_elem_info_t *uinfo)
 934 {
 935         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 936         uinfo->count = 1;
 937         return 0;
 938 }
 939
 940 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
 941                                         snd_ctl_elem_value_t *ucontrol)
 942 {
 943         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
 944         int i;
 945
 946         spin_lock_irq(&chip->reg_lock);
 947         for (i = 0; i < 4; i++)
 948                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
 949         spin_unlock_irq(&chip->reg_lock);
 950         return 0;
 951 }
 952
 953 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
 954                                          snd_ctl_elem_value_t * ucontrol)
 955 {
 956         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
 957         int i, change;
 958         unsigned int val;
 959
 960         val = 0;
 961         spin_lock_irq(&chip->reg_lock);
 962         for (i = 0; i < 4; i++)
 963                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
 964         change = val != chip->dig_status;
 965         chip->dig_status = val;
 966         spin_unlock_irq(&chip->reg_lock);
 967         return change;
 968 }
 969
 970 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
 971 {
 972         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
 973         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
 974         .info =         snd_cmipci_spdif_default_info,
 975         .get =          snd_cmipci_spdif_default_get,
 976         .put =          snd_cmipci_spdif_default_put
 977 };
 978
 979 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
 980                                       snd_ctl_elem_info_t *uinfo)
 981 {
 982         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 983         uinfo->count = 1;
 984         return 0;
 985 }
 986
 987 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
 988                                      snd_ctl_elem_value_t *ucontrol)
 989 {
 990         ucontrol->value.iec958.status[0] = 0xff;
 991         ucontrol->value.iec958.status[1] = 0xff;
 992         ucontrol->value.iec958.status[2] = 0xff;
 993         ucontrol->value.iec958.status[3] = 0xff;
 994         return 0;
 995 }
 996
 997 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
 998 {
 999         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1000         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1001         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1002         .info =         snd_cmipci_spdif_mask_info,
1003         .get =          snd_cmipci_spdif_mask_get,
1004 };
1005
1006 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1007                                         snd_ctl_elem_info_t *uinfo)
1008 {
1009         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1010         uinfo->count = 1;
1011         return 0;
1012 }
1013
1014 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1015                                        snd_ctl_elem_value_t *ucontrol)
1016 {
1017         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1018         int i;
1019
1020         spin_lock_irq(&chip->reg_lock);
1021         for (i = 0; i < 4; i++)
1022                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1023         spin_unlock_irq(&chip->reg_lock);
1024         return 0;
1025 }
1026
1027 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1028                                        snd_ctl_elem_value_t *ucontrol)
1029 {
1030         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1031         int i, change;
1032         unsigned int val;
1033
1034         val = 0;
1035         spin_lock_irq(&chip->reg_lock);
1036         for (i = 0; i < 4; i++)
1037                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1038         change = val != chip->dig_pcm_status;
1039         chip->dig_pcm_status = val;
1040         spin_unlock_irq(&chip->reg_lock);
1041         return change;
1042 }
1043
1044 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1045 {
1046         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1047         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1048         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1049         .info =         snd_cmipci_spdif_stream_info,
1050         .get =          snd_cmipci_spdif_stream_get,
1051         .put =          snd_cmipci_spdif_stream_put
1052 };
1053
1054 /*
1055  */
1056
1057 /* save mixer setting and mute for AC3 playback */
1058 static int save_mixer_state(cmipci_t *cm)
1059 {
1060         if (! cm->mixer_insensitive) {
1061                 snd_ctl_elem_value_t *val;
1062                 unsigned int i;
1063
1064                 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1065                 if (!val)
1066                         return -ENOMEM;
1067                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1068                         snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1069                         if (ctl) {
1070                                 int event;
1071                                 memset(val, 0, sizeof(*val));
1072                                 ctl->get(ctl, val);
1073                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1074                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1075                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1076                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1077                                         ctl->put(ctl, val); /* toggle */
1078                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1079                                 }
1080                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1081                                 snd_ctl_notify(cm->card, event, &ctl->id);
1082                         }
1083                 }
1084                 kfree(val);
1085                 cm->mixer_insensitive = 1;
1086         }
1087         return 0;
1088 }
1089
1090
1091 /* restore the previously saved mixer status */
1092 static void restore_mixer_state(cmipci_t *cm)
1093 {
1094         if (cm->mixer_insensitive) {
1095                 snd_ctl_elem_value_t *val;
1096                 unsigned int i;
1097
1098                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1099                 if (!val)
1100                         return;
1101                 cm->mixer_insensitive = 0; /* at first clear this;
1102                                               otherwise the changes will be ignored */
1103                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1104                         snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1105                         if (ctl) {
1106                                 int event;
1107
1108                                 memset(val, 0, sizeof(*val));
1109                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1110                                 ctl->get(ctl, val);
1111                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1112                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1113                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1114                                         ctl->put(ctl, val);
1115                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1116                                 }
1117                                 snd_ctl_notify(cm->card, event, &ctl->id);
1118                         }
1119                 }
1120                 kfree(val);
1121         }
1122 }
1123
1124 /* spinlock held! */
1125 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1126 {
1127         if (do_ac3) {
1128                 /* AC3EN for 037 */
1129                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1130                 /* AC3EN for 039 */
1131                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1132
1133                 if (cm->can_ac3_hw) {
1134                         /* SPD24SEL for 037, 0x02 */
1135                         /* SPD24SEL for 039, 0x20, but cannot be set */
1136                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1137                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1138                 } else { /* can_ac3_sw */
1139                         /* SPD32SEL for 037 & 039, 0x20 */
1140                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1141                         /* set 176K sample rate to fix 033 HW bug */
1142                         if (cm->chip_version == 33) {
1143                                 if (rate >= 48000) {
1144                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1145                                 } else {
1146                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1147                                 }
1148                         }
1149                 }
1150
1151         } else {
1152                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1153                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1154
1155                 if (cm->can_ac3_hw) {
1156                         /* chip model >= 37 */
1157                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1158                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1159                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1160                         } else {
1161                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1162                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1163                         }
1164                 } else {
1165                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1166                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1167                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1168                 }
1169         }
1170 }
1171
1172 static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1173 {
1174         int rate, err;
1175
1176         rate = subs->runtime->rate;
1177
1178         if (up && do_ac3)
1179                 if ((err = save_mixer_state(cm)) < 0)
1180                         return err;
1181
1182         spin_lock_irq(&cm->reg_lock);
1183         cm->spdif_playback_avail = up;
1184         if (up) {
1185                 /* they are controlled via "IEC958 Output Switch" */
1186                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1187                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1188                 if (cm->spdif_playback_enabled)
1189                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1190                 setup_ac3(cm, subs, do_ac3, rate);
1191
1192                 if (rate == 48000)
1193                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1194                 else
1195                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1196
1197         } else {
1198                 /* they are controlled via "IEC958 Output Switch" */
1199                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1200                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1201                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1202                 setup_ac3(cm, subs, 0, 0);
1203         }
1204         spin_unlock_irq(&cm->reg_lock);
1205         return 0;
1206 }
1207
1208
1209 /*
1210  * preparation
1211  */
1212
1213 /* playback - enable spdif only on the certain condition */
1214 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1215 {
1216         cmipci_t *cm = snd_pcm_substream_chip(substream);
1217         int rate = substream->runtime->rate;
1218         int err, do_spdif, do_ac3 = 0;
1219
1220         do_spdif = ((rate == 44100 || rate == 48000) &&
1221                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1222                     substream->runtime->channels == 2);
1223         if (do_spdif && cm->can_ac3_hw)
1224                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1225         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1226                 return err;
1227         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1228 }
1229
1230 /* playback  (via device #2) - enable spdif always */
1231 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1232 {
1233         cmipci_t *cm = snd_pcm_substream_chip(substream);
1234         int err, do_ac3;
1235
1236         if (cm->can_ac3_hw)
1237                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1238         else
1239                 do_ac3 = 1; /* doesn't matter */
1240         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1241                 return err;
1242         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1243 }
1244
1245 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1246 {
1247         cmipci_t *cm = snd_pcm_substream_chip(substream);
1248         setup_spdif_playback(cm, substream, 0, 0);
1249         restore_mixer_state(cm);
1250         return snd_cmipci_hw_free(substream);
1251 }
1252
1253 /* capture */
1254 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1255 {
1256         cmipci_t *cm = snd_pcm_substream_chip(substream);
1257         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1258 }
1259
1260 /* capture with spdif (via device #2) */
1261 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1262 {
1263         cmipci_t *cm = snd_pcm_substream_chip(substream);
1264
1265         spin_lock_irq(&cm->reg_lock);
1266         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1267         spin_unlock_irq(&cm->reg_lock);
1268
1269         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1270 }
1271
1272 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1273 {
1274         cmipci_t *cm = snd_pcm_substream_chip(subs);
1275
1276         spin_lock_irq(&cm->reg_lock);
1277         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1278         spin_unlock_irq(&cm->reg_lock);
1279
1280         return snd_cmipci_hw_free(subs);
1281 }
1282
1283
1284 /*
1285  * interrupt handler
1286  */
1287 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1288 {
1289         cmipci_t *cm = dev_id;
1290         unsigned int status, mask = 0;
1291
1292         /* fastpath out, to ease interrupt sharing */
1293         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1294         if (!(status & CM_INTR))
1295                 return IRQ_NONE;
1296
1297         /* acknowledge interrupt */
1298         spin_lock(&cm->reg_lock);
1299         if (status & CM_CHINT0)
1300                 mask |= CM_CH0_INT_EN;
1301         if (status & CM_CHINT1)
1302                 mask |= CM_CH1_INT_EN;
1303         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1304         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1305         spin_unlock(&cm->reg_lock);
1306
1307         if (cm->rmidi && (status & CM_UARTINT))
1308                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1309
1310         if (cm->pcm) {
1311                 if ((status & CM_CHINT0) && cm->channel[0].running)
1312                         snd_pcm_period_elapsed(cm->channel[0].substream);
1313                 if ((status & CM_CHINT1) && cm->channel[1].running)
1314                         snd_pcm_period_elapsed(cm->channel[1].substream);
1315         }
1316         return IRQ_HANDLED;
1317 }
1318
1319 /*
1320  * h/w infos
1321  */
1322
1323 /* playback on channel A */
1324 static snd_pcm_hardware_t snd_cmipci_playback =
1325 {
1326         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1327                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1328                                  SNDRV_PCM_INFO_MMAP_VALID),
1329         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1330         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1331         .rate_min =             5512,
1332         .rate_max =             48000,
1333         .channels_min =         1,
1334         .channels_max =         2,
1335         .buffer_bytes_max =     (128*1024),
1336         .period_bytes_min =     64,
1337         .period_bytes_max =     (128*1024),
1338         .periods_min =          2,
1339         .periods_max =          1024,
1340         .fifo_size =            0,
1341 };
1342
1343 /* capture on channel B */
1344 static snd_pcm_hardware_t snd_cmipci_capture =
1345 {
1346         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1347                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1348                                  SNDRV_PCM_INFO_MMAP_VALID),
1349         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1350         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1351         .rate_min =             5512,
1352         .rate_max =             48000,
1353         .channels_min =         1,
1354         .channels_max =         2,
1355         .buffer_bytes_max =     (128*1024),
1356         .period_bytes_min =     64,
1357         .period_bytes_max =     (128*1024),
1358         .periods_min =          2,
1359         .periods_max =          1024,
1360         .fifo_size =            0,
1361 };
1362
1363 /* playback on channel B - stereo 16bit only? */
1364 static snd_pcm_hardware_t snd_cmipci_playback2 =
1365 {
1366         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1367                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1368                                  SNDRV_PCM_INFO_MMAP_VALID),
1369         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1370         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1371         .rate_min =             5512,
1372         .rate_max =             48000,
1373         .channels_min =         2,
1374         .channels_max =         2,
1375         .buffer_bytes_max =     (128*1024),
1376         .period_bytes_min =     64,
1377         .period_bytes_max =     (128*1024),
1378         .periods_min =          2,
1379         .periods_max =          1024,
1380         .fifo_size =            0,
1381 };
1382
1383 /* spdif playback on channel A */
1384 static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1385 {
1386         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1387                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1388                                  SNDRV_PCM_INFO_MMAP_VALID),
1389         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1390         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1391         .rate_min =             44100,
1392         .rate_max =             48000,
1393         .channels_min =         2,
1394         .channels_max =         2,
1395         .buffer_bytes_max =     (128*1024),
1396         .period_bytes_min =     64,
1397         .period_bytes_max =     (128*1024),
1398         .periods_min =          2,
1399         .periods_max =          1024,
1400         .fifo_size =            0,
1401 };
1402
1403 /* spdif playback on channel A (32bit, IEC958 subframes) */
1404 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1405 {
1406         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1407                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1408                                  SNDRV_PCM_INFO_MMAP_VALID),
1409         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1410         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1411         .rate_min =             44100,
1412         .rate_max =             48000,
1413         .channels_min =         2,
1414         .channels_max =         2,
1415         .buffer_bytes_max =     (128*1024),
1416         .period_bytes_min =     64,
1417         .period_bytes_max =     (128*1024),
1418         .periods_min =          2,
1419         .periods_max =          1024,
1420         .fifo_size =            0,
1421 };
1422
1423 /* spdif capture on channel B */
1424 static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1425 {
1426         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1427                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1428                                  SNDRV_PCM_INFO_MMAP_VALID),
1429         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1430         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1431         .rate_min =             44100,
1432         .rate_max =             48000,
1433         .channels_min =         2,
1434         .channels_max =         2,
1435         .buffer_bytes_max =     (128*1024),
1436         .period_bytes_min =     64,
1437         .period_bytes_max =     (128*1024),
1438         .periods_min =          2,
1439         .periods_max =          1024,
1440         .fifo_size =            0,
1441 };
1442
1443 /*
1444  * check device open/close
1445  */
1446 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1447 {
1448         int ch = mode & CM_OPEN_CH_MASK;
1449
1450         /* FIXME: a file should wait until the device becomes free
1451          * when it's opened on blocking mode.  however, since the current
1452          * pcm framework doesn't pass file pointer before actually opened,
1453          * we can't know whether blocking mode or not in open callback..
1454          */
1455         down(&cm->open_mutex);
1456         if (cm->opened[ch]) {
1457                 up(&cm->open_mutex);
1458                 return -EBUSY;
1459         }
1460         cm->opened[ch] = mode;
1461         cm->channel[ch].substream = subs;
1462         if (! (mode & CM_OPEN_DAC)) {
1463                 /* disable dual DAC mode */
1464                 cm->channel[ch].is_dac = 0;
1465                 spin_lock_irq(&cm->reg_lock);
1466                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1467                 spin_unlock_irq(&cm->reg_lock);
1468         }
1469         up(&cm->open_mutex);
1470         return 0;
1471 }
1472
1473 static void close_device_check(cmipci_t *cm, int mode)
1474 {
1475         int ch = mode & CM_OPEN_CH_MASK;
1476
1477         down(&cm->open_mutex);
1478         if (cm->opened[ch] == mode) {
1479                 if (cm->channel[ch].substream) {
1480                         snd_cmipci_ch_reset(cm, ch);
1481                         cm->channel[ch].running = 0;
1482                         cm->channel[ch].substream = NULL;
1483                 }
1484                 cm->opened[ch] = 0;
1485                 if (! cm->channel[ch].is_dac) {
1486                         /* enable dual DAC mode again */
1487                         cm->channel[ch].is_dac = 1;
1488                         spin_lock_irq(&cm->reg_lock);
1489                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1490                         spin_unlock_irq(&cm->reg_lock);
1491                 }
1492         }
1493         up(&cm->open_mutex);
1494 }
1495
1496 /*
1497  */
1498
1499 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1500 {
1501         cmipci_t *cm = snd_pcm_substream_chip(substream);
1502         snd_pcm_runtime_t *runtime = substream->runtime;
1503         int err;
1504
1505         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1506                 return err;
1507         runtime->hw = snd_cmipci_playback;
1508         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1509         cm->dig_pcm_status = cm->dig_status;
1510         return 0;
1511 }
1512
1513 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1514 {
1515         cmipci_t *cm = snd_pcm_substream_chip(substream);
1516         snd_pcm_runtime_t *runtime = substream->runtime;
1517         int err;
1518
1519         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1520                 return err;
1521         runtime->hw = snd_cmipci_capture;
1522         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1523         return 0;
1524 }
1525
1526 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1527 {
1528         cmipci_t *cm = snd_pcm_substream_chip(substream);
1529         snd_pcm_runtime_t *runtime = substream->runtime;
1530         int err;
1531
1532         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1533                 return err;
1534         runtime->hw = snd_cmipci_playback2;
1535         down(&cm->open_mutex);
1536         if (! cm->opened[CM_CH_PLAY]) {
1537                 if (cm->can_multi_ch) {
1538                         runtime->hw.channels_max = cm->max_channels;
1539                         if (cm->max_channels == 4)
1540                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1541                         else
1542                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1543                 }
1544                 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1545         }
1546         up(&cm->open_mutex);
1547         return 0;
1548 }
1549
1550 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1551 {
1552         cmipci_t *cm = snd_pcm_substream_chip(substream);
1553         snd_pcm_runtime_t *runtime = substream->runtime;
1554         int err;
1555
1556         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1557                 return err;
1558         if (cm->can_ac3_hw) {
1559                 runtime->hw = snd_cmipci_playback_spdif;
1560                 if (cm->chip_version >= 37)
1561                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1562         } else {
1563                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1564         }
1565         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1566         cm->dig_pcm_status = cm->dig_status;
1567         return 0;
1568 }
1569
1570 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1571 {
1572         cmipci_t *cm = snd_pcm_substream_chip(substream);
1573         snd_pcm_runtime_t *runtime = substream->runtime;
1574         int err;
1575
1576         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1577                 return err;
1578         runtime->hw = snd_cmipci_capture_spdif;
1579         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1580         return 0;
1581 }
1582
1583
1584 /*
1585  */
1586
1587 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1588 {
1589         cmipci_t *cm = snd_pcm_substream_chip(substream);
1590         close_device_check(cm, CM_OPEN_PLAYBACK);
1591         return 0;
1592 }
1593
1594 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1595 {
1596         cmipci_t *cm = snd_pcm_substream_chip(substream);
1597         close_device_check(cm, CM_OPEN_CAPTURE);
1598         return 0;
1599 }
1600
1601 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1602 {
1603         cmipci_t *cm = snd_pcm_substream_chip(substream);
1604         close_device_check(cm, CM_OPEN_PLAYBACK2);
1605         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1606         return 0;
1607 }
1608
1609 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1610 {
1611         cmipci_t *cm = snd_pcm_substream_chip(substream);
1612         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1613         return 0;
1614 }
1615
1616 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1617 {
1618         cmipci_t *cm = snd_pcm_substream_chip(substream);
1619         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1620         return 0;
1621 }
1622
1623
1624 /*
1625  */
1626
1627 static snd_pcm_ops_t snd_cmipci_playback_ops = {
1628         .open =         snd_cmipci_playback_open,
1629         .close =        snd_cmipci_playback_close,
1630         .ioctl =        snd_pcm_lib_ioctl,
1631         .hw_params =    snd_cmipci_hw_params,
1632         .hw_free =      snd_cmipci_playback_hw_free,
1633         .prepare =      snd_cmipci_playback_prepare,
1634         .trigger =      snd_cmipci_playback_trigger,
1635         .pointer =      snd_cmipci_playback_pointer,
1636 };
1637
1638 static snd_pcm_ops_t snd_cmipci_capture_ops = {
1639         .open =         snd_cmipci_capture_open,
1640         .close =        snd_cmipci_capture_close,
1641         .ioctl =        snd_pcm_lib_ioctl,
1642         .hw_params =    snd_cmipci_hw_params,
1643         .hw_free =      snd_cmipci_hw_free,
1644         .prepare =      snd_cmipci_capture_prepare,
1645         .trigger =      snd_cmipci_capture_trigger,
1646         .pointer =      snd_cmipci_capture_pointer,
1647 };
1648
1649 static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1650         .open =         snd_cmipci_playback2_open,
1651         .close =        snd_cmipci_playback2_close,
1652         .ioctl =        snd_pcm_lib_ioctl,
1653         .hw_params =    snd_cmipci_playback2_hw_params,
1654         .hw_free =      snd_cmipci_hw_free,
1655         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1656         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1657         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1658 };
1659
1660 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1661         .open =         snd_cmipci_playback_spdif_open,
1662         .close =        snd_cmipci_playback_spdif_close,
1663         .ioctl =        snd_pcm_lib_ioctl,
1664         .hw_params =    snd_cmipci_hw_params,
1665         .hw_free =      snd_cmipci_playback_hw_free,
1666         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1667         .trigger =      snd_cmipci_playback_trigger,
1668         .pointer =      snd_cmipci_playback_pointer,
1669 };
1670
1671 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1672         .open =         snd_cmipci_capture_spdif_open,
1673         .close =        snd_cmipci_capture_spdif_close,
1674         .ioctl =        snd_pcm_lib_ioctl,
1675         .hw_params =    snd_cmipci_hw_params,
1676         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1677         .prepare =      snd_cmipci_capture_spdif_prepare,
1678         .trigger =      snd_cmipci_capture_trigger,
1679         .pointer =      snd_cmipci_capture_pointer,
1680 };
1681
1682
1683 /*
1684  */
1685
1686 static void snd_cmipci_pcm_free(snd_pcm_t *pcm)
1687 {
1688         snd_pcm_lib_preallocate_free_for_all(pcm);
1689 }
1690
1691 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1692 {
1693         snd_pcm_t *pcm;
1694         int err;
1695
1696         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1697         if (err < 0)
1698                 return err;
1699
1700         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1701         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1702
1703         pcm->private_data = cm;
1704         pcm->private_free = snd_cmipci_pcm_free;
1705         pcm->info_flags = 0;
1706         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1707         cm->pcm = pcm;
1708
1709         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1710                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1711
1712         return 0;
1713 }
1714
1715 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1716 {
1717         snd_pcm_t *pcm;
1718         int err;
1719
1720         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1721         if (err < 0)
1722                 return err;
1723
1724         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1725
1726         pcm->private_data = cm;
1727         pcm->private_free = snd_cmipci_pcm_free;
1728         pcm->info_flags = 0;
1729         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1730         cm->pcm2 = pcm;
1731
1732         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1733                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1734
1735         return 0;
1736 }
1737
1738 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1739 {
1740         snd_pcm_t *pcm;
1741         int err;
1742
1743         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1744         if (err < 0)
1745                 return err;
1746
1747         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1748         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1749
1750         pcm->private_data = cm;
1751         pcm->private_free = snd_cmipci_pcm_free;
1752         pcm->info_flags = 0;
1753         strcpy(pcm->name, "C-Media PCI IEC958");
1754         cm->pcm_spdif = pcm;
1755
1756         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1757                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1758
1759         return 0;
1760 }
1761
1762 /*
1763  * mixer interface:
1764  * - CM8338/8738 has a compatible mixer interface with SB16, but
1765  *   lack of some elements like tone control, i/o gain and AGC.
1766  * - Access to native registers:
1767  *   - A 3D switch
1768  *   - Output mute switches
1769  */
1770
1771 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1772 {
1773         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1774         outb(data, s->iobase + CM_REG_SB16_DATA);
1775 }
1776
1777 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1778 {
1779         unsigned char v;
1780
1781         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1782         v = inb(s->iobase + CM_REG_SB16_DATA);
1783         return v;
1784 }
1785
1786 /*
1787  * general mixer element
1788  */
1789 typedef struct cmipci_sb_reg {
1790         unsigned int left_reg, right_reg;
1791         unsigned int left_shift, right_shift;
1792         unsigned int mask;
1793         unsigned int invert: 1;
1794         unsigned int stereo: 1;
1795 } cmipci_sb_reg_t;
1796
1797 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1798  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1799
1800 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1801 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1802   .info = snd_cmipci_info_volume, \
1803   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1804   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1805 }
1806
1807 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1808 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1809 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1810 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1811
1812 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1813 {
1814         r->left_reg = val & 0xff;
1815         r->right_reg = (val >> 8) & 0xff;
1816         r->left_shift = (val >> 16) & 0x07;
1817         r->right_shift = (val >> 19) & 0x07;
1818         r->invert = (val >> 22) & 1;
1819         r->stereo = (val >> 23) & 1;
1820         r->mask = (val >> 24) & 0xff;
1821 }
1822
1823 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1824 {
1825         cmipci_sb_reg_t reg;
1826
1827         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1828         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1829         uinfo->count = reg.stereo + 1;
1830         uinfo->value.integer.min = 0;
1831         uinfo->value.integer.max = reg.mask;
1832         return 0;
1833 }
1834
1835 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1836 {
1837         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1838         cmipci_sb_reg_t reg;
1839         int val;
1840
1841         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1842         spin_lock_irq(&cm->reg_lock);
1843         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1844         if (reg.invert)
1845                 val = reg.mask - val;
1846         ucontrol->value.integer.value[0] = val;
1847         if (reg.stereo) {
1848                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1849                 if (reg.invert)
1850                         val = reg.mask - val;
1851                  ucontrol->value.integer.value[1] = val;
1852         }
1853         spin_unlock_irq(&cm->reg_lock);
1854         return 0;
1855 }
1856
1857 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1858 {
1859         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1860         cmipci_sb_reg_t reg;
1861         int change;
1862         int left, right, oleft, oright;
1863
1864         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1865         left = ucontrol->value.integer.value[0] & reg.mask;
1866         if (reg.invert)
1867                 left = reg.mask - left;
1868         left <<= reg.left_shift;
1869         if (reg.stereo) {
1870                 right = ucontrol->value.integer.value[1] & reg.mask;
1871                 if (reg.invert)
1872                         right = reg.mask - right;
1873                 right <<= reg.right_shift;
1874         } else
1875                 right = 0;
1876         spin_lock_irq(&cm->reg_lock);
1877         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1878         left |= oleft & ~(reg.mask << reg.left_shift);
1879         change = left != oleft;
1880         if (reg.stereo) {
1881                 if (reg.left_reg != reg.right_reg) {
1882                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
1883                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1884                 } else
1885                         oright = left;
1886                 right |= oright & ~(reg.mask << reg.right_shift);
1887                 change |= right != oright;
1888                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1889         } else
1890                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1891         spin_unlock_irq(&cm->reg_lock);
1892         return change;
1893 }
1894
1895 /*
1896  * input route (left,right) -> (left,right)
1897  */
1898 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1899 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1900   .info = snd_cmipci_info_input_sw, \
1901   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1902   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1903 }
1904
1905 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1906 {
1907         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1908         uinfo->count = 4;
1909         uinfo->value.integer.min = 0;
1910         uinfo->value.integer.max = 1;
1911         return 0;
1912 }
1913
1914 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1915 {
1916         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1917         cmipci_sb_reg_t reg;
1918         int val1, val2;
1919
1920         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1921         spin_lock_irq(&cm->reg_lock);
1922         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1923         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1924         spin_unlock_irq(&cm->reg_lock);
1925         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1926         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1927         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1928         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1929         return 0;
1930 }
1931
1932 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1933 {
1934         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1935         cmipci_sb_reg_t reg;
1936         int change;
1937         int val1, val2, oval1, oval2;
1938
1939         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1940         spin_lock_irq(&cm->reg_lock);
1941         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1942         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1943         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1944         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1945         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1946         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1947         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1948         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1949         change = val1 != oval1 || val2 != oval2;
1950         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1951         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1952         spin_unlock_irq(&cm->reg_lock);
1953         return change;
1954 }
1955
1956 /*
1957  * native mixer switches/volumes
1958  */
1959
1960 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1961 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1962   .info = snd_cmipci_info_native_mixer, \
1963   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1964   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1965 }
1966
1967 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1968 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1969   .info = snd_cmipci_info_native_mixer, \
1970   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1971   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1972 }
1973
1974 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1975 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1976   .info = snd_cmipci_info_native_mixer, \
1977   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1978   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1979 }
1980
1981 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1982 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1983   .info = snd_cmipci_info_native_mixer, \
1984   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1985   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
1986 }
1987
1988 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1989 {
1990         cmipci_sb_reg_t reg;
1991
1992         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1993         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1994         uinfo->count = reg.stereo + 1;
1995         uinfo->value.integer.min = 0;
1996         uinfo->value.integer.max = reg.mask;
1997         return 0;
1998
1999 }
2000
2001 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2002 {
2003         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2004         cmipci_sb_reg_t reg;
2005         unsigned char oreg, val;
2006
2007         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2008         spin_lock_irq(&cm->reg_lock);
2009         oreg = inb(cm->iobase + reg.left_reg);
2010         val = (oreg >> reg.left_shift) & reg.mask;
2011         if (reg.invert)
2012                 val = reg.mask - val;
2013         ucontrol->value.integer.value[0] = val;
2014         if (reg.stereo) {
2015                 val = (oreg >> reg.right_shift) & reg.mask;
2016                 if (reg.invert)
2017                         val = reg.mask - val;
2018                 ucontrol->value.integer.value[1] = val;
2019         }
2020         spin_unlock_irq(&cm->reg_lock);
2021         return 0;
2022 }
2023
2024 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2025 {
2026         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2027         cmipci_sb_reg_t reg;
2028         unsigned char oreg, nreg, val;
2029
2030         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2031         spin_lock_irq(&cm->reg_lock);
2032         oreg = inb(cm->iobase + reg.left_reg);
2033         val = ucontrol->value.integer.value[0] & reg.mask;
2034         if (reg.invert)
2035                 val = reg.mask - val;
2036         nreg = oreg & ~(reg.mask << reg.left_shift);
2037         nreg |= (val << reg.left_shift);
2038         if (reg.stereo) {
2039                 val = ucontrol->value.integer.value[1] & reg.mask;
2040                 if (reg.invert)
2041                         val = reg.mask - val;
2042                 nreg &= ~(reg.mask << reg.right_shift);
2043                 nreg |= (val << reg.right_shift);
2044         }
2045         outb(nreg, cm->iobase + reg.left_reg);
2046         spin_unlock_irq(&cm->reg_lock);
2047         return (nreg != oreg);
2048 }
2049
2050 /*
2051  * special case - check mixer sensitivity
2052  */
2053 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2054 {
2055         //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2056         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2057 }
2058
2059 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2060 {
2061         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2062         if (cm->mixer_insensitive) {
2063                 /* ignored */
2064                 return 0;
2065         }
2066         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2067 }
2068
2069
2070 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2071         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2072         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2073         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2074         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2075         { /* switch with sensitivity */
2076                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2077                 .name = "PCM Playback Switch",
2078                 .info = snd_cmipci_info_native_mixer,
2079                 .get = snd_cmipci_get_native_mixer_sensitive,
2080                 .put = snd_cmipci_put_native_mixer_sensitive,
2081                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2082         },
2083         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2084         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2085         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2086         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2087         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2088         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2089         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2090         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2091         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2092         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2093         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2094         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2095         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2096         CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2097         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2098         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2099         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2100         CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2101         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2102 };
2103
2104 /*
2105  * other switches
2106  */
2107
2108 typedef struct snd_cmipci_switch_args {
2109         int reg;                /* register index */
2110         unsigned int mask;      /* mask bits */
2111         unsigned int mask_on;   /* mask bits to turn on */
2112         int is_byte: 1;         /* byte access? */
2113         int ac3_sensitive: 1;   /* access forbidden during non-audio operation? */
2114 } snd_cmipci_switch_args_t;
2115
2116 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2117 {
2118         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2119         uinfo->count = 1;
2120         uinfo->value.integer.min = 0;
2121         uinfo->value.integer.max = 1;
2122         return 0;
2123 }
2124
2125 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2126 {
2127         unsigned int val;
2128         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2129
2130         spin_lock_irq(&cm->reg_lock);
2131         if (args->ac3_sensitive && cm->mixer_insensitive) {
2132                 ucontrol->value.integer.value[0] = 0;
2133                 spin_unlock_irq(&cm->reg_lock);
2134                 return 0;
2135         }
2136         if (args->is_byte)
2137                 val = inb(cm->iobase + args->reg);
2138         else
2139                 val = snd_cmipci_read(cm, args->reg);
2140         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2141         spin_unlock_irq(&cm->reg_lock);
2142         return 0;
2143 }
2144
2145 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2146 {
2147         snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2148         snd_assert(args != NULL, return -EINVAL);
2149         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2150 }
2151
2152 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2153 {
2154         unsigned int val;
2155         int change;
2156         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2157
2158         spin_lock_irq(&cm->reg_lock);
2159         if (args->ac3_sensitive && cm->mixer_insensitive) {
2160                 /* ignored */
2161                 spin_unlock_irq(&cm->reg_lock);
2162                 return 0;
2163         }
2164         if (args->is_byte)
2165                 val = inb(cm->iobase + args->reg);
2166         else
2167                 val = snd_cmipci_read(cm, args->reg);
2168         change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2169         if (change) {
2170                 val &= ~args->mask;
2171                 if (ucontrol->value.integer.value[0])
2172                         val |= args->mask_on;
2173                 else
2174                         val |= (args->mask & ~args->mask_on);
2175                 if (args->is_byte)
2176                         outb((unsigned char)val, cm->iobase + args->reg);
2177                 else
2178                         snd_cmipci_write(cm, args->reg, val);
2179         }
2180         spin_unlock_irq(&cm->reg_lock);
2181         return change;
2182 }
2183
2184 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2185 {
2186         snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2187         snd_assert(args != NULL, return -EINVAL);
2188         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2189 }
2190
2191 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2192 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2193   .reg = xreg, \
2194   .mask = xmask, \
2195   .mask_on = xmask_on, \
2196   .is_byte = xis_byte, \
2197   .ac3_sensitive = xac3, \
2198 }
2199
2200 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2201         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2202
2203 #if 0 /* these will be controlled in pcm device */
2204 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2205 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2206 #endif
2207 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2208 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2209 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2210 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2211 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2212 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2213 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2214 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2215 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2216 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2217 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2218 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2219 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2220 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2221 #if CM_CH_PLAY == 1
2222 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2223 #else
2224 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2225 #endif
2226 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2227 DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2228 DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2229 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2230 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2231
2232 #define DEFINE_SWITCH(sname, stype, sarg) \
2233 { .name = sname, \
2234   .iface = stype, \
2235   .info = snd_cmipci_uswitch_info, \
2236   .get = snd_cmipci_uswitch_get, \
2237   .put = snd_cmipci_uswitch_put, \
2238   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2239 }
2240
2241 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2242 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2243
2244
2245 /*
2246  * callbacks for spdif output switch
2247  * needs toggle two registers..
2248  */
2249 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2250 {
2251         int changed;
2252         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2253         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2254         return changed;
2255 }
2256
2257 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2258 {
2259         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2260         int changed;
2261         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2262         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2263         if (changed) {
2264                 if (ucontrol->value.integer.value[0]) {
2265                         if (chip->spdif_playback_avail)
2266                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2267                 } else {
2268                         if (chip->spdif_playback_avail)
2269                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2270                 }
2271         }
2272         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2273         return changed;
2274 }
2275
2276
2277 /* both for CM8338/8738 */
2278 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2279         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2280         DEFINE_MIXER_SWITCH("Line-In As Rear", line_rear),
2281 };
2282
2283 /* for non-multichannel chips */
2284 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2285 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2286
2287 /* only for CM8738 */
2288 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2289 #if 0 /* controlled in pcm device */
2290         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2291         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2292         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2293 #endif
2294         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2295         { .name = "IEC958 Output Switch",
2296           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2297           .info = snd_cmipci_uswitch_info,
2298           .get = snd_cmipci_spdout_enable_get,
2299           .put = snd_cmipci_spdout_enable_put,
2300         },
2301         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2302         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2303         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2304 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2305         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2306         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2307 };
2308
2309 /* only for model 033/037 */
2310 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2311         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2312         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2313         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2314 };
2315
2316 /* only for model 039 or later */
2317 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
2318         DEFINE_MIXER_SWITCH("Line-In As Bass", line_bass),
2319         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2320         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2321         DEFINE_MIXER_SWITCH("Mic As Center/LFE", spdi_phase), /* same bit as spdi_phase */
2322 };
2323
2324 /* card control switches */
2325 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2326         // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2327         DEFINE_CARD_SWITCH("Modem", modem),
2328 };
2329
2330
2331 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2332 {
2333         snd_card_t *card;
2334         snd_kcontrol_new_t *sw;
2335         snd_kcontrol_t *kctl;
2336         unsigned int idx;
2337         int err;
2338
2339         snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2340
2341         card = cm->card;
2342
2343         strcpy(card->mixername, "CMedia PCI");
2344
2345         spin_lock_irq(&cm->reg_lock);
2346         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2347         spin_unlock_irq(&cm->reg_lock);
2348
2349         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2350                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2351                         return err;
2352         }
2353
2354         /* mixer switches */
2355         sw = snd_cmipci_mixer_switches;
2356         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2357                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2358                 if (err < 0)
2359                         return err;
2360         }
2361         if (! cm->can_multi_ch) {
2362                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2363                 if (err < 0)
2364                         return err;
2365         }
2366         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2367             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2368                 sw = snd_cmipci_8738_mixer_switches;
2369                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2370                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2371                         if (err < 0)
2372                                 return err;
2373                 }
2374                 if (cm->can_ac3_hw) {
2375                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2376                                 return err;
2377                         kctl->id.device = pcm_spdif_device;
2378                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2379                                 return err;
2380                         kctl->id.device = pcm_spdif_device;
2381                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2382                                 return err;
2383                         kctl->id.device = pcm_spdif_device;
2384                 }
2385                 if (cm->chip_version <= 37) {
2386                         sw = snd_cmipci_old_mixer_switches;
2387                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2388                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2389                                 if (err < 0)
2390                                         return err;
2391                         }
2392                 }
2393         }
2394         if (cm->chip_version >= 39) {
2395                 sw = snd_cmipci_extra_mixer_switches;
2396                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2397                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2398                         if (err < 0)
2399                                 return err;
2400                 }
2401         }
2402
2403         /* card switches */
2404         sw = snd_cmipci_control_switches;
2405         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2406                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2407                 if (err < 0)
2408                         return err;
2409         }
2410
2411         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2412                 snd_ctl_elem_id_t id;
2413                 snd_kcontrol_t *ctl;
2414                 memset(&id, 0, sizeof(id));
2415                 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2416                 strcpy(id.name, cm_saved_mixer[idx].name);
2417                 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2418                         cm->mixer_res_ctl[idx] = ctl;
2419         }
2420
2421         return 0;
2422 }
2423
2424
2425 /*
2426  * proc interface
2427  */
2428
2429 #ifdef CONFIG_PROC_FS
2430 static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2431                                  snd_info_buffer_t *buffer)
2432 {
2433         cmipci_t *cm = entry->private_data;
2434         int i;
2435
2436         snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2437         for (i = 0; i < 0x40; i++) {
2438                 int v = inb(cm->iobase + i);
2439                 if (i % 4 == 0)
2440                         snd_iprintf(buffer, "%02x: ", i);
2441                 snd_iprintf(buffer, "%02x", v);
2442                 if (i % 4 == 3)
2443                         snd_iprintf(buffer, "\n");
2444                 else
2445                         snd_iprintf(buffer, " ");
2446         }
2447 }
2448
2449 static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2450 {
2451         snd_info_entry_t *entry;
2452
2453         if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2454                 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2455 }
2456 #else /* !CONFIG_PROC_FS */
2457 static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2458 #endif
2459
2460
2461 static struct pci_device_id snd_cmipci_ids[] = {
2462         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2463         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2464         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2465         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2466         {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2467         {0,},
2468 };
2469
2470
2471 /*
2472  * check chip version and capabilities
2473  * driver name is modified according to the chip model
2474  */
2475 static void __devinit query_chip(cmipci_t *cm)
2476 {
2477         unsigned int detect;
2478
2479         /* check reg 0Ch, bit 24-31 */
2480         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2481         if (! detect) {
2482                 /* check reg 08h, bit 24-28 */
2483                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2484                 if (! detect) {
2485                         cm->chip_version = 33;
2486                         cm->max_channels = 2;
2487                         if (cm->do_soft_ac3)
2488                                 cm->can_ac3_sw = 1;
2489                         else
2490                                 cm->can_ac3_hw = 1;
2491                         cm->has_dual_dac = 1;
2492                 } else {
2493                         cm->chip_version = 37;
2494                         cm->max_channels = 2;
2495                         cm->can_ac3_hw = 1;
2496                         cm->has_dual_dac = 1;
2497                 }
2498         } else {
2499                 /* check reg 0Ch, bit 26 */
2500                 if (detect & CM_CHIP_039) {
2501                         cm->chip_version = 39;
2502                         if (detect & CM_CHIP_039_6CH)
2503                                 cm->max_channels  = 6;
2504                         else
2505                                 cm->max_channels = 4;
2506                         cm->can_ac3_hw = 1;
2507                         cm->has_dual_dac = 1;
2508                         cm->can_multi_ch = 1;
2509                 } else {
2510                         cm->chip_version = 55; /* 4 or 6 channels */
2511                         cm->max_channels  = 6;
2512                         cm->can_ac3_hw = 1;
2513                         cm->has_dual_dac = 1;
2514                         cm->can_multi_ch = 1;
2515                 }
2516         }
2517
2518         /* added -MCx suffix for chip supporting multi-channels */
2519         if (cm->can_multi_ch)
2520                 sprintf(cm->card->driver + strlen(cm->card->driver),
2521                         "-MC%d", cm->max_channels);
2522         else if (cm->can_ac3_sw)
2523                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2524 }
2525
2526
2527 static int snd_cmipci_free(cmipci_t *cm)
2528 {
2529         if (cm->irq >= 0) {
2530                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2531                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2532                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2533                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2534                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2535                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2536                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2537
2538                 /* reset mixer */
2539                 snd_cmipci_mixer_write(cm, 0, 0);
2540
2541                 synchronize_irq(cm->irq);
2542
2543                 free_irq(cm->irq, (void *)cm);
2544         }
2545 #ifdef SUPPORT_JOYSTICK
2546         if (cm->res_joystick) {
2547                 gameport_unregister_port(&cm->gameport);
2548                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2549                 release_resource(cm->res_joystick);
2550                 kfree_nocheck(cm->res_joystick);
2551         }
2552 #endif
2553         pci_release_regions(cm->pci);
2554         kfree(cm);
2555         return 0;
2556 }
2557
2558 static int snd_cmipci_dev_free(snd_device_t *device)
2559 {
2560         cmipci_t *cm = device->device_data;
2561         return snd_cmipci_free(cm);
2562 }
2563
2564 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2565                                        int dev, cmipci_t **rcmipci)
2566 {
2567         cmipci_t *cm;
2568         int err;
2569         static snd_device_ops_t ops = {
2570                 .dev_free =     snd_cmipci_dev_free,
2571         };
2572         unsigned int val = 0;
2573         long iomidi = mpu_port[dev];
2574         long iosynth = fm_port[dev];
2575         int pcm_index, pcm_spdif_index;
2576
2577         *rcmipci = NULL;
2578
2579         if ((err = pci_enable_device(pci)) < 0)
2580                 return err;
2581
2582         cm = kcalloc(1, sizeof(*cm), GFP_KERNEL);
2583         if (cm == NULL)
2584                 return -ENOMEM;
2585
2586         spin_lock_init(&cm->reg_lock);
2587         init_MUTEX(&cm->open_mutex);
2588         cm->device = pci->device;
2589         cm->card = card;
2590         cm->pci = pci;
2591         cm->irq = -1;
2592         cm->channel[0].ch = 0;
2593         cm->channel[1].ch = 1;
2594         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2595
2596         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2597                 kfree(cm);
2598                 return err;
2599         }
2600         cm->iobase = pci_resource_start(pci, 0);
2601
2602         if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
2603                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2604                 err = -EBUSY;
2605                 goto __error;
2606         }
2607         cm->irq = pci->irq;
2608
2609         pci_set_master(cm->pci);
2610
2611         /*
2612          * check chip version, max channels and capabilities
2613          */
2614
2615         cm->chip_version = 0;
2616         cm->max_channels = 2;
2617         cm->do_soft_ac3 = soft_ac3[dev];
2618
2619         query_chip(cm);
2620
2621         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2622         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2623
2624 #if CM_CH_PLAY == 1
2625         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
2626 #else
2627         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
2628 #endif
2629
2630         /* initialize codec registers */
2631         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
2632         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2633         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2634         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
2635         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2636
2637         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2638         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2639 #if CM_CH_PLAY == 1
2640         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2641 #else
2642         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2643 #endif
2644         /* Set Bus Master Request */
2645         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2646
2647         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2648         switch (pci->device) {
2649         case PCI_DEVICE_ID_CMEDIA_CM8738:
2650         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2651                 /* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX */
2652                 if (! pci_find_device(0x8086, 0x7030, NULL))
2653                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2654                 break;
2655         default:
2656                 break;
2657         }
2658
2659         /* set MPU address */
2660         switch (iomidi) {
2661         case 0x320: val = CM_VMPU_320; break;
2662         case 0x310: val = CM_VMPU_310; break;
2663         case 0x300: val = CM_VMPU_300; break;
2664         case 0x330: val = CM_VMPU_330; break;
2665         default:
2666                 iomidi = 0; break;
2667         }
2668         if (iomidi > 0) {
2669                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2670                 /* enable UART */
2671                 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2672         }
2673
2674         /* set FM address */
2675         val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2676         switch (iosynth) {
2677         case 0x3E8: val |= CM_FMSEL_3E8; break;
2678         case 0x3E0: val |= CM_FMSEL_3E0; break;
2679         case 0x3C8: val |= CM_FMSEL_3C8; break;
2680         case 0x388: val |= CM_FMSEL_388; break;
2681         default:
2682                 iosynth = 0; break;
2683         }
2684         if (iosynth > 0) {
2685                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2686                 /* enable FM */
2687                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2688
2689                 if (snd_opl3_create(card, iosynth, iosynth + 2,
2690                                     OPL3_HW_OPL3, 0, &cm->opl3) < 0) {
2691                         printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth);
2692                         iosynth = 0;
2693                 } else {
2694                         if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) {
2695                                 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2696                                 return err;
2697                         }
2698                 }
2699         }
2700         if (! iosynth) {
2701                 /* disable FM */
2702                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK);
2703                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2704         }
2705
2706         /* reset mixer */
2707         snd_cmipci_mixer_write(cm, 0, 0);
2708
2709         snd_cmipci_proc_init(cm);
2710
2711         /* create pcm devices */
2712         pcm_index = pcm_spdif_index = 0;
2713         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2714                 goto __error;
2715         pcm_index++;
2716         if (cm->has_dual_dac) {
2717                 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2718                         goto __error;
2719                 pcm_index++;
2720         }
2721         if (cm->can_ac3_hw || cm->can_ac3_sw) {
2722                 pcm_spdif_index = pcm_index;
2723                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2724                         goto __error;
2725         }
2726
2727         /* create mixer interface & switches */
2728         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2729                 goto __error;
2730
2731         if (iomidi > 0) {
2732                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2733                                                iomidi, 0,
2734                                                cm->irq, 0, &cm->rmidi)) < 0) {
2735                         printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2736                 }
2737         }
2738
2739         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2740                 snd_cmipci_free(cm);
2741                 return err;
2742         }
2743 #ifdef USE_VAR48KRATE
2744         for (val = 0; val < ARRAY_SIZE(rates); val++)
2745                 snd_cmipci_set_pll(cm, rates[val], val);
2746
2747         /*
2748          * (Re-)Enable external switch spdo_48k
2749          */
2750         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2751 #endif /* USE_VAR48KRATE */
2752
2753 #ifdef SUPPORT_JOYSTICK
2754         if (joystick_port[dev] > 0) {
2755                 if (joystick_port[dev] == 1) { /* auto-detect */
2756                         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2757                         int i;
2758                         for (i = 0; ports[i]; i++) {
2759                                 joystick_port[dev] = ports[i];
2760                                 cm->res_joystick = request_region(ports[i], 1, "CMIPCI gameport");
2761                                 if (cm->res_joystick)
2762                                         break;
2763                         }
2764                 } else {
2765                         cm->res_joystick = request_region(joystick_port[dev], 1, "CMIPCI gameport");
2766                 }
2767         }
2768         if (cm->res_joystick) {
2769                 cm->gameport.io = joystick_port[dev];
2770                 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2771                 gameport_register_port(&cm->gameport);
2772         } else {
2773                 if (joystick_port[dev] > 0)
2774                         printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2775                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2776         }
2777 #endif
2778         snd_card_set_dev(card, &pci->dev);
2779
2780         *rcmipci = cm;
2781         return 0;
2782
2783  __error:
2784         snd_cmipci_free(cm);
2785         return err;
2786 }
2787
2788 /*
2789  */
2790
2791 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2792
2793 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2794                                       const struct pci_device_id *pci_id)
2795 {
2796         static int dev;
2797         snd_card_t *card;
2798         cmipci_t *cm;
2799         int err;
2800
2801         if (dev >= SNDRV_CARDS)
2802                 return -ENODEV;
2803         if (! enable[dev]) {
2804                 dev++;
2805                 return -ENOENT;
2806         }
2807
2808         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2809         if (card == NULL)
2810                 return -ENOMEM;
2811
2812         switch (pci->device) {
2813         case PCI_DEVICE_ID_CMEDIA_CM8738:
2814         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2815                 strcpy(card->driver, "CMI8738");
2816                 break;
2817         case PCI_DEVICE_ID_CMEDIA_CM8338A:
2818         case PCI_DEVICE_ID_CMEDIA_CM8338B:
2819                 strcpy(card->driver, "CMI8338");
2820                 break;
2821         default:
2822                 strcpy(card->driver, "CMIPCI");
2823                 break;
2824         }
2825
2826         if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
2827                 snd_card_free(card);
2828                 return err;
2829         }
2830
2831         sprintf(card->shortname, "C-Media PCI %s", card->driver);
2832         sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
2833                 card->shortname,
2834                 cm->chip_version,
2835                 cm->iobase,
2836                 cm->irq);
2837
2838         //snd_printd("%s is detected\n", card->longname);
2839
2840         if ((err = snd_card_register(card)) < 0) {
2841                 snd_card_free(card);
2842                 return err;
2843         }
2844         pci_set_drvdata(pci, card);
2845         dev++;
2846         return 0;
2847
2848 }
2849
2850 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
2851 {
2852         snd_card_free(pci_get_drvdata(pci));
2853         pci_set_drvdata(pci, NULL);
2854 }
2855
2856
2857 static struct pci_driver driver = {
2858         .name = "C-Media PCI",
2859         .id_table = snd_cmipci_ids,
2860         .probe = snd_cmipci_probe,
2861         .remove = __devexit_p(snd_cmipci_remove),
2862 };
2863
2864 static int __init alsa_card_cmipci_init(void)
2865 {
2866         return pci_module_init(&driver);
2867 }
2868
2869 static void __exit alsa_card_cmipci_exit(void)
2870 {
2871         pci_unregister_driver(&driver);
2872 }
2873
2874 module_init(alsa_card_cmipci_init)
2875 module_exit(alsa_card_cmipci_exit)