sound/pci/cmipci.c

   1 /*
   2  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   3  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program; if not, write to the Free Software
  17  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 /* Does not work. Warning may block system in capture mode */
  21 /* #define USE_VAR48KRATE */
  22
  23 #include <sound/driver.h>
  24 #include <asm/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/init.h>
  28 #include <linux/pci.h>
  29 #include <linux/slab.h>
  30 #include <linux/gameport.h>
  31 #include <linux/moduleparam.h>
  32 #include <sound/core.h>
  33 #include <sound/info.h>
  34 #include <sound/control.h>
  35 #include <sound/pcm.h>
  36 #include <sound/rawmidi.h>
  37 #include <sound/mpu401.h>
  38 #include <sound/opl3.h>
  39 #include <sound/sb.h>
  40 #include <sound/asoundef.h>
  41 #include <sound/initval.h>
  42
  43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  45 MODULE_LICENSE("GPL");
  46 MODULE_CLASSES("{sound}");
  47 MODULE_DEVICES("{{C-Media,CMI8738},"
  48                 "{C-Media,CMI8738B},"
  49                 "{C-Media,CMI8338A},"
  50                 "{C-Media,CMI8338B}}");
  51
  52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  53 #define SUPPORT_JOYSTICK 1
  54 #endif
  55
  56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  59 static long mpu_port[SNDRV_CARDS];
  60 static long fm_port[SNDRV_CARDS];
  61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  62 #ifdef SUPPORT_JOYSTICK
  63 static int joystick_port[SNDRV_CARDS];
  64 #endif
  65 static int boot_devs;
  66
  67 module_param_array(index, int, boot_devs, 0444);
  68 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  69 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  70 module_param_array(id, charp, boot_devs, 0444);
  71 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  72 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  73 module_param_array(enable, bool, boot_devs, 0444);
  74 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  75 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  76 module_param_array(mpu_port, long, boot_devs, 0444);
  77 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  78 MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x320},{0x310},{0x300}},dialog:list");
  79 module_param_array(fm_port, long, boot_devs, 0444);
  80 MODULE_PARM_DESC(fm_port, "FM port.");
  81 MODULE_PARM_SYNTAX(fm_port, SNDRV_ENABLED ",allows:{{0},{0x388},{0x3c8},{0x3e0},{0x3e8}},dialog:list");
  82 module_param_array(soft_ac3, bool, boot_devs, 0444);
  83 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
  84 #ifdef SUPPORT_JOYSTICK
  85 module_param_array(joystick_port, int, boot_devs, 0444);
  86 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  87 MODULE_PARM_SYNTAX(joystick_port, SNDRV_ENABLED ",allows:{{0},{1},{0x200},{0x201}},dialog:list");
  88 #endif
  89
  90 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
  91 #define PCI_DEVICE_ID_CMEDIA_CM8738     0x0111
  92 #endif
  93 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
  94 #define PCI_DEVICE_ID_CMEDIA_CM8738B    0x0112
  95 #endif
  96
  97 /*
  98  * CM8x38 registers definition
  99  */
 100
 101 #define CM_REG_FUNCTRL0         0x00
 102 #define CM_RST_CH1              0x00080000
 103 #define CM_RST_CH0              0x00040000
 104 #define CM_CHEN1                0x00020000      /* ch1: enable */
 105 #define CM_CHEN0                0x00010000      /* ch0: enable */
 106 #define CM_PAUSE1               0x00000008      /* ch1: pause */
 107 #define CM_PAUSE0               0x00000004      /* ch0: pause */
 108 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
 109 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
 110
 111 #define CM_REG_FUNCTRL1         0x04
 112 #define CM_ASFC_MASK            0x0000E000      /* ADC sampling frequency */
 113 #define CM_ASFC_SHIFT           13
 114 #define CM_DSFC_MASK            0x00001C00      /* DAC sampling frequency */
 115 #define CM_DSFC_SHIFT           10
 116 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
 117 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
 118 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/OUT -> IN loopback */
 119 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
 120 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
 121 #define CM_BREQ                 0x00000010      /* bus master enabled */
 122 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
 123 #define CM_UART_EN              0x00000004      /* UART */
 124 #define CM_JYSTK_EN             0x00000002      /* joy stick */
 125
 126 #define CM_REG_CHFORMAT         0x08
 127
 128 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 129 #define CM_CHB3D                0x20000000      /* 4 channels */
 130
 131 #define CM_CHIP_MASK1           0x1f000000
 132 #define CM_CHIP_037             0x01000000
 133
 134 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 135 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 136 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 137 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 138
 139 #define CM_ADCBITLEN_MASK       0x0000C000
 140 #define CM_ADCBITLEN_16         0x00000000
 141 #define CM_ADCBITLEN_15         0x00004000
 142 #define CM_ADCBITLEN_14         0x00008000
 143 #define CM_ADCBITLEN_13         0x0000C000
 144
 145 #define CM_ADCDACLEN_MASK       0x00003000
 146 #define CM_ADCDACLEN_060        0x00000000
 147 #define CM_ADCDACLEN_066        0x00001000
 148 #define CM_ADCDACLEN_130        0x00002000
 149 #define CM_ADCDACLEN_280        0x00003000
 150
 151 #define CM_CH1_SRATE_176K       0x00000800
 152 #define CM_CH1_SRATE_88K        0x00000400
 153 #define CM_CH0_SRATE_176K       0x00000200
 154 #define CM_CH0_SRATE_88K        0x00000100
 155
 156 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 157
 158 #define CM_CH1FMT_MASK          0x0000000C
 159 #define CM_CH1FMT_SHIFT         2
 160 #define CM_CH0FMT_MASK          0x00000003
 161 #define CM_CH0FMT_SHIFT         0
 162
 163 #define CM_REG_INT_HLDCLR       0x0C
 164 #define CM_CHIP_MASK2           0xff000000
 165 #define CM_CHIP_039             0x04000000
 166 #define CM_CHIP_039_6CH         0x01000000
 167 #define CM_TDMA_INT_EN          0x00040000
 168 #define CM_CH1_INT_EN           0x00020000
 169 #define CM_CH0_INT_EN           0x00010000
 170 #define CM_INT_HOLD             0x00000002
 171 #define CM_INT_CLEAR            0x00000001
 172
 173 #define CM_REG_INT_STATUS       0x10
 174 #define CM_INTR                 0x80000000
 175 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 176 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 177 #define CM_UARTINT              0x00010000
 178 #define CM_LTDMAINT             0x00008000
 179 #define CM_HTDMAINT             0x00004000
 180 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 181 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 182 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 183 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 184 #define CM_CH1BUSY              0x00000008
 185 #define CM_CH0BUSY              0x00000004
 186 #define CM_CHINT1               0x00000002
 187 #define CM_CHINT0               0x00000001
 188
 189 #define CM_REG_LEGACY_CTRL      0x14
 190 #define CM_NXCHG                0x80000000      /* h/w multi channels? */
 191 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 192 #define CM_VMPU_330             0x00000000
 193 #define CM_VMPU_320             0x20000000
 194 #define CM_VMPU_310             0x40000000
 195 #define CM_VMPU_300             0x60000000
 196 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 197 #define CM_VSBSEL_220           0x00000000
 198 #define CM_VSBSEL_240           0x04000000
 199 #define CM_VSBSEL_260           0x08000000
 200 #define CM_VSBSEL_280           0x0C000000
 201 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 202 #define CM_FMSEL_388            0x00000000
 203 #define CM_FMSEL_3C8            0x01000000
 204 #define CM_FMSEL_3E0            0x02000000
 205 #define CM_FMSEL_3E8            0x03000000
 206 #define CM_ENSPDOUT             0x00800000      /* enable XPDIF/OUT to I/O interface */
 207 #define CM_SPDCOPYRHT           0x00400000      /* set copyright spdif in/out */
 208 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 209 #define CM_SETRETRY             0x00010000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 210 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 211 #define CM_LINE_AS_BASS         0x00006000      /* use line-in as bass */
 212
 213 #define CM_REG_MISC_CTRL        0x18
 214 #define CM_PWD                  0x80000000
 215 #define CM_RESET                0x40000000
 216 #define CM_SFIL_MASK            0x30000000
 217 #define CM_TXVX                 0x08000000
 218 #define CM_N4SPK3D              0x04000000      /* 4ch output */
 219 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 220 #define CM_SPDIF48K             0x01000000      /* write */
 221 #define CM_SPATUS48K            0x01000000      /* read */
 222 #define CM_ENDBDAC              0x00800000      /* enable dual dac */
 223 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 224 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 225 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-IN -> int. OUT */
 226 #define CM_FM_EN                0x00080000      /* enalbe FM */
 227 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 228 #define CM_VIDWPDSB             0x00010000
 229 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 230 #define CM_MASK_EN              0x00004000
 231 #define CM_VIDWPPRT             0x00002000
 232 #define CM_SFILENB              0x00001000
 233 #define CM_MMODE_MASK           0x00000E00
 234 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 235 #define CM_ENCENTER             0x00000080
 236 #define CM_FLINKON              0x00000040
 237 #define CM_FLINKOFF             0x00000020
 238 #define CM_MIDSMP               0x00000010
 239 #define CM_UPDDMA_MASK          0x0000000C
 240 #define CM_TWAIT_MASK           0x00000003
 241
 242         /* byte */
 243 #define CM_REG_MIXER0           0x20
 244
 245 #define CM_REG_SB16_DATA        0x22
 246 #define CM_REG_SB16_ADDR        0x23
 247
 248 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 249 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 250 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 251 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 252
 253 #define CM_REG_MIXER1           0x24
 254 #define CM_FMMUTE               0x80    /* mute FM */
 255 #define CM_FMMUTE_SHIFT         7
 256 #define CM_WSMUTE               0x40    /* mute PCM */
 257 #define CM_WSMUTE_SHIFT         6
 258 #define CM_SPK4                 0x20    /* lin-in -> rear line out */
 259 #define CM_SPK4_SHIFT           5
 260 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 261 #define CM_REAR2FRONT_SHIFT     4
 262 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 263 #define CM_WAVEINL_SHIFT        3
 264 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 265 #define CM_WAVEINR_SHIFT        2
 266 #define CM_X3DEN                0x02    /* 3D surround enable */
 267 #define CM_X3DEN_SHIFT          1
 268 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 269 #define CM_CDPLAY_SHIFT         0
 270
 271 #define CM_REG_MIXER2           0x25
 272 #define CM_RAUXREN              0x80    /* AUX right capture */
 273 #define CM_RAUXREN_SHIFT        7
 274 #define CM_RAUXLEN              0x40    /* AUX left capture */
 275 #define CM_RAUXLEN_SHIFT        6
 276 #define CM_VAUXRM               0x20    /* AUX right mute */
 277 #define CM_VAUXRM_SHIFT         5
 278 #define CM_VAUXLM               0x10    /* AUX left mute */
 279 #define CM_VAUXLM_SHIFT         4
 280 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 281 #define CM_VADMIC_SHIFT         1
 282 #define CM_MICGAINZ             0x01    /* mic boost */
 283 #define CM_MICGAINZ_SHIFT       0
 284
 285 #define CM_REG_AUX_VOL          0x26
 286 #define CM_VAUXL_MASK           0xf0
 287 #define CM_VAUXR_MASK           0x0f
 288
 289 #define CM_REG_MISC             0x27
 290 #define CM_XGPO1                0x20
 291 // #define CM_XGPBIO            0x04
 292 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 293 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 294 #define CM_SPDVALID             0x02    /* spdif input valid check */
 295 #define CM_DMAUTO               0x01
 296
 297 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 298 /*
 299  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 300  * or identical with AC97 codec?
 301  */
 302 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 303
 304 /*
 305  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 306  */
 307 #define CM_REG_MPU_PCI          0x40
 308
 309 /*
 310  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 311  */
 312 #define CM_REG_FM_PCI           0x50
 313
 314 /*
 315  * for CMI-8338 .. this is not valid for CMI-8738.
 316  */
 317 #define CM_REG_EXTENT_IND       0xf0
 318 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 319 #define CM_VPHONE_SHIFT         5
 320 #define CM_VPHOM                0x10    /* Phone mute control */
 321 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 322 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 323 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 324
 325 /*
 326  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 327  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 328  * unit (readonly?).
 329  */
 330 #define CM_REG_PLL              0xf8
 331
 332 /*
 333  * extended registers
 334  */
 335 #define CM_REG_CH0_FRAME1       0x80    /* base address */
 336 #define CM_REG_CH0_FRAME2       0x84
 337 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 338 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 339
 340 /*
 341  * size of i/o region
 342  */
 343 #define CM_EXTENT_CODEC   0x100
 344 #define CM_EXTENT_MIDI    0x2
 345 #define CM_EXTENT_SYNTH   0x4
 346
 347
 348 /*
 349  * pci ids
 350  */
 351 #ifndef PCI_VENDOR_ID_CMEDIA
 352 #define PCI_VENDOR_ID_CMEDIA         0x13F6
 353 #endif
 354 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
 355 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
 356 #endif
 357 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
 358 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
 359 #endif
 360 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
 361 #define PCI_DEVICE_ID_CMEDIA_CM8738  0x0111
 362 #endif
 363 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
 364 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
 365 #endif
 366
 367 /*
 368  * channels for playback / capture
 369  */
 370 #define CM_CH_PLAY      0
 371 #define CM_CH_CAPT      1
 372
 373 /*
 374  * flags to check device open/close
 375  */
 376 #define CM_OPEN_NONE    0
 377 #define CM_OPEN_CH_MASK 0x01
 378 #define CM_OPEN_DAC     0x10
 379 #define CM_OPEN_ADC     0x20
 380 #define CM_OPEN_SPDIF   0x40
 381 #define CM_OPEN_MCHAN   0x80
 382 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 383 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 384 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 385 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 386 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 387 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 388
 389
 390 #if CM_CH_PLAY == 1
 391 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 392 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 393 #define CM_CAPTURE_SPDF         CM_SPDF_0
 394 #else
 395 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 396 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 397 #define CM_CAPTURE_SPDF         CM_SPDF_1
 398 #endif
 399
 400
 401 /*
 402  * driver data
 403  */
 404
 405 typedef struct snd_stru_cmipci cmipci_t;
 406 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
 407
 408 #define chip_t cmipci_t
 409
 410 struct snd_stru_cmipci_pcm {
 411         snd_pcm_substream_t *substream;
 412         int running;            /* dac/adc running? */
 413         unsigned int dma_size;  /* in frames */
 414         unsigned int period_size;       /* in frames */
 415         unsigned int offset;    /* physical address of the buffer */
 416         unsigned int fmt;       /* format bits */
 417         int ch;                 /* channel (0/1) */
 418         unsigned int is_dac;            /* is dac? */
 419         int bytes_per_frame;
 420         int shift;
 421 };
 422
 423 /* mixer elements toggled/resumed during ac3 playback */
 424 struct cmipci_mixer_auto_switches {
 425         const char *name;       /* switch to toggle */
 426         int toggle_on;          /* value to change when ac3 mode */
 427 };
 428 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 429         {"PCM Playback Switch", 0},
 430         {"IEC958 Output Switch", 1},
 431         {"IEC958 Mix Analog", 0},
 432         // {"IEC958 Out To DAC", 1}, // no longer used
 433         {"IEC958 Loop", 0},
 434 };
 435 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 436
 437 struct snd_stru_cmipci {
 438         snd_card_t *card;
 439
 440         struct pci_dev *pci;
 441         unsigned int device;    /* device ID */
 442         int irq;
 443
 444         unsigned long iobase;
 445         struct resource *res_iobase;
 446         unsigned int ctrl;      /* FUNCTRL0 current value */
 447
 448         snd_pcm_t *pcm;         /* DAC/ADC PCM */
 449         snd_pcm_t *pcm2;        /* 2nd DAC */
 450         snd_pcm_t *pcm_spdif;   /* SPDIF */
 451
 452         int chip_version;
 453         int max_channels;
 454         unsigned int has_dual_dac: 1;
 455         unsigned int can_ac3_sw: 1;
 456         unsigned int can_ac3_hw: 1;
 457         unsigned int can_multi_ch: 1;
 458         unsigned int do_soft_ac3: 1;
 459
 460         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 461         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 462         int spdif_counter;      /* for software AC3 */
 463
 464         unsigned int dig_status;
 465         unsigned int dig_pcm_status;
 466
 467         snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
 468
 469         int opened[2];  /* open mode */
 470         struct semaphore open_mutex;
 471
 472         int mixer_insensitive: 1;
 473         snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
 474         int mixer_res_status[CM_SAVED_MIXERS];
 475
 476         opl3_t *opl3;
 477         snd_hwdep_t *opl3hwdep;
 478
 479         cmipci_pcm_t channel[2];        /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 480
 481         /* external MIDI */
 482         snd_rawmidi_t *rmidi;
 483
 484 #ifdef SUPPORT_JOYSTICK
 485         struct gameport gameport;
 486         struct resource *res_joystick;
 487 #endif
 488
 489         spinlock_t reg_lock;
 490 };
 491
 492
 493 /* read/write operations for dword register */
 494 inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
 495 {
 496         outl(data, cm->iobase + cmd);
 497 }
 498 inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
 499 {
 500         return inl(cm->iobase + cmd);
 501 }
 502
 503 /* read/write operations for word register */
 504 inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
 505 {
 506         outw(data, cm->iobase + cmd);
 507 }
 508 inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
 509 {
 510         return inw(cm->iobase + cmd);
 511 }
 512
 513 /* read/write operations for byte register */
 514 inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
 515 {
 516         outb(data, cm->iobase + cmd);
 517 }
 518
 519 inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
 520 {
 521         return inb(cm->iobase + cmd);
 522 }
 523
 524 /* bit operations for dword register */
 525 static void snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
 526 {
 527         unsigned int val;
 528         val = inl(cm->iobase + cmd);
 529         val |= flag;
 530         outl(val, cm->iobase + cmd);
 531 }
 532
 533 static void snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
 534 {
 535         unsigned int val;
 536         val = inl(cm->iobase + cmd);
 537         val &= ~flag;
 538         outl(val, cm->iobase + cmd);
 539 }
 540
 541 #if 0 // not used
 542 /* bit operations for byte register */
 543 static void snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
 544 {
 545         unsigned char val;
 546         val = inb(cm->iobase + cmd);
 547         val |= flag;
 548         outb(val, cm->iobase + cmd);
 549 }
 550
 551 static void snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
 552 {
 553         unsigned char val;
 554         val = inb(cm->iobase + cmd);
 555         val &= ~flag;
 556         outb(val, cm->iobase + cmd);
 557 }
 558 #endif
 559
 560
 561 /*
 562  * PCM interface
 563  */
 564
 565 /*
 566  * calculate frequency
 567  */
 568
 569 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 570
 571 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 572 {
 573         unsigned int i;
 574         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 575                 if (rates[i] == rate)
 576                         return i;
 577         }
 578         snd_BUG();
 579         return 0;
 580 }
 581
 582 #ifdef USE_VAR48KRATE
 583 /*
 584  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 585  * does it this way .. maybe not.  Never get any information from C-Media about
 586  * that <werner@suse.de>.
 587  */
 588 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 589 {
 590         unsigned int delta, tolerance;
 591         int xm, xn, xr;
 592
 593         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 594                 rate <<= 1;
 595         *n = -1;
 596         if (*r > 0xff)
 597                 goto out;
 598         tolerance = rate*CM_TOLERANCE_RATE;
 599
 600         for (xn = (1+2); xn < (0x1f+2); xn++) {
 601                 for (xm = (1+2); xm < (0xff+2); xm++) {
 602                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 603
 604                         if (xr < rate)
 605                                 delta = rate - xr;
 606                         else
 607                                 delta = xr - rate;
 608
 609                         /*
 610                          * If we found one, remember this,
 611                          * and try to find a closer one
 612                          */
 613                         if (delta < tolerance) {
 614                                 tolerance = delta;
 615                                 *m = xm - 2;
 616                                 *n = xn - 2;
 617                         }
 618                 }
 619         }
 620 out:
 621         return (*n > -1);
 622 }
 623
 624 /*
 625  * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
 626  * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
 627  * at the register CM_REG_FUNCTRL1 (0x04).
 628  * Problem: other ways are also possible (any information about that?)
 629  */
 630 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
 631 {
 632         unsigned int reg = CM_REG_PLL + slot;
 633         /*
 634          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 635          * for DSFC/ASFC (000 upto 111).
 636          */
 637
 638         /* FIXME: Init (Do we've to set an other register first before programming?) */
 639
 640         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 641         snd_cmipci_write_b(cm, reg, rate>>8);
 642         snd_cmipci_write_b(cm, reg, rate&0xff);
 643
 644         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 645 }
 646 #endif /* USE_VAR48KRATE */
 647
 648 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
 649                                 snd_pcm_hw_params_t * hw_params)
 650 {
 651         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 652 }
 653
 654 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
 655                                           snd_pcm_hw_params_t * hw_params)
 656 {
 657         cmipci_t *cm = snd_pcm_substream_chip(substream);
 658         if (params_channels(hw_params) > 2) {
 659                 down(&cm->open_mutex);
 660                 if (cm->opened[CM_CH_PLAY]) {
 661                         up(&cm->open_mutex);
 662                         return -EBUSY;
 663                 }
 664                 /* reserve the channel A */
 665                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 666                 up(&cm->open_mutex);
 667         }
 668         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 669 }
 670
 671 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
 672 {
 673         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 674         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 675         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 676         udelay(10);
 677 }
 678
 679 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
 680 {
 681         return snd_pcm_lib_free_pages(substream);
 682 }
 683
 684
 685 /*
 686  */
 687
 688 static unsigned int hw_channels[] = {1, 2, 4, 5, 6};
 689 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
 690         .count = 3,
 691         .list = hw_channels,
 692         .mask = 0,
 693 };
 694 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
 695         .count = 5,
 696         .list = hw_channels,
 697         .mask = 0,
 698 };
 699
 700 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
 701 {
 702         unsigned long flags;
 703
 704         if (channels > 2) {
 705                 if (! cm->can_multi_ch)
 706                         return -EINVAL;
 707                 if (rec->fmt != 0x03) /* stereo 16bit only */
 708                         return -EINVAL;
 709
 710                 spin_lock_irqsave(&cm->reg_lock, flags);
 711                 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 712                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 713                 if (channels > 4) {
 714                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 715                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 716                 } else {
 717                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 718                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 719                 }
 720                 if (channels == 6) {
 721                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 722                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 723                 } else {
 724                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 725                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 726                 }
 727                 spin_unlock_irqrestore(&cm->reg_lock, flags);
 728
 729         } else {
 730                 if (cm->can_multi_ch) {
 731                         spin_lock_irqsave(&cm->reg_lock, flags);
 732                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 733                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 734                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 735                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 736                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
 737                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 738                         spin_unlock_irqrestore(&cm->reg_lock, flags);
 739                 }
 740         }
 741         return 0;
 742 }
 743
 744
 745 /*
 746  * prepare playback/capture channel
 747  * channel to be used must have been set in rec->ch.
 748  */
 749 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
 750                                  snd_pcm_substream_t *substream)
 751 {
 752         unsigned long flags;
 753         unsigned int reg, freq, val;
 754         snd_pcm_runtime_t *runtime = substream->runtime;
 755
 756         rec->fmt = 0;
 757         rec->shift = 0;
 758         if (snd_pcm_format_width(runtime->format) >= 16) {
 759                 rec->fmt |= 0x02;
 760                 if (snd_pcm_format_width(runtime->format) > 16)
 761                         rec->shift++; /* 24/32bit */
 762         }
 763         if (runtime->channels > 1)
 764                 rec->fmt |= 0x01;
 765         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 766                 snd_printd("cannot set dac channels\n");
 767                 return -EINVAL;
 768         }
 769
 770         rec->offset = runtime->dma_addr;
 771         /* buffer and period sizes in frame */
 772         rec->dma_size = runtime->buffer_size << rec->shift;
 773         rec->period_size = runtime->period_size << rec->shift;
 774         if (runtime->channels > 2) {
 775                 /* multi-channels */
 776                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 777                 rec->period_size = (rec->period_size * runtime->channels) / 2;
 778         }
 779
 780         spin_lock_irqsave(&cm->reg_lock, flags);
 781
 782         /* set buffer address */
 783         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 784         snd_cmipci_write(cm, reg, rec->offset);
 785         /* program sample counts */
 786         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 787         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 788         snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
 789
 790         /* set adc/dac flag */
 791         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 792         if (rec->is_dac)
 793                 cm->ctrl &= ~val;
 794         else
 795                 cm->ctrl |= val;
 796         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 797         //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
 798
 799         /* set sample rate */
 800         freq = snd_cmipci_rate_freq(runtime->rate);
 801         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 802         if (rec->ch) {
 803                 val &= ~CM_ASFC_MASK;
 804                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 805         } else {
 806                 val &= ~CM_DSFC_MASK;
 807                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 808         }
 809         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 810         //snd_printd("cmipci: functrl1 = %08x\n", val);
 811
 812         /* set format */
 813         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 814         if (rec->ch) {
 815                 val &= ~CM_CH1FMT_MASK;
 816                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 817         } else {
 818                 val &= ~CM_CH0FMT_MASK;
 819                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 820         }
 821         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 822         //snd_printd("cmipci: chformat = %08x\n", val);
 823
 824         rec->running = 0;
 825         spin_unlock_irqrestore(&cm->reg_lock, flags);
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * PCM trigger/stop
 832  */
 833 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
 834                                  snd_pcm_substream_t *substream, int cmd)
 835 {
 836         unsigned int inthld, chen, reset, pause;
 837         int result = 0;
 838
 839         inthld = CM_CH0_INT_EN << rec->ch;
 840         chen = CM_CHEN0 << rec->ch;
 841         reset = CM_RST_CH0 << rec->ch;
 842         pause = CM_PAUSE0 << rec->ch;
 843
 844         spin_lock(&cm->reg_lock);
 845         switch (cmd) {
 846         case SNDRV_PCM_TRIGGER_START:
 847                 rec->running = 1;
 848                 /* set interrupt */
 849                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 850                 cm->ctrl |= chen;
 851                 /* enable channel */
 852                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 853                 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
 854                 break;
 855         case SNDRV_PCM_TRIGGER_STOP:
 856                 rec->running = 0;
 857                 /* disable interrupt */
 858                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 859                 /* reset */
 860                 cm->ctrl &= ~chen;
 861                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 862                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 863                 break;
 864         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 865                 cm->ctrl |= pause;
 866                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 867                 break;
 868         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 869                 cm->ctrl &= ~pause;
 870                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 871                 break;
 872         default:
 873                 result = -EINVAL;
 874                 break;
 875         }
 876         spin_unlock(&cm->reg_lock);
 877         return result;
 878 }
 879
 880 /*
 881  * return the current pointer
 882  */
 883 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
 884                                           snd_pcm_substream_t *substream)
 885 {
 886         size_t ptr;
 887         unsigned int reg;
 888         if (!rec->running)
 889                 return 0;
 890 #if 1 // this seems better..
 891         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 892         ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
 893         ptr >>= rec->shift;
 894 #else
 895         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 896         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 897         ptr = bytes_to_frames(substream->runtime, ptr);
 898 #endif
 899         if (substream->runtime->channels > 2)
 900                 ptr = (ptr * 2) / substream->runtime->channels;
 901         return ptr;
 902 }
 903
 904 /*
 905  * playback
 906  */
 907
 908 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
 909                                        int cmd)
 910 {
 911         cmipci_t *cm = snd_pcm_substream_chip(substream);
 912         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
 913 }
 914
 915 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
 916 {
 917         cmipci_t *cm = snd_pcm_substream_chip(substream);
 918         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 919 }
 920
 921
 922
 923 /*
 924  * capture
 925  */
 926
 927 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
 928                                      int cmd)
 929 {
 930         cmipci_t *cm = snd_pcm_substream_chip(substream);
 931         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
 932 }
 933
 934 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
 935 {
 936         cmipci_t *cm = snd_pcm_substream_chip(substream);
 937         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 938 }
 939
 940
 941 /*
 942  * hw preparation for spdif
 943  */
 944
 945 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
 946                                          snd_ctl_elem_info_t *uinfo)
 947 {
 948         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 949         uinfo->count = 1;
 950         return 0;
 951 }
 952
 953 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
 954                                         snd_ctl_elem_value_t *ucontrol)
 955 {
 956         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
 957         unsigned long flags;
 958         int i;
 959
 960         spin_lock_irqsave(&chip->reg_lock, flags);
 961         for (i = 0; i < 4; i++)
 962                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
 963         spin_unlock_irqrestore(&chip->reg_lock, flags);
 964         return 0;
 965 }
 966
 967 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
 968                                          snd_ctl_elem_value_t * ucontrol)
 969 {
 970         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
 971         unsigned long flags;
 972         int i, change;
 973         unsigned int val;
 974
 975         val = 0;
 976         spin_lock_irqsave(&chip->reg_lock, flags);
 977         for (i = 0; i < 4; i++)
 978                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
 979         change = val != chip->dig_status;
 980         chip->dig_status = val;
 981         spin_unlock_irqrestore(&chip->reg_lock, flags);
 982         return change;
 983 }
 984
 985 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
 986 {
 987         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
 988         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
 989         .info =         snd_cmipci_spdif_default_info,
 990         .get =          snd_cmipci_spdif_default_get,
 991         .put =          snd_cmipci_spdif_default_put
 992 };
 993
 994 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
 995                                       snd_ctl_elem_info_t *uinfo)
 996 {
 997         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 998         uinfo->count = 1;
 999         return 0;
1000 }
1001
1002 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
1003                                      snd_ctl_elem_value_t *ucontrol)
1004 {
1005         ucontrol->value.iec958.status[0] = 0xff;
1006         ucontrol->value.iec958.status[1] = 0xff;
1007         ucontrol->value.iec958.status[2] = 0xff;
1008         ucontrol->value.iec958.status[3] = 0xff;
1009         return 0;
1010 }
1011
1012 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
1013 {
1014         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1015         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1016         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1017         .info =         snd_cmipci_spdif_mask_info,
1018         .get =          snd_cmipci_spdif_mask_get,
1019 };
1020
1021 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1022                                         snd_ctl_elem_info_t *uinfo)
1023 {
1024         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1025         uinfo->count = 1;
1026         return 0;
1027 }
1028
1029 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1030                                        snd_ctl_elem_value_t *ucontrol)
1031 {
1032         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1033         unsigned long flags;
1034         int i;
1035
1036         spin_lock_irqsave(&chip->reg_lock, flags);
1037         for (i = 0; i < 4; i++)
1038                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1039         spin_unlock_irqrestore(&chip->reg_lock, flags);
1040         return 0;
1041 }
1042
1043 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1044                                        snd_ctl_elem_value_t *ucontrol)
1045 {
1046         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1047         unsigned long flags;
1048         int i, change;
1049         unsigned int val;
1050
1051         val = 0;
1052         spin_lock_irqsave(&chip->reg_lock, flags);
1053         for (i = 0; i < 4; i++)
1054                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1055         change = val != chip->dig_pcm_status;
1056         chip->dig_pcm_status = val;
1057         spin_unlock_irqrestore(&chip->reg_lock, flags);
1058         return change;
1059 }
1060
1061 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1062 {
1063         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1064         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1065         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1066         .info =         snd_cmipci_spdif_stream_info,
1067         .get =          snd_cmipci_spdif_stream_get,
1068         .put =          snd_cmipci_spdif_stream_put
1069 };
1070
1071 /*
1072  */
1073
1074 /* save mixer setting and mute for AC3 playback */
1075 static void save_mixer_state(cmipci_t *cm)
1076 {
1077         if (! cm->mixer_insensitive) {
1078                 unsigned int i;
1079                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1080                         snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1081                         if (ctl) {
1082                                 snd_ctl_elem_value_t val;
1083                                 int event;
1084                                 memset(&val, 0, sizeof(val));
1085                                 ctl->get(ctl, &val);
1086                                 cm->mixer_res_status[i] = val.value.integer.value[0];
1087                                 val.value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1088                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1089                                 if (cm->mixer_res_status[i] != val.value.integer.value[0]) {
1090                                         ctl->put(ctl, &val); /* toggle */
1091                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1092                                 }
1093                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1094                                 snd_ctl_notify(cm->card, event, &ctl->id);
1095                         }
1096                 }
1097                 cm->mixer_insensitive = 1;
1098         }
1099 }
1100
1101
1102 /* restore the previously saved mixer status */
1103 static void restore_mixer_state(cmipci_t *cm)
1104 {
1105         if (cm->mixer_insensitive) {
1106                 unsigned int i;
1107                 cm->mixer_insensitive = 0; /* at first clear this;
1108                                               otherwise the changes will be ignored */
1109                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1110                         snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1111                         if (ctl) {
1112                                 snd_ctl_elem_value_t val;
1113                                 int event;
1114
1115                                 memset(&val, 0, sizeof(val));
1116                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1117                                 ctl->get(ctl, &val);
1118                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1119                                 if (val.value.integer.value[0] != cm->mixer_res_status[i]) {
1120                                         val.value.integer.value[0] = cm->mixer_res_status[i];
1121                                         ctl->put(ctl, &val);
1122                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1123                                 }
1124                                 snd_ctl_notify(cm->card, event, &ctl->id);
1125                         }
1126                 }
1127         }
1128 }
1129
1130 /* spinlock held! */
1131 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1132 {
1133         if (do_ac3) {
1134                 /* AC3EN for 037 */
1135                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1136                 /* AC3EN for 039 */
1137                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1138
1139                 if (cm->can_ac3_hw) {
1140                         /* SPD24SEL for 037, 0x02 */
1141                         /* SPD24SEL for 039, 0x20, but cannot be set */
1142                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1143                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1144                 } else { /* can_ac3_sw */
1145                         /* SPD32SEL for 037 & 039, 0x20 */
1146                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1147                         /* set 176K sample rate to fix 033 HW bug */
1148                         if (cm->chip_version == 33) {
1149                                 if (rate >= 48000) {
1150                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1151                                 } else {
1152                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1153                                 }
1154                         }
1155                 }
1156
1157         } else {
1158                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1159                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1160
1161                 if (cm->can_ac3_hw) {
1162                         /* chip model >= 37 */
1163                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1164                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1165                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1166                         } else {
1167                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1168                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1169                         }
1170                 } else {
1171                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1172                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1173                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1174                 }
1175         }
1176 }
1177
1178 static void setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1179 {
1180         int rate;
1181         unsigned long flags;
1182
1183         rate = subs->runtime->rate;
1184
1185         if (up && do_ac3)
1186                 save_mixer_state(cm);
1187
1188         spin_lock_irqsave(&cm->reg_lock, flags);
1189         cm->spdif_playback_avail = up;
1190         if (up) {
1191                 /* they are controlled via "IEC958 Output Switch" */
1192                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1193                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1194                 if (cm->spdif_playback_enabled)
1195                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1196                 setup_ac3(cm, subs, do_ac3, rate);
1197
1198                 if (rate == 48000)
1199                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1200                 else
1201                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1202
1203         } else {
1204                 /* they are controlled via "IEC958 Output Switch" */
1205                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1206                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1207                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1208                 setup_ac3(cm, subs, 0, 0);
1209         }
1210         spin_unlock_irqrestore(&cm->reg_lock, flags);
1211 }
1212
1213
1214 /*
1215  * preparation
1216  */
1217
1218 /* playback - enable spdif only on the certain condition */
1219 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1220 {
1221         cmipci_t *cm = snd_pcm_substream_chip(substream);
1222         int rate = substream->runtime->rate;
1223         int do_spdif, do_ac3 = 0;
1224         do_spdif = ((rate == 44100 || rate == 48000) &&
1225                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1226                     substream->runtime->channels == 2);
1227         if (do_spdif && cm->can_ac3_hw)
1228                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1229         setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1230         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1231 }
1232
1233 /* playback  (via device #2) - enable spdif always */
1234 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1235 {
1236         cmipci_t *cm = snd_pcm_substream_chip(substream);
1237         int do_ac3;
1238         if (cm->can_ac3_hw)
1239                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1240         else
1241                 do_ac3 = 1; /* doesn't matter */
1242         setup_spdif_playback(cm, substream, 1, do_ac3);
1243         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1244 }
1245
1246 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1247 {
1248         cmipci_t *cm = snd_pcm_substream_chip(substream);
1249         setup_spdif_playback(cm, substream, 0, 0);
1250         restore_mixer_state(cm);
1251         return snd_cmipci_hw_free(substream);
1252 }
1253
1254 /* capture */
1255 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1256 {
1257         cmipci_t *cm = snd_pcm_substream_chip(substream);
1258         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1259 }
1260
1261 /* capture with spdif (via device #2) */
1262 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1263 {
1264         cmipci_t *cm = snd_pcm_substream_chip(substream);
1265         unsigned long flags;
1266
1267         spin_lock_irqsave(&cm->reg_lock, flags);
1268         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1269         spin_unlock_irqrestore(&cm->reg_lock, flags);
1270
1271         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1272 }
1273
1274 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1275 {
1276         cmipci_t *cm = snd_pcm_substream_chip(subs);
1277         unsigned long flags;
1278
1279         spin_lock_irqsave(&cm->reg_lock, flags);
1280         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1281         spin_unlock_irqrestore(&cm->reg_lock, flags);
1282
1283         return snd_cmipci_hw_free(subs);
1284 }
1285
1286
1287 /*
1288  * interrupt handler
1289  */
1290 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1291 {
1292         cmipci_t *cm = snd_magic_cast(cmipci_t, dev_id, return IRQ_NONE);
1293         unsigned int status, mask = 0;
1294
1295         /* fastpath out, to ease interrupt sharing */
1296         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1297         if (!(status & CM_INTR))
1298                 return IRQ_NONE;
1299
1300         /* acknowledge interrupt */
1301         spin_lock(&cm->reg_lock);
1302         if (status & CM_CHINT0)
1303                 mask |= CM_CH0_INT_EN;
1304         if (status & CM_CHINT1)
1305                 mask |= CM_CH1_INT_EN;
1306         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1307         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1308         spin_unlock(&cm->reg_lock);
1309
1310         if (cm->rmidi && (status & CM_UARTINT))
1311                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1312
1313         if (cm->pcm) {
1314                 if ((status & CM_CHINT0) && cm->channel[0].running)
1315                         snd_pcm_period_elapsed(cm->channel[0].substream);
1316                 if ((status & CM_CHINT1) && cm->channel[1].running)
1317                         snd_pcm_period_elapsed(cm->channel[1].substream);
1318         }
1319         return IRQ_HANDLED;
1320 }
1321
1322 /*
1323  * h/w infos
1324  */
1325
1326 /* playback on channel A */
1327 static snd_pcm_hardware_t snd_cmipci_playback =
1328 {
1329         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1330                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1331                                  SNDRV_PCM_INFO_MMAP_VALID),
1332         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1333         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1334         .rate_min =             5512,
1335         .rate_max =             48000,
1336         .channels_min =         1,
1337         .channels_max =         2,
1338         .buffer_bytes_max =     (128*1024),
1339         .period_bytes_min =     64,
1340         .period_bytes_max =     (128*1024),
1341         .periods_min =          2,
1342         .periods_max =          1024,
1343         .fifo_size =            0,
1344 };
1345
1346 /* capture on channel B */
1347 static snd_pcm_hardware_t snd_cmipci_capture =
1348 {
1349         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1350                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1351                                  SNDRV_PCM_INFO_MMAP_VALID),
1352         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1353         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1354         .rate_min =             5512,
1355         .rate_max =             48000,
1356         .channels_min =         1,
1357         .channels_max =         2,
1358         .buffer_bytes_max =     (128*1024),
1359         .period_bytes_min =     64,
1360         .period_bytes_max =     (128*1024),
1361         .periods_min =          2,
1362         .periods_max =          1024,
1363         .fifo_size =            0,
1364 };
1365
1366 /* playback on channel B - stereo 16bit only? */
1367 static snd_pcm_hardware_t snd_cmipci_playback2 =
1368 {
1369         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1370                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1371                                  SNDRV_PCM_INFO_MMAP_VALID),
1372         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1373         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1374         .rate_min =             5512,
1375         .rate_max =             48000,
1376         .channels_min =         2,
1377         .channels_max =         2,
1378         .buffer_bytes_max =     (128*1024),
1379         .period_bytes_min =     64,
1380         .period_bytes_max =     (128*1024),
1381         .periods_min =          2,
1382         .periods_max =          1024,
1383         .fifo_size =            0,
1384 };
1385
1386 /* spdif playback on channel A */
1387 static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1388 {
1389         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1390                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1391                                  SNDRV_PCM_INFO_MMAP_VALID),
1392         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1393         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1394         .rate_min =             44100,
1395         .rate_max =             48000,
1396         .channels_min =         2,
1397         .channels_max =         2,
1398         .buffer_bytes_max =     (128*1024),
1399         .period_bytes_min =     64,
1400         .period_bytes_max =     (128*1024),
1401         .periods_min =          2,
1402         .periods_max =          1024,
1403         .fifo_size =            0,
1404 };
1405
1406 /* spdif playback on channel A (32bit, IEC958 subframes) */
1407 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1408 {
1409         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1410                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1411                                  SNDRV_PCM_INFO_MMAP_VALID),
1412         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1413         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1414         .rate_min =             44100,
1415         .rate_max =             48000,
1416         .channels_min =         2,
1417         .channels_max =         2,
1418         .buffer_bytes_max =     (128*1024),
1419         .period_bytes_min =     64,
1420         .period_bytes_max =     (128*1024),
1421         .periods_min =          2,
1422         .periods_max =          1024,
1423         .fifo_size =            0,
1424 };
1425
1426 /* spdif capture on channel B */
1427 static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1428 {
1429         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1430                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1431                                  SNDRV_PCM_INFO_MMAP_VALID),
1432         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1433         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1434         .rate_min =             44100,
1435         .rate_max =             48000,
1436         .channels_min =         2,
1437         .channels_max =         2,
1438         .buffer_bytes_max =     (128*1024),
1439         .period_bytes_min =     64,
1440         .period_bytes_max =     (128*1024),
1441         .periods_min =          2,
1442         .periods_max =          1024,
1443         .fifo_size =            0,
1444 };
1445
1446 /*
1447  * check device open/close
1448  */
1449 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1450 {
1451         unsigned long flags;
1452         int ch = mode & CM_OPEN_CH_MASK;
1453
1454         /* FIXME: a file should wait until the device becomes free
1455          * when it's opened on blocking mode.  however, since the current
1456          * pcm framework doesn't pass file pointer before actually opened,
1457          * we can't know whether blocking mode or not in open callback..
1458          */
1459         down(&cm->open_mutex);
1460         if (cm->opened[ch]) {
1461                 up(&cm->open_mutex);
1462                 return -EBUSY;
1463         }
1464         cm->opened[ch] = mode;
1465         cm->channel[ch].substream = subs;
1466         if (! (mode & CM_OPEN_DAC)) {
1467                 /* disable dual DAC mode */
1468                 cm->channel[ch].is_dac = 0;
1469                 spin_lock_irqsave(&cm->reg_lock, flags);
1470                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1471                 spin_unlock_irqrestore(&cm->reg_lock, flags);
1472         }
1473         up(&cm->open_mutex);
1474         return 0;
1475 }
1476
1477 static void close_device_check(cmipci_t *cm, int mode)
1478 {
1479         unsigned long flags;
1480         int ch = mode & CM_OPEN_CH_MASK;
1481
1482         down(&cm->open_mutex);
1483         if (cm->opened[ch] == mode) {
1484                 if (cm->channel[ch].substream) {
1485                         snd_cmipci_ch_reset(cm, ch);
1486                         cm->channel[ch].running = 0;
1487                         cm->channel[ch].substream = NULL;
1488                 }
1489                 cm->opened[ch] = 0;
1490                 if (! cm->channel[ch].is_dac) {
1491                         /* enable dual DAC mode again */
1492                         cm->channel[ch].is_dac = 1;
1493                         spin_lock_irqsave(&cm->reg_lock, flags);
1494                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1495                         spin_unlock_irqrestore(&cm->reg_lock, flags);
1496                 }
1497         }
1498         up(&cm->open_mutex);
1499 }
1500
1501 /*
1502  */
1503
1504 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1505 {
1506         cmipci_t *cm = snd_pcm_substream_chip(substream);
1507         snd_pcm_runtime_t *runtime = substream->runtime;
1508         int err;
1509
1510         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1511                 return err;
1512         runtime->hw = snd_cmipci_playback;
1513         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1514         cm->dig_pcm_status = cm->dig_status;
1515         return 0;
1516 }
1517
1518 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1519 {
1520         cmipci_t *cm = snd_pcm_substream_chip(substream);
1521         snd_pcm_runtime_t *runtime = substream->runtime;
1522         int err;
1523
1524         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1525                 return err;
1526         runtime->hw = snd_cmipci_capture;
1527         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1528         return 0;
1529 }
1530
1531 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1532 {
1533         cmipci_t *cm = snd_pcm_substream_chip(substream);
1534         snd_pcm_runtime_t *runtime = substream->runtime;
1535         int err;
1536
1537         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1538                 return err;
1539         runtime->hw = snd_cmipci_playback2;
1540         down(&cm->open_mutex);
1541         if (! cm->opened[CM_CH_PLAY]) {
1542                 if (cm->can_multi_ch) {
1543                         runtime->hw.channels_max = cm->max_channels;
1544                         if (cm->max_channels == 4)
1545                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1546                         else
1547                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1548                 }
1549                 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1550         }
1551         up(&cm->open_mutex);
1552         return 0;
1553 }
1554
1555 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1556 {
1557         cmipci_t *cm = snd_pcm_substream_chip(substream);
1558         snd_pcm_runtime_t *runtime = substream->runtime;
1559         int err;
1560
1561         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1562                 return err;
1563         if (cm->can_ac3_hw) {
1564                 runtime->hw = snd_cmipci_playback_spdif;
1565                 if (cm->chip_version >= 37)
1566                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1567         } else {
1568                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1569         }
1570         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1571         cm->dig_pcm_status = cm->dig_status;
1572         return 0;
1573 }
1574
1575 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1576 {
1577         cmipci_t *cm = snd_pcm_substream_chip(substream);
1578         snd_pcm_runtime_t *runtime = substream->runtime;
1579         int err;
1580
1581         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1582                 return err;
1583         runtime->hw = snd_cmipci_capture_spdif;
1584         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1585         return 0;
1586 }
1587
1588
1589 /*
1590  */
1591
1592 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1593 {
1594         cmipci_t *cm = snd_pcm_substream_chip(substream);
1595         close_device_check(cm, CM_OPEN_PLAYBACK);
1596         return 0;
1597 }
1598
1599 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1600 {
1601         cmipci_t *cm = snd_pcm_substream_chip(substream);
1602         close_device_check(cm, CM_OPEN_CAPTURE);
1603         return 0;
1604 }
1605
1606 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1607 {
1608         cmipci_t *cm = snd_pcm_substream_chip(substream);
1609         close_device_check(cm, CM_OPEN_PLAYBACK2);
1610         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1611         return 0;
1612 }
1613
1614 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1615 {
1616         cmipci_t *cm = snd_pcm_substream_chip(substream);
1617         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1618         return 0;
1619 }
1620
1621 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1622 {
1623         cmipci_t *cm = snd_pcm_substream_chip(substream);
1624         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1625         return 0;
1626 }
1627
1628
1629 /*
1630  */
1631
1632 static snd_pcm_ops_t snd_cmipci_playback_ops = {
1633         .open =         snd_cmipci_playback_open,
1634         .close =        snd_cmipci_playback_close,
1635         .ioctl =        snd_pcm_lib_ioctl,
1636         .hw_params =    snd_cmipci_hw_params,
1637         .hw_free =      snd_cmipci_playback_hw_free,
1638         .prepare =      snd_cmipci_playback_prepare,
1639         .trigger =      snd_cmipci_playback_trigger,
1640         .pointer =      snd_cmipci_playback_pointer,
1641 };
1642
1643 static snd_pcm_ops_t snd_cmipci_capture_ops = {
1644         .open =         snd_cmipci_capture_open,
1645         .close =        snd_cmipci_capture_close,
1646         .ioctl =        snd_pcm_lib_ioctl,
1647         .hw_params =    snd_cmipci_hw_params,
1648         .hw_free =      snd_cmipci_hw_free,
1649         .prepare =      snd_cmipci_capture_prepare,
1650         .trigger =      snd_cmipci_capture_trigger,
1651         .pointer =      snd_cmipci_capture_pointer,
1652 };
1653
1654 static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1655         .open =         snd_cmipci_playback2_open,
1656         .close =        snd_cmipci_playback2_close,
1657         .ioctl =        snd_pcm_lib_ioctl,
1658         .hw_params =    snd_cmipci_playback2_hw_params,
1659         .hw_free =      snd_cmipci_hw_free,
1660         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1661         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1662         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1663 };
1664
1665 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1666         .open =         snd_cmipci_playback_spdif_open,
1667         .close =        snd_cmipci_playback_spdif_close,
1668         .ioctl =        snd_pcm_lib_ioctl,
1669         .hw_params =    snd_cmipci_hw_params,
1670         .hw_free =      snd_cmipci_playback_hw_free,
1671         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1672         .trigger =      snd_cmipci_playback_trigger,
1673         .pointer =      snd_cmipci_playback_pointer,
1674 };
1675
1676 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1677         .open =         snd_cmipci_capture_spdif_open,
1678         .close =        snd_cmipci_capture_spdif_close,
1679         .ioctl =        snd_pcm_lib_ioctl,
1680         .hw_params =    snd_cmipci_hw_params,
1681         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1682         .prepare =      snd_cmipci_capture_spdif_prepare,
1683         .trigger =      snd_cmipci_capture_trigger,
1684         .pointer =      snd_cmipci_capture_pointer,
1685 };
1686
1687
1688 /*
1689  */
1690
1691 static void snd_cmipci_pcm_free(snd_pcm_t *pcm)
1692 {
1693         snd_pcm_lib_preallocate_free_for_all(pcm);
1694 }
1695
1696 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1697 {
1698         snd_pcm_t *pcm;
1699         int err;
1700
1701         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1702         if (err < 0)
1703                 return err;
1704
1705         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1706         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1707
1708         pcm->private_data = cm;
1709         pcm->private_free = snd_cmipci_pcm_free;
1710         pcm->info_flags = 0;
1711         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1712         cm->pcm = pcm;
1713
1714         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1715                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1716
1717         return 0;
1718 }
1719
1720 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1721 {
1722         snd_pcm_t *pcm;
1723         int err;
1724
1725         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1726         if (err < 0)
1727                 return err;
1728
1729         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1730
1731         pcm->private_data = cm;
1732         pcm->private_free = snd_cmipci_pcm_free;
1733         pcm->info_flags = 0;
1734         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1735         cm->pcm2 = pcm;
1736
1737         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1738                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1739
1740         return 0;
1741 }
1742
1743 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1744 {
1745         snd_pcm_t *pcm;
1746         int err;
1747
1748         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1749         if (err < 0)
1750                 return err;
1751
1752         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1753         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1754
1755         pcm->private_data = cm;
1756         pcm->private_free = snd_cmipci_pcm_free;
1757         pcm->info_flags = 0;
1758         strcpy(pcm->name, "C-Media PCI IEC958");
1759         cm->pcm_spdif = pcm;
1760
1761         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1762                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1763
1764         return 0;
1765 }
1766
1767 /*
1768  * mixer interface:
1769  * - CM8338/8738 has a compatible mixer interface with SB16, but
1770  *   lack of some elements like tone control, i/o gain and AGC.
1771  * - Access to native registers:
1772  *   - A 3D switch
1773  *   - Output mute switches
1774  */
1775
1776 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1777 {
1778         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1779         outb(data, s->iobase + CM_REG_SB16_DATA);
1780 }
1781
1782 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1783 {
1784         unsigned char v;
1785
1786         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1787         v = inb(s->iobase + CM_REG_SB16_DATA);
1788         return v;
1789 }
1790
1791 /*
1792  * general mixer element
1793  */
1794 typedef struct cmipci_sb_reg {
1795         unsigned int left_reg, right_reg;
1796         unsigned int left_shift, right_shift;
1797         unsigned int mask;
1798         unsigned int invert: 1;
1799         unsigned int stereo: 1;
1800 } cmipci_sb_reg_t;
1801
1802 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1803  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1804
1805 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1806 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1807   .info = snd_cmipci_info_volume, \
1808   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1809   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1810 }
1811
1812 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1813 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1814 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1815 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1816
1817 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1818 {
1819         r->left_reg = val & 0xff;
1820         r->right_reg = (val >> 8) & 0xff;
1821         r->left_shift = (val >> 16) & 0x07;
1822         r->right_shift = (val >> 19) & 0x07;
1823         r->invert = (val >> 22) & 1;
1824         r->stereo = (val >> 23) & 1;
1825         r->mask = (val >> 24) & 0xff;
1826 }
1827
1828 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1829 {
1830         cmipci_sb_reg_t reg;
1831
1832         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1833         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1834         uinfo->count = reg.stereo + 1;
1835         uinfo->value.integer.min = 0;
1836         uinfo->value.integer.max = reg.mask;
1837         return 0;
1838 }
1839
1840 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1841 {
1842         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1843         unsigned long flags;
1844         cmipci_sb_reg_t reg;
1845         int val;
1846
1847         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1848         spin_lock_irqsave(&cm->reg_lock, flags);
1849         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1850         if (reg.invert)
1851                 val = reg.mask - val;
1852         ucontrol->value.integer.value[0] = val;
1853         if (reg.stereo) {
1854                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1855                 if (reg.invert)
1856                         val = reg.mask - val;
1857                  ucontrol->value.integer.value[1] = val;
1858         }
1859         spin_unlock_irqrestore(&cm->reg_lock, flags);
1860         return 0;
1861 }
1862
1863 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1864 {
1865         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1866         unsigned long flags;
1867         cmipci_sb_reg_t reg;
1868         int change;
1869         int left, right, oleft, oright;
1870
1871         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1872         left = ucontrol->value.integer.value[0] & reg.mask;
1873         if (reg.invert)
1874                 left = reg.mask - left;
1875         left <<= reg.left_shift;
1876         if (reg.stereo) {
1877                 right = ucontrol->value.integer.value[1] & reg.mask;
1878                 if (reg.invert)
1879                         right = reg.mask - right;
1880                 right <<= reg.right_shift;
1881         } else
1882                 right = 0;
1883         spin_lock_irqsave(&cm->reg_lock, flags);
1884         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1885         left |= oleft & ~(reg.mask << reg.left_shift);
1886         change = left != oleft;
1887         if (reg.stereo) {
1888                 if (reg.left_reg != reg.right_reg) {
1889                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
1890                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1891                 } else
1892                         oright = left;
1893                 right |= oright & ~(reg.mask << reg.right_shift);
1894                 change |= right != oright;
1895                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1896         } else
1897                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1898         spin_unlock_irqrestore(&cm->reg_lock, flags);
1899         return change;
1900 }
1901
1902 /*
1903  * input route (left,right) -> (left,right)
1904  */
1905 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1906 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1907   .info = snd_cmipci_info_input_sw, \
1908   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1909   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1910 }
1911
1912 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1913 {
1914         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1915         uinfo->count = 4;
1916         uinfo->value.integer.min = 0;
1917         uinfo->value.integer.max = 1;
1918         return 0;
1919 }
1920
1921 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1922 {
1923         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1924         unsigned long flags;
1925         cmipci_sb_reg_t reg;
1926         int val1, val2;
1927
1928         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1929         spin_lock_irqsave(&cm->reg_lock, flags);
1930         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1931         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1932         spin_unlock_irqrestore(&cm->reg_lock, flags);
1933         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1934         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1935         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1936         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1937         return 0;
1938 }
1939
1940 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1941 {
1942         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1943         unsigned long flags;
1944         cmipci_sb_reg_t reg;
1945         int change;
1946         int val1, val2, oval1, oval2;
1947
1948         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1949         spin_lock_irqsave(&cm->reg_lock, flags);
1950         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1951         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1952         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1953         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1954         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1955         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1956         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1957         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1958         change = val1 != oval1 || val2 != oval2;
1959         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1960         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1961         spin_unlock_irqrestore(&cm->reg_lock, flags);
1962         return change;
1963 }
1964
1965 /*
1966  * native mixer switches/volumes
1967  */
1968
1969 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1970 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1971   .info = snd_cmipci_info_native_mixer, \
1972   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1973   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1974 }
1975
1976 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1977 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1978   .info = snd_cmipci_info_native_mixer, \
1979   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1980   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1981 }
1982
1983 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1984 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1985   .info = snd_cmipci_info_native_mixer, \
1986   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1987   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1988 }
1989
1990 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1991 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1992   .info = snd_cmipci_info_native_mixer, \
1993   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1994   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
1995 }
1996
1997 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1998 {
1999         cmipci_sb_reg_t reg;
2000
2001         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2002         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2003         uinfo->count = reg.stereo + 1;
2004         uinfo->value.integer.min = 0;
2005         uinfo->value.integer.max = reg.mask;
2006         return 0;
2007
2008 }
2009
2010 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2011 {
2012         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2013         cmipci_sb_reg_t reg;
2014         unsigned long flags;
2015         unsigned char oreg, val;
2016
2017         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2018         spin_lock_irqsave(&cm->reg_lock, flags);
2019         oreg = inb(cm->iobase + reg.left_reg);
2020         val = (oreg >> reg.left_shift) & reg.mask;
2021         if (reg.invert)
2022                 val = reg.mask - val;
2023         ucontrol->value.integer.value[0] = val;
2024         if (reg.stereo) {
2025                 val = (oreg >> reg.right_shift) & reg.mask;
2026                 if (reg.invert)
2027                         val = reg.mask - val;
2028                 ucontrol->value.integer.value[1] = val;
2029         }
2030         spin_unlock_irqrestore(&cm->reg_lock, flags);
2031         return 0;
2032 }
2033
2034 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2035 {
2036         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2037         cmipci_sb_reg_t reg;
2038         unsigned long flags;
2039         unsigned char oreg, nreg, val;
2040
2041         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2042         spin_lock_irqsave(&cm->reg_lock, flags);
2043         oreg = inb(cm->iobase + reg.left_reg);
2044         val = ucontrol->value.integer.value[0] & reg.mask;
2045         if (reg.invert)
2046                 val = reg.mask - val;
2047         nreg = oreg & ~(reg.mask << reg.left_shift);
2048         nreg |= (val << reg.left_shift);
2049         if (reg.stereo) {
2050                 val = ucontrol->value.integer.value[1] & reg.mask;
2051                 if (reg.invert)
2052                         val = reg.mask - val;
2053                 nreg &= ~(reg.mask << reg.right_shift);
2054                 nreg |= (val << reg.right_shift);
2055         }
2056         outb(nreg, cm->iobase + reg.left_reg);
2057         spin_unlock_irqrestore(&cm->reg_lock, flags);
2058         return (nreg != oreg);
2059 }
2060
2061 /*
2062  * special case - check mixer sensitivity
2063  */
2064 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2065 {
2066         //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2067         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2068 }
2069
2070 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2071 {
2072         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2073         if (cm->mixer_insensitive) {
2074                 /* ignored */
2075                 return 0;
2076         }
2077         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2078 }
2079
2080
2081 #define num_controls(ary) (sizeof(ary) / sizeof(snd_kcontrol_new_t))
2082
2083 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2084         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2085         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2086         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2087         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2088         { /* switch with sensitivity */
2089                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2090                 .name = "PCM Playback Switch",
2091                 .info = snd_cmipci_info_native_mixer,
2092                 .get = snd_cmipci_get_native_mixer_sensitive,
2093                 .put = snd_cmipci_put_native_mixer_sensitive,
2094                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2095         },
2096         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2097         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2098         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2099         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2100         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2101         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2102         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2103         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2104         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2105         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2106         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2107         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2108         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2109         CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2110         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2111         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2112         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2113         CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2114         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2115 };
2116
2117 /*
2118  * other switches
2119  */
2120
2121 typedef struct snd_cmipci_switch_args {
2122         int reg;                /* register index */
2123         unsigned int mask;      /* mask bits */
2124         unsigned int mask_on;   /* mask bits to turn on */
2125         int is_byte: 1;         /* byte access? */
2126         int ac3_sensitive: 1;   /* access forbidden during non-audio operation? */
2127 } snd_cmipci_switch_args_t;
2128
2129 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2130 {
2131         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2132         uinfo->count = 1;
2133         uinfo->value.integer.min = 0;
2134         uinfo->value.integer.max = 1;
2135         return 0;
2136 }
2137
2138 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2139 {
2140         unsigned long flags;
2141         unsigned int val;
2142         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2143
2144         spin_lock_irqsave(&cm->reg_lock, flags);
2145         if (args->ac3_sensitive && cm->mixer_insensitive) {
2146                 ucontrol->value.integer.value[0] = 0;
2147                 spin_unlock_irqrestore(&cm->reg_lock, flags);
2148                 return 0;
2149         }
2150         if (args->is_byte)
2151                 val = inb(cm->iobase + args->reg);
2152         else
2153                 val = snd_cmipci_read(cm, args->reg);
2154         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2155         spin_unlock_irqrestore(&cm->reg_lock, flags);
2156         return 0;
2157 }
2158
2159 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2160 {
2161         snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2162         snd_assert(args != NULL, return -EINVAL);
2163         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2164 }
2165
2166 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2167 {
2168         unsigned long flags;
2169         unsigned int val;
2170         int change;
2171         cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2172
2173         spin_lock_irqsave(&cm->reg_lock, flags);
2174         if (args->ac3_sensitive && cm->mixer_insensitive) {
2175                 /* ignored */
2176                 spin_unlock_irqrestore(&cm->reg_lock, flags);
2177                 return 0;
2178         }
2179         if (args->is_byte)
2180                 val = inb(cm->iobase + args->reg);
2181         else
2182                 val = snd_cmipci_read(cm, args->reg);
2183         change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2184         if (change) {
2185                 val &= ~args->mask;
2186                 if (ucontrol->value.integer.value[0])
2187                         val |= args->mask_on;
2188                 else
2189                         val |= (args->mask & ~args->mask_on);
2190                 if (args->is_byte)
2191                         outb((unsigned char)val, cm->iobase + args->reg);
2192                 else
2193                         snd_cmipci_write(cm, args->reg, val);
2194         }
2195         spin_unlock_irqrestore(&cm->reg_lock, flags);
2196         return change;
2197 }
2198
2199 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2200 {
2201         snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2202         snd_assert(args != NULL, return -EINVAL);
2203         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2204 }
2205
2206 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2207 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2208   .reg = xreg, \
2209   .mask = xmask, \
2210   .mask_on = xmask_on, \
2211   .is_byte = xis_byte, \
2212   .ac3_sensitive = xac3, \
2213 }
2214
2215 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2216         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2217
2218 #if 0 /* these will be controlled in pcm device */
2219 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2220 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2221 #endif
2222 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2223 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2224 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2225 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2226 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2227 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2228 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2229 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2230 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2231 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2232 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2233 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2234 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2235 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2236 #if CM_CH_PLAY == 1
2237 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2238 #else
2239 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2240 #endif
2241 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2242 DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2243 DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2244 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2245 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2246
2247 #define DEFINE_SWITCH(sname, stype, sarg) \
2248 { .name = sname, \
2249   .iface = stype, \
2250   .info = snd_cmipci_uswitch_info, \
2251   .get = snd_cmipci_uswitch_get, \
2252   .put = snd_cmipci_uswitch_put, \
2253   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2254 }
2255
2256 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2257 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2258
2259
2260 /*
2261  * callbacks for spdif output switch
2262  * needs toggle two registers..
2263  */
2264 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2265 {
2266         int changed;
2267         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2268         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2269         return changed;
2270 }
2271
2272 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2273 {
2274         cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2275         int changed;
2276         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2277         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2278         if (changed) {
2279                 if (ucontrol->value.integer.value[0]) {
2280                         if (chip->spdif_playback_avail)
2281                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2282                 } else {
2283                         if (chip->spdif_playback_avail)
2284                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2285                 }
2286         }
2287         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2288         return changed;
2289 }
2290
2291
2292 /* both for CM8338/8738 */
2293 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2294         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2295         DEFINE_MIXER_SWITCH("Line-In As Rear", line_rear),
2296 };
2297
2298 /* for non-multichannel chips */
2299 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2300 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2301
2302 /* only for CM8738 */
2303 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2304 #if 0 /* controlled in pcm device */
2305         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2306         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2307         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2308 #endif
2309         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2310         { .name = "IEC958 Output Switch",
2311           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2312           .info = snd_cmipci_uswitch_info,
2313           .get = snd_cmipci_spdout_enable_get,
2314           .put = snd_cmipci_spdout_enable_put,
2315         },
2316         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2317         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2318         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2319 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2320         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2321         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2322 };
2323
2324 /* only for model 033/037 */
2325 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2326         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2327         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2328         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2329 };
2330
2331 /* only for model 039 or later */
2332 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
2333         DEFINE_MIXER_SWITCH("Line-In As Bass", line_bass),
2334         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2335         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2336         DEFINE_MIXER_SWITCH("Mic As Center/LFE", spdi_phase), /* same bit as spdi_phase */
2337 };
2338
2339 /* card control switches */
2340 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2341         // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2342         DEFINE_CARD_SWITCH("Modem", modem),
2343 };
2344
2345
2346 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2347 {
2348         unsigned long flags;
2349         snd_card_t *card;
2350         snd_kcontrol_new_t *sw;
2351         snd_kcontrol_t *kctl;
2352         unsigned int idx;
2353         int err;
2354
2355         snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2356
2357         card = cm->card;
2358
2359         strcpy(card->mixername, "CMedia PCI");
2360
2361         spin_lock_irqsave(&cm->reg_lock, flags);
2362         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2363         spin_unlock_irqrestore(&cm->reg_lock, flags);
2364
2365         for (idx = 0; idx < num_controls(snd_cmipci_mixers); idx++) {
2366                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2367                         return err;
2368         }
2369
2370         /* mixer switches */
2371         sw = snd_cmipci_mixer_switches;
2372         for (idx = 0; idx < num_controls(snd_cmipci_mixer_switches); idx++, sw++) {
2373                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2374                 if (err < 0)
2375                         return err;
2376         }
2377         if (! cm->can_multi_ch) {
2378                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2379                 if (err < 0)
2380                         return err;
2381         }
2382         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2383             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2384                 sw = snd_cmipci_8738_mixer_switches;
2385                 for (idx = 0; idx < num_controls(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2386                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2387                         if (err < 0)
2388                                 return err;
2389                 }
2390                 if (cm->can_ac3_hw) {
2391                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2392                                 return err;
2393                         kctl->id.device = pcm_spdif_device;
2394                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2395                                 return err;
2396                         kctl->id.device = pcm_spdif_device;
2397                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2398                                 return err;
2399                         kctl->id.device = pcm_spdif_device;
2400                 }
2401                 if (cm->chip_version <= 37) {
2402                         sw = snd_cmipci_old_mixer_switches;
2403                         for (idx = 0; idx < num_controls(snd_cmipci_old_mixer_switches); idx++, sw++) {
2404                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2405                                 if (err < 0)
2406                                         return err;
2407                         }
2408                 }
2409         }
2410         if (cm->chip_version >= 39) {
2411                 sw = snd_cmipci_extra_mixer_switches;
2412                 for (idx = 0; idx < num_controls(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2413                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2414                         if (err < 0)
2415                                 return err;
2416                 }
2417         }
2418
2419         /* card switches */
2420         sw = snd_cmipci_control_switches;
2421         for (idx = 0; idx < num_controls(snd_cmipci_control_switches); idx++, sw++) {
2422                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2423                 if (err < 0)
2424                         return err;
2425         }
2426
2427         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2428                 snd_ctl_elem_id_t id;
2429                 snd_kcontrol_t *ctl;
2430                 memset(&id, 0, sizeof(id));
2431                 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2432                 strcpy(id.name, cm_saved_mixer[idx].name);
2433                 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2434                         cm->mixer_res_ctl[idx] = ctl;
2435         }
2436
2437         return 0;
2438 }
2439
2440
2441 /*
2442  * proc interface
2443  */
2444
2445 #ifdef CONFIG_PROC_FS
2446 static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2447                                  snd_info_buffer_t *buffer)
2448 {
2449         cmipci_t *cm = snd_magic_cast(cmipci_t, entry->private_data, return);
2450         int i;
2451
2452         snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2453         for (i = 0; i < 0x40; i++) {
2454                 int v = inb(cm->iobase + i);
2455                 if (i % 4 == 0)
2456                         snd_iprintf(buffer, "%02x: ", i);
2457                 snd_iprintf(buffer, "%02x", v);
2458                 if (i % 4 == 3)
2459                         snd_iprintf(buffer, "\n");
2460                 else
2461                         snd_iprintf(buffer, " ");
2462         }
2463 }
2464
2465 static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2466 {
2467         snd_info_entry_t *entry;
2468
2469         if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2470                 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2471 }
2472 #else /* !CONFIG_PROC_FS */
2473 static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2474 #endif
2475
2476
2477 static struct pci_device_id snd_cmipci_ids[] = {
2478         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2479         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2480         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2481         {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2482         {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2483         {0,},
2484 };
2485
2486
2487 /*
2488  * check chip version and capabilities
2489  * driver name is modified according to the chip model
2490  */
2491 static void __devinit query_chip(cmipci_t *cm)
2492 {
2493         unsigned int detect;
2494
2495         /* check reg 0Ch, bit 24-31 */
2496         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2497         if (! detect) {
2498                 /* check reg 08h, bit 24-28 */
2499                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2500                 if (! detect) {
2501                         cm->chip_version = 33;
2502                         cm->max_channels = 2;
2503                         if (cm->do_soft_ac3)
2504                                 cm->can_ac3_sw = 1;
2505                         else
2506                                 cm->can_ac3_hw = 1;
2507                         cm->has_dual_dac = 1;
2508                 } else {
2509                         cm->chip_version = 37;
2510                         cm->max_channels = 2;
2511                         cm->can_ac3_hw = 1;
2512                         cm->has_dual_dac = 1;
2513                 }
2514         } else {
2515                 /* check reg 0Ch, bit 26 */
2516                 if (detect & CM_CHIP_039) {
2517                         cm->chip_version = 39;
2518                         if (detect & CM_CHIP_039_6CH)
2519                                 cm->max_channels  = 6;
2520                         else
2521                                 cm->max_channels = 4;
2522                         cm->can_ac3_hw = 1;
2523                         cm->has_dual_dac = 1;
2524                         cm->can_multi_ch = 1;
2525                 } else {
2526                         cm->chip_version = 55; /* 4 or 6 channels */
2527                         cm->max_channels  = 6;
2528                         cm->can_ac3_hw = 1;
2529                         cm->has_dual_dac = 1;
2530                         cm->can_multi_ch = 1;
2531                 }
2532         }
2533
2534         /* added -MCx suffix for chip supporting multi-channels */
2535         if (cm->can_multi_ch)
2536                 sprintf(cm->card->driver + strlen(cm->card->driver),
2537                         "-MC%d", cm->max_channels);
2538         else if (cm->can_ac3_sw)
2539                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2540 }
2541
2542
2543 static int snd_cmipci_free(cmipci_t *cm)
2544 {
2545         if (cm->irq >= 0) {
2546                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2547                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2548                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2549                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2550                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2551                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2552                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2553
2554                 /* reset mixer */
2555                 snd_cmipci_mixer_write(cm, 0, 0);
2556
2557                 synchronize_irq(cm->irq);
2558
2559                 free_irq(cm->irq, (void *)cm);
2560         }
2561 #ifdef SUPPORT_JOYSTICK
2562         if (cm->res_joystick) {
2563                 gameport_unregister_port(&cm->gameport);
2564                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2565                 release_resource(cm->res_joystick);
2566                 kfree_nocheck(cm->res_joystick);
2567         }
2568 #endif
2569         if (cm->res_iobase) {
2570                 release_resource(cm->res_iobase);
2571                 kfree_nocheck(cm->res_iobase);
2572         }
2573         snd_magic_kfree(cm);
2574         return 0;
2575 }
2576
2577 static int snd_cmipci_dev_free(snd_device_t *device)
2578 {
2579         cmipci_t *cm = snd_magic_cast(cmipci_t, device->device_data, return -ENXIO);
2580         return snd_cmipci_free(cm);
2581 }
2582
2583 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2584                                        int dev, cmipci_t **rcmipci)
2585 {
2586         cmipci_t *cm;
2587         int err;
2588         static snd_device_ops_t ops = {
2589                 .dev_free =     snd_cmipci_dev_free,
2590         };
2591         unsigned int val = 0;
2592         long iomidi = mpu_port[dev];
2593         long iosynth = fm_port[dev];
2594         int pcm_index, pcm_spdif_index;
2595
2596         *rcmipci = NULL;
2597
2598         if ((err = pci_enable_device(pci)) < 0)
2599                 return err;
2600
2601         cm = snd_magic_kcalloc(cmipci_t, 0, GFP_KERNEL);
2602         if (cm == NULL)
2603                 return -ENOMEM;
2604
2605         spin_lock_init(&cm->reg_lock);
2606         init_MUTEX(&cm->open_mutex);
2607         cm->device = pci->device;
2608         cm->card = card;
2609         cm->pci = pci;
2610         cm->irq = -1;
2611         cm->iobase = pci_resource_start(pci, 0);
2612         cm->channel[0].ch = 0;
2613         cm->channel[1].ch = 1;
2614         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2615
2616         if ((cm->res_iobase = request_region(cm->iobase, CM_EXTENT_CODEC, card->driver)) == NULL) {
2617                 snd_printk("unable to grab ports 0x%lx-0x%lx\n", cm->iobase, cm->iobase + CM_EXTENT_CODEC - 1);
2618                 err = -EBUSY;
2619                 goto __error;
2620         }
2621         if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
2622                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2623                 err = -EBUSY;
2624                 goto __error;
2625         }
2626         cm->irq = pci->irq;
2627
2628         pci_set_master(cm->pci);
2629
2630         /*
2631          * check chip version, max channels and capabilities
2632          */
2633
2634         cm->chip_version = 0;
2635         cm->max_channels = 2;
2636         cm->do_soft_ac3 = soft_ac3[dev];
2637
2638         query_chip(cm);
2639
2640         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2641         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2642
2643 #if CM_CH_PLAY == 1
2644         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
2645 #else
2646         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
2647 #endif
2648
2649         /* initialize codec registers */
2650         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
2651         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2652         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2653         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
2654         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2655
2656         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2657         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2658 #if CM_CH_PLAY == 1
2659         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2660 #else
2661         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2662 #endif
2663         /* Set Bus Master Request */
2664         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2665
2666         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2667         switch (pci->device) {
2668         case PCI_DEVICE_ID_CMEDIA_CM8738:
2669         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2670                 /* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX */
2671                 if (! pci_find_device(0x8086, 0x7030, NULL))
2672                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2673                 break;
2674         default:
2675                 break;
2676         }
2677
2678         /* set MPU address */
2679         switch (iomidi) {
2680         case 0x320: val = CM_VMPU_320; break;
2681         case 0x310: val = CM_VMPU_310; break;
2682         case 0x300: val = CM_VMPU_300; break;
2683         case 0x330: val = CM_VMPU_330; break;
2684         default:
2685                 iomidi = 0; break;
2686         }
2687         if (iomidi > 0) {
2688                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2689                 /* enable UART */
2690                 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2691         }
2692
2693         /* set FM address */
2694         val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2695         switch (iosynth) {
2696         case 0x3E8: val |= CM_FMSEL_3E8; break;
2697         case 0x3E0: val |= CM_FMSEL_3E0; break;
2698         case 0x3C8: val |= CM_FMSEL_3C8; break;
2699         case 0x388: val |= CM_FMSEL_388; break;
2700         default:
2701                 iosynth = 0; break;
2702         }
2703         if (iosynth > 0) {
2704                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2705                 /* enable FM */
2706                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2707
2708                 if (snd_opl3_create(card, iosynth, iosynth + 2,
2709                                     OPL3_HW_OPL3, 0, &cm->opl3) < 0) {
2710                         printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth);
2711                         iosynth = 0;
2712                 } else {
2713                         if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) {
2714                                 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2715                                 return err;
2716                         }
2717                 }
2718         }
2719         if (! iosynth) {
2720                 /* disable FM */
2721                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK);
2722                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2723         }
2724
2725         /* reset mixer */
2726         snd_cmipci_mixer_write(cm, 0, 0);
2727
2728         snd_cmipci_proc_init(cm);
2729
2730         /* create pcm devices */
2731         pcm_index = pcm_spdif_index = 0;
2732         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2733                 goto __error;
2734         pcm_index++;
2735         if (cm->has_dual_dac) {
2736                 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2737                         goto __error;
2738                 pcm_index++;
2739         }
2740         if (cm->can_ac3_hw || cm->can_ac3_sw) {
2741                 pcm_spdif_index = pcm_index;
2742                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2743                         goto __error;
2744         }
2745
2746         /* create mixer interface & switches */
2747         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2748                 goto __error;
2749
2750         if (iomidi > 0) {
2751                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2752                                                iomidi, 0,
2753                                                cm->irq, 0, &cm->rmidi)) < 0) {
2754                         printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2755                 }
2756         }
2757
2758         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2759                 snd_cmipci_free(cm);
2760                 return err;
2761         }
2762 #ifdef USE_VAR48KRATE
2763         for (val = 0; val < ARRAY_SIZE(rates); val++)
2764                 snd_cmipci_set_pll(cm, rates[val], val);
2765
2766         /*
2767          * (Re-)Enable external switch spdo_48k
2768          */
2769         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2770 #endif /* USE_VAR48KRATE */
2771
2772 #ifdef SUPPORT_JOYSTICK
2773         if (joystick_port[dev] > 0) {
2774                 if (joystick_port[dev] == 1) { /* auto-detect */
2775                         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2776                         int i;
2777                         for (i = 0; ports[i]; i++) {
2778                                 joystick_port[dev] = ports[i];
2779                                 cm->res_joystick = request_region(ports[i], 8, "CMIPCI gameport");
2780                                 if (cm->res_joystick)
2781                                         break;
2782                         }
2783                 } else {
2784                         cm->res_joystick = request_region(joystick_port[dev], 8, "CMIPCI gameport");
2785                 }
2786         }
2787         if (cm->res_joystick) {
2788                 cm->gameport.io = joystick_port[dev];
2789                 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2790                 gameport_register_port(&cm->gameport);
2791         } else {
2792                 if (joystick_port[dev] > 0)
2793                         printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2794                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2795         }
2796 #endif
2797         snd_card_set_dev(card, &pci->dev);
2798
2799         *rcmipci = cm;
2800         return 0;
2801
2802  __error:
2803         snd_cmipci_free(cm);
2804         return err;
2805 }
2806
2807 /*
2808  */
2809
2810 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2811
2812 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2813                                       const struct pci_device_id *pci_id)
2814 {
2815         static int dev;
2816         snd_card_t *card;
2817         cmipci_t *cm;
2818         int err;
2819
2820         if (dev >= SNDRV_CARDS)
2821                 return -ENODEV;
2822         if (! enable[dev]) {
2823                 dev++;
2824                 return -ENOENT;
2825         }
2826
2827         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2828         if (card == NULL)
2829                 return -ENOMEM;
2830
2831         switch (pci->device) {
2832         case PCI_DEVICE_ID_CMEDIA_CM8738:
2833         case PCI_DEVICE_ID_CMEDIA_CM8738B:
2834                 strcpy(card->driver, "CMI8738");
2835                 break;
2836         case PCI_DEVICE_ID_CMEDIA_CM8338A:
2837         case PCI_DEVICE_ID_CMEDIA_CM8338B:
2838                 strcpy(card->driver, "CMI8338");
2839                 break;
2840         default:
2841                 strcpy(card->driver, "CMIPCI");
2842                 break;
2843         }
2844
2845         if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
2846                 snd_card_free(card);
2847                 return err;
2848         }
2849
2850         sprintf(card->shortname, "C-Media PCI %s", card->driver);
2851         sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
2852                 card->shortname,
2853                 cm->chip_version,
2854                 cm->iobase,
2855                 cm->irq);
2856
2857         //snd_printd("%s is detected\n", card->longname);
2858
2859         if ((err = snd_card_register(card)) < 0) {
2860                 snd_card_free(card);
2861                 return err;
2862         }
2863         pci_set_drvdata(pci, card);
2864         dev++;
2865         return 0;
2866
2867 }
2868
2869 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
2870 {
2871         snd_card_free(pci_get_drvdata(pci));
2872         pci_set_drvdata(pci, NULL);
2873 }
2874
2875
2876 static struct pci_driver driver = {
2877         .name = "C-Media PCI",
2878         .id_table = snd_cmipci_ids,
2879         .probe = snd_cmipci_probe,
2880         .remove = __devexit_p(snd_cmipci_remove),
2881 };
2882
2883 static int __init alsa_card_cmipci_init(void)
2884 {
2885         return pci_module_init(&driver);
2886 }
2887
2888 static void __exit alsa_card_cmipci_exit(void)
2889 {
2890         pci_unregister_driver(&driver);
2891 }
2892
2893 module_init(alsa_card_cmipci_init)
2894 module_exit(alsa_card_cmipci_exit)