sound/pci/cs4281.c

   1 /*
   2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <linux/moduleparam.h>
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/rawmidi.h>
  35 #include <sound/ac97_codec.h>
  36 #include <sound/opl3.h>
  37 #include <sound/initval.h>
  38
  39
  40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
  42 MODULE_LICENSE("GPL");
  43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
  44
  45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  47 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  48 static int dual_codec[SNDRV_CARDS];     /* dual codec */
  49 static int boot_devs;
  50
  51 module_param_array(index, int, boot_devs, 0444);
  52 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  53 module_param_array(id, charp, boot_devs, 0444);
  54 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  55 module_param_array(enable, bool, boot_devs, 0444);
  56 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  57 module_param_array(dual_codec, bool, boot_devs, 0444);
  58 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  59
  60 /*
  61  *
  62  */
  63
  64 #ifndef PCI_VENDOR_ID_CIRRUS
  65 #define PCI_VENDOR_ID_CIRRUS            0x1013
  66 #endif
  67 #ifndef PCI_DEVICE_ID_CIRRUS_4281
  68 #define PCI_DEVICE_ID_CIRRUS_4281       0x6005
  69 #endif
  70
  71 /*
  72  *  Direct registers
  73  */
  74
  75 #define CS4281_BA0_SIZE         0x1000
  76 #define CS4281_BA1_SIZE         0x10000
  77
  78 /*
  79  *  BA0 registers
  80  */
  81 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
  82 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
  83 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
  84 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
  85 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
  86 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
  87 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
  88 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
  89 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
  90 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
  91 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
  92 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
  93 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
  94
  95 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
  96 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
  97 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
  98 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
  99
 100 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
 101                                         /* Use same contants as for BA0_HISR */
 102
 103 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
 104
 105 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
 106 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
 107 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
 108 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
 109
 110 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
 111 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
 112 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
 113 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
 114 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
 115 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
 116
 117 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
 118 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
 119 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
 120 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
 121 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
 122 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
 123 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
 124 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
 125 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
 126 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
 127 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
 128 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
 129 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
 130 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
 131 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
 132 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
 133 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
 134 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
 135 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
 136 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
 137 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
 138 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
 139 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
 140 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
 141
 142 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
 143 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
 144 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
 145 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
 146 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
 147 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
 148 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
 149 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
 150 #define BA0_DMR_MONO            (1<<17) /* Mono */
 151 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
 152 #define BA0_DMR_TYPE_DEMAND     (0<<6)
 153 #define BA0_DMR_TYPE_SINGLE     (1<<6)
 154 #define BA0_DMR_TYPE_BLOCK      (2<<6)
 155 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
 156 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
 157 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
 158 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
 159 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
 160 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
 161
 162 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
 163 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
 164 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
 165
 166 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
 167 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
 168 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
 169 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
 170
 171 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
 172 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
 173 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
 174 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
 175 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
 176 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
 177 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
 178
 179 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
 180 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
 181 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
 182 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
 183
 184 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
 185 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
 186 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
 187 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
 188 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
 189 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
 190 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
 191 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
 192 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
 193
 194 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
 195 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
 196 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
 197 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
 198
 199 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
 200 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
 201 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
 202 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
 203 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
 204 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
 205 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
 206 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
 207
 208 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
 209 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
 210 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
 211 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
 212
 213 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
 214 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
 215 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
 216 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
 217 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
 218 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
 219 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
 220 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
 221 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
 222 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
 223
 224 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
 225 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
 226 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
 227 #define BA0_TMS                 0x03f8  /* Test Register */
 228 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
 229
 230 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
 231 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
 232 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
 233 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
 234 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
 235 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
 236 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
 237
 238 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
 239 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
 240
 241 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
 242 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
 243 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
 244 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
 245 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
 246 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
 247 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
 248 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
 249 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
 250 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
 251 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
 252 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
 253 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
 254
 255 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
 256 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
 257 #define BA0_SERC1_AC97          (1<<1)
 258 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
 259
 260 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
 261 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
 262 #define BA0_SERC2_AC97          (1<<1)
 263 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
 264
 265 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
 266
 267 #define BA0_ACCTL               0x0460  /* AC'97 Control */
 268 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
 269 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
 270 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
 271 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
 272 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
 273
 274 #define BA0_ACSTS               0x0464  /* AC'97 Status */
 275 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
 276 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
 277
 278 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
 279 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
 280
 281 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
 282 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
 283
 284 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
 285 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
 286
 287 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
 288 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
 289 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
 290 #define BA0_JSCTL               0x0484  /* Joystick control */
 291 #define BA0_JSC1                0x0488  /* Joystick control */
 292 #define BA0_JSC2                0x048c  /* Joystick control */
 293 #define BA0_JSIO                0x04a0
 294
 295 #define BA0_MIDCR               0x0490  /* MIDI Control */
 296 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
 297 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
 298 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
 299 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
 300 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
 301 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
 302
 303 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
 304
 305 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
 306 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
 307 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
 308 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
 309 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
 310
 311 #define BA0_MIDWP               0x0498  /* MIDI Write */
 312 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
 313
 314 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
 315 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
 316
 317 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
 318 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
 319
 320 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
 321 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
 322 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
 323 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
 324 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
 325 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
 326 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
 327 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
 328 #define BA0_FMDP                0x0734  /* FM Data Port */
 329 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
 330 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
 331
 332 #define BA0_SSPM                0x0740  /* Sound System Power Management */
 333 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
 334 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
 335 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
 336 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
 337 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
 338 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
 339
 340 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
 341 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
 342
 343 #define BA0_SSCR                0x074c  /* Sound System Control Register */
 344 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
 345 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
 346 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
 347 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
 348 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
 349 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
 350 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
 351 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
 352 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
 353
 354 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
 355 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
 356 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
 357 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
 358 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
 359 #define BA0_PASR                0x0768  /* playback sample rate */
 360 #define BA0_CASR                0x076C  /* capture sample rate */
 361
 362 /* Source Slot Numbers - Playback */
 363 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
 364 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
 365 #define SRCSLOT_PHONE_LINE_1_DAC                2
 366 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
 367 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
 368 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
 369 #define SRCSLOT_LFE_PCM_PLAYBACK                6
 370 #define SRCSLOT_PHONE_LINE_2_DAC                7
 371 #define SRCSLOT_HEADSET_DAC                     8
 372 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
 373 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
 374
 375 /* Source Slot Numbers - Capture */
 376 #define SRCSLOT_LEFT_PCM_RECORD                 10
 377 #define SRCSLOT_RIGHT_PCM_RECORD                11
 378 #define SRCSLOT_PHONE_LINE_1_ADC                12
 379 #define SRCSLOT_MIC_ADC                         13
 380 #define SRCSLOT_PHONE_LINE_2_ADC                17
 381 #define SRCSLOT_HEADSET_ADC                     18
 382 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
 383 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
 384 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
 385 #define SRCSLOT_SECONDARY_MIC_ADC               23
 386 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
 387 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
 388
 389 /* Source Slot Numbers - Others */
 390 #define SRCSLOT_POWER_DOWN                      31
 391
 392 /* MIDI modes */
 393 #define CS4281_MODE_OUTPUT              (1<<0)
 394 #define CS4281_MODE_INPUT               (1<<1)
 395
 396 /* joystick bits */
 397 /* Bits for JSPT */
 398 #define JSPT_CAX                                0x00000001
 399 #define JSPT_CAY                                0x00000002
 400 #define JSPT_CBX                                0x00000004
 401 #define JSPT_CBY                                0x00000008
 402 #define JSPT_BA1                                0x00000010
 403 #define JSPT_BA2                                0x00000020
 404 #define JSPT_BB1                                0x00000040
 405 #define JSPT_BB2                                0x00000080
 406
 407 /* Bits for JSCTL */
 408 #define JSCTL_SP_MASK                           0x00000003
 409 #define JSCTL_SP_SLOW                           0x00000000
 410 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
 411 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
 412 #define JSCTL_SP_FAST                           0x00000003
 413 #define JSCTL_ARE                               0x00000004
 414
 415 /* Data register pairs masks */
 416 #define JSC1_Y1V_MASK                           0x0000FFFF
 417 #define JSC1_X1V_MASK                           0xFFFF0000
 418 #define JSC1_Y1V_SHIFT                          0
 419 #define JSC1_X1V_SHIFT                          16
 420 #define JSC2_Y2V_MASK                           0x0000FFFF
 421 #define JSC2_X2V_MASK                           0xFFFF0000
 422 #define JSC2_Y2V_SHIFT                          0
 423 #define JSC2_X2V_SHIFT                          16
 424
 425 /* JS GPIO */
 426 #define JSIO_DAX                                0x00000001
 427 #define JSIO_DAY                                0x00000002
 428 #define JSIO_DBX                                0x00000004
 429 #define JSIO_DBY                                0x00000008
 430 #define JSIO_AXOE                               0x00000010
 431 #define JSIO_AYOE                               0x00000020
 432 #define JSIO_BXOE                               0x00000040
 433 #define JSIO_BYOE                               0x00000080
 434
 435 /*
 436  *
 437  */
 438
 439 typedef struct snd_cs4281 cs4281_t;
 440 typedef struct snd_cs4281_dma cs4281_dma_t;
 441
 442 struct snd_cs4281_dma {
 443         snd_pcm_substream_t *substream;
 444         unsigned int regDBA;            /* offset to DBA register */
 445         unsigned int regDCA;            /* offset to DCA register */
 446         unsigned int regDBC;            /* offset to DBC register */
 447         unsigned int regDCC;            /* offset to DCC register */
 448         unsigned int regDMR;            /* offset to DMR register */
 449         unsigned int regDCR;            /* offset to DCR register */
 450         unsigned int regHDSR;           /* offset to HDSR register */
 451         unsigned int regFCR;            /* offset to FCR register */
 452         unsigned int regFSIC;           /* offset to FSIC register */
 453         unsigned int valDMR;            /* DMA mode */
 454         unsigned int valDCR;            /* DMA command */
 455         unsigned int valFCR;            /* FIFO control */
 456         unsigned int fifo_offset;       /* FIFO offset within BA1 */
 457         unsigned char left_slot;        /* FIFO left slot */
 458         unsigned char right_slot;       /* FIFO right slot */
 459         int frag;                       /* period number */
 460 };
 461
 462 #define SUSPEND_REGISTERS       20
 463
 464 struct snd_cs4281 {
 465         int irq;
 466
 467         unsigned long ba0;              /* virtual (accessible) address */
 468         unsigned long ba1;              /* virtual (accessible) address */
 469         unsigned long ba0_addr;
 470         unsigned long ba1_addr;
 471
 472         int dual_codec;
 473
 474         ac97_bus_t *ac97_bus;
 475         ac97_t *ac97;
 476         ac97_t *ac97_secondary;
 477
 478         struct pci_dev *pci;
 479         snd_card_t *card;
 480         snd_pcm_t *pcm;
 481         snd_rawmidi_t *rmidi;
 482         snd_rawmidi_substream_t *midi_input;
 483         snd_rawmidi_substream_t *midi_output;
 484
 485         cs4281_dma_t dma[4];
 486
 487         unsigned char src_left_play_slot;
 488         unsigned char src_right_play_slot;
 489         unsigned char src_left_rec_slot;
 490         unsigned char src_right_rec_slot;
 491
 492         unsigned int spurious_dhtc_irq;
 493         unsigned int spurious_dtc_irq;
 494
 495         spinlock_t reg_lock;
 496         unsigned int midcr;
 497         unsigned int uartm;
 498
 499         struct snd_cs4281_gameport *gameport;
 500
 501 #ifdef CONFIG_PM
 502         u32 suspend_regs[SUSPEND_REGISTERS];
 503 #endif
 504
 505 };
 506
 507 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 508
 509 static struct pci_device_id snd_cs4281_ids[] = {
 510         { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* CS4281 */
 511         { 0, }
 512 };
 513
 514 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
 515
 516 /*
 517  *  constants
 518  */
 519
 520 #define CS4281_FIFO_SIZE        32
 521
 522 /*
 523  *  common I/O routines
 524  */
 525
 526 static void snd_cs4281_delay(unsigned int delay)
 527 {
 528         if (delay > 999) {
 529                 unsigned long end_time;
 530                 delay = (delay * HZ) / 1000000;
 531                 if (delay < 1)
 532                         delay = 1;
 533                 end_time = jiffies + delay;
 534                 do {
 535                         set_current_state(TASK_UNINTERRUPTIBLE);
 536                         schedule_timeout(1);
 537                 } while (time_after_eq(end_time, jiffies));
 538         } else {
 539                 udelay(delay);
 540         }
 541 }
 542
 543 inline static void snd_cs4281_delay_long(void)
 544 {
 545         set_current_state(TASK_UNINTERRUPTIBLE);
 546         schedule_timeout(1);
 547 }
 548
 549 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
 550 {
 551         writel(val, chip->ba0 + offset);
 552 }
 553
 554 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
 555 {
 556         return readl(chip->ba0 + offset);
 557 }
 558
 559 static void snd_cs4281_ac97_write(ac97_t *ac97,
 560                                   unsigned short reg, unsigned short val)
 561 {
 562         /*
 563          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 564          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 565          *  3. Write ACCTL = Control Register = 460h for initiating the write
 566          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 567          *  5. if DCV not cleared, break and return error
 568          */
 569         cs4281_t *chip = ac97->private_data;
 570         int count;
 571
 572         /*
 573          *  Setup the AC97 control registers on the CS461x to send the
 574          *  appropriate command to the AC97 to perform the read.
 575          *  ACCAD = Command Address Register = 46Ch
 576          *  ACCDA = Command Data Register = 470h
 577          *  ACCTL = Control Register = 460h
 578          *  set DCV - will clear when process completed
 579          *  reset CRW - Write command
 580          *  set VFRM - valid frame enabled
 581          *  set ESYN - ASYNC generation enabled
 582          *  set RSTN - ARST# inactive, AC97 codec not reset
 583          */
 584         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 585         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
 586         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
 587                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
 588         for (count = 0; count < 2000; count++) {
 589                 /*
 590                  *  First, we want to wait for a short time.
 591                  */
 592                 udelay(10);
 593                 /*
 594                  *  Now, check to see if the write has completed.
 595                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 596                  */
 597                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
 598                         return;
 599                 }
 600         }
 601         snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
 602 }
 603
 604 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
 605                                            unsigned short reg)
 606 {
 607         cs4281_t *chip = ac97->private_data;
 608         int count;
 609         unsigned short result;
 610         // FIXME: volatile is necessary in the following due to a bug of
 611         // some gcc versions
 612         volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
 613
 614         /*
 615          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 616          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 617          *  3. Write ACCTL = Control Register = 460h for initiating the write
 618          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 619          *  5. if DCV not cleared, break and return error
 620          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 621          */
 622
 623         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 624
 625         /*
 626          *  Setup the AC97 control registers on the CS461x to send the
 627          *  appropriate command to the AC97 to perform the read.
 628          *  ACCAD = Command Address Register = 46Ch
 629          *  ACCDA = Command Data Register = 470h
 630          *  ACCTL = Control Register = 460h
 631          *  set DCV - will clear when process completed
 632          *  set CRW - Read command
 633          *  set VFRM - valid frame enabled
 634          *  set ESYN - ASYNC generation enabled
 635          *  set RSTN - ARST# inactive, AC97 codec not reset
 636          */
 637
 638         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 639         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
 640         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
 641                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
 642                            (ac97_num ? BA0_ACCTL_TC : 0));
 643
 644
 645         /*
 646          *  Wait for the read to occur.
 647          */
 648         for (count = 0; count < 500; count++) {
 649                 /*
 650                  *  First, we want to wait for a short time.
 651                  */
 652                 udelay(10);
 653                 /*
 654                  *  Now, check to see if the read has completed.
 655                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 656                  */
 657                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
 658                         goto __ok1;
 659         }
 660
 661         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 662         result = 0xffff;
 663         goto __end;
 664
 665       __ok1:
 666         /*
 667          *  Wait for the valid status bit to go active.
 668          */
 669         for (count = 0; count < 100; count++) {
 670                 /*
 671                  *  Read the AC97 status register.
 672                  *  ACSTS = Status Register = 464h
 673                  *  VSTS - Valid Status
 674                  */
 675                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
 676                         goto __ok2;
 677                 udelay(10);
 678         }
 679
 680         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
 681         result = 0xffff;
 682         goto __end;
 683
 684       __ok2:
 685         /*
 686          *  Read the data returned from the AC97 register.
 687          *  ACSDA = Status Data Register = 474h
 688          */
 689         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 690
 691       __end:
 692         return result;
 693 }
 694
 695 /*
 696  *  PCM part
 697  */
 698
 699 static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
 700 {
 701         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
 702         cs4281_t *chip = snd_pcm_substream_chip(substream);
 703
 704         spin_lock(&chip->reg_lock);
 705         switch (cmd) {
 706         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 707                 dma->valDCR |= BA0_DCR_MSK;
 708                 dma->valFCR |= BA0_FCR_FEN;
 709                 break;
 710         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 711                 dma->valDCR &= ~BA0_DCR_MSK;
 712                 dma->valFCR &= ~BA0_FCR_FEN;
 713                 break;
 714         case SNDRV_PCM_TRIGGER_START:
 715         case SNDRV_PCM_TRIGGER_RESUME:
 716                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
 717                 dma->valDMR |= BA0_DMR_DMA;
 718                 dma->valDCR &= ~BA0_DCR_MSK;
 719                 dma->valFCR |= BA0_FCR_FEN;
 720                 break;
 721         case SNDRV_PCM_TRIGGER_STOP:
 722         case SNDRV_PCM_TRIGGER_SUSPEND:
 723                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
 724                 dma->valDCR |= BA0_DCR_MSK;
 725                 dma->valFCR &= ~BA0_FCR_FEN;
 726                 /* Leave wave playback FIFO enabled for FM */
 727                 if (dma->regFCR != BA0_FCR0)
 728                         dma->valFCR &= ~BA0_FCR_FEN;
 729                 break;
 730         default:
 731                 spin_unlock(&chip->reg_lock);
 732                 return -EINVAL;
 733         }
 734         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
 735         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
 736         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
 737         spin_unlock(&chip->reg_lock);
 738         return 0;
 739 }
 740
 741 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
 742 {
 743         unsigned int val = ~0;
 744
 745         if (real_rate)
 746                 *real_rate = rate;
 747         /* special "hardcoded" rates */
 748         switch (rate) {
 749         case 8000:      return 5;
 750         case 11025:     return 4;
 751         case 16000:     return 3;
 752         case 22050:     return 2;
 753         case 44100:     return 1;
 754         case 48000:     return 0;
 755         default:
 756                 goto __variable;
 757         }
 758       __variable:
 759         val = 1536000 / rate;
 760         if (real_rate)
 761                 *real_rate = 1536000 / val;
 762         return val;
 763 }
 764
 765 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
 766 {
 767         int rec_mono;
 768
 769         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
 770                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
 771         if (runtime->channels == 1)
 772                 dma->valDMR |= BA0_DMR_MONO;
 773         if (snd_pcm_format_unsigned(runtime->format) > 0)
 774                 dma->valDMR |= BA0_DMR_USIGN;
 775         if (snd_pcm_format_big_endian(runtime->format) > 0)
 776                 dma->valDMR |= BA0_DMR_BEND;
 777         switch (snd_pcm_format_width(runtime->format)) {
 778         case 8: dma->valDMR |= BA0_DMR_SIZE8;
 779                 if (runtime->channels == 1)
 780                         dma->valDMR |= BA0_DMR_SWAPC;
 781                 break;
 782         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
 783         }
 784         dma->frag = 0;  /* for workaround */
 785         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
 786         if (runtime->buffer_size != runtime->period_size)
 787                 dma->valDCR |= BA0_DCR_HTCIE;
 788         /* Initialize DMA */
 789         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
 790         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
 791         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
 792         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
 793                                             (chip->src_right_play_slot << 8) |
 794                                             (chip->src_left_rec_slot << 16) |
 795                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
 796         if (!src)
 797                 goto __skip_src;
 798         if (!capture) {
 799                 if (dma->left_slot == chip->src_left_play_slot) {
 800                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 801                         snd_assert(dma->right_slot == chip->src_right_play_slot, );
 802                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
 803                 }
 804         } else {
 805                 if (dma->left_slot == chip->src_left_rec_slot) {
 806                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 807                         snd_assert(dma->right_slot == chip->src_right_rec_slot, );
 808                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
 809                 }
 810         }
 811       __skip_src:
 812         /* Deactivate wave playback FIFO before changing slot assignments */
 813         if (dma->regFCR == BA0_FCR0)
 814                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
 815         /* Initialize FIFO */
 816         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
 817                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
 818                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
 819                       BA0_FCR_OF(dma->fifo_offset);
 820         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
 821         /* Activate FIFO again for FM playback */
 822         if (dma->regFCR == BA0_FCR0)
 823                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
 824         /* Clear FIFO Status and Interrupt Control Register */
 825         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
 826 }
 827
 828 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
 829                                 snd_pcm_hw_params_t * hw_params)
 830 {
 831         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 832 }
 833
 834 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
 835 {
 836         return snd_pcm_lib_free_pages(substream);
 837 }
 838
 839 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
 840 {
 841         snd_pcm_runtime_t *runtime = substream->runtime;
 842         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
 843         cs4281_t *chip = snd_pcm_substream_chip(substream);
 844
 845         spin_lock_irq(&chip->reg_lock);
 846         snd_cs4281_mode(chip, dma, runtime, 0, 1);
 847         spin_unlock_irq(&chip->reg_lock);
 848         return 0;
 849 }
 850
 851 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
 852 {
 853         snd_pcm_runtime_t *runtime = substream->runtime;
 854         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
 855         cs4281_t *chip = snd_pcm_substream_chip(substream);
 856
 857         spin_lock_irq(&chip->reg_lock);
 858         snd_cs4281_mode(chip, dma, runtime, 1, 1);
 859         spin_unlock_irq(&chip->reg_lock);
 860         return 0;
 861 }
 862
 863 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
 864 {
 865         snd_pcm_runtime_t *runtime = substream->runtime;
 866         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
 867         cs4281_t *chip = snd_pcm_substream_chip(substream);
 868
 869         // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
 870         return runtime->buffer_size -
 871                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
 872 }
 873
 874 static snd_pcm_hardware_t snd_cs4281_playback =
 875 {
 876         .info =                 (SNDRV_PCM_INFO_MMAP |
 877                                  SNDRV_PCM_INFO_INTERLEAVED |
 878                                  SNDRV_PCM_INFO_MMAP_VALID |
 879                                  SNDRV_PCM_INFO_PAUSE |
 880                                  SNDRV_PCM_INFO_RESUME |
 881                                  SNDRV_PCM_INFO_SYNC_START),
 882         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 883                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 884                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 885                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 886                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 887         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 888         .rate_min =             4000,
 889         .rate_max =             48000,
 890         .channels_min =         1,
 891         .channels_max =         2,
 892         .buffer_bytes_max =     (512*1024),
 893         .period_bytes_min =     64,
 894         .period_bytes_max =     (512*1024),
 895         .periods_min =          1,
 896         .periods_max =          2,
 897         .fifo_size =            CS4281_FIFO_SIZE,
 898 };
 899
 900 static snd_pcm_hardware_t snd_cs4281_capture =
 901 {
 902         .info =                 (SNDRV_PCM_INFO_MMAP |
 903                                  SNDRV_PCM_INFO_INTERLEAVED |
 904                                  SNDRV_PCM_INFO_MMAP_VALID |
 905                                  SNDRV_PCM_INFO_PAUSE |
 906                                  SNDRV_PCM_INFO_RESUME |
 907                                  SNDRV_PCM_INFO_SYNC_START),
 908         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 909                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 910                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 911                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 912                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 913         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 914         .rate_min =             4000,
 915         .rate_max =             48000,
 916         .channels_min =         1,
 917         .channels_max =         2,
 918         .buffer_bytes_max =     (512*1024),
 919         .period_bytes_min =     64,
 920         .period_bytes_max =     (512*1024),
 921         .periods_min =          1,
 922         .periods_max =          2,
 923         .fifo_size =            CS4281_FIFO_SIZE,
 924 };
 925
 926 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
 927 {
 928         cs4281_t *chip = snd_pcm_substream_chip(substream);
 929         snd_pcm_runtime_t *runtime = substream->runtime;
 930         cs4281_dma_t *dma;
 931
 932         dma = &chip->dma[0];
 933         dma->substream = substream;
 934         dma->left_slot = 0;
 935         dma->right_slot = 1;
 936         runtime->private_data = dma;
 937         runtime->hw = snd_cs4281_playback;
 938         snd_pcm_set_sync(substream);
 939         /* should be detected from the AC'97 layer, but it seems
 940            that although CS4297A rev B reports 18-bit ADC resolution,
 941            samples are 20-bit */
 942         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 943         return 0;
 944 }
 945
 946 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
 947 {
 948         cs4281_t *chip = snd_pcm_substream_chip(substream);
 949         snd_pcm_runtime_t *runtime = substream->runtime;
 950         cs4281_dma_t *dma;
 951
 952         dma = &chip->dma[1];
 953         dma->substream = substream;
 954         dma->left_slot = 10;
 955         dma->right_slot = 11;
 956         runtime->private_data = dma;
 957         runtime->hw = snd_cs4281_capture;
 958         snd_pcm_set_sync(substream);
 959         /* should be detected from the AC'97 layer, but it seems
 960            that although CS4297A rev B reports 18-bit ADC resolution,
 961            samples are 20-bit */
 962         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 963         return 0;
 964 }
 965
 966 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
 967 {
 968         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
 969
 970         dma->substream = NULL;
 971         return 0;
 972 }
 973
 974 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
 975 {
 976         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
 977
 978         dma->substream = NULL;
 979         return 0;
 980 }
 981
 982 static snd_pcm_ops_t snd_cs4281_playback_ops = {
 983         .open =         snd_cs4281_playback_open,
 984         .close =        snd_cs4281_playback_close,
 985         .ioctl =        snd_pcm_lib_ioctl,
 986         .hw_params =    snd_cs4281_hw_params,
 987         .hw_free =      snd_cs4281_hw_free,
 988         .prepare =      snd_cs4281_playback_prepare,
 989         .trigger =      snd_cs4281_trigger,
 990         .pointer =      snd_cs4281_pointer,
 991 };
 992
 993 static snd_pcm_ops_t snd_cs4281_capture_ops = {
 994         .open =         snd_cs4281_capture_open,
 995         .close =        snd_cs4281_capture_close,
 996         .ioctl =        snd_pcm_lib_ioctl,
 997         .hw_params =    snd_cs4281_hw_params,
 998         .hw_free =      snd_cs4281_hw_free,
 999         .prepare =      snd_cs4281_capture_prepare,
1000         .trigger =      snd_cs4281_trigger,
1001         .pointer =      snd_cs4281_pointer,
1002 };
1003
1004 static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
1005 {
1006         cs4281_t *chip = pcm->private_data;
1007         chip->pcm = NULL;
1008         snd_pcm_lib_preallocate_free_for_all(pcm);
1009 }
1010
1011 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1012 {
1013         snd_pcm_t *pcm;
1014         int err;
1015
1016         if (rpcm)
1017                 *rpcm = NULL;
1018         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1019         if (err < 0)
1020                 return err;
1021
1022         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1023         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1024
1025         pcm->private_data = chip;
1026         pcm->private_free = snd_cs4281_pcm_free;
1027         pcm->info_flags = 0;
1028         strcpy(pcm->name, "CS4281");
1029         chip->pcm = pcm;
1030
1031         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1032                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1033
1034         if (rpcm)
1035                 *rpcm = pcm;
1036         return 0;
1037 }
1038
1039 /*
1040  *  Mixer section
1041  */
1042
1043 #define CS_VOL_MASK     0x1f
1044
1045 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1046 {
1047         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1048         uinfo->count             = 2;
1049         uinfo->value.integer.min = 0;
1050         uinfo->value.integer.max = CS_VOL_MASK;
1051         return 0;
1052 }
1053
1054 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1055 {
1056         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1057         int regL = (kcontrol->private_value >> 16) & 0xffff;
1058         int regR = kcontrol->private_value & 0xffff;
1059         int volL, volR;
1060
1061         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1062         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1063
1064         ucontrol->value.integer.value[0] = volL;
1065         ucontrol->value.integer.value[1] = volR;
1066         return 0;
1067 }
1068
1069 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1070 {
1071         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1072         int change = 0;
1073         int regL = (kcontrol->private_value >> 16) & 0xffff;
1074         int regR = kcontrol->private_value & 0xffff;
1075         int volL, volR;
1076
1077         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1078         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1079
1080         if (ucontrol->value.integer.value[0] != volL) {
1081                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1082                 snd_cs4281_pokeBA0(chip, regL, volL);
1083                 change = 1;
1084         }
1085         if (ucontrol->value.integer.value[0] != volL) {
1086                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1087                 snd_cs4281_pokeBA0(chip, regR, volR);
1088                 change = 1;
1089         }
1090         return change;
1091 }
1092
1093 static snd_kcontrol_new_t snd_cs4281_fm_vol =
1094 {
1095         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1096         .name = "Synth Playback Volume",
1097         .info = snd_cs4281_info_volume,
1098         .get = snd_cs4281_get_volume,
1099         .put = snd_cs4281_put_volume,
1100         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1101 };
1102
1103 static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1104 {
1105         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1106         .name = "PCM Stream Playback Volume",
1107         .info = snd_cs4281_info_volume,
1108         .get = snd_cs4281_get_volume,
1109         .put = snd_cs4281_put_volume,
1110         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1111 };
1112
1113 static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1114 {
1115         cs4281_t *chip = bus->private_data;
1116         chip->ac97_bus = NULL;
1117 }
1118
1119 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1120 {
1121         cs4281_t *chip = ac97->private_data;
1122         if (ac97->num)
1123                 chip->ac97_secondary = NULL;
1124         else
1125                 chip->ac97 = NULL;
1126 }
1127
1128 static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1129 {
1130         snd_card_t *card = chip->card;
1131         ac97_template_t ac97;
1132         int err;
1133         static ac97_bus_ops_t ops = {
1134                 .write = snd_cs4281_ac97_write,
1135                 .read = snd_cs4281_ac97_read,
1136         };
1137
1138         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1139                 return err;
1140         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1141
1142         memset(&ac97, 0, sizeof(ac97));
1143         ac97.private_data = chip;
1144         ac97.private_free = snd_cs4281_mixer_free_ac97;
1145         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1146                 return err;
1147         if (chip->dual_codec) {
1148                 ac97.num = 1;
1149                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1150                         return err;
1151         }
1152         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1153                 return err;
1154         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1155                 return err;
1156         return 0;
1157 }
1158
1159
1160 /*
1161  * proc interface
1162  */
1163
1164 static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1165                                   snd_info_buffer_t * buffer)
1166 {
1167         cs4281_t *chip = entry->private_data;
1168
1169         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1170         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1171         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1172 }
1173
1174 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1175                                 struct file *file, char __user *buf,
1176                                 unsigned long count, unsigned long pos)
1177 {
1178         long size;
1179         cs4281_t *chip = entry->private_data;
1180
1181         size = count;
1182         if (pos + size > CS4281_BA0_SIZE)
1183                 size = (long)CS4281_BA0_SIZE - pos;
1184         if (size > 0) {
1185                 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1186                         return -EFAULT;
1187         }
1188         return size;
1189 }
1190
1191 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1192                                 struct file *file, char __user *buf,
1193                                 unsigned long count, unsigned long pos)
1194 {
1195         long size;
1196         cs4281_t *chip = entry->private_data;
1197
1198         size = count;
1199         if (pos + size > CS4281_BA1_SIZE)
1200                 size = (long)CS4281_BA1_SIZE - pos;
1201         if (size > 0) {
1202                 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1203                         return -EFAULT;
1204         }
1205         return size;
1206 }
1207
1208 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1209         .read = snd_cs4281_BA0_read,
1210 };
1211
1212 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1213         .read = snd_cs4281_BA1_read,
1214 };
1215
1216 static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1217 {
1218         snd_info_entry_t *entry;
1219
1220         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1221                 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1222         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1223                 entry->content = SNDRV_INFO_CONTENT_DATA;
1224                 entry->private_data = chip;
1225                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1226                 entry->size = CS4281_BA0_SIZE;
1227         }
1228         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1229                 entry->content = SNDRV_INFO_CONTENT_DATA;
1230                 entry->private_data = chip;
1231                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1232                 entry->size = CS4281_BA1_SIZE;
1233         }
1234 }
1235
1236 /*
1237  * joystick support
1238  */
1239
1240 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1241
1242 typedef struct snd_cs4281_gameport {
1243         struct gameport info;
1244         cs4281_t *chip;
1245 } cs4281_gameport_t;
1246
1247 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1248 {
1249         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1250         cs4281_t *chip;
1251         snd_assert(gp, return);
1252         chip = gp->chip;
1253         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1254 }
1255
1256 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1257 {
1258         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1259         cs4281_t *chip;
1260         snd_assert(gp, return 0);
1261         chip = gp->chip;
1262         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1263 }
1264
1265 #ifdef COOKED_MODE
1266 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1267 {
1268         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1269         cs4281_t *chip;
1270         unsigned js1, js2, jst;
1271
1272         snd_assert(gp, return 0);
1273         chip = gp->chip;
1274
1275         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1276         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1277         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1278
1279         *buttons = (~jst >> 4) & 0x0F;
1280
1281         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1282         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1283         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1284         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1285
1286         for(jst=0;jst<4;++jst)
1287                 if(axes[jst]==0xFFFF) axes[jst] = -1;
1288         return 0;
1289 }
1290 #endif
1291
1292 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1293 {
1294         switch (mode) {
1295 #ifdef COOKED_MODE
1296         case GAMEPORT_MODE_COOKED:
1297                 return 0;
1298 #endif
1299         case GAMEPORT_MODE_RAW:
1300                 return 0;
1301         default:
1302                 return -1;
1303         }
1304         return 0;
1305 }
1306
1307 static void __devinit snd_cs4281_gameport(cs4281_t *chip)
1308 {
1309         cs4281_gameport_t *gp;
1310         gp = kmalloc(sizeof(*gp), GFP_KERNEL);
1311         if (! gp) {
1312                 snd_printk(KERN_ERR "cannot allocate gameport area\n");
1313                 return;
1314         }
1315         memset(gp, 0, sizeof(*gp));
1316         gp->info.open = snd_cs4281_gameport_open;
1317         gp->info.read = snd_cs4281_gameport_read;
1318         gp->info.trigger = snd_cs4281_gameport_trigger;
1319 #ifdef COOKED_MODE
1320         gp->info.cooked_read = snd_cs4281_gameport_cooked_read;
1321 #endif
1322         gp->chip = chip;
1323         chip->gameport = gp;
1324
1325         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1326         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1327         gameport_register_port(&gp->info);
1328 }
1329
1330 #else
1331 #define snd_cs4281_gameport(chip) /*NOP*/
1332 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1333
1334
1335 /*
1336
1337  */
1338
1339 static int snd_cs4281_free(cs4281_t *chip)
1340 {
1341 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1342         if (chip->gameport) {
1343                 gameport_unregister_port(&chip->gameport->info);
1344                 kfree(chip->gameport);
1345         }
1346 #endif
1347         if (chip->irq >= 0)
1348                 synchronize_irq(chip->irq);
1349
1350         /* Mask interrupts */
1351         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1352         /* Stop the DLL Clock logic. */
1353         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1354         /* Sound System Power Management - Turn Everything OFF */
1355         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1356         /* PCI interface - D3 state */
1357         pci_set_power_state(chip->pci, 3);
1358
1359         if (chip->irq >= 0)
1360                 free_irq(chip->irq, (void *)chip);
1361         if (chip->ba0)
1362                 iounmap((void *) chip->ba0);
1363         if (chip->ba1)
1364                 iounmap((void *) chip->ba1);
1365         pci_release_regions(chip->pci);
1366
1367         kfree(chip);
1368         return 0;
1369 }
1370
1371 static int snd_cs4281_dev_free(snd_device_t *device)
1372 {
1373         cs4281_t *chip = device->device_data;
1374         return snd_cs4281_free(chip);
1375 }
1376
1377 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1378 #ifdef CONFIG_PM
1379 static int cs4281_suspend(snd_card_t *card, unsigned int state);
1380 static int cs4281_resume(snd_card_t *card, unsigned int state);
1381 #endif
1382
1383 static int __devinit snd_cs4281_create(snd_card_t * card,
1384                                        struct pci_dev *pci,
1385                                        cs4281_t ** rchip,
1386                                        int dual_codec)
1387 {
1388         cs4281_t *chip;
1389         unsigned int tmp;
1390         int err;
1391         static snd_device_ops_t ops = {
1392                 .dev_free =     snd_cs4281_dev_free,
1393         };
1394
1395         *rchip = NULL;
1396         if ((err = pci_enable_device(pci)) < 0)
1397                 return err;
1398         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1399         if (chip == NULL)
1400                 return -ENOMEM;
1401         spin_lock_init(&chip->reg_lock);
1402         chip->card = card;
1403         chip->pci = pci;
1404         chip->irq = -1;
1405         pci_set_master(pci);
1406         if (dual_codec < 0 || dual_codec > 3) {
1407                 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1408                 dual_codec = 0;
1409         }
1410         chip->dual_codec = dual_codec;
1411
1412         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1413                 kfree(chip);
1414                 return err;
1415         }
1416         chip->ba0_addr = pci_resource_start(pci, 0);
1417         chip->ba1_addr = pci_resource_start(pci, 1);
1418
1419         if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1420                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1421                 snd_cs4281_free(chip);
1422                 return -ENOMEM;
1423         }
1424         chip->irq = pci->irq;
1425
1426         chip->ba0 = (unsigned long) ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1427         chip->ba1 = (unsigned long) ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1428         if (!chip->ba0 || !chip->ba1) {
1429                 snd_cs4281_free(chip);
1430                 return -ENOMEM;
1431         }
1432
1433         tmp = snd_cs4281_chip_init(chip);
1434         if (tmp) {
1435                 snd_cs4281_free(chip);
1436                 return tmp;
1437         }
1438
1439         snd_cs4281_proc_init(chip);
1440
1441         snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1442
1443         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1444                 snd_cs4281_free(chip);
1445                 return err;
1446         }
1447
1448         snd_card_set_dev(card, &pci->dev);
1449
1450         *rchip = chip;
1451         return 0;
1452 }
1453
1454 static int snd_cs4281_chip_init(cs4281_t *chip)
1455 {
1456         unsigned int tmp;
1457         int timeout;
1458         int retry_count = 2;
1459
1460       __retry:
1461         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1462         if (tmp != BA0_CFLR_DEFAULT) {
1463                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1464                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1465                 if (tmp != BA0_CFLR_DEFAULT) {
1466                         snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1467                         return -EIO;
1468                 }
1469         }
1470
1471         /* Set the 'Configuration Write Protect' register
1472          * to 4281h.  Allows vendor-defined configuration
1473          * space between 0e4h and 0ffh to be written. */
1474         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1475
1476         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1477                 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1478                 return -EIO;
1479         }
1480         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1481                 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1482                 return -EIO;
1483         }
1484
1485         /* Sound System Power Management */
1486         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1487                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1488                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1489
1490         /* Serial Port Power Management */
1491         /* Blast the clock control register to zero so that the
1492          * PLL starts out in a known state, and blast the master serial
1493          * port control register to zero so that the serial ports also
1494          * start out in a known state. */
1495         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1496         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1497
1498         /* Make ESYN go to zero to turn off
1499          * the Sync pulse on the AC97 link. */
1500         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1501         udelay(50);
1502
1503         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1504          *  spec) and then drive it high.  This is done for non AC97 modes since
1505          *  there might be logic external to the CS4281 that uses the ARST# line
1506          *  for a reset. */
1507         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1508         udelay(50);
1509         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1510         snd_cs4281_delay(50000);
1511
1512         if (chip->dual_codec)
1513                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1514
1515         /*
1516          *  Set the serial port timing configuration.
1517          */
1518         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1519                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1520                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1521
1522         /*
1523          *  Start the DLL Clock logic.
1524          */
1525         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1526         snd_cs4281_delay(50000);
1527         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1528
1529         /*
1530          * Wait for the DLL ready signal from the clock logic.
1531          */
1532         timeout = HZ;
1533         do {
1534                 /*
1535                  *  Read the AC97 status register to see if we've seen a CODEC
1536                  *  signal from the AC97 codec.
1537                  */
1538                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1539                         goto __ok0;
1540                 snd_cs4281_delay_long();
1541         } while (timeout-- > 0);
1542
1543         snd_printk(KERN_ERR "DLLRDY not seen\n");
1544         return -EIO;
1545
1546       __ok0:
1547
1548         /*
1549          *  The first thing we do here is to enable sync generation.  As soon
1550          *  as we start receiving bit clock, we'll start producing the SYNC
1551          *  signal.
1552          */
1553         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1554
1555         /*
1556          * Wait for the codec ready signal from the AC97 codec.
1557          */
1558         timeout = HZ;
1559         do {
1560                 /*
1561                  *  Read the AC97 status register to see if we've seen a CODEC
1562                  *  signal from the AC97 codec.
1563                  */
1564                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1565                         goto __ok1;
1566                 snd_cs4281_delay_long();
1567         } while (timeout-- > 0);
1568
1569         snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1570         return -EIO;
1571
1572       __ok1:
1573         if (chip->dual_codec) {
1574                 timeout = HZ;
1575                 do {
1576                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1577                                 goto __codec2_ok;
1578                         snd_cs4281_delay_long();
1579                 } while (timeout-- > 0);
1580                 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1581                 chip->dual_codec = 0;
1582         __codec2_ok: ;
1583         }
1584
1585         /*
1586          *  Assert the valid frame signal so that we can start sending commands
1587          *  to the AC97 codec.
1588          */
1589
1590         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1591
1592         /*
1593          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1594          *  the codec is pumping ADC data across the AC-link.
1595          */
1596
1597         timeout = HZ;
1598         do {
1599                 /*
1600                  *  Read the input slot valid register and see if input slots 3
1601                  *  4 are valid yet.
1602                  */
1603                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1604                         goto __ok2;
1605                 snd_cs4281_delay_long();
1606         } while (timeout-- > 0);
1607
1608         if (--retry_count > 0)
1609                 goto __retry;
1610         snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1611         return -EIO;
1612
1613       __ok2:
1614
1615         /*
1616          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1617          *  commense the transfer of digital audio data to the AC97 codec.
1618          */
1619         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1620
1621         /*
1622          *  Initialize DMA structures
1623          */
1624         for (tmp = 0; tmp < 4; tmp++) {
1625                 cs4281_dma_t *dma = &chip->dma[tmp];
1626                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1627                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1628                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1629                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1630                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1631                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1632                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1633                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1634                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1635                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1636                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1637                                    BA0_FCR_LS(31) |
1638                                    BA0_FCR_RS(31) |
1639                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1640                                    BA0_FCR_OF(dma->fifo_offset));
1641         }
1642
1643         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1644         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1645         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1646         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1647
1648         /* Activate wave playback FIFO for FM playback */
1649         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1650                               BA0_FCR_RS(1) |
1651                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1652                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1653         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1654         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1655                                             (chip->src_right_play_slot << 8) |
1656                                             (chip->src_left_rec_slot << 16) |
1657                                             (chip->src_right_rec_slot << 24));
1658
1659         /* Initialize digital volume */
1660         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1661         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1662
1663         /* Enable IRQs */
1664         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1665         /* Unmask interrupts */
1666         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1667                                         BA0_HISR_MIDI |
1668                                         BA0_HISR_DMAI |
1669                                         BA0_HISR_DMA(0) |
1670                                         BA0_HISR_DMA(1) |
1671                                         BA0_HISR_DMA(2) |
1672                                         BA0_HISR_DMA(3)));
1673         synchronize_irq(chip->irq);
1674
1675         return 0;
1676 }
1677
1678 /*
1679  *  MIDI section
1680  */
1681
1682 static void snd_cs4281_midi_reset(cs4281_t *chip)
1683 {
1684         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1685         udelay(100);
1686         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1687 }
1688
1689 static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1690 {
1691         cs4281_t *chip = substream->rmidi->private_data;
1692
1693         spin_lock_irq(&chip->reg_lock);
1694         chip->midcr |= BA0_MIDCR_RXE;
1695         chip->midi_input = substream;
1696         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1697                 snd_cs4281_midi_reset(chip);
1698         } else {
1699                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1700         }
1701         spin_unlock_irq(&chip->reg_lock);
1702         return 0;
1703 }
1704
1705 static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1706 {
1707         cs4281_t *chip = substream->rmidi->private_data;
1708
1709         spin_lock_irq(&chip->reg_lock);
1710         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1711         chip->midi_input = NULL;
1712         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1713                 snd_cs4281_midi_reset(chip);
1714         } else {
1715                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1716         }
1717         chip->uartm &= ~CS4281_MODE_INPUT;
1718         spin_unlock_irq(&chip->reg_lock);
1719         return 0;
1720 }
1721
1722 static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1723 {
1724         cs4281_t *chip = substream->rmidi->private_data;
1725
1726         spin_lock_irq(&chip->reg_lock);
1727         chip->uartm |= CS4281_MODE_OUTPUT;
1728         chip->midcr |= BA0_MIDCR_TXE;
1729         chip->midi_output = substream;
1730         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1731                 snd_cs4281_midi_reset(chip);
1732         } else {
1733                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1734         }
1735         spin_unlock_irq(&chip->reg_lock);
1736         return 0;
1737 }
1738
1739 static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1740 {
1741         cs4281_t *chip = substream->rmidi->private_data;
1742
1743         spin_lock_irq(&chip->reg_lock);
1744         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1745         chip->midi_output = NULL;
1746         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1747                 snd_cs4281_midi_reset(chip);
1748         } else {
1749                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1750         }
1751         chip->uartm &= ~CS4281_MODE_OUTPUT;
1752         spin_unlock_irq(&chip->reg_lock);
1753         return 0;
1754 }
1755
1756 static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1757 {
1758         unsigned long flags;
1759         cs4281_t *chip = substream->rmidi->private_data;
1760
1761         spin_lock_irqsave(&chip->reg_lock, flags);
1762         if (up) {
1763                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1764                         chip->midcr |= BA0_MIDCR_RIE;
1765                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1766                 }
1767         } else {
1768                 if (chip->midcr & BA0_MIDCR_RIE) {
1769                         chip->midcr &= ~BA0_MIDCR_RIE;
1770                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1771                 }
1772         }
1773         spin_unlock_irqrestore(&chip->reg_lock, flags);
1774 }
1775
1776 static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1777 {
1778         unsigned long flags;
1779         cs4281_t *chip = substream->rmidi->private_data;
1780         unsigned char byte;
1781
1782         spin_lock_irqsave(&chip->reg_lock, flags);
1783         if (up) {
1784                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1785                         chip->midcr |= BA0_MIDCR_TIE;
1786                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1787                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1788                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1789                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1790                                         chip->midcr &= ~BA0_MIDCR_TIE;
1791                                 } else {
1792                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1793                                 }
1794                         }
1795                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1796                 }
1797         } else {
1798                 if (chip->midcr & BA0_MIDCR_TIE) {
1799                         chip->midcr &= ~BA0_MIDCR_TIE;
1800                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1801                 }
1802         }
1803         spin_unlock_irqrestore(&chip->reg_lock, flags);
1804 }
1805
1806 static snd_rawmidi_ops_t snd_cs4281_midi_output =
1807 {
1808         .open =         snd_cs4281_midi_output_open,
1809         .close =        snd_cs4281_midi_output_close,
1810         .trigger =      snd_cs4281_midi_output_trigger,
1811 };
1812
1813 static snd_rawmidi_ops_t snd_cs4281_midi_input =
1814 {
1815         .open =         snd_cs4281_midi_input_open,
1816         .close =        snd_cs4281_midi_input_close,
1817         .trigger =      snd_cs4281_midi_input_trigger,
1818 };
1819
1820 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1821 {
1822         snd_rawmidi_t *rmidi;
1823         int err;
1824
1825         if (rrawmidi)
1826                 *rrawmidi = NULL;
1827         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1828                 return err;
1829         strcpy(rmidi->name, "CS4281");
1830         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1831         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1832         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1833         rmidi->private_data = chip;
1834         chip->rmidi = rmidi;
1835         if (rrawmidi)
1836                 *rrawmidi = rmidi;
1837         return 0;
1838 }
1839
1840 /*
1841  *  Interrupt handler
1842  */
1843
1844 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1845 {
1846         cs4281_t *chip = dev_id;
1847         unsigned int status, dma, val;
1848         cs4281_dma_t *cdma;
1849
1850         if (chip == NULL)
1851                 return IRQ_NONE;
1852         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1853         if ((status & 0x7fffffff) == 0) {
1854                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1855                 return IRQ_NONE;
1856         }
1857
1858         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1859                 for (dma = 0; dma < 4; dma++)
1860                         if (status & BA0_HISR_DMA(dma)) {
1861                                 cdma = &chip->dma[dma];
1862                                 spin_lock(&chip->reg_lock);
1863                                 /* ack DMA IRQ */
1864                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1865                                 /* workaround, sometimes CS4281 acknowledges */
1866                                 /* end or middle transfer position twice */
1867                                 cdma->frag++;
1868                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1869                                         cdma->frag--;
1870                                         chip->spurious_dhtc_irq++;
1871                                         spin_unlock(&chip->reg_lock);
1872                                         continue;
1873                                 }
1874                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1875                                         cdma->frag--;
1876                                         chip->spurious_dtc_irq++;
1877                                         spin_unlock(&chip->reg_lock);
1878                                         continue;
1879                                 }
1880                                 spin_unlock(&chip->reg_lock);
1881                                 snd_pcm_period_elapsed(cdma->substream);
1882                         }
1883         }
1884
1885         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1886                 unsigned char c;
1887
1888                 spin_lock(&chip->reg_lock);
1889                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1890                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1891                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1892                                 continue;
1893                         spin_unlock(&chip->reg_lock);
1894                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1895                         spin_lock(&chip->reg_lock);
1896                 }
1897                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1898                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1899                                 break;
1900                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1901                                 chip->midcr &= ~BA0_MIDCR_TIE;
1902                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1903                                 break;
1904                         }
1905                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1906                 }
1907                 spin_unlock(&chip->reg_lock);
1908         }
1909
1910         /* EOI to the PCI part... reenables interrupts */
1911         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1912
1913         return IRQ_HANDLED;
1914 }
1915
1916
1917 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1918                                       const struct pci_device_id *pci_id)
1919 {
1920         static int dev;
1921         snd_card_t *card;
1922         cs4281_t *chip;
1923         opl3_t *opl3;
1924         int err;
1925
1926         if (dev >= SNDRV_CARDS)
1927                 return -ENODEV;
1928         if (!enable[dev]) {
1929                 dev++;
1930                 return -ENOENT;
1931         }
1932
1933         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1934         if (card == NULL)
1935                 return -ENOMEM;
1936
1937         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1938                 snd_card_free(card);
1939                 return err;
1940         }
1941
1942         if ((err = snd_cs4281_mixer(chip)) < 0) {
1943                 snd_card_free(card);
1944                 return err;
1945         }
1946         if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1947                 snd_card_free(card);
1948                 return err;
1949         }
1950         if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1951                 snd_card_free(card);
1952                 return err;
1953         }
1954         if ((err = snd_opl3_create(card,
1955                                    (chip->ba0 + BA0_B0AP) >> 2,
1956                                    (chip->ba0 + BA0_B1AP) >> 2,
1957                                    OPL3_HW_OPL3_CS4281, 1, &opl3)) < 0) {
1958                 snd_card_free(card);
1959                 return err;
1960         }
1961         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1962                 snd_card_free(card);
1963                 return err;
1964         }
1965         snd_cs4281_gameport(chip);
1966         strcpy(card->driver, "CS4281");
1967         strcpy(card->shortname, "Cirrus Logic CS4281");
1968         sprintf(card->longname, "%s at 0x%lx, irq %d",
1969                 card->shortname,
1970                 chip->ba0_addr,
1971                 chip->irq);
1972
1973         if ((err = snd_card_register(card)) < 0) {
1974                 snd_card_free(card);
1975                 return err;
1976         }
1977
1978         pci_set_drvdata(pci, card);
1979         dev++;
1980         return 0;
1981 }
1982
1983 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
1984 {
1985         snd_card_free(pci_get_drvdata(pci));
1986         pci_set_drvdata(pci, NULL);
1987 }
1988
1989 /*
1990  * Power Management
1991  */
1992 #ifdef CONFIG_PM
1993
1994 static int saved_regs[SUSPEND_REGISTERS] = {
1995         BA0_JSCTL,
1996         BA0_GPIOR,
1997         BA0_SSCR,
1998         BA0_MIDCR,
1999         BA0_SRCSA,
2000         BA0_PASR,
2001         BA0_CASR,
2002         BA0_DACSR,
2003         BA0_ADCSR,
2004         BA0_FMLVC,
2005         BA0_FMRVC,
2006         BA0_PPLVC,
2007         BA0_PPRVC,
2008 };
2009
2010 #define CLKCR1_CKRA                             0x00010000L
2011
2012 static int cs4281_suspend(snd_card_t *card, unsigned int state)
2013 {
2014         cs4281_t *chip = card->pm_private_data;
2015         u32 ulCLK;
2016         unsigned int i;
2017
2018         snd_pcm_suspend_all(chip->pcm);
2019
2020         if (chip->ac97)
2021                 snd_ac97_suspend(chip->ac97);
2022         if (chip->ac97_secondary)
2023                 snd_ac97_suspend(chip->ac97_secondary);
2024
2025         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2026         ulCLK |= CLKCR1_CKRA;
2027         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2028
2029         /* Disable interrupts. */
2030         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2031
2032         /* remember the status registers */
2033         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2034                 if (saved_regs[i])
2035                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2036
2037         /* Turn off the serial ports. */
2038         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2039
2040         /* Power off FM, Joystick, AC link, */
2041         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2042
2043         /* DLL off. */
2044         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2045
2046         /* AC link off. */
2047         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2048
2049         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2050         ulCLK &= ~CLKCR1_CKRA;
2051         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2052
2053         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2054         return 0;
2055 }
2056
2057 static int cs4281_resume(snd_card_t *card, unsigned int state)
2058 {
2059         cs4281_t *chip = card->pm_private_data;
2060         unsigned int i;
2061         u32 ulCLK;
2062
2063         pci_enable_device(chip->pci);
2064
2065         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2066         ulCLK |= CLKCR1_CKRA;
2067         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2068
2069         snd_cs4281_chip_init(chip);
2070
2071         /* restore the status registers */
2072         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2073                 if (saved_regs[i])
2074                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2075
2076         if (chip->ac97)
2077                 snd_ac97_resume(chip->ac97);
2078         if (chip->ac97_secondary)
2079                 snd_ac97_resume(chip->ac97_secondary);
2080
2081         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2082         ulCLK &= ~CLKCR1_CKRA;
2083         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2084
2085         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2086         return 0;
2087 }
2088 #endif /* CONFIG_PM */
2089
2090 static struct pci_driver driver = {
2091         .name = "CS4281",
2092         .id_table = snd_cs4281_ids,
2093         .probe = snd_cs4281_probe,
2094         .remove = __devexit_p(snd_cs4281_remove),
2095         SND_PCI_PM_CALLBACKS
2096 };
2097
2098 static int __init alsa_card_cs4281_init(void)
2099 {
2100         return pci_module_init(&driver);
2101 }
2102
2103 static void __exit alsa_card_cs4281_exit(void)
2104 {
2105         pci_unregister_driver(&driver);
2106 }
2107
2108 module_init(alsa_card_cs4281_init)
2109 module_exit(alsa_card_cs4281_exit)