sound/pci/cs4281.c

   1 /*
   2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <sound/core.h>
  31 #include <sound/control.h>
  32 #include <sound/pcm.h>
  33 #include <sound/rawmidi.h>
  34 #include <sound/ac97_codec.h>
  35 #include <sound/opl3.h>
  36 #define SNDRV_GET_ID
  37 #include <sound/initval.h>
  38
  39
  40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
  42 MODULE_LICENSE("GPL");
  43 MODULE_CLASSES("{sound}");
  44 MODULE_DEVICES("{{Cirrus Logic,CS4281}}");
  45
  46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  49 static int dual_codec[SNDRV_CARDS];     /* dual codec */
  50
  51 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  52 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  53 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  54 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
  55 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  56 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  57 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  58 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  59 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  60 MODULE_PARM(dual_codec, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  61 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  62 MODULE_PARM_SYNTAX(dual_codec, SNDRV_ENABLED ",allows:{{0,3}}");
  63
  64 /*
  65  *
  66  */
  67
  68 #ifndef PCI_VENDOR_ID_CIRRUS
  69 #define PCI_VENDOR_ID_CIRRUS            0x1013
  70 #endif
  71 #ifndef PCI_DEVICE_ID_CIRRUS_4281
  72 #define PCI_DEVICE_ID_CIRRUS_4281       0x6005
  73 #endif
  74
  75 /*
  76  *  Direct registers
  77  */
  78
  79 #define CS4281_BA0_SIZE         0x1000
  80 #define CS4281_BA1_SIZE         0x10000
  81
  82 /*
  83  *  BA0 registers
  84  */
  85 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
  86 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
  87 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
  88 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
  89 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
  90 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
  91 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
  92 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
  93 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
  94 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
  95 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
  96 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
  97 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
  98
  99 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
 100 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
 101 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
 102 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
 103
 104 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
 105                                         /* Use same contants as for BA0_HISR */
 106
 107 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
 108
 109 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
 110 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
 111 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
 112 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
 113
 114 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
 115 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
 116 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
 117 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
 118 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
 119 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
 120
 121 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
 122 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
 123 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
 124 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
 125 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
 126 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
 127 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
 128 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
 129 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
 130 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
 131 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
 132 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
 133 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
 134 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
 135 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
 136 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
 137 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
 138 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
 139 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
 140 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
 141 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
 142 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
 143 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
 144 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
 145
 146 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
 147 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
 148 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
 149 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
 150 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
 151 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
 152 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
 153 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
 154 #define BA0_DMR_MONO            (1<<17) /* Mono */
 155 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
 156 #define BA0_DMR_TYPE_DEMAND     (0<<6)
 157 #define BA0_DMR_TYPE_SINGLE     (1<<6)
 158 #define BA0_DMR_TYPE_BLOCK      (2<<6)
 159 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
 160 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
 161 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
 162 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
 163 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
 164 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
 165
 166 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
 167 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
 168 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
 169
 170 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
 171 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
 172 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
 173 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
 174
 175 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
 176 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
 177 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
 178 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
 179 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
 180 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
 181 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
 182
 183 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
 184 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
 185 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
 186 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
 187
 188 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
 189 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
 190 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
 191 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
 192 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
 193 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
 194 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
 195 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
 196 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
 197
 198 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
 199 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
 200 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
 201 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
 202
 203 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
 204 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
 205 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
 206 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
 207 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
 208 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
 209 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
 210 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
 211
 212 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
 213 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
 214 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
 215 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
 216
 217 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
 218 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
 219 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
 220 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
 221 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
 222 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
 223 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
 224 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
 225 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
 226 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
 227
 228 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
 229 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
 230 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
 231 #define BA0_TMS                 0x03f8  /* Test Register */
 232 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
 233
 234 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
 235 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
 236 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
 237 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
 238 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
 239 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
 240 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
 241
 242 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
 243 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
 244
 245 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
 246 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
 247 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
 248 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
 249 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
 250 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
 251 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
 252 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
 253 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
 254 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
 255 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
 256 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
 257 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
 258
 259 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
 260 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
 261 #define BA0_SERC1_AC97          (1<<1)
 262 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
 263
 264 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
 265 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
 266 #define BA0_SERC2_AC97          (1<<1)
 267 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
 268
 269 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
 270
 271 #define BA0_ACCTL               0x0460  /* AC'97 Control */
 272 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
 273 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
 274 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
 275 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
 276 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
 277
 278 #define BA0_ACSTS               0x0464  /* AC'97 Status */
 279 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
 280 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
 281
 282 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
 283 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
 284
 285 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
 286 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
 287
 288 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
 289 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
 290
 291 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
 292 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
 293 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
 294 #define BA0_JSCTL               0x0484  /* Joystick control */
 295 #define BA0_JSC1                0x0488  /* Joystick control */
 296 #define BA0_JSC2                0x048c  /* Joystick control */
 297 #define BA0_JSIO                0x04a0
 298
 299 #define BA0_MIDCR               0x0490  /* MIDI Control */
 300 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
 301 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
 302 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
 303 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
 304 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
 305 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
 306
 307 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
 308
 309 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
 310 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
 311 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
 312 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
 313 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
 314
 315 #define BA0_MIDWP               0x0498  /* MIDI Write */
 316 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
 317
 318 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
 319 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
 320
 321 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
 322 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
 323
 324 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
 325 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
 326 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
 327 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
 328 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
 329 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
 330 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
 331 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
 332 #define BA0_FMDP                0x0734  /* FM Data Port */
 333 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
 334 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
 335
 336 #define BA0_SSPM                0x0740  /* Sound System Power Management */
 337 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
 338 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
 339 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
 340 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
 341 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
 342 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
 343
 344 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
 345 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
 346
 347 #define BA0_SSCR                0x074c  /* Sound System Control Register */
 348 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
 349 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
 350 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
 351 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
 352 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
 353 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
 354 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
 355 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
 356 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
 357
 358 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
 359 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
 360 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
 361 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
 362 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
 363 #define BA0_PASR                0x0768  /* playback sample rate */
 364 #define BA0_CASR                0x076C  /* capture sample rate */
 365
 366 /* Source Slot Numbers - Playback */
 367 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
 368 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
 369 #define SRCSLOT_PHONE_LINE_1_DAC                2
 370 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
 371 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
 372 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
 373 #define SRCSLOT_LFE_PCM_PLAYBACK                6
 374 #define SRCSLOT_PHONE_LINE_2_DAC                7
 375 #define SRCSLOT_HEADSET_DAC                     8
 376 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
 377 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
 378
 379 /* Source Slot Numbers - Capture */
 380 #define SRCSLOT_LEFT_PCM_RECORD                 10
 381 #define SRCSLOT_RIGHT_PCM_RECORD                11
 382 #define SRCSLOT_PHONE_LINE_1_ADC                12
 383 #define SRCSLOT_MIC_ADC                         13
 384 #define SRCSLOT_PHONE_LINE_2_ADC                17
 385 #define SRCSLOT_HEADSET_ADC                     18
 386 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
 387 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
 388 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
 389 #define SRCSLOT_SECONDARY_MIC_ADC               23
 390 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
 391 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
 392
 393 /* Source Slot Numbers - Others */
 394 #define SRCSLOT_POWER_DOWN                      31
 395
 396 /* MIDI modes */
 397 #define CS4281_MODE_OUTPUT              (1<<0)
 398 #define CS4281_MODE_INPUT               (1<<1)
 399
 400 /* joystick bits */
 401 /* Bits for JSPT */
 402 #define JSPT_CAX                                0x00000001
 403 #define JSPT_CAY                                0x00000002
 404 #define JSPT_CBX                                0x00000004
 405 #define JSPT_CBY                                0x00000008
 406 #define JSPT_BA1                                0x00000010
 407 #define JSPT_BA2                                0x00000020
 408 #define JSPT_BB1                                0x00000040
 409 #define JSPT_BB2                                0x00000080
 410
 411 /* Bits for JSCTL */
 412 #define JSCTL_SP_MASK                           0x00000003
 413 #define JSCTL_SP_SLOW                           0x00000000
 414 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
 415 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
 416 #define JSCTL_SP_FAST                           0x00000003
 417 #define JSCTL_ARE                               0x00000004
 418
 419 /* Data register pairs masks */
 420 #define JSC1_Y1V_MASK                           0x0000FFFF
 421 #define JSC1_X1V_MASK                           0xFFFF0000
 422 #define JSC1_Y1V_SHIFT                          0
 423 #define JSC1_X1V_SHIFT                          16
 424 #define JSC2_Y2V_MASK                           0x0000FFFF
 425 #define JSC2_X2V_MASK                           0xFFFF0000
 426 #define JSC2_Y2V_SHIFT                          0
 427 #define JSC2_X2V_SHIFT                          16
 428
 429 /* JS GPIO */
 430 #define JSIO_DAX                                0x00000001
 431 #define JSIO_DAY                                0x00000002
 432 #define JSIO_DBX                                0x00000004
 433 #define JSIO_DBY                                0x00000008
 434 #define JSIO_AXOE                               0x00000010
 435 #define JSIO_AYOE                               0x00000020
 436 #define JSIO_BXOE                               0x00000040
 437 #define JSIO_BYOE                               0x00000080
 438
 439 /*
 440  *
 441  */
 442
 443 #define chip_t cs4281_t
 444
 445 typedef struct snd_cs4281 cs4281_t;
 446 typedef struct snd_cs4281_dma cs4281_dma_t;
 447
 448 struct snd_cs4281_dma {
 449         snd_pcm_substream_t *substream;
 450         unsigned int regDBA;            /* offset to DBA register */
 451         unsigned int regDCA;            /* offset to DCA register */
 452         unsigned int regDBC;            /* offset to DBC register */
 453         unsigned int regDCC;            /* offset to DCC register */
 454         unsigned int regDMR;            /* offset to DMR register */
 455         unsigned int regDCR;            /* offset to DCR register */
 456         unsigned int regHDSR;           /* offset to HDSR register */
 457         unsigned int regFCR;            /* offset to FCR register */
 458         unsigned int regFSIC;           /* offset to FSIC register */
 459         unsigned int valDMR;            /* DMA mode */
 460         unsigned int valDCR;            /* DMA command */
 461         unsigned int valFCR;            /* FIFO control */
 462         unsigned int fifo_offset;       /* FIFO offset within BA1 */
 463         unsigned char left_slot;        /* FIFO left slot */
 464         unsigned char right_slot;       /* FIFO right slot */
 465         int frag;                       /* period number */
 466 };
 467
 468 #define SUSPEND_REGISTERS       20
 469
 470 struct snd_cs4281 {
 471         int irq;
 472
 473         unsigned long ba0;              /* virtual (accessible) address */
 474         unsigned long ba1;              /* virtual (accessible) address */
 475         unsigned long ba0_addr;
 476         unsigned long ba1_addr;
 477         struct resource *ba0_res;
 478         struct resource *ba1_res;
 479
 480         int dual_codec;
 481
 482         ac97_bus_t *ac97_bus;
 483         ac97_t *ac97;
 484         ac97_t *ac97_secondary;
 485
 486         struct pci_dev *pci;
 487         snd_card_t *card;
 488         snd_pcm_t *pcm;
 489         snd_rawmidi_t *rmidi;
 490         snd_rawmidi_substream_t *midi_input;
 491         snd_rawmidi_substream_t *midi_output;
 492
 493         cs4281_dma_t dma[4];
 494
 495         unsigned char src_left_play_slot;
 496         unsigned char src_right_play_slot;
 497         unsigned char src_left_rec_slot;
 498         unsigned char src_right_rec_slot;
 499
 500         unsigned int spurious_dhtc_irq;
 501         unsigned int spurious_dtc_irq;
 502
 503         spinlock_t reg_lock;
 504         unsigned int midcr;
 505         unsigned int uartm;
 506
 507         struct snd_cs4281_gameport *gameport;
 508
 509 #ifdef CONFIG_PM
 510         u32 suspend_regs[SUSPEND_REGISTERS];
 511 #endif
 512
 513 };
 514
 515 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 516
 517 static struct pci_device_id snd_cs4281_ids[] = {
 518         { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* CS4281 */
 519         { 0, }
 520 };
 521
 522 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
 523
 524 /*
 525  *  constants
 526  */
 527
 528 #define CS4281_FIFO_SIZE        32
 529
 530 /*
 531  *  common I/O routines
 532  */
 533
 534 static void snd_cs4281_delay(unsigned int delay)
 535 {
 536         if (delay > 999) {
 537                 unsigned long end_time;
 538                 delay = (delay * HZ) / 1000000;
 539                 if (delay < 1)
 540                         delay = 1;
 541                 end_time = jiffies + delay;
 542                 do {
 543                         set_current_state(TASK_UNINTERRUPTIBLE);
 544                         schedule_timeout(1);
 545                 } while (time_after_eq(end_time, jiffies));
 546         } else {
 547                 udelay(delay);
 548         }
 549 }
 550
 551 inline static void snd_cs4281_delay_long(void)
 552 {
 553         set_current_state(TASK_UNINTERRUPTIBLE);
 554         schedule_timeout(1);
 555 }
 556
 557 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
 558 {
 559         writel(val, chip->ba0 + offset);
 560 }
 561
 562 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
 563 {
 564         return readl(chip->ba0 + offset);
 565 }
 566
 567 static void snd_cs4281_ac97_write(ac97_t *ac97,
 568                                   unsigned short reg, unsigned short val)
 569 {
 570         /*
 571          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 572          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 573          *  3. Write ACCTL = Control Register = 460h for initiating the write
 574          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 575          *  5. if DCV not cleared, break and return error
 576          */
 577         cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return);
 578         int count;
 579
 580         /*
 581          *  Setup the AC97 control registers on the CS461x to send the
 582          *  appropriate command to the AC97 to perform the read.
 583          *  ACCAD = Command Address Register = 46Ch
 584          *  ACCDA = Command Data Register = 470h
 585          *  ACCTL = Control Register = 460h
 586          *  set DCV - will clear when process completed
 587          *  reset CRW - Write command
 588          *  set VFRM - valid frame enabled
 589          *  set ESYN - ASYNC generation enabled
 590          *  set RSTN - ARST# inactive, AC97 codec not reset
 591          */
 592         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 593         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
 594         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
 595                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
 596         for (count = 0; count < 2000; count++) {
 597                 /*
 598                  *  First, we want to wait for a short time.
 599                  */
 600                 udelay(10);
 601                 /*
 602                  *  Now, check to see if the write has completed.
 603                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 604                  */
 605                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
 606                         return;
 607                 }
 608         }
 609         snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
 610 }
 611
 612 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
 613                                            unsigned short reg)
 614 {
 615         cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return -ENXIO);
 616         int count;
 617         unsigned short result;
 618         // FIXME: volatile is necessary in the following due to a bug of
 619         // some gcc versions
 620         volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
 621
 622         /*
 623          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 624          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 625          *  3. Write ACCTL = Control Register = 460h for initiating the write
 626          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 627          *  5. if DCV not cleared, break and return error
 628          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 629          */
 630
 631         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 632
 633         /*
 634          *  Setup the AC97 control registers on the CS461x to send the
 635          *  appropriate command to the AC97 to perform the read.
 636          *  ACCAD = Command Address Register = 46Ch
 637          *  ACCDA = Command Data Register = 470h
 638          *  ACCTL = Control Register = 460h
 639          *  set DCV - will clear when process completed
 640          *  set CRW - Read command
 641          *  set VFRM - valid frame enabled
 642          *  set ESYN - ASYNC generation enabled
 643          *  set RSTN - ARST# inactive, AC97 codec not reset
 644          */
 645
 646         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 647         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
 648         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
 649                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
 650                            (ac97_num ? BA0_ACCTL_TC : 0));
 651
 652
 653         /*
 654          *  Wait for the read to occur.
 655          */
 656         for (count = 0; count < 500; count++) {
 657                 /*
 658                  *  First, we want to wait for a short time.
 659                  */
 660                 udelay(10);
 661                 /*
 662                  *  Now, check to see if the read has completed.
 663                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 664                  */
 665                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
 666                         goto __ok1;
 667         }
 668
 669         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 670         result = 0xffff;
 671         goto __end;
 672
 673       __ok1:
 674         /*
 675          *  Wait for the valid status bit to go active.
 676          */
 677         for (count = 0; count < 100; count++) {
 678                 /*
 679                  *  Read the AC97 status register.
 680                  *  ACSTS = Status Register = 464h
 681                  *  VSTS - Valid Status
 682                  */
 683                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
 684                         goto __ok2;
 685                 udelay(10);
 686         }
 687
 688         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
 689         result = 0xffff;
 690         goto __end;
 691
 692       __ok2:
 693         /*
 694          *  Read the data returned from the AC97 register.
 695          *  ACSDA = Status Data Register = 474h
 696          */
 697         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 698
 699       __end:
 700         return result;
 701 }
 702
 703 /*
 704  *  PCM part
 705  */
 706
 707 static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
 708 {
 709         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
 710         cs4281_t *chip = snd_pcm_substream_chip(substream);
 711         unsigned long flags;
 712
 713         spin_lock_irqsave(&chip->reg_lock, flags);
 714         switch (cmd) {
 715         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 716                 dma->valDCR |= BA0_DCR_MSK;
 717                 dma->valFCR |= BA0_FCR_FEN;
 718                 break;
 719         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 720                 dma->valDCR &= ~BA0_DCR_MSK;
 721                 dma->valFCR &= ~BA0_FCR_FEN;
 722                 break;
 723         case SNDRV_PCM_TRIGGER_START:
 724         case SNDRV_PCM_TRIGGER_RESUME:
 725                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
 726                 dma->valDMR |= BA0_DMR_DMA;
 727                 dma->valDCR &= ~BA0_DCR_MSK;
 728                 dma->valFCR |= BA0_FCR_FEN;
 729                 break;
 730         case SNDRV_PCM_TRIGGER_STOP:
 731         case SNDRV_PCM_TRIGGER_SUSPEND:
 732                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
 733                 dma->valDCR |= BA0_DCR_MSK;
 734                 dma->valFCR &= ~BA0_FCR_FEN;
 735                 /* Leave wave playback FIFO enabled for FM */
 736                 if (dma->regFCR != BA0_FCR0)
 737                         dma->valFCR &= ~BA0_FCR_FEN;
 738                 break;
 739         default:
 740                 spin_unlock_irqrestore(&chip->reg_lock, flags);
 741                 return -EINVAL;
 742         }
 743         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
 744         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
 745         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
 746         spin_unlock_irqrestore(&chip->reg_lock, flags);
 747         return 0;
 748 }
 749
 750 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
 751 {
 752         unsigned int val = ~0;
 753
 754         if (real_rate)
 755                 *real_rate = rate;
 756         /* special "hardcoded" rates */
 757         switch (rate) {
 758         case 8000:      return 5;
 759         case 11025:     return 4;
 760         case 16000:     return 3;
 761         case 22050:     return 2;
 762         case 44100:     return 1;
 763         case 48000:     return 0;
 764         default:
 765                 goto __variable;
 766         }
 767       __variable:
 768         val = 1536000 / rate;
 769         if (real_rate)
 770                 *real_rate = 1536000 / val;
 771         return val;
 772 }
 773
 774 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
 775 {
 776         int rec_mono;
 777
 778         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
 779                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
 780         if (runtime->channels == 1)
 781                 dma->valDMR |= BA0_DMR_MONO;
 782         if (snd_pcm_format_unsigned(runtime->format) > 0)
 783                 dma->valDMR |= BA0_DMR_USIGN;
 784         if (snd_pcm_format_big_endian(runtime->format) > 0)
 785                 dma->valDMR |= BA0_DMR_BEND;
 786         switch (snd_pcm_format_width(runtime->format)) {
 787         case 8: dma->valDMR |= BA0_DMR_SIZE8;
 788                 if (runtime->channels == 1)
 789                         dma->valDMR |= BA0_DMR_SWAPC;
 790                 break;
 791         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
 792         }
 793         dma->frag = 0;  /* for workaround */
 794         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
 795         if (runtime->buffer_size != runtime->period_size)
 796                 dma->valDCR |= BA0_DCR_HTCIE;
 797         /* Initialize DMA */
 798         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
 799         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
 800         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
 801         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
 802                                             (chip->src_right_play_slot << 8) |
 803                                             (chip->src_left_rec_slot << 16) |
 804                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
 805         if (!src)
 806                 goto __skip_src;
 807         if (!capture) {
 808                 if (dma->left_slot == chip->src_left_play_slot) {
 809                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 810                         snd_assert(dma->right_slot == chip->src_right_play_slot, );
 811                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
 812                 }
 813         } else {
 814                 if (dma->left_slot == chip->src_left_rec_slot) {
 815                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 816                         snd_assert(dma->right_slot == chip->src_right_rec_slot, );
 817                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
 818                 }
 819         }
 820       __skip_src:
 821         /* Deactivate wave playback FIFO before changing slot assignments */
 822         if (dma->regFCR == BA0_FCR0)
 823                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
 824         /* Initialize FIFO */
 825         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
 826                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
 827                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
 828                       BA0_FCR_OF(dma->fifo_offset);
 829         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
 830         /* Activate FIFO again for FM playback */
 831         if (dma->regFCR == BA0_FCR0)
 832                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
 833         /* Clear FIFO Status and Interrupt Control Register */
 834         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
 835 }
 836
 837 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
 838                                 snd_pcm_hw_params_t * hw_params)
 839 {
 840         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 841 }
 842
 843 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
 844 {
 845         return snd_pcm_lib_free_pages(substream);
 846 }
 847
 848 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
 849 {
 850         snd_pcm_runtime_t *runtime = substream->runtime;
 851         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
 852         cs4281_t *chip = snd_pcm_substream_chip(substream);
 853         unsigned long flags;
 854
 855         spin_lock_irqsave(&chip->reg_lock, flags);
 856         snd_cs4281_mode(chip, dma, runtime, 0, 1);
 857         spin_unlock_irqrestore(&chip->reg_lock, flags);
 858         return 0;
 859 }
 860
 861 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
 862 {
 863         snd_pcm_runtime_t *runtime = substream->runtime;
 864         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
 865         cs4281_t *chip = snd_pcm_substream_chip(substream);
 866         unsigned long flags;
 867
 868         spin_lock_irqsave(&chip->reg_lock, flags);
 869         snd_cs4281_mode(chip, dma, runtime, 1, 1);
 870         spin_unlock_irqrestore(&chip->reg_lock, flags);
 871         return 0;
 872 }
 873
 874 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
 875 {
 876         snd_pcm_runtime_t *runtime = substream->runtime;
 877         cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
 878         cs4281_t *chip = snd_pcm_substream_chip(substream);
 879
 880         // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
 881         return runtime->buffer_size -
 882                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
 883 }
 884
 885 static snd_pcm_hardware_t snd_cs4281_playback =
 886 {
 887         .info =                 (SNDRV_PCM_INFO_MMAP |
 888                                  SNDRV_PCM_INFO_INTERLEAVED |
 889                                  SNDRV_PCM_INFO_MMAP_VALID |
 890                                  SNDRV_PCM_INFO_PAUSE |
 891                                  SNDRV_PCM_INFO_RESUME |
 892                                  SNDRV_PCM_INFO_SYNC_START),
 893         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 894                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 895                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 896                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 897                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 898         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 899         .rate_min =             4000,
 900         .rate_max =             48000,
 901         .channels_min =         1,
 902         .channels_max =         2,
 903         .buffer_bytes_max =     (512*1024),
 904         .period_bytes_min =     64,
 905         .period_bytes_max =     (512*1024),
 906         .periods_min =          1,
 907         .periods_max =          2,
 908         .fifo_size =            CS4281_FIFO_SIZE,
 909 };
 910
 911 static snd_pcm_hardware_t snd_cs4281_capture =
 912 {
 913         .info =                 (SNDRV_PCM_INFO_MMAP |
 914                                  SNDRV_PCM_INFO_INTERLEAVED |
 915                                  SNDRV_PCM_INFO_MMAP_VALID |
 916                                  SNDRV_PCM_INFO_PAUSE |
 917                                  SNDRV_PCM_INFO_RESUME |
 918                                  SNDRV_PCM_INFO_SYNC_START),
 919         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 920                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 921                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 922                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 923                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 924         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 925         .rate_min =             4000,
 926         .rate_max =             48000,
 927         .channels_min =         1,
 928         .channels_max =         2,
 929         .buffer_bytes_max =     (512*1024),
 930         .period_bytes_min =     64,
 931         .period_bytes_max =     (512*1024),
 932         .periods_min =          1,
 933         .periods_max =          2,
 934         .fifo_size =            CS4281_FIFO_SIZE,
 935 };
 936
 937 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
 938 {
 939         cs4281_t *chip = snd_pcm_substream_chip(substream);
 940         snd_pcm_runtime_t *runtime = substream->runtime;
 941         cs4281_dma_t *dma;
 942
 943         dma = &chip->dma[0];
 944         dma->substream = substream;
 945         dma->left_slot = 0;
 946         dma->right_slot = 1;
 947         runtime->private_data = dma;
 948         runtime->hw = snd_cs4281_playback;
 949         snd_pcm_set_sync(substream);
 950         /* should be detected from the AC'97 layer, but it seems
 951            that although CS4297A rev B reports 18-bit ADC resolution,
 952            samples are 20-bit */
 953         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 954         return 0;
 955 }
 956
 957 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
 958 {
 959         cs4281_t *chip = snd_pcm_substream_chip(substream);
 960         snd_pcm_runtime_t *runtime = substream->runtime;
 961         cs4281_dma_t *dma;
 962
 963         dma = &chip->dma[1];
 964         dma->substream = substream;
 965         dma->left_slot = 10;
 966         dma->right_slot = 11;
 967         runtime->private_data = dma;
 968         runtime->hw = snd_cs4281_capture;
 969         snd_pcm_set_sync(substream);
 970         /* should be detected from the AC'97 layer, but it seems
 971            that although CS4297A rev B reports 18-bit ADC resolution,
 972            samples are 20-bit */
 973         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 974         return 0;
 975 }
 976
 977 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
 978 {
 979         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
 980
 981         dma->substream = NULL;
 982         return 0;
 983 }
 984
 985 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
 986 {
 987         cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
 988
 989         dma->substream = NULL;
 990         return 0;
 991 }
 992
 993 static snd_pcm_ops_t snd_cs4281_playback_ops = {
 994         .open =         snd_cs4281_playback_open,
 995         .close =        snd_cs4281_playback_close,
 996         .ioctl =        snd_pcm_lib_ioctl,
 997         .hw_params =    snd_cs4281_hw_params,
 998         .hw_free =      snd_cs4281_hw_free,
 999         .prepare =      snd_cs4281_playback_prepare,
1000         .trigger =      snd_cs4281_trigger,
1001         .pointer =      snd_cs4281_pointer,
1002 };
1003
1004 static snd_pcm_ops_t snd_cs4281_capture_ops = {
1005         .open =         snd_cs4281_capture_open,
1006         .close =        snd_cs4281_capture_close,
1007         .ioctl =        snd_pcm_lib_ioctl,
1008         .hw_params =    snd_cs4281_hw_params,
1009         .hw_free =      snd_cs4281_hw_free,
1010         .prepare =      snd_cs4281_capture_prepare,
1011         .trigger =      snd_cs4281_trigger,
1012         .pointer =      snd_cs4281_pointer,
1013 };
1014
1015 static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
1016 {
1017         cs4281_t *chip = snd_magic_cast(cs4281_t, pcm->private_data, return);
1018         chip->pcm = NULL;
1019         snd_pcm_lib_preallocate_free_for_all(pcm);
1020 }
1021
1022 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1023 {
1024         snd_pcm_t *pcm;
1025         int err;
1026
1027         if (rpcm)
1028                 *rpcm = NULL;
1029         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1030         if (err < 0)
1031                 return err;
1032
1033         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1034         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1035
1036         pcm->private_data = chip;
1037         pcm->private_free = snd_cs4281_pcm_free;
1038         pcm->info_flags = 0;
1039         strcpy(pcm->name, "CS4281");
1040         chip->pcm = pcm;
1041
1042         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1043                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1044
1045         if (rpcm)
1046                 *rpcm = pcm;
1047         return 0;
1048 }
1049
1050 /*
1051  *  Mixer section
1052  */
1053
1054 #define CS_VOL_MASK     0x1f
1055
1056 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1057 {
1058         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1059         uinfo->count             = 2;
1060         uinfo->value.integer.min = 0;
1061         uinfo->value.integer.max = CS_VOL_MASK;
1062         return 0;
1063 }
1064
1065 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1066 {
1067         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1068         int regL = (kcontrol->private_value >> 16) & 0xffff;
1069         int regR = kcontrol->private_value & 0xffff;
1070         int volL, volR;
1071
1072         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1073         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1074
1075         ucontrol->value.integer.value[0] = volL;
1076         ucontrol->value.integer.value[1] = volR;
1077         return 0;
1078 }
1079
1080 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1081 {
1082         cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1083         int change = 0;
1084         int regL = (kcontrol->private_value >> 16) & 0xffff;
1085         int regR = kcontrol->private_value & 0xffff;
1086         int volL, volR;
1087
1088         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1089         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1090
1091         if (ucontrol->value.integer.value[0] != volL) {
1092                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1093                 snd_cs4281_pokeBA0(chip, regL, volL);
1094                 change = 1;
1095         }
1096         if (ucontrol->value.integer.value[0] != volL) {
1097                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1098                 snd_cs4281_pokeBA0(chip, regR, volR);
1099                 change = 1;
1100         }
1101         return change;
1102 }
1103
1104 static snd_kcontrol_new_t snd_cs4281_fm_vol =
1105 {
1106         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1107         .name = "Synth Playback Volume",
1108         .info = snd_cs4281_info_volume,
1109         .get = snd_cs4281_get_volume,
1110         .put = snd_cs4281_put_volume,
1111         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1112 };
1113
1114 static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1115 {
1116         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1117         .name = "PCM Stream Playback Volume",
1118         .info = snd_cs4281_info_volume,
1119         .get = snd_cs4281_get_volume,
1120         .put = snd_cs4281_put_volume,
1121         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1122 };
1123
1124 static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1125 {
1126         cs4281_t *chip = snd_magic_cast(cs4281_t, bus->private_data, return);
1127         chip->ac97_bus = NULL;
1128 }
1129
1130 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1131 {
1132         cs4281_t *chip = snd_magic_cast(cs4281_t, ac97->private_data, return);
1133         if (ac97->num)
1134                 chip->ac97_secondary = NULL;
1135         else
1136                 chip->ac97 = NULL;
1137 }
1138
1139 static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1140 {
1141         snd_card_t *card = chip->card;
1142         ac97_bus_t bus;
1143         ac97_t ac97;
1144         int err;
1145
1146         memset(&bus, 0, sizeof(bus));
1147         bus.write = snd_cs4281_ac97_write;
1148         bus.read = snd_cs4281_ac97_read;
1149         bus.private_data = chip;
1150         bus.private_free = snd_cs4281_mixer_free_ac97_bus;
1151         if ((err = snd_ac97_bus(card, &bus, &chip->ac97_bus)) < 0)
1152                 return err;
1153
1154         memset(&ac97, 0, sizeof(ac97));
1155         ac97.private_data = chip;
1156         ac97.private_free = snd_cs4281_mixer_free_ac97;
1157         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1158                 return err;
1159         if (chip->dual_codec) {
1160                 ac97.num = 1;
1161                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1162                         return err;
1163         }
1164         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1165                 return err;
1166         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1167                 return err;
1168         return 0;
1169 }
1170
1171
1172 /*
1173  * proc interface
1174  */
1175
1176 static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1177                                   snd_info_buffer_t * buffer)
1178 {
1179         cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return);
1180
1181         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1182         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1183         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1184 }
1185
1186 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1187                                 struct file *file, char *buf, long count)
1188 {
1189         long size;
1190         cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return -ENXIO);
1191
1192         size = count;
1193         if (file->f_pos + size > CS4281_BA0_SIZE)
1194                 size = (long)CS4281_BA0_SIZE - file->f_pos;
1195         if (size > 0) {
1196                 if (copy_to_user_fromio(buf, chip->ba0 + file->f_pos, size))
1197                         return -EFAULT;
1198                 file->f_pos += size;
1199         }
1200         return size;
1201 }
1202
1203 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1204                                 struct file *file, char *buf, long count)
1205 {
1206         long size;
1207         cs4281_t *chip = snd_magic_cast(cs4281_t, entry->private_data, return -ENXIO);
1208
1209         size = count;
1210         if (file->f_pos + size > CS4281_BA1_SIZE)
1211                 size = (long)CS4281_BA1_SIZE - file->f_pos;
1212         if (size > 0) {
1213                 if (copy_to_user_fromio(buf, chip->ba1 + file->f_pos, size))
1214                         return -EFAULT;
1215                 file->f_pos += size;
1216         }
1217         return size;
1218 }
1219
1220 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1221         .read = snd_cs4281_BA0_read,
1222 };
1223
1224 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1225         .read = snd_cs4281_BA1_read,
1226 };
1227
1228 static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1229 {
1230         snd_info_entry_t *entry;
1231
1232         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1233                 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1234         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1235                 entry->content = SNDRV_INFO_CONTENT_DATA;
1236                 entry->private_data = chip;
1237                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1238                 entry->size = CS4281_BA0_SIZE;
1239         }
1240         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1241                 entry->content = SNDRV_INFO_CONTENT_DATA;
1242                 entry->private_data = chip;
1243                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1244                 entry->size = CS4281_BA1_SIZE;
1245         }
1246 }
1247
1248 /*
1249  * joystick support
1250  */
1251
1252 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1253
1254 typedef struct snd_cs4281_gameport {
1255         struct gameport info;
1256         cs4281_t *chip;
1257 } cs4281_gameport_t;
1258
1259 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1260 {
1261         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1262         cs4281_t *chip;
1263         snd_assert(gp, return);
1264         chip = snd_magic_cast(cs4281_t, gp->chip, return);
1265         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1266 }
1267
1268 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1269 {
1270         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1271         cs4281_t *chip;
1272         snd_assert(gp, return 0);
1273         chip = snd_magic_cast(cs4281_t, gp->chip, return 0);
1274         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1275 }
1276
1277 #ifdef COOKED_MODE
1278 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1279 {
1280         cs4281_gameport_t *gp = (cs4281_gameport_t *)gameport;
1281         cs4281_t *chip;
1282         unsigned js1, js2, jst;
1283
1284         snd_assert(gp, return 0);
1285         chip = snd_magic_cast(cs4281_t, gp->chip, return 0);
1286
1287         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1288         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1289         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1290
1291         *buttons = (~jst >> 4) & 0x0F;
1292
1293         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1294         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1295         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1296         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1297
1298         for(jst=0;jst<4;++jst)
1299                 if(axes[jst]==0xFFFF) axes[jst] = -1;
1300         return 0;
1301 }
1302 #endif
1303
1304 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1305 {
1306         switch (mode) {
1307 #ifdef COOKED_MODE
1308         case GAMEPORT_MODE_COOKED:
1309                 return 0;
1310 #endif
1311         case GAMEPORT_MODE_RAW:
1312                 return 0;
1313         default:
1314                 return -1;
1315         }
1316         return 0;
1317 }
1318
1319 static void __devinit snd_cs4281_gameport(cs4281_t *chip)
1320 {
1321         cs4281_gameport_t *gp;
1322         gp = kmalloc(sizeof(*gp), GFP_KERNEL);
1323         if (! gp) {
1324                 snd_printk(KERN_ERR "cannot allocate gameport area\n");
1325                 return;
1326         }
1327         memset(gp, 0, sizeof(*gp));
1328         gp->info.open = snd_cs4281_gameport_open;
1329         gp->info.read = snd_cs4281_gameport_read;
1330         gp->info.trigger = snd_cs4281_gameport_trigger;
1331 #ifdef COOKED_MODE
1332         gp->info.cooked_read = snd_cs4281_gameport_cooked_read;
1333 #endif
1334         gp->chip = chip;
1335         chip->gameport = gp;
1336
1337         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1338         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1339         gameport_register_port(&gp->info);
1340 }
1341
1342 #else
1343 #define snd_cs4281_gameport(chip) /*NOP*/
1344 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1345
1346
1347 /*
1348
1349  */
1350
1351 static int snd_cs4281_free(cs4281_t *chip)
1352 {
1353 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1354         if (chip->gameport) {
1355                 gameport_unregister_port(&chip->gameport->info);
1356                 kfree(chip->gameport);
1357         }
1358 #endif
1359         if (chip->irq >= 0)
1360                 synchronize_irq(chip->irq);
1361
1362         /* Mask interrupts */
1363         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1364         /* Stop the DLL Clock logic. */
1365         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1366         /* Sound System Power Management - Turn Everything OFF */
1367         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1368         /* PCI interface - D3 state */
1369         pci_set_power_state(chip->pci, 3);
1370
1371         if (chip->ba0)
1372                 iounmap((void *) chip->ba0);
1373         if (chip->ba1)
1374                 iounmap((void *) chip->ba1);
1375         if (chip->ba0_res) {
1376                 release_resource(chip->ba0_res);
1377                 kfree_nocheck(chip->ba0_res);
1378         }
1379         if (chip->ba1_res) {
1380                 release_resource(chip->ba1_res);
1381                 kfree_nocheck(chip->ba1_res);
1382         }
1383         if (chip->irq >= 0)
1384                 free_irq(chip->irq, (void *)chip);
1385
1386         snd_magic_kfree(chip);
1387         return 0;
1388 }
1389
1390 static int snd_cs4281_dev_free(snd_device_t *device)
1391 {
1392         cs4281_t *chip = snd_magic_cast(cs4281_t, device->device_data, return -ENXIO);
1393         return snd_cs4281_free(chip);
1394 }
1395
1396 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1397 #ifdef CONFIG_PM
1398 static int snd_cs4281_set_power_state(snd_card_t *card, unsigned int power_state);
1399 #endif
1400
1401 static int __devinit snd_cs4281_create(snd_card_t * card,
1402                                        struct pci_dev *pci,
1403                                        cs4281_t ** rchip,
1404                                        int dual_codec)
1405 {
1406         cs4281_t *chip;
1407         unsigned int tmp;
1408         int err;
1409         static snd_device_ops_t ops = {
1410                 .dev_free =     snd_cs4281_dev_free,
1411         };
1412
1413         *rchip = NULL;
1414         if ((err = pci_enable_device(pci)) < 0)
1415                 return err;
1416         chip = snd_magic_kcalloc(cs4281_t, 0, GFP_KERNEL);
1417         if (chip == NULL)
1418                 return -ENOMEM;
1419         spin_lock_init(&chip->reg_lock);
1420         chip->card = card;
1421         chip->pci = pci;
1422         chip->irq = -1;
1423         chip->ba0_addr = pci_resource_start(pci, 0);
1424         chip->ba1_addr = pci_resource_start(pci, 1);
1425         pci_set_master(pci);
1426         if (dual_codec < 0 || dual_codec > 3) {
1427                 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1428                 dual_codec = 0;
1429         }
1430         chip->dual_codec = dual_codec;
1431
1432         if ((chip->ba0_res = request_mem_region(chip->ba0_addr, CS4281_BA0_SIZE, "CS4281 BA0")) == NULL) {
1433                 snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->ba0_addr, chip->ba0_addr + CS4281_BA0_SIZE - 1);
1434                 snd_cs4281_free(chip);
1435                 return -ENOMEM;
1436         }
1437         if ((chip->ba1_res = request_mem_region(chip->ba1_addr, CS4281_BA1_SIZE, "CS4281 BA1")) == NULL) {
1438                 snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->ba1_addr, chip->ba1_addr + CS4281_BA1_SIZE - 1);
1439                 snd_cs4281_free(chip);
1440                 return -ENOMEM;
1441         }
1442         if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1443                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1444                 snd_cs4281_free(chip);
1445                 return -ENOMEM;
1446         }
1447         chip->irq = pci->irq;
1448
1449         chip->ba0 = (unsigned long) ioremap_nocache(chip->ba0_addr, CS4281_BA0_SIZE);
1450         chip->ba1 = (unsigned long) ioremap_nocache(chip->ba1_addr, CS4281_BA1_SIZE);
1451         if (!chip->ba0 || !chip->ba1) {
1452                 snd_cs4281_free(chip);
1453                 return -ENOMEM;
1454         }
1455
1456         tmp = snd_cs4281_chip_init(chip);
1457         if (tmp) {
1458                 snd_cs4281_free(chip);
1459                 return tmp;
1460         }
1461
1462         snd_cs4281_proc_init(chip);
1463
1464 #ifdef CONFIG_PM
1465         card->set_power_state = snd_cs4281_set_power_state;
1466         card->power_state_private_data = chip;
1467 #endif
1468
1469         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1470                 snd_cs4281_free(chip);
1471                 return err;
1472         }
1473
1474         snd_card_set_dev(card, &pci->dev);
1475
1476         *rchip = chip;
1477         return 0;
1478 }
1479
1480 static int snd_cs4281_chip_init(cs4281_t *chip)
1481 {
1482         unsigned int tmp;
1483         int timeout;
1484
1485         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1486         if (tmp != BA0_CFLR_DEFAULT) {
1487                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1488                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1489                 if (tmp != BA0_CFLR_DEFAULT) {
1490                         snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1491                         return -EIO;
1492                 }
1493         }
1494
1495         /* Set the 'Configuration Write Protect' register
1496          * to 4281h.  Allows vendor-defined configuration
1497          * space between 0e4h and 0ffh to be written. */
1498         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1499
1500         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1501                 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1502                 return -EIO;
1503         }
1504         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1505                 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1506                 return -EIO;
1507         }
1508
1509         /* Sound System Power Management */
1510         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1511                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1512                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1513
1514         /* Serial Port Power Management */
1515         /* Blast the clock control register to zero so that the
1516          * PLL starts out in a known state, and blast the master serial
1517          * port control register to zero so that the serial ports also
1518          * start out in a known state. */
1519         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1520         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1521
1522         /* Make ESYN go to zero to turn off
1523          * the Sync pulse on the AC97 link. */
1524         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1525         udelay(50);
1526
1527         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1528          *  spec) and then drive it high.  This is done for non AC97 modes since
1529          *  there might be logic external to the CS4281 that uses the ARST# line
1530          *  for a reset. */
1531         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1532         udelay(50);
1533         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1534         snd_cs4281_delay(50000);
1535
1536         if (chip->dual_codec)
1537                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1538
1539         /*
1540          *  Set the serial port timing configuration.
1541          */
1542         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1543                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1544                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1545
1546         /*
1547          *  Start the DLL Clock logic.
1548          */
1549         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1550         snd_cs4281_delay(50000);
1551         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1552
1553         /*
1554          * Wait for the DLL ready signal from the clock logic.
1555          */
1556         timeout = HZ;
1557         do {
1558                 /*
1559                  *  Read the AC97 status register to see if we've seen a CODEC
1560                  *  signal from the AC97 codec.
1561                  */
1562                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1563                         goto __ok0;
1564                 snd_cs4281_delay_long();
1565         } while (timeout-- > 0);
1566
1567         snd_printk(KERN_ERR "DLLRDY not seen\n");
1568         return -EIO;
1569
1570       __ok0:
1571
1572         /*
1573          *  The first thing we do here is to enable sync generation.  As soon
1574          *  as we start receiving bit clock, we'll start producing the SYNC
1575          *  signal.
1576          */
1577         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1578
1579         /*
1580          * Wait for the codec ready signal from the AC97 codec.
1581          */
1582         timeout = HZ;
1583         do {
1584                 /*
1585                  *  Read the AC97 status register to see if we've seen a CODEC
1586                  *  signal from the AC97 codec.
1587                  */
1588                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1589                         goto __ok1;
1590                 snd_cs4281_delay_long();
1591         } while (timeout-- > 0);
1592
1593         snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1594         return -EIO;
1595
1596       __ok1:
1597         if (chip->dual_codec) {
1598                 timeout = HZ;
1599                 do {
1600                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1601                                 goto __codec2_ok;
1602                         snd_cs4281_delay_long();
1603                 } while (timeout-- > 0);
1604                 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1605                 chip->dual_codec = 0;
1606         __codec2_ok: ;
1607         }
1608
1609         /*
1610          *  Assert the valid frame signal so that we can start sending commands
1611          *  to the AC97 codec.
1612          */
1613
1614         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1615
1616         /*
1617          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1618          *  the codec is pumping ADC data across the AC-link.
1619          */
1620
1621         timeout = HZ;
1622         do {
1623                 /*
1624                  *  Read the input slot valid register and see if input slots 3
1625                  *  4 are valid yet.
1626                  */
1627                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1628                         goto __ok2;
1629                 snd_cs4281_delay_long();
1630         } while (timeout-- > 0);
1631
1632         snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1633         return -EIO;
1634
1635       __ok2:
1636
1637         /*
1638          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1639          *  commense the transfer of digital audio data to the AC97 codec.
1640          */
1641         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1642
1643         /*
1644          *  Initialize DMA structures
1645          */
1646         for (tmp = 0; tmp < 4; tmp++) {
1647                 cs4281_dma_t *dma = &chip->dma[tmp];
1648                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1649                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1650                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1651                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1652                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1653                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1654                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1655                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1656                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1657                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1658                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1659                                    BA0_FCR_LS(31) |
1660                                    BA0_FCR_RS(31) |
1661                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1662                                    BA0_FCR_OF(dma->fifo_offset));
1663         }
1664
1665         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1666         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1667         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1668         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1669
1670         /* Activate wave playback FIFO for FM playback */
1671         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1672                               BA0_FCR_RS(1) |
1673                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1674                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1675         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1676         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1677                                             (chip->src_right_play_slot << 8) |
1678                                             (chip->src_left_rec_slot << 16) |
1679                                             (chip->src_right_rec_slot << 24));
1680
1681         /* Initialize digital volume */
1682         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1683         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1684
1685         /* Enable IRQs */
1686         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1687         /* Unmask interrupts */
1688         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1689                                         BA0_HISR_MIDI |
1690                                         BA0_HISR_DMAI |
1691                                         BA0_HISR_DMA(0) |
1692                                         BA0_HISR_DMA(1) |
1693                                         BA0_HISR_DMA(2) |
1694                                         BA0_HISR_DMA(3)));
1695         synchronize_irq(chip->irq);
1696
1697         return 0;
1698 }
1699
1700 /*
1701  *  MIDI section
1702  */
1703
1704 static void snd_cs4281_midi_reset(cs4281_t *chip)
1705 {
1706         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1707         udelay(100);
1708         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1709 }
1710
1711 static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1712 {
1713         unsigned long flags;
1714         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1715
1716         spin_lock_irqsave(&chip->reg_lock, flags);
1717         chip->midcr |= BA0_MIDCR_RXE;
1718         chip->midi_input = substream;
1719         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1720                 snd_cs4281_midi_reset(chip);
1721         } else {
1722                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1723         }
1724         spin_unlock_irqrestore(&chip->reg_lock, flags);
1725         return 0;
1726 }
1727
1728 static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1729 {
1730         unsigned long flags;
1731         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1732
1733         spin_lock_irqsave(&chip->reg_lock, flags);
1734         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1735         chip->midi_input = NULL;
1736         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1737                 snd_cs4281_midi_reset(chip);
1738         } else {
1739                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1740         }
1741         chip->uartm &= ~CS4281_MODE_INPUT;
1742         spin_unlock_irqrestore(&chip->reg_lock, flags);
1743         return 0;
1744 }
1745
1746 static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1747 {
1748         unsigned long flags;
1749         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1750
1751         spin_lock_irqsave(&chip->reg_lock, flags);
1752         chip->uartm |= CS4281_MODE_OUTPUT;
1753         chip->midcr |= BA0_MIDCR_TXE;
1754         chip->midi_output = substream;
1755         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1756                 snd_cs4281_midi_reset(chip);
1757         } else {
1758                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1759         }
1760         spin_unlock_irqrestore(&chip->reg_lock, flags);
1761         return 0;
1762 }
1763
1764 static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1765 {
1766         unsigned long flags;
1767         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return -ENXIO);
1768
1769         spin_lock_irqsave(&chip->reg_lock, flags);
1770         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1771         chip->midi_output = NULL;
1772         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1773                 snd_cs4281_midi_reset(chip);
1774         } else {
1775                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1776         }
1777         chip->uartm &= ~CS4281_MODE_OUTPUT;
1778         spin_unlock_irqrestore(&chip->reg_lock, flags);
1779         return 0;
1780 }
1781
1782 static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1783 {
1784         unsigned long flags;
1785         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return);
1786
1787         spin_lock_irqsave(&chip->reg_lock, flags);
1788         if (up) {
1789                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1790                         chip->midcr |= BA0_MIDCR_RIE;
1791                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1792                 }
1793         } else {
1794                 if (chip->midcr & BA0_MIDCR_RIE) {
1795                         chip->midcr &= ~BA0_MIDCR_RIE;
1796                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1797                 }
1798         }
1799         spin_unlock_irqrestore(&chip->reg_lock, flags);
1800 }
1801
1802 static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1803 {
1804         unsigned long flags;
1805         cs4281_t *chip = snd_magic_cast(cs4281_t, substream->rmidi->private_data, return);
1806         unsigned char byte;
1807
1808         spin_lock_irqsave(&chip->reg_lock, flags);
1809         if (up) {
1810                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1811                         chip->midcr |= BA0_MIDCR_TIE;
1812                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1813                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1814                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1815                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1816                                         chip->midcr &= ~BA0_MIDCR_TIE;
1817                                 } else {
1818                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1819                                 }
1820                         }
1821                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1822                 }
1823         } else {
1824                 if (chip->midcr & BA0_MIDCR_TIE) {
1825                         chip->midcr &= ~BA0_MIDCR_TIE;
1826                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1827                 }
1828         }
1829         spin_unlock_irqrestore(&chip->reg_lock, flags);
1830 }
1831
1832 static snd_rawmidi_ops_t snd_cs4281_midi_output =
1833 {
1834         .open =         snd_cs4281_midi_output_open,
1835         .close =        snd_cs4281_midi_output_close,
1836         .trigger =      snd_cs4281_midi_output_trigger,
1837 };
1838
1839 static snd_rawmidi_ops_t snd_cs4281_midi_input =
1840 {
1841         .open =         snd_cs4281_midi_input_open,
1842         .close =        snd_cs4281_midi_input_close,
1843         .trigger =      snd_cs4281_midi_input_trigger,
1844 };
1845
1846 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1847 {
1848         snd_rawmidi_t *rmidi;
1849         int err;
1850
1851         if (rrawmidi)
1852                 *rrawmidi = NULL;
1853         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1854                 return err;
1855         strcpy(rmidi->name, "CS4281");
1856         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1857         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1858         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1859         rmidi->private_data = chip;
1860         chip->rmidi = rmidi;
1861         if (rrawmidi)
1862                 *rrawmidi = rmidi;
1863         return 0;
1864 }
1865
1866 /*
1867  *  Interrupt handler
1868  */
1869
1870 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1871 {
1872         cs4281_t *chip = snd_magic_cast(cs4281_t, dev_id, return IRQ_NONE);
1873         unsigned int status, dma, val;
1874         cs4281_dma_t *cdma;
1875
1876         if (chip == NULL)
1877                 return IRQ_NONE;
1878         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1879         if ((status & 0x7fffffff) == 0) {
1880                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1881                 return IRQ_NONE;
1882         }
1883
1884         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1885                 for (dma = 0; dma < 4; dma++)
1886                         if (status & BA0_HISR_DMA(dma)) {
1887                                 cdma = &chip->dma[dma];
1888                                 spin_lock(&chip->reg_lock);
1889                                 /* ack DMA IRQ */
1890                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1891                                 /* workaround, sometimes CS4281 acknowledges */
1892                                 /* end or middle transfer position twice */
1893                                 cdma->frag++;
1894                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1895                                         cdma->frag--;
1896                                         chip->spurious_dhtc_irq++;
1897                                         spin_unlock(&chip->reg_lock);
1898                                         continue;
1899                                 }
1900                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1901                                         cdma->frag--;
1902                                         chip->spurious_dtc_irq++;
1903                                         spin_unlock(&chip->reg_lock);
1904                                         continue;
1905                                 }
1906                                 spin_unlock(&chip->reg_lock);
1907                                 snd_pcm_period_elapsed(cdma->substream);
1908                         }
1909         }
1910
1911         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1912                 unsigned char c;
1913
1914                 spin_lock(&chip->reg_lock);
1915                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1916                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1917                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1918                                 continue;
1919                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1920                 }
1921                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1922                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1923                                 break;
1924                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1925                                 chip->midcr &= ~BA0_MIDCR_TIE;
1926                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1927                                 break;
1928                         }
1929                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1930                 }
1931                 spin_unlock(&chip->reg_lock);
1932         }
1933
1934         /* EOI to the PCI part... reenables interrupts */
1935         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1936
1937         return IRQ_HANDLED;
1938 }
1939
1940
1941 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1942                                       const struct pci_device_id *pci_id)
1943 {
1944         static int dev;
1945         snd_card_t *card;
1946         cs4281_t *chip;
1947         opl3_t *opl3;
1948         int err;
1949
1950         if (dev >= SNDRV_CARDS)
1951                 return -ENODEV;
1952         if (!enable[dev]) {
1953                 dev++;
1954                 return -ENOENT;
1955         }
1956
1957         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1958         if (card == NULL)
1959                 return -ENOMEM;
1960
1961         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1962                 snd_card_free(card);
1963                 return err;
1964         }
1965
1966         if ((err = snd_cs4281_mixer(chip)) < 0) {
1967                 snd_card_free(card);
1968                 return err;
1969         }
1970         if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1971                 snd_card_free(card);
1972                 return err;
1973         }
1974         if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1975                 snd_card_free(card);
1976                 return err;
1977         }
1978         if ((err = snd_opl3_create(card,
1979                                    (chip->ba0 + BA0_B0AP) >> 2,
1980                                    (chip->ba0 + BA0_B1AP) >> 2,
1981                                    OPL3_HW_OPL3_CS4281, 1, &opl3)) < 0) {
1982                 snd_card_free(card);
1983                 return err;
1984         }
1985         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1986                 snd_card_free(card);
1987                 return err;
1988         }
1989         snd_cs4281_gameport(chip);
1990         strcpy(card->driver, "CS4281");
1991         strcpy(card->shortname, "Cirrus Logic CS4281");
1992         sprintf(card->longname, "%s at 0x%lx, irq %d",
1993                 card->shortname,
1994                 chip->ba0_addr,
1995                 chip->irq);
1996
1997         if ((err = snd_card_register(card)) < 0) {
1998                 snd_card_free(card);
1999                 return err;
2000         }
2001
2002         pci_set_drvdata(pci, chip);
2003         dev++;
2004         return 0;
2005 }
2006
2007 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
2008 {
2009         cs4281_t *chip = pci_get_drvdata(pci);
2010         snd_card_free(chip->card);
2011         pci_set_drvdata(pci, NULL);
2012 }
2013
2014 /*
2015  * Power Management
2016  */
2017 #ifdef CONFIG_PM
2018
2019 static int saved_regs[SUSPEND_REGISTERS] = {
2020         BA0_JSCTL,
2021         BA0_GPIOR,
2022         BA0_SSCR,
2023         BA0_MIDCR,
2024         BA0_SRCSA,
2025         BA0_PASR,
2026         BA0_CASR,
2027         BA0_DACSR,
2028         BA0_ADCSR,
2029         BA0_FMLVC,
2030         BA0_FMRVC,
2031         BA0_PPLVC,
2032         BA0_PPRVC,
2033 };
2034
2035 #define number_of(array)        (sizeof(array) / sizeof(array[0]))
2036
2037 #define CLKCR1_CKRA                             0x00010000L
2038
2039 static void cs4281_suspend(cs4281_t *chip)
2040 {
2041         snd_card_t *card = chip->card;
2042         u32 ulCLK;
2043         unsigned int i;
2044
2045         if (card->power_state == SNDRV_CTL_POWER_D3hot)
2046                 return;
2047
2048         snd_pcm_suspend_all(chip->pcm);
2049
2050         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2051         ulCLK |= CLKCR1_CKRA;
2052         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2053
2054         /* Disable interrupts. */
2055         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2056
2057         /* remember the status registers */
2058         for (i = 0; i < number_of(saved_regs); i++)
2059                 if (saved_regs[i])
2060                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2061
2062         /* Turn off the serial ports. */
2063         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2064
2065         /* Power off FM, Joystick, AC link, */
2066         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2067
2068         /* DLL off. */
2069         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2070
2071         /* AC link off. */
2072         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2073
2074         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2075         ulCLK &= ~CLKCR1_CKRA;
2076         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2077
2078         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2079 }
2080
2081 static void cs4281_resume(cs4281_t *chip)
2082 {
2083         snd_card_t *card = chip->card;
2084         unsigned int i;
2085         u32 ulCLK;
2086
2087         if (card->power_state == SNDRV_CTL_POWER_D0)
2088                 return;
2089
2090         pci_enable_device(chip->pci);
2091
2092         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2093         ulCLK |= CLKCR1_CKRA;
2094         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2095
2096         snd_cs4281_chip_init(chip);
2097
2098         /* restore the status registers */
2099         for (i = 0; i < number_of(saved_regs); i++)
2100                 if (saved_regs[i])
2101                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2102
2103         if (chip->ac97)
2104                 snd_ac97_resume(chip->ac97);
2105         if (chip->ac97_secondary)
2106                 snd_ac97_resume(chip->ac97_secondary);
2107
2108         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2109         ulCLK &= ~CLKCR1_CKRA;
2110         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2111
2112         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2113 }
2114
2115 static int snd_cs4281_suspend(struct pci_dev *dev, u32 state)
2116 {
2117         cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return -ENXIO);
2118         cs4281_suspend(chip);
2119         return 0;
2120 }
2121 static int snd_cs4281_resume(struct pci_dev *dev)
2122 {
2123         cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return -ENXIO);
2124         cs4281_resume(chip);
2125         return 0;
2126 }
2127
2128 /* callback */
2129 static int snd_cs4281_set_power_state(snd_card_t *card, unsigned int power_state)
2130 {
2131         cs4281_t *chip = snd_magic_cast(cs4281_t, card->power_state_private_data, return -ENXIO);
2132         switch (power_state) {
2133         case SNDRV_CTL_POWER_D0:
2134         case SNDRV_CTL_POWER_D1:
2135         case SNDRV_CTL_POWER_D2:
2136                 cs4281_resume(chip);
2137                 break;
2138         case SNDRV_CTL_POWER_D3hot:
2139         case SNDRV_CTL_POWER_D3cold:
2140                 cs4281_suspend(chip);
2141                 break;
2142         default:
2143                 return -EINVAL;
2144         }
2145         return 0;
2146 }
2147
2148 #endif /* CONFIG_PM */
2149
2150 static struct pci_driver driver = {
2151         .name = "CS4281",
2152         .id_table = snd_cs4281_ids,
2153         .probe = snd_cs4281_probe,
2154         .remove = __devexit_p(snd_cs4281_remove),
2155 #ifdef CONFIG_PM
2156         .suspend = snd_cs4281_suspend,
2157         .resume = snd_cs4281_resume,
2158 #endif
2159 };
2160
2161 static int __init alsa_card_cs4281_init(void)
2162 {
2163         int err;
2164
2165         if ((err = pci_module_init(&driver)) < 0) {
2166 #ifdef MODULE
2167                 printk(KERN_ERR "CS4281 soundcard not found or device busy\n");
2168 #endif
2169                 return err;
2170         }
2171         return 0;
2172 }
2173
2174 static void __exit alsa_card_cs4281_exit(void)
2175 {
2176         pci_unregister_driver(&driver);
2177 }
2178
2179 module_init(alsa_card_cs4281_init)
2180 module_exit(alsa_card_cs4281_exit)
2181
2182 #ifndef MODULE
2183
2184 /* format is: snd-cs4281=enable,index,id */
2185
2186 static int __init alsa_card_cs4281_setup(char *str)
2187 {
2188         static unsigned __initdata nr_dev = 0;
2189
2190         if (nr_dev >= SNDRV_CARDS)
2191                 return 0;
2192         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2193                get_option(&str,&index[nr_dev]) == 2 &&
2194                get_id(&str,&id[nr_dev]) == 2);
2195         nr_dev++;
2196         return 1;
2197 }
2198
2199 __setup("snd-cs4281=", alsa_card_cs4281_setup);
2200
2201 #endif /* ifndef MODULE */