sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer controll.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <sound/driver.h>
  49 #include <linux/delay.h>
  50 #include <linux/pci.h>
  51 #include <linux/pm.h>
  52 #include <linux/init.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/slab.h>
  55 #include <linux/gameport.h>
  56
  57 #include <sound/core.h>
  58 #include <sound/control.h>
  59 #include <sound/info.h>
  60 #include <sound/pcm.h>
  61 #include <sound/pcm_params.h>
  62 #include <sound/cs46xx.h>
  63
  64 #include <asm/io.h>
  65
  66 #include "cs46xx_lib.h"
  67 #include "dsp_spos.h"
  68
  69 static void amp_voyetra(cs46xx_t *chip, int change);
  70
  71 #ifdef CONFIG_SND_CS46XX_NEW_DSP
  72 static snd_pcm_ops_t snd_cs46xx_playback_rear_ops;
  73 static snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops;
  74 static snd_pcm_ops_t snd_cs46xx_playback_clfe_ops;
  75 static snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops;
  76 static snd_pcm_ops_t snd_cs46xx_playback_iec958_ops;
  77 static snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops;
  78 #endif
  79
  80 static snd_pcm_ops_t snd_cs46xx_playback_ops;
  81 static snd_pcm_ops_t snd_cs46xx_playback_indirect_ops;
  82 static snd_pcm_ops_t snd_cs46xx_capture_ops;
  83 static snd_pcm_ops_t snd_cs46xx_capture_indirect_ops;
  84
  85 static unsigned short snd_cs46xx_codec_read(cs46xx_t *chip,
  86                                             unsigned short reg,
  87                                             int codec_index)
  88 {
  89         int count;
  90         unsigned short result,tmp;
  91         u32 offset = 0;
  92         snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  93                      (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  94                      return -EINVAL);
  95
  96         chip->active_ctrl(chip, 1);
  97
  98         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  99                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
 100
 101         /*
 102          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 103          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 104          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
 105          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 106          *  5. if DCV not cleared, break and return error
 107          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 108          */
 109
 110         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 111
 112         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 113         if ((tmp & ACCTL_VFRM) == 0) {
 114                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
 115                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 116                 msleep(50);
 117                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 118                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 119
 120         }
 121
 122         /*
 123          *  Setup the AC97 control registers on the CS461x to send the
 124          *  appropriate command to the AC97 to perform the read.
 125          *  ACCAD = Command Address Register = 46Ch
 126          *  ACCDA = Command Data Register = 470h
 127          *  ACCTL = Control Register = 460h
 128          *  set DCV - will clear when process completed
 129          *  set CRW - Read command
 130          *  set VFRM - valid frame enabled
 131          *  set ESYN - ASYNC generation enabled
 132          *  set RSTN - ARST# inactive, AC97 codec not reset
 133          */
 134
 135         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 136         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 137         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 138                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 139                                    ACCTL_VFRM | ACCTL_ESYN |
 140                                    ACCTL_RSTN);
 141                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 142                                    ACCTL_VFRM | ACCTL_ESYN |
 143                                    ACCTL_RSTN);
 144         } else {
 145                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 146                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 147                                    ACCTL_RSTN);
 148         }
 149
 150         /*
 151          *  Wait for the read to occur.
 152          */
 153         for (count = 0; count < 1000; count++) {
 154                 /*
 155                  *  First, we want to wait for a short time.
 156                  */
 157                 udelay(10);
 158                 /*
 159                  *  Now, check to see if the read has completed.
 160                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 161                  */
 162                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 163                         goto ok1;
 164         }
 165
 166         snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 167         result = 0xffff;
 168         goto end;
 169
 170  ok1:
 171         /*
 172          *  Wait for the valid status bit to go active.
 173          */
 174         for (count = 0; count < 100; count++) {
 175                 /*
 176                  *  Read the AC97 status register.
 177                  *  ACSTS = Status Register = 464h
 178                  *  VSTS - Valid Status
 179                  */
 180                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 181                         goto ok2;
 182                 udelay(10);
 183         }
 184
 185         snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 186         result = 0xffff;
 187         goto end;
 188
 189  ok2:
 190         /*
 191          *  Read the data returned from the AC97 register.
 192          *  ACSDA = Status Data Register = 474h
 193          */
 194 #if 0
 195         printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 196                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 197                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 198 #endif
 199
 200         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 201         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 202  end:
 203         chip->active_ctrl(chip, -1);
 204         return result;
 205 }
 206
 207 static unsigned short snd_cs46xx_ac97_read(ac97_t * ac97,
 208                                             unsigned short reg)
 209 {
 210         cs46xx_t *chip = ac97->private_data;
 211         unsigned short val;
 212         int codec_index = ac97->num;
 213
 214         snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
 215                    codec_index == CS46XX_SECONDARY_CODEC_INDEX,
 216                    return 0xffff);
 217
 218         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 219
 220         return val;
 221 }
 222
 223
 224 static void snd_cs46xx_codec_write(cs46xx_t *chip,
 225                                    unsigned short reg,
 226                                    unsigned short val,
 227                                    int codec_index)
 228 {
 229         int count;
 230
 231         snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
 232                     (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
 233                     return);
 234
 235         chip->active_ctrl(chip, 1);
 236
 237         /*
 238          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 239          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 240          *  3. Write ACCTL = Control Register = 460h for initiating the write
 241          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 242          *  5. if DCV not cleared, break and return error
 243          */
 244
 245         /*
 246          *  Setup the AC97 control registers on the CS461x to send the
 247          *  appropriate command to the AC97 to perform the read.
 248          *  ACCAD = Command Address Register = 46Ch
 249          *  ACCDA = Command Data Register = 470h
 250          *  ACCTL = Control Register = 460h
 251          *  set DCV - will clear when process completed
 252          *  reset CRW - Write command
 253          *  set VFRM - valid frame enabled
 254          *  set ESYN - ASYNC generation enabled
 255          *  set RSTN - ARST# inactive, AC97 codec not reset
 256          */
 257         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 258         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 259         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 260
 261         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 262                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 263                                    ACCTL_ESYN | ACCTL_RSTN);
 264                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 265                                    ACCTL_ESYN | ACCTL_RSTN);
 266         } else {
 267                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 268                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 269         }
 270
 271         for (count = 0; count < 4000; count++) {
 272                 /*
 273                  *  First, we want to wait for a short time.
 274                  */
 275                 udelay(10);
 276                 /*
 277                  *  Now, check to see if the write has completed.
 278                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 279                  */
 280                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 281                         goto end;
 282                 }
 283         }
 284         snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 285  end:
 286         chip->active_ctrl(chip, -1);
 287 }
 288
 289 static void snd_cs46xx_ac97_write(ac97_t *ac97,
 290                                    unsigned short reg,
 291                                    unsigned short val)
 292 {
 293         cs46xx_t *chip = ac97->private_data;
 294         int codec_index = ac97->num;
 295
 296         snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
 297                    codec_index == CS46XX_SECONDARY_CODEC_INDEX,
 298                    return);
 299
 300         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 301 }
 302
 303
 304 /*
 305  *  Chip initialization
 306  */
 307
 308 int snd_cs46xx_download(cs46xx_t *chip,
 309                         u32 *src,
 310                         unsigned long offset,
 311                         unsigned long len)
 312 {
 313         void __iomem *dst;
 314         unsigned int bank = offset >> 16;
 315         offset = offset & 0xffff;
 316
 317         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 318         dst = chip->region.idx[bank+1].remap_addr + offset;
 319         len /= sizeof(u32);
 320
 321         /* writel already converts 32-bit value to right endianess */
 322         while (len-- > 0) {
 323                 writel(*src++, dst);
 324                 dst += sizeof(u32);
 325         }
 326         return 0;
 327 }
 328
 329 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 330
 331 #include "imgs/cwc4630.h"
 332 #include "imgs/cwcasync.h"
 333 #include "imgs/cwcsnoop.h"
 334 #include "imgs/cwcbinhack.h"
 335 #include "imgs/cwcdma.h"
 336
 337 int snd_cs46xx_clear_BA1(cs46xx_t *chip,
 338                          unsigned long offset,
 339                          unsigned long len)
 340 {
 341         void __iomem *dst;
 342         unsigned int bank = offset >> 16;
 343         offset = offset & 0xffff;
 344
 345         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 346         dst = chip->region.idx[bank+1].remap_addr + offset;
 347         len /= sizeof(u32);
 348
 349         /* writel already converts 32-bit value to right endianess */
 350         while (len-- > 0) {
 351                 writel(0, dst);
 352                 dst += sizeof(u32);
 353         }
 354         return 0;
 355 }
 356
 357 #else /* old DSP image */
 358
 359 #include "cs46xx_image.h"
 360
 361 int snd_cs46xx_download_image(cs46xx_t *chip)
 362 {
 363         int idx, err;
 364         unsigned long offset = 0;
 365
 366         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 367                 if ((err = snd_cs46xx_download(chip,
 368                                                &BA1Struct.map[offset],
 369                                                BA1Struct.memory[idx].offset,
 370                                                BA1Struct.memory[idx].size)) < 0)
 371                         return err;
 372                 offset += BA1Struct.memory[idx].size >> 2;
 373         }
 374         return 0;
 375 }
 376 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 377
 378 /*
 379  *  Chip reset
 380  */
 381
 382 static void snd_cs46xx_reset(cs46xx_t *chip)
 383 {
 384         int idx;
 385
 386         /*
 387          *  Write the reset bit of the SP control register.
 388          */
 389         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 390
 391         /*
 392          *  Write the control register.
 393          */
 394         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 395
 396         /*
 397          *  Clear the trap registers.
 398          */
 399         for (idx = 0; idx < 8; idx++) {
 400                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 401                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 402         }
 403         snd_cs46xx_poke(chip, BA1_DREG, 0);
 404
 405         /*
 406          *  Set the frame timer to reflect the number of cycles per frame.
 407          */
 408         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 409 }
 410
 411 static int cs46xx_wait_for_fifo(cs46xx_t * chip,int retry_timeout)
 412 {
 413         u32 i, status = 0;
 414         /*
 415          * Make sure the previous FIFO write operation has completed.
 416          */
 417         for(i = 0; i < 50; i++){
 418                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 419
 420                 if( !(status & SERBST_WBSY) )
 421                         break;
 422
 423                 mdelay(retry_timeout);
 424         }
 425
 426         if(status & SERBST_WBSY) {
 427                 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
 428
 429                 return -EINVAL;
 430         }
 431
 432         return 0;
 433 }
 434
 435 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t *chip)
 436 {
 437         int idx, powerdown = 0;
 438         unsigned int tmp;
 439
 440         /*
 441          *  See if the devices are powered down.  If so, we must power them up first
 442          *  or they will not respond.
 443          */
 444         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 445         if (!(tmp & CLKCR1_SWCE)) {
 446                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 447                 powerdown = 1;
 448         }
 449
 450         /*
 451          *  We want to clear out the serial port FIFOs so we don't end up playing
 452          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 453          *  with zero (silence).
 454          */
 455         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 456
 457         /*
 458          *  Fill all 256 sample FIFO locations.
 459          */
 460         for (idx = 0; idx < 0xFF; idx++) {
 461                 /*
 462                  *  Make sure the previous FIFO write operation has completed.
 463                  */
 464                 if (cs46xx_wait_for_fifo(chip,1)) {
 465                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 466
 467                         if (powerdown)
 468                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 469
 470                         break;
 471                 }
 472                 /*
 473                  *  Write the serial port FIFO index.
 474                  */
 475                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 476                 /*
 477                  *  Tell the serial port to load the new value into the FIFO location.
 478                  */
 479                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 480         }
 481         /*
 482          *  Now, if we powered up the devices, then power them back down again.
 483          *  This is kinda ugly, but should never happen.
 484          */
 485         if (powerdown)
 486                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 487 }
 488
 489 static void snd_cs46xx_proc_start(cs46xx_t *chip)
 490 {
 491         int cnt;
 492
 493         /*
 494          *  Set the frame timer to reflect the number of cycles per frame.
 495          */
 496         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 497         /*
 498          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 499          *  the SP control register.
 500          */
 501         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 502         /*
 503          *  Wait until the run at frame bit resets itself in the SP control
 504          *  register.
 505          */
 506         for (cnt = 0; cnt < 25; cnt++) {
 507                 udelay(50);
 508                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 509                         break;
 510         }
 511
 512         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 513                 snd_printk("SPCR_RUNFR never reset\n");
 514 }
 515
 516 static void snd_cs46xx_proc_stop(cs46xx_t *chip)
 517 {
 518         /*
 519          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 520          *  the SP control register.
 521          */
 522         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 523 }
 524
 525 /*
 526  *  Sample rate routines
 527  */
 528
 529 #define GOF_PER_SEC 200
 530
 531 static void snd_cs46xx_set_play_sample_rate(cs46xx_t *chip, unsigned int rate)
 532 {
 533         unsigned long flags;
 534         unsigned int tmp1, tmp2;
 535         unsigned int phiIncr;
 536         unsigned int correctionPerGOF, correctionPerSec;
 537
 538         /*
 539          *  Compute the values used to drive the actual sample rate conversion.
 540          *  The following formulas are being computed, using inline assembly
 541          *  since we need to use 64 bit arithmetic to compute the values:
 542          *
 543          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 544          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 545          *                                   GOF_PER_SEC)
 546          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 547          *                       GOF_PER_SEC * correctionPerGOF
 548          *
 549          *  i.e.
 550          *
 551          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 552          *  correctionPerGOF:correctionPerSec =
 553          *      dividend:remainder(ulOther / GOF_PER_SEC)
 554          */
 555         tmp1 = rate << 16;
 556         phiIncr = tmp1 / 48000;
 557         tmp1 -= phiIncr * 48000;
 558         tmp1 <<= 10;
 559         phiIncr <<= 10;
 560         tmp2 = tmp1 / 48000;
 561         phiIncr += tmp2;
 562         tmp1 -= tmp2 * 48000;
 563         correctionPerGOF = tmp1 / GOF_PER_SEC;
 564         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 565         correctionPerSec = tmp1;
 566
 567         /*
 568          *  Fill in the SampleRateConverter control block.
 569          */
 570         spin_lock_irqsave(&chip->reg_lock, flags);
 571         snd_cs46xx_poke(chip, BA1_PSRC,
 572           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 573         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 574         spin_unlock_irqrestore(&chip->reg_lock, flags);
 575 }
 576
 577 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t *chip, unsigned int rate)
 578 {
 579         unsigned long flags;
 580         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 581         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 582         unsigned int frameGroupLength, cnt;
 583
 584         /*
 585          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 586          *  Correct the value if an attempt is made to stray outside that limit.
 587          */
 588         if ((rate * 9) < 48000)
 589                 rate = 48000 / 9;
 590
 591         /*
 592          *  We can not capture at at rate greater than the Input Rate (48000).
 593          *  Return an error if an attempt is made to stray outside that limit.
 594          */
 595         if (rate > 48000)
 596                 rate = 48000;
 597
 598         /*
 599          *  Compute the values used to drive the actual sample rate conversion.
 600          *  The following formulas are being computed, using inline assembly
 601          *  since we need to use 64 bit arithmetic to compute the values:
 602          *
 603          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 604          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 605          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 606          *                                GOF_PER_SEC)
 607          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 608          *                          GOF_PER_SEC * correctionPerGOF
 609          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 610          *
 611          * i.e.
 612          *
 613          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 614          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 615          *     correctionPerGOF:correctionPerSec =
 616          *          dividend:remainder(ulOther / GOF_PER_SEC)
 617          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 618          */
 619
 620         tmp1 = rate << 16;
 621         coeffIncr = tmp1 / 48000;
 622         tmp1 -= coeffIncr * 48000;
 623         tmp1 <<= 7;
 624         coeffIncr <<= 7;
 625         coeffIncr += tmp1 / 48000;
 626         coeffIncr ^= 0xFFFFFFFF;
 627         coeffIncr++;
 628         tmp1 = 48000 << 16;
 629         phiIncr = tmp1 / rate;
 630         tmp1 -= phiIncr * rate;
 631         tmp1 <<= 10;
 632         phiIncr <<= 10;
 633         tmp2 = tmp1 / rate;
 634         phiIncr += tmp2;
 635         tmp1 -= tmp2 * rate;
 636         correctionPerGOF = tmp1 / GOF_PER_SEC;
 637         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 638         correctionPerSec = tmp1;
 639         initialDelay = ((48000 * 24) + rate - 1) / rate;
 640
 641         /*
 642          *  Fill in the VariDecimate control block.
 643          */
 644         spin_lock_irqsave(&chip->reg_lock, flags);
 645         snd_cs46xx_poke(chip, BA1_CSRC,
 646                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 647         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 648         snd_cs46xx_poke(chip, BA1_CD,
 649                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 650         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 651         spin_unlock_irqrestore(&chip->reg_lock, flags);
 652
 653         /*
 654          *  Figure out the frame group length for the write back task.  Basically,
 655          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 656          *  the output sample rate.
 657          */
 658         frameGroupLength = 1;
 659         for (cnt = 2; cnt <= 64; cnt *= 2) {
 660                 if (((rate / cnt) * cnt) != rate)
 661                         frameGroupLength *= 2;
 662         }
 663         if (((rate / 3) * 3) != rate) {
 664                 frameGroupLength *= 3;
 665         }
 666         for (cnt = 5; cnt <= 125; cnt *= 5) {
 667                 if (((rate / cnt) * cnt) != rate)
 668                         frameGroupLength *= 5;
 669         }
 670
 671         /*
 672          * Fill in the WriteBack control block.
 673          */
 674         spin_lock_irqsave(&chip->reg_lock, flags);
 675         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 676         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 677         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 678         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 679         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 680         spin_unlock_irqrestore(&chip->reg_lock, flags);
 681 }
 682
 683 /*
 684  *  PCM part
 685  */
 686
 687 static void snd_cs46xx_pb_trans_copy(snd_pcm_substream_t *substream,
 688                                      snd_pcm_indirect_t *rec, size_t bytes)
 689 {
 690         snd_pcm_runtime_t *runtime = substream->runtime;
 691         cs46xx_pcm_t * cpcm = runtime->private_data;
 692         memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 693 }
 694
 695 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t *substream)
 696 {
 697         snd_pcm_runtime_t *runtime = substream->runtime;
 698         cs46xx_pcm_t * cpcm = runtime->private_data;
 699         snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
 700         return 0;
 701 }
 702
 703 static void snd_cs46xx_cp_trans_copy(snd_pcm_substream_t *substream,
 704                                      snd_pcm_indirect_t *rec, size_t bytes)
 705 {
 706         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 707         snd_pcm_runtime_t *runtime = substream->runtime;
 708         memcpy(runtime->dma_area + rec->sw_data,
 709                chip->capt.hw_buf.area + rec->hw_data, bytes);
 710 }
 711
 712 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t *substream)
 713 {
 714         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 715         snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
 716         return 0;
 717 }
 718
 719 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t * substream)
 720 {
 721         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 722         size_t ptr;
 723         cs46xx_pcm_t *cpcm = substream->runtime->private_data;
 724         snd_assert (cpcm->pcm_channel,return -ENXIO);
 725
 726 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 727         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 728 #else
 729         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 730 #endif
 731         ptr -= cpcm->hw_buf.addr;
 732         return ptr >> cpcm->shift;
 733 }
 734
 735 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t * substream)
 736 {
 737         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 738         size_t ptr;
 739         cs46xx_pcm_t *cpcm = substream->runtime->private_data;
 740
 741 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 742         snd_assert (cpcm->pcm_channel,return -ENXIO);
 743         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 744 #else
 745         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 746 #endif
 747         ptr -= cpcm->hw_buf.addr;
 748         return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 749 }
 750
 751 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t * substream)
 752 {
 753         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 754         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 755         return ptr >> chip->capt.shift;
 756 }
 757
 758 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t * substream)
 759 {
 760         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 761         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 762         return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 763 }
 764
 765 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t * substream,
 766                                        int cmd)
 767 {
 768         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 769         /*snd_pcm_runtime_t *runtime = substream->runtime;*/
 770         int result = 0;
 771
 772 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 773         cs46xx_pcm_t *cpcm = substream->runtime->private_data;
 774         if (! cpcm->pcm_channel) {
 775                 return -ENXIO;
 776         }
 777 #endif
 778         switch (cmd) {
 779         case SNDRV_PCM_TRIGGER_START:
 780         case SNDRV_PCM_TRIGGER_RESUME:
 781 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 782                 /* magic value to unmute PCM stream  playback volume */
 783                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 784                                        SCBVolumeCtrl) << 2, 0x80008000);
 785
 786                 if (cpcm->pcm_channel->unlinked)
 787                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 788
 789                 if (substream->runtime->periods != CS46XX_FRAGS)
 790                         snd_cs46xx_playback_transfer(substream);
 791 #else
 792                 spin_lock(&chip->reg_lock);
 793                 if (substream->runtime->periods != CS46XX_FRAGS)
 794                         snd_cs46xx_playback_transfer(substream);
 795                 { unsigned int tmp;
 796                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 797                 tmp &= 0x0000ffff;
 798                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 799                 }
 800                 spin_unlock(&chip->reg_lock);
 801 #endif
 802                 break;
 803         case SNDRV_PCM_TRIGGER_STOP:
 804         case SNDRV_PCM_TRIGGER_SUSPEND:
 805 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 806                 /* magic mute channel */
 807                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 808                                        SCBVolumeCtrl) << 2, 0xffffffff);
 809
 810                 if (!cpcm->pcm_channel->unlinked)
 811                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 812 #else
 813                 spin_lock(&chip->reg_lock);
 814                 { unsigned int tmp;
 815                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 816                 tmp &= 0x0000ffff;
 817                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 818                 }
 819                 spin_unlock(&chip->reg_lock);
 820 #endif
 821                 break;
 822         default:
 823                 result = -EINVAL;
 824                 break;
 825         }
 826
 827         return result;
 828 }
 829
 830 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t * substream,
 831                                       int cmd)
 832 {
 833         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 834         unsigned int tmp;
 835         int result = 0;
 836
 837         spin_lock(&chip->reg_lock);
 838         switch (cmd) {
 839         case SNDRV_PCM_TRIGGER_START:
 840         case SNDRV_PCM_TRIGGER_RESUME:
 841                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 842                 tmp &= 0xffff0000;
 843                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
 844                 break;
 845         case SNDRV_PCM_TRIGGER_STOP:
 846         case SNDRV_PCM_TRIGGER_SUSPEND:
 847                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 848                 tmp &= 0xffff0000;
 849                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
 850                 break;
 851         default:
 852                 result = -EINVAL;
 853                 break;
 854         }
 855         spin_unlock(&chip->reg_lock);
 856
 857         return result;
 858 }
 859
 860 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 861 static int _cs46xx_adjust_sample_rate (cs46xx_t *chip, cs46xx_pcm_t *cpcm,
 862                                        int sample_rate)
 863 {
 864
 865         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
 866         if ( cpcm->pcm_channel == NULL) {
 867                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
 868                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
 869                 if (cpcm->pcm_channel == NULL) {
 870                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
 871                         return -ENOMEM;
 872                 }
 873                 cpcm->pcm_channel->sample_rate = sample_rate;
 874         } else
 875         /* if sample rate is changed */
 876         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
 877                 int unlinked = cpcm->pcm_channel->unlinked;
 878                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
 879
 880                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
 881                                                                          cpcm->hw_buf.addr,
 882                                                                          cpcm->pcm_channel_id)) == NULL) {
 883                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
 884                         return -ENOMEM;
 885                 }
 886
 887                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
 888                 cpcm->pcm_channel->sample_rate = sample_rate;
 889         }
 890
 891         return 0;
 892 }
 893 #endif
 894
 895
 896 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t * substream,
 897                                          snd_pcm_hw_params_t * hw_params)
 898 {
 899         snd_pcm_runtime_t *runtime = substream->runtime;
 900         cs46xx_pcm_t *cpcm;
 901         int err;
 902 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 903         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 904         int sample_rate = params_rate(hw_params);
 905         int period_size = params_period_bytes(hw_params);
 906 #endif
 907         cpcm = runtime->private_data;
 908
 909 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 910         snd_assert (sample_rate != 0, return -ENXIO);
 911
 912         down (&chip->spos_mutex);
 913
 914         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
 915                 up (&chip->spos_mutex);
 916                 return -ENXIO;
 917         }
 918
 919         snd_assert (cpcm->pcm_channel != NULL);
 920         if (!cpcm->pcm_channel) {
 921                 up (&chip->spos_mutex);
 922                 return -ENXIO;
 923         }
 924
 925
 926         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
 927                  up (&chip->spos_mutex);
 928                  return -EINVAL;
 929          }
 930
 931         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
 932                      period_size, params_periods(hw_params),
 933                      params_buffer_bytes(hw_params));
 934 #endif
 935
 936         if (params_periods(hw_params) == CS46XX_FRAGS) {
 937                 if (runtime->dma_area != cpcm->hw_buf.area)
 938                         snd_pcm_lib_free_pages(substream);
 939                 runtime->dma_area = cpcm->hw_buf.area;
 940                 runtime->dma_addr = cpcm->hw_buf.addr;
 941                 runtime->dma_bytes = cpcm->hw_buf.bytes;
 942
 943
 944 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 945                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 946                         substream->ops = &snd_cs46xx_playback_ops;
 947                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 948                         substream->ops = &snd_cs46xx_playback_rear_ops;
 949                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 950                         substream->ops = &snd_cs46xx_playback_clfe_ops;
 951                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 952                         substream->ops = &snd_cs46xx_playback_iec958_ops;
 953                 } else {
 954                         snd_assert(0);
 955                 }
 956 #else
 957                 substream->ops = &snd_cs46xx_playback_ops;
 958 #endif
 959
 960         } else {
 961                 if (runtime->dma_area == cpcm->hw_buf.area) {
 962                         runtime->dma_area = NULL;
 963                         runtime->dma_addr = 0;
 964                         runtime->dma_bytes = 0;
 965                 }
 966                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
 967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 968                         up (&chip->spos_mutex);
 969 #endif
 970                         return err;
 971                 }
 972
 973 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 974                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 975                         substream->ops = &snd_cs46xx_playback_indirect_ops;
 976                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 977                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
 978                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 979                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
 980                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 981                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
 982                 } else {
 983                         snd_assert(0);
 984                 }
 985 #else
 986                 substream->ops = &snd_cs46xx_playback_indirect_ops;
 987 #endif
 988
 989         }
 990
 991 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 992         up (&chip->spos_mutex);
 993 #endif
 994
 995         return 0;
 996 }
 997
 998 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t * substream)
 999 {
1000         /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
1001         snd_pcm_runtime_t *runtime = substream->runtime;
1002         cs46xx_pcm_t *cpcm;
1003
1004         cpcm = runtime->private_data;
1005
1006         /* if play_back open fails, then this function
1007            is called and cpcm can actually be NULL here */
1008         if (!cpcm) return -ENXIO;
1009
1010         if (runtime->dma_area != cpcm->hw_buf.area)
1011                 snd_pcm_lib_free_pages(substream);
1012
1013         runtime->dma_area = NULL;
1014         runtime->dma_addr = 0;
1015         runtime->dma_bytes = 0;
1016
1017         return 0;
1018 }
1019
1020 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t * substream)
1021 {
1022         unsigned int tmp;
1023         unsigned int pfie;
1024         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1025         snd_pcm_runtime_t *runtime = substream->runtime;
1026         cs46xx_pcm_t *cpcm;
1027
1028         cpcm = runtime->private_data;
1029
1030 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1031     snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1032
1033         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1034         pfie &= ~0x0000f03f;
1035 #else
1036         /* old dsp */
1037         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1038         pfie &= ~0x0000f03f;
1039 #endif
1040
1041         cpcm->shift = 2;
1042         /* if to convert from stereo to mono */
1043         if (runtime->channels == 1) {
1044                 cpcm->shift--;
1045                 pfie |= 0x00002000;
1046         }
1047         /* if to convert from 8 bit to 16 bit */
1048         if (snd_pcm_format_width(runtime->format) == 8) {
1049                 cpcm->shift--;
1050                 pfie |= 0x00001000;
1051         }
1052         /* if to convert to unsigned */
1053         if (snd_pcm_format_unsigned(runtime->format))
1054                 pfie |= 0x00008000;
1055
1056         /* Never convert byte order when sample stream is 8 bit */
1057         if (snd_pcm_format_width(runtime->format) != 8) {
1058                 /* convert from big endian to little endian */
1059                 if (snd_pcm_format_big_endian(runtime->format))
1060                         pfie |= 0x00004000;
1061         }
1062
1063         memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1064         cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1065         cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1066
1067 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1068
1069         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1070         tmp &= ~0x000003ff;
1071         tmp |= (4 << cpcm->shift) - 1;
1072         /* playback transaction count register */
1073         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1074
1075         /* playback format && interrupt enable */
1076         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1077 #else
1078         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1079         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1080         tmp &= ~0x000003ff;
1081         tmp |= (4 << cpcm->shift) - 1;
1082         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1083         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1084         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1085 #endif
1086
1087         return 0;
1088 }
1089
1090 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t * substream,
1091                                         snd_pcm_hw_params_t * hw_params)
1092 {
1093         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1094         snd_pcm_runtime_t *runtime = substream->runtime;
1095         int err;
1096
1097 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1098         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1099 #endif
1100         if (runtime->periods == CS46XX_FRAGS) {
1101                 if (runtime->dma_area != chip->capt.hw_buf.area)
1102                         snd_pcm_lib_free_pages(substream);
1103                 runtime->dma_area = chip->capt.hw_buf.area;
1104                 runtime->dma_addr = chip->capt.hw_buf.addr;
1105                 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1106                 substream->ops = &snd_cs46xx_capture_ops;
1107         } else {
1108                 if (runtime->dma_area == chip->capt.hw_buf.area) {
1109                         runtime->dma_area = NULL;
1110                         runtime->dma_addr = 0;
1111                         runtime->dma_bytes = 0;
1112                 }
1113                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1114                         return err;
1115                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t * substream)
1122 {
1123         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1124         snd_pcm_runtime_t *runtime = substream->runtime;
1125
1126         if (runtime->dma_area != chip->capt.hw_buf.area)
1127                 snd_pcm_lib_free_pages(substream);
1128         runtime->dma_area = NULL;
1129         runtime->dma_addr = 0;
1130         runtime->dma_bytes = 0;
1131
1132         return 0;
1133 }
1134
1135 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t * substream)
1136 {
1137         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1138         snd_pcm_runtime_t *runtime = substream->runtime;
1139
1140         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1141         chip->capt.shift = 2;
1142         memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1143         chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1144         chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1145         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1146
1147         return 0;
1148 }
1149
1150 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1151 {
1152         cs46xx_t *chip = dev_id;
1153         u32 status1;
1154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1155         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1156         u32 status2;
1157         int i;
1158         cs46xx_pcm_t *cpcm = NULL;
1159 #endif
1160
1161         /*
1162          *  Read the Interrupt Status Register to clear the interrupt
1163          */
1164         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1165         if ((status1 & 0x7fffffff) == 0) {
1166                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1167                 return IRQ_NONE;
1168         }
1169
1170 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1171         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1172
1173         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1174                 if (i <= 15) {
1175                         if ( status1 & (1 << i) ) {
1176                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1177                                         if (chip->capt.substream)
1178                                                 snd_pcm_period_elapsed(chip->capt.substream);
1179                                 } else {
1180                                         if (ins->pcm_channels[i].active &&
1181                                             ins->pcm_channels[i].private_data &&
1182                                             !ins->pcm_channels[i].unlinked) {
1183                                                 cpcm = ins->pcm_channels[i].private_data;
1184                                                 snd_pcm_period_elapsed(cpcm->substream);
1185                                         }
1186                                 }
1187                         }
1188                 } else {
1189                         if ( status2 & (1 << (i - 16))) {
1190                                 if (ins->pcm_channels[i].active &&
1191                                     ins->pcm_channels[i].private_data &&
1192                                     !ins->pcm_channels[i].unlinked) {
1193                                         cpcm = ins->pcm_channels[i].private_data;
1194                                         snd_pcm_period_elapsed(cpcm->substream);
1195                                 }
1196                         }
1197                 }
1198         }
1199
1200 #else
1201         /* old dsp */
1202         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1203                 if (chip->playback_pcm->substream)
1204                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1205         }
1206         if ((status1 & HISR_VC1) && chip->pcm) {
1207                 if (chip->capt.substream)
1208                         snd_pcm_period_elapsed(chip->capt.substream);
1209         }
1210 #endif
1211
1212         if ((status1 & HISR_MIDI) && chip->rmidi) {
1213                 unsigned char c;
1214
1215                 spin_lock(&chip->reg_lock);
1216                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1217                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1218                         if ((chip->midcr & MIDCR_RIE) == 0)
1219                                 continue;
1220                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1221                 }
1222                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1223                         if ((chip->midcr & MIDCR_TIE) == 0)
1224                                 break;
1225                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1226                                 chip->midcr &= ~MIDCR_TIE;
1227                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1228                                 break;
1229                         }
1230                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1231                 }
1232                 spin_unlock(&chip->reg_lock);
1233         }
1234         /*
1235          *  EOI to the PCI part....reenables interrupts
1236          */
1237         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1238
1239         return IRQ_HANDLED;
1240 }
1241
1242 static snd_pcm_hardware_t snd_cs46xx_playback =
1243 {
1244         .info =                 (SNDRV_PCM_INFO_MMAP |
1245                                  SNDRV_PCM_INFO_INTERLEAVED |
1246                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1247                                  SNDRV_PCM_INFO_RESUME),
1248         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1249                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1250                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1251         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1252         .rate_min =             5500,
1253         .rate_max =             48000,
1254         .channels_min =         1,
1255         .channels_max =         2,
1256         .buffer_bytes_max =     (256 * 1024),
1257         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1258         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1259         .periods_min =          CS46XX_FRAGS,
1260         .periods_max =          1024,
1261         .fifo_size =            0,
1262 };
1263
1264 static snd_pcm_hardware_t snd_cs46xx_capture =
1265 {
1266         .info =                 (SNDRV_PCM_INFO_MMAP |
1267                                  SNDRV_PCM_INFO_INTERLEAVED |
1268                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1269                                  SNDRV_PCM_INFO_RESUME),
1270         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1271         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1272         .rate_min =             5500,
1273         .rate_max =             48000,
1274         .channels_min =         2,
1275         .channels_max =         2,
1276         .buffer_bytes_max =     (256 * 1024),
1277         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1278         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1279         .periods_min =          CS46XX_FRAGS,
1280         .periods_max =          1024,
1281         .fifo_size =            0,
1282 };
1283
1284 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1285
1286 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1287
1288 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
1289         .count = ARRAY_SIZE(period_sizes),
1290         .list = period_sizes,
1291         .mask = 0
1292 };
1293
1294 #endif
1295
1296 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t *runtime)
1297 {
1298         cs46xx_pcm_t * cpcm = runtime->private_data;
1299         kfree(cpcm);
1300 }
1301
1302 static int _cs46xx_playback_open_channel (snd_pcm_substream_t * substream,int pcm_channel_id)
1303 {
1304         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1305         cs46xx_pcm_t * cpcm;
1306         snd_pcm_runtime_t *runtime = substream->runtime;
1307
1308         cpcm = kcalloc(1, sizeof(*cpcm), GFP_KERNEL);
1309         if (cpcm == NULL)
1310                 return -ENOMEM;
1311         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1312                                 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1313                 kfree(cpcm);
1314                 return -ENOMEM;
1315         }
1316
1317         runtime->hw = snd_cs46xx_playback;
1318         runtime->private_data = cpcm;
1319         runtime->private_free = snd_cs46xx_pcm_free_substream;
1320
1321         cpcm->substream = substream;
1322 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1323         down (&chip->spos_mutex);
1324         cpcm->pcm_channel = NULL;
1325         cpcm->pcm_channel_id = pcm_channel_id;
1326
1327
1328         snd_pcm_hw_constraint_list(runtime, 0,
1329                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1330                                    &hw_constraints_period_sizes);
1331
1332         up (&chip->spos_mutex);
1333 #else
1334         chip->playback_pcm = cpcm; /* HACK */
1335 #endif
1336
1337         if (chip->accept_valid)
1338                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1339         chip->active_ctrl(chip, 1);
1340
1341         return 0;
1342 }
1343
1344 static int snd_cs46xx_playback_open(snd_pcm_substream_t * substream)
1345 {
1346         snd_printdd("open front channel\n");
1347         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1348 }
1349
1350 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1351 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t * substream)
1352 {
1353         snd_printdd("open rear channel\n");
1354
1355         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1356 }
1357
1358 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t * substream)
1359 {
1360         snd_printdd("open center - LFE channel\n");
1361
1362         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1363 }
1364
1365 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t * substream)
1366 {
1367         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1368
1369         snd_printdd("open raw iec958 channel\n");
1370
1371         down (&chip->spos_mutex);
1372         cs46xx_iec958_pre_open (chip);
1373         up (&chip->spos_mutex);
1374
1375         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1376 }
1377
1378 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream);
1379
1380 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t * substream)
1381 {
1382         int err;
1383         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1384
1385         snd_printdd("close raw iec958 channel\n");
1386
1387         err = snd_cs46xx_playback_close(substream);
1388
1389         down (&chip->spos_mutex);
1390         cs46xx_iec958_post_close (chip);
1391         up (&chip->spos_mutex);
1392
1393         return err;
1394 }
1395 #endif
1396
1397 static int snd_cs46xx_capture_open(snd_pcm_substream_t * substream)
1398 {
1399         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1400
1401         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1402                                 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1403                 return -ENOMEM;
1404         chip->capt.substream = substream;
1405         substream->runtime->hw = snd_cs46xx_capture;
1406
1407         if (chip->accept_valid)
1408                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1409
1410         chip->active_ctrl(chip, 1);
1411
1412 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1413         snd_pcm_hw_constraint_list(substream->runtime, 0,
1414                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1415                                    &hw_constraints_period_sizes);
1416 #endif
1417         return 0;
1418 }
1419
1420 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream)
1421 {
1422         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1423         snd_pcm_runtime_t *runtime = substream->runtime;
1424         cs46xx_pcm_t * cpcm;
1425
1426         cpcm = runtime->private_data;
1427
1428         /* when playback_open fails, then cpcm can be NULL */
1429         if (!cpcm) return -ENXIO;
1430
1431 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1432         down (&chip->spos_mutex);
1433         if (cpcm->pcm_channel) {
1434                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1435                 cpcm->pcm_channel = NULL;
1436         }
1437         up (&chip->spos_mutex);
1438 #else
1439         chip->playback_pcm = NULL;
1440 #endif
1441
1442         cpcm->substream = NULL;
1443         snd_dma_free_pages(&cpcm->hw_buf);
1444         chip->active_ctrl(chip, -1);
1445
1446         return 0;
1447 }
1448
1449 static int snd_cs46xx_capture_close(snd_pcm_substream_t * substream)
1450 {
1451         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1452
1453         chip->capt.substream = NULL;
1454         snd_dma_free_pages(&chip->capt.hw_buf);
1455         chip->active_ctrl(chip, -1);
1456
1457         return 0;
1458 }
1459
1460 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1461 static snd_pcm_ops_t snd_cs46xx_playback_rear_ops = {
1462         .open =                 snd_cs46xx_playback_open_rear,
1463         .close =                snd_cs46xx_playback_close,
1464         .ioctl =                snd_pcm_lib_ioctl,
1465         .hw_params =            snd_cs46xx_playback_hw_params,
1466         .hw_free =              snd_cs46xx_playback_hw_free,
1467         .prepare =              snd_cs46xx_playback_prepare,
1468         .trigger =              snd_cs46xx_playback_trigger,
1469         .pointer =              snd_cs46xx_playback_direct_pointer,
1470 };
1471
1472 static snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops = {
1473         .open =                 snd_cs46xx_playback_open_rear,
1474         .close =                snd_cs46xx_playback_close,
1475         .ioctl =                snd_pcm_lib_ioctl,
1476         .hw_params =            snd_cs46xx_playback_hw_params,
1477         .hw_free =              snd_cs46xx_playback_hw_free,
1478         .prepare =              snd_cs46xx_playback_prepare,
1479         .trigger =              snd_cs46xx_playback_trigger,
1480         .pointer =              snd_cs46xx_playback_indirect_pointer,
1481         .ack =                  snd_cs46xx_playback_transfer,
1482 };
1483
1484 static snd_pcm_ops_t snd_cs46xx_playback_clfe_ops = {
1485         .open =                 snd_cs46xx_playback_open_clfe,
1486         .close =                snd_cs46xx_playback_close,
1487         .ioctl =                snd_pcm_lib_ioctl,
1488         .hw_params =            snd_cs46xx_playback_hw_params,
1489         .hw_free =              snd_cs46xx_playback_hw_free,
1490         .prepare =              snd_cs46xx_playback_prepare,
1491         .trigger =              snd_cs46xx_playback_trigger,
1492         .pointer =              snd_cs46xx_playback_direct_pointer,
1493 };
1494
1495 static snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops = {
1496         .open =                 snd_cs46xx_playback_open_clfe,
1497         .close =                snd_cs46xx_playback_close,
1498         .ioctl =                snd_pcm_lib_ioctl,
1499         .hw_params =            snd_cs46xx_playback_hw_params,
1500         .hw_free =              snd_cs46xx_playback_hw_free,
1501         .prepare =              snd_cs46xx_playback_prepare,
1502         .trigger =              snd_cs46xx_playback_trigger,
1503         .pointer =              snd_cs46xx_playback_indirect_pointer,
1504         .ack =                  snd_cs46xx_playback_transfer,
1505 };
1506
1507 static snd_pcm_ops_t snd_cs46xx_playback_iec958_ops = {
1508         .open =                 snd_cs46xx_playback_open_iec958,
1509         .close =                snd_cs46xx_playback_close_iec958,
1510         .ioctl =                snd_pcm_lib_ioctl,
1511         .hw_params =            snd_cs46xx_playback_hw_params,
1512         .hw_free =              snd_cs46xx_playback_hw_free,
1513         .prepare =              snd_cs46xx_playback_prepare,
1514         .trigger =              snd_cs46xx_playback_trigger,
1515         .pointer =              snd_cs46xx_playback_direct_pointer,
1516 };
1517
1518 static snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops = {
1519         .open =                 snd_cs46xx_playback_open_iec958,
1520         .close =                snd_cs46xx_playback_close_iec958,
1521         .ioctl =                snd_pcm_lib_ioctl,
1522         .hw_params =            snd_cs46xx_playback_hw_params,
1523         .hw_free =              snd_cs46xx_playback_hw_free,
1524         .prepare =              snd_cs46xx_playback_prepare,
1525         .trigger =              snd_cs46xx_playback_trigger,
1526         .pointer =              snd_cs46xx_playback_indirect_pointer,
1527         .ack =                  snd_cs46xx_playback_transfer,
1528 };
1529
1530 #endif
1531
1532 static snd_pcm_ops_t snd_cs46xx_playback_ops = {
1533         .open =                 snd_cs46xx_playback_open,
1534         .close =                snd_cs46xx_playback_close,
1535         .ioctl =                snd_pcm_lib_ioctl,
1536         .hw_params =            snd_cs46xx_playback_hw_params,
1537         .hw_free =              snd_cs46xx_playback_hw_free,
1538         .prepare =              snd_cs46xx_playback_prepare,
1539         .trigger =              snd_cs46xx_playback_trigger,
1540         .pointer =              snd_cs46xx_playback_direct_pointer,
1541 };
1542
1543 static snd_pcm_ops_t snd_cs46xx_playback_indirect_ops = {
1544         .open =                 snd_cs46xx_playback_open,
1545         .close =                snd_cs46xx_playback_close,
1546         .ioctl =                snd_pcm_lib_ioctl,
1547         .hw_params =            snd_cs46xx_playback_hw_params,
1548         .hw_free =              snd_cs46xx_playback_hw_free,
1549         .prepare =              snd_cs46xx_playback_prepare,
1550         .trigger =              snd_cs46xx_playback_trigger,
1551         .pointer =              snd_cs46xx_playback_indirect_pointer,
1552         .ack =                  snd_cs46xx_playback_transfer,
1553 };
1554
1555 static snd_pcm_ops_t snd_cs46xx_capture_ops = {
1556         .open =                 snd_cs46xx_capture_open,
1557         .close =                snd_cs46xx_capture_close,
1558         .ioctl =                snd_pcm_lib_ioctl,
1559         .hw_params =            snd_cs46xx_capture_hw_params,
1560         .hw_free =              snd_cs46xx_capture_hw_free,
1561         .prepare =              snd_cs46xx_capture_prepare,
1562         .trigger =              snd_cs46xx_capture_trigger,
1563         .pointer =              snd_cs46xx_capture_direct_pointer,
1564 };
1565
1566 static snd_pcm_ops_t snd_cs46xx_capture_indirect_ops = {
1567         .open =                 snd_cs46xx_capture_open,
1568         .close =                snd_cs46xx_capture_close,
1569         .ioctl =                snd_pcm_lib_ioctl,
1570         .hw_params =            snd_cs46xx_capture_hw_params,
1571         .hw_free =              snd_cs46xx_capture_hw_free,
1572         .prepare =              snd_cs46xx_capture_prepare,
1573         .trigger =              snd_cs46xx_capture_trigger,
1574         .pointer =              snd_cs46xx_capture_indirect_pointer,
1575         .ack =                  snd_cs46xx_capture_transfer,
1576 };
1577
1578 static void snd_cs46xx_pcm_free(snd_pcm_t *pcm)
1579 {
1580         cs46xx_t *chip = pcm->private_data;
1581         chip->pcm = NULL;
1582         snd_pcm_lib_preallocate_free_for_all(pcm);
1583 }
1584
1585 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1586 static void snd_cs46xx_pcm_rear_free(snd_pcm_t *pcm)
1587 {
1588         cs46xx_t *chip = pcm->private_data;
1589         chip->pcm_rear = NULL;
1590         snd_pcm_lib_preallocate_free_for_all(pcm);
1591 }
1592
1593 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t *pcm)
1594 {
1595         cs46xx_t *chip = pcm->private_data;
1596         chip->pcm_center_lfe = NULL;
1597         snd_pcm_lib_preallocate_free_for_all(pcm);
1598 }
1599
1600 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t *pcm)
1601 {
1602         cs46xx_t *chip = pcm->private_data;
1603         chip->pcm_iec958 = NULL;
1604         snd_pcm_lib_preallocate_free_for_all(pcm);
1605 }
1606
1607 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1608 #else
1609 #define MAX_PLAYBACK_CHANNELS   1
1610 #endif
1611
1612 int __devinit snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1613 {
1614         snd_pcm_t *pcm;
1615         int err;
1616
1617         if (rpcm)
1618                 *rpcm = NULL;
1619         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1620                 return err;
1621
1622         pcm->private_data = chip;
1623         pcm->private_free = snd_cs46xx_pcm_free;
1624
1625         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1626         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1627
1628         /* global setup */
1629         pcm->info_flags = 0;
1630         strcpy(pcm->name, "CS46xx");
1631         chip->pcm = pcm;
1632
1633         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1634                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1635
1636         if (rpcm)
1637                 *rpcm = pcm;
1638
1639         return 0;
1640 }
1641
1642
1643 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1644 int __devinit snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1645 {
1646         snd_pcm_t *pcm;
1647         int err;
1648
1649         if (rpcm)
1650                 *rpcm = NULL;
1651
1652         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1653                 return err;
1654
1655         pcm->private_data = chip;
1656         pcm->private_free = snd_cs46xx_pcm_rear_free;
1657
1658         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1659
1660         /* global setup */
1661         pcm->info_flags = 0;
1662         strcpy(pcm->name, "CS46xx - Rear");
1663         chip->pcm_rear = pcm;
1664
1665         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1666                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1667
1668         if (rpcm)
1669                 *rpcm = pcm;
1670
1671         return 0;
1672 }
1673
1674 int __devinit snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1675 {
1676         snd_pcm_t *pcm;
1677         int err;
1678
1679         if (rpcm)
1680                 *rpcm = NULL;
1681
1682         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1683                 return err;
1684
1685         pcm->private_data = chip;
1686         pcm->private_free = snd_cs46xx_pcm_center_lfe_free;
1687
1688         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1689
1690         /* global setup */
1691         pcm->info_flags = 0;
1692         strcpy(pcm->name, "CS46xx - Center LFE");
1693         chip->pcm_center_lfe = pcm;
1694
1695         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1696                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1697
1698         if (rpcm)
1699                 *rpcm = pcm;
1700
1701         return 0;
1702 }
1703
1704 int __devinit snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1705 {
1706         snd_pcm_t *pcm;
1707         int err;
1708
1709         if (rpcm)
1710                 *rpcm = NULL;
1711
1712         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1713                 return err;
1714
1715         pcm->private_data = chip;
1716         pcm->private_free = snd_cs46xx_pcm_iec958_free;
1717
1718         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1719
1720         /* global setup */
1721         pcm->info_flags = 0;
1722         strcpy(pcm->name, "CS46xx - IEC958");
1723         chip->pcm_rear = pcm;
1724
1725         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1726                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1727
1728         if (rpcm)
1729                 *rpcm = pcm;
1730
1731         return 0;
1732 }
1733 #endif
1734
1735 /*
1736  *  Mixer routines
1737  */
1738 static void snd_cs46xx_mixer_free_ac97_bus(ac97_bus_t *bus)
1739 {
1740         cs46xx_t *chip = bus->private_data;
1741
1742         chip->ac97_bus = NULL;
1743 }
1744
1745 static void snd_cs46xx_mixer_free_ac97(ac97_t *ac97)
1746 {
1747         cs46xx_t *chip = ac97->private_data;
1748
1749         snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1750                     (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1751                     return);
1752
1753         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1754                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1755                 chip->eapd_switch = NULL;
1756         }
1757         else
1758                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1759 }
1760
1761 static int snd_cs46xx_vol_info(snd_kcontrol_t *kcontrol,
1762                                snd_ctl_elem_info_t *uinfo)
1763 {
1764         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1765         uinfo->count = 2;
1766         uinfo->value.integer.min = 0;
1767         uinfo->value.integer.max = 0x7fff;
1768         return 0;
1769 }
1770
1771 static int snd_cs46xx_vol_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1772 {
1773         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1774         int reg = kcontrol->private_value;
1775         unsigned int val = snd_cs46xx_peek(chip, reg);
1776         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1777         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1778         return 0;
1779 }
1780
1781 static int snd_cs46xx_vol_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1782 {
1783         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1784         int reg = kcontrol->private_value;
1785         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1786                             (0xffff - ucontrol->value.integer.value[1]));
1787         unsigned int old = snd_cs46xx_peek(chip, reg);
1788         int change = (old != val);
1789
1790         if (change) {
1791                 snd_cs46xx_poke(chip, reg, val);
1792         }
1793
1794         return change;
1795 }
1796
1797 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1798
1799 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1800 {
1801         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1802
1803         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1804         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1805
1806         return 0;
1807 }
1808
1809 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1810 {
1811         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1812         int change = 0;
1813
1814         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1815             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1816                 cs46xx_dsp_set_dac_volume(chip,
1817                                           ucontrol->value.integer.value[0],
1818                                           ucontrol->value.integer.value[1]);
1819                 change = 1;
1820         }
1821
1822         return change;
1823 }
1824
1825 #if 0
1826 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1827 {
1828         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1829
1830         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1831         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1832         return 0;
1833 }
1834
1835 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1836 {
1837         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1838         int change = 0;
1839
1840         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1841             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1842                 cs46xx_dsp_set_iec958_volume (chip,
1843                                               ucontrol->value.integer.value[0],
1844                                               ucontrol->value.integer.value[1]);
1845                 change = 1;
1846         }
1847
1848         return change;
1849 }
1850 #endif
1851
1852 static int snd_mixer_boolean_info(snd_kcontrol_t *kcontrol,
1853                                   snd_ctl_elem_info_t *uinfo)
1854 {
1855         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1856         uinfo->count = 1;
1857         uinfo->value.integer.min = 0;
1858         uinfo->value.integer.max = 1;
1859         return 0;
1860 }
1861
1862 static int snd_cs46xx_iec958_get(snd_kcontrol_t *kcontrol,
1863                                  snd_ctl_elem_value_t *ucontrol)
1864 {
1865         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1866         int reg = kcontrol->private_value;
1867
1868         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1869                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1870         else
1871                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1872
1873         return 0;
1874 }
1875
1876 static int snd_cs46xx_iec958_put(snd_kcontrol_t *kcontrol,
1877                                   snd_ctl_elem_value_t *ucontrol)
1878 {
1879         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1880         int change, res;
1881
1882         switch (kcontrol->private_value) {
1883         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1884                 down (&chip->spos_mutex);
1885                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1886                 if (ucontrol->value.integer.value[0] && !change)
1887                         cs46xx_dsp_enable_spdif_out(chip);
1888                 else if (change && !ucontrol->value.integer.value[0])
1889                         cs46xx_dsp_disable_spdif_out(chip);
1890
1891                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1892                 up (&chip->spos_mutex);
1893                 break;
1894         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1895                 change = chip->dsp_spos_instance->spdif_status_in;
1896                 if (ucontrol->value.integer.value[0] && !change) {
1897                         cs46xx_dsp_enable_spdif_in(chip);
1898                         /* restore volume */
1899                 }
1900                 else if (change && !ucontrol->value.integer.value[0])
1901                         cs46xx_dsp_disable_spdif_in(chip);
1902
1903                 res = (change != chip->dsp_spos_instance->spdif_status_in);
1904                 break;
1905         default:
1906                 res = -EINVAL;
1907                 snd_assert(0, (void)0);
1908         }
1909
1910         return res;
1911 }
1912
1913 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t *kcontrol,
1914                                       snd_ctl_elem_value_t *ucontrol)
1915 {
1916         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1917         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1918
1919         if (ins->adc_input != NULL)
1920                 ucontrol->value.integer.value[0] = 1;
1921         else
1922                 ucontrol->value.integer.value[0] = 0;
1923
1924         return 0;
1925 }
1926
1927 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t *kcontrol,
1928                                       snd_ctl_elem_value_t *ucontrol)
1929 {
1930         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1931         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1932         int change = 0;
1933
1934         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1935                 cs46xx_dsp_enable_adc_capture(chip);
1936                 change = 1;
1937         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1938                 cs46xx_dsp_disable_adc_capture(chip);
1939                 change = 1;
1940         }
1941         return change;
1942 }
1943
1944 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t *kcontrol,
1945                                       snd_ctl_elem_value_t *ucontrol)
1946 {
1947         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1948         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1949
1950         if (ins->pcm_input != NULL)
1951                 ucontrol->value.integer.value[0] = 1;
1952         else
1953                 ucontrol->value.integer.value[0] = 0;
1954
1955         return 0;
1956 }
1957
1958
1959 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t *kcontrol,
1960                                       snd_ctl_elem_value_t *ucontrol)
1961 {
1962         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1963         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1964         int change = 0;
1965
1966         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1967                 cs46xx_dsp_enable_pcm_capture(chip);
1968                 change = 1;
1969         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1970                 cs46xx_dsp_disable_pcm_capture(chip);
1971                 change = 1;
1972         }
1973
1974         return change;
1975 }
1976
1977 static int snd_herc_spdif_select_get(snd_kcontrol_t *kcontrol,
1978                                      snd_ctl_elem_value_t *ucontrol)
1979 {
1980         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1981
1982         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1983
1984         if (val1 & EGPIODR_GPOE0)
1985                 ucontrol->value.integer.value[0] = 1;
1986         else
1987                 ucontrol->value.integer.value[0] = 0;
1988
1989         return 0;
1990 }
1991
1992 /*
1993  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1994  */
1995 static int snd_herc_spdif_select_put(snd_kcontrol_t *kcontrol,
1996                                        snd_ctl_elem_value_t *ucontrol)
1997 {
1998         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1999         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2000         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2001
2002         if (ucontrol->value.integer.value[0]) {
2003                 /* optical is default */
2004                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2005                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
2006                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2007                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2008         } else {
2009                 /* coaxial */
2010                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
2011                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2012         }
2013
2014         /* checking diff from the EGPIO direction register
2015            should be enough */
2016         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2017 }
2018
2019
2020 static int snd_cs46xx_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2021 {
2022         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2023         uinfo->count = 1;
2024         return 0;
2025 }
2026
2027 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t * kcontrol,
2028                                         snd_ctl_elem_value_t * ucontrol)
2029 {
2030         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2031         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2032
2033         down (&chip->spos_mutex);
2034         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2035         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2036         ucontrol->value.iec958.status[2] = 0;
2037         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2038         up (&chip->spos_mutex);
2039
2040         return 0;
2041 }
2042
2043 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t * kcontrol,
2044                                         snd_ctl_elem_value_t * ucontrol)
2045 {
2046         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2047         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2048         unsigned int val;
2049         int change;
2050
2051         down (&chip->spos_mutex);
2052         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2053                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2054                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2055                 /* left and right validity bit */
2056                 (1 << 13) | (1 << 12);
2057
2058
2059         change = (unsigned int)ins->spdif_csuv_default != val;
2060         ins->spdif_csuv_default = val;
2061
2062         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2063                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2064
2065         up (&chip->spos_mutex);
2066
2067         return change;
2068 }
2069
2070 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t * kcontrol,
2071                                      snd_ctl_elem_value_t * ucontrol)
2072 {
2073         ucontrol->value.iec958.status[0] = 0xff;
2074         ucontrol->value.iec958.status[1] = 0xff;
2075         ucontrol->value.iec958.status[2] = 0x00;
2076         ucontrol->value.iec958.status[3] = 0xff;
2077         return 0;
2078 }
2079
2080 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t * kcontrol,
2081                                          snd_ctl_elem_value_t * ucontrol)
2082 {
2083         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2084         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2085
2086         down (&chip->spos_mutex);
2087         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2088         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2089         ucontrol->value.iec958.status[2] = 0;
2090         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2091         up (&chip->spos_mutex);
2092
2093         return 0;
2094 }
2095
2096 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t * kcontrol,
2097                                         snd_ctl_elem_value_t * ucontrol)
2098 {
2099         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2100         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2101         unsigned int val;
2102         int change;
2103
2104         down (&chip->spos_mutex);
2105         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2106                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2107                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2108                 /* left and right validity bit */
2109                 (1 << 13) | (1 << 12);
2110
2111
2112         change = ins->spdif_csuv_stream != val;
2113         ins->spdif_csuv_stream = val;
2114
2115         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2116                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2117
2118         up (&chip->spos_mutex);
2119
2120         return change;
2121 }
2122
2123 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2124
2125
2126 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2127 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t *kcontrol,
2128                                         snd_ctl_elem_info_t *uinfo)
2129 {
2130         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2131         uinfo->count = 1;
2132         uinfo->value.integer.min = 0;
2133         uinfo->value.integer.max = 8;
2134         return 0;
2135 }
2136
2137 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t *kcontrol,
2138                                        snd_ctl_elem_value_t *ucontrol)
2139 {
2140         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2141         ucontrol->value.integer.value[0] = chip->current_gpio;
2142
2143         return 0;
2144 }
2145
2146 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t *kcontrol,
2147                                        snd_ctl_elem_value_t *ucontrol)
2148 {
2149         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2150         int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2151         chip->current_gpio = ucontrol->value.integer.value[0];
2152
2153         return change;
2154 }
2155
2156
2157 static int snd_cs46xx_egpio_get(snd_kcontrol_t *kcontrol,
2158                                        snd_ctl_elem_value_t *ucontrol)
2159 {
2160         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2161         int reg = kcontrol->private_value;
2162
2163         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2164         ucontrol->value.integer.value[0] =
2165                 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2166
2167         return 0;
2168 }
2169
2170 static int snd_cs46xx_egpio_put(snd_kcontrol_t *kcontrol,
2171                                        snd_ctl_elem_value_t *ucontrol)
2172 {
2173         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2174         int reg = kcontrol->private_value;
2175         int val = snd_cs46xx_peekBA0(chip, reg);
2176         int oldval = val;
2177         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2178
2179         if (ucontrol->value.integer.value[0])
2180                 val |= (1 << chip->current_gpio);
2181         else
2182                 val &= ~(1 << chip->current_gpio);
2183
2184         snd_cs46xx_pokeBA0(chip, reg,val);
2185         snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2186
2187         return (oldval != val);
2188 }
2189 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2190
2191 static snd_kcontrol_new_t snd_cs46xx_controls[] __devinitdata = {
2192 {
2193         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2194         .name = "DAC Volume",
2195         .info = snd_cs46xx_vol_info,
2196 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2197         .get = snd_cs46xx_vol_get,
2198         .put = snd_cs46xx_vol_put,
2199         .private_value = BA1_PVOL,
2200 #else
2201         .get = snd_cs46xx_vol_dac_get,
2202         .put = snd_cs46xx_vol_dac_put,
2203 #endif
2204 },
2205
2206 {
2207         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2208         .name = "ADC Volume",
2209         .info = snd_cs46xx_vol_info,
2210         .get = snd_cs46xx_vol_get,
2211         .put = snd_cs46xx_vol_put,
2212 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2213         .private_value = BA1_CVOL,
2214 #else
2215         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2216 #endif
2217 },
2218 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2219 {
2220         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2221         .name = "ADC Capture Switch",
2222         .info = snd_mixer_boolean_info,
2223         .get = snd_cs46xx_adc_capture_get,
2224         .put = snd_cs46xx_adc_capture_put
2225 },
2226 {
2227         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2228         .name = "DAC Capture Switch",
2229         .info = snd_mixer_boolean_info,
2230         .get = snd_cs46xx_pcm_capture_get,
2231         .put = snd_cs46xx_pcm_capture_put
2232 },
2233 {
2234         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2235         .name = "IEC958 Output Switch",
2236         .info = snd_mixer_boolean_info,
2237         .get = snd_cs46xx_iec958_get,
2238         .put = snd_cs46xx_iec958_put,
2239         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2240 },
2241 {
2242         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2243         .name = "IEC958 Input Switch",
2244         .info = snd_mixer_boolean_info,
2245         .get = snd_cs46xx_iec958_get,
2246         .put = snd_cs46xx_iec958_put,
2247         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2248 },
2249 #if 0
2250 /* Input IEC958 volume does not work for the moment. (Benny) */
2251 {
2252         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2253         .name = "IEC958 Input Volume",
2254         .info = snd_cs46xx_vol_info,
2255         .get = snd_cs46xx_vol_iec958_get,
2256         .put = snd_cs46xx_vol_iec958_put,
2257         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2258 },
2259 #endif
2260 {
2261         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2262         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2263         .info =  snd_cs46xx_spdif_info,
2264         .get =   snd_cs46xx_spdif_default_get,
2265         .put =   snd_cs46xx_spdif_default_put,
2266 },
2267 {
2268         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2269         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2270         .info =  snd_cs46xx_spdif_info,
2271         .get =   snd_cs46xx_spdif_mask_get,
2272         .access = SNDRV_CTL_ELEM_ACCESS_READ
2273 },
2274 {
2275         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2276         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2277         .info =  snd_cs46xx_spdif_info,
2278         .get =   snd_cs46xx_spdif_stream_get,
2279         .put =   snd_cs46xx_spdif_stream_put
2280 },
2281
2282 #endif
2283 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2284 {
2285         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2286         .name = "EGPIO select",
2287         .info = snd_cs46xx_egpio_select_info,
2288         .get = snd_cs46xx_egpio_select_get,
2289         .put = snd_cs46xx_egpio_select_put,
2290         .private_value = 0,
2291 },
2292 {
2293         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2294         .name = "EGPIO Input/Output",
2295         .info = snd_mixer_boolean_info,
2296         .get = snd_cs46xx_egpio_get,
2297         .put = snd_cs46xx_egpio_put,
2298         .private_value = BA0_EGPIODR,
2299 },
2300 {
2301         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2302         .name = "EGPIO CMOS/Open drain",
2303         .info = snd_mixer_boolean_info,
2304         .get = snd_cs46xx_egpio_get,
2305         .put = snd_cs46xx_egpio_put,
2306         .private_value = BA0_EGPIOPTR,
2307 },
2308 {
2309         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2310         .name = "EGPIO On/Off",
2311         .info = snd_mixer_boolean_info,
2312         .get = snd_cs46xx_egpio_get,
2313         .put = snd_cs46xx_egpio_put,
2314         .private_value = BA0_EGPIOSR,
2315 },
2316 #endif
2317 };
2318
2319 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2320 /* set primary cs4294 codec into Extended Audio Mode */
2321 static int snd_cs46xx_front_dup_get(snd_kcontrol_t *kcontrol,
2322                                     snd_ctl_elem_value_t *ucontrol)
2323 {
2324         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2325         unsigned short val;
2326         val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2327         ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2328         return 0;
2329 }
2330
2331 static int snd_cs46xx_front_dup_put(snd_kcontrol_t *kcontrol,
2332                                     snd_ctl_elem_value_t *ucontrol)
2333 {
2334         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2335         return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2336                                     AC97_CSR_ACMODE, 0x200,
2337                                     ucontrol->value.integer.value[0] ? 0 : 0x200);
2338 }
2339
2340 static snd_kcontrol_new_t snd_cs46xx_front_dup_ctl = {
2341         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2342         .name = "Duplicate Front",
2343         .info = snd_mixer_boolean_info,
2344         .get = snd_cs46xx_front_dup_get,
2345         .put = snd_cs46xx_front_dup_put,
2346 };
2347 #endif
2348
2349 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2350 /* Only available on the Hercules Game Theater XP soundcard */
2351 static snd_kcontrol_new_t snd_hercules_controls[] __devinitdata = {
2352 {
2353         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2354         .name = "Optical/Coaxial SPDIF Input Switch",
2355         .info = snd_mixer_boolean_info,
2356         .get = snd_herc_spdif_select_get,
2357         .put = snd_herc_spdif_select_put,
2358 },
2359 };
2360
2361
2362 static void snd_cs46xx_codec_reset (ac97_t * ac97)
2363 {
2364         unsigned long end_time;
2365         int err;
2366
2367         /* reset to defaults */
2368         snd_ac97_write(ac97, AC97_RESET, 0);
2369
2370         /* set the desired CODEC mode */
2371         if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2372                 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2373                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2374         } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2375                 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2376                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2377         } else {
2378                 snd_assert(0); /* should never happen ... */
2379         }
2380
2381         udelay(50);
2382
2383         /* it's necessary to wait awhile until registers are accessible after RESET */
2384         /* because the PCM or MASTER volume registers can be modified, */
2385         /* the REC_GAIN register is used for tests */
2386         end_time = jiffies + HZ;
2387         do {
2388                 unsigned short ext_mid;
2389
2390                 /* use preliminary reads to settle the communication */
2391                 snd_ac97_read(ac97, AC97_RESET);
2392                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2393                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2394                 /* modem? */
2395                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2396                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2397                         return;
2398
2399                 /* test if we can write to the record gain volume register */
2400                 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2401                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2402                         return;
2403
2404                 set_current_state(TASK_UNINTERRUPTIBLE);
2405                 schedule_timeout(HZ/100);
2406         } while (time_after_eq(end_time, jiffies));
2407
2408         snd_printk("CS46xx secondary codec dont respond!\n");
2409 }
2410 #endif
2411
2412 static int __devinit cs46xx_detect_codec(cs46xx_t *chip, int codec)
2413 {
2414         int idx, err;
2415         ac97_template_t ac97;
2416
2417         memset(&ac97, 0, sizeof(ac97));
2418         ac97.private_data = chip;
2419         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2420         ac97.num = codec;
2421         if (chip->amplifier_ctrl == amp_voyetra)
2422                 ac97.scaps = AC97_SCAP_INV_EAPD;
2423
2424         if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2425                 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2426                 udelay(10);
2427                 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2428                         snd_printdd("snd_cs46xx: seconadry codec not present\n");
2429                         return -ENXIO;
2430                 }
2431         }
2432
2433         snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2434         for (idx = 0; idx < 100; ++idx) {
2435                 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2436                         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2437                         return err;
2438                 }
2439                 set_current_state(TASK_INTERRUPTIBLE);
2440                 schedule_timeout(HZ/100);
2441         }
2442         snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2443         return -ENXIO;
2444 }
2445
2446 int __devinit snd_cs46xx_mixer(cs46xx_t *chip)
2447 {
2448         snd_card_t *card = chip->card;
2449         snd_ctl_elem_id_t id;
2450         int err;
2451         unsigned int idx;
2452         static ac97_bus_ops_t ops = {
2453 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2454                 .reset = snd_cs46xx_codec_reset,
2455 #endif
2456                 .write = snd_cs46xx_ac97_write,
2457                 .read = snd_cs46xx_ac97_read,
2458         };
2459
2460         /* detect primary codec */
2461         chip->nr_ac97_codecs = 0;
2462         snd_printdd("snd_cs46xx: detecting primary codec\n");
2463         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2464                 return err;
2465         chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2466
2467         if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2468                 return -ENXIO;
2469         chip->nr_ac97_codecs = 1;
2470
2471 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2472         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2473         /* try detect a secondary codec */
2474         if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2475                 chip->nr_ac97_codecs = 2;
2476 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2477
2478         /* add cs4630 mixer controls */
2479         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2480                 snd_kcontrol_t *kctl;
2481                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2482                 if ((err = snd_ctl_add(card, kctl)) < 0)
2483                         return err;
2484         }
2485
2486         /* get EAPD mixer switch (for voyetra hack) */
2487         memset(&id, 0, sizeof(id));
2488         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2489         strcpy(id.name, "External Amplifier");
2490         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2491
2492 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2493         if (chip->nr_ac97_codecs == 1) {
2494                 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2495                 if (id2 == 0x592b || id2 == 0x592d) {
2496                         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2497                         if (err < 0)
2498                                 return err;
2499                         snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2500                                              AC97_CSR_ACMODE, 0x200);
2501                 }
2502         }
2503         /* do soundcard specific mixer setup */
2504         if (chip->mixer_init) {
2505                 snd_printdd ("calling chip->mixer_init(chip);\n");
2506                 chip->mixer_init(chip);
2507         }
2508 #endif
2509
2510         /* turn on amplifier */
2511         chip->amplifier_ctrl(chip, 1);
2512
2513         return 0;
2514 }
2515
2516 /*
2517  *  RawMIDI interface
2518  */
2519
2520 static void snd_cs46xx_midi_reset(cs46xx_t *chip)
2521 {
2522         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2523         udelay(100);
2524         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2525 }
2526
2527 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t * substream)
2528 {
2529         cs46xx_t *chip = substream->rmidi->private_data;
2530
2531         chip->active_ctrl(chip, 1);
2532         spin_lock_irq(&chip->reg_lock);
2533         chip->uartm |= CS46XX_MODE_INPUT;
2534         chip->midcr |= MIDCR_RXE;
2535         chip->midi_input = substream;
2536         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2537                 snd_cs46xx_midi_reset(chip);
2538         } else {
2539                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2540         }
2541         spin_unlock_irq(&chip->reg_lock);
2542         return 0;
2543 }
2544
2545 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t * substream)
2546 {
2547         cs46xx_t *chip = substream->rmidi->private_data;
2548
2549         spin_lock_irq(&chip->reg_lock);
2550         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2551         chip->midi_input = NULL;
2552         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2553                 snd_cs46xx_midi_reset(chip);
2554         } else {
2555                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2556         }
2557         chip->uartm &= ~CS46XX_MODE_INPUT;
2558         spin_unlock_irq(&chip->reg_lock);
2559         chip->active_ctrl(chip, -1);
2560         return 0;
2561 }
2562
2563 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t * substream)
2564 {
2565         cs46xx_t *chip = substream->rmidi->private_data;
2566
2567         chip->active_ctrl(chip, 1);
2568
2569         spin_lock_irq(&chip->reg_lock);
2570         chip->uartm |= CS46XX_MODE_OUTPUT;
2571         chip->midcr |= MIDCR_TXE;
2572         chip->midi_output = substream;
2573         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2574                 snd_cs46xx_midi_reset(chip);
2575         } else {
2576                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2577         }
2578         spin_unlock_irq(&chip->reg_lock);
2579         return 0;
2580 }
2581
2582 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t * substream)
2583 {
2584         cs46xx_t *chip = substream->rmidi->private_data;
2585
2586         spin_lock_irq(&chip->reg_lock);
2587         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2588         chip->midi_output = NULL;
2589         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2590                 snd_cs46xx_midi_reset(chip);
2591         } else {
2592                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2593         }
2594         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2595         spin_unlock_irq(&chip->reg_lock);
2596         chip->active_ctrl(chip, -1);
2597         return 0;
2598 }
2599
2600 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2601 {
2602         unsigned long flags;
2603         cs46xx_t *chip = substream->rmidi->private_data;
2604
2605         spin_lock_irqsave(&chip->reg_lock, flags);
2606         if (up) {
2607                 if ((chip->midcr & MIDCR_RIE) == 0) {
2608                         chip->midcr |= MIDCR_RIE;
2609                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2610                 }
2611         } else {
2612                 if (chip->midcr & MIDCR_RIE) {
2613                         chip->midcr &= ~MIDCR_RIE;
2614                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2615                 }
2616         }
2617         spin_unlock_irqrestore(&chip->reg_lock, flags);
2618 }
2619
2620 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2621 {
2622         unsigned long flags;
2623         cs46xx_t *chip = substream->rmidi->private_data;
2624         unsigned char byte;
2625
2626         spin_lock_irqsave(&chip->reg_lock, flags);
2627         if (up) {
2628                 if ((chip->midcr & MIDCR_TIE) == 0) {
2629                         chip->midcr |= MIDCR_TIE;
2630                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2631                         while ((chip->midcr & MIDCR_TIE) &&
2632                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2633                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2634                                         chip->midcr &= ~MIDCR_TIE;
2635                                 } else {
2636                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2637                                 }
2638                         }
2639                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2640                 }
2641         } else {
2642                 if (chip->midcr & MIDCR_TIE) {
2643                         chip->midcr &= ~MIDCR_TIE;
2644                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2645                 }
2646         }
2647         spin_unlock_irqrestore(&chip->reg_lock, flags);
2648 }
2649
2650 static snd_rawmidi_ops_t snd_cs46xx_midi_output =
2651 {
2652         .open =         snd_cs46xx_midi_output_open,
2653         .close =        snd_cs46xx_midi_output_close,
2654         .trigger =      snd_cs46xx_midi_output_trigger,
2655 };
2656
2657 static snd_rawmidi_ops_t snd_cs46xx_midi_input =
2658 {
2659         .open =         snd_cs46xx_midi_input_open,
2660         .close =        snd_cs46xx_midi_input_close,
2661         .trigger =      snd_cs46xx_midi_input_trigger,
2662 };
2663
2664 int __devinit snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rrawmidi)
2665 {
2666         snd_rawmidi_t *rmidi;
2667         int err;
2668
2669         if (rrawmidi)
2670                 *rrawmidi = NULL;
2671         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2672                 return err;
2673         strcpy(rmidi->name, "CS46XX");
2674         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2675         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2676         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2677         rmidi->private_data = chip;
2678         chip->rmidi = rmidi;
2679         if (rrawmidi)
2680                 *rrawmidi = NULL;
2681         return 0;
2682 }
2683
2684
2685 /*
2686  * gameport interface
2687  */
2688
2689 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2690
2691 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2692 {
2693         cs46xx_t *chip = gameport_get_port_data(gameport);
2694
2695         snd_assert(chip, return);
2696         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2697 }
2698
2699 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2700 {
2701         cs46xx_t *chip = gameport_get_port_data(gameport);
2702
2703         snd_assert(chip, return 0);
2704         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2705 }
2706
2707 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2708 {
2709         cs46xx_t *chip = gameport_get_port_data(gameport);
2710         unsigned js1, js2, jst;
2711
2712         snd_assert(chip, return 0);
2713
2714         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2715         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2716         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2717
2718         *buttons = (~jst >> 4) & 0x0F;
2719
2720         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2721         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2722         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2723         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2724
2725         for(jst=0;jst<4;++jst)
2726                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2727         return 0;
2728 }
2729
2730 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2731 {
2732         switch (mode) {
2733         case GAMEPORT_MODE_COOKED:
2734                 return 0;
2735         case GAMEPORT_MODE_RAW:
2736                 return 0;
2737         default:
2738                 return -1;
2739         }
2740         return 0;
2741 }
2742
2743 int __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2744 {
2745         struct gameport *gp;
2746
2747         chip->gameport = gp = gameport_allocate_port();
2748         if (!gp) {
2749                 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
2750                 return -ENOMEM;
2751         }
2752
2753         gameport_set_name(gp, "CS46xx Gameport");
2754         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2755         gameport_set_dev_parent(gp, &chip->pci->dev);
2756         gameport_set_port_data(gp, chip);
2757
2758         gp->open = snd_cs46xx_gameport_open;
2759         gp->read = snd_cs46xx_gameport_read;
2760         gp->trigger = snd_cs46xx_gameport_trigger;
2761         gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2762
2763         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2764         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2765
2766         gameport_register_port(gp);
2767
2768         return 0;
2769 }
2770
2771 static inline void snd_cs46xx_remove_gameport(cs46xx_t *chip)
2772 {
2773         if (chip->gameport) {
2774                 gameport_unregister_port(chip->gameport);
2775                 chip->gameport = NULL;
2776         }
2777 }
2778 #else
2779 int __devinit snd_cs46xx_gameport(cs46xx_t *chip) { return -ENOSYS; }
2780 static inline void snd_cs46xx_remove_gameport(cs46xx_t *chip) { }
2781 #endif /* CONFIG_GAMEPORT */
2782
2783 /*
2784  *  proc interface
2785  */
2786
2787 static long snd_cs46xx_io_read(snd_info_entry_t *entry, void *file_private_data,
2788                                struct file *file, char __user *buf,
2789                                unsigned long count, unsigned long pos)
2790 {
2791         long size;
2792         snd_cs46xx_region_t *region = (snd_cs46xx_region_t *)entry->private_data;
2793
2794         size = count;
2795         if (pos + (size_t)size > region->size)
2796                 size = region->size - pos;
2797         if (size > 0) {
2798                 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2799                         return -EFAULT;
2800         }
2801         return size;
2802 }
2803
2804 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2805         .read = snd_cs46xx_io_read,
2806 };
2807
2808 static int __devinit snd_cs46xx_proc_init(snd_card_t * card, cs46xx_t *chip)
2809 {
2810         snd_info_entry_t *entry;
2811         int idx;
2812
2813         for (idx = 0; idx < 5; idx++) {
2814                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2815                 if (! snd_card_proc_new(card, region->name, &entry)) {
2816                         entry->content = SNDRV_INFO_CONTENT_DATA;
2817                         entry->private_data = chip;
2818                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2819                         entry->size = region->size;
2820                         entry->mode = S_IFREG | S_IRUSR;
2821                 }
2822         }
2823 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2824         cs46xx_dsp_proc_init(card, chip);
2825 #endif
2826         return 0;
2827 }
2828
2829 static int snd_cs46xx_proc_done(cs46xx_t *chip)
2830 {
2831 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2832         cs46xx_dsp_proc_done(chip);
2833 #endif
2834         return 0;
2835 }
2836
2837 /*
2838  * stop the h/w
2839  */
2840 static void snd_cs46xx_hw_stop(cs46xx_t *chip)
2841 {
2842         unsigned int tmp;
2843
2844         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2845         tmp &= ~0x0000f03f;
2846         tmp |=  0x00000010;
2847         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2848
2849         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2850         tmp &= ~0x0000003f;
2851         tmp |=  0x00000011;
2852         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2853
2854         /*
2855          *  Stop playback DMA.
2856          */
2857         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2858         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2859
2860         /*
2861          *  Stop capture DMA.
2862          */
2863         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2864         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2865
2866         /*
2867          *  Reset the processor.
2868          */
2869         snd_cs46xx_reset(chip);
2870
2871         snd_cs46xx_proc_stop(chip);
2872
2873         /*
2874          *  Power down the PLL.
2875          */
2876         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2877
2878         /*
2879          *  Turn off the Processor by turning off the software clock enable flag in
2880          *  the clock control register.
2881          */
2882         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2883         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2884 }
2885
2886
2887 static int snd_cs46xx_free(cs46xx_t *chip)
2888 {
2889         int idx;
2890
2891         snd_assert(chip != NULL, return -EINVAL);
2892
2893         if (chip->active_ctrl)
2894                 chip->active_ctrl(chip, 1);
2895
2896         snd_cs46xx_remove_gameport(chip);
2897
2898         if (chip->amplifier_ctrl)
2899                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2900
2901         snd_cs46xx_proc_done(chip);
2902
2903         if (chip->region.idx[0].resource)
2904                 snd_cs46xx_hw_stop(chip);
2905
2906         for (idx = 0; idx < 5; idx++) {
2907                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2908                 if (region->remap_addr)
2909                         iounmap(region->remap_addr);
2910                 if (region->resource) {
2911                         release_resource(region->resource);
2912                         kfree_nocheck(region->resource);
2913                 }
2914         }
2915         if (chip->irq >= 0)
2916                 free_irq(chip->irq, (void *)chip);
2917
2918         if (chip->active_ctrl)
2919                 chip->active_ctrl(chip, -chip->amplifier);
2920
2921 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2922         if (chip->dsp_spos_instance) {
2923                 cs46xx_dsp_spos_destroy(chip);
2924                 chip->dsp_spos_instance = NULL;
2925         }
2926 #endif
2927
2928         pci_disable_device(chip->pci);
2929         kfree(chip);
2930         return 0;
2931 }
2932
2933 static int snd_cs46xx_dev_free(snd_device_t *device)
2934 {
2935         cs46xx_t *chip = device->device_data;
2936         return snd_cs46xx_free(chip);
2937 }
2938
2939 /*
2940  *  initialize chip
2941  */
2942 static int snd_cs46xx_chip_init(cs46xx_t *chip)
2943 {
2944         int timeout;
2945
2946         /*
2947          *  First, blast the clock control register to zero so that the PLL starts
2948          *  out in a known state, and blast the master serial port control register
2949          *  to zero so that the serial ports also start out in a known state.
2950          */
2951         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2952         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2953
2954         /*
2955          *  If we are in AC97 mode, then we must set the part to a host controlled
2956          *  AC-link.  Otherwise, we won't be able to bring up the link.
2957          */
2958 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2959         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2960                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
2961         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2962 #else
2963         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2964 #endif
2965
2966         /*
2967          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2968          *  spec) and then drive it high.  This is done for non AC97 modes since
2969          *  there might be logic external to the CS461x that uses the ARST# line
2970          *  for a reset.
2971          */
2972         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2973 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2974         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2975 #endif
2976         udelay(50);
2977         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2978 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2979         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2980 #endif
2981
2982         /*
2983          *  The first thing we do here is to enable sync generation.  As soon
2984          *  as we start receiving bit clock, we'll start producing the SYNC
2985          *  signal.
2986          */
2987         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2988 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2989         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2990 #endif
2991
2992         /*
2993          *  Now wait for a short while to allow the AC97 part to start
2994          *  generating bit clock (so we don't try to start the PLL without an
2995          *  input clock).
2996          */
2997         mdelay(10);
2998
2999         /*
3000          *  Set the serial port timing configuration, so that
3001          *  the clock control circuit gets its clock from the correct place.
3002          */
3003         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3004
3005         /*
3006          *  Write the selected clock control setup to the hardware.  Do not turn on
3007          *  SWCE yet (if requested), so that the devices clocked by the output of
3008          *  PLL are not clocked until the PLL is stable.
3009          */
3010         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3011         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3012         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3013
3014         /*
3015          *  Power up the PLL.
3016          */
3017         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3018
3019         /*
3020          *  Wait until the PLL has stabilized.
3021          */
3022         set_current_state(TASK_UNINTERRUPTIBLE);
3023         schedule_timeout(HZ/10); /* 100ms */
3024
3025         /*
3026          *  Turn on clocking of the core so that we can setup the serial ports.
3027          */
3028         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3029
3030         /*
3031          * Enable FIFO  Host Bypass
3032          */
3033         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3034
3035         /*
3036          *  Fill the serial port FIFOs with silence.
3037          */
3038         snd_cs46xx_clear_serial_FIFOs(chip);
3039
3040         /*
3041          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3042          */
3043         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3044
3045         /*
3046          *  Write the serial port configuration to the part.  The master
3047          *  enable bit is not set until all other values have been written.
3048          */
3049         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3050         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3051         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3052
3053
3054 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3055         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3056         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3057         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3058         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3059         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3060 #endif
3061
3062         mdelay(5);
3063
3064
3065         /*
3066          * Wait for the codec ready signal from the AC97 codec.
3067          */
3068         timeout = 150;
3069         while (timeout-- > 0) {
3070                 /*
3071                  *  Read the AC97 status register to see if we've seen a CODEC READY
3072                  *  signal from the AC97 codec.
3073                  */
3074                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3075                         goto ok1;
3076                 set_current_state(TASK_UNINTERRUPTIBLE);
3077                 schedule_timeout((HZ+99)/100);
3078         }
3079
3080
3081         snd_printk("create - never read codec ready from AC'97\n");
3082         snd_printk("it is not probably bug, try to use CS4236 driver\n");
3083         return -EIO;
3084  ok1:
3085 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3086         {
3087                 int count;
3088                 for (count = 0; count < 150; count++) {
3089                         /* First, we want to wait for a short time. */
3090                         udelay(25);
3091
3092                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3093                                 break;
3094                 }
3095
3096                 /*
3097                  *  Make sure CODEC is READY.
3098                  */
3099                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3100                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3101         }
3102 #endif
3103
3104         /*
3105          *  Assert the vaid frame signal so that we can start sending commands
3106          *  to the AC97 codec.
3107          */
3108         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3109 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3110         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3111 #endif
3112
3113
3114         /*
3115          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3116          *  the codec is pumping ADC data across the AC-link.
3117          */
3118         timeout = 150;
3119         while (timeout-- > 0) {
3120                 /*
3121                  *  Read the input slot valid register and see if input slots 3 and
3122                  *  4 are valid yet.
3123                  */
3124                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3125                         goto ok2;
3126                 set_current_state(TASK_UNINTERRUPTIBLE);
3127                 schedule_timeout((HZ+99)/100);
3128         }
3129
3130 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3131         snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3132         return -EIO;
3133 #else
3134         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3135            Reloading the driver may help, if there's other soundcards
3136            with the same problem I would like to know. (Benny) */
3137
3138         snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3139         snd_printk("       Try reloading the ALSA driver, if you find something\n");
3140         snd_printk("       broken or not working on your soundcard upon\n");
3141         snd_printk("       this message please report to alsa-devel@lists.sourceforge.net\n");
3142
3143         return -EIO;
3144 #endif
3145  ok2:
3146
3147         /*
3148          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3149          *  commense the transfer of digital audio data to the AC97 codec.
3150          */
3151
3152         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3153
3154
3155         /*
3156          *  Power down the DAC and ADC.  We will power them up (if) when we need
3157          *  them.
3158          */
3159         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3160
3161         /*
3162          *  Turn off the Processor by turning off the software clock enable flag in
3163          *  the clock control register.
3164          */
3165         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3166         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3167
3168         return 0;
3169 }
3170
3171 /*
3172  *  start and load DSP
3173  */
3174 int __devinit snd_cs46xx_start_dsp(cs46xx_t *chip)
3175 {
3176         unsigned int tmp;
3177         /*
3178          *  Reset the processor.
3179          */
3180         snd_cs46xx_reset(chip);
3181         /*
3182          *  Download the image to the processor.
3183          */
3184 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3185 #if 0
3186         if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3187                 snd_printk(KERN_ERR "image download error\n");
3188                 return -EIO;
3189         }
3190 #endif
3191
3192         if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3193                 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3194                 return -EIO;
3195         }
3196
3197         if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3198                 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3199                 return -EIO;
3200         }
3201
3202         if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3203                 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3204                 return -EIO;
3205         }
3206
3207         if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3208                 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3209                 return -EIO;
3210         }
3211
3212         if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3213                 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3214                 return -EIO;
3215         }
3216
3217         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3218                 return -EIO;
3219 #else
3220         /* old image */
3221         if (snd_cs46xx_download_image(chip) < 0) {
3222                 snd_printk("image download error\n");
3223                 return -EIO;
3224         }
3225
3226         /*
3227          *  Stop playback DMA.
3228          */
3229         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3230         chip->play_ctl = tmp & 0xffff0000;
3231         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3232 #endif
3233
3234         /*
3235          *  Stop capture DMA.
3236          */
3237         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3238         chip->capt.ctl = tmp & 0x0000ffff;
3239         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3240
3241         mdelay(5);
3242
3243         snd_cs46xx_set_play_sample_rate(chip, 8000);
3244         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3245
3246         snd_cs46xx_proc_start(chip);
3247
3248         /*
3249          *  Enable interrupts on the part.
3250          */
3251         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3252
3253         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3254         tmp &= ~0x0000f03f;
3255         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3256
3257         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3258         tmp &= ~0x0000003f;
3259         tmp |=  0x00000001;
3260         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3261
3262 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3263         /* set the attenuation to 0dB */
3264         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3265         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3266 #endif
3267
3268         return 0;
3269 }
3270
3271
3272 /*
3273  *      AMP control - null AMP
3274  */
3275
3276 static void amp_none(cs46xx_t *chip, int change)
3277 {
3278 }
3279
3280 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3281 static int voyetra_setup_eapd_slot(cs46xx_t *chip)
3282 {
3283
3284         u32 idx, valid_slots,tmp,powerdown = 0;
3285         u16 modem_power,pin_config,logic_type;
3286
3287         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3288
3289         /*
3290          *  See if the devices are powered down.  If so, we must power them up first
3291          *  or they will not respond.
3292          */
3293         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3294
3295         if (!(tmp & CLKCR1_SWCE)) {
3296                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3297                 powerdown = 1;
3298         }
3299
3300         /*
3301          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3302          * stuff.
3303          */
3304         if(chip->nr_ac97_codecs != 2) {
3305                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3306                 return -EINVAL;
3307         }
3308
3309         modem_power = snd_cs46xx_codec_read (chip,
3310                                              AC97_EXTENDED_MSTATUS,
3311                                              CS46XX_SECONDARY_CODEC_INDEX);
3312         modem_power &=0xFEFF;
3313
3314         snd_cs46xx_codec_write(chip,
3315                                AC97_EXTENDED_MSTATUS, modem_power,
3316                                CS46XX_SECONDARY_CODEC_INDEX);
3317
3318         /*
3319          * Set GPIO pin's 7 and 8 so that they are configured for output.
3320          */
3321         pin_config = snd_cs46xx_codec_read (chip,
3322                                             AC97_GPIO_CFG,
3323                                             CS46XX_SECONDARY_CODEC_INDEX);
3324         pin_config &=0x27F;
3325
3326         snd_cs46xx_codec_write(chip,
3327                                AC97_GPIO_CFG, pin_config,
3328                                CS46XX_SECONDARY_CODEC_INDEX);
3329
3330         /*
3331          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3332          */
3333
3334         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3335                                            CS46XX_SECONDARY_CODEC_INDEX);
3336         logic_type &=0x27F;
3337
3338         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3339                                 CS46XX_SECONDARY_CODEC_INDEX);
3340
3341         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3342         valid_slots |= 0x200;
3343         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3344
3345         if ( cs46xx_wait_for_fifo(chip,1) ) {
3346           snd_printdd("FIFO is busy\n");
3347
3348           return -EINVAL;
3349         }
3350
3351         /*
3352          * Fill slots 12 with the correct value for the GPIO pins.
3353          */
3354         for(idx = 0x90; idx <= 0x9F; idx++) {
3355                 /*
3356                  * Initialize the fifo so that bits 7 and 8 are on.
3357                  *
3358                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3359                  * the left.  0x1800 corresponds to bits 7 and 8.
3360                  */
3361                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3362
3363                 /*
3364                  * Wait for command to complete
3365                  */
3366                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3367                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3368
3369                         return -EINVAL;
3370                 }
3371
3372                 /*
3373                  * Write the serial port FIFO index.
3374                  */
3375                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3376
3377                 /*
3378                  * Tell the serial port to load the new value into the FIFO location.
3379                  */
3380                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3381         }
3382
3383         /* wait for last command to complete */
3384         cs46xx_wait_for_fifo(chip,200);
3385
3386         /*
3387          *  Now, if we powered up the devices, then power them back down again.
3388          *  This is kinda ugly, but should never happen.
3389          */
3390         if (powerdown)
3391                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3392
3393         return 0;
3394 }
3395 #endif
3396
3397 /*
3398  *      Crystal EAPD mode
3399  */
3400
3401 static void amp_voyetra(cs46xx_t *chip, int change)
3402 {
3403         /* Manage the EAPD bit on the Crystal 4297
3404            and the Analog AD1885 */
3405
3406 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3407         int old = chip->amplifier;
3408 #endif
3409         int oval, val;
3410
3411         chip->amplifier += change;
3412         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3413                                      CS46XX_PRIMARY_CODEC_INDEX);
3414         val = oval;
3415         if (chip->amplifier) {
3416                 /* Turn the EAPD amp on */
3417                 val |= 0x8000;
3418         } else {
3419                 /* Turn the EAPD amp off */
3420                 val &= ~0x8000;
3421         }
3422         if (val != oval) {
3423                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3424                                        CS46XX_PRIMARY_CODEC_INDEX);
3425                 if (chip->eapd_switch)
3426                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3427                                        &chip->eapd_switch->id);
3428         }
3429
3430 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3431         if (chip->amplifier && !old) {
3432                 voyetra_setup_eapd_slot(chip);
3433         }
3434 #endif
3435 }
3436
3437 static void hercules_init(cs46xx_t *chip)
3438 {
3439         /* default: AMP off, and SPDIF input optical */
3440         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3441         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3442 }
3443
3444
3445 /*
3446  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3447  */
3448 static void amp_hercules(cs46xx_t *chip, int change)
3449 {
3450         int old = chip->amplifier;
3451         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3452         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3453
3454         chip->amplifier += change;
3455         if (chip->amplifier && !old) {
3456                 snd_printdd ("Hercules amplifier ON\n");
3457
3458                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3459                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3460                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3461                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3462         } else if (old && !chip->amplifier) {
3463                 snd_printdd ("Hercules amplifier OFF\n");
3464                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3465                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3466         }
3467 }
3468
3469 static void voyetra_mixer_init (cs46xx_t *chip)
3470 {
3471         snd_printdd ("initializing Voyetra mixer\n");
3472
3473         /* Enable SPDIF out */
3474         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3475         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3476 }
3477
3478 static void hercules_mixer_init (cs46xx_t *chip)
3479 {
3480 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3481         unsigned int idx;
3482         int err;
3483         snd_card_t *card = chip->card;
3484 #endif
3485
3486         /* set EGPIO to default */
3487         hercules_init(chip);
3488
3489         snd_printdd ("initializing Hercules mixer\n");
3490
3491 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3492         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3493                 snd_kcontrol_t *kctl;
3494
3495                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3496                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3497                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3498                         break;
3499                 }
3500         }
3501 #endif
3502 }
3503
3504
3505 #if 0
3506 /*
3507  *      Untested
3508  */
3509
3510 static void amp_voyetra_4294(cs46xx_t *chip, int change)
3511 {
3512         chip->amplifier += change;
3513
3514         if (chip->amplifier) {
3515                 /* Switch the GPIO pins 7 and 8 to open drain */
3516                 snd_cs46xx_codec_write(chip, 0x4C,
3517                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3518                 snd_cs46xx_codec_write(chip, 0x4E,
3519                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3520                 /* Now wake the AMP (this might be backwards) */
3521                 snd_cs46xx_codec_write(chip, 0x54,
3522                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3523         } else {
3524                 snd_cs46xx_codec_write(chip, 0x54,
3525                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3526         }
3527 }
3528 #endif
3529
3530
3531 /*
3532  * piix4 pci ids
3533  */
3534 #ifndef PCI_VENDOR_ID_INTEL
3535 #define PCI_VENDOR_ID_INTEL 0x8086
3536 #endif /* PCI_VENDOR_ID_INTEL */
3537
3538 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3539 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3540 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3541
3542 /*
3543  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3544  *      whenever we need to beat on the chip.
3545  *
3546  *      The original idea and code for this hack comes from David Kaiser at
3547  *      Linuxcare. Perhaps one day Crystal will document their chips well
3548  *      enough to make them useful.
3549  */
3550
3551 static void clkrun_hack(cs46xx_t *chip, int change)
3552 {
3553         u16 control, nval;
3554
3555         if (chip->acpi_dev == NULL)
3556                 return;
3557
3558         chip->amplifier += change;
3559
3560         /* Read ACPI port */
3561         nval = control = inw(chip->acpi_port + 0x10);
3562
3563         /* Flip CLKRUN off while running */
3564         if (! chip->amplifier)
3565                 nval |= 0x2000;
3566         else
3567                 nval &= ~0x2000;
3568         if (nval != control)
3569                 outw(nval, chip->acpi_port + 0x10);
3570 }
3571
3572
3573 /*
3574  * detect intel piix4
3575  */
3576 static void clkrun_init(cs46xx_t *chip)
3577 {
3578         u8 pp;
3579
3580         chip->acpi_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3581         if (chip->acpi_dev == NULL)
3582                 return;         /* Not a thinkpad thats for sure */
3583
3584         /* Find the control port */
3585         pci_read_config_byte(chip->acpi_dev, 0x41, &pp);
3586         chip->acpi_port = pp << 8;
3587 }
3588
3589
3590 /*
3591  * Card subid table
3592  */
3593
3594 struct cs_card_type
3595 {
3596         u16 vendor;
3597         u16 id;
3598         char *name;
3599         void (*init)(cs46xx_t *);
3600         void (*amp)(cs46xx_t *, int);
3601         void (*active)(cs46xx_t *, int);
3602         void (*mixer_init)(cs46xx_t *);
3603 };
3604
3605 static struct cs_card_type __devinitdata cards[] = {
3606         {
3607                 .vendor = 0x1489,
3608                 .id = 0x7001,
3609                 .name = "Genius Soundmaker 128 value",
3610                 /* nothing special */
3611         },
3612         {
3613                 .vendor = 0x5053,
3614                 .id = 0x3357,
3615                 .name = "Voyetra",
3616                 .amp = amp_voyetra,
3617                 .mixer_init = voyetra_mixer_init,
3618         },
3619         {
3620                 .vendor = 0x1071,
3621                 .id = 0x6003,
3622                 .name = "Mitac MI6020/21",
3623                 .amp = amp_voyetra,
3624         },
3625         {
3626                 .vendor = 0x14AF,
3627                 .id = 0x0050,
3628                 .name = "Hercules Game Theatre XP",
3629                 .amp = amp_hercules,
3630                 .mixer_init = hercules_mixer_init,
3631         },
3632         {
3633                 .vendor = 0x1681,
3634                 .id = 0x0050,
3635                 .name = "Hercules Game Theatre XP",
3636                 .amp = amp_hercules,
3637                 .mixer_init = hercules_mixer_init,
3638         },
3639         {
3640                 .vendor = 0x1681,
3641                 .id = 0x0051,
3642                 .name = "Hercules Game Theatre XP",
3643                 .amp = amp_hercules,
3644                 .mixer_init = hercules_mixer_init,
3645
3646         },
3647         {
3648                 .vendor = 0x1681,
3649                 .id = 0x0052,
3650                 .name = "Hercules Game Theatre XP",
3651                 .amp = amp_hercules,
3652                 .mixer_init = hercules_mixer_init,
3653         },
3654         {
3655                 .vendor = 0x1681,
3656                 .id = 0x0053,
3657                 .name = "Hercules Game Theatre XP",
3658                 .amp = amp_hercules,
3659                 .mixer_init = hercules_mixer_init,
3660         },
3661         {
3662                 .vendor = 0x1681,
3663                 .id = 0x0054,
3664                 .name = "Hercules Game Theatre XP",
3665                 .amp = amp_hercules,
3666                 .mixer_init = hercules_mixer_init,
3667         },
3668         /* Teratec */
3669         {
3670                 .vendor = 0x153b,
3671                 .id = 0x1136,
3672                 .name = "Terratec SiXPack 5.1",
3673         },
3674         /* Not sure if the 570 needs the clkrun hack */
3675         {
3676                 .vendor = PCI_VENDOR_ID_IBM,
3677                 .id = 0x0132,
3678                 .name = "Thinkpad 570",
3679                 .init = clkrun_init,
3680                 .active = clkrun_hack,
3681         },
3682         {
3683                 .vendor = PCI_VENDOR_ID_IBM,
3684                 .id = 0x0153,
3685                 .name = "Thinkpad 600X/A20/T20",
3686                 .init = clkrun_init,
3687                 .active = clkrun_hack,
3688         },
3689         {
3690                 .vendor = PCI_VENDOR_ID_IBM,
3691                 .id = 0x1010,
3692                 .name = "Thinkpad 600E (unsupported)",
3693         },
3694         {} /* terminator */
3695 };
3696
3697
3698 /*
3699  * APM support
3700  */
3701 #ifdef CONFIG_PM
3702 static int snd_cs46xx_suspend(snd_card_t *card, pm_message_t state)
3703 {
3704         cs46xx_t *chip = card->pm_private_data;
3705         int amp_saved;
3706
3707         snd_pcm_suspend_all(chip->pcm);
3708         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3709         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3710
3711         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3712         if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3713                 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3714
3715         amp_saved = chip->amplifier;
3716         /* turn off amp */
3717         chip->amplifier_ctrl(chip, -chip->amplifier);
3718         snd_cs46xx_hw_stop(chip);
3719         /* disable CLKRUN */
3720         chip->active_ctrl(chip, -chip->amplifier);
3721         chip->amplifier = amp_saved; /* restore the status */
3722         pci_disable_device(chip->pci);
3723         return 0;
3724 }
3725
3726 static int snd_cs46xx_resume(snd_card_t *card)
3727 {
3728         cs46xx_t *chip = card->pm_private_data;
3729         int amp_saved;
3730
3731         pci_enable_device(chip->pci);
3732         pci_set_master(chip->pci);
3733         amp_saved = chip->amplifier;
3734         chip->amplifier = 0;
3735         chip->active_ctrl(chip, 1); /* force to on */
3736
3737         snd_cs46xx_chip_init(chip);
3738
3739 #if 0
3740         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3741                                chip->ac97_general_purpose);
3742         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3743                                chip->ac97_powerdown);
3744         mdelay(10);
3745         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3746                                chip->ac97_powerdown);
3747         mdelay(5);
3748 #endif
3749
3750         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3751         if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3752                 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3753
3754         if (amp_saved)
3755                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3756         else
3757                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3758         chip->amplifier = amp_saved;
3759         return 0;
3760 }
3761 #endif /* CONFIG_PM */
3762
3763
3764 /*
3765  */
3766
3767 int __devinit snd_cs46xx_create(snd_card_t * card,
3768                       struct pci_dev * pci,
3769                       int external_amp, int thinkpad,
3770                       cs46xx_t ** rchip)
3771 {
3772         cs46xx_t *chip;
3773         int err, idx;
3774         snd_cs46xx_region_t *region;
3775         struct cs_card_type *cp;
3776         u16 ss_card, ss_vendor;
3777         static snd_device_ops_t ops = {
3778                 .dev_free =     snd_cs46xx_dev_free,
3779         };
3780
3781         *rchip = NULL;
3782
3783         /* enable PCI device */
3784         if ((err = pci_enable_device(pci)) < 0)
3785                 return err;
3786
3787         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
3788         if (chip == NULL) {
3789                 pci_disable_device(pci);
3790                 return -ENOMEM;
3791         }
3792         spin_lock_init(&chip->reg_lock);
3793 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3794         init_MUTEX(&chip->spos_mutex);
3795 #endif
3796         chip->card = card;
3797         chip->pci = pci;
3798         chip->irq = -1;
3799         chip->ba0_addr = pci_resource_start(pci, 0);
3800         chip->ba1_addr = pci_resource_start(pci, 1);
3801         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3802             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3803                 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip->ba0_addr, chip->ba1_addr);
3804                 snd_cs46xx_free(chip);
3805                 return -ENOMEM;
3806         }
3807
3808         region = &chip->region.name.ba0;
3809         strcpy(region->name, "CS46xx_BA0");
3810         region->base = chip->ba0_addr;
3811         region->size = CS46XX_BA0_SIZE;
3812
3813         region = &chip->region.name.data0;
3814         strcpy(region->name, "CS46xx_BA1_data0");
3815         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3816         region->size = CS46XX_BA1_DATA0_SIZE;
3817
3818         region = &chip->region.name.data1;
3819         strcpy(region->name, "CS46xx_BA1_data1");
3820         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3821         region->size = CS46XX_BA1_DATA1_SIZE;
3822
3823         region = &chip->region.name.pmem;
3824         strcpy(region->name, "CS46xx_BA1_pmem");
3825         region->base = chip->ba1_addr + BA1_SP_PMEM;
3826         region->size = CS46XX_BA1_PRG_SIZE;
3827
3828         region = &chip->region.name.reg;
3829         strcpy(region->name, "CS46xx_BA1_reg");
3830         region->base = chip->ba1_addr + BA1_SP_REG;
3831         region->size = CS46XX_BA1_REG_SIZE;
3832
3833         /* set up amp and clkrun hack */
3834         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3835         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3836
3837         for (cp = &cards[0]; cp->name; cp++) {
3838                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3839                         snd_printdd ("hack for %s enabled\n", cp->name);
3840
3841                         chip->amplifier_ctrl = cp->amp;
3842                         chip->active_ctrl = cp->active;
3843                         chip->mixer_init = cp->mixer_init;
3844
3845                         if (cp->init)
3846                                 cp->init(chip);
3847                         break;
3848                 }
3849         }
3850
3851         if (external_amp) {
3852                 snd_printk("Crystal EAPD support forced on.\n");
3853                 chip->amplifier_ctrl = amp_voyetra;
3854         }
3855
3856         if (thinkpad) {
3857                 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3858                 chip->active_ctrl = clkrun_hack;
3859                 clkrun_init(chip);
3860         }
3861
3862         if (chip->amplifier_ctrl == NULL)
3863                 chip->amplifier_ctrl = amp_none;
3864         if (chip->active_ctrl == NULL)
3865                 chip->active_ctrl = amp_none;
3866
3867         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3868
3869         pci_set_master(pci);
3870
3871         for (idx = 0; idx < 5; idx++) {
3872                 region = &chip->region.idx[idx];
3873                 if ((region->resource = request_mem_region(region->base, region->size, region->name)) == NULL) {
3874                         snd_printk("unable to request memory region 0x%lx-0x%lx\n", region->base, region->base + region->size - 1);
3875                         snd_cs46xx_free(chip);
3876                         return -EBUSY;
3877                 }
3878                 region->remap_addr = ioremap_nocache(region->base, region->size);
3879                 if (region->remap_addr == NULL) {
3880                         snd_printk("%s ioremap problem\n", region->name);
3881                         snd_cs46xx_free(chip);
3882                         return -ENOMEM;
3883                 }
3884         }
3885
3886         if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS46XX", (void *) chip)) {
3887                 snd_printk("unable to grab IRQ %d\n", pci->irq);
3888                 snd_cs46xx_free(chip);
3889                 return -EBUSY;
3890         }
3891         chip->irq = pci->irq;
3892
3893 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3894         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3895         if (chip->dsp_spos_instance == NULL) {
3896                 snd_cs46xx_free(chip);
3897                 return -ENOMEM;
3898         }
3899 #endif
3900
3901         err = snd_cs46xx_chip_init(chip);
3902         if (err < 0) {
3903                 snd_cs46xx_free(chip);
3904                 return err;
3905         }
3906
3907         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3908                 snd_cs46xx_free(chip);
3909                 return err;
3910         }
3911
3912         snd_cs46xx_proc_init(card, chip);
3913
3914         snd_card_set_pm_callback(card, snd_cs46xx_suspend, snd_cs46xx_resume, chip);
3915
3916         chip->active_ctrl(chip, -1); /* disable CLKRUN */
3917
3918         snd_card_set_dev(card, &pci->dev);
3919
3920         *rchip = chip;
3921         return 0;
3922 }