sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer controll.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <sound/driver.h>
  49 #include <linux/delay.h>
  50 #include <linux/pci.h>
  51 #include <linux/pm.h>
  52 #include <linux/init.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/slab.h>
  55 #include <linux/gameport.h>
  56
  57 #include <sound/core.h>
  58 #include <sound/control.h>
  59 #include <sound/info.h>
  60 #include <sound/pcm.h>
  61 #include <sound/pcm_params.h>
  62 #include <sound/cs46xx.h>
  63
  64 #include <asm/io.h>
  65
  66 #include "cs46xx_lib.h"
  67 #include "dsp_spos.h"
  68
  69 static void amp_voyetra(cs46xx_t *chip, int change);
  70
  71 static unsigned short snd_cs46xx_codec_read(cs46xx_t *chip,
  72                                             unsigned short reg,
  73                                             int codec_index)
  74 {
  75         int count;
  76         unsigned short result,tmp;
  77         u32 offset = 0;
  78         snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  79                      (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  80                      return -EINVAL);
  81
  82         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  83                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
  84
  85         /*
  86          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  87          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
  88          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
  89          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  90          *  5. if DCV not cleared, break and return error
  91          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
  92          */
  93
  94         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
  95
  96         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
  97         if ((tmp & ACCTL_VFRM) == 0) {
  98                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
  99                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 100                 mdelay(50);
 101                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 102                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 103
 104         }
 105
 106         /*
 107          *  Setup the AC97 control registers on the CS461x to send the
 108          *  appropriate command to the AC97 to perform the read.
 109          *  ACCAD = Command Address Register = 46Ch
 110          *  ACCDA = Command Data Register = 470h
 111          *  ACCTL = Control Register = 460h
 112          *  set DCV - will clear when process completed
 113          *  set CRW - Read command
 114          *  set VFRM - valid frame enabled
 115          *  set ESYN - ASYNC generation enabled
 116          *  set RSTN - ARST# inactive, AC97 codec not reset
 117          */
 118
 119         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 120         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 121         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 122                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 123                                    ACCTL_VFRM | ACCTL_ESYN |
 124                                    ACCTL_RSTN);
 125                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 126                                    ACCTL_VFRM | ACCTL_ESYN |
 127                                    ACCTL_RSTN);
 128         } else {
 129                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 130                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 131                                    ACCTL_RSTN);
 132         }
 133
 134         /*
 135          *  Wait for the read to occur.
 136          */
 137         for (count = 0; count < 1000; count++) {
 138                 /*
 139                  *  First, we want to wait for a short time.
 140                  */
 141                 udelay(10);
 142                 /*
 143                  *  Now, check to see if the read has completed.
 144                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 145                  */
 146                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 147                         goto ok1;
 148         }
 149
 150         snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 151         result = 0xffff;
 152         goto end;
 153
 154  ok1:
 155         /*
 156          *  Wait for the valid status bit to go active.
 157          */
 158         for (count = 0; count < 100; count++) {
 159                 /*
 160                  *  Read the AC97 status register.
 161                  *  ACSTS = Status Register = 464h
 162                  *  VSTS - Valid Status
 163                  */
 164                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 165                         goto ok2;
 166                 udelay(10);
 167         }
 168
 169         snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 170         result = 0xffff;
 171         goto end;
 172
 173  ok2:
 174         /*
 175          *  Read the data returned from the AC97 register.
 176          *  ACSDA = Status Data Register = 474h
 177          */
 178 #if 0
 179         printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 180                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 181                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 182 #endif
 183
 184         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 185         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 186  end:
 187         return result;
 188 }
 189
 190 static unsigned short snd_cs46xx_ac97_read(ac97_t * ac97,
 191                                             unsigned short reg)
 192 {
 193         cs46xx_t *chip = snd_magic_cast(cs46xx_t, ac97->private_data, return -ENXIO);
 194         unsigned short val;
 195         int codec_index = -1;
 196
 197         /* UGGLY: nr_ac97_codecs == 0 primery codec detection is in progress */
 198         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] || chip->nr_ac97_codecs == 0)
 199                 codec_index = CS46XX_PRIMARY_CODEC_INDEX;
 200         /* UGGLY: nr_ac97_codecs == 1 secondary codec detection is in progress */
 201         else if (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] || chip->nr_ac97_codecs == 1)
 202                 codec_index = CS46XX_SECONDARY_CODEC_INDEX;
 203         else
 204                 snd_assert(0, return 0xffff);
 205         chip->active_ctrl(chip, 1);
 206         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 207         chip->active_ctrl(chip, -1);
 208
 209         /* HACK: voyetra uses EAPD bit in the reverse way.
 210          * we flip the bit to show the mixer status correctly
 211          */
 212         if (reg == AC97_POWERDOWN && chip->amplifier_ctrl == amp_voyetra)
 213                 val ^= 0x8000;
 214
 215         return val;
 216 }
 217
 218
 219 static void snd_cs46xx_codec_write(cs46xx_t *chip,
 220                                    unsigned short reg,
 221                                    unsigned short val,
 222                                    int codec_index)
 223 {
 224         int count;
 225
 226         snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
 227                     (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
 228                     return);
 229
 230         /*
 231          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 232          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 233          *  3. Write ACCTL = Control Register = 460h for initiating the write
 234          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 235          *  5. if DCV not cleared, break and return error
 236          */
 237
 238         /*
 239          *  Setup the AC97 control registers on the CS461x to send the
 240          *  appropriate command to the AC97 to perform the read.
 241          *  ACCAD = Command Address Register = 46Ch
 242          *  ACCDA = Command Data Register = 470h
 243          *  ACCTL = Control Register = 460h
 244          *  set DCV - will clear when process completed
 245          *  reset CRW - Write command
 246          *  set VFRM - valid frame enabled
 247          *  set ESYN - ASYNC generation enabled
 248          *  set RSTN - ARST# inactive, AC97 codec not reset
 249          */
 250         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 251         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 252         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 253
 254         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 255                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 256                                    ACCTL_ESYN | ACCTL_RSTN);
 257                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 258                                    ACCTL_ESYN | ACCTL_RSTN);
 259         } else {
 260                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 261                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 262         }
 263
 264         for (count = 0; count < 4000; count++) {
 265                 /*
 266                  *  First, we want to wait for a short time.
 267                  */
 268                 udelay(10);
 269                 /*
 270                  *  Now, check to see if the write has completed.
 271                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 272                  */
 273                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 274                         return;
 275                 }
 276         }
 277         snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 278 }
 279
 280 static void snd_cs46xx_ac97_write(ac97_t *ac97,
 281                                    unsigned short reg,
 282                                    unsigned short val)
 283 {
 284         cs46xx_t *chip = snd_magic_cast(cs46xx_t, ac97->private_data, return);
 285         int codec_index = -1;
 286
 287         /* UGGLY: nr_ac97_codecs == 0 primery codec detection is in progress */
 288         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] || chip->nr_ac97_codecs == 0)
 289                 codec_index = CS46XX_PRIMARY_CODEC_INDEX;
 290         /* UGGLY: nr_ac97_codecs == 1 secondary codec detection is in progress */
 291         else  if (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] || chip->nr_ac97_codecs == 1)
 292                 codec_index = CS46XX_SECONDARY_CODEC_INDEX;
 293         else
 294                 snd_assert(0,return);
 295
 296         /* HACK: voyetra uses EAPD bit in the reverse way.
 297          * we flip the bit to show the mixer status correctly
 298          */
 299         if (reg == AC97_POWERDOWN && chip->amplifier_ctrl == amp_voyetra)
 300                 val ^= 0x8000;
 301
 302         chip->active_ctrl(chip, 1);
 303         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 304         chip->active_ctrl(chip, -1);
 305 }
 306
 307
 308 /*
 309  *  Chip initialization
 310  */
 311
 312 int snd_cs46xx_download(cs46xx_t *chip,
 313                         u32 *src,
 314                         unsigned long offset,
 315                         unsigned long len)
 316 {
 317         unsigned long dst;
 318         unsigned int bank = offset >> 16;
 319         offset = offset & 0xffff;
 320
 321         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 322         dst = chip->region.idx[bank+1].remap_addr + offset;
 323         len /= sizeof(u32);
 324
 325         /* writel already converts 32-bit value to right endianess */
 326         while (len-- > 0) {
 327                 writel(*src++, dst);
 328                 dst += sizeof(u32);
 329         }
 330         return 0;
 331 }
 332
 333 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 334
 335 #include "imgs/cwc4630.h"
 336 #include "imgs/cwcasync.h"
 337 #include "imgs/cwcsnoop.h"
 338 #include "imgs/cwcbinhack.h"
 339 #include "imgs/cwcdma.h"
 340
 341 int snd_cs46xx_clear_BA1(cs46xx_t *chip,
 342                          unsigned long offset,
 343                          unsigned long len)
 344 {
 345         unsigned long dst;
 346         unsigned int bank = offset >> 16;
 347         offset = offset & 0xffff;
 348
 349         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 350         dst = chip->region.idx[bank+1].remap_addr + offset;
 351         len /= sizeof(u32);
 352
 353         /* writel already converts 32-bit value to right endianess */
 354         while (len-- > 0) {
 355                 writel(0, dst);
 356                 dst += sizeof(u32);
 357         }
 358         return 0;
 359 }
 360
 361 #else /* old DSP image */
 362
 363 #include "cs46xx_image.h"
 364
 365 int snd_cs46xx_download_image(cs46xx_t *chip)
 366 {
 367         int idx, err;
 368         unsigned long offset = 0;
 369
 370         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 371                 if ((err = snd_cs46xx_download(chip,
 372                                                &BA1Struct.map[offset],
 373                                                BA1Struct.memory[idx].offset,
 374                                                BA1Struct.memory[idx].size)) < 0)
 375                         return err;
 376                 offset += BA1Struct.memory[idx].size >> 2;
 377         }
 378         return 0;
 379 }
 380 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 381
 382 /*
 383  *  Chip reset
 384  */
 385
 386 static void snd_cs46xx_reset(cs46xx_t *chip)
 387 {
 388         int idx;
 389
 390         /*
 391          *  Write the reset bit of the SP control register.
 392          */
 393         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 394
 395         /*
 396          *  Write the control register.
 397          */
 398         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 399
 400         /*
 401          *  Clear the trap registers.
 402          */
 403         for (idx = 0; idx < 8; idx++) {
 404                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 405                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 406         }
 407         snd_cs46xx_poke(chip, BA1_DREG, 0);
 408
 409         /*
 410          *  Set the frame timer to reflect the number of cycles per frame.
 411          */
 412         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 413 }
 414
 415 static int cs46xx_wait_for_fifo(cs46xx_t * chip,int retry_timeout)
 416 {
 417         u32 i, status = 0;
 418         /*
 419          * Make sure the previous FIFO write operation has completed.
 420          */
 421         for(i = 0; i < 50; i++){
 422                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 423
 424                 if( !(status & SERBST_WBSY) )
 425                         break;
 426
 427                 mdelay(retry_timeout);
 428         }
 429
 430         if(status & SERBST_WBSY) {
 431                 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
 432
 433                 return -EINVAL;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t *chip)
 440 {
 441         int idx, powerdown = 0;
 442         unsigned int tmp;
 443
 444         /*
 445          *  See if the devices are powered down.  If so, we must power them up first
 446          *  or they will not respond.
 447          */
 448         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 449         if (!(tmp & CLKCR1_SWCE)) {
 450                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 451                 powerdown = 1;
 452         }
 453
 454         /*
 455          *  We want to clear out the serial port FIFOs so we don't end up playing
 456          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 457          *  with zero (silence).
 458          */
 459         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 460
 461         /*
 462          *  Fill all 256 sample FIFO locations.
 463          */
 464         for (idx = 0; idx < 0xFF; idx++) {
 465                 /*
 466                  *  Make sure the previous FIFO write operation has completed.
 467                  */
 468                 if (cs46xx_wait_for_fifo(chip,1)) {
 469                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 470
 471                         if (powerdown)
 472                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 473
 474                         break;
 475                 }
 476                 /*
 477                  *  Write the serial port FIFO index.
 478                  */
 479                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 480                 /*
 481                  *  Tell the serial port to load the new value into the FIFO location.
 482                  */
 483                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 484         }
 485         /*
 486          *  Now, if we powered up the devices, then power them back down again.
 487          *  This is kinda ugly, but should never happen.
 488          */
 489         if (powerdown)
 490                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 491 }
 492
 493 static void snd_cs46xx_proc_start(cs46xx_t *chip)
 494 {
 495         int cnt;
 496
 497         /*
 498          *  Set the frame timer to reflect the number of cycles per frame.
 499          */
 500         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 501         /*
 502          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 503          *  the SP control register.
 504          */
 505         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 506         /*
 507          *  Wait until the run at frame bit resets itself in the SP control
 508          *  register.
 509          */
 510         for (cnt = 0; cnt < 25; cnt++) {
 511                 udelay(50);
 512                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 513                         break;
 514         }
 515
 516         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 517                 snd_printk("SPCR_RUNFR never reset\n");
 518 }
 519
 520 static void snd_cs46xx_proc_stop(cs46xx_t *chip)
 521 {
 522         /*
 523          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 524          *  the SP control register.
 525          */
 526         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 527 }
 528
 529 /*
 530  *  Sample rate routines
 531  */
 532
 533 #define GOF_PER_SEC 200
 534
 535 static void snd_cs46xx_set_play_sample_rate(cs46xx_t *chip, unsigned int rate)
 536 {
 537         unsigned long flags;
 538         unsigned int tmp1, tmp2;
 539         unsigned int phiIncr;
 540         unsigned int correctionPerGOF, correctionPerSec;
 541
 542         /*
 543          *  Compute the values used to drive the actual sample rate conversion.
 544          *  The following formulas are being computed, using inline assembly
 545          *  since we need to use 64 bit arithmetic to compute the values:
 546          *
 547          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 548          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 549          *                                   GOF_PER_SEC)
 550          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 551          *                       GOF_PER_SEC * correctionPerGOF
 552          *
 553          *  i.e.
 554          *
 555          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 556          *  correctionPerGOF:correctionPerSec =
 557          *      dividend:remainder(ulOther / GOF_PER_SEC)
 558          */
 559         tmp1 = rate << 16;
 560         phiIncr = tmp1 / 48000;
 561         tmp1 -= phiIncr * 48000;
 562         tmp1 <<= 10;
 563         phiIncr <<= 10;
 564         tmp2 = tmp1 / 48000;
 565         phiIncr += tmp2;
 566         tmp1 -= tmp2 * 48000;
 567         correctionPerGOF = tmp1 / GOF_PER_SEC;
 568         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 569         correctionPerSec = tmp1;
 570
 571         /*
 572          *  Fill in the SampleRateConverter control block.
 573          */
 574         spin_lock_irqsave(&chip->reg_lock, flags);
 575         snd_cs46xx_poke(chip, BA1_PSRC,
 576           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 577         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 578         spin_unlock_irqrestore(&chip->reg_lock, flags);
 579 }
 580
 581 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t *chip, unsigned int rate)
 582 {
 583         unsigned long flags;
 584         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 585         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 586         unsigned int frameGroupLength, cnt;
 587
 588         /*
 589          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 590          *  Correct the value if an attempt is made to stray outside that limit.
 591          */
 592         if ((rate * 9) < 48000)
 593                 rate = 48000 / 9;
 594
 595         /*
 596          *  We can not capture at at rate greater than the Input Rate (48000).
 597          *  Return an error if an attempt is made to stray outside that limit.
 598          */
 599         if (rate > 48000)
 600                 rate = 48000;
 601
 602         /*
 603          *  Compute the values used to drive the actual sample rate conversion.
 604          *  The following formulas are being computed, using inline assembly
 605          *  since we need to use 64 bit arithmetic to compute the values:
 606          *
 607          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 608          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 609          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 610          *                                GOF_PER_SEC)
 611          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 612          *                          GOF_PER_SEC * correctionPerGOF
 613          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 614          *
 615          * i.e.
 616          *
 617          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 618          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 619          *     correctionPerGOF:correctionPerSec =
 620          *          dividend:remainder(ulOther / GOF_PER_SEC)
 621          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 622          */
 623
 624         tmp1 = rate << 16;
 625         coeffIncr = tmp1 / 48000;
 626         tmp1 -= coeffIncr * 48000;
 627         tmp1 <<= 7;
 628         coeffIncr <<= 7;
 629         coeffIncr += tmp1 / 48000;
 630         coeffIncr ^= 0xFFFFFFFF;
 631         coeffIncr++;
 632         tmp1 = 48000 << 16;
 633         phiIncr = tmp1 / rate;
 634         tmp1 -= phiIncr * rate;
 635         tmp1 <<= 10;
 636         phiIncr <<= 10;
 637         tmp2 = tmp1 / rate;
 638         phiIncr += tmp2;
 639         tmp1 -= tmp2 * rate;
 640         correctionPerGOF = tmp1 / GOF_PER_SEC;
 641         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 642         correctionPerSec = tmp1;
 643         initialDelay = ((48000 * 24) + rate - 1) / rate;
 644
 645         /*
 646          *  Fill in the VariDecimate control block.
 647          */
 648         spin_lock_irqsave(&chip->reg_lock, flags);
 649         snd_cs46xx_poke(chip, BA1_CSRC,
 650                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 651         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 652         snd_cs46xx_poke(chip, BA1_CD,
 653                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 654         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 655         spin_unlock_irqrestore(&chip->reg_lock, flags);
 656
 657         /*
 658          *  Figure out the frame group length for the write back task.  Basically,
 659          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 660          *  the output sample rate.
 661          */
 662         frameGroupLength = 1;
 663         for (cnt = 2; cnt <= 64; cnt *= 2) {
 664                 if (((rate / cnt) * cnt) != rate)
 665                         frameGroupLength *= 2;
 666         }
 667         if (((rate / 3) * 3) != rate) {
 668                 frameGroupLength *= 3;
 669         }
 670         for (cnt = 5; cnt <= 125; cnt *= 5) {
 671                 if (((rate / cnt) * cnt) != rate)
 672                         frameGroupLength *= 5;
 673         }
 674
 675         /*
 676          * Fill in the WriteBack control block.
 677          */
 678         spin_lock_irqsave(&chip->reg_lock, flags);
 679         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 680         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 681         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 682         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 683         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 684         spin_unlock_irqrestore(&chip->reg_lock, flags);
 685 }
 686
 687 /*
 688  *  PCM part
 689  */
 690
 691 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t *substream)
 692 {
 693         /* cs46xx_t *chip = snd_pcm_substream_chip(substream); */
 694         snd_pcm_runtime_t *runtime = substream->runtime;
 695         cs46xx_pcm_t * cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
 696         snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
 697         snd_pcm_sframes_t diff = appl_ptr - cpcm->appl_ptr;
 698         int buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
 699
 700         if (diff) {
 701                 if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
 702                         diff += runtime->boundary;
 703                 cpcm->sw_ready += diff * (1 << cpcm->shift);
 704                 cpcm->appl_ptr = appl_ptr;
 705         }
 706         while (cpcm->hw_ready < buffer_size &&
 707                cpcm->sw_ready > 0) {
 708                 size_t hw_to_end = buffer_size - cpcm->hw_data;
 709                 size_t sw_to_end = cpcm->sw_bufsize - cpcm->sw_data;
 710                 size_t bytes = buffer_size - cpcm->hw_ready;
 711                 if (cpcm->sw_ready < (int)bytes)
 712                         bytes = cpcm->sw_ready;
 713                 if (hw_to_end < bytes)
 714                         bytes = hw_to_end;
 715                 if (sw_to_end < bytes)
 716                         bytes = sw_to_end;
 717                 memcpy(cpcm->hw_buf.area + cpcm->hw_data,
 718                        runtime->dma_area + cpcm->sw_data,
 719                        bytes);
 720                 cpcm->hw_data += bytes;
 721                 if ((int)cpcm->hw_data == buffer_size)
 722                         cpcm->hw_data = 0;
 723                 cpcm->sw_data += bytes;
 724                 if (cpcm->sw_data == cpcm->sw_bufsize)
 725                         cpcm->sw_data = 0;
 726                 cpcm->hw_ready += bytes;
 727                 cpcm->sw_ready -= bytes;
 728         }
 729         return 0;
 730 }
 731
 732 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t *substream)
 733 {
 734         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 735         snd_pcm_runtime_t *runtime = substream->runtime;
 736         snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
 737         snd_pcm_sframes_t diff = appl_ptr - chip->capt.appl_ptr;
 738         int buffer_size = runtime->period_size * CS46XX_FRAGS << chip->capt.shift;
 739
 740         if (diff) {
 741                 if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
 742                         diff += runtime->boundary;
 743                 chip->capt.sw_ready -= diff * (1 << chip->capt.shift);
 744                 chip->capt.appl_ptr = appl_ptr;
 745         }
 746         while (chip->capt.hw_ready > 0 &&
 747                chip->capt.sw_ready < (int)chip->capt.sw_bufsize) {
 748                 size_t hw_to_end = buffer_size - chip->capt.hw_data;
 749                 size_t sw_to_end = chip->capt.sw_bufsize - chip->capt.sw_data;
 750                 size_t bytes = chip->capt.sw_bufsize - chip->capt.sw_ready;
 751                 if (chip->capt.hw_ready < (int)bytes)
 752                         bytes = chip->capt.hw_ready;
 753                 if (hw_to_end < bytes)
 754                         bytes = hw_to_end;
 755                 if (sw_to_end < bytes)
 756                         bytes = sw_to_end;
 757                 memcpy(runtime->dma_area + chip->capt.sw_data,
 758                        chip->capt.hw_buf.area + chip->capt.hw_data,
 759                        bytes);
 760                 chip->capt.hw_data += bytes;
 761                 if ((int)chip->capt.hw_data == buffer_size)
 762                         chip->capt.hw_data = 0;
 763                 chip->capt.sw_data += bytes;
 764                 if (chip->capt.sw_data == chip->capt.sw_bufsize)
 765                         chip->capt.sw_data = 0;
 766                 chip->capt.hw_ready -= bytes;
 767                 chip->capt.sw_ready += bytes;
 768         }
 769         return 0;
 770 }
 771
 772 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t * substream)
 773 {
 774         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 775         size_t ptr;
 776         cs46xx_pcm_t *cpcm = snd_magic_cast(cs46xx_pcm_t, substream->runtime->private_data, return -ENXIO);
 777         snd_assert (cpcm->pcm_channel,return -ENXIO);
 778
 779 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 780         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 781 #else
 782         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 783 #endif
 784         ptr -= cpcm->hw_buf.addr;
 785         return ptr >> cpcm->shift;
 786 }
 787
 788 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t * substream)
 789 {
 790         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 791         size_t ptr;
 792         cs46xx_pcm_t *cpcm = snd_magic_cast(cs46xx_pcm_t, substream->runtime->private_data, return -ENXIO);
 793         ssize_t bytes;
 794         int buffer_size = substream->runtime->period_size * CS46XX_FRAGS << cpcm->shift;
 795
 796 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 797         snd_assert (cpcm->pcm_channel,return -ENXIO);
 798         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 799 #else
 800         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 801 #endif
 802         ptr -= cpcm->hw_buf.addr;
 803
 804         bytes = ptr - cpcm->hw_io;
 805
 806         if (bytes < 0)
 807                 bytes += buffer_size;
 808         cpcm->hw_io = ptr;
 809         cpcm->hw_ready -= bytes;
 810         cpcm->sw_io += bytes;
 811         if (cpcm->sw_io >= cpcm->sw_bufsize)
 812                 cpcm->sw_io -= cpcm->sw_bufsize;
 813         snd_cs46xx_playback_transfer(substream);
 814         return cpcm->sw_io >> cpcm->shift;
 815 }
 816
 817 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t * substream)
 818 {
 819         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 820         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 821         return ptr >> chip->capt.shift;
 822 }
 823
 824 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t * substream)
 825 {
 826         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 827         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 828         ssize_t bytes = ptr - chip->capt.hw_io;
 829         int buffer_size = substream->runtime->period_size * CS46XX_FRAGS << chip->capt.shift;
 830
 831         if (bytes < 0)
 832                 bytes += buffer_size;
 833         chip->capt.hw_io = ptr;
 834         chip->capt.hw_ready += bytes;
 835         chip->capt.sw_io += bytes;
 836         if (chip->capt.sw_io >= chip->capt.sw_bufsize)
 837                 chip->capt.sw_io -= chip->capt.sw_bufsize;
 838         snd_cs46xx_capture_transfer(substream);
 839         return chip->capt.sw_io >> chip->capt.shift;
 840 }
 841
 842 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t * substream,
 843                                        int cmd)
 844 {
 845         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 846         /*snd_pcm_runtime_t *runtime = substream->runtime;*/
 847         int result = 0;
 848
 849 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 850         cs46xx_pcm_t *cpcm = snd_magic_cast(cs46xx_pcm_t, substream->runtime->private_data, return -ENXIO);
 851 #else
 852         spin_lock(&chip->reg_lock);
 853 #endif
 854
 855 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 856
 857         if (! cpcm->pcm_channel) {
 858                 return -ENXIO;
 859         }
 860 #endif
 861         switch (cmd) {
 862         case SNDRV_PCM_TRIGGER_START:
 863         case SNDRV_PCM_TRIGGER_RESUME:
 864 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 865                 /* magic value to unmute PCM stream  playback volume */
 866                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 867                                        SCBVolumeCtrl) << 2, 0x80008000);
 868
 869                 if (cpcm->pcm_channel->unlinked)
 870                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 871
 872                 if (substream->runtime->periods != CS46XX_FRAGS)
 873                         snd_cs46xx_playback_transfer(substream);
 874 #else
 875                 if (substream->runtime->periods != CS46XX_FRAGS)
 876                         snd_cs46xx_playback_transfer(substream);
 877                 { unsigned int tmp;
 878                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 879                 tmp &= 0x0000ffff;
 880                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 881                 }
 882 #endif
 883                 break;
 884         case SNDRV_PCM_TRIGGER_STOP:
 885         case SNDRV_PCM_TRIGGER_SUSPEND:
 886 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 887                 /* magic mute channel */
 888                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 889                                        SCBVolumeCtrl) << 2, 0xffffffff);
 890
 891                 if (!cpcm->pcm_channel->unlinked)
 892                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 893 #else
 894                 { unsigned int tmp;
 895                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 896                 tmp &= 0x0000ffff;
 897                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 898                 }
 899 #endif
 900                 break;
 901         default:
 902                 result = -EINVAL;
 903                 break;
 904         }
 905
 906 #ifndef CONFIG_SND_CS46XX_NEW_DSP
 907         spin_unlock(&chip->reg_lock);
 908 #endif
 909
 910         return result;
 911 }
 912
 913 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t * substream,
 914                                       int cmd)
 915 {
 916         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 917         unsigned int tmp;
 918         int result = 0;
 919
 920         spin_lock(&chip->reg_lock);
 921         switch (cmd) {
 922         case SNDRV_PCM_TRIGGER_START:
 923         case SNDRV_PCM_TRIGGER_RESUME:
 924                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 925                 tmp &= 0xffff0000;
 926                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
 927                 break;
 928         case SNDRV_PCM_TRIGGER_STOP:
 929         case SNDRV_PCM_TRIGGER_SUSPEND:
 930                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 931                 tmp &= 0xffff0000;
 932                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
 933                 break;
 934         default:
 935                 result = -EINVAL;
 936                 break;
 937         }
 938         spin_unlock(&chip->reg_lock);
 939
 940         return result;
 941 }
 942
 943 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 944 static int _cs46xx_adjust_sample_rate (cs46xx_t *chip, cs46xx_pcm_t *cpcm,
 945                                        int sample_rate)
 946 {
 947
 948         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
 949         if ( cpcm->pcm_channel == NULL) {
 950                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
 951                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
 952                 if (cpcm->pcm_channel == NULL) {
 953                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
 954                         return -ENOMEM;
 955                 }
 956                 cpcm->pcm_channel->sample_rate = sample_rate;
 957         } else
 958         /* if sample rate is changed */
 959         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
 960                 int unlinked = cpcm->pcm_channel->unlinked;
 961                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
 962
 963                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
 964                                                                          cpcm->hw_buf.addr,
 965                                                                          cpcm->pcm_channel_id)) == NULL) {
 966                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
 967                         return -ENOMEM;
 968                 }
 969
 970                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
 971                 cpcm->pcm_channel->sample_rate = sample_rate;
 972         }
 973
 974         return 0;
 975 }
 976 #endif
 977
 978
 979 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t * substream,
 980                                          snd_pcm_hw_params_t * hw_params)
 981 {
 982         snd_pcm_runtime_t *runtime = substream->runtime;
 983         cs46xx_pcm_t *cpcm;
 984         int err;
 985 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 986         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 987         int sample_rate = params_rate(hw_params);
 988         int period_size = params_period_bytes(hw_params);
 989 #endif
 990         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
 991
 992 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 993         snd_assert (sample_rate != 0, return -ENXIO);
 994
 995         down (&chip->spos_mutex);
 996
 997         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
 998                 up (&chip->spos_mutex);
 999                 return -ENXIO;
1000         }
1001
1002         snd_assert (cpcm->pcm_channel != NULL);
1003         if (!cpcm->pcm_channel) {
1004                 up (&chip->spos_mutex);
1005                 return -ENXIO;
1006         }
1007
1008
1009         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1010                  up (&chip->spos_mutex);
1011                  return -EINVAL;
1012          }
1013
1014         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
1015                      period_size, params_periods(hw_params),
1016                      params_buffer_bytes(hw_params));
1017 #endif
1018
1019         if (params_periods(hw_params) == CS46XX_FRAGS) {
1020                 if (runtime->dma_area != cpcm->hw_buf.area)
1021                         snd_pcm_lib_free_pages(substream);
1022                 runtime->dma_area = cpcm->hw_buf.area;
1023                 runtime->dma_addr = cpcm->hw_buf.addr;
1024                 runtime->dma_bytes = cpcm->hw_buf.bytes;
1025
1026
1027 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1028                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1029                         substream->ops = &snd_cs46xx_playback_ops;
1030                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1031                         substream->ops = &snd_cs46xx_playback_rear_ops;
1032                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1033                         substream->ops = &snd_cs46xx_playback_clfe_ops;
1034                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1035                         substream->ops = &snd_cs46xx_playback_iec958_ops;
1036                 } else {
1037                         snd_assert(0);
1038                 }
1039 #else
1040                 substream->ops = &snd_cs46xx_playback_ops;
1041 #endif
1042
1043         } else {
1044                 if (runtime->dma_area == cpcm->hw_buf.area) {
1045                         runtime->dma_area = NULL;
1046                         runtime->dma_addr = 0;
1047                         runtime->dma_bytes = 0;
1048                 }
1049                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1050 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1051                         up (&chip->spos_mutex);
1052 #endif
1053                         return err;
1054                 }
1055
1056 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1057                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1058                         substream->ops = &snd_cs46xx_playback_indirect_ops;
1059                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1060                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1061                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1062                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1063                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1064                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1065                 } else {
1066                         snd_assert(0);
1067                 }
1068 #else
1069                 substream->ops = &snd_cs46xx_playback_indirect_ops;
1070 #endif
1071
1072         }
1073
1074 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1075         up (&chip->spos_mutex);
1076 #endif
1077
1078         return 0;
1079 }
1080
1081 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t * substream)
1082 {
1083         /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
1084         snd_pcm_runtime_t *runtime = substream->runtime;
1085         cs46xx_pcm_t *cpcm;
1086
1087         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
1088
1089         /* if play_back open fails, then this function
1090            is called and cpcm can actually be NULL here */
1091         if (!cpcm) return -ENXIO;
1092
1093         if (runtime->dma_area != cpcm->hw_buf.area)
1094                 snd_pcm_lib_free_pages(substream);
1095
1096         runtime->dma_area = NULL;
1097         runtime->dma_addr = 0;
1098         runtime->dma_bytes = 0;
1099
1100         return 0;
1101 }
1102
1103 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t * substream)
1104 {
1105         unsigned int tmp;
1106         unsigned int pfie;
1107         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1108         snd_pcm_runtime_t *runtime = substream->runtime;
1109         cs46xx_pcm_t *cpcm;
1110
1111         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
1112
1113 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1114     snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1115
1116         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1117         pfie &= ~0x0000f03f;
1118 #else
1119         /* old dsp */
1120         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1121         pfie &= ~0x0000f03f;
1122 #endif
1123
1124         cpcm->shift = 2;
1125         /* if to convert from stereo to mono */
1126         if (runtime->channels == 1) {
1127                 cpcm->shift--;
1128                 pfie |= 0x00002000;
1129         }
1130         /* if to convert from 8 bit to 16 bit */
1131         if (snd_pcm_format_width(runtime->format) == 8) {
1132                 cpcm->shift--;
1133                 pfie |= 0x00001000;
1134         }
1135         /* if to convert to unsigned */
1136         if (snd_pcm_format_unsigned(runtime->format))
1137                 pfie |= 0x00008000;
1138
1139         /* Never convert byte order when sample stream is 8 bit */
1140         if (snd_pcm_format_width(runtime->format) != 8) {
1141                 /* convert from big endian to little endian */
1142                 if (snd_pcm_format_big_endian(runtime->format))
1143                         pfie |= 0x00004000;
1144         }
1145
1146         cpcm->sw_bufsize = snd_pcm_lib_buffer_bytes(substream);
1147         cpcm->sw_data = cpcm->sw_io = cpcm->sw_ready = 0;
1148         cpcm->hw_data = cpcm->hw_io = cpcm->hw_ready = 0;
1149         cpcm->appl_ptr = 0;
1150
1151 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1152
1153         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1154         tmp &= ~0x000003ff;
1155         tmp |= (4 << cpcm->shift) - 1;
1156         /* playback transaction count register */
1157         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1158
1159         /* playback format && interrupt enable */
1160         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1161 #else
1162         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1163         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1164         tmp &= ~0x000003ff;
1165         tmp |= (4 << cpcm->shift) - 1;
1166         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1167         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1168         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1169 #endif
1170
1171         return 0;
1172 }
1173
1174 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t * substream,
1175                                         snd_pcm_hw_params_t * hw_params)
1176 {
1177         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1178         snd_pcm_runtime_t *runtime = substream->runtime;
1179         int err;
1180
1181 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1182         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1183 #endif
1184         if (runtime->periods == CS46XX_FRAGS) {
1185                 if (runtime->dma_area != chip->capt.hw_buf.area)
1186                         snd_pcm_lib_free_pages(substream);
1187                 runtime->dma_area = chip->capt.hw_buf.area;
1188                 runtime->dma_addr = chip->capt.hw_buf.addr;
1189                 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1190                 substream->ops = &snd_cs46xx_capture_ops;
1191         } else {
1192                 if (runtime->dma_area == chip->capt.hw_buf.area) {
1193                         runtime->dma_area = NULL;
1194                         runtime->dma_addr = 0;
1195                         runtime->dma_bytes = 0;
1196                 }
1197                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1198                         return err;
1199                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t * substream)
1206 {
1207         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1208         snd_pcm_runtime_t *runtime = substream->runtime;
1209
1210         if (runtime->dma_area != chip->capt.hw_buf.area)
1211                 snd_pcm_lib_free_pages(substream);
1212         runtime->dma_area = NULL;
1213         runtime->dma_addr = 0;
1214         runtime->dma_bytes = 0;
1215
1216         return 0;
1217 }
1218
1219 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t * substream)
1220 {
1221         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1222         snd_pcm_runtime_t *runtime = substream->runtime;
1223
1224         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1225         chip->capt.shift = 2;
1226         chip->capt.sw_bufsize = snd_pcm_lib_buffer_bytes(substream);
1227         chip->capt.sw_data = chip->capt.sw_io = chip->capt.sw_ready = 0;
1228         chip->capt.hw_data = chip->capt.hw_io = chip->capt.hw_ready = 0;
1229         chip->capt.appl_ptr = 0;
1230         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1231
1232         return 0;
1233 }
1234
1235 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1236 {
1237         cs46xx_t *chip = snd_magic_cast(cs46xx_t, dev_id, return IRQ_NONE);
1238         u32 status1;
1239 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1240         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1241         u32 status2;
1242         int i;
1243         cs46xx_pcm_t *cpcm = NULL;
1244 #endif
1245
1246         /*
1247          *  Read the Interrupt Status Register to clear the interrupt
1248          */
1249         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1250         if ((status1 & 0x7fffffff) == 0) {
1251                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1252                 return IRQ_NONE;
1253         }
1254
1255 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1256         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1257
1258         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1259                 if (i <= 15) {
1260                         if ( status1 & (1 << i) ) {
1261                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1262                                         if (chip->capt.substream)
1263                                                 snd_pcm_period_elapsed(chip->capt.substream);
1264                                 } else {
1265                                         if (ins->pcm_channels[i].active &&
1266                                             ins->pcm_channels[i].private_data &&
1267                                             !ins->pcm_channels[i].unlinked) {
1268                                                 cpcm = snd_magic_cast(cs46xx_pcm_t, ins->pcm_channels[i].private_data, continue);
1269                                                 snd_pcm_period_elapsed(cpcm->substream);
1270                                         }
1271                                 }
1272                         }
1273                 } else {
1274                         if ( status2 & (1 << (i - 16))) {
1275                                 if (ins->pcm_channels[i].active &&
1276                                     ins->pcm_channels[i].private_data &&
1277                                     !ins->pcm_channels[i].unlinked) {
1278                                         cpcm = snd_magic_cast(cs46xx_pcm_t, ins->pcm_channels[i].private_data, continue);
1279                                         snd_pcm_period_elapsed(cpcm->substream);
1280                                 }
1281                         }
1282                 }
1283         }
1284
1285 #else
1286         /* old dsp */
1287         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1288                 if (chip->playback_pcm->substream)
1289                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1290         }
1291         if ((status1 & HISR_VC1) && chip->pcm) {
1292                 if (chip->capt.substream)
1293                         snd_pcm_period_elapsed(chip->capt.substream);
1294         }
1295 #endif
1296
1297         if ((status1 & HISR_MIDI) && chip->rmidi) {
1298                 unsigned char c;
1299
1300                 spin_lock(&chip->reg_lock);
1301                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1302                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1303                         if ((chip->midcr & MIDCR_RIE) == 0)
1304                                 continue;
1305                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1306                 }
1307                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1308                         if ((chip->midcr & MIDCR_TIE) == 0)
1309                                 break;
1310                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1311                                 chip->midcr &= ~MIDCR_TIE;
1312                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1313                                 break;
1314                         }
1315                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1316                 }
1317                 spin_unlock(&chip->reg_lock);
1318         }
1319         /*
1320          *  EOI to the PCI part....reenables interrupts
1321          */
1322         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1323
1324         return IRQ_HANDLED;
1325 }
1326
1327 static snd_pcm_hardware_t snd_cs46xx_playback =
1328 {
1329         .info =                 (SNDRV_PCM_INFO_MMAP |
1330                                  SNDRV_PCM_INFO_INTERLEAVED |
1331                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1332                                  SNDRV_PCM_INFO_RESUME),
1333         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1334                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1335                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1336         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1337         .rate_min =             5500,
1338         .rate_max =             48000,
1339         .channels_min =         1,
1340         .channels_max =         2,
1341         .buffer_bytes_max =     (256 * 1024),
1342         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1343         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1344         .periods_min =          CS46XX_FRAGS,
1345         .periods_max =          1024,
1346         .fifo_size =            0,
1347 };
1348
1349 static snd_pcm_hardware_t snd_cs46xx_capture =
1350 {
1351         .info =                 (SNDRV_PCM_INFO_MMAP |
1352                                  SNDRV_PCM_INFO_INTERLEAVED |
1353                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1354                                  SNDRV_PCM_INFO_RESUME),
1355         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1356         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1357         .rate_min =             5500,
1358         .rate_max =             48000,
1359         .channels_min =         2,
1360         .channels_max =         2,
1361         .buffer_bytes_max =     (256 * 1024),
1362         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1363         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1364         .periods_min =          CS46XX_FRAGS,
1365         .periods_max =          1024,
1366         .fifo_size =            0,
1367 };
1368
1369 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1370
1371 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1372
1373 #define PERIOD_SIZES sizeof(period_sizes) / sizeof(period_sizes[0])
1374
1375 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
1376         .count = PERIOD_SIZES,
1377         .list = period_sizes,
1378         .mask = 0
1379 };
1380
1381 #endif
1382
1383 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t *runtime)
1384 {
1385         cs46xx_pcm_t * cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return);
1386
1387         if (cpcm)
1388                 snd_magic_kfree(cpcm);
1389 }
1390
1391 static int _cs46xx_playback_open_channel (snd_pcm_substream_t * substream,int pcm_channel_id)
1392 {
1393         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1394         cs46xx_pcm_t * cpcm;
1395         snd_pcm_runtime_t *runtime = substream->runtime;
1396
1397         cpcm = snd_magic_kcalloc(cs46xx_pcm_t, 0, GFP_KERNEL);
1398         if (cpcm == NULL)
1399                 return -ENOMEM;
1400         if (snd_dma_alloc_pages(&chip->dma_dev, PAGE_SIZE, &cpcm->hw_buf) < 0) {
1401                 snd_magic_kfree(cpcm);
1402                 return -ENOMEM;
1403         }
1404
1405         runtime->hw = snd_cs46xx_playback;
1406         runtime->private_data = cpcm;
1407         runtime->private_free = snd_cs46xx_pcm_free_substream;
1408
1409         cpcm->substream = substream;
1410 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1411         down (&chip->spos_mutex);
1412         cpcm->pcm_channel = NULL;
1413         cpcm->pcm_channel_id = pcm_channel_id;
1414
1415
1416         snd_pcm_hw_constraint_list(runtime, 0,
1417                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1418                                    &hw_constraints_period_sizes);
1419
1420         up (&chip->spos_mutex);
1421 #else
1422         chip->playback_pcm = cpcm; /* HACK */
1423 #endif
1424
1425         if (chip->accept_valid)
1426                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1427         chip->active_ctrl(chip, 1);
1428
1429         return 0;
1430 }
1431
1432 static int snd_cs46xx_playback_open(snd_pcm_substream_t * substream)
1433 {
1434         snd_printdd("open front channel\n");
1435         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1436 }
1437
1438 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1439 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t * substream)
1440 {
1441         snd_printdd("open rear channel\n");
1442
1443         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1444 }
1445
1446 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t * substream)
1447 {
1448         snd_printdd("open center - LFE channel\n");
1449
1450         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1451 }
1452
1453 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t * substream)
1454 {
1455         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1456
1457         snd_printdd("open raw iec958 channel\n");
1458
1459         down (&chip->spos_mutex);
1460         cs46xx_iec958_pre_open (chip);
1461         up (&chip->spos_mutex);
1462
1463         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1464 }
1465
1466 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream);
1467
1468 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t * substream)
1469 {
1470         int err;
1471         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1472
1473         snd_printdd("close raw iec958 channel\n");
1474
1475         err = snd_cs46xx_playback_close(substream);
1476
1477         down (&chip->spos_mutex);
1478         cs46xx_iec958_post_close (chip);
1479         up (&chip->spos_mutex);
1480
1481         return err;
1482 }
1483 #endif
1484
1485 static int snd_cs46xx_capture_open(snd_pcm_substream_t * substream)
1486 {
1487         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1488
1489         if (snd_dma_alloc_pages(&chip->dma_dev, PAGE_SIZE, &chip->capt.hw_buf) < 0)
1490                 return -ENOMEM;
1491         chip->capt.substream = substream;
1492         substream->runtime->hw = snd_cs46xx_capture;
1493
1494         if (chip->accept_valid)
1495                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1496
1497         chip->active_ctrl(chip, 1);
1498
1499 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1500         snd_pcm_hw_constraint_list(substream->runtime, 0,
1501                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1502                                    &hw_constraints_period_sizes);
1503 #endif
1504         return 0;
1505 }
1506
1507 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream)
1508 {
1509         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1510         snd_pcm_runtime_t *runtime = substream->runtime;
1511         cs46xx_pcm_t * cpcm;
1512
1513         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
1514
1515         /* when playback_open fails, then cpcm can be NULL */
1516         if (!cpcm) return -ENXIO;
1517
1518 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1519         down (&chip->spos_mutex);
1520         if (cpcm->pcm_channel) {
1521                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1522                 cpcm->pcm_channel = NULL;
1523         }
1524         up (&chip->spos_mutex);
1525 #else
1526         chip->playback_pcm = NULL;
1527 #endif
1528
1529         cpcm->substream = NULL;
1530         snd_dma_free_pages(&chip->dma_dev, &cpcm->hw_buf);
1531         chip->active_ctrl(chip, -1);
1532
1533         return 0;
1534 }
1535
1536 static int snd_cs46xx_capture_close(snd_pcm_substream_t * substream)
1537 {
1538         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1539
1540         chip->capt.substream = NULL;
1541         snd_dma_free_pages(&chip->dma_dev, &chip->capt.hw_buf);
1542         chip->active_ctrl(chip, -1);
1543
1544         return 0;
1545 }
1546
1547 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1548 snd_pcm_ops_t snd_cs46xx_playback_rear_ops = {
1549         .open =                 snd_cs46xx_playback_open_rear,
1550         .close =                snd_cs46xx_playback_close,
1551         .ioctl =                snd_pcm_lib_ioctl,
1552         .hw_params =            snd_cs46xx_playback_hw_params,
1553         .hw_free =              snd_cs46xx_playback_hw_free,
1554         .prepare =              snd_cs46xx_playback_prepare,
1555         .trigger =              snd_cs46xx_playback_trigger,
1556         .pointer =              snd_cs46xx_playback_direct_pointer,
1557 };
1558
1559 snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops = {
1560         .open =                 snd_cs46xx_playback_open_rear,
1561         .close =                snd_cs46xx_playback_close,
1562         .ioctl =                snd_pcm_lib_ioctl,
1563         .hw_params =            snd_cs46xx_playback_hw_params,
1564         .hw_free =              snd_cs46xx_playback_hw_free,
1565         .prepare =              snd_cs46xx_playback_prepare,
1566         .trigger =              snd_cs46xx_playback_trigger,
1567         .pointer =              snd_cs46xx_playback_indirect_pointer,
1568         .ack =                  snd_cs46xx_playback_transfer,
1569 };
1570
1571 snd_pcm_ops_t snd_cs46xx_playback_clfe_ops = {
1572         .open =                 snd_cs46xx_playback_open_clfe,
1573         .close =                snd_cs46xx_playback_close,
1574         .ioctl =                snd_pcm_lib_ioctl,
1575         .hw_params =            snd_cs46xx_playback_hw_params,
1576         .hw_free =              snd_cs46xx_playback_hw_free,
1577         .prepare =              snd_cs46xx_playback_prepare,
1578         .trigger =              snd_cs46xx_playback_trigger,
1579         .pointer =              snd_cs46xx_playback_direct_pointer,
1580 };
1581
1582 snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops = {
1583         .open =                 snd_cs46xx_playback_open_clfe,
1584         .close =                snd_cs46xx_playback_close,
1585         .ioctl =                snd_pcm_lib_ioctl,
1586         .hw_params =            snd_cs46xx_playback_hw_params,
1587         .hw_free =              snd_cs46xx_playback_hw_free,
1588         .prepare =              snd_cs46xx_playback_prepare,
1589         .trigger =              snd_cs46xx_playback_trigger,
1590         .pointer =              snd_cs46xx_playback_indirect_pointer,
1591         .ack =                  snd_cs46xx_playback_transfer,
1592 };
1593
1594 snd_pcm_ops_t snd_cs46xx_playback_iec958_ops = {
1595         .open =                 snd_cs46xx_playback_open_iec958,
1596         .close =                snd_cs46xx_playback_close_iec958,
1597         .ioctl =                snd_pcm_lib_ioctl,
1598         .hw_params =            snd_cs46xx_playback_hw_params,
1599         .hw_free =              snd_cs46xx_playback_hw_free,
1600         .prepare =              snd_cs46xx_playback_prepare,
1601         .trigger =              snd_cs46xx_playback_trigger,
1602         .pointer =              snd_cs46xx_playback_direct_pointer,
1603 };
1604
1605 snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops = {
1606         .open =                 snd_cs46xx_playback_open_iec958,
1607         .close =                snd_cs46xx_playback_close_iec958,
1608         .ioctl =                snd_pcm_lib_ioctl,
1609         .hw_params =            snd_cs46xx_playback_hw_params,
1610         .hw_free =              snd_cs46xx_playback_hw_free,
1611         .prepare =              snd_cs46xx_playback_prepare,
1612         .trigger =              snd_cs46xx_playback_trigger,
1613         .pointer =              snd_cs46xx_playback_indirect_pointer,
1614         .ack =                  snd_cs46xx_playback_transfer,
1615 };
1616
1617 #endif
1618
1619 snd_pcm_ops_t snd_cs46xx_playback_ops = {
1620         .open =                 snd_cs46xx_playback_open,
1621         .close =                snd_cs46xx_playback_close,
1622         .ioctl =                snd_pcm_lib_ioctl,
1623         .hw_params =            snd_cs46xx_playback_hw_params,
1624         .hw_free =              snd_cs46xx_playback_hw_free,
1625         .prepare =              snd_cs46xx_playback_prepare,
1626         .trigger =              snd_cs46xx_playback_trigger,
1627         .pointer =              snd_cs46xx_playback_direct_pointer,
1628 };
1629
1630 snd_pcm_ops_t snd_cs46xx_playback_indirect_ops = {
1631         .open =                 snd_cs46xx_playback_open,
1632         .close =                snd_cs46xx_playback_close,
1633         .ioctl =                snd_pcm_lib_ioctl,
1634         .hw_params =            snd_cs46xx_playback_hw_params,
1635         .hw_free =              snd_cs46xx_playback_hw_free,
1636         .prepare =              snd_cs46xx_playback_prepare,
1637         .trigger =              snd_cs46xx_playback_trigger,
1638         .pointer =              snd_cs46xx_playback_indirect_pointer,
1639         .ack =                  snd_cs46xx_playback_transfer,
1640 };
1641
1642 snd_pcm_ops_t snd_cs46xx_capture_ops = {
1643         .open =                 snd_cs46xx_capture_open,
1644         .close =                snd_cs46xx_capture_close,
1645         .ioctl =                snd_pcm_lib_ioctl,
1646         .hw_params =            snd_cs46xx_capture_hw_params,
1647         .hw_free =              snd_cs46xx_capture_hw_free,
1648         .prepare =              snd_cs46xx_capture_prepare,
1649         .trigger =              snd_cs46xx_capture_trigger,
1650         .pointer =              snd_cs46xx_capture_direct_pointer,
1651 };
1652
1653 snd_pcm_ops_t snd_cs46xx_capture_indirect_ops = {
1654         .open =                 snd_cs46xx_capture_open,
1655         .close =                snd_cs46xx_capture_close,
1656         .ioctl =                snd_pcm_lib_ioctl,
1657         .hw_params =            snd_cs46xx_capture_hw_params,
1658         .hw_free =              snd_cs46xx_capture_hw_free,
1659         .prepare =              snd_cs46xx_capture_prepare,
1660         .trigger =              snd_cs46xx_capture_trigger,
1661         .pointer =              snd_cs46xx_capture_indirect_pointer,
1662         .ack =                  snd_cs46xx_capture_transfer,
1663 };
1664
1665 static void snd_cs46xx_pcm_free(snd_pcm_t *pcm)
1666 {
1667         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1668         chip->pcm = NULL;
1669         snd_pcm_lib_preallocate_free_for_all(pcm);
1670 }
1671
1672 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1673 static void snd_cs46xx_pcm_rear_free(snd_pcm_t *pcm)
1674 {
1675         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1676         chip->pcm_rear = NULL;
1677         snd_pcm_lib_preallocate_free_for_all(pcm);
1678 }
1679
1680 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t *pcm)
1681 {
1682         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1683         chip->pcm_center_lfe = NULL;
1684         snd_pcm_lib_preallocate_free_for_all(pcm);
1685 }
1686
1687 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t *pcm)
1688 {
1689         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1690         chip->pcm_iec958 = NULL;
1691         snd_pcm_lib_preallocate_free_for_all(pcm);
1692 }
1693
1694 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1695 #else
1696 #define MAX_PLAYBACK_CHANNELS   1
1697 #endif
1698
1699 int __devinit snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1700 {
1701         snd_pcm_t *pcm;
1702         int err;
1703
1704         if (rpcm)
1705                 *rpcm = NULL;
1706         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1707                 return err;
1708
1709         pcm->private_data = chip;
1710         pcm->private_free = snd_cs46xx_pcm_free;
1711
1712         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1713         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1714
1715         /* global setup */
1716         pcm->info_flags = 0;
1717         strcpy(pcm->name, "CS46xx");
1718         chip->pcm = pcm;
1719
1720         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1721                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1722
1723         if (rpcm)
1724                 *rpcm = pcm;
1725
1726         return 0;
1727 }
1728
1729
1730 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1731 int __devinit snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1732 {
1733         snd_pcm_t *pcm;
1734         int err;
1735
1736         if (rpcm)
1737                 *rpcm = NULL;
1738
1739         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1740                 return err;
1741
1742         pcm->private_data = chip;
1743         pcm->private_free = snd_cs46xx_pcm_rear_free;
1744
1745         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1746
1747         /* global setup */
1748         pcm->info_flags = 0;
1749         strcpy(pcm->name, "CS46xx - Rear");
1750         chip->pcm_rear = pcm;
1751
1752         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1753                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1754
1755         if (rpcm)
1756                 *rpcm = pcm;
1757
1758         return 0;
1759 }
1760
1761 int __devinit snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1762 {
1763         snd_pcm_t *pcm;
1764         int err;
1765
1766         if (rpcm)
1767                 *rpcm = NULL;
1768
1769         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1770                 return err;
1771
1772         pcm->private_data = chip;
1773         pcm->private_free = snd_cs46xx_pcm_center_lfe_free;
1774
1775         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1776
1777         /* global setup */
1778         pcm->info_flags = 0;
1779         strcpy(pcm->name, "CS46xx - Center LFE");
1780         chip->pcm_center_lfe = pcm;
1781
1782         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1783                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1784
1785         if (rpcm)
1786                 *rpcm = pcm;
1787
1788         return 0;
1789 }
1790
1791 int __devinit snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1792 {
1793         snd_pcm_t *pcm;
1794         int err;
1795
1796         if (rpcm)
1797                 *rpcm = NULL;
1798
1799         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1800                 return err;
1801
1802         pcm->private_data = chip;
1803         pcm->private_free = snd_cs46xx_pcm_iec958_free;
1804
1805         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1806
1807         /* global setup */
1808         pcm->info_flags = 0;
1809         strcpy(pcm->name, "CS46xx - IEC958");
1810         chip->pcm_rear = pcm;
1811
1812         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1813                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1814
1815         if (rpcm)
1816                 *rpcm = pcm;
1817
1818         return 0;
1819 }
1820 #endif
1821
1822 /*
1823  *  Mixer routines
1824  */
1825 static void snd_cs46xx_mixer_free_ac97_bus(ac97_bus_t *bus)
1826 {
1827         cs46xx_t *chip = snd_magic_cast(cs46xx_t, bus->private_data, return);
1828
1829         chip->ac97_bus = NULL;
1830 }
1831
1832 static void snd_cs46xx_mixer_free_ac97(ac97_t *ac97)
1833 {
1834         cs46xx_t *chip = snd_magic_cast(cs46xx_t, ac97->private_data, return);
1835
1836         snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1837                     (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1838                     return);
1839
1840         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1841                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1842                 chip->eapd_switch = NULL;
1843         }
1844         else
1845                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1846 }
1847
1848 static int snd_cs46xx_vol_info(snd_kcontrol_t *kcontrol,
1849                                snd_ctl_elem_info_t *uinfo)
1850 {
1851         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1852         uinfo->count = 2;
1853         uinfo->value.integer.min = 0;
1854         uinfo->value.integer.max = 0x7fff;
1855         return 0;
1856 }
1857
1858 static int snd_cs46xx_vol_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1859 {
1860         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1861         int reg = kcontrol->private_value;
1862         unsigned int val = snd_cs46xx_peek(chip, reg);
1863         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1864         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1865         return 0;
1866 }
1867
1868 static int snd_cs46xx_vol_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1869 {
1870         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1871         int reg = kcontrol->private_value;
1872         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1873                             (0xffff - ucontrol->value.integer.value[1]));
1874         unsigned int old = snd_cs46xx_peek(chip, reg);
1875         int change = (old != val);
1876
1877         if (change) {
1878                 snd_cs46xx_poke(chip, reg, val);
1879         }
1880
1881         return change;
1882 }
1883
1884 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1885
1886 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1887 {
1888         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1889
1890         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1891         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1892
1893         return 0;
1894 }
1895
1896 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1897 {
1898         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1899         int change = 0;
1900
1901         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1902             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1903                 cs46xx_dsp_set_dac_volume(chip,
1904                                           ucontrol->value.integer.value[0],
1905                                           ucontrol->value.integer.value[1]);
1906                 change = 1;
1907         }
1908
1909         return change;
1910 }
1911
1912 #if 0
1913 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1914 {
1915         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1916
1917         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1918         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1919         return 0;
1920 }
1921
1922 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1923 {
1924         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1925         int change = 0;
1926
1927         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1928             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1929                 cs46xx_dsp_set_iec958_volume (chip,
1930                                               ucontrol->value.integer.value[0],
1931                                               ucontrol->value.integer.value[1]);
1932                 change = 1;
1933         }
1934
1935         return change;
1936 }
1937 #endif
1938
1939 static int snd_mixer_boolean_info(snd_kcontrol_t *kcontrol,
1940                                   snd_ctl_elem_info_t *uinfo)
1941 {
1942         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1943         uinfo->count = 1;
1944         uinfo->value.integer.min = 0;
1945         uinfo->value.integer.max = 1;
1946         return 0;
1947 }
1948
1949 static int snd_cs46xx_iec958_get(snd_kcontrol_t *kcontrol,
1950                                  snd_ctl_elem_value_t *ucontrol)
1951 {
1952         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1953         int reg = kcontrol->private_value;
1954
1955         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1956                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1957         else
1958                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1959
1960         return 0;
1961 }
1962
1963 static int snd_cs46xx_iec958_put(snd_kcontrol_t *kcontrol,
1964                                   snd_ctl_elem_value_t *ucontrol)
1965 {
1966         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1967         int change, res;
1968
1969         switch (kcontrol->private_value) {
1970         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1971                 down (&chip->spos_mutex);
1972                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1973                 if (ucontrol->value.integer.value[0] && !change)
1974                         cs46xx_dsp_enable_spdif_out(chip);
1975                 else if (change && !ucontrol->value.integer.value[0])
1976                         cs46xx_dsp_disable_spdif_out(chip);
1977
1978                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1979                 up (&chip->spos_mutex);
1980                 break;
1981         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1982                 change = chip->dsp_spos_instance->spdif_status_in;
1983                 if (ucontrol->value.integer.value[0] && !change) {
1984                         cs46xx_dsp_enable_spdif_in(chip);
1985                         /* restore volume */
1986                 }
1987                 else if (change && !ucontrol->value.integer.value[0])
1988                         cs46xx_dsp_disable_spdif_in(chip);
1989
1990                 res = (change != chip->dsp_spos_instance->spdif_status_in);
1991                 break;
1992         default:
1993                 res = -EINVAL;
1994                 snd_assert(0, (void)0);
1995         }
1996
1997         return res;
1998 }
1999
2000 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t *kcontrol,
2001                                       snd_ctl_elem_value_t *ucontrol)
2002 {
2003         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2004         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2005
2006         if (ins->adc_input != NULL)
2007                 ucontrol->value.integer.value[0] = 1;
2008         else
2009                 ucontrol->value.integer.value[0] = 0;
2010
2011         return 0;
2012 }
2013
2014 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t *kcontrol,
2015                                       snd_ctl_elem_value_t *ucontrol)
2016 {
2017         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2018         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2019         int change = 0;
2020
2021         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2022                 cs46xx_dsp_enable_adc_capture(chip);
2023                 change = 1;
2024         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2025                 cs46xx_dsp_disable_adc_capture(chip);
2026                 change = 1;
2027         }
2028         return change;
2029 }
2030
2031 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t *kcontrol,
2032                                       snd_ctl_elem_value_t *ucontrol)
2033 {
2034         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2035         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2036
2037         if (ins->pcm_input != NULL)
2038                 ucontrol->value.integer.value[0] = 1;
2039         else
2040                 ucontrol->value.integer.value[0] = 0;
2041
2042         return 0;
2043 }
2044
2045
2046 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t *kcontrol,
2047                                       snd_ctl_elem_value_t *ucontrol)
2048 {
2049         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2050         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2051         int change = 0;
2052
2053         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2054                 cs46xx_dsp_enable_pcm_capture(chip);
2055                 change = 1;
2056         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2057                 cs46xx_dsp_disable_pcm_capture(chip);
2058                 change = 1;
2059         }
2060
2061         return change;
2062 }
2063
2064 static int snd_herc_spdif_select_get(snd_kcontrol_t *kcontrol,
2065                                      snd_ctl_elem_value_t *ucontrol)
2066 {
2067         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2068
2069         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2070
2071         if (val1 & EGPIODR_GPOE0)
2072                 ucontrol->value.integer.value[0] = 1;
2073         else
2074                 ucontrol->value.integer.value[0] = 0;
2075
2076         return 0;
2077 }
2078
2079 /*
2080  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2081  */
2082 static int snd_herc_spdif_select_put(snd_kcontrol_t *kcontrol,
2083                                        snd_ctl_elem_value_t *ucontrol)
2084 {
2085         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2086         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2087         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2088
2089         if (ucontrol->value.integer.value[0]) {
2090                 /* optical is default */
2091                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2092                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
2093                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2094                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2095         } else {
2096                 /* coaxial */
2097                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
2098                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2099         }
2100
2101         /* checking diff from the EGPIO direction register
2102            should be enough */
2103         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2104 }
2105
2106
2107 static int snd_cs46xx_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2108 {
2109         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2110         uinfo->count = 1;
2111         return 0;
2112 }
2113
2114 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t * kcontrol,
2115                                         snd_ctl_elem_value_t * ucontrol)
2116 {
2117         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2118         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2119
2120         down (&chip->spos_mutex);
2121         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2122         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2123         ucontrol->value.iec958.status[2] = 0;
2124         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2125         up (&chip->spos_mutex);
2126
2127         return 0;
2128 }
2129
2130 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t * kcontrol,
2131                                         snd_ctl_elem_value_t * ucontrol)
2132 {
2133         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2134         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2135         unsigned int val;
2136         int change;
2137
2138         down (&chip->spos_mutex);
2139         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2140                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2141                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2142                 /* left and right validity bit */
2143                 (1 << 13) | (1 << 12);
2144
2145
2146         change = (unsigned int)ins->spdif_csuv_default != val;
2147         ins->spdif_csuv_default = val;
2148
2149         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2150                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2151
2152         up (&chip->spos_mutex);
2153
2154         return change;
2155 }
2156
2157 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t * kcontrol,
2158                                      snd_ctl_elem_value_t * ucontrol)
2159 {
2160         ucontrol->value.iec958.status[0] = 0xff;
2161         ucontrol->value.iec958.status[1] = 0xff;
2162         ucontrol->value.iec958.status[2] = 0x00;
2163         ucontrol->value.iec958.status[3] = 0xff;
2164         return 0;
2165 }
2166
2167 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t * kcontrol,
2168                                          snd_ctl_elem_value_t * ucontrol)
2169 {
2170         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2171         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2172
2173         down (&chip->spos_mutex);
2174         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2175         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2176         ucontrol->value.iec958.status[2] = 0;
2177         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2178         up (&chip->spos_mutex);
2179
2180         return 0;
2181 }
2182
2183 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t * kcontrol,
2184                                         snd_ctl_elem_value_t * ucontrol)
2185 {
2186         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2187         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2188         unsigned int val;
2189         int change;
2190
2191         down (&chip->spos_mutex);
2192         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2193                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2194                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2195                 /* left and right validity bit */
2196                 (1 << 13) | (1 << 12);
2197
2198
2199         change = ins->spdif_csuv_stream != val;
2200         ins->spdif_csuv_stream = val;
2201
2202         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2203                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2204
2205         up (&chip->spos_mutex);
2206
2207         return change;
2208 }
2209
2210 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2211
2212
2213 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2214 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t *kcontrol,
2215                                         snd_ctl_elem_info_t *uinfo)
2216 {
2217         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2218         uinfo->count = 1;
2219         uinfo->value.integer.min = 0;
2220         uinfo->value.integer.max = 8;
2221         return 0;
2222 }
2223
2224 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t *kcontrol,
2225                                        snd_ctl_elem_value_t *ucontrol)
2226 {
2227         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2228         ucontrol->value.integer.value[0] = chip->current_gpio;
2229
2230         return 0;
2231 }
2232
2233 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t *kcontrol,
2234                                        snd_ctl_elem_value_t *ucontrol)
2235 {
2236         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2237         int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2238         chip->current_gpio = ucontrol->value.integer.value[0];
2239
2240         return change;
2241 }
2242
2243
2244 static int snd_cs46xx_egpio_get(snd_kcontrol_t *kcontrol,
2245                                        snd_ctl_elem_value_t *ucontrol)
2246 {
2247         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2248         int reg = kcontrol->private_value;
2249
2250         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2251         ucontrol->value.integer.value[0] =
2252                 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2253
2254         return 0;
2255 }
2256
2257 static int snd_cs46xx_egpio_put(snd_kcontrol_t *kcontrol,
2258                                        snd_ctl_elem_value_t *ucontrol)
2259 {
2260         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2261         int reg = kcontrol->private_value;
2262         int val = snd_cs46xx_peekBA0(chip, reg);
2263         int oldval = val;
2264         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2265
2266         if (ucontrol->value.integer.value[0])
2267                 val |= (1 << chip->current_gpio);
2268         else
2269                 val &= ~(1 << chip->current_gpio);
2270
2271         snd_cs46xx_pokeBA0(chip, reg,val);
2272         snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2273
2274         return (oldval != val);
2275 }
2276 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2277
2278 static snd_kcontrol_new_t snd_cs46xx_controls[] __devinitdata = {
2279 {
2280         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2281         .name = "DAC Volume",
2282         .info = snd_cs46xx_vol_info,
2283 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2284         .get = snd_cs46xx_vol_get,
2285         .put = snd_cs46xx_vol_put,
2286         .private_value = BA1_PVOL,
2287 #else
2288         .get = snd_cs46xx_vol_dac_get,
2289         .put = snd_cs46xx_vol_dac_put,
2290 #endif
2291 },
2292
2293 {
2294         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2295         .name = "ADC Volume",
2296         .info = snd_cs46xx_vol_info,
2297         .get = snd_cs46xx_vol_get,
2298         .put = snd_cs46xx_vol_put,
2299 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2300         .private_value = BA1_CVOL,
2301 #else
2302         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2303 #endif
2304 },
2305 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2306 {
2307         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2308         .name = "ADC Capture Switch",
2309         .info = snd_mixer_boolean_info,
2310         .get = snd_cs46xx_adc_capture_get,
2311         .put = snd_cs46xx_adc_capture_put
2312 },
2313 {
2314         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2315         .name = "DAC Capture Switch",
2316         .info = snd_mixer_boolean_info,
2317         .get = snd_cs46xx_pcm_capture_get,
2318         .put = snd_cs46xx_pcm_capture_put
2319 },
2320 {
2321         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2322         .name = "IEC958 Output Switch",
2323         .info = snd_mixer_boolean_info,
2324         .get = snd_cs46xx_iec958_get,
2325         .put = snd_cs46xx_iec958_put,
2326         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2327 },
2328 {
2329         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2330         .name = "IEC958 Input Switch",
2331         .info = snd_mixer_boolean_info,
2332         .get = snd_cs46xx_iec958_get,
2333         .put = snd_cs46xx_iec958_put,
2334         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2335 },
2336 #if 0
2337 /* Input IEC958 volume does not work for the moment. (Benny) */
2338 {
2339         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2340         .name = "IEC958 Input Volume",
2341         .info = snd_cs46xx_vol_info,
2342         .get = snd_cs46xx_vol_iec958_get,
2343         .put = snd_cs46xx_vol_iec958_put,
2344         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2345 },
2346 #endif
2347 {
2348         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2349         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2350         .info =  snd_cs46xx_spdif_info,
2351         .get =   snd_cs46xx_spdif_default_get,
2352         .put =   snd_cs46xx_spdif_default_put,
2353 },
2354 {
2355         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2356         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2357         .info =  snd_cs46xx_spdif_info,
2358         .get =   snd_cs46xx_spdif_mask_get,
2359         .access = SNDRV_CTL_ELEM_ACCESS_READ
2360 },
2361 {
2362         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2363         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2364         .info =  snd_cs46xx_spdif_info,
2365         .get =   snd_cs46xx_spdif_stream_get,
2366         .put =   snd_cs46xx_spdif_stream_put
2367 },
2368
2369 #endif
2370 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2371 {
2372         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2373         .name = "EGPIO select",
2374         .info = snd_cs46xx_egpio_select_info,
2375         .get = snd_cs46xx_egpio_select_get,
2376         .put = snd_cs46xx_egpio_select_put,
2377         .private_value = 0,
2378 },
2379 {
2380         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2381         .name = "EGPIO Input/Output",
2382         .info = snd_mixer_boolean_info,
2383         .get = snd_cs46xx_egpio_get,
2384         .put = snd_cs46xx_egpio_put,
2385         .private_value = BA0_EGPIODR,
2386 },
2387 {
2388         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2389         .name = "EGPIO CMOS/Open drain",
2390         .info = snd_mixer_boolean_info,
2391         .get = snd_cs46xx_egpio_get,
2392         .put = snd_cs46xx_egpio_put,
2393         .private_value = BA0_EGPIOPTR,
2394 },
2395 {
2396         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2397         .name = "EGPIO On/Off",
2398         .info = snd_mixer_boolean_info,
2399         .get = snd_cs46xx_egpio_get,
2400         .put = snd_cs46xx_egpio_put,
2401         .private_value = BA0_EGPIOSR,
2402 },
2403 #endif
2404 };
2405
2406 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2407 /* Only available on the Hercules Game Theater XP soundcard */
2408 static snd_kcontrol_new_t snd_hercules_controls[] __devinitdata = {
2409 {
2410         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2411         .name = "Optical/Coaxial SPDIF Input Switch",
2412         .info = snd_mixer_boolean_info,
2413         .get = snd_herc_spdif_select_get,
2414         .put = snd_herc_spdif_select_put,
2415 },
2416 };
2417
2418
2419 static void snd_cs46xx_codec_reset (ac97_t * ac97)
2420 {
2421         unsigned long end_time;
2422         int err;
2423         cs46xx_t * chip = snd_magic_cast(cs46xx_t,ac97->private_data,return /* -ENXIO */);
2424
2425         /* reset to defaults */
2426         snd_ac97_write(ac97, AC97_RESET, 0);
2427
2428         /* set the desired CODEC mode */
2429         if (chip->nr_ac97_codecs == 0) {
2430                 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2431                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2432         } else if (chip->nr_ac97_codecs == 1) {
2433                 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2434                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2435         } else {
2436                 snd_assert(0); /* should never happen ... */
2437         }
2438
2439         udelay(50);
2440
2441         /* it's necessary to wait awhile until registers are accessible after RESET */
2442         /* because the PCM or MASTER volume registers can be modified, */
2443         /* the REC_GAIN register is used for tests */
2444         end_time = jiffies + HZ;
2445         do {
2446                 unsigned short ext_mid;
2447
2448                 /* use preliminary reads to settle the communication */
2449                 snd_ac97_read(ac97, AC97_RESET);
2450                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2451                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2452                 /* modem? */
2453                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2454                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2455                         return;
2456
2457                 /* test if we can write to the record gain volume register */
2458                 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2459                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2460                         return;
2461
2462                 set_current_state(TASK_UNINTERRUPTIBLE);
2463                 schedule_timeout(HZ/100);
2464         } while (time_after_eq(end_time, jiffies));
2465
2466         snd_printk("CS46xx secondary codec dont respond!\n");
2467 }
2468 #endif
2469
2470 int __devinit snd_cs46xx_mixer(cs46xx_t *chip)
2471 {
2472         snd_card_t *card = chip->card;
2473         ac97_bus_t bus;
2474         ac97_t ac97;
2475         snd_ctl_elem_id_t id;
2476         int err;
2477         unsigned int idx;
2478
2479         /* detect primary codec */
2480         chip->nr_ac97_codecs = 0;
2481         snd_printdd("snd_cs46xx: detecting primary codec\n");
2482         memset(&bus, 0, sizeof(bus));
2483         bus.write = snd_cs46xx_ac97_write;
2484         bus.read = snd_cs46xx_ac97_read;
2485 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2486         bus.reset = snd_cs46xx_codec_reset;
2487 #endif
2488         bus.private_data = chip;
2489         bus.private_free = snd_cs46xx_mixer_free_ac97_bus;
2490         if ((err = snd_ac97_bus(card, &bus, &chip->ac97_bus)) < 0)
2491                 return err;
2492
2493         memset(&ac97, 0, sizeof(ac97));
2494         ac97.private_data = chip;
2495         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2496         chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = &ac97;
2497
2498         snd_cs46xx_ac97_write(&ac97, AC97_MASTER, 0x8000);
2499         for (idx = 0; idx < 100; ++idx) {
2500                 if (snd_cs46xx_ac97_read(&ac97, AC97_MASTER) == 0x8000)
2501                         goto _ok;
2502                 set_current_state(TASK_INTERRUPTIBLE);
2503                 schedule_timeout(HZ/100);
2504         }
2505         chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
2506         return -ENXIO;
2507
2508  _ok:
2509         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[CS46XX_PRIMARY_CODEC_INDEX])) < 0)
2510                 return err;
2511         snd_printdd("snd_cs46xx: primary codec phase one\n");
2512         chip->nr_ac97_codecs = 1;
2513
2514 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2515         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2516         /* try detect a secondary codec */
2517         memset(&ac97, 0, sizeof(ac97));
2518         ac97.private_data = chip;
2519         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2520         ac97.num = CS46XX_SECONDARY_CODEC_INDEX;
2521
2522         snd_cs46xx_ac97_write(&ac97, AC97_RESET, 0);
2523         udelay(10);
2524
2525         if (snd_cs46xx_ac97_read(&ac97, AC97_RESET) & 0x8000) {
2526                 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2527                 goto _no_sec_codec;
2528         }
2529
2530         chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = &ac97;
2531         snd_cs46xx_ac97_write(&ac97, AC97_MASTER, 0x8000);
2532         for (idx = 0; idx < 100; ++idx) {
2533                 if (snd_cs46xx_ac97_read(&ac97, AC97_MASTER) == 0x8000) {
2534                         goto _ok2;
2535                 }
2536                 set_current_state(TASK_INTERRUPTIBLE);
2537                 schedule_timeout(HZ/100);
2538         }
2539
2540  _no_sec_codec:
2541         snd_printdd("snd_cs46xx: secondary codec did not respond ...\n");
2542
2543         chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
2544         chip->nr_ac97_codecs = 1;
2545
2546         /* well, one codec only ... */
2547         goto _end;
2548  _ok2:
2549         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) < 0)
2550                 return err;
2551         chip->nr_ac97_codecs = 2;
2552
2553  _end:
2554
2555 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2556
2557         /* add cs4630 mixer controls */
2558         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2559                 snd_kcontrol_t *kctl;
2560                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2561                 if ((err = snd_ctl_add(card, kctl)) < 0)
2562                         return err;
2563         }
2564
2565         /* get EAPD mixer switch (for voyetra hack) */
2566         memset(&id, 0, sizeof(id));
2567         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2568         strcpy(id.name, "External Amplifier");
2569         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2570
2571 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2572         if (chip->nr_ac97_codecs == 1 &&
2573             (snd_cs46xx_codec_read(chip, AC97_VENDOR_ID2,
2574                                   CS46XX_PRIMARY_CODEC_INDEX) == 0x592b ||
2575              snd_cs46xx_codec_read(chip, AC97_VENDOR_ID2,
2576                                    CS46XX_PRIMARY_CODEC_INDEX) == 0x592d)) {
2577                 /* set primary cs4294 codec into Extended Audio Mode */
2578                 snd_printdd("setting EAM bit on cs4294 CODEC\n");
2579                 snd_cs46xx_codec_write(chip, AC97_CSR_ACMODE, 0x200,
2580                                        CS46XX_PRIMARY_CODEC_INDEX);
2581         }
2582         /* do soundcard specific mixer setup */
2583         if (chip->mixer_init) {
2584                 snd_printdd ("calling chip->mixer_init(chip);\n");
2585                 chip->mixer_init(chip);
2586         }
2587 #endif
2588
2589         /* turn on amplifier */
2590         chip->amplifier_ctrl(chip, 1);
2591
2592         return 0;
2593 }
2594
2595 /*
2596  *  RawMIDI interface
2597  */
2598
2599 static void snd_cs46xx_midi_reset(cs46xx_t *chip)
2600 {
2601         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2602         udelay(100);
2603         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2604 }
2605
2606 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t * substream)
2607 {
2608         unsigned long flags;
2609         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2610
2611         chip->active_ctrl(chip, 1);
2612         spin_lock_irqsave(&chip->reg_lock, flags);
2613         chip->uartm |= CS46XX_MODE_INPUT;
2614         chip->midcr |= MIDCR_RXE;
2615         chip->midi_input = substream;
2616         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2617                 snd_cs46xx_midi_reset(chip);
2618         } else {
2619                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2620         }
2621         spin_unlock_irqrestore(&chip->reg_lock, flags);
2622         return 0;
2623 }
2624
2625 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t * substream)
2626 {
2627         unsigned long flags;
2628         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2629
2630         spin_lock_irqsave(&chip->reg_lock, flags);
2631         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2632         chip->midi_input = NULL;
2633         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2634                 snd_cs46xx_midi_reset(chip);
2635         } else {
2636                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2637         }
2638         chip->uartm &= ~CS46XX_MODE_INPUT;
2639         spin_unlock_irqrestore(&chip->reg_lock, flags);
2640         chip->active_ctrl(chip, -1);
2641         return 0;
2642 }
2643
2644 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t * substream)
2645 {
2646         unsigned long flags;
2647         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2648
2649         chip->active_ctrl(chip, 1);
2650
2651         spin_lock_irqsave(&chip->reg_lock, flags);
2652         chip->uartm |= CS46XX_MODE_OUTPUT;
2653         chip->midcr |= MIDCR_TXE;
2654         chip->midi_output = substream;
2655         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2656                 snd_cs46xx_midi_reset(chip);
2657         } else {
2658                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2659         }
2660         spin_unlock_irqrestore(&chip->reg_lock, flags);
2661         return 0;
2662 }
2663
2664 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t * substream)
2665 {
2666         unsigned long flags;
2667         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2668
2669         spin_lock_irqsave(&chip->reg_lock, flags);
2670         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2671         chip->midi_output = NULL;
2672         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2673                 snd_cs46xx_midi_reset(chip);
2674         } else {
2675                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2676         }
2677         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2678         spin_unlock_irqrestore(&chip->reg_lock, flags);
2679         chip->active_ctrl(chip, -1);
2680         return 0;
2681 }
2682
2683 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2684 {
2685         unsigned long flags;
2686         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return);
2687
2688         spin_lock_irqsave(&chip->reg_lock, flags);
2689         if (up) {
2690                 if ((chip->midcr & MIDCR_RIE) == 0) {
2691                         chip->midcr |= MIDCR_RIE;
2692                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2693                 }
2694         } else {
2695                 if (chip->midcr & MIDCR_RIE) {
2696                         chip->midcr &= ~MIDCR_RIE;
2697                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2698                 }
2699         }
2700         spin_unlock_irqrestore(&chip->reg_lock, flags);
2701 }
2702
2703 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2704 {
2705         unsigned long flags;
2706         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return);
2707         unsigned char byte;
2708
2709         spin_lock_irqsave(&chip->reg_lock, flags);
2710         if (up) {
2711                 if ((chip->midcr & MIDCR_TIE) == 0) {
2712                         chip->midcr |= MIDCR_TIE;
2713                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2714                         while ((chip->midcr & MIDCR_TIE) &&
2715                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2716                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2717                                         chip->midcr &= ~MIDCR_TIE;
2718                                 } else {
2719                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2720                                 }
2721                         }
2722                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2723                 }
2724         } else {
2725                 if (chip->midcr & MIDCR_TIE) {
2726                         chip->midcr &= ~MIDCR_TIE;
2727                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2728                 }
2729         }
2730         spin_unlock_irqrestore(&chip->reg_lock, flags);
2731 }
2732
2733 static snd_rawmidi_ops_t snd_cs46xx_midi_output =
2734 {
2735         .open =         snd_cs46xx_midi_output_open,
2736         .close =        snd_cs46xx_midi_output_close,
2737         .trigger =      snd_cs46xx_midi_output_trigger,
2738 };
2739
2740 static snd_rawmidi_ops_t snd_cs46xx_midi_input =
2741 {
2742         .open =         snd_cs46xx_midi_input_open,
2743         .close =        snd_cs46xx_midi_input_close,
2744         .trigger =      snd_cs46xx_midi_input_trigger,
2745 };
2746
2747 int __devinit snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rrawmidi)
2748 {
2749         snd_rawmidi_t *rmidi;
2750         int err;
2751
2752         if (rrawmidi)
2753                 *rrawmidi = NULL;
2754         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2755                 return err;
2756         strcpy(rmidi->name, "CS46XX");
2757         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2758         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2759         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2760         rmidi->private_data = chip;
2761         chip->rmidi = rmidi;
2762         if (rrawmidi)
2763                 *rrawmidi = NULL;
2764         return 0;
2765 }
2766
2767
2768 /*
2769  * gameport interface
2770  */
2771
2772 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2773
2774 typedef struct snd_cs46xx_gameport {
2775         struct gameport info;
2776         cs46xx_t *chip;
2777 } cs46xx_gameport_t;
2778
2779 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2780 {
2781         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2782         cs46xx_t *chip;
2783         snd_assert(gp, return);
2784         chip = snd_magic_cast(cs46xx_t, gp->chip, return);
2785         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2786 }
2787
2788 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2789 {
2790         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2791         cs46xx_t *chip;
2792         snd_assert(gp, return 0);
2793         chip = snd_magic_cast(cs46xx_t, gp->chip, return 0);
2794         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2795 }
2796
2797 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2798 {
2799         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2800         cs46xx_t *chip;
2801         unsigned js1, js2, jst;
2802
2803         snd_assert(gp, return 0);
2804         chip = snd_magic_cast(cs46xx_t, gp->chip, return 0);
2805
2806         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2807         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2808         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2809
2810         *buttons = (~jst >> 4) & 0x0F;
2811
2812         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2813         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2814         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2815         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2816
2817         for(jst=0;jst<4;++jst)
2818                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2819         return 0;
2820 }
2821
2822 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2823 {
2824         switch (mode) {
2825         case GAMEPORT_MODE_COOKED:
2826                 return 0;
2827         case GAMEPORT_MODE_RAW:
2828                 return 0;
2829         default:
2830                 return -1;
2831         }
2832         return 0;
2833 }
2834
2835 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2836 {
2837         cs46xx_gameport_t *gp;
2838         gp = kmalloc(sizeof(*gp), GFP_KERNEL);
2839         if (! gp) {
2840                 snd_printk("cannot allocate gameport area\n");
2841                 return;
2842         }
2843         memset(gp, 0, sizeof(*gp));
2844         gp->info.open = snd_cs46xx_gameport_open;
2845         gp->info.read = snd_cs46xx_gameport_read;
2846         gp->info.trigger = snd_cs46xx_gameport_trigger;
2847         gp->info.cooked_read = snd_cs46xx_gameport_cooked_read;
2848         gp->chip = chip;
2849         chip->gameport = gp;
2850
2851         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2852         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2853         gameport_register_port(&gp->info);
2854 }
2855
2856 #else
2857
2858 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2859 {
2860 }
2861
2862 #endif /* CONFIG_GAMEPORT */
2863
2864 /*
2865  *  proc interface
2866  */
2867
2868 static long snd_cs46xx_io_read(snd_info_entry_t *entry, void *file_private_data,
2869                                struct file *file, char __user *buf, long count)
2870 {
2871         long size;
2872         snd_cs46xx_region_t *region = (snd_cs46xx_region_t *)entry->private_data;
2873
2874         size = count;
2875         if (file->f_pos + (size_t)size > region->size)
2876                 size = region->size - file->f_pos;
2877         if (size > 0) {
2878                 if (copy_to_user_fromio(buf, region->remap_addr + file->f_pos, size))
2879                         return -EFAULT;
2880                 file->f_pos += size;
2881         }
2882         return size;
2883 }
2884
2885 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2886         .read = snd_cs46xx_io_read,
2887 };
2888
2889 static int __devinit snd_cs46xx_proc_init(snd_card_t * card, cs46xx_t *chip)
2890 {
2891         snd_info_entry_t *entry;
2892         int idx;
2893
2894         for (idx = 0; idx < 5; idx++) {
2895                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2896                 if (! snd_card_proc_new(card, region->name, &entry)) {
2897                         entry->content = SNDRV_INFO_CONTENT_DATA;
2898                         entry->private_data = chip;
2899                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2900                         entry->size = region->size;
2901                         entry->mode = S_IFREG | S_IRUSR;
2902                 }
2903         }
2904 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2905         cs46xx_dsp_proc_init(card, chip);
2906 #endif
2907         return 0;
2908 }
2909
2910 static int snd_cs46xx_proc_done(cs46xx_t *chip)
2911 {
2912 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2913         cs46xx_dsp_proc_done(chip);
2914 #endif
2915         return 0;
2916 }
2917
2918 /*
2919  * stop the h/w
2920  */
2921 static void snd_cs46xx_hw_stop(cs46xx_t *chip)
2922 {
2923         unsigned int tmp;
2924
2925         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2926         tmp &= ~0x0000f03f;
2927         tmp |=  0x00000010;
2928         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2929
2930         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2931         tmp &= ~0x0000003f;
2932         tmp |=  0x00000011;
2933         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2934
2935         /*
2936          *  Stop playback DMA.
2937          */
2938         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2939         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2940
2941         /*
2942          *  Stop capture DMA.
2943          */
2944         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2945         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2946
2947         /*
2948          *  Reset the processor.
2949          */
2950         snd_cs46xx_reset(chip);
2951
2952         snd_cs46xx_proc_stop(chip);
2953
2954         /*
2955          *  Power down the PLL.
2956          */
2957         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2958
2959         /*
2960          *  Turn off the Processor by turning off the software clock enable flag in
2961          *  the clock control register.
2962          */
2963         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2964         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2965 }
2966
2967
2968 static int snd_cs46xx_free(cs46xx_t *chip)
2969 {
2970         int idx;
2971
2972         snd_assert(chip != NULL, return -EINVAL);
2973
2974         if (chip->active_ctrl)
2975                 chip->active_ctrl(chip, 1);
2976
2977 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2978         if (chip->gameport) {
2979                 gameport_unregister_port(&chip->gameport->info);
2980                 kfree(chip->gameport);
2981         }
2982 #endif
2983
2984         if (chip->amplifier_ctrl)
2985                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2986
2987         snd_cs46xx_proc_done(chip);
2988
2989         if (chip->region.idx[0].resource)
2990                 snd_cs46xx_hw_stop(chip);
2991
2992         for (idx = 0; idx < 5; idx++) {
2993                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2994                 if (region->remap_addr)
2995                         iounmap((void *) region->remap_addr);
2996                 if (region->resource) {
2997                         release_resource(region->resource);
2998                         kfree_nocheck(region->resource);
2999                 }
3000         }
3001         if (chip->irq >= 0)
3002                 free_irq(chip->irq, (void *)chip);
3003
3004         if (chip->active_ctrl)
3005                 chip->active_ctrl(chip, -chip->amplifier);
3006
3007 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3008         if (chip->dsp_spos_instance) {
3009                 cs46xx_dsp_spos_destroy(chip);
3010                 chip->dsp_spos_instance = NULL;
3011         }
3012 #endif
3013
3014         snd_magic_kfree(chip);
3015         return 0;
3016 }
3017
3018 static int snd_cs46xx_dev_free(snd_device_t *device)
3019 {
3020         cs46xx_t *chip = snd_magic_cast(cs46xx_t, device->device_data, return -ENXIO);
3021         return snd_cs46xx_free(chip);
3022 }
3023
3024 /*
3025  *  initialize chip
3026  */
3027 static int snd_cs46xx_chip_init(cs46xx_t *chip)
3028 {
3029         int timeout;
3030
3031         /*
3032          *  First, blast the clock control register to zero so that the PLL starts
3033          *  out in a known state, and blast the master serial port control register
3034          *  to zero so that the serial ports also start out in a known state.
3035          */
3036         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
3037         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
3038
3039         /*
3040          *  If we are in AC97 mode, then we must set the part to a host controlled
3041          *  AC-link.  Otherwise, we won't be able to bring up the link.
3042          */
3043 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3044         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
3045                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
3046         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3047 #else
3048         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3049 #endif
3050
3051         /*
3052          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3053          *  spec) and then drive it high.  This is done for non AC97 modes since
3054          *  there might be logic external to the CS461x that uses the ARST# line
3055          *  for a reset.
3056          */
3057         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3058 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3059         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3060 #endif
3061         udelay(50);
3062         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3063 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3064         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3065 #endif
3066
3067         /*
3068          *  The first thing we do here is to enable sync generation.  As soon
3069          *  as we start receiving bit clock, we'll start producing the SYNC
3070          *  signal.
3071          */
3072         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3073 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3074         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3075 #endif
3076
3077         /*
3078          *  Now wait for a short while to allow the AC97 part to start
3079          *  generating bit clock (so we don't try to start the PLL without an
3080          *  input clock).
3081          */
3082         mdelay(10);
3083
3084         /*
3085          *  Set the serial port timing configuration, so that
3086          *  the clock control circuit gets its clock from the correct place.
3087          */
3088         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3089
3090         /*
3091          *  Write the selected clock control setup to the hardware.  Do not turn on
3092          *  SWCE yet (if requested), so that the devices clocked by the output of
3093          *  PLL are not clocked until the PLL is stable.
3094          */
3095         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3096         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3097         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3098
3099         /*
3100          *  Power up the PLL.
3101          */
3102         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3103
3104         /*
3105          *  Wait until the PLL has stabilized.
3106          */
3107         set_current_state(TASK_UNINTERRUPTIBLE);
3108         schedule_timeout(HZ/10); /* 100ms */
3109
3110         /*
3111          *  Turn on clocking of the core so that we can setup the serial ports.
3112          */
3113         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3114
3115         /*
3116          * Enable FIFO  Host Bypass
3117          */
3118         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3119
3120         /*
3121          *  Fill the serial port FIFOs with silence.
3122          */
3123         snd_cs46xx_clear_serial_FIFOs(chip);
3124
3125         /*
3126          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3127          */
3128         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3129
3130         /*
3131          *  Write the serial port configuration to the part.  The master
3132          *  enable bit is not set until all other values have been written.
3133          */
3134         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3135         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3136         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3137
3138
3139 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3140         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3141         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3142         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3143         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3144         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3145 #endif
3146
3147         mdelay(5);
3148
3149
3150         /*
3151          * Wait for the codec ready signal from the AC97 codec.
3152          */
3153         timeout = 150;
3154         while (timeout-- > 0) {
3155                 /*
3156                  *  Read the AC97 status register to see if we've seen a CODEC READY
3157                  *  signal from the AC97 codec.
3158                  */
3159                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3160                         goto ok1;
3161                 set_current_state(TASK_UNINTERRUPTIBLE);
3162                 schedule_timeout((HZ+99)/100);
3163         }
3164
3165
3166         snd_printk("create - never read codec ready from AC'97\n");
3167         snd_printk("it is not probably bug, try to use CS4236 driver\n");
3168         return -EIO;
3169  ok1:
3170 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3171         {
3172                 int count;
3173                 for (count = 0; count < 150; count++) {
3174                         /* First, we want to wait for a short time. */
3175                         udelay(25);
3176
3177                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3178                                 break;
3179                 }
3180
3181                 /*
3182                  *  Make sure CODEC is READY.
3183                  */
3184                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3185                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3186         }
3187 #endif
3188
3189         /*
3190          *  Assert the vaid frame signal so that we can start sending commands
3191          *  to the AC97 codec.
3192          */
3193         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3194 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3195         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3196 #endif
3197
3198
3199         /*
3200          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3201          *  the codec is pumping ADC data across the AC-link.
3202          */
3203         timeout = 150;
3204         while (timeout-- > 0) {
3205                 /*
3206                  *  Read the input slot valid register and see if input slots 3 and
3207                  *  4 are valid yet.
3208                  */
3209                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3210                         goto ok2;
3211                 set_current_state(TASK_UNINTERRUPTIBLE);
3212                 schedule_timeout((HZ+99)/100);
3213         }
3214
3215 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3216         snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3217         return -EIO;
3218 #else
3219         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3220            Reloading the driver may help, if there's other soundcards
3221            with the same problem I would like to know. (Benny) */
3222
3223         snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3224         snd_printk("       Try reloading the ALSA driver, if you find something\n");
3225         snd_printk("       broken or not working on your soundcard upon\n");
3226         snd_printk("       this message please report to alsa-devel@lists.sourceforge.net\n");
3227
3228         return -EIO;
3229 #endif
3230  ok2:
3231
3232         /*
3233          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3234          *  commense the transfer of digital audio data to the AC97 codec.
3235          */
3236
3237         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3238
3239
3240         /*
3241          *  Power down the DAC and ADC.  We will power them up (if) when we need
3242          *  them.
3243          */
3244         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3245
3246         /*
3247          *  Turn off the Processor by turning off the software clock enable flag in
3248          *  the clock control register.
3249          */
3250         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3251         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3252
3253         return 0;
3254 }
3255
3256 /*
3257  *  start and load DSP
3258  */
3259 int __devinit snd_cs46xx_start_dsp(cs46xx_t *chip)
3260 {
3261         unsigned int tmp;
3262         /*
3263          *  Reset the processor.
3264          */
3265         snd_cs46xx_reset(chip);
3266         /*
3267          *  Download the image to the processor.
3268          */
3269 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3270 #if 0
3271         if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3272                 snd_printk(KERN_ERR "image download error\n");
3273                 return -EIO;
3274         }
3275 #endif
3276
3277         if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3278                 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3279                 return -EIO;
3280         }
3281
3282         if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3283                 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3284                 return -EIO;
3285         }
3286
3287         if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3288                 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3289                 return -EIO;
3290         }
3291
3292         if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3293                 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3294                 return -EIO;
3295         }
3296
3297         if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3298                 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3299                 return -EIO;
3300         }
3301
3302         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3303                 return -EIO;
3304 #else
3305         /* old image */
3306         if (snd_cs46xx_download_image(chip) < 0) {
3307                 snd_printk("image download error\n");
3308                 return -EIO;
3309         }
3310
3311         /*
3312          *  Stop playback DMA.
3313          */
3314         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3315         chip->play_ctl = tmp & 0xffff0000;
3316         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3317 #endif
3318
3319         /*
3320          *  Stop capture DMA.
3321          */
3322         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3323         chip->capt.ctl = tmp & 0x0000ffff;
3324         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3325
3326         mdelay(5);
3327
3328         snd_cs46xx_set_play_sample_rate(chip, 8000);
3329         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3330
3331         snd_cs46xx_proc_start(chip);
3332
3333         /*
3334          *  Enable interrupts on the part.
3335          */
3336         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3337
3338         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3339         tmp &= ~0x0000f03f;
3340         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3341
3342         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3343         tmp &= ~0x0000003f;
3344         tmp |=  0x00000001;
3345         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3346
3347 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3348         /* set the attenuation to 0dB */
3349         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3350         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3351 #endif
3352
3353         return 0;
3354 }
3355
3356
3357 /*
3358  *      AMP control - null AMP
3359  */
3360
3361 static void amp_none(cs46xx_t *chip, int change)
3362 {
3363 }
3364
3365 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3366 static int voyetra_setup_eapd_slot(cs46xx_t *chip)
3367 {
3368
3369         u32 idx, valid_slots,tmp,powerdown = 0;
3370         u16 modem_power,pin_config,logic_type;
3371
3372         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3373
3374         /*
3375          *  See if the devices are powered down.  If so, we must power them up first
3376          *  or they will not respond.
3377          */
3378         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3379
3380         if (!(tmp & CLKCR1_SWCE)) {
3381                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3382                 powerdown = 1;
3383         }
3384
3385         /*
3386          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3387          * stuff.
3388          */
3389         if(chip->nr_ac97_codecs != 2) {
3390                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3391                 return -EINVAL;
3392         }
3393
3394         modem_power = snd_cs46xx_codec_read (chip,
3395                                              AC97_EXTENDED_MSTATUS,
3396                                              CS46XX_SECONDARY_CODEC_INDEX);
3397         modem_power &=0xFEFF;
3398
3399         snd_cs46xx_codec_write(chip,
3400                                AC97_EXTENDED_MSTATUS, modem_power,
3401                                CS46XX_SECONDARY_CODEC_INDEX);
3402
3403         /*
3404          * Set GPIO pin's 7 and 8 so that they are configured for output.
3405          */
3406         pin_config = snd_cs46xx_codec_read (chip,
3407                                             AC97_GPIO_CFG,
3408                                             CS46XX_SECONDARY_CODEC_INDEX);
3409         pin_config &=0x27F;
3410
3411         snd_cs46xx_codec_write(chip,
3412                                AC97_GPIO_CFG, pin_config,
3413                                CS46XX_SECONDARY_CODEC_INDEX);
3414
3415         /*
3416          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3417          */
3418
3419         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3420                                            CS46XX_SECONDARY_CODEC_INDEX);
3421         logic_type &=0x27F;
3422
3423         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3424                                 CS46XX_SECONDARY_CODEC_INDEX);
3425
3426         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3427         valid_slots |= 0x200;
3428         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3429
3430         if ( cs46xx_wait_for_fifo(chip,1) ) {
3431           snd_printdd("FIFO is busy\n");
3432
3433           return -EINVAL;
3434         }
3435
3436         /*
3437          * Fill slots 12 with the correct value for the GPIO pins.
3438          */
3439         for(idx = 0x90; idx <= 0x9F; idx++) {
3440                 /*
3441                  * Initialize the fifo so that bits 7 and 8 are on.
3442                  *
3443                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3444                  * the left.  0x1800 corresponds to bits 7 and 8.
3445                  */
3446                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3447
3448                 /*
3449                  * Wait for command to complete
3450                  */
3451                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3452                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3453
3454                         return -EINVAL;
3455                 }
3456
3457                 /*
3458                  * Write the serial port FIFO index.
3459                  */
3460                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3461
3462                 /*
3463                  * Tell the serial port to load the new value into the FIFO location.
3464                  */
3465                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3466         }
3467
3468         /* wait for last command to complete */
3469         cs46xx_wait_for_fifo(chip,200);
3470
3471         /*
3472          *  Now, if we powered up the devices, then power them back down again.
3473          *  This is kinda ugly, but should never happen.
3474          */
3475         if (powerdown)
3476                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3477
3478         return 0;
3479 }
3480 #endif
3481
3482 /*
3483  *      Crystal EAPD mode
3484  */
3485
3486 static void amp_voyetra(cs46xx_t *chip, int change)
3487 {
3488         /* Manage the EAPD bit on the Crystal 4297
3489            and the Analog AD1885 */
3490
3491 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3492         int old = chip->amplifier;
3493 #endif
3494         int oval, val;
3495
3496         chip->amplifier += change;
3497         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3498                                      CS46XX_PRIMARY_CODEC_INDEX);
3499         val = oval;
3500         if (chip->amplifier) {
3501                 /* Turn the EAPD amp on */
3502                 val |= 0x8000;
3503         } else {
3504                 /* Turn the EAPD amp off */
3505                 val &= ~0x8000;
3506         }
3507         if (val != oval) {
3508                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3509                                        CS46XX_PRIMARY_CODEC_INDEX);
3510                 if (chip->eapd_switch)
3511                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3512                                        &chip->eapd_switch->id);
3513         }
3514
3515 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3516         if (chip->amplifier && !old) {
3517                 voyetra_setup_eapd_slot(chip);
3518         }
3519 #endif
3520 }
3521
3522 static void hercules_init(cs46xx_t *chip)
3523 {
3524         /* default: AMP off, and SPDIF input optical */
3525         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3526         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3527 }
3528
3529
3530 /*
3531  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3532  */
3533 static void amp_hercules(cs46xx_t *chip, int change)
3534 {
3535         int old = chip->amplifier;
3536         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3537         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3538
3539         chip->amplifier += change;
3540         if (chip->amplifier && !old) {
3541                 snd_printdd ("Hercules amplifier ON\n");
3542
3543                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3544                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3545                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3546                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3547         } else if (old && !chip->amplifier) {
3548                 snd_printdd ("Hercules amplifier OFF\n");
3549                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3550                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3551         }
3552 }
3553
3554 static void voyetra_mixer_init (cs46xx_t *chip)
3555 {
3556         snd_printdd ("initializing Voyetra mixer\n");
3557
3558         /* Enable SPDIF out */
3559         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3560         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3561 }
3562
3563 static void hercules_mixer_init (cs46xx_t *chip)
3564 {
3565 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3566         unsigned int idx;
3567         int err;
3568         snd_card_t *card = chip->card;
3569 #endif
3570
3571         /* set EGPIO to default */
3572         hercules_init(chip);
3573
3574         snd_printdd ("initializing Hercules mixer\n");
3575
3576 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3577         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3578                 snd_kcontrol_t *kctl;
3579
3580                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3581                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3582                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3583                         break;
3584                 }
3585         }
3586 #endif
3587 }
3588
3589
3590 #if 0
3591 /*
3592  *      Untested
3593  */
3594
3595 static void amp_voyetra_4294(cs46xx_t *chip, int change)
3596 {
3597         chip->amplifier += change;
3598
3599         if (chip->amplifier) {
3600                 /* Switch the GPIO pins 7 and 8 to open drain */
3601                 snd_cs46xx_codec_write(chip, 0x4C,
3602                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3603                 snd_cs46xx_codec_write(chip, 0x4E,
3604                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3605                 /* Now wake the AMP (this might be backwards) */
3606                 snd_cs46xx_codec_write(chip, 0x54,
3607                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3608         } else {
3609                 snd_cs46xx_codec_write(chip, 0x54,
3610                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3611         }
3612 }
3613 #endif
3614
3615
3616 /*
3617  * piix4 pci ids
3618  */
3619 #ifndef PCI_VENDOR_ID_INTEL
3620 #define PCI_VENDOR_ID_INTEL 0x8086
3621 #endif /* PCI_VENDOR_ID_INTEL */
3622
3623 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3624 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3625 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3626
3627 /*
3628  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3629  *      whenever we need to beat on the chip.
3630  *
3631  *      The original idea and code for this hack comes from David Kaiser at
3632  *      Linuxcare. Perhaps one day Crystal will document their chips well
3633  *      enough to make them useful.
3634  */
3635
3636 static void clkrun_hack(cs46xx_t *chip, int change)
3637 {
3638         u16 control, nval;
3639
3640         if (chip->acpi_dev == NULL)
3641                 return;
3642
3643         chip->amplifier += change;
3644
3645         /* Read ACPI port */
3646         nval = control = inw(chip->acpi_port + 0x10);
3647
3648         /* Flip CLKRUN off while running */
3649         if (! chip->amplifier)
3650                 nval |= 0x2000;
3651         else
3652                 nval &= ~0x2000;
3653         if (nval != control)
3654                 outw(nval, chip->acpi_port + 0x10);
3655 }
3656
3657
3658 /*
3659  * detect intel piix4
3660  */
3661 static void clkrun_init(cs46xx_t *chip)
3662 {
3663         u8 pp;
3664
3665         chip->acpi_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3666         if (chip->acpi_dev == NULL)
3667                 return;         /* Not a thinkpad thats for sure */
3668
3669         /* Find the control port */
3670         pci_read_config_byte(chip->acpi_dev, 0x41, &pp);
3671         chip->acpi_port = pp << 8;
3672 }
3673
3674
3675 /*
3676  * Card subid table
3677  */
3678
3679 struct cs_card_type
3680 {
3681         u16 vendor;
3682         u16 id;
3683         char *name;
3684         void (*init)(cs46xx_t *);
3685         void (*amp)(cs46xx_t *, int);
3686         void (*active)(cs46xx_t *, int);
3687         void (*mixer_init)(cs46xx_t *);
3688 };
3689
3690 static struct cs_card_type __devinitdata cards[] = {
3691         {
3692                 .vendor = 0x1489,
3693                 .id = 0x7001,
3694                 .name = "Genius Soundmaker 128 value",
3695                 /* nothing special */
3696         },
3697         {
3698                 .vendor = 0x5053,
3699                 .id = 0x3357,
3700                 .name = "Voyetra",
3701                 .amp = amp_voyetra,
3702                 .mixer_init = voyetra_mixer_init,
3703         },
3704         {
3705                 .vendor = 0x1071,
3706                 .id = 0x6003,
3707                 .name = "Mitac MI6020/21",
3708                 .amp = amp_voyetra,
3709         },
3710         {
3711                 .vendor = 0x14AF,
3712                 .id = 0x0050,
3713                 .name = "Hercules Game Theatre XP",
3714                 .amp = amp_hercules,
3715                 .mixer_init = hercules_mixer_init,
3716         },
3717         {
3718                 .vendor = 0x1681,
3719                 .id = 0x0050,
3720                 .name = "Hercules Game Theatre XP",
3721                 .amp = amp_hercules,
3722                 .mixer_init = hercules_mixer_init,
3723         },
3724         {
3725                 .vendor = 0x1681,
3726                 .id = 0x0051,
3727                 .name = "Hercules Game Theatre XP",
3728                 .amp = amp_hercules,
3729                 .mixer_init = hercules_mixer_init,
3730
3731         },
3732         {
3733                 .vendor = 0x1681,
3734                 .id = 0x0052,
3735                 .name = "Hercules Game Theatre XP",
3736                 .amp = amp_hercules,
3737                 .mixer_init = hercules_mixer_init,
3738         },
3739         {
3740                 .vendor = 0x1681,
3741                 .id = 0x0053,
3742                 .name = "Hercules Game Theatre XP",
3743                 .amp = amp_hercules,
3744                 .mixer_init = hercules_mixer_init,
3745         },
3746         {
3747                 .vendor = 0x1681,
3748                 .id = 0x0054,
3749                 .name = "Hercules Game Theatre XP",
3750                 .amp = amp_hercules,
3751                 .mixer_init = hercules_mixer_init,
3752         },
3753         /* Teratec */
3754         {
3755                 .vendor = 0x153b,
3756                 .id = 0x1136,
3757                 .name = "Terratec SiXPack 5.1",
3758         },
3759         /* Not sure if the 570 needs the clkrun hack */
3760         {
3761                 .vendor = PCI_VENDOR_ID_IBM,
3762                 .id = 0x0132,
3763                 .name = "Thinkpad 570",
3764                 .init = clkrun_init,
3765                 .active = clkrun_hack,
3766         },
3767         {
3768                 .vendor = PCI_VENDOR_ID_IBM,
3769                 .id = 0x0153,
3770                 .name = "Thinkpad 600X/A20/T20",
3771                 .init = clkrun_init,
3772                 .active = clkrun_hack,
3773         },
3774         {
3775                 .vendor = PCI_VENDOR_ID_IBM,
3776                 .id = 0x1010,
3777                 .name = "Thinkpad 600E (unsupported)",
3778         },
3779         {} /* terminator */
3780 };
3781
3782
3783 /*
3784  * APM support
3785  */
3786 #ifdef CONFIG_PM
3787 static int snd_cs46xx_suspend(snd_card_t *card, unsigned int state)
3788 {
3789         cs46xx_t *chip = snd_magic_cast(cs46xx_t, card->pm_private_data, return -EINVAL);
3790         int amp_saved;
3791
3792         snd_pcm_suspend_all(chip->pcm);
3793         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3794         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3795
3796         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3797         if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3798                 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3799
3800         amp_saved = chip->amplifier;
3801         /* turn off amp */
3802         chip->amplifier_ctrl(chip, -chip->amplifier);
3803         snd_cs46xx_hw_stop(chip);
3804         /* disable CLKRUN */
3805         chip->active_ctrl(chip, -chip->amplifier);
3806         chip->amplifier = amp_saved; /* restore the status */
3807         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3808         return 0;
3809 }
3810
3811 static int snd_cs46xx_resume(snd_card_t *card, unsigned int state)
3812 {
3813         cs46xx_t *chip = snd_magic_cast(cs46xx_t, card->pm_private_data, return -EINVAL);
3814         int amp_saved;
3815
3816         pci_enable_device(chip->pci);
3817         amp_saved = chip->amplifier;
3818         chip->amplifier = 0;
3819         chip->active_ctrl(chip, 1); /* force to on */
3820
3821         snd_cs46xx_chip_init(chip);
3822
3823 #if 0
3824         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3825                                chip->ac97_general_purpose);
3826         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3827                                chip->ac97_powerdown);
3828         mdelay(10);
3829         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3830                                chip->ac97_powerdown);
3831         mdelay(5);
3832 #endif
3833
3834         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3835         if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3836                 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3837
3838         if (amp_saved)
3839                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3840         else
3841                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3842         chip->amplifier = amp_saved;
3843         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3844         return 0;
3845 }
3846 #endif /* CONFIG_PM */
3847
3848
3849 /*
3850  */
3851
3852 int __devinit snd_cs46xx_create(snd_card_t * card,
3853                       struct pci_dev * pci,
3854                       int external_amp, int thinkpad,
3855                       cs46xx_t ** rchip)
3856 {
3857         cs46xx_t *chip;
3858         int err, idx;
3859         snd_cs46xx_region_t *region;
3860         struct cs_card_type *cp;
3861         u16 ss_card, ss_vendor;
3862         static snd_device_ops_t ops = {
3863                 .dev_free =     snd_cs46xx_dev_free,
3864         };
3865
3866         *rchip = NULL;
3867
3868         /* enable PCI device */
3869         if ((err = pci_enable_device(pci)) < 0)
3870                 return err;
3871
3872         chip = snd_magic_kcalloc(cs46xx_t, 0, GFP_KERNEL);
3873         if (chip == NULL)
3874                 return -ENOMEM;
3875         spin_lock_init(&chip->reg_lock);
3876 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3877         init_MUTEX(&chip->spos_mutex);
3878 #endif
3879         chip->card = card;
3880         chip->pci = pci;
3881         chip->irq = -1;
3882         chip->ba0_addr = pci_resource_start(pci, 0);
3883         chip->ba1_addr = pci_resource_start(pci, 1);
3884         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3885             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3886                 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip->ba0_addr, chip->ba1_addr);
3887                 snd_cs46xx_free(chip);
3888                 return -ENOMEM;
3889         }
3890
3891         region = &chip->region.name.ba0;
3892         strcpy(region->name, "CS46xx_BA0");
3893         region->base = chip->ba0_addr;
3894         region->size = CS46XX_BA0_SIZE;
3895
3896         region = &chip->region.name.data0;
3897         strcpy(region->name, "CS46xx_BA1_data0");
3898         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3899         region->size = CS46XX_BA1_DATA0_SIZE;
3900
3901         region = &chip->region.name.data1;
3902         strcpy(region->name, "CS46xx_BA1_data1");
3903         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3904         region->size = CS46XX_BA1_DATA1_SIZE;
3905
3906         region = &chip->region.name.pmem;
3907         strcpy(region->name, "CS46xx_BA1_pmem");
3908         region->base = chip->ba1_addr + BA1_SP_PMEM;
3909         region->size = CS46XX_BA1_PRG_SIZE;
3910
3911         region = &chip->region.name.reg;
3912         strcpy(region->name, "CS46xx_BA1_reg");
3913         region->base = chip->ba1_addr + BA1_SP_REG;
3914         region->size = CS46XX_BA1_REG_SIZE;
3915
3916         memset(&chip->dma_dev, 0, sizeof(chip->dma_dev));
3917         chip->dma_dev.type = SNDRV_DMA_TYPE_DEV;
3918         chip->dma_dev.dev = snd_dma_pci_data(pci);
3919
3920         /* set up amp and clkrun hack */
3921         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3922         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3923
3924         for (cp = &cards[0]; cp->name; cp++) {
3925                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3926                         snd_printdd ("hack for %s enabled\n", cp->name);
3927
3928                         chip->amplifier_ctrl = cp->amp;
3929                         chip->active_ctrl = cp->active;
3930                         chip->mixer_init = cp->mixer_init;
3931
3932                         if (cp->init)
3933                                 cp->init(chip);
3934                         break;
3935                 }
3936         }
3937
3938         if (external_amp) {
3939                 snd_printk("Crystal EAPD support forced on.\n");
3940                 chip->amplifier_ctrl = amp_voyetra;
3941         }
3942
3943         if (thinkpad) {
3944                 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3945                 chip->active_ctrl = clkrun_hack;
3946                 clkrun_init(chip);
3947         }
3948
3949         if (chip->amplifier_ctrl == NULL)
3950                 chip->amplifier_ctrl = amp_none;
3951         if (chip->active_ctrl == NULL)
3952                 chip->active_ctrl = amp_none;
3953
3954         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3955
3956         pci_set_master(pci);
3957
3958         for (idx = 0; idx < 5; idx++) {
3959                 region = &chip->region.idx[idx];
3960                 if ((region->resource = request_mem_region(region->base, region->size, region->name)) == NULL) {
3961                         snd_printk("unable to request memory region 0x%lx-0x%lx\n", region->base, region->base + region->size - 1);
3962                         snd_cs46xx_free(chip);
3963                         return -EBUSY;
3964                 }
3965                 region->remap_addr = (unsigned long) ioremap_nocache(region->base, region->size);
3966                 if (region->remap_addr == 0) {
3967                         snd_printk("%s ioremap problem\n", region->name);
3968                         snd_cs46xx_free(chip);
3969                         return -ENOMEM;
3970                 }
3971         }
3972
3973         if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS46XX", (void *) chip)) {
3974                 snd_printk("unable to grab IRQ %d\n", pci->irq);
3975                 snd_cs46xx_free(chip);
3976                 return -EBUSY;
3977         }
3978         chip->irq = pci->irq;
3979
3980 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3981         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3982         if (chip->dsp_spos_instance == NULL) {
3983                 snd_cs46xx_free(chip);
3984                 return -ENOMEM;
3985         }
3986 #endif
3987
3988         err = snd_cs46xx_chip_init(chip);
3989         if (err < 0) {
3990                 snd_cs46xx_free(chip);
3991                 return err;
3992         }
3993
3994         snd_cs46xx_proc_init(card, chip);
3995
3996         snd_card_set_pm_callback(card, snd_cs46xx_suspend, snd_cs46xx_resume, chip);
3997
3998         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3999                 snd_cs46xx_free(chip);
4000                 return err;
4001         }
4002
4003         chip->active_ctrl(chip, -1); /* disable CLKRUN */
4004
4005         snd_card_set_dev(card, &pci->dev);
4006
4007         *rchip = chip;
4008         return 0;
4009 }