2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 * Routines for control of EMU10K1 chips
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <sound/driver.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/slab.h>
34 #include <linux/vmalloc.h>
36 #include <sound/core.h>
37 #include <sound/emu10k1.h>
40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Creative Labs, Inc.");
41 MODULE_DESCRIPTION("Routines for control of EMU10K1 chips");
42 MODULE_LICENSE("GPL");
45 /*************************************************************************
47 *************************************************************************/
49 void snd_emu10k1_voice_init(emu10k1_t * emu, int ch)
51 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
52 snd_emu10k1_ptr_write(emu, IP, ch, 0);
53 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
54 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
55 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
56 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
57 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
59 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
60 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
61 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
62 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
63 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
64 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
66 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
67 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
68 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
69 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
70 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
71 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
72 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
73 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
75 /*** these are last so OFF prevents writing ***/
76 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
77 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
78 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
79 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
80 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
82 /* Audigy extra stuffs */
84 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
85 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
86 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
87 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
88 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
89 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
90 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
94 static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
97 unsigned int silent_page;
99 emu->fx8010.itram_size = (16 * 1024)/2;
100 emu->fx8010.etram_pages.area = NULL;
101 emu->fx8010.etram_pages.bytes = 0;
103 /* disable audio and lock cache */
104 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
106 /* reset recording buffers */
107 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
108 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
109 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
110 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
111 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
112 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
114 /* disable channel interrupt */
115 outl(0, emu->port + INTE);
116 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
117 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
118 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
119 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
122 snd_emu10k1_ptr_write(emu, 0x5e, 0, 0xf00); /* ?? */
123 snd_emu10k1_ptr_write(emu, 0x5f, 0, 0x3); /* ?? */
126 /* init envelope engine */
127 for (ch = 0; ch < NUM_G; ch++) {
128 emu->voices[ch].emu = emu;
129 emu->voices[ch].number = ch;
130 snd_emu10k1_voice_init(emu, ch);
134 * Init to 0x02109204 :
135 * Clock accuracy = 0 (1000ppm)
136 * Sample Rate = 2 (48kHz)
137 * Audio Channel = 1 (Left of 2)
138 * Source Number = 0 (Unspecified)
139 * Generation Status = 1 (Original for Cat Code 12)
140 * Cat Code = 12 (Digital Signal Mixer)
142 * Emphasis = 0 (None)
143 * CP = 1 (Copyright unasserted)
144 * AN = 0 (Audio data)
147 snd_emu10k1_ptr_write(emu, SPCS0, 0,
149 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
150 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
151 SPCS_GENERATIONSTATUS | 0x00001200 |
152 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
153 snd_emu10k1_ptr_write(emu, SPCS1, 0,
155 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
156 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
157 SPCS_GENERATIONSTATUS | 0x00001200 |
158 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
159 snd_emu10k1_ptr_write(emu, SPCS2, 0,
161 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
162 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
163 SPCS_GENERATIONSTATUS | 0x00001200 |
164 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
166 if (emu->audigy && emu->revision == 4) { /* audigy2 */
167 /* Hacks for Alice3 to work independent of haP16V driver */
170 //Setup SRCMulti_I2S SamplingRate
171 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
174 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
176 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
177 outl(0x600000, emu->port + 0x20);
178 outl(0x14, emu->port + 0x24);
180 /* Setup SRCMulti Input Audio Enable */
181 outl(0x6E0000, emu->port + 0x20);
182 outl(0xFF00FF00, emu->port + 0x24);
186 * Clear page with silence & setup all pointers to this page
188 memset(emu->silent_page.area, 0, PAGE_SIZE);
189 silent_page = emu->silent_page.addr << 1;
190 for (idx = 0; idx < MAXPAGES; idx++)
191 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
192 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
193 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
194 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
196 silent_page = (emu->silent_page.addr << 1) | MAP_PTI_MASK;
197 for (ch = 0; ch < NUM_G; ch++) {
198 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
199 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
204 * Mute Disable Audio = 0
205 * Lock Tank Memory = 1
206 * Lock Sound Memory = 0
210 if (emu->revision == 4) /* audigy2 */
211 outl(HCFG_AUDIOENABLE |
212 HCFG_AC3ENABLE_CDSPDIF |
213 HCFG_AC3ENABLE_GPSPDIF |
214 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
216 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
217 } else if (emu->model == 0x20 ||
218 emu->model == 0xc400 ||
219 (emu->model == 0x21 && emu->revision < 6))
220 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
222 // With on-chip joystick
223 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
225 if (enable_ir) { /* enable IR for SB Live */
227 unsigned int reg = inl(emu->port + A_IOCFG);
228 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
230 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
232 outl(reg, emu->port + A_IOCFG);
234 unsigned int reg = inl(emu->port + HCFG);
235 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
237 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
239 outl(reg, emu->port + HCFG);
243 if (emu->audigy) { /* enable analog output */
244 unsigned int reg = inl(emu->port + A_IOCFG);
245 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
249 * Initialize the effect engine
251 if ((err = snd_emu10k1_init_efx(emu)) < 0)
255 * Enable the audio bit
257 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
259 /* Enable analog/digital outs on audigy */
261 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
263 if (emu->revision == 4) { /* audigy2 */
264 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
265 * This has to be done after init ALice3 I2SOut beyond 48KHz.
266 * So, sequence is important. */
267 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
269 /* Disable routing from AC97 line out to Front speakers */
270 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
277 /* FIXME: the following routine disables LiveDrive-II !! */
280 tmp = inl(emu->port + HCFG);
281 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
282 outl(tmp|0x800, emu->port + HCFG);
284 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
286 outl(tmp, emu->port + HCFG);
292 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
294 emu->reserved_page = (emu10k1_memblk_t *)snd_emu10k1_synth_alloc(emu, 4096);
295 if (emu->reserved_page)
296 emu->reserved_page->map_locked = 1;
301 static int snd_emu10k1_done(emu10k1_t * emu)
305 outl(0, emu->port + INTE);
310 for (ch = 0; ch < NUM_G; ch++)
311 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
312 for (ch = 0; ch < NUM_G; ch++) {
313 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
314 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
315 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
316 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
319 /* reset recording buffers */
320 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
321 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
322 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
323 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
324 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
325 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
326 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
327 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
328 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
330 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
332 snd_emu10k1_ptr_write(emu, DBG, 0, 0x8000);
334 /* disable channel interrupt */
335 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
336 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
337 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
338 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
340 /* remove reserved page */
341 if (emu->reserved_page != NULL) {
342 snd_emu10k1_synth_free(emu, (snd_util_memblk_t *)emu->reserved_page);
343 emu->reserved_page = NULL;
346 /* disable audio and lock cache */
347 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
348 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
350 snd_emu10k1_free_efx(emu);
355 /*************************************************************************
356 * ECARD functional implementation
357 *************************************************************************/
359 /* In A1 Silicon, these bits are in the HC register */
360 #define HOOKN_BIT (1L << 12)
361 #define HANDN_BIT (1L << 11)
362 #define PULSEN_BIT (1L << 10)
364 #define EC_GDI1 (1 << 13)
365 #define EC_GDI0 (1 << 14)
367 #define EC_NUM_CONTROL_BITS 20
369 #define EC_AC3_DATA_SELN 0x0001L
370 #define EC_EE_DATA_SEL 0x0002L
371 #define EC_EE_CNTRL_SELN 0x0004L
372 #define EC_EECLK 0x0008L
373 #define EC_EECS 0x0010L
374 #define EC_EESDO 0x0020L
375 #define EC_TRIM_CSN 0x0040L
376 #define EC_TRIM_SCLK 0x0080L
377 #define EC_TRIM_SDATA 0x0100L
378 #define EC_TRIM_MUTEN 0x0200L
379 #define EC_ADCCAL 0x0400L
380 #define EC_ADCRSTN 0x0800L
381 #define EC_DACCAL 0x1000L
382 #define EC_DACMUTEN 0x2000L
383 #define EC_LEDN 0x4000L
385 #define EC_SPDIF0_SEL_SHIFT 15
386 #define EC_SPDIF1_SEL_SHIFT 17
387 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
388 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
389 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
390 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
391 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
392 * be incremented any time the EEPROM's
393 * format is changed. */
395 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
397 /* Addresses for special values stored in to EEPROM */
398 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
399 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
400 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
402 #define EC_LAST_PROMFILE_ADDR 0x2f
404 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
405 * can be up to 30 characters in length
406 * and is stored as a NULL-terminated
407 * ASCII string. Any unused bytes must be
408 * filled with zeros */
409 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
412 /* Most of this stuff is pretty self-evident. According to the hardware
413 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
414 * offset problem. Weird.
416 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
420 #define EC_DEFAULT_ADC_GAIN 0xC4C4
421 #define EC_DEFAULT_SPDIF0_SEL 0x0
422 #define EC_DEFAULT_SPDIF1_SEL 0x4
424 /**************************************************************************
425 * @func Clock bits into the Ecard's control latch. The Ecard uses a
426 * control latch will is loaded bit-serially by toggling the Modem control
427 * lines from function 2 on the E8010. This function hides these details
428 * and presents the illusion that we are actually writing to a distinct
432 static void snd_emu10k1_ecard_write(emu10k1_t * emu, unsigned int value)
434 unsigned short count;
436 unsigned long hc_port;
437 unsigned int hc_value;
439 hc_port = emu->port + HCFG;
440 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
441 outl(hc_value, hc_port);
443 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
445 /* Set up the value */
446 data = ((value & 0x1) ? PULSEN_BIT : 0);
449 outl(hc_value | data, hc_port);
451 /* Clock the shift register */
452 outl(hc_value | data | HANDN_BIT, hc_port);
453 outl(hc_value | data, hc_port);
457 outl(hc_value | HOOKN_BIT, hc_port);
458 outl(hc_value, hc_port);
461 /**************************************************************************
462 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
463 * trim value consists of a 16bit value which is composed of two
464 * 8 bit gain/trim values, one for the left channel and one for the
465 * right channel. The following table maps from the Gain/Attenuation
466 * value in decibels into the corresponding bit pattern for a single
470 static void snd_emu10k1_ecard_setadcgain(emu10k1_t * emu,
475 /* Enable writing to the TRIM registers */
476 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
478 /* Do it again to insure that we meet hold time requirements */
479 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
481 for (bit = (1 << 15); bit; bit >>= 1) {
484 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
487 value |= EC_TRIM_SDATA;
490 snd_emu10k1_ecard_write(emu, value);
491 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
492 snd_emu10k1_ecard_write(emu, value);
495 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
498 static int __devinit snd_emu10k1_ecard_init(emu10k1_t * emu)
500 unsigned int hc_value;
502 /* Set up the initial settings */
503 emu->ecard_ctrl = EC_RAW_RUN_MODE |
504 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
505 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
507 /* Step 0: Set the codec type in the hardware control register
508 * and enable audio output */
509 hc_value = inl(emu->port + HCFG);
510 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
511 inl(emu->port + HCFG);
513 /* Step 1: Turn off the led and deassert TRIM_CS */
514 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
516 /* Step 2: Calibrate the ADC and DAC */
517 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
519 /* Step 3: Wait for awhile; XXX We can't get away with this
520 * under a real operating system; we'll need to block and wait that
522 snd_emu10k1_wait(emu, 48000);
524 /* Step 4: Switch off the DAC and ADC calibration. Note
525 * That ADC_CAL is actually an inverted signal, so we assert
526 * it here to stop calibration. */
527 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
529 /* Step 4: Switch into run mode */
530 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
532 /* Step 5: Set the analog input gain */
533 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
539 * Create the EMU10K1 instance
542 static int snd_emu10k1_free(emu10k1_t *emu)
544 if (emu->res_port != NULL) { /* avoid access to already used hardware */
545 snd_emu10k1_fx8010_tram_setup(emu, 0);
546 snd_emu10k1_done(emu);
549 snd_util_memhdr_free(emu->memhdr);
550 if (emu->silent_page.area)
551 snd_dma_free_pages(&emu->dma_dev, &emu->silent_page);
552 if (emu->ptb_pages.area)
553 snd_dma_free_pages(&emu->dma_dev, &emu->ptb_pages);
554 if (emu->page_ptr_table)
555 vfree(emu->page_ptr_table);
556 if (emu->page_addr_table)
557 vfree(emu->page_addr_table);
559 release_resource(emu->res_port);
560 kfree_nocheck(emu->res_port);
563 free_irq(emu->irq, (void *)emu);
564 snd_magic_kfree(emu);
568 static int snd_emu10k1_dev_free(snd_device_t *device)
570 emu10k1_t *emu = snd_magic_cast(emu10k1_t, device->device_data, return -ENXIO);
571 return snd_emu10k1_free(emu);
574 int __devinit snd_emu10k1_create(snd_card_t * card,
575 struct pci_dev * pci,
576 unsigned short extin_mask,
577 unsigned short extout_mask,
578 long max_cache_bytes,
585 static snd_device_ops_t ops = {
586 .dev_free = snd_emu10k1_dev_free,
591 // is_audigy = (int)pci->driver_data;
592 is_audigy = (pci->device == 0x0004);
594 /* enable PCI device */
595 if ((err = pci_enable_device(pci)) < 0)
598 emu = snd_magic_kcalloc(emu10k1_t, 0, GFP_KERNEL);
601 /* set the DMA transfer mask */
602 emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
603 if (pci_set_dma_mask(pci, emu->dma_mask) < 0 ||
604 pci_set_consistent_dma_mask(pci, emu->dma_mask) < 0) {
605 snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
606 snd_magic_kfree(emu);
610 spin_lock_init(&emu->reg_lock);
611 spin_lock_init(&emu->emu_lock);
612 spin_lock_init(&emu->voice_lock);
613 spin_lock_init(&emu->synth_lock);
614 spin_lock_init(&emu->memblk_lock);
615 init_MUTEX(&emu->ptb_lock);
616 init_MUTEX(&emu->fx8010.lock);
617 INIT_LIST_HEAD(&emu->mapped_link_head);
618 INIT_LIST_HEAD(&emu->mapped_order_link_head);
622 emu->get_synth_voice = NULL;
623 emu->port = pci_resource_start(pci, 0);
625 emu->audigy = is_audigy;
627 emu->gpr_base = A_FXGPREGBASE;
629 emu->gpr_base = FXGPREGBASE;
631 if ((emu->res_port = request_region(emu->port, 0x20, "EMU10K1")) == NULL) {
632 snd_emu10k1_free(emu);
636 if (request_irq(pci->irq, snd_emu10k1_interrupt, SA_INTERRUPT|SA_SHIRQ, "EMU10K1", (void *)emu)) {
637 snd_emu10k1_free(emu);
642 memset(&emu->dma_dev, 0, sizeof(emu->dma_dev));
643 emu->dma_dev.type = SNDRV_DMA_TYPE_DEV;
644 emu->dma_dev.dev = snd_dma_pci_data(pci);
646 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
647 if (snd_dma_alloc_pages(&emu->dma_dev, 32 * 1024, &emu->ptb_pages) < 0) {
648 snd_emu10k1_free(emu);
652 emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
653 emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
654 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
655 snd_emu10k1_free(emu);
659 if (snd_dma_alloc_pages(&emu->dma_dev, EMUPAGESIZE, &emu->silent_page) < 0) {
660 snd_emu10k1_free(emu);
663 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
664 if (emu->memhdr == NULL) {
665 snd_emu10k1_free(emu);
668 emu->memhdr->block_extra_size = sizeof(emu10k1_memblk_t) - sizeof(snd_util_memblk_t);
671 /* read revision & serial */
672 pci_read_config_byte(pci, PCI_REVISION_ID, (char *)&emu->revision);
673 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
674 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
675 emu->card_type = EMU10K1_CARD_CREATIVE;
676 if (emu->serial == 0x40011102) {
677 emu->card_type = EMU10K1_CARD_EMUAPS;
679 emu->no_ac97 = 1; /* APS has no AC97 chip */
681 else if (emu->revision == 4 && emu->serial == 0x10051102) {
682 /* Audigy 2 EX has apparently no effective AC97 controls
683 * (for both input and output), so we skip the AC97 detections
685 snd_printdd(KERN_INFO "Audigy2 EX is detected. skpping ac97.\n");
689 emu->fx8010.fxbus_mask = 0x303f;
692 if (extout_mask == 0)
693 extout_mask = 0x7fff;
694 emu->fx8010.extin_mask = extin_mask;
695 emu->fx8010.extout_mask = extout_mask;
698 if ((err = snd_emu10k1_ecard_init(emu)) < 0) {
699 snd_emu10k1_free(emu);
703 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
704 does not support this, it shouldn't do any harm */
705 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
708 if ((err = snd_emu10k1_init(emu, enable_ir)) < 0) {
709 snd_emu10k1_free(emu);
713 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0) {
714 snd_emu10k1_free(emu);
718 snd_emu10k1_proc_init(emu);
720 snd_card_set_dev(card, &pci->dev);
726 EXPORT_SYMBOL(snd_emu10k1_synth_alloc);
727 EXPORT_SYMBOL(snd_emu10k1_synth_free);
728 EXPORT_SYMBOL(snd_emu10k1_synth_bzero);
729 EXPORT_SYMBOL(snd_emu10k1_synth_copy_from_user);
730 EXPORT_SYMBOL(snd_emu10k1_memblk_map);
732 EXPORT_SYMBOL(snd_emu10k1_voice_alloc);
733 EXPORT_SYMBOL(snd_emu10k1_voice_free);
735 EXPORT_SYMBOL(snd_emu10k1_ptr_read);
736 EXPORT_SYMBOL(snd_emu10k1_ptr_write);