sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <linux/moduleparam.h>
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/rawmidi.h>
  35 #ifdef CHIP1371
  36 #include <sound/ac97_codec.h>
  37 #else
  38 #include <sound/ak4531_codec.h>
  39 #endif
  40 #include <sound/initval.h>
  41 #include <sound/asoundef.h>
  42
  43 #define chip_t ensoniq_t
  44
  45 #ifndef CHIP1371
  46 #undef CHIP1370
  47 #define CHIP1370
  48 #endif
  49
  50 #ifdef CHIP1370
  51 #define DRIVER_NAME "ENS1370"
  52 #else
  53 #define DRIVER_NAME "ENS1371"
  54 #endif
  55
  56
  57 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  58 MODULE_LICENSE("GPL");
  59 MODULE_CLASSES("{sound}");
  60 #ifdef CHIP1370
  61 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  62 MODULE_DEVICES("{{Ensoniq,AudioPCI-97 ES1370},"
  63                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  64 #endif
  65 #ifdef CHIP1371
  66 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  67 MODULE_DEVICES("{{Ensoniq,AudioPCI ES1371/73},"
  68                 "{Ensoniq,AudioPCI ES1373},"
  69                 "{Creative Labs,Ectiva EV1938},"
  70                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  71                 "{Creative Labs,Vibra PCI128},"
  72                 "{Ectiva,EV1938}}");
  73 #endif
  74
  75 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  76 #define SUPPORT_JOYSTICK
  77 #endif
  78
  79 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  80 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  81 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  82 #ifdef SUPPORT_JOYSTICK
  83 #ifdef CHIP1371
  84 static int joystick_port[SNDRV_CARDS];
  85 #else
  86 static int joystick[SNDRV_CARDS];
  87 #endif
  88 #endif
  89 static int boot_devs;
  90
  91 module_param_array(index, int, boot_devs, 0444);
  92 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  93 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  94 module_param_array(id, charp, boot_devs, 0444);
  95 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  96 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  97 module_param_array(enable, bool, boot_devs, 0444);
  98 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  99 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
 100 #ifdef SUPPORT_JOYSTICK
 101 #ifdef CHIP1371
 102 module_param_array(joystick_port, int, boot_devs, 0444);
 103 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 104 MODULE_PARM_SYNTAX(joystick_port, SNDRV_ENABLED ",allows:{{0},{1},{0x200},{0x208},{0x210},{0x218}},dialog:list");
 105 #else
 106 module_param_array(joystick, bool, boot_devs, 0444);
 107 MODULE_PARM_DESC(joystick, "Enable joystick.");
 108 MODULE_PARM_SYNTAX(joystick, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
 109 #endif
 110 #endif /* SUPPORT_JOYSTICK */
 111
 112 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
 113 #define PCI_DEVICE_ID_ENSONIQ_CT5880    0x5880
 114 #endif
 115 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
 116 #define PCI_DEVICE_ID_ENSONIQ_ES1371    0x1371
 117 #endif
 118
 119 /* ES1371 chip ID */
 120 /* This is a little confusing because all ES1371 compatible chips have the
 121    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 122    This is only significant if you want to enable features on the later parts.
 123    Yes, I know it's stupid and why didn't we use the sub IDs?
 124 */
 125 #define ES1371REV_ES1373_A  0x04
 126 #define ES1371REV_ES1373_B  0x06
 127 #define ES1371REV_CT5880_A  0x07
 128 #define CT5880REV_CT5880_C  0x02
 129 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 130 #define CT5880REV_CT5880_E  0x04        /* mw */
 131 #define ES1371REV_ES1371_B  0x09
 132 #define EV1938REV_EV1938_A  0x00
 133 #define ES1371REV_ES1373_8  0x08
 134
 135 /*
 136  * Direct registers
 137  */
 138
 139 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 140
 141 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 142 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 143 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 144 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 145 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 146 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 147 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 148 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 149 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 150 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 151 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 152 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 153 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 154 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 155 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 156 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 157 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 158 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 159 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 160 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 161 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 162 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 163 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 164 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 165 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 166 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 167 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 168 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 169 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 170 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 171 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 172 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 173 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 174 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 175 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 176 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 177 #define   ES_UART_EN            (1<<3)          /* UART enable */
 178 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 179 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 180 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 181 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 182 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 183 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 184 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 185 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 186 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 187 #define   ES_1373_REAR_BIT26    (1<<26)
 188 #define   ES_1373_REAR_BIT24    (1<<24)
 189 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 190 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 191 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 192 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 193 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 194 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 195 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 196 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 197 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 198 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 199 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 200 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 201 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 202 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 203 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 204 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 205 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 206 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 207 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 208 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 209 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 210 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 211 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 212 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 213 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 214 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 215 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 216 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 217 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 218 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 219 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 220 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 221 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 222 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 223 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 224 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 225 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 226 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 227 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 228 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 229 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 230 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 231 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 232 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 233 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 234
 235 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 236 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 237 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 238 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 239 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 240 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 241 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 242 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 243 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 244 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 245 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 246 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 247 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 248
 249 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 250 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 251 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 252 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 253 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 254 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 255 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 256 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 257 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 258 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 259 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 260 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 261 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 262 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 263 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 264 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 265 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 266 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 267 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 268 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 269 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 270 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 271 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 272
 273 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 274
 275 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 276 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 277 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 278 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 279 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 280 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 281 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 282 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 283 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 284 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 285 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 286 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 287 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 288 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 289 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 290 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 291 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 292 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 293 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 294 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 295 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 296 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 297 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 298 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 299 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 300 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 301 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 302
 303 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 304 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 305 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 306 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 307 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 308 #define   ES_REG_COUNTM         (0xffff<<0)
 309 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 310
 311 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 312 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 313 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 314 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 315 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 316 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 317 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 318 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 319 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 320 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 321 #define   ES_REG_FSIZEM          (0xffff<<0)
 322 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 323 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 324 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 325
 326 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 327 #define   ES_REG_UF_VALID        (1<<8)
 328 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 329 #define   ES_REG_UF_BYTEM        (0xff<<0)
 330 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 331
 332
 333 /*
 334  *  Pages
 335  */
 336
 337 #define ES_PAGE_DAC     0x0c
 338 #define ES_PAGE_ADC     0x0d
 339 #define ES_PAGE_UART    0x0e
 340 #define ES_PAGE_UART1   0x0f
 341
 342 /*
 343  *  Sample rate converter addresses
 344  */
 345
 346 #define ES_SMPREG_DAC1          0x70
 347 #define ES_SMPREG_DAC2          0x74
 348 #define ES_SMPREG_ADC           0x78
 349 #define ES_SMPREG_VOL_ADC       0x6c
 350 #define ES_SMPREG_VOL_DAC1      0x7c
 351 #define ES_SMPREG_VOL_DAC2      0x7e
 352 #define ES_SMPREG_TRUNC_N       0x00
 353 #define ES_SMPREG_INT_REGS      0x01
 354 #define ES_SMPREG_ACCUM_FRAC    0x02
 355 #define ES_SMPREG_VFREQ_FRAC    0x03
 356
 357 /*
 358  *  Some contants
 359  */
 360
 361 #define ES_1370_SRCLOCK    1411200
 362 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 363
 364 /*
 365  *  Open modes
 366  */
 367
 368 #define ES_MODE_PLAY1   0x0001
 369 #define ES_MODE_PLAY2   0x0002
 370 #define ES_MODE_CAPTURE 0x0004
 371
 372 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 373 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 374
 375 /*
 376
 377  */
 378
 379 typedef struct _snd_ensoniq ensoniq_t;
 380
 381 struct _snd_ensoniq {
 382         spinlock_t reg_lock;
 383
 384         int irq;
 385
 386         unsigned long playback1size;
 387         unsigned long playback2size;
 388         unsigned long capture3size;
 389
 390         unsigned long port;
 391         struct resource *res_port;
 392         unsigned int mode;
 393         unsigned int uartm;     /* UART mode */
 394
 395         unsigned int ctrl;      /* control register */
 396         unsigned int sctrl;     /* serial control register */
 397         unsigned int cssr;      /* control status register */
 398         unsigned int uartc;     /* uart control register */
 399         unsigned int rev;       /* chip revision */
 400
 401         union {
 402 #ifdef CHIP1371
 403                 struct {
 404                         ac97_t *ac97;
 405                 } es1371;
 406 #else
 407                 struct {
 408                         int pclkdiv_lock;
 409                         ak4531_t *ak4531;
 410                 } es1370;
 411 #endif
 412         } u;
 413
 414         struct pci_dev *pci;
 415         unsigned short subsystem_vendor_id;
 416         unsigned short subsystem_device_id;
 417         snd_card_t *card;
 418         snd_pcm_t *pcm1;        /* DAC1/ADC PCM */
 419         snd_pcm_t *pcm2;        /* DAC2 PCM */
 420         snd_pcm_substream_t *playback1_substream;
 421         snd_pcm_substream_t *playback2_substream;
 422         snd_pcm_substream_t *capture_substream;
 423         unsigned int p1_dma_size;
 424         unsigned int p2_dma_size;
 425         unsigned int c_dma_size;
 426         unsigned int p1_period_size;
 427         unsigned int p2_period_size;
 428         unsigned int c_period_size;
 429         snd_rawmidi_t *rmidi;
 430         snd_rawmidi_substream_t *midi_input;
 431         snd_rawmidi_substream_t *midi_output;
 432
 433         unsigned int spdif;
 434         unsigned int spdif_default;
 435         unsigned int spdif_stream;
 436
 437 #ifdef CHIP1370
 438         struct snd_dma_device dma_dev;
 439         struct snd_dma_buffer dma_bug;
 440 #endif
 441
 442 #ifdef SUPPORT_JOYSTICK
 443         struct gameport gameport;
 444 #endif
 445 };
 446
 447 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 448
 449 static struct pci_device_id snd_audiopci_ids[] = {
 450 #ifdef CHIP1370
 451         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 452 #endif
 453 #ifdef CHIP1371
 454         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 455         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 456         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 457 #endif
 458         { 0, }
 459 };
 460
 461 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 462
 463 /*
 464  *  constants
 465  */
 466
 467 #define POLL_COUNT      0xa000
 468
 469 #ifdef CHIP1370
 470 static unsigned int snd_es1370_fixed_rates[] =
 471         {5512, 11025, 22050, 44100};
 472 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
 473         .count = 4,
 474         .list = snd_es1370_fixed_rates,
 475         .mask = 0,
 476 };
 477 static ratnum_t es1370_clock = {
 478         .num = ES_1370_SRCLOCK,
 479         .den_min = 29,
 480         .den_max = 353,
 481         .den_step = 1,
 482 };
 483 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
 484         .nrats = 1,
 485         .rats = &es1370_clock,
 486 };
 487 #else
 488 static ratden_t es1371_dac_clock = {
 489         .num_min = 3000 * (1 << 15),
 490         .num_max = 48000 * (1 << 15),
 491         .num_step = 3000,
 492         .den = 1 << 15,
 493 };
 494 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
 495         .nrats = 1,
 496         .rats = &es1371_dac_clock,
 497 };
 498 static ratnum_t es1371_adc_clock = {
 499         .num = 48000 << 15,
 500         .den_min = 32768,
 501         .den_max = 393216,
 502         .den_step = 1,
 503 };
 504 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
 505         .nrats = 1,
 506         .rats = &es1371_adc_clock,
 507 };
 508 #endif
 509 static const unsigned int snd_ensoniq_sample_shift[] =
 510         {0, 1, 1, 2};
 511
 512 /*
 513  *  common I/O routines
 514  */
 515
 516 #ifdef CHIP1371
 517
 518 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
 519 {
 520         unsigned int t, r = 0;
 521
 522         for (t = 0; t < POLL_COUNT; t++) {
 523                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 524                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 525                         return r;
 526         }
 527         snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
 528         return 0;
 529 }
 530
 531 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
 532 {
 533         unsigned int temp, i, orig, r;
 534
 535         /* wait for ready */
 536         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 537
 538         /* expose the SRC state bits */
 539         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 540                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 541         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 542         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 543
 544         /* now, wait for busy and the correct time to read */
 545         temp = snd_es1371_wait_src_ready(ensoniq);
 546
 547         if ((temp & 0x00870000) != 0x00010000) {
 548                 /* wait for the right state */
 549                 for (i = 0; i < POLL_COUNT; i++) {
 550                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 551                         if ((temp & 0x00870000) == 0x00010000)
 552                                 break;
 553                 }
 554         }
 555
 556         /* hide the state bits */
 557         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 558                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 559         r |= ES_1371_SRC_RAM_ADDRO(reg);
 560         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 561
 562         return temp;
 563 }
 564
 565 static void snd_es1371_src_write(ensoniq_t * ensoniq,
 566                                  unsigned short reg, unsigned short data)
 567 {
 568         unsigned int r;
 569
 570         r = snd_es1371_wait_src_ready(ensoniq) &
 571             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 572              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 573         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 574         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 575 }
 576
 577 #endif /* CHIP1371 */
 578
 579 #ifdef CHIP1370
 580
 581 static void snd_es1370_codec_write(ak4531_t *ak4531,
 582                                    unsigned short reg, unsigned short val)
 583 {
 584         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ak4531->private_data, return);
 585         unsigned long flags;
 586         unsigned long end_time = jiffies + HZ / 10;
 587
 588 #if 0
 589         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 590 #endif
 591         do {
 592                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 593                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 594                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 595                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 596                         return;
 597                 }
 598                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 599 #if 0
 600                 set_current_state(TASK_UNINTERRUPTIBLE);
 601                 schedule_timeout(1);
 602 #endif
 603         } while (time_after(end_time, jiffies));
 604         snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
 605 }
 606
 607 #endif /* CHIP1370 */
 608
 609 #ifdef CHIP1371
 610
 611 static void snd_es1371_codec_write(ac97_t *ac97,
 612                                    unsigned short reg, unsigned short val)
 613 {
 614         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ac97->private_data, return);
 615         unsigned long flags;
 616         unsigned int t, x;
 617
 618         for (t = 0; t < POLL_COUNT; t++) {
 619                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 620                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 621                         /* save the current state for latter */
 622                         x = snd_es1371_wait_src_ready(ensoniq);
 623                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 624                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 625                              ES_REG(ensoniq, 1371_SMPRATE));
 626                         /* wait for not busy (state 0) first to avoid
 627                            transition states */
 628                         for (t = 0; t < POLL_COUNT; t++) {
 629                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 630                                         break;
 631                         }
 632                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 633                         for (t = 0; t < POLL_COUNT; t++) {
 634                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 635                                         break;
 636                         }
 637                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 638                         /* restore SRC reg */
 639                         snd_es1371_wait_src_ready(ensoniq);
 640                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 641                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 642                         return;
 643                 }
 644                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 645         }
 646         snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 647 }
 648
 649 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 650                                             unsigned short reg)
 651 {
 652         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ac97->private_data, return -ENXIO);
 653         unsigned long flags;
 654         unsigned int t, x, fail = 0;
 655
 656       __again:
 657         for (t = 0; t < POLL_COUNT; t++) {
 658                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 659                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 660                         /* save the current state for latter */
 661                         x = snd_es1371_wait_src_ready(ensoniq);
 662                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 663                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 664                              ES_REG(ensoniq, 1371_SMPRATE));
 665                         /* wait for not busy (state 0) first to avoid
 666                            transition states */
 667                         for (t = 0; t < POLL_COUNT; t++) {
 668                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 669                                         break;
 670                         }
 671                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 672                         for (t = 0; t < POLL_COUNT; t++) {
 673                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 674                                         break;
 675                         }
 676                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 677                         /* restore SRC reg */
 678                         snd_es1371_wait_src_ready(ensoniq);
 679                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 680                         /* wait for WIP again */
 681                         for (t = 0; t < POLL_COUNT; t++) {
 682                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 683                                         break;
 684                         }
 685                         /* now wait for the stinkin' data (RDY) */
 686                         for (t = 0; t < POLL_COUNT; t++) {
 687                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 688                                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 689                                         return ES_1371_CODEC_READ(x);
 690                                 }
 691                         }
 692                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 693                         if (++fail > 10) {
 694                                 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
 695                                 return 0;
 696                         }
 697                         goto __again;
 698                 }
 699                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 700         }
 701         snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 702         return 0;
 703 }
 704
 705 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 706 {
 707         unsigned int n, truncm, freq, result;
 708
 709         n = rate / 3000;
 710         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 711                 n--;
 712         truncm = (21 * n - 1) | 1;
 713         freq = ((48000UL << 15) / rate) * n;
 714         result = (48000UL << 15) / (freq / n);
 715         if (rate >= 24000) {
 716                 if (truncm > 239)
 717                         truncm = 239;
 718                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 719                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 720         } else {
 721                 if (truncm > 119)
 722                         truncm = 119;
 723                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 724                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 725         }
 726         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 727                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
 728                                      ((freq >> 5) & 0xfc00));
 729         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 730         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 731         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 732 }
 733
 734 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
 735 {
 736         unsigned int freq, r;
 737
 738         freq = ((rate << 15) + 1500) / 3000;
 739         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
 740         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 741         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 742                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
 743                              ((freq >> 5) & 0xfc00));
 744         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 745         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
 746         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 747 }
 748
 749 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
 750 {
 751         unsigned int freq, r;
 752
 753         freq = ((rate << 15) + 1500) / 3000;
 754         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
 755         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 756         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 757                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
 758                              ((freq >> 5) & 0xfc00));
 759         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 760         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
 761         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 762 }
 763
 764 #endif /* CHIP1371 */
 765
 766 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
 767 {
 768         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 769         switch (cmd) {
 770         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 771         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 772         {
 773                 unsigned int what = 0;
 774                 struct list_head *pos;
 775                 snd_pcm_substream_t *s;
 776                 snd_pcm_group_for_each(pos, substream) {
 777                         s = snd_pcm_group_substream_entry(pos);
 778                         if (s == ensoniq->playback1_substream) {
 779                                 what |= ES_P1_PAUSE;
 780                                 snd_pcm_trigger_done(s, substream);
 781                         } else if (s == ensoniq->playback2_substream) {
 782                                 what |= ES_P2_PAUSE;
 783                                 snd_pcm_trigger_done(s, substream);
 784                         } else if (s == ensoniq->capture_substream)
 785                                 return -EINVAL;
 786                 }
 787                 spin_lock(&ensoniq->reg_lock);
 788                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 789                         ensoniq->sctrl |= what;
 790                 else
 791                         ensoniq->sctrl &= ~what;
 792                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 793                 spin_unlock(&ensoniq->reg_lock);
 794                 break;
 795         }
 796         case SNDRV_PCM_TRIGGER_START:
 797         case SNDRV_PCM_TRIGGER_STOP:
 798         {
 799                 unsigned int what = 0;
 800                 struct list_head *pos;
 801                 snd_pcm_substream_t *s;
 802                 snd_pcm_group_for_each(pos, substream) {
 803                         s = snd_pcm_group_substream_entry(pos);
 804                         if (s == ensoniq->playback1_substream) {
 805                                 what |= ES_DAC1_EN;
 806                                 snd_pcm_trigger_done(s, substream);
 807                         } else if (s == ensoniq->playback2_substream) {
 808                                 what |= ES_DAC2_EN;
 809                                 snd_pcm_trigger_done(s, substream);
 810                         } else if (s == ensoniq->capture_substream) {
 811                                 what |= ES_ADC_EN;
 812                                 snd_pcm_trigger_done(s, substream);
 813                         }
 814                 }
 815                 spin_lock(&ensoniq->reg_lock);
 816                 if (cmd == SNDRV_PCM_TRIGGER_START)
 817                         ensoniq->ctrl |= what;
 818                 else
 819                         ensoniq->ctrl &= ~what;
 820                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 821                 spin_unlock(&ensoniq->reg_lock);
 822                 break;
 823         }
 824         default:
 825                 return -EINVAL;
 826         }
 827         return 0;
 828 }
 829
 830 /*
 831  *  PCM part
 832  */
 833
 834 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
 835                                  snd_pcm_hw_params_t * hw_params)
 836 {
 837         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 838 }
 839
 840 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
 841 {
 842         return snd_pcm_lib_free_pages(substream);
 843 }
 844
 845 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
 846 {
 847         unsigned long flags;
 848         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 849         snd_pcm_runtime_t *runtime = substream->runtime;
 850         unsigned int mode = 0;
 851
 852         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 853         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 854         if (snd_pcm_format_width(runtime->format) == 16)
 855                 mode |= 0x02;
 856         if (runtime->channels > 1)
 857                 mode |= 0x01;
 858         spin_lock_irqsave(&ensoniq->reg_lock, flags);
 859         ensoniq->ctrl &= ~ES_DAC1_EN;
 860         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 861         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 862         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 863         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 864         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 865         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 866         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 867         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
 868 #ifdef CHIP1370
 869         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 870         switch (runtime->rate) {
 871         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 872         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 873         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 874         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 875         default: snd_BUG();
 876         }
 877 #else
 878         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 879 #endif
 880         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 881         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 882         return 0;
 883 }
 884
 885 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
 886 {
 887         unsigned long flags;
 888         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 889         snd_pcm_runtime_t *runtime = substream->runtime;
 890         unsigned int mode = 0;
 891
 892         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 893         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 894         if (snd_pcm_format_width(runtime->format) == 16)
 895                 mode |= 0x02;
 896         if (runtime->channels > 1)
 897                 mode |= 0x01;
 898         spin_lock_irqsave(&ensoniq->reg_lock, flags);
 899         ensoniq->ctrl &= ~ES_DAC2_EN;
 900         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 901         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 902         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 903         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 904         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 905                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 906         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 907                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 908         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 909         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
 910 #ifdef CHIP1370
 911         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 912                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 913                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 914                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 915         }
 916 #else
 917         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 918 #endif
 919         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 920         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 921         return 0;
 922 }
 923
 924 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
 925 {
 926         unsigned long flags;
 927         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 928         snd_pcm_runtime_t *runtime = substream->runtime;
 929         unsigned int mode = 0;
 930
 931         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 932         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 933         if (snd_pcm_format_width(runtime->format) == 16)
 934                 mode |= 0x02;
 935         if (runtime->channels > 1)
 936                 mode |= 0x01;
 937         spin_lock_irqsave(&ensoniq->reg_lock, flags);
 938         ensoniq->ctrl &= ~ES_ADC_EN;
 939         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 940         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 941         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 942         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 943         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 944         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 945         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 946         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
 947 #ifdef CHIP1370
 948         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 949                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 950                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 951                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 952         }
 953 #else
 954         snd_es1371_adc_rate(ensoniq, runtime->rate);
 955 #endif
 956         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 957         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 958         return 0;
 959 }
 960
 961 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
 962 {
 963         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 964         size_t ptr;
 965
 966         spin_lock(&ensoniq->reg_lock);
 967         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 968                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 969                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 970                 ptr = bytes_to_frames(substream->runtime, ptr);
 971         } else {
 972                 ptr = 0;
 973         }
 974         spin_unlock(&ensoniq->reg_lock);
 975         return ptr;
 976 }
 977
 978 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
 979 {
 980         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 981         size_t ptr;
 982
 983         spin_lock(&ensoniq->reg_lock);
 984         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
 985                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 986                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
 987                 ptr = bytes_to_frames(substream->runtime, ptr);
 988         } else {
 989                 ptr = 0;
 990         }
 991         spin_unlock(&ensoniq->reg_lock);
 992         return ptr;
 993 }
 994
 995 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
 996 {
 997         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 998         size_t ptr;
 999
1000         spin_lock(&ensoniq->reg_lock);
1001         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1002                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1003                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1004                 ptr = bytes_to_frames(substream->runtime, ptr);
1005         } else {
1006                 ptr = 0;
1007         }
1008         spin_unlock(&ensoniq->reg_lock);
1009         return ptr;
1010 }
1011
1012 static snd_pcm_hardware_t snd_ensoniq_playback1 =
1013 {
1014         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1015                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1016                                  SNDRV_PCM_INFO_MMAP_VALID |
1017                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1018         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1019         .rates =
1020 #ifndef CHIP1370
1021                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1022 #else
1023                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1024                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1025                                  SNDRV_PCM_RATE_44100),
1026 #endif
1027         .rate_min =             4000,
1028         .rate_max =             48000,
1029         .channels_min =         1,
1030         .channels_max =         2,
1031         .buffer_bytes_max =     (128*1024),
1032         .period_bytes_min =     64,
1033         .period_bytes_max =     (128*1024),
1034         .periods_min =          1,
1035         .periods_max =          1024,
1036         .fifo_size =            0,
1037 };
1038
1039 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1040 {
1041         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1042                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1043                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1044                                  SNDRV_PCM_INFO_SYNC_START),
1045         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1046         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1047         .rate_min =             4000,
1048         .rate_max =             48000,
1049         .channels_min =         1,
1050         .channels_max =         2,
1051         .buffer_bytes_max =     (128*1024),
1052         .period_bytes_min =     64,
1053         .period_bytes_max =     (128*1024),
1054         .periods_min =          1,
1055         .periods_max =          1024,
1056         .fifo_size =            0,
1057 };
1058
1059 static snd_pcm_hardware_t snd_ensoniq_capture =
1060 {
1061         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1062                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1063                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1064         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1065         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1066         .rate_min =             4000,
1067         .rate_max =             48000,
1068         .channels_min =         1,
1069         .channels_max =         2,
1070         .buffer_bytes_max =     (128*1024),
1071         .period_bytes_min =     64,
1072         .period_bytes_max =     (128*1024),
1073         .periods_min =          1,
1074         .periods_max =          1024,
1075         .fifo_size =            0,
1076 };
1077
1078 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1079 {
1080         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1081         snd_pcm_runtime_t *runtime = substream->runtime;
1082
1083         ensoniq->mode |= ES_MODE_PLAY1;
1084         ensoniq->playback1_substream = substream;
1085         runtime->hw = snd_ensoniq_playback1;
1086         snd_pcm_set_sync(substream);
1087         spin_lock_irq(&ensoniq->reg_lock);
1088         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1089                 ensoniq->spdif_stream = ensoniq->spdif_default;
1090         spin_unlock_irq(&ensoniq->reg_lock);
1091 #ifdef CHIP1370
1092         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1093                                    &snd_es1370_hw_constraints_rates);
1094 #else
1095         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1096                                       &snd_es1371_hw_constraints_dac_clock);
1097 #endif
1098         return 0;
1099 }
1100
1101 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1102 {
1103         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1104         snd_pcm_runtime_t *runtime = substream->runtime;
1105
1106         ensoniq->mode |= ES_MODE_PLAY2;
1107         ensoniq->playback2_substream = substream;
1108         runtime->hw = snd_ensoniq_playback2;
1109         snd_pcm_set_sync(substream);
1110         spin_lock_irq(&ensoniq->reg_lock);
1111         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1112                 ensoniq->spdif_stream = ensoniq->spdif_default;
1113         spin_unlock_irq(&ensoniq->reg_lock);
1114 #ifdef CHIP1370
1115         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1116                                       &snd_es1370_hw_constraints_clock);
1117 #else
1118         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1119                                       &snd_es1371_hw_constraints_dac_clock);
1120 #endif
1121         return 0;
1122 }
1123
1124 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1125 {
1126         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1127         snd_pcm_runtime_t *runtime = substream->runtime;
1128
1129         ensoniq->mode |= ES_MODE_CAPTURE;
1130         ensoniq->capture_substream = substream;
1131         runtime->hw = snd_ensoniq_capture;
1132         snd_pcm_set_sync(substream);
1133 #ifdef CHIP1370
1134         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1135                                       &snd_es1370_hw_constraints_clock);
1136 #else
1137         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1138                                       &snd_es1371_hw_constraints_adc_clock);
1139 #endif
1140         return 0;
1141 }
1142
1143 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1144 {
1145         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1146
1147         ensoniq->playback1_substream = NULL;
1148         ensoniq->mode &= ~ES_MODE_PLAY1;
1149         return 0;
1150 }
1151
1152 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1153 {
1154         unsigned long flags;
1155         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1156
1157         ensoniq->playback2_substream = NULL;
1158         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1159 #ifdef CHIP1370
1160         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1161 #endif
1162         ensoniq->mode &= ~ES_MODE_PLAY2;
1163         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1164         return 0;
1165 }
1166
1167 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1168 {
1169         unsigned long flags;
1170         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1171
1172         ensoniq->capture_substream = NULL;
1173         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1174 #ifdef CHIP1370
1175         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1176 #endif
1177         ensoniq->mode &= ~ES_MODE_CAPTURE;
1178         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1179         return 0;
1180 }
1181
1182 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1183         .open =         snd_ensoniq_playback1_open,
1184         .close =        snd_ensoniq_playback1_close,
1185         .ioctl =        snd_pcm_lib_ioctl,
1186         .hw_params =    snd_ensoniq_hw_params,
1187         .hw_free =      snd_ensoniq_hw_free,
1188         .prepare =      snd_ensoniq_playback1_prepare,
1189         .trigger =      snd_ensoniq_trigger,
1190         .pointer =      snd_ensoniq_playback1_pointer,
1191 };
1192
1193 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1194         .open =         snd_ensoniq_playback2_open,
1195         .close =        snd_ensoniq_playback2_close,
1196         .ioctl =        snd_pcm_lib_ioctl,
1197         .hw_params =    snd_ensoniq_hw_params,
1198         .hw_free =      snd_ensoniq_hw_free,
1199         .prepare =      snd_ensoniq_playback2_prepare,
1200         .trigger =      snd_ensoniq_trigger,
1201         .pointer =      snd_ensoniq_playback2_pointer,
1202 };
1203
1204 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1205         .open =         snd_ensoniq_capture_open,
1206         .close =        snd_ensoniq_capture_close,
1207         .ioctl =        snd_pcm_lib_ioctl,
1208         .hw_params =    snd_ensoniq_hw_params,
1209         .hw_free =      snd_ensoniq_hw_free,
1210         .prepare =      snd_ensoniq_capture_prepare,
1211         .trigger =      snd_ensoniq_trigger,
1212         .pointer =      snd_ensoniq_capture_pointer,
1213 };
1214
1215 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1216 {
1217         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, pcm->private_data, return);
1218         ensoniq->pcm1 = NULL;
1219         snd_pcm_lib_preallocate_free_for_all(pcm);
1220 }
1221
1222 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1223 {
1224         snd_pcm_t *pcm;
1225         int err;
1226
1227         if (rpcm)
1228                 *rpcm = NULL;
1229 #ifdef CHIP1370
1230         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1231 #else
1232         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1233 #endif
1234         if (err < 0)
1235                 return err;
1236
1237 #ifdef CHIP1370
1238         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1239 #else
1240         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1241 #endif
1242         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1243
1244         pcm->private_data = ensoniq;
1245         pcm->private_free = snd_ensoniq_pcm_free;
1246         pcm->info_flags = 0;
1247 #ifdef CHIP1370
1248         strcpy(pcm->name, "ES1370 DAC2/ADC");
1249 #else
1250         strcpy(pcm->name, "ES1371 DAC2/ADC");
1251 #endif
1252         ensoniq->pcm1 = pcm;
1253
1254         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1255                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1256
1257         if (rpcm)
1258                 *rpcm = pcm;
1259         return 0;
1260 }
1261
1262 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1263 {
1264         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, pcm->private_data, return);
1265         ensoniq->pcm2 = NULL;
1266         snd_pcm_lib_preallocate_free_for_all(pcm);
1267 }
1268
1269 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1270 {
1271         snd_pcm_t *pcm;
1272         int err;
1273
1274         if (rpcm)
1275                 *rpcm = NULL;
1276 #ifdef CHIP1370
1277         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1278 #else
1279         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1280 #endif
1281         if (err < 0)
1282                 return err;
1283
1284 #ifdef CHIP1370
1285         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1286 #else
1287         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1288 #endif
1289         pcm->private_data = ensoniq;
1290         pcm->private_free = snd_ensoniq_pcm_free2;
1291         pcm->info_flags = 0;
1292 #ifdef CHIP1370
1293         strcpy(pcm->name, "ES1370 DAC1");
1294 #else
1295         strcpy(pcm->name, "ES1371 DAC1");
1296 #endif
1297         ensoniq->pcm2 = pcm;
1298
1299         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1300                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1301
1302         if (rpcm)
1303                 *rpcm = pcm;
1304         return 0;
1305 }
1306
1307 /*
1308  *  Mixer section
1309  */
1310
1311 /*
1312  * ENS1371 mixer (including SPDIF interface)
1313  */
1314 #ifdef CHIP1371
1315 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1316 {
1317         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1318         uinfo->count = 1;
1319         return 0;
1320 }
1321
1322 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1323                                          snd_ctl_elem_value_t * ucontrol)
1324 {
1325         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1326         spin_lock_irq(&ensoniq->reg_lock);
1327         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1328         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1329         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1330         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1331         spin_unlock_irq(&ensoniq->reg_lock);
1332         return 0;
1333 }
1334
1335 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1336                                          snd_ctl_elem_value_t * ucontrol)
1337 {
1338         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1339         unsigned int val;
1340         int change;
1341
1342         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1343               ((u32)ucontrol->value.iec958.status[1] << 8) |
1344               ((u32)ucontrol->value.iec958.status[2] << 16) |
1345               ((u32)ucontrol->value.iec958.status[3] << 24);
1346         spin_lock_irq(&ensoniq->reg_lock);
1347         change = ensoniq->spdif_default != val;
1348         ensoniq->spdif_default = val;
1349         if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1350                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1351         spin_unlock_irq(&ensoniq->reg_lock);
1352         return change;
1353 }
1354
1355 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1356                                          snd_ctl_elem_value_t * ucontrol)
1357 {
1358         ucontrol->value.iec958.status[0] = 0xff;
1359         ucontrol->value.iec958.status[1] = 0xff;
1360         ucontrol->value.iec958.status[2] = 0xff;
1361         ucontrol->value.iec958.status[3] = 0xff;
1362         return 0;
1363 }
1364
1365 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1366                                          snd_ctl_elem_value_t * ucontrol)
1367 {
1368         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1369         spin_lock_irq(&ensoniq->reg_lock);
1370         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1371         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1372         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1373         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1374         spin_unlock_irq(&ensoniq->reg_lock);
1375         return 0;
1376 }
1377
1378 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1379                                         snd_ctl_elem_value_t * ucontrol)
1380 {
1381         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1382         unsigned int val;
1383         int change;
1384
1385         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1386               ((u32)ucontrol->value.iec958.status[1] << 8) |
1387               ((u32)ucontrol->value.iec958.status[2] << 16) |
1388               ((u32)ucontrol->value.iec958.status[3] << 24);
1389         spin_lock_irq(&ensoniq->reg_lock);
1390         change = ensoniq->spdif_stream != val;
1391         ensoniq->spdif_stream = val;
1392         if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1393                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1394         spin_unlock_irq(&ensoniq->reg_lock);
1395         return change;
1396 }
1397
1398 #define ES1371_SPDIF(xname) \
1399 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1400   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1401
1402 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1403 {
1404         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1405         uinfo->count = 1;
1406         uinfo->value.integer.min = 0;
1407         uinfo->value.integer.max = 1;
1408         return 0;
1409 }
1410
1411 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1412 {
1413         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1414
1415         spin_lock_irq(&ensoniq->reg_lock);
1416         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1417         spin_unlock_irq(&ensoniq->reg_lock);
1418         return 0;
1419 }
1420
1421 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1422 {
1423         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1424         unsigned int nval1, nval2;
1425         int change;
1426
1427         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1428         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1429         spin_lock_irq(&ensoniq->reg_lock);
1430         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1431         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1432         ensoniq->ctrl |= nval1;
1433         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1434         ensoniq->cssr |= nval2;
1435         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1436         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1437         spin_unlock_irq(&ensoniq->reg_lock);
1438         return change;
1439 }
1440
1441
1442 /* spdif controls */
1443 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1444         ES1371_SPDIF("IEC958 Playback Switch"),
1445         {
1446                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1447                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1448                 .info =         snd_ens1373_spdif_info,
1449                 .get =          snd_ens1373_spdif_default_get,
1450                 .put =          snd_ens1373_spdif_default_put,
1451         },
1452         {
1453                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1454                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1455                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1456                 .info =         snd_ens1373_spdif_info,
1457                 .get =          snd_ens1373_spdif_mask_get
1458         },
1459         {
1460                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1461                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1462                 .info =         snd_ens1373_spdif_info,
1463                 .get =          snd_ens1373_spdif_stream_get,
1464                 .put =          snd_ens1373_spdif_stream_put
1465         },
1466 };
1467
1468
1469 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1470 {
1471         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1472         uinfo->count = 1;
1473         uinfo->value.integer.min = 0;
1474         uinfo->value.integer.max = 1;
1475         return 0;
1476 }
1477
1478 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1479 {
1480         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1481         int val = 0;
1482
1483         spin_lock_irq(&ensoniq->reg_lock);
1484         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1485                 val = 1;
1486         ucontrol->value.integer.value[0] = val;
1487         spin_unlock_irq(&ensoniq->reg_lock);
1488         return 0;
1489 }
1490
1491 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1492 {
1493         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1494         unsigned int nval1;
1495         int change;
1496
1497         nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1498         spin_lock_irq(&ensoniq->reg_lock);
1499         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1500         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1501         ensoniq->cssr |= nval1;
1502         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1503         spin_unlock_irq(&ensoniq->reg_lock);
1504         return change;
1505 }
1506
1507 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1508 {
1509         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1510         .name =         "AC97 2ch->4ch Copy Switch",
1511         .info =         snd_es1373_rear_info,
1512         .get =          snd_es1373_rear_get,
1513         .put =          snd_es1373_rear_put,
1514 };
1515
1516 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1517 {
1518         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1519         uinfo->count = 1;
1520         uinfo->value.integer.min = 0;
1521         uinfo->value.integer.max = 1;
1522         return 0;
1523 }
1524
1525 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1526 {
1527         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1528         int val = 0;
1529
1530         spin_lock_irq(&ensoniq->reg_lock);
1531         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1532                 val = 1;
1533         ucontrol->value.integer.value[0] = val;
1534         spin_unlock_irq(&ensoniq->reg_lock);
1535         return 0;
1536 }
1537
1538 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1539 {
1540         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1541         int changed;
1542         unsigned int ctrl;
1543
1544         spin_lock_irq(&ensoniq->reg_lock);
1545         ctrl = ensoniq->ctrl;
1546         if (ucontrol->value.integer.value[0])
1547                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1548         else
1549                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1550         changed = (ctrl != ensoniq->ctrl);
1551         if (changed)
1552                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1553         spin_unlock_irq(&ensoniq->reg_lock);
1554         return changed;
1555 }
1556
1557 static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1558 {
1559         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1560         .name =         "Line In->Rear Out Switch",
1561         .info =         snd_es1373_line_info,
1562         .get =          snd_es1373_line_get,
1563         .put =          snd_es1373_line_put,
1564 };
1565
1566 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1567 {
1568         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ac97->private_data, return);
1569         ensoniq->u.es1371.ac97 = NULL;
1570 }
1571
1572 static struct {
1573         unsigned short vid;             /* vendor ID */
1574         unsigned short did;             /* device ID */
1575         unsigned char rev;              /* revision */
1576 } es1371_spdif_present[] __devinitdata = {
1577         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1578         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1579         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1580         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1581         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1582         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1583 };
1584
1585 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1586 {
1587         snd_card_t *card = ensoniq->card;
1588         ac97_bus_t bus, *pbus;
1589         ac97_t ac97;
1590         int err, idx;
1591
1592         memset(&bus, 0, sizeof(bus));
1593         bus.write = snd_es1371_codec_write;
1594         bus.read = snd_es1371_codec_read;
1595         if ((err = snd_ac97_bus(card, &bus, &pbus)) < 0)
1596                 return err;
1597
1598         memset(&ac97, 0, sizeof(ac97));
1599         ac97.private_data = ensoniq;
1600         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1601         ac97.scaps = AC97_SCAP_AUDIO;
1602         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1603                 return err;
1604         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1605                 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1606                     ensoniq->pci->device == es1371_spdif_present[idx].did &&
1607                     ensoniq->rev == es1371_spdif_present[idx].rev) {
1608                         snd_kcontrol_t *kctl;
1609                         int i, index = 0;
1610
1611                         ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1612                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1613
1614                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1615                                 index++;
1616
1617                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1618                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1619                                 if (! kctl)
1620                                         return -ENOMEM;
1621                                 kctl->id.index = index;
1622                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1623                                         return err;
1624                         }
1625                         break;
1626                 }
1627         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1628                 /* mirror rear to front speakers */
1629                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1630                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1631                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1632                 if (err < 0)
1633                         return err;
1634         }
1635         if ((ensoniq->subsystem_vendor_id == 0x1274) &&
1636             (ensoniq->subsystem_device_id == 0x2000)) { /* GA-7DXR */
1637                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1638                  if (err < 0)
1639                          return err;
1640         }
1641
1642         return 0;
1643 }
1644
1645 #endif /* CHIP1371 */
1646
1647 /* generic control callbacks for ens1370 */
1648 #ifdef CHIP1370
1649 #define ENSONIQ_CONTROL(xname, mask) \
1650 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1651   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1652   .private_value = mask }
1653
1654 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1655 {
1656         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1657         uinfo->count = 1;
1658         uinfo->value.integer.min = 0;
1659         uinfo->value.integer.max = 1;
1660         return 0;
1661 }
1662
1663 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1664 {
1665         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1666         unsigned long flags;
1667         int mask = kcontrol->private_value;
1668
1669         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1670         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1671         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1672         return 0;
1673 }
1674
1675 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1676 {
1677         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1678         unsigned long flags;
1679         int mask = kcontrol->private_value;
1680         unsigned int nval;
1681         int change;
1682
1683         nval = ucontrol->value.integer.value[0] ? mask : 0;
1684         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1685         change = (ensoniq->ctrl & mask) != nval;
1686         ensoniq->ctrl &= ~mask;
1687         ensoniq->ctrl |= nval;
1688         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1689         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1690         return change;
1691 }
1692
1693 /*
1694  * ENS1370 mixer
1695  */
1696
1697 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1698 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1699 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1700 };
1701
1702 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1703
1704 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1705 {
1706         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ak4531->private_data, return);
1707         ensoniq->u.es1370.ak4531 = NULL;
1708 }
1709
1710 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1711 {
1712         snd_card_t *card = ensoniq->card;
1713         ak4531_t ak4531;
1714         unsigned int idx;
1715         int err;
1716
1717         /* try reset AK4531 */
1718         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1719         inw(ES_REG(ensoniq, 1370_CODEC));
1720         udelay(100);
1721         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1722         inw(ES_REG(ensoniq, 1370_CODEC));
1723         udelay(100);
1724
1725         memset(&ak4531, 0, sizeof(ak4531));
1726         ak4531.write = snd_es1370_codec_write;
1727         ak4531.private_data = ensoniq;
1728         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1729         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1730                 return err;
1731         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1732                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1733                 if (err < 0)
1734                         return err;
1735         }
1736         return 0;
1737 }
1738
1739 #endif /* CHIP1370 */
1740
1741 #ifdef SUPPORT_JOYSTICK
1742 static int snd_ensoniq_joystick(ensoniq_t *ensoniq, long port)
1743 {
1744 #ifdef CHIP1371
1745         if (port == 1) { /* auto-detect */
1746                 for (port = 0x200; port <= 0x218; port += 8)
1747                         if (request_region(port, 8, "ens137x: gameport"))
1748                                 break;
1749                 if (port > 0x218) {
1750                         snd_printk("no gameport available\n");
1751                         return -EBUSY;
1752                 }
1753         } else
1754 #endif
1755         {
1756                 if (!request_region(port, 8, "ens137x: gameport")) {
1757                         snd_printk("gameport io port 0x%03x in use", ensoniq->gameport.io);
1758                         return -EBUSY;
1759                 }
1760         }
1761         ensoniq->gameport.io = port;
1762         ensoniq->ctrl |= ES_JYSTK_EN;
1763 #ifdef CHIP1371
1764         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1765         ensoniq->ctrl |= ES_1371_JOY_ASEL((ensoniq->gameport.io - 0x200) / 8);
1766 #endif
1767         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1768         gameport_register_port(&ensoniq->gameport);
1769         return 0;
1770 }
1771
1772 static void snd_ensoniq_joystick_free(ensoniq_t *ensoniq)
1773 {
1774         gameport_unregister_port(&ensoniq->gameport);
1775         ensoniq->ctrl &= ~ES_JYSTK_EN;
1776         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1777         release_region(ensoniq->gameport.io, 8);
1778 }
1779 #endif /* SUPPORT_JOYSTICK */
1780
1781 /*
1782
1783  */
1784
1785 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1786                                   snd_info_buffer_t * buffer)
1787 {
1788         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, entry->private_data, return);
1789
1790 #ifdef CHIP1370
1791         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1792 #else
1793         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1794 #endif
1795         snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1796 #ifdef CHIP1370
1797         snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1798         snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1799 #else
1800         snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1801 #endif
1802 }
1803
1804 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1805 {
1806         snd_info_entry_t *entry;
1807
1808         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1809                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1810 }
1811
1812 /*
1813
1814  */
1815
1816 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1817 {
1818 #ifdef SUPPORT_JOYSTICK
1819         if (ensoniq->ctrl & ES_JYSTK_EN)
1820                 snd_ensoniq_joystick_free(ensoniq);
1821 #endif
1822         if (ensoniq->irq < 0)
1823                 goto __hw_end;
1824 #ifdef CHIP1370
1825         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1826         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1827 #else
1828         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1829         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1830 #endif
1831         synchronize_irq(ensoniq->irq);
1832         pci_set_power_state(ensoniq->pci, 3);
1833       __hw_end:
1834 #ifdef CHIP1370
1835         if (ensoniq->dma_bug.area)
1836                 snd_dma_free_pages(&ensoniq->dma_dev, &ensoniq->dma_bug);
1837 #endif
1838         if (ensoniq->res_port) {
1839                 release_resource(ensoniq->res_port);
1840                 kfree_nocheck(ensoniq->res_port);
1841         }
1842         if (ensoniq->irq >= 0)
1843                 free_irq(ensoniq->irq, (void *)ensoniq);
1844         snd_magic_kfree(ensoniq);
1845         return 0;
1846 }
1847
1848 static int snd_ensoniq_dev_free(snd_device_t *device)
1849 {
1850         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, device->device_data, return -ENXIO);
1851         return snd_ensoniq_free(ensoniq);
1852 }
1853
1854 #ifdef CHIP1371
1855 static struct {
1856         unsigned short svid;            /* subsystem vendor ID */
1857         unsigned short sdid;            /* subsystem device ID */
1858 } es1371_amplifier_hack[] = {
1859         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1860         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1861         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1862         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1863         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1864 };
1865 static struct {
1866         unsigned short vid;             /* vendor ID */
1867         unsigned short did;             /* device ID */
1868         unsigned char rev;              /* revision */
1869 } es1371_ac97_reset_hack[] = {
1870         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1871         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1872         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1873         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1874         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1875         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1876 };
1877 #endif
1878
1879 static int __devinit snd_ensoniq_create(snd_card_t * card,
1880                                      struct pci_dev *pci,
1881                                      ensoniq_t ** rensoniq)
1882 {
1883         ensoniq_t *ensoniq;
1884         unsigned short cmdw;
1885         unsigned char cmdb;
1886 #ifdef CHIP1371
1887         int idx;
1888 #endif
1889         int err;
1890         static snd_device_ops_t ops = {
1891                 .dev_free =     snd_ensoniq_dev_free,
1892         };
1893
1894         *rensoniq = NULL;
1895         if ((err = pci_enable_device(pci)) < 0)
1896                 return err;
1897         ensoniq = snd_magic_kcalloc(ensoniq_t, 0, GFP_KERNEL);
1898         if (ensoniq == NULL)
1899                 return -ENOMEM;
1900         spin_lock_init(&ensoniq->reg_lock);
1901         ensoniq->card = card;
1902         ensoniq->pci = pci;
1903         ensoniq->irq = -1;
1904         ensoniq->port = pci_resource_start(pci, 0);
1905         if ((ensoniq->res_port = request_region(ensoniq->port, 0x40, "Ensoniq AudioPCI")) == NULL) {
1906                 snd_printk("unable to grab ports 0x%lx-0x%lx\n", ensoniq->port, ensoniq->port + 0x40 - 1);
1907                 snd_ensoniq_free(ensoniq);
1908                 return -EBUSY;
1909         }
1910         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1911                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1912                 snd_ensoniq_free(ensoniq);
1913                 return -EBUSY;
1914         }
1915         ensoniq->irq = pci->irq;
1916 #ifdef CHIP1370
1917         memset(&ensoniq->dma_dev, 0, sizeof(ensoniq->dma_dev));
1918         ensoniq->dma_dev.type = SNDRV_DMA_TYPE_DEV;
1919         ensoniq->dma_dev.dev = snd_dma_pci_data(pci);
1920         if (snd_dma_alloc_pages(&ensoniq->dma_dev, 16, &ensoniq->dma_bug) < 0) {
1921                 snd_printk("unable to allocate space for phantom area - dma_bug\n");
1922                 snd_ensoniq_free(ensoniq);
1923                 return -EBUSY;
1924         }
1925 #endif
1926         pci_set_master(pci);
1927         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1928         ensoniq->rev = cmdb;
1929         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1930         ensoniq->subsystem_vendor_id = cmdw;
1931         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1932         ensoniq->subsystem_device_id = cmdw;
1933         snd_ensoniq_proc_init(ensoniq);
1934 #ifdef CHIP1370
1935 #if 0
1936         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1937 #else   /* get microphone working */
1938         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1939 #endif
1940         ensoniq->sctrl = 0;
1941         /* initialize the chips */
1942         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1943         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1944         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1945         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1946         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1947 #else
1948         ensoniq->ctrl = 0;
1949         ensoniq->sctrl = 0;
1950         ensoniq->cssr = 0;
1951         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
1952                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
1953                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
1954                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
1955                         break;
1956                 }
1957         /* initialize the chips */
1958         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1959         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1960         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1961         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1962                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1963                     pci->device == es1371_ac97_reset_hack[idx].did &&
1964                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1965                         unsigned long tmo;
1966                         signed long tmo2;
1967
1968                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
1969                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1970                         /* need to delay around 20ms(bleech) to give
1971                         some CODECs enough time to wakeup */
1972                         tmo = jiffies + (HZ / 50) + 1;
1973                         while (1) {
1974                                 tmo2 = tmo - jiffies;
1975                                 if (tmo2 <= 0)
1976                                         break;
1977                                 set_current_state(TASK_UNINTERRUPTIBLE);
1978                                 schedule_timeout(tmo2);
1979                         }
1980                         break;
1981                 }
1982         /* AC'97 warm reset to start the bitclk */
1983         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1984         inl(ES_REG(ensoniq, CONTROL));
1985         udelay(20);
1986         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1987         /* Init the sample rate converter */
1988         snd_es1371_wait_src_ready(ensoniq);
1989         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1990         for (idx = 0; idx < 0x80; idx++)
1991                 snd_es1371_src_write(ensoniq, idx, 0);
1992         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1993         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1994         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1995         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1996         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1997         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1998         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1999         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2000         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2001         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2002         snd_es1371_adc_rate(ensoniq, 22050);
2003         snd_es1371_dac1_rate(ensoniq, 22050);
2004         snd_es1371_dac2_rate(ensoniq, 22050);
2005         /* WARNING:
2006          * enabling the sample rate converter without properly programming
2007          * its parameters causes the chip to lock up (the SRC busy bit will
2008          * be stuck high, and I've found no way to rectify this other than
2009          * power cycle) - Thomas Sailer
2010          */
2011         snd_es1371_wait_src_ready(ensoniq);
2012         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2013         /* try reset codec directly */
2014         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2015 #endif
2016         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2017         outb(0x00, ES_REG(ensoniq, UART_RES));
2018         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2019         synchronize_irq(ensoniq->irq);
2020
2021         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2022                 snd_ensoniq_free(ensoniq);
2023                 return err;
2024         }
2025
2026         snd_card_set_dev(card, &pci->dev);
2027
2028         *rensoniq = ensoniq;
2029         return 0;
2030 }
2031
2032 /*
2033  *  MIDI section
2034  */
2035
2036 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2037 {
2038         snd_rawmidi_t * rmidi = ensoniq->rmidi;
2039         unsigned char status, mask, byte;
2040
2041         if (rmidi == NULL)
2042                 return;
2043         /* do Rx at first */
2044         spin_lock(&ensoniq->reg_lock);
2045         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2046         while (mask) {
2047                 status = inb(ES_REG(ensoniq, UART_STATUS));
2048                 if ((status & mask) == 0)
2049                         break;
2050                 byte = inb(ES_REG(ensoniq, UART_DATA));
2051                 spin_unlock(&ensoniq->reg_lock);
2052                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2053                 spin_lock(&ensoniq->reg_lock);
2054         }
2055         spin_unlock(&ensoniq->reg_lock);
2056
2057         /* do Tx at second */
2058         spin_lock(&ensoniq->reg_lock);
2059         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2060         while (mask) {
2061                 status = inb(ES_REG(ensoniq, UART_STATUS));
2062                 if ((status & mask) == 0)
2063                         break;
2064                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2065                         ensoniq->uartc &= ~ES_TXINTENM;
2066                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2067                         mask &= ~ES_TXRDY;
2068                 } else {
2069                         outb(byte, ES_REG(ensoniq, UART_DATA));
2070                 }
2071         }
2072         spin_unlock(&ensoniq->reg_lock);
2073 }
2074
2075 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2076 {
2077         unsigned long flags;
2078         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2079
2080         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2081         ensoniq->uartm |= ES_MODE_INPUT;
2082         ensoniq->midi_input = substream;
2083         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2084                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2085                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2086                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2087         }
2088         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2089         return 0;
2090 }
2091
2092 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2093 {
2094         unsigned long flags;
2095         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2096
2097         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2098         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2099                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2100                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2101         } else {
2102                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2103         }
2104         ensoniq->midi_input = NULL;
2105         ensoniq->uartm &= ~ES_MODE_INPUT;
2106         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2107         return 0;
2108 }
2109
2110 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2111 {
2112         unsigned long flags;
2113         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2114
2115         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2116         ensoniq->uartm |= ES_MODE_OUTPUT;
2117         ensoniq->midi_output = substream;
2118         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2119                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2120                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2121                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2122         }
2123         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2124         return 0;
2125 }
2126
2127 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2128 {
2129         unsigned long flags;
2130         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2131
2132         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2133         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2134                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2135                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2136         } else {
2137                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2138         }
2139         ensoniq->midi_output = NULL;
2140         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2141         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2142         return 0;
2143 }
2144
2145 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2146 {
2147         unsigned long flags;
2148         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return);
2149         int idx;
2150
2151         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2152         if (up) {
2153                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2154                         /* empty input FIFO */
2155                         for (idx = 0; idx < 32; idx++)
2156                                 inb(ES_REG(ensoniq, UART_DATA));
2157                         ensoniq->uartc |= ES_RXINTEN;
2158                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2159                 }
2160         } else {
2161                 if (ensoniq->uartc & ES_RXINTEN) {
2162                         ensoniq->uartc &= ~ES_RXINTEN;
2163                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2164                 }
2165         }
2166         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2167 }
2168
2169 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2170 {
2171         unsigned long flags;
2172         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return);
2173         unsigned char byte;
2174
2175         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2176         if (up) {
2177                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2178                         ensoniq->uartc |= ES_TXINTENO(1);
2179                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2180                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2181                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2182                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2183                                         ensoniq->uartc &= ~ES_TXINTENM;
2184                                 } else {
2185                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2186                                 }
2187                         }
2188                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2189                 }
2190         } else {
2191                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2192                         ensoniq->uartc &= ~ES_TXINTENM;
2193                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2194                 }
2195         }
2196         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2197 }
2198
2199 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2200 {
2201         .open =         snd_ensoniq_midi_output_open,
2202         .close =        snd_ensoniq_midi_output_close,
2203         .trigger =      snd_ensoniq_midi_output_trigger,
2204 };
2205
2206 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2207 {
2208         .open =         snd_ensoniq_midi_input_open,
2209         .close =        snd_ensoniq_midi_input_close,
2210         .trigger =      snd_ensoniq_midi_input_trigger,
2211 };
2212
2213 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2214 {
2215         snd_rawmidi_t *rmidi;
2216         int err;
2217
2218         if (rrawmidi)
2219                 *rrawmidi = NULL;
2220         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2221                 return err;
2222 #ifdef CHIP1370
2223         strcpy(rmidi->name, "ES1370");
2224 #else
2225         strcpy(rmidi->name, "ES1371");
2226 #endif
2227         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2228         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2229         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2230         rmidi->private_data = ensoniq;
2231         ensoniq->rmidi = rmidi;
2232         if (rrawmidi)
2233                 *rrawmidi = rmidi;
2234         return 0;
2235 }
2236
2237 /*
2238  *  Interrupt handler
2239  */
2240
2241 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2242 {
2243         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, dev_id, return IRQ_NONE);
2244         unsigned int status, sctrl;
2245
2246         if (ensoniq == NULL)
2247                 return IRQ_NONE;
2248
2249         status = inl(ES_REG(ensoniq, STATUS));
2250         if (!(status & ES_INTR))
2251                 return IRQ_NONE;
2252
2253         spin_lock(&ensoniq->reg_lock);
2254         sctrl = ensoniq->sctrl;
2255         if (status & ES_DAC1)
2256                 sctrl &= ~ES_P1_INT_EN;
2257         if (status & ES_DAC2)
2258                 sctrl &= ~ES_P2_INT_EN;
2259         if (status & ES_ADC)
2260                 sctrl &= ~ES_R1_INT_EN;
2261         outl(sctrl, ES_REG(ensoniq, SERIAL));
2262         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2263         spin_unlock(&ensoniq->reg_lock);
2264
2265         if (status & ES_UART)
2266                 snd_ensoniq_midi_interrupt(ensoniq);
2267         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2268                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2269         if ((status & ES_ADC) && ensoniq->capture_substream)
2270                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2271         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2272                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2273         return IRQ_HANDLED;
2274 }
2275
2276 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2277                                         const struct pci_device_id *pci_id)
2278 {
2279         static int dev;
2280         snd_card_t *card;
2281         ensoniq_t *ensoniq;
2282         int err, pcm_devs[2];
2283
2284         if (dev >= SNDRV_CARDS)
2285                 return -ENODEV;
2286         if (!enable[dev]) {
2287                 dev++;
2288                 return -ENOENT;
2289         }
2290
2291         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2292         if (card == NULL)
2293                 return -ENOMEM;
2294
2295         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2296                 snd_card_free(card);
2297                 return err;
2298         }
2299
2300         pcm_devs[0] = 0; pcm_devs[1] = 1;
2301 #ifdef CHIP1370
2302         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2303                 snd_card_free(card);
2304                 return err;
2305         }
2306 #endif
2307 #ifdef CHIP1371
2308         if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2309                 snd_card_free(card);
2310                 return err;
2311         }
2312 #endif
2313         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2314                 snd_card_free(card);
2315                 return err;
2316         }
2317         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2318                 snd_card_free(card);
2319                 return err;
2320         }
2321         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2322                 snd_card_free(card);
2323                 return err;
2324         }
2325 #ifdef SUPPORT_JOYSTICK
2326 #ifdef CHIP1371
2327         switch (joystick_port[dev]) {
2328         case 1: /* auto-detect */
2329         case 0x200:
2330         case 0x208:
2331         case 0x210:
2332         case 0x218:
2333                 snd_ensoniq_joystick(ensoniq, joystick_port[dev]);
2334                 break;
2335         }
2336 #else
2337         if (joystick[dev])
2338                 snd_ensoniq_joystick(ensoniq, 0x200);
2339 #endif
2340 #endif /* SUPPORT_JOYSTICK */
2341         strcpy(card->driver, DRIVER_NAME);
2342
2343         strcpy(card->shortname, "Ensoniq AudioPCI");
2344         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2345                 card->shortname,
2346                 card->driver,
2347                 ensoniq->port,
2348                 ensoniq->irq);
2349
2350         if ((err = snd_card_register(card)) < 0) {
2351                 snd_card_free(card);
2352                 return err;
2353         }
2354
2355         pci_set_drvdata(pci, card);
2356         dev++;
2357         return 0;
2358 }
2359
2360 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2361 {
2362         snd_card_free(pci_get_drvdata(pci));
2363         pci_set_drvdata(pci, NULL);
2364 }
2365
2366 static struct pci_driver driver = {
2367         .name = DRIVER_NAME,
2368         .id_table = snd_audiopci_ids,
2369         .probe = snd_audiopci_probe,
2370         .remove = __devexit_p(snd_audiopci_remove),
2371 };
2372
2373 static int __init alsa_card_ens137x_init(void)
2374 {
2375         return pci_module_init(&driver);
2376 }
2377
2378 static void __exit alsa_card_ens137x_exit(void)
2379 {
2380         pci_unregister_driver(&driver);
2381 }
2382
2383 module_init(alsa_card_ens137x_init)
2384 module_exit(alsa_card_ens137x_exit)