sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <linux/moduleparam.h>
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/rawmidi.h>
  35 #ifdef CHIP1371
  36 #include <sound/ac97_codec.h>
  37 #else
  38 #include <sound/ak4531_codec.h>
  39 #endif
  40 #include <sound/initval.h>
  41 #include <sound/asoundef.h>
  42
  43 #ifndef CHIP1371
  44 #undef CHIP1370
  45 #define CHIP1370
  46 #endif
  47
  48 #ifdef CHIP1370
  49 #define DRIVER_NAME "ENS1370"
  50 #else
  51 #define DRIVER_NAME "ENS1371"
  52 #endif
  53
  54
  55 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  56 MODULE_LICENSE("GPL");
  57 #ifdef CHIP1370
  58 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  59 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  60                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  61 #endif
  62 #ifdef CHIP1371
  63 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  64 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  65                 "{Ensoniq,AudioPCI ES1373},"
  66                 "{Creative Labs,Ectiva EV1938},"
  67                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  68                 "{Creative Labs,Vibra PCI128},"
  69                 "{Ectiva,EV1938}}");
  70 #endif
  71
  72 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  73 #define SUPPORT_JOYSTICK
  74 #endif
  75
  76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  79 #ifdef SUPPORT_JOYSTICK
  80 #ifdef CHIP1371
  81 static int joystick_port[SNDRV_CARDS];
  82 #else
  83 static int joystick[SNDRV_CARDS];
  84 #endif
  85 #endif
  86 static int boot_devs;
  87
  88 module_param_array(index, int, boot_devs, 0444);
  89 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  90 module_param_array(id, charp, boot_devs, 0444);
  91 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  92 module_param_array(enable, bool, boot_devs, 0444);
  93 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  94 #ifdef SUPPORT_JOYSTICK
  95 #ifdef CHIP1371
  96 module_param_array(joystick_port, int, boot_devs, 0444);
  97 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  98 #else
  99 module_param_array(joystick, bool, boot_devs, 0444);
 100 MODULE_PARM_DESC(joystick, "Enable joystick.");
 101 #endif
 102 #endif /* SUPPORT_JOYSTICK */
 103
 104 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
 105 #define PCI_DEVICE_ID_ENSONIQ_CT5880    0x5880
 106 #endif
 107 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
 108 #define PCI_DEVICE_ID_ENSONIQ_ES1371    0x1371
 109 #endif
 110
 111 /* ES1371 chip ID */
 112 /* This is a little confusing because all ES1371 compatible chips have the
 113    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 114    This is only significant if you want to enable features on the later parts.
 115    Yes, I know it's stupid and why didn't we use the sub IDs?
 116 */
 117 #define ES1371REV_ES1373_A  0x04
 118 #define ES1371REV_ES1373_B  0x06
 119 #define ES1371REV_CT5880_A  0x07
 120 #define CT5880REV_CT5880_C  0x02
 121 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 122 #define CT5880REV_CT5880_E  0x04        /* mw */
 123 #define ES1371REV_ES1371_B  0x09
 124 #define EV1938REV_EV1938_A  0x00
 125 #define ES1371REV_ES1373_8  0x08
 126
 127 /*
 128  * Direct registers
 129  */
 130
 131 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 132
 133 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 134 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 135 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 136 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 137 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 138 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 139 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 140 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 141 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 142 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 143 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 144 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 145 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 146 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 147 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 148 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 149 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 150 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 151 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 152 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 153 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 154 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 155 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 156 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 157 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 158 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 159 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 160 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 161 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 162 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 163 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 164 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 165 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 166 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 167 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 168 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 169 #define   ES_UART_EN            (1<<3)          /* UART enable */
 170 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 171 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 172 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 173 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 174 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 175 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 176 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 177 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 178 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 179 #define   ES_1373_REAR_BIT26    (1<<26)
 180 #define   ES_1373_REAR_BIT24    (1<<24)
 181 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 182 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 183 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 184 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 185 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 186 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 187 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 188 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 189 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 190 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 191 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 192 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 193 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 194 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 195 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 196 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 197 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 198 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 199 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 200 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 201 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 202 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 203 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 204 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 205 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 206 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 207 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 208 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 209 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 210 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 211 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 212 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 213 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 214 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 215 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 216 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 217 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 218 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 219 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 220 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 221 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 222 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 223 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 224 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 225 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 226
 227 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 228 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 229 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 230 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 231 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 232 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 233 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 234 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 235 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 236 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 237 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 238 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 239 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 240
 241 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 242 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 243 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 244 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 245 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 246 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 247 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 248 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 249 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 250 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 251 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 252 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 253 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 254 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 255 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 256 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 257 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 258 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 259 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 260 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 261 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 262 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 263 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 264
 265 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 266
 267 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 268 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 269 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 270 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 271 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 272 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 273 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 274 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 275 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 276 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 277 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 278 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 279 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 280 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 281 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 282 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 283 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 284 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 285 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 286 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 287 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 288 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 289 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 290 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 291 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 292 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 293 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 294
 295 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 296 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 297 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 298 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 299 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 300 #define   ES_REG_COUNTM         (0xffff<<0)
 301 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 302
 303 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 304 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 305 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 306 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 307 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 308 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 309 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 310 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 311 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 312 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 313 #define   ES_REG_FSIZEM          (0xffff<<0)
 314 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 315 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 316 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 317
 318 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 319 #define   ES_REG_UF_VALID        (1<<8)
 320 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 321 #define   ES_REG_UF_BYTEM        (0xff<<0)
 322 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 323
 324
 325 /*
 326  *  Pages
 327  */
 328
 329 #define ES_PAGE_DAC     0x0c
 330 #define ES_PAGE_ADC     0x0d
 331 #define ES_PAGE_UART    0x0e
 332 #define ES_PAGE_UART1   0x0f
 333
 334 /*
 335  *  Sample rate converter addresses
 336  */
 337
 338 #define ES_SMPREG_DAC1          0x70
 339 #define ES_SMPREG_DAC2          0x74
 340 #define ES_SMPREG_ADC           0x78
 341 #define ES_SMPREG_VOL_ADC       0x6c
 342 #define ES_SMPREG_VOL_DAC1      0x7c
 343 #define ES_SMPREG_VOL_DAC2      0x7e
 344 #define ES_SMPREG_TRUNC_N       0x00
 345 #define ES_SMPREG_INT_REGS      0x01
 346 #define ES_SMPREG_ACCUM_FRAC    0x02
 347 #define ES_SMPREG_VFREQ_FRAC    0x03
 348
 349 /*
 350  *  Some contants
 351  */
 352
 353 #define ES_1370_SRCLOCK    1411200
 354 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 355
 356 /*
 357  *  Open modes
 358  */
 359
 360 #define ES_MODE_PLAY1   0x0001
 361 #define ES_MODE_PLAY2   0x0002
 362 #define ES_MODE_CAPTURE 0x0004
 363
 364 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 365 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 366
 367 /*
 368
 369  */
 370
 371 typedef struct _snd_ensoniq ensoniq_t;
 372
 373 struct _snd_ensoniq {
 374         spinlock_t reg_lock;
 375
 376         int irq;
 377
 378         unsigned long playback1size;
 379         unsigned long playback2size;
 380         unsigned long capture3size;
 381
 382         unsigned long port;
 383         unsigned int mode;
 384         unsigned int uartm;     /* UART mode */
 385
 386         unsigned int ctrl;      /* control register */
 387         unsigned int sctrl;     /* serial control register */
 388         unsigned int cssr;      /* control status register */
 389         unsigned int uartc;     /* uart control register */
 390         unsigned int rev;       /* chip revision */
 391
 392         union {
 393 #ifdef CHIP1371
 394                 struct {
 395                         ac97_t *ac97;
 396                 } es1371;
 397 #else
 398                 struct {
 399                         int pclkdiv_lock;
 400                         ak4531_t *ak4531;
 401                 } es1370;
 402 #endif
 403         } u;
 404
 405         struct pci_dev *pci;
 406         unsigned short subsystem_vendor_id;
 407         unsigned short subsystem_device_id;
 408         snd_card_t *card;
 409         snd_pcm_t *pcm1;        /* DAC1/ADC PCM */
 410         snd_pcm_t *pcm2;        /* DAC2 PCM */
 411         snd_pcm_substream_t *playback1_substream;
 412         snd_pcm_substream_t *playback2_substream;
 413         snd_pcm_substream_t *capture_substream;
 414         unsigned int p1_dma_size;
 415         unsigned int p2_dma_size;
 416         unsigned int c_dma_size;
 417         unsigned int p1_period_size;
 418         unsigned int p2_period_size;
 419         unsigned int c_period_size;
 420         snd_rawmidi_t *rmidi;
 421         snd_rawmidi_substream_t *midi_input;
 422         snd_rawmidi_substream_t *midi_output;
 423
 424         unsigned int spdif;
 425         unsigned int spdif_default;
 426         unsigned int spdif_stream;
 427
 428 #ifdef CHIP1370
 429         struct snd_dma_buffer dma_bug;
 430 #endif
 431
 432 #ifdef SUPPORT_JOYSTICK
 433         struct gameport gameport;
 434 #endif
 435 };
 436
 437 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 438
 439 static struct pci_device_id snd_audiopci_ids[] = {
 440 #ifdef CHIP1370
 441         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 442 #endif
 443 #ifdef CHIP1371
 444         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 445         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 446         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 447 #endif
 448         { 0, }
 449 };
 450
 451 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 452
 453 /*
 454  *  constants
 455  */
 456
 457 #define POLL_COUNT      0xa000
 458
 459 #ifdef CHIP1370
 460 static unsigned int snd_es1370_fixed_rates[] =
 461         {5512, 11025, 22050, 44100};
 462 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
 463         .count = 4,
 464         .list = snd_es1370_fixed_rates,
 465         .mask = 0,
 466 };
 467 static ratnum_t es1370_clock = {
 468         .num = ES_1370_SRCLOCK,
 469         .den_min = 29,
 470         .den_max = 353,
 471         .den_step = 1,
 472 };
 473 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
 474         .nrats = 1,
 475         .rats = &es1370_clock,
 476 };
 477 #else
 478 static ratden_t es1371_dac_clock = {
 479         .num_min = 3000 * (1 << 15),
 480         .num_max = 48000 * (1 << 15),
 481         .num_step = 3000,
 482         .den = 1 << 15,
 483 };
 484 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
 485         .nrats = 1,
 486         .rats = &es1371_dac_clock,
 487 };
 488 static ratnum_t es1371_adc_clock = {
 489         .num = 48000 << 15,
 490         .den_min = 32768,
 491         .den_max = 393216,
 492         .den_step = 1,
 493 };
 494 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
 495         .nrats = 1,
 496         .rats = &es1371_adc_clock,
 497 };
 498 #endif
 499 static const unsigned int snd_ensoniq_sample_shift[] =
 500         {0, 1, 1, 2};
 501
 502 /*
 503  *  common I/O routines
 504  */
 505
 506 #ifdef CHIP1371
 507
 508 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
 509 {
 510         unsigned int t, r = 0;
 511
 512         for (t = 0; t < POLL_COUNT; t++) {
 513                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 514                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 515                         return r;
 516         }
 517         snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
 518         return 0;
 519 }
 520
 521 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
 522 {
 523         unsigned int temp, i, orig, r;
 524
 525         /* wait for ready */
 526         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 527
 528         /* expose the SRC state bits */
 529         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 530                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 531         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 532         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 533
 534         /* now, wait for busy and the correct time to read */
 535         temp = snd_es1371_wait_src_ready(ensoniq);
 536
 537         if ((temp & 0x00870000) != 0x00010000) {
 538                 /* wait for the right state */
 539                 for (i = 0; i < POLL_COUNT; i++) {
 540                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 541                         if ((temp & 0x00870000) == 0x00010000)
 542                                 break;
 543                 }
 544         }
 545
 546         /* hide the state bits */
 547         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 548                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 549         r |= ES_1371_SRC_RAM_ADDRO(reg);
 550         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 551
 552         return temp;
 553 }
 554
 555 static void snd_es1371_src_write(ensoniq_t * ensoniq,
 556                                  unsigned short reg, unsigned short data)
 557 {
 558         unsigned int r;
 559
 560         r = snd_es1371_wait_src_ready(ensoniq) &
 561             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 562              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 563         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 564         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 565 }
 566
 567 #endif /* CHIP1371 */
 568
 569 #ifdef CHIP1370
 570
 571 static void snd_es1370_codec_write(ak4531_t *ak4531,
 572                                    unsigned short reg, unsigned short val)
 573 {
 574         ensoniq_t *ensoniq = ak4531->private_data;
 575         unsigned long flags;
 576         unsigned long end_time = jiffies + HZ / 10;
 577
 578 #if 0
 579         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 580 #endif
 581         do {
 582                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 583                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 584                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 585                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 586                         return;
 587                 }
 588                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 589 #if 0
 590                 set_current_state(TASK_UNINTERRUPTIBLE);
 591                 schedule_timeout(1);
 592 #endif
 593         } while (time_after(end_time, jiffies));
 594         snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
 595 }
 596
 597 #endif /* CHIP1370 */
 598
 599 #ifdef CHIP1371
 600
 601 static void snd_es1371_codec_write(ac97_t *ac97,
 602                                    unsigned short reg, unsigned short val)
 603 {
 604         ensoniq_t *ensoniq = ac97->private_data;
 605         unsigned long flags;
 606         unsigned int t, x;
 607
 608         for (t = 0; t < POLL_COUNT; t++) {
 609                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 610                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 611                         /* save the current state for latter */
 612                         x = snd_es1371_wait_src_ready(ensoniq);
 613                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 614                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 615                              ES_REG(ensoniq, 1371_SMPRATE));
 616                         /* wait for not busy (state 0) first to avoid
 617                            transition states */
 618                         for (t = 0; t < POLL_COUNT; t++) {
 619                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 620                                         break;
 621                         }
 622                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 623                         for (t = 0; t < POLL_COUNT; t++) {
 624                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 625                                         break;
 626                         }
 627                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 628                         /* restore SRC reg */
 629                         snd_es1371_wait_src_ready(ensoniq);
 630                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 631                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 632                         return;
 633                 }
 634                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 635         }
 636         snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 637 }
 638
 639 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 640                                             unsigned short reg)
 641 {
 642         ensoniq_t *ensoniq = ac97->private_data;
 643         unsigned long flags;
 644         unsigned int t, x, fail = 0;
 645
 646       __again:
 647         for (t = 0; t < POLL_COUNT; t++) {
 648                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 649                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 650                         /* save the current state for latter */
 651                         x = snd_es1371_wait_src_ready(ensoniq);
 652                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 653                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 654                              ES_REG(ensoniq, 1371_SMPRATE));
 655                         /* wait for not busy (state 0) first to avoid
 656                            transition states */
 657                         for (t = 0; t < POLL_COUNT; t++) {
 658                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 659                                         break;
 660                         }
 661                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 662                         for (t = 0; t < POLL_COUNT; t++) {
 663                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 664                                         break;
 665                         }
 666                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 667                         /* restore SRC reg */
 668                         snd_es1371_wait_src_ready(ensoniq);
 669                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 670                         /* wait for WIP again */
 671                         for (t = 0; t < POLL_COUNT; t++) {
 672                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 673                                         break;
 674                         }
 675                         /* now wait for the stinkin' data (RDY) */
 676                         for (t = 0; t < POLL_COUNT; t++) {
 677                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 678                                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 679                                         return ES_1371_CODEC_READ(x);
 680                                 }
 681                         }
 682                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 683                         if (++fail > 10) {
 684                                 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
 685                                 return 0;
 686                         }
 687                         goto __again;
 688                 }
 689                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 690         }
 691         snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 692         return 0;
 693 }
 694
 695 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 696 {
 697         unsigned int n, truncm, freq, result;
 698
 699         n = rate / 3000;
 700         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 701                 n--;
 702         truncm = (21 * n - 1) | 1;
 703         freq = ((48000UL << 15) / rate) * n;
 704         result = (48000UL << 15) / (freq / n);
 705         if (rate >= 24000) {
 706                 if (truncm > 239)
 707                         truncm = 239;
 708                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 709                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 710         } else {
 711                 if (truncm > 119)
 712                         truncm = 119;
 713                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 714                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 715         }
 716         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 717                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
 718                                      ((freq >> 5) & 0xfc00));
 719         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 720         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 721         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 722 }
 723
 724 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
 725 {
 726         unsigned int freq, r;
 727
 728         freq = ((rate << 15) + 1500) / 3000;
 729         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
 730         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 731         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 732                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
 733                              ((freq >> 5) & 0xfc00));
 734         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 735         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
 736         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 737 }
 738
 739 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
 740 {
 741         unsigned int freq, r;
 742
 743         freq = ((rate << 15) + 1500) / 3000;
 744         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
 745         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 746         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 747                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
 748                              ((freq >> 5) & 0xfc00));
 749         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 750         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
 751         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 752 }
 753
 754 #endif /* CHIP1371 */
 755
 756 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
 757 {
 758         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 759         switch (cmd) {
 760         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 761         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 762         {
 763                 unsigned int what = 0;
 764                 struct list_head *pos;
 765                 snd_pcm_substream_t *s;
 766                 snd_pcm_group_for_each(pos, substream) {
 767                         s = snd_pcm_group_substream_entry(pos);
 768                         if (s == ensoniq->playback1_substream) {
 769                                 what |= ES_P1_PAUSE;
 770                                 snd_pcm_trigger_done(s, substream);
 771                         } else if (s == ensoniq->playback2_substream) {
 772                                 what |= ES_P2_PAUSE;
 773                                 snd_pcm_trigger_done(s, substream);
 774                         } else if (s == ensoniq->capture_substream)
 775                                 return -EINVAL;
 776                 }
 777                 spin_lock(&ensoniq->reg_lock);
 778                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 779                         ensoniq->sctrl |= what;
 780                 else
 781                         ensoniq->sctrl &= ~what;
 782                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 783                 spin_unlock(&ensoniq->reg_lock);
 784                 break;
 785         }
 786         case SNDRV_PCM_TRIGGER_START:
 787         case SNDRV_PCM_TRIGGER_STOP:
 788         {
 789                 unsigned int what = 0;
 790                 struct list_head *pos;
 791                 snd_pcm_substream_t *s;
 792                 snd_pcm_group_for_each(pos, substream) {
 793                         s = snd_pcm_group_substream_entry(pos);
 794                         if (s == ensoniq->playback1_substream) {
 795                                 what |= ES_DAC1_EN;
 796                                 snd_pcm_trigger_done(s, substream);
 797                         } else if (s == ensoniq->playback2_substream) {
 798                                 what |= ES_DAC2_EN;
 799                                 snd_pcm_trigger_done(s, substream);
 800                         } else if (s == ensoniq->capture_substream) {
 801                                 what |= ES_ADC_EN;
 802                                 snd_pcm_trigger_done(s, substream);
 803                         }
 804                 }
 805                 spin_lock(&ensoniq->reg_lock);
 806                 if (cmd == SNDRV_PCM_TRIGGER_START)
 807                         ensoniq->ctrl |= what;
 808                 else
 809                         ensoniq->ctrl &= ~what;
 810                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 811                 spin_unlock(&ensoniq->reg_lock);
 812                 break;
 813         }
 814         default:
 815                 return -EINVAL;
 816         }
 817         return 0;
 818 }
 819
 820 /*
 821  *  PCM part
 822  */
 823
 824 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
 825                                  snd_pcm_hw_params_t * hw_params)
 826 {
 827         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 828 }
 829
 830 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
 831 {
 832         return snd_pcm_lib_free_pages(substream);
 833 }
 834
 835 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
 836 {
 837         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 838         snd_pcm_runtime_t *runtime = substream->runtime;
 839         unsigned int mode = 0;
 840
 841         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 842         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 843         if (snd_pcm_format_width(runtime->format) == 16)
 844                 mode |= 0x02;
 845         if (runtime->channels > 1)
 846                 mode |= 0x01;
 847         spin_lock_irq(&ensoniq->reg_lock);
 848         ensoniq->ctrl &= ~ES_DAC1_EN;
 849         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 850         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 851         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 852         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 853         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 854         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 855         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 856         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
 857 #ifdef CHIP1370
 858         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 859         switch (runtime->rate) {
 860         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 861         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 862         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 863         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 864         default: snd_BUG();
 865         }
 866 #else
 867         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 868 #endif
 869         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 870         spin_unlock_irq(&ensoniq->reg_lock);
 871         return 0;
 872 }
 873
 874 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
 875 {
 876         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 877         snd_pcm_runtime_t *runtime = substream->runtime;
 878         unsigned int mode = 0;
 879
 880         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 881         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 882         if (snd_pcm_format_width(runtime->format) == 16)
 883                 mode |= 0x02;
 884         if (runtime->channels > 1)
 885                 mode |= 0x01;
 886         spin_lock_irq(&ensoniq->reg_lock);
 887         ensoniq->ctrl &= ~ES_DAC2_EN;
 888         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 889         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 890         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 891         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 892         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 893                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 894         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 895                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 896         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 897         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
 898 #ifdef CHIP1370
 899         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 900                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 901                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 902                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 903         }
 904 #else
 905         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 906 #endif
 907         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 908         spin_unlock_irq(&ensoniq->reg_lock);
 909         return 0;
 910 }
 911
 912 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
 913 {
 914         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 915         snd_pcm_runtime_t *runtime = substream->runtime;
 916         unsigned int mode = 0;
 917
 918         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 919         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 920         if (snd_pcm_format_width(runtime->format) == 16)
 921                 mode |= 0x02;
 922         if (runtime->channels > 1)
 923                 mode |= 0x01;
 924         spin_lock_irq(&ensoniq->reg_lock);
 925         ensoniq->ctrl &= ~ES_ADC_EN;
 926         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 927         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 928         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 929         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 930         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 931         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 932         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 933         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
 934 #ifdef CHIP1370
 935         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 936                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 937                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 938                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 939         }
 940 #else
 941         snd_es1371_adc_rate(ensoniq, runtime->rate);
 942 #endif
 943         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 944         spin_unlock_irq(&ensoniq->reg_lock);
 945         return 0;
 946 }
 947
 948 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
 949 {
 950         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 951         size_t ptr;
 952
 953         spin_lock(&ensoniq->reg_lock);
 954         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 955                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 956                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 957                 ptr = bytes_to_frames(substream->runtime, ptr);
 958         } else {
 959                 ptr = 0;
 960         }
 961         spin_unlock(&ensoniq->reg_lock);
 962         return ptr;
 963 }
 964
 965 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
 966 {
 967         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 968         size_t ptr;
 969
 970         spin_lock(&ensoniq->reg_lock);
 971         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
 972                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 973                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
 974                 ptr = bytes_to_frames(substream->runtime, ptr);
 975         } else {
 976                 ptr = 0;
 977         }
 978         spin_unlock(&ensoniq->reg_lock);
 979         return ptr;
 980 }
 981
 982 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
 983 {
 984         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 985         size_t ptr;
 986
 987         spin_lock(&ensoniq->reg_lock);
 988         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
 989                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 990                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
 991                 ptr = bytes_to_frames(substream->runtime, ptr);
 992         } else {
 993                 ptr = 0;
 994         }
 995         spin_unlock(&ensoniq->reg_lock);
 996         return ptr;
 997 }
 998
 999 static snd_pcm_hardware_t snd_ensoniq_playback1 =
1000 {
1001         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1002                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1003                                  SNDRV_PCM_INFO_MMAP_VALID |
1004                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1005         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1006         .rates =
1007 #ifndef CHIP1370
1008                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1009 #else
1010                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1011                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1012                                  SNDRV_PCM_RATE_44100),
1013 #endif
1014         .rate_min =             4000,
1015         .rate_max =             48000,
1016         .channels_min =         1,
1017         .channels_max =         2,
1018         .buffer_bytes_max =     (128*1024),
1019         .period_bytes_min =     64,
1020         .period_bytes_max =     (128*1024),
1021         .periods_min =          1,
1022         .periods_max =          1024,
1023         .fifo_size =            0,
1024 };
1025
1026 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1027 {
1028         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1029                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1030                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1031                                  SNDRV_PCM_INFO_SYNC_START),
1032         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1033         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1034         .rate_min =             4000,
1035         .rate_max =             48000,
1036         .channels_min =         1,
1037         .channels_max =         2,
1038         .buffer_bytes_max =     (128*1024),
1039         .period_bytes_min =     64,
1040         .period_bytes_max =     (128*1024),
1041         .periods_min =          1,
1042         .periods_max =          1024,
1043         .fifo_size =            0,
1044 };
1045
1046 static snd_pcm_hardware_t snd_ensoniq_capture =
1047 {
1048         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1049                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1050                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1051         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1052         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1053         .rate_min =             4000,
1054         .rate_max =             48000,
1055         .channels_min =         1,
1056         .channels_max =         2,
1057         .buffer_bytes_max =     (128*1024),
1058         .period_bytes_min =     64,
1059         .period_bytes_max =     (128*1024),
1060         .periods_min =          1,
1061         .periods_max =          1024,
1062         .fifo_size =            0,
1063 };
1064
1065 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1066 {
1067         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1068         snd_pcm_runtime_t *runtime = substream->runtime;
1069
1070         ensoniq->mode |= ES_MODE_PLAY1;
1071         ensoniq->playback1_substream = substream;
1072         runtime->hw = snd_ensoniq_playback1;
1073         snd_pcm_set_sync(substream);
1074         spin_lock_irq(&ensoniq->reg_lock);
1075         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1076                 ensoniq->spdif_stream = ensoniq->spdif_default;
1077         spin_unlock_irq(&ensoniq->reg_lock);
1078 #ifdef CHIP1370
1079         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1080                                    &snd_es1370_hw_constraints_rates);
1081 #else
1082         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1083                                       &snd_es1371_hw_constraints_dac_clock);
1084 #endif
1085         return 0;
1086 }
1087
1088 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1089 {
1090         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1091         snd_pcm_runtime_t *runtime = substream->runtime;
1092
1093         ensoniq->mode |= ES_MODE_PLAY2;
1094         ensoniq->playback2_substream = substream;
1095         runtime->hw = snd_ensoniq_playback2;
1096         snd_pcm_set_sync(substream);
1097         spin_lock_irq(&ensoniq->reg_lock);
1098         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1099                 ensoniq->spdif_stream = ensoniq->spdif_default;
1100         spin_unlock_irq(&ensoniq->reg_lock);
1101 #ifdef CHIP1370
1102         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1103                                       &snd_es1370_hw_constraints_clock);
1104 #else
1105         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1106                                       &snd_es1371_hw_constraints_dac_clock);
1107 #endif
1108         return 0;
1109 }
1110
1111 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1112 {
1113         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1114         snd_pcm_runtime_t *runtime = substream->runtime;
1115
1116         ensoniq->mode |= ES_MODE_CAPTURE;
1117         ensoniq->capture_substream = substream;
1118         runtime->hw = snd_ensoniq_capture;
1119         snd_pcm_set_sync(substream);
1120 #ifdef CHIP1370
1121         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1122                                       &snd_es1370_hw_constraints_clock);
1123 #else
1124         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1125                                       &snd_es1371_hw_constraints_adc_clock);
1126 #endif
1127         return 0;
1128 }
1129
1130 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1131 {
1132         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1133
1134         ensoniq->playback1_substream = NULL;
1135         ensoniq->mode &= ~ES_MODE_PLAY1;
1136         return 0;
1137 }
1138
1139 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1140 {
1141         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1142
1143         ensoniq->playback2_substream = NULL;
1144         spin_lock_irq(&ensoniq->reg_lock);
1145 #ifdef CHIP1370
1146         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1147 #endif
1148         ensoniq->mode &= ~ES_MODE_PLAY2;
1149         spin_unlock_irq(&ensoniq->reg_lock);
1150         return 0;
1151 }
1152
1153 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1154 {
1155         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1156
1157         ensoniq->capture_substream = NULL;
1158         spin_lock_irq(&ensoniq->reg_lock);
1159 #ifdef CHIP1370
1160         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1161 #endif
1162         ensoniq->mode &= ~ES_MODE_CAPTURE;
1163         spin_unlock_irq(&ensoniq->reg_lock);
1164         return 0;
1165 }
1166
1167 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1168         .open =         snd_ensoniq_playback1_open,
1169         .close =        snd_ensoniq_playback1_close,
1170         .ioctl =        snd_pcm_lib_ioctl,
1171         .hw_params =    snd_ensoniq_hw_params,
1172         .hw_free =      snd_ensoniq_hw_free,
1173         .prepare =      snd_ensoniq_playback1_prepare,
1174         .trigger =      snd_ensoniq_trigger,
1175         .pointer =      snd_ensoniq_playback1_pointer,
1176 };
1177
1178 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1179         .open =         snd_ensoniq_playback2_open,
1180         .close =        snd_ensoniq_playback2_close,
1181         .ioctl =        snd_pcm_lib_ioctl,
1182         .hw_params =    snd_ensoniq_hw_params,
1183         .hw_free =      snd_ensoniq_hw_free,
1184         .prepare =      snd_ensoniq_playback2_prepare,
1185         .trigger =      snd_ensoniq_trigger,
1186         .pointer =      snd_ensoniq_playback2_pointer,
1187 };
1188
1189 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1190         .open =         snd_ensoniq_capture_open,
1191         .close =        snd_ensoniq_capture_close,
1192         .ioctl =        snd_pcm_lib_ioctl,
1193         .hw_params =    snd_ensoniq_hw_params,
1194         .hw_free =      snd_ensoniq_hw_free,
1195         .prepare =      snd_ensoniq_capture_prepare,
1196         .trigger =      snd_ensoniq_trigger,
1197         .pointer =      snd_ensoniq_capture_pointer,
1198 };
1199
1200 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1201 {
1202         ensoniq_t *ensoniq = pcm->private_data;
1203         ensoniq->pcm1 = NULL;
1204         snd_pcm_lib_preallocate_free_for_all(pcm);
1205 }
1206
1207 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1208 {
1209         snd_pcm_t *pcm;
1210         int err;
1211
1212         if (rpcm)
1213                 *rpcm = NULL;
1214 #ifdef CHIP1370
1215         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1216 #else
1217         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1218 #endif
1219         if (err < 0)
1220                 return err;
1221
1222 #ifdef CHIP1370
1223         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1224 #else
1225         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1226 #endif
1227         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1228
1229         pcm->private_data = ensoniq;
1230         pcm->private_free = snd_ensoniq_pcm_free;
1231         pcm->info_flags = 0;
1232 #ifdef CHIP1370
1233         strcpy(pcm->name, "ES1370 DAC2/ADC");
1234 #else
1235         strcpy(pcm->name, "ES1371 DAC2/ADC");
1236 #endif
1237         ensoniq->pcm1 = pcm;
1238
1239         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1240                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1241
1242         if (rpcm)
1243                 *rpcm = pcm;
1244         return 0;
1245 }
1246
1247 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1248 {
1249         ensoniq_t *ensoniq = pcm->private_data;
1250         ensoniq->pcm2 = NULL;
1251         snd_pcm_lib_preallocate_free_for_all(pcm);
1252 }
1253
1254 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1255 {
1256         snd_pcm_t *pcm;
1257         int err;
1258
1259         if (rpcm)
1260                 *rpcm = NULL;
1261 #ifdef CHIP1370
1262         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1263 #else
1264         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1265 #endif
1266         if (err < 0)
1267                 return err;
1268
1269 #ifdef CHIP1370
1270         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1271 #else
1272         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1273 #endif
1274         pcm->private_data = ensoniq;
1275         pcm->private_free = snd_ensoniq_pcm_free2;
1276         pcm->info_flags = 0;
1277 #ifdef CHIP1370
1278         strcpy(pcm->name, "ES1370 DAC1");
1279 #else
1280         strcpy(pcm->name, "ES1371 DAC1");
1281 #endif
1282         ensoniq->pcm2 = pcm;
1283
1284         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1285                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1286
1287         if (rpcm)
1288                 *rpcm = pcm;
1289         return 0;
1290 }
1291
1292 /*
1293  *  Mixer section
1294  */
1295
1296 /*
1297  * ENS1371 mixer (including SPDIF interface)
1298  */
1299 #ifdef CHIP1371
1300 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1301 {
1302         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1303         uinfo->count = 1;
1304         return 0;
1305 }
1306
1307 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1308                                          snd_ctl_elem_value_t * ucontrol)
1309 {
1310         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1311         spin_lock_irq(&ensoniq->reg_lock);
1312         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1313         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1314         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1315         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1316         spin_unlock_irq(&ensoniq->reg_lock);
1317         return 0;
1318 }
1319
1320 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1321                                          snd_ctl_elem_value_t * ucontrol)
1322 {
1323         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1324         unsigned int val;
1325         int change;
1326
1327         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1328               ((u32)ucontrol->value.iec958.status[1] << 8) |
1329               ((u32)ucontrol->value.iec958.status[2] << 16) |
1330               ((u32)ucontrol->value.iec958.status[3] << 24);
1331         spin_lock_irq(&ensoniq->reg_lock);
1332         change = ensoniq->spdif_default != val;
1333         ensoniq->spdif_default = val;
1334         if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1335                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1336         spin_unlock_irq(&ensoniq->reg_lock);
1337         return change;
1338 }
1339
1340 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1341                                          snd_ctl_elem_value_t * ucontrol)
1342 {
1343         ucontrol->value.iec958.status[0] = 0xff;
1344         ucontrol->value.iec958.status[1] = 0xff;
1345         ucontrol->value.iec958.status[2] = 0xff;
1346         ucontrol->value.iec958.status[3] = 0xff;
1347         return 0;
1348 }
1349
1350 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1351                                          snd_ctl_elem_value_t * ucontrol)
1352 {
1353         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1354         spin_lock_irq(&ensoniq->reg_lock);
1355         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1356         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1357         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1358         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1359         spin_unlock_irq(&ensoniq->reg_lock);
1360         return 0;
1361 }
1362
1363 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1364                                         snd_ctl_elem_value_t * ucontrol)
1365 {
1366         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1367         unsigned int val;
1368         int change;
1369
1370         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1371               ((u32)ucontrol->value.iec958.status[1] << 8) |
1372               ((u32)ucontrol->value.iec958.status[2] << 16) |
1373               ((u32)ucontrol->value.iec958.status[3] << 24);
1374         spin_lock_irq(&ensoniq->reg_lock);
1375         change = ensoniq->spdif_stream != val;
1376         ensoniq->spdif_stream = val;
1377         if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1378                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1379         spin_unlock_irq(&ensoniq->reg_lock);
1380         return change;
1381 }
1382
1383 #define ES1371_SPDIF(xname) \
1384 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1385   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1386
1387 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1388 {
1389         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1390         uinfo->count = 1;
1391         uinfo->value.integer.min = 0;
1392         uinfo->value.integer.max = 1;
1393         return 0;
1394 }
1395
1396 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1397 {
1398         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1399
1400         spin_lock_irq(&ensoniq->reg_lock);
1401         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1402         spin_unlock_irq(&ensoniq->reg_lock);
1403         return 0;
1404 }
1405
1406 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1407 {
1408         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1409         unsigned int nval1, nval2;
1410         int change;
1411
1412         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1413         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1414         spin_lock_irq(&ensoniq->reg_lock);
1415         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1416         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1417         ensoniq->ctrl |= nval1;
1418         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1419         ensoniq->cssr |= nval2;
1420         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1421         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1422         spin_unlock_irq(&ensoniq->reg_lock);
1423         return change;
1424 }
1425
1426
1427 /* spdif controls */
1428 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1429         ES1371_SPDIF("IEC958 Playback Switch"),
1430         {
1431                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1432                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1433                 .info =         snd_ens1373_spdif_info,
1434                 .get =          snd_ens1373_spdif_default_get,
1435                 .put =          snd_ens1373_spdif_default_put,
1436         },
1437         {
1438                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1439                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1440                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1441                 .info =         snd_ens1373_spdif_info,
1442                 .get =          snd_ens1373_spdif_mask_get
1443         },
1444         {
1445                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1446                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1447                 .info =         snd_ens1373_spdif_info,
1448                 .get =          snd_ens1373_spdif_stream_get,
1449                 .put =          snd_ens1373_spdif_stream_put
1450         },
1451 };
1452
1453
1454 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1455 {
1456         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1457         uinfo->count = 1;
1458         uinfo->value.integer.min = 0;
1459         uinfo->value.integer.max = 1;
1460         return 0;
1461 }
1462
1463 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1464 {
1465         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1466         int val = 0;
1467
1468         spin_lock_irq(&ensoniq->reg_lock);
1469         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1470                 val = 1;
1471         ucontrol->value.integer.value[0] = val;
1472         spin_unlock_irq(&ensoniq->reg_lock);
1473         return 0;
1474 }
1475
1476 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1477 {
1478         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1479         unsigned int nval1;
1480         int change;
1481
1482         nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1483         spin_lock_irq(&ensoniq->reg_lock);
1484         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1485         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1486         ensoniq->cssr |= nval1;
1487         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1488         spin_unlock_irq(&ensoniq->reg_lock);
1489         return change;
1490 }
1491
1492 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1493 {
1494         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1495         .name =         "AC97 2ch->4ch Copy Switch",
1496         .info =         snd_es1373_rear_info,
1497         .get =          snd_es1373_rear_get,
1498         .put =          snd_es1373_rear_put,
1499 };
1500
1501 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1502 {
1503         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1504         uinfo->count = 1;
1505         uinfo->value.integer.min = 0;
1506         uinfo->value.integer.max = 1;
1507         return 0;
1508 }
1509
1510 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1511 {
1512         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1513         int val = 0;
1514
1515         spin_lock_irq(&ensoniq->reg_lock);
1516         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1517                 val = 1;
1518         ucontrol->value.integer.value[0] = val;
1519         spin_unlock_irq(&ensoniq->reg_lock);
1520         return 0;
1521 }
1522
1523 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1524 {
1525         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1526         int changed;
1527         unsigned int ctrl;
1528
1529         spin_lock_irq(&ensoniq->reg_lock);
1530         ctrl = ensoniq->ctrl;
1531         if (ucontrol->value.integer.value[0])
1532                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1533         else
1534                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1535         changed = (ctrl != ensoniq->ctrl);
1536         if (changed)
1537                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1538         spin_unlock_irq(&ensoniq->reg_lock);
1539         return changed;
1540 }
1541
1542 static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1543 {
1544         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1545         .name =         "Line In->Rear Out Switch",
1546         .info =         snd_es1373_line_info,
1547         .get =          snd_es1373_line_get,
1548         .put =          snd_es1373_line_put,
1549 };
1550
1551 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1552 {
1553         ensoniq_t *ensoniq = ac97->private_data;
1554         ensoniq->u.es1371.ac97 = NULL;
1555 }
1556
1557 static struct {
1558         unsigned short vid;             /* vendor ID */
1559         unsigned short did;             /* device ID */
1560         unsigned char rev;              /* revision */
1561 } es1371_spdif_present[] __devinitdata = {
1562         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1563         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1564         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1565         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1566         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1567         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1568 };
1569
1570 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1571 {
1572         snd_card_t *card = ensoniq->card;
1573         ac97_bus_t *pbus;
1574         ac97_template_t ac97;
1575         int err, idx;
1576         static ac97_bus_ops_t ops = {
1577                 .write = snd_es1371_codec_write,
1578                 .read = snd_es1371_codec_read,
1579         };
1580
1581         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1582                 return err;
1583
1584         memset(&ac97, 0, sizeof(ac97));
1585         ac97.private_data = ensoniq;
1586         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1587         ac97.scaps = AC97_SCAP_AUDIO;
1588         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1589                 return err;
1590         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1591                 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1592                     ensoniq->pci->device == es1371_spdif_present[idx].did &&
1593                     ensoniq->rev == es1371_spdif_present[idx].rev) {
1594                         snd_kcontrol_t *kctl;
1595                         int i, index = 0;
1596
1597                         ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1598                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1599
1600                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1601                                 index++;
1602
1603                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1604                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1605                                 if (! kctl)
1606                                         return -ENOMEM;
1607                                 kctl->id.index = index;
1608                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1609                                         return err;
1610                         }
1611                         break;
1612                 }
1613         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1614                 /* mirror rear to front speakers */
1615                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1616                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1617                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1618                 if (err < 0)
1619                         return err;
1620         }
1621         if ((ensoniq->subsystem_vendor_id == 0x1274) &&
1622             (ensoniq->subsystem_device_id == 0x2000)) { /* GA-7DXR */
1623                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1624                  if (err < 0)
1625                          return err;
1626         }
1627
1628         return 0;
1629 }
1630
1631 #endif /* CHIP1371 */
1632
1633 /* generic control callbacks for ens1370 */
1634 #ifdef CHIP1370
1635 #define ENSONIQ_CONTROL(xname, mask) \
1636 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1637   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1638   .private_value = mask }
1639
1640 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1641 {
1642         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1643         uinfo->count = 1;
1644         uinfo->value.integer.min = 0;
1645         uinfo->value.integer.max = 1;
1646         return 0;
1647 }
1648
1649 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1650 {
1651         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1652         int mask = kcontrol->private_value;
1653
1654         spin_lock_irq(&ensoniq->reg_lock);
1655         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1656         spin_unlock_irq(&ensoniq->reg_lock);
1657         return 0;
1658 }
1659
1660 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1661 {
1662         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1663         int mask = kcontrol->private_value;
1664         unsigned int nval;
1665         int change;
1666
1667         nval = ucontrol->value.integer.value[0] ? mask : 0;
1668         spin_lock_irq(&ensoniq->reg_lock);
1669         change = (ensoniq->ctrl & mask) != nval;
1670         ensoniq->ctrl &= ~mask;
1671         ensoniq->ctrl |= nval;
1672         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1673         spin_unlock_irq(&ensoniq->reg_lock);
1674         return change;
1675 }
1676
1677 /*
1678  * ENS1370 mixer
1679  */
1680
1681 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1682 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1683 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1684 };
1685
1686 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1687
1688 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1689 {
1690         ensoniq_t *ensoniq = ak4531->private_data;
1691         ensoniq->u.es1370.ak4531 = NULL;
1692 }
1693
1694 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1695 {
1696         snd_card_t *card = ensoniq->card;
1697         ak4531_t ak4531;
1698         unsigned int idx;
1699         int err;
1700
1701         /* try reset AK4531 */
1702         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1703         inw(ES_REG(ensoniq, 1370_CODEC));
1704         udelay(100);
1705         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1706         inw(ES_REG(ensoniq, 1370_CODEC));
1707         udelay(100);
1708
1709         memset(&ak4531, 0, sizeof(ak4531));
1710         ak4531.write = snd_es1370_codec_write;
1711         ak4531.private_data = ensoniq;
1712         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1713         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1714                 return err;
1715         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1716                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1717                 if (err < 0)
1718                         return err;
1719         }
1720         return 0;
1721 }
1722
1723 #endif /* CHIP1370 */
1724
1725 #ifdef SUPPORT_JOYSTICK
1726 static int snd_ensoniq_joystick(ensoniq_t *ensoniq, long port)
1727 {
1728 #ifdef CHIP1371
1729         if (port == 1) { /* auto-detect */
1730                 for (port = 0x200; port <= 0x218; port += 8)
1731                         if (request_region(port, 8, "ens137x: gameport"))
1732                                 break;
1733                 if (port > 0x218) {
1734                         snd_printk("no gameport available\n");
1735                         return -EBUSY;
1736                 }
1737         } else
1738 #endif
1739         {
1740                 if (!request_region(port, 8, "ens137x: gameport")) {
1741                         snd_printk("gameport io port 0x%03x in use", ensoniq->gameport.io);
1742                         return -EBUSY;
1743                 }
1744         }
1745         ensoniq->gameport.io = port;
1746         ensoniq->ctrl |= ES_JYSTK_EN;
1747 #ifdef CHIP1371
1748         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1749         ensoniq->ctrl |= ES_1371_JOY_ASEL((ensoniq->gameport.io - 0x200) / 8);
1750 #endif
1751         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1752         gameport_register_port(&ensoniq->gameport);
1753         return 0;
1754 }
1755
1756 static void snd_ensoniq_joystick_free(ensoniq_t *ensoniq)
1757 {
1758         gameport_unregister_port(&ensoniq->gameport);
1759         ensoniq->ctrl &= ~ES_JYSTK_EN;
1760         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1761         release_region(ensoniq->gameport.io, 8);
1762 }
1763 #endif /* SUPPORT_JOYSTICK */
1764
1765 /*
1766
1767  */
1768
1769 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1770                                   snd_info_buffer_t * buffer)
1771 {
1772         ensoniq_t *ensoniq = entry->private_data;
1773
1774 #ifdef CHIP1370
1775         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1776 #else
1777         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1778 #endif
1779         snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1780 #ifdef CHIP1370
1781         snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1782         snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1783 #else
1784         snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1785 #endif
1786 }
1787
1788 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1789 {
1790         snd_info_entry_t *entry;
1791
1792         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1793                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1794 }
1795
1796 /*
1797
1798  */
1799
1800 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1801 {
1802 #ifdef SUPPORT_JOYSTICK
1803         if (ensoniq->ctrl & ES_JYSTK_EN)
1804                 snd_ensoniq_joystick_free(ensoniq);
1805 #endif
1806         if (ensoniq->irq < 0)
1807                 goto __hw_end;
1808 #ifdef CHIP1370
1809         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1810         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1811 #else
1812         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1813         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1814 #endif
1815         synchronize_irq(ensoniq->irq);
1816         pci_set_power_state(ensoniq->pci, 3);
1817       __hw_end:
1818 #ifdef CHIP1370
1819         if (ensoniq->dma_bug.area)
1820                 snd_dma_free_pages(&ensoniq->dma_bug);
1821 #endif
1822         if (ensoniq->irq >= 0)
1823                 free_irq(ensoniq->irq, (void *)ensoniq);
1824         pci_release_regions(ensoniq->pci);
1825         kfree(ensoniq);
1826         return 0;
1827 }
1828
1829 static int snd_ensoniq_dev_free(snd_device_t *device)
1830 {
1831         ensoniq_t *ensoniq = device->device_data;
1832         return snd_ensoniq_free(ensoniq);
1833 }
1834
1835 #ifdef CHIP1371
1836 static struct {
1837         unsigned short svid;            /* subsystem vendor ID */
1838         unsigned short sdid;            /* subsystem device ID */
1839 } es1371_amplifier_hack[] = {
1840         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1841         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1842         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1843         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1844         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1845 };
1846 static struct {
1847         unsigned short vid;             /* vendor ID */
1848         unsigned short did;             /* device ID */
1849         unsigned char rev;              /* revision */
1850 } es1371_ac97_reset_hack[] = {
1851         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1852         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1853         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1854         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1855         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1856         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1857 };
1858 #endif
1859
1860 static int __devinit snd_ensoniq_create(snd_card_t * card,
1861                                      struct pci_dev *pci,
1862                                      ensoniq_t ** rensoniq)
1863 {
1864         ensoniq_t *ensoniq;
1865         unsigned short cmdw;
1866         unsigned char cmdb;
1867 #ifdef CHIP1371
1868         int idx;
1869 #endif
1870         int err;
1871         static snd_device_ops_t ops = {
1872                 .dev_free =     snd_ensoniq_dev_free,
1873         };
1874
1875         *rensoniq = NULL;
1876         if ((err = pci_enable_device(pci)) < 0)
1877                 return err;
1878         ensoniq = kcalloc(1, sizeof(*ensoniq), GFP_KERNEL);
1879         if (ensoniq == NULL)
1880                 return -ENOMEM;
1881         spin_lock_init(&ensoniq->reg_lock);
1882         ensoniq->card = card;
1883         ensoniq->pci = pci;
1884         ensoniq->irq = -1;
1885         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
1886                 kfree(ensoniq);
1887                 return err;
1888         }
1889         ensoniq->port = pci_resource_start(pci, 0);
1890         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1891                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1892                 snd_ensoniq_free(ensoniq);
1893                 return -EBUSY;
1894         }
1895         ensoniq->irq = pci->irq;
1896 #ifdef CHIP1370
1897         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1898                                 16, &ensoniq->dma_bug) < 0) {
1899                 snd_printk("unable to allocate space for phantom area - dma_bug\n");
1900                 snd_ensoniq_free(ensoniq);
1901                 return -EBUSY;
1902         }
1903 #endif
1904         pci_set_master(pci);
1905         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1906         ensoniq->rev = cmdb;
1907         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1908         ensoniq->subsystem_vendor_id = cmdw;
1909         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1910         ensoniq->subsystem_device_id = cmdw;
1911         snd_ensoniq_proc_init(ensoniq);
1912 #ifdef CHIP1370
1913 #if 0
1914         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1915 #else   /* get microphone working */
1916         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1917 #endif
1918         ensoniq->sctrl = 0;
1919         /* initialize the chips */
1920         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1921         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1922         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1923         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1924         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1925 #else
1926         ensoniq->ctrl = 0;
1927         ensoniq->sctrl = 0;
1928         ensoniq->cssr = 0;
1929         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
1930                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
1931                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
1932                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
1933                         break;
1934                 }
1935         /* initialize the chips */
1936         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1937         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1938         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1939         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1940                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1941                     pci->device == es1371_ac97_reset_hack[idx].did &&
1942                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1943                         unsigned long tmo;
1944                         signed long tmo2;
1945
1946                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
1947                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1948                         /* need to delay around 20ms(bleech) to give
1949                         some CODECs enough time to wakeup */
1950                         tmo = jiffies + (HZ / 50) + 1;
1951                         while (1) {
1952                                 tmo2 = tmo - jiffies;
1953                                 if (tmo2 <= 0)
1954                                         break;
1955                                 set_current_state(TASK_UNINTERRUPTIBLE);
1956                                 schedule_timeout(tmo2);
1957                         }
1958                         break;
1959                 }
1960         /* AC'97 warm reset to start the bitclk */
1961         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1962         inl(ES_REG(ensoniq, CONTROL));
1963         udelay(20);
1964         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1965         /* Init the sample rate converter */
1966         snd_es1371_wait_src_ready(ensoniq);
1967         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1968         for (idx = 0; idx < 0x80; idx++)
1969                 snd_es1371_src_write(ensoniq, idx, 0);
1970         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1971         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1972         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1973         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1974         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1975         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1976         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1977         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1978         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1979         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1980         snd_es1371_adc_rate(ensoniq, 22050);
1981         snd_es1371_dac1_rate(ensoniq, 22050);
1982         snd_es1371_dac2_rate(ensoniq, 22050);
1983         /* WARNING:
1984          * enabling the sample rate converter without properly programming
1985          * its parameters causes the chip to lock up (the SRC busy bit will
1986          * be stuck high, and I've found no way to rectify this other than
1987          * power cycle) - Thomas Sailer
1988          */
1989         snd_es1371_wait_src_ready(ensoniq);
1990         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1991         /* try reset codec directly */
1992         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1993 #endif
1994         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1995         outb(0x00, ES_REG(ensoniq, UART_RES));
1996         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1997         synchronize_irq(ensoniq->irq);
1998
1999         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2000                 snd_ensoniq_free(ensoniq);
2001                 return err;
2002         }
2003
2004         snd_card_set_dev(card, &pci->dev);
2005
2006         *rensoniq = ensoniq;
2007         return 0;
2008 }
2009
2010 /*
2011  *  MIDI section
2012  */
2013
2014 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2015 {
2016         snd_rawmidi_t * rmidi = ensoniq->rmidi;
2017         unsigned char status, mask, byte;
2018
2019         if (rmidi == NULL)
2020                 return;
2021         /* do Rx at first */
2022         spin_lock(&ensoniq->reg_lock);
2023         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2024         while (mask) {
2025                 status = inb(ES_REG(ensoniq, UART_STATUS));
2026                 if ((status & mask) == 0)
2027                         break;
2028                 byte = inb(ES_REG(ensoniq, UART_DATA));
2029                 spin_unlock(&ensoniq->reg_lock);
2030                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2031                 spin_lock(&ensoniq->reg_lock);
2032         }
2033         spin_unlock(&ensoniq->reg_lock);
2034
2035         /* do Tx at second */
2036         spin_lock(&ensoniq->reg_lock);
2037         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2038         while (mask) {
2039                 status = inb(ES_REG(ensoniq, UART_STATUS));
2040                 if ((status & mask) == 0)
2041                         break;
2042                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2043                         ensoniq->uartc &= ~ES_TXINTENM;
2044                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2045                         mask &= ~ES_TXRDY;
2046                 } else {
2047                         outb(byte, ES_REG(ensoniq, UART_DATA));
2048                 }
2049         }
2050         spin_unlock(&ensoniq->reg_lock);
2051 }
2052
2053 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2054 {
2055         ensoniq_t *ensoniq = substream->rmidi->private_data;
2056
2057         spin_lock_irq(&ensoniq->reg_lock);
2058         ensoniq->uartm |= ES_MODE_INPUT;
2059         ensoniq->midi_input = substream;
2060         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2061                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2062                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2063                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2064         }
2065         spin_unlock_irq(&ensoniq->reg_lock);
2066         return 0;
2067 }
2068
2069 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2070 {
2071         ensoniq_t *ensoniq = substream->rmidi->private_data;
2072
2073         spin_lock_irq(&ensoniq->reg_lock);
2074         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2075                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2076                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2077         } else {
2078                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2079         }
2080         ensoniq->midi_input = NULL;
2081         ensoniq->uartm &= ~ES_MODE_INPUT;
2082         spin_unlock_irq(&ensoniq->reg_lock);
2083         return 0;
2084 }
2085
2086 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2087 {
2088         ensoniq_t *ensoniq = substream->rmidi->private_data;
2089
2090         spin_lock_irq(&ensoniq->reg_lock);
2091         ensoniq->uartm |= ES_MODE_OUTPUT;
2092         ensoniq->midi_output = substream;
2093         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2094                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2095                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2096                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2097         }
2098         spin_unlock_irq(&ensoniq->reg_lock);
2099         return 0;
2100 }
2101
2102 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2103 {
2104         ensoniq_t *ensoniq = substream->rmidi->private_data;
2105
2106         spin_lock_irq(&ensoniq->reg_lock);
2107         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2108                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2109                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2110         } else {
2111                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2112         }
2113         ensoniq->midi_output = NULL;
2114         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2115         spin_unlock_irq(&ensoniq->reg_lock);
2116         return 0;
2117 }
2118
2119 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2120 {
2121         unsigned long flags;
2122         ensoniq_t *ensoniq = substream->rmidi->private_data;
2123         int idx;
2124
2125         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2126         if (up) {
2127                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2128                         /* empty input FIFO */
2129                         for (idx = 0; idx < 32; idx++)
2130                                 inb(ES_REG(ensoniq, UART_DATA));
2131                         ensoniq->uartc |= ES_RXINTEN;
2132                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2133                 }
2134         } else {
2135                 if (ensoniq->uartc & ES_RXINTEN) {
2136                         ensoniq->uartc &= ~ES_RXINTEN;
2137                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2138                 }
2139         }
2140         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2141 }
2142
2143 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2144 {
2145         unsigned long flags;
2146         ensoniq_t *ensoniq = substream->rmidi->private_data;
2147         unsigned char byte;
2148
2149         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2150         if (up) {
2151                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2152                         ensoniq->uartc |= ES_TXINTENO(1);
2153                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2154                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2155                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2156                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2157                                         ensoniq->uartc &= ~ES_TXINTENM;
2158                                 } else {
2159                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2160                                 }
2161                         }
2162                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2163                 }
2164         } else {
2165                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2166                         ensoniq->uartc &= ~ES_TXINTENM;
2167                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2168                 }
2169         }
2170         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2171 }
2172
2173 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2174 {
2175         .open =         snd_ensoniq_midi_output_open,
2176         .close =        snd_ensoniq_midi_output_close,
2177         .trigger =      snd_ensoniq_midi_output_trigger,
2178 };
2179
2180 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2181 {
2182         .open =         snd_ensoniq_midi_input_open,
2183         .close =        snd_ensoniq_midi_input_close,
2184         .trigger =      snd_ensoniq_midi_input_trigger,
2185 };
2186
2187 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2188 {
2189         snd_rawmidi_t *rmidi;
2190         int err;
2191
2192         if (rrawmidi)
2193                 *rrawmidi = NULL;
2194         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2195                 return err;
2196 #ifdef CHIP1370
2197         strcpy(rmidi->name, "ES1370");
2198 #else
2199         strcpy(rmidi->name, "ES1371");
2200 #endif
2201         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2202         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2203         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2204         rmidi->private_data = ensoniq;
2205         ensoniq->rmidi = rmidi;
2206         if (rrawmidi)
2207                 *rrawmidi = rmidi;
2208         return 0;
2209 }
2210
2211 /*
2212  *  Interrupt handler
2213  */
2214
2215 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2216 {
2217         ensoniq_t *ensoniq = dev_id;
2218         unsigned int status, sctrl;
2219
2220         if (ensoniq == NULL)
2221                 return IRQ_NONE;
2222
2223         status = inl(ES_REG(ensoniq, STATUS));
2224         if (!(status & ES_INTR))
2225                 return IRQ_NONE;
2226
2227         spin_lock(&ensoniq->reg_lock);
2228         sctrl = ensoniq->sctrl;
2229         if (status & ES_DAC1)
2230                 sctrl &= ~ES_P1_INT_EN;
2231         if (status & ES_DAC2)
2232                 sctrl &= ~ES_P2_INT_EN;
2233         if (status & ES_ADC)
2234                 sctrl &= ~ES_R1_INT_EN;
2235         outl(sctrl, ES_REG(ensoniq, SERIAL));
2236         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2237         spin_unlock(&ensoniq->reg_lock);
2238
2239         if (status & ES_UART)
2240                 snd_ensoniq_midi_interrupt(ensoniq);
2241         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2242                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2243         if ((status & ES_ADC) && ensoniq->capture_substream)
2244                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2245         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2246                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2247         return IRQ_HANDLED;
2248 }
2249
2250 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2251                                         const struct pci_device_id *pci_id)
2252 {
2253         static int dev;
2254         snd_card_t *card;
2255         ensoniq_t *ensoniq;
2256         int err, pcm_devs[2];
2257
2258         if (dev >= SNDRV_CARDS)
2259                 return -ENODEV;
2260         if (!enable[dev]) {
2261                 dev++;
2262                 return -ENOENT;
2263         }
2264
2265         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2266         if (card == NULL)
2267                 return -ENOMEM;
2268
2269         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2270                 snd_card_free(card);
2271                 return err;
2272         }
2273
2274         pcm_devs[0] = 0; pcm_devs[1] = 1;
2275 #ifdef CHIP1370
2276         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2277                 snd_card_free(card);
2278                 return err;
2279         }
2280 #endif
2281 #ifdef CHIP1371
2282         if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2283                 snd_card_free(card);
2284                 return err;
2285         }
2286 #endif
2287         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2288                 snd_card_free(card);
2289                 return err;
2290         }
2291         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2292                 snd_card_free(card);
2293                 return err;
2294         }
2295         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2296                 snd_card_free(card);
2297                 return err;
2298         }
2299 #ifdef SUPPORT_JOYSTICK
2300 #ifdef CHIP1371
2301         switch (joystick_port[dev]) {
2302         case 1: /* auto-detect */
2303         case 0x200:
2304         case 0x208:
2305         case 0x210:
2306         case 0x218:
2307                 snd_ensoniq_joystick(ensoniq, joystick_port[dev]);
2308                 break;
2309         }
2310 #else
2311         if (joystick[dev])
2312                 snd_ensoniq_joystick(ensoniq, 0x200);
2313 #endif
2314 #endif /* SUPPORT_JOYSTICK */
2315         strcpy(card->driver, DRIVER_NAME);
2316
2317         strcpy(card->shortname, "Ensoniq AudioPCI");
2318         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2319                 card->shortname,
2320                 card->driver,
2321                 ensoniq->port,
2322                 ensoniq->irq);
2323
2324         if ((err = snd_card_register(card)) < 0) {
2325                 snd_card_free(card);
2326                 return err;
2327         }
2328
2329         pci_set_drvdata(pci, card);
2330         dev++;
2331         return 0;
2332 }
2333
2334 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2335 {
2336         snd_card_free(pci_get_drvdata(pci));
2337         pci_set_drvdata(pci, NULL);
2338 }
2339
2340 static struct pci_driver driver = {
2341         .name = DRIVER_NAME,
2342         .id_table = snd_audiopci_ids,
2343         .probe = snd_audiopci_probe,
2344         .remove = __devexit_p(snd_audiopci_remove),
2345 };
2346
2347 static int __init alsa_card_ens137x_init(void)
2348 {
2349         return pci_module_init(&driver);
2350 }
2351
2352 static void __exit alsa_card_ens137x_exit(void)
2353 {
2354         pci_unregister_driver(&driver);
2355 }
2356
2357 module_init(alsa_card_ens137x_init)
2358 module_exit(alsa_card_ens137x_exit)