2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
8 * Rewritted from card-es1938.c source.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * Notes from Zach Brown about the driver code
30 * Hardware Description
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
97 #include <sound/driver.h>
99 #include <linux/delay.h>
100 #include <linux/interrupt.h>
101 #include <linux/init.h>
102 #include <linux/pci.h>
103 #include <linux/slab.h>
104 #include <linux/gameport.h>
105 #include <linux/moduleparam.h>
106 #include <sound/core.h>
107 #include <sound/pcm.h>
108 #include <sound/mpu401.h>
109 #include <sound/ac97_codec.h>
110 #include <sound/initval.h>
112 #define CARD_NAME "ESS Maestro1/2"
113 #define DRIVER_NAME "ES1968"
115 MODULE_DESCRIPTION("ESS Maestro");
116 MODULE_LICENSE("GPL");
117 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
122 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
123 #define SUPPORT_JOYSTICK 1
126 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
127 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
128 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
129 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
130 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
131 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
132 static int clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
133 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
134 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
135 #ifdef SUPPORT_JOYSTICK
136 static int joystick[SNDRV_CARDS];
138 static int boot_devs;
140 module_param_array(index, int, boot_devs, 0444);
141 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
142 module_param_array(id, charp, boot_devs, 0444);
143 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
144 module_param_array(enable, bool, boot_devs, 0444);
145 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
146 module_param_array(total_bufsize, int, boot_devs, 0444);
147 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
148 module_param_array(pcm_substreams_p, int, boot_devs, 0444);
149 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
150 module_param_array(pcm_substreams_c, int, boot_devs, 0444);
151 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
152 module_param_array(clock, int, boot_devs, 0444);
153 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
154 module_param_array(use_pm, int, boot_devs, 0444);
155 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
156 module_param_array(enable_mpu, int, boot_devs, 0444);
157 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
158 #ifdef SUPPORT_JOYSTICK
159 module_param_array(joystick, bool, boot_devs, 0444);
160 MODULE_PARM_DESC(joystick, "Enable joystick.");
166 #ifndef PCI_VENDOR_ID_ESS
167 #define PCI_VENDOR_ID_ESS 0x125D
170 #define PCI_VENDOR_ID_ESS_OLD 0x1285 /* Platform Tech, the people the ESS
173 #ifndef PCI_DEVICE_ID_ESS_M2E
174 #define PCI_DEVICE_ID_ESS_M2E 0x1978
176 #ifndef PCI_DEVICE_ID_ESS_M2
177 #define PCI_DEVICE_ID_ESS_M2 0x1968
179 #ifndef PCI_DEVICE_ID_ESS_M1
180 #define PCI_DEVICE_ID_ESS_M1 0x0100
184 #define NR_APU_REGS 16
187 #define NEC_VERSA_SUBID1 0x80581033
188 #define NEC_VERSA_SUBID2 0x803c1033
191 #define ESS_FMT_STEREO 0x01
192 #define ESS_FMT_16BIT 0x02
194 #define DAC_RUNNING 1
195 #define ADC_RUNNING 2
197 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
199 #define ESS_ENABLE_AUDIO 0x8000
200 #define ESS_ENABLE_SERIAL_IRQ 0x4000
201 #define IO_ADRESS_ALIAS 0x0020
202 #define MPU401_IRQ_ENABLE 0x0010
203 #define MPU401_IO_ENABLE 0x0008
204 #define GAME_IO_ENABLE 0x0004
205 #define FM_IO_ENABLE 0x0002
206 #define SB_IO_ENABLE 0x0001
208 /* Values for the ESM_CONFIG_A */
210 #define PIC_SNOOP1 0x4000
211 #define PIC_SNOOP2 0x2000
212 #define SAFEGUARD 0x0800
213 #define DMA_CLEAR 0x0700
214 #define DMA_DDMA 0x0000
215 #define DMA_TDMA 0x0100
216 #define DMA_PCPCI 0x0200
217 #define POST_WRITE 0x0080
218 #define ISA_TIMING 0x0040
219 #define SWAP_LR 0x0020
220 #define SUBTR_DECODE 0x0002
222 /* Values for the ESM_CONFIG_B */
224 #define SPDIF_CONFB 0x0100
225 #define HWV_CONFB 0x0080
226 #define DEBOUNCE 0x0040
227 #define GPIO_CONFB 0x0020
228 #define CHI_CONFB 0x0010
229 #define IDMA_CONFB 0x0008 /*undoc */
230 #define MIDI_FIX 0x0004 /*undoc */
231 #define IRQ_TO_ISA 0x0001 /*undoc */
233 /* Values for Ring Bus Control B */
234 #define RINGB_2CODEC_ID_MASK 0x0003
235 #define RINGB_DIS_VALIDATION 0x0008
236 #define RINGB_EN_SPDIF 0x0010
237 #define RINGB_EN_2CODEC 0x0020
238 #define RINGB_SING_BIT_DUAL 0x0040
240 /* ****Port Adresses**** */
243 #define ESM_INDEX 0x02
244 #define ESM_DATA 0x00
247 #define ESM_AC97_INDEX 0x30
248 #define ESM_AC97_DATA 0x32
249 #define ESM_RING_BUS_DEST 0x34
250 #define ESM_RING_BUS_CONTR_A 0x36
251 #define ESM_RING_BUS_CONTR_B 0x38
252 #define ESM_RING_BUS_SDO 0x3A
255 #define WC_INDEX 0x10
257 #define WC_CONTROL 0x14
260 #define ASSP_INDEX 0x80
261 #define ASSP_MEMORY 0x82
262 #define ASSP_DATA 0x84
263 #define ASSP_CONTROL_A 0xA2
264 #define ASSP_CONTROL_B 0xA4
265 #define ASSP_CONTROL_C 0xA6
266 #define ASSP_HOSTW_INDEX 0xA8
267 #define ASSP_HOSTW_DATA 0xAA
268 #define ASSP_HOSTW_IRQ 0xAC
270 #define ESM_MPU401_PORT 0x98
272 #define ESM_PORT_HOST_IRQ 0x18
274 #define IDR0_DATA_PORT 0x00
275 #define IDR1_CRAM_POINTER 0x01
276 #define IDR2_CRAM_DATA 0x02
277 #define IDR3_WAVE_DATA 0x03
278 #define IDR4_WAVE_PTR_LOW 0x04
279 #define IDR5_WAVE_PTR_HI 0x05
280 #define IDR6_TIMER_CTRL 0x06
281 #define IDR7_WAVE_ROMRAM 0x07
283 #define WRITEABLE_MAP 0xEFFFFF
284 #define READABLE_MAP 0x64003F
288 #define ESM_LEGACY_AUDIO_CONTROL 0x40
289 #define ESM_ACPI_COMMAND 0x54
290 #define ESM_CONFIG_A 0x50
291 #define ESM_CONFIG_B 0x52
292 #define ESM_DDMA 0x60
295 #define ESM_BOB_ENABLE 0x0001
296 #define ESM_BOB_START 0x0001
298 /* Host IRQ Control Bits */
299 #define ESM_RESET_MAESTRO 0x8000
300 #define ESM_RESET_DIRECTSOUND 0x4000
301 #define ESM_HIRQ_ClkRun 0x0100
302 #define ESM_HIRQ_HW_VOLUME 0x0040
303 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
304 #define ESM_HIRQ_ASSP 0x0010
305 #define ESM_HIRQ_DSIE 0x0004
306 #define ESM_HIRQ_MPU401 0x0002
307 #define ESM_HIRQ_SB 0x0001
309 /* Host IRQ Status Bits */
310 #define ESM_MPU401_IRQ 0x02
311 #define ESM_SB_IRQ 0x01
312 #define ESM_SOUND_IRQ 0x04
313 #define ESM_ASSP_IRQ 0x10
314 #define ESM_HWVOL_IRQ 0x40
316 #define ESS_SYSCLK 50000000
317 #define ESM_BOB_FREQ 200
318 #define ESM_BOB_FREQ_MAX 800
320 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
321 #define ESM_FREQ_ESM2 (50000000L / 1024L)
323 /* APU Modes: reg 0x00, bit 4-7 */
324 #define ESM_APU_MODE_SHIFT 4
325 #define ESM_APU_MODE_MASK (0xf << 4)
326 #define ESM_APU_OFF 0x00
327 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
328 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
329 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
330 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
331 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
332 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
333 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
334 #define ESM_APU_CORRELATOR 0x08 /* Correlator */
335 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
336 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
337 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
338 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
339 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
340 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
341 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
344 #define ESM_APU_FILTER_Q_SHIFT 0
345 #define ESM_APU_FILTER_Q_MASK (3 << 0)
346 /* APU Filtey Q Control */
347 #define ESM_APU_FILTER_LESSQ 0x00
348 #define ESM_APU_FILTER_MOREQ 0x03
350 #define ESM_APU_FILTER_TYPE_SHIFT 2
351 #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
352 #define ESM_APU_ENV_TYPE_SHIFT 8
353 #define ESM_APU_ENV_TYPE_MASK (3 << 8)
354 #define ESM_APU_ENV_STATE_SHIFT 10
355 #define ESM_APU_ENV_STATE_MASK (3 << 10)
356 #define ESM_APU_END_CURVE (1 << 12)
357 #define ESM_APU_INT_ON_LOOP (1 << 13)
358 #define ESM_APU_DMA_ENABLE (1 << 14)
361 #define ESM_APU_SUBMIX_GROUP_SHIRT 0
362 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
363 #define ESM_APU_SUBMIX_MODE (1 << 3)
364 #define ESM_APU_6dB (1 << 4)
365 #define ESM_APU_DUAL_EFFECT (1 << 5)
366 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
367 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
370 #define ESM_APU_STEP_SIZE_MASK 0x0fff
373 #define ESM_APU_PHASE_SHIFT 0
374 #define ESM_APU_PHASE_MASK (0xff << 0)
375 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
376 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
378 /* reg 0x05 - wave start offset */
379 /* reg 0x06 - wave end offset */
380 /* reg 0x07 - wave loop length */
383 #define ESM_APU_EFFECT_GAIN_SHIFT 0
384 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
385 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
386 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
387 #define ESM_APU_TREMOLO_RATE_SHIFT 12
388 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
391 /* bit 0-7 amplitude dest? */
392 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
393 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
396 #define ESM_APU_POLAR_PAN_SHIFT 0
397 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
398 /* Polar Pan Control */
399 #define ESM_APU_PAN_CENTER_CIRCLE 0x00
400 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
401 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
403 #define ESM_APU_FILTER_TUNING_SHIFT 8
404 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
407 #define ESM_APU_DATA_SRC_A_SHIFT 0
408 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
409 #define ESM_APU_INV_POL_A (1 << 7)
410 #define ESM_APU_DATA_SRC_B_SHIFT 8
411 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
412 #define ESM_APU_INV_POL_B (1 << 15)
414 #define ESM_APU_VIBRATO_RATE_SHIFT 0
415 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
416 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
417 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
418 #define ESM_APU_VIBRATO_PHASE_SHIFT 8
419 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
422 #define ESM_APU_RADIUS_SELECT (1 << 6)
424 /* APU Filter Control */
425 #define ESM_APU_FILTER_2POLE_LOPASS 0x00
426 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
427 #define ESM_APU_FILTER_2POLE_HIPASS 0x02
428 #define ESM_APU_FILTER_1POLE_LOPASS 0x03
429 #define ESM_APU_FILTER_1POLE_HIPASS 0x04
430 #define ESM_APU_FILTER_OFF 0x05
433 #define ESM_APU_ATFP_AMPLITUDE 0x00
434 #define ESM_APU_ATFP_TREMELO 0x01
435 #define ESM_APU_ATFP_FILTER 0x02
436 #define ESM_APU_ATFP_PAN 0x03
439 #define ESM_APU_ATFP_FLG_OFF 0x00
440 #define ESM_APU_ATFP_FLG_WAIT 0x01
441 #define ESM_APU_ATFP_FLG_DONE 0x02
442 #define ESM_APU_ATFP_FLG_INPROCESS 0x03
445 /* capture mixing buffer size */
446 #define ESM_MEM_ALIGN 0x1000
447 #define ESM_MIXBUF_SIZE 0x400
449 #define ESM_MODE_PLAY 0
450 #define ESM_MODE_CAPTURE 1
460 /* bits in the acpi masks */
461 #define ACPI_12MHZ ( 1 << 15)
462 #define ACPI_24MHZ ( 1 << 14)
463 #define ACPI_978 ( 1 << 13)
464 #define ACPI_SPDIF ( 1 << 12)
465 #define ACPI_GLUE ( 1 << 11)
466 #define ACPI__10 ( 1 << 10) /* reserved */
467 #define ACPI_PCIINT ( 1 << 9)
468 #define ACPI_HV ( 1 << 8) /* hardware volume */
469 #define ACPI_GPIO ( 1 << 7)
470 #define ACPI_ASSP ( 1 << 6)
471 #define ACPI_SB ( 1 << 5) /* sb emul */
472 #define ACPI_FM ( 1 << 4) /* fm emul */
473 #define ACPI_RB ( 1 << 3) /* ringbus / aclink */
474 #define ACPI_MIDI ( 1 << 2)
475 #define ACPI_GP ( 1 << 1) /* game port */
476 #define ACPI_WP ( 1 << 0) /* wave processor */
478 #define ACPI_ALL (0xffff)
479 #define ACPI_SLEEP (~(ACPI_SPDIF|ACPI_ASSP|ACPI_SB|ACPI_FM| \
480 ACPI_MIDI|ACPI_GP|ACPI_WP))
481 #define ACPI_NONE (ACPI__10)
483 /* these masks indicate which units we care about at
485 static u16 acpi_state_mask[] = {
486 [ACPI_D0] = ACPI_ALL,
487 [ACPI_D1] = ACPI_SLEEP,
488 [ACPI_D2] = ACPI_SLEEP,
489 [ACPI_D3] = ACPI_NONE
493 typedef struct snd_es1968 es1968_t;
494 typedef struct snd_esschan esschan_t;
495 typedef struct snd_esm_memory esm_memory_t;
497 /* APU use in the driver */
498 enum snd_enum_apu_type {
501 ESM_APU_PCM_RATECONV,
507 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
511 struct snd_esm_memory {
512 struct snd_dma_buffer buf;
513 int empty; /* status */
514 struct list_head list;
517 /* Playback Channel */
524 /* playback/capture pcm buffer */
525 esm_memory_t *memory;
526 /* capture mixer buffer */
527 esm_memory_t *mixbuf;
529 unsigned int hwptr; /* current hw pointer in bytes */
530 unsigned int count; /* sample counter in bytes */
531 unsigned int dma_size; /* total buffer size in bytes */
532 unsigned int frag_size; /* period size in bytes */
533 unsigned int wav_shift;
534 u16 base[4]; /* offset for ptr */
536 /* stereo/16bit flag */
538 int mode; /* playback / capture */
540 int bob_freq; /* required timer frequency */
542 snd_pcm_substream_t *substream;
545 struct list_head list;
554 int total_bufsize; /* in bytes */
556 int playback_streams, capture_streams;
558 unsigned int clock; /* clock */
561 struct snd_dma_buffer dma;
565 unsigned long io_port;
570 int do_pm; /* power-management enabled */
572 /* DMA memory block */
573 struct list_head buf_list;
577 snd_kcontrol_t *master_switch; /* for h/w volume control */
578 snd_kcontrol_t *master_volume;
580 snd_rawmidi_t *rmidi;
583 struct tasklet_struct hwvol_tq;
587 int bobclient; /* active timer instancs */
588 int bob_freq; /* timer frequency */
589 struct semaphore memory_mutex; /* memory lock */
592 unsigned char apu[NR_APUS];
594 /* active substreams */
595 struct list_head substream_list;
596 spinlock_t substream_lock;
599 u16 apu_map[NR_APUS][NR_APU_REGS];
602 #ifdef SUPPORT_JOYSTICK
603 struct gameport gameport;
604 struct resource *res_joystick;
608 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs);
610 static struct pci_device_id snd_es1968_ids[] = {
612 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
614 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
616 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
620 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
622 /* *********************
624 *********************/
627 static void __maestro_write(es1968_t *chip, u16 reg, u16 data)
629 outw(reg, chip->io_port + ESM_INDEX);
630 outw(data, chip->io_port + ESM_DATA);
631 chip->maestro_map[reg] = data;
634 inline static void maestro_write(es1968_t *chip, u16 reg, u16 data)
637 spin_lock_irqsave(&chip->reg_lock, flags);
638 __maestro_write(chip, reg, data);
639 spin_unlock_irqrestore(&chip->reg_lock, flags);
643 static u16 __maestro_read(es1968_t *chip, u16 reg)
645 if (READABLE_MAP & (1 << reg)) {
646 outw(reg, chip->io_port + ESM_INDEX);
647 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
649 return chip->maestro_map[reg];
652 inline static u16 maestro_read(es1968_t *chip, u16 reg)
656 spin_lock_irqsave(&chip->reg_lock, flags);
657 result = __maestro_read(chip, reg);
658 spin_unlock_irqrestore(&chip->reg_lock, flags);
662 #define big_mdelay(msec) do {\
663 set_current_state(TASK_UNINTERRUPTIBLE);\
664 schedule_timeout(((msec) * HZ + 999) / 1000);\
667 /* Wait for the codec bus to be free */
668 static int snd_es1968_ac97_wait(es1968_t *chip)
670 int timeout = 100000;
672 while (timeout-- > 0) {
673 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
676 snd_printd("es1968: ac97 timeout\n");
677 return 1; /* timeout */
680 static void snd_es1968_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
682 es1968_t *chip = ac97->private_data;
685 spin_lock_irqsave(&chip->reg_lock, flags);
687 snd_es1968_ac97_wait(chip);
690 outw(val, chip->io_port + ESM_AC97_DATA);
692 outb(reg, chip->io_port + ESM_AC97_INDEX);
695 spin_unlock_irqrestore(&chip->reg_lock, flags);
698 static unsigned short snd_es1968_ac97_read(ac97_t *ac97, unsigned short reg)
701 es1968_t *chip = ac97->private_data;
704 spin_lock_irqsave(&chip->reg_lock, flags);
706 snd_es1968_ac97_wait(chip);
708 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
711 if (! snd_es1968_ac97_wait(chip)) {
712 data = inw(chip->io_port + ESM_AC97_DATA);
715 spin_unlock_irqrestore(&chip->reg_lock, flags);
721 static void apu_index_set(es1968_t *chip, u16 index)
724 __maestro_write(chip, IDR1_CRAM_POINTER, index);
725 for (i = 0; i < 1000; i++)
726 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
728 snd_printd("es1968: APU register select failed. (Timeout)\n");
732 static void apu_data_set(es1968_t *chip, u16 data)
735 for (i = 0; i < 1000; i++) {
736 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
738 __maestro_write(chip, IDR0_DATA_PORT, data);
740 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
744 static void __apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
746 snd_assert(channel < NR_APUS, return);
748 chip->apu_map[channel][reg] = data;
750 reg |= (channel << 4);
751 apu_index_set(chip, reg);
752 apu_data_set(chip, data);
755 inline static void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
758 spin_lock_irqsave(&chip->reg_lock, flags);
759 __apu_set_register(chip, channel, reg, data);
760 spin_unlock_irqrestore(&chip->reg_lock, flags);
763 static u16 __apu_get_register(es1968_t *chip, u16 channel, u8 reg)
765 snd_assert(channel < NR_APUS, return 0);
766 reg |= (channel << 4);
767 apu_index_set(chip, reg);
768 return __maestro_read(chip, IDR0_DATA_PORT);
771 inline static u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg)
775 spin_lock_irqsave(&chip->reg_lock, flags);
776 v = __apu_get_register(chip, channel, reg);
777 spin_unlock_irqrestore(&chip->reg_lock, flags);
781 #if 0 /* ASSP is not supported */
783 static void assp_set_register(es1968_t *chip, u32 reg, u32 value)
787 spin_lock_irqsave(&chip->reg_lock, flags);
788 outl(reg, chip->io_port + ASSP_INDEX);
789 outl(value, chip->io_port + ASSP_DATA);
790 spin_unlock_irqrestore(&chip->reg_lock, flags);
793 static u32 assp_get_register(es1968_t *chip, u32 reg)
798 spin_lock_irqsave(&chip->reg_lock, flags);
799 outl(reg, chip->io_port + ASSP_INDEX);
800 value = inl(chip->io_port + ASSP_DATA);
801 spin_unlock_irqrestore(&chip->reg_lock, flags);
808 static void wave_set_register(es1968_t *chip, u16 reg, u16 value)
812 spin_lock_irqsave(&chip->reg_lock, flags);
813 outw(reg, chip->io_port + WC_INDEX);
814 outw(value, chip->io_port + WC_DATA);
815 spin_unlock_irqrestore(&chip->reg_lock, flags);
818 static u16 wave_get_register(es1968_t *chip, u16 reg)
823 spin_lock_irqsave(&chip->reg_lock, flags);
824 outw(reg, chip->io_port + WC_INDEX);
825 value = inw(chip->io_port + WC_DATA);
826 spin_unlock_irqrestore(&chip->reg_lock, flags);
831 /* *******************
835 static void snd_es1968_bob_stop(es1968_t *chip)
840 spin_lock_irqsave(&chip->reg_lock, flags);
841 reg = __maestro_read(chip, 0x11);
842 reg &= ~ESM_BOB_ENABLE;
843 __maestro_write(chip, 0x11, reg);
844 reg = __maestro_read(chip, 0x17);
845 reg &= ~ESM_BOB_START;
846 __maestro_write(chip, 0x17, reg);
847 spin_unlock_irqrestore(&chip->reg_lock, flags);
850 static void snd_es1968_bob_start(es1968_t *chip)
856 /* compute ideal interrupt frequency for buffer size & play rate */
857 /* first, find best prescaler value to match freq */
858 for (prescale = 5; prescale < 12; prescale++)
859 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
862 /* next, back off prescaler whilst getting divider into optimum range */
864 while ((prescale > 5) && (divide < 32)) {
870 /* now fine-tune the divider for best match */
871 for (; divide < 31; divide++)
873 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
875 /* divide = 0 is illegal, but don't let prescale = 4! */
880 } else if (divide > 1)
883 spin_lock_irqsave(&chip->reg_lock, flags);
884 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
886 /* Now set IDR 11/17 */
887 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
888 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
889 spin_unlock_irqrestore(&chip->reg_lock, flags);
892 /* call with substream spinlock */
893 static void snd_es1968_bob_inc(es1968_t *chip, int freq)
896 if (chip->bobclient == 1) {
897 chip->bob_freq = freq;
898 snd_es1968_bob_start(chip);
899 } else if (chip->bob_freq < freq) {
900 snd_es1968_bob_stop(chip);
901 chip->bob_freq = freq;
902 snd_es1968_bob_start(chip);
906 /* call with substream spinlock */
907 static void snd_es1968_bob_dec(es1968_t *chip)
910 if (chip->bobclient <= 0)
911 snd_es1968_bob_stop(chip);
912 else if (chip->bob_freq > ESM_BOB_FREQ) {
913 /* check reduction of timer frequency */
915 int max_freq = ESM_BOB_FREQ;
916 list_for_each(p, &chip->substream_list) {
917 esschan_t *es = list_entry(p, esschan_t, list);
918 if (max_freq < es->bob_freq)
919 max_freq = es->bob_freq;
921 if (max_freq != chip->bob_freq) {
922 snd_es1968_bob_stop(chip);
923 chip->bob_freq = max_freq;
924 snd_es1968_bob_start(chip);
930 snd_es1968_calc_bob_rate(es1968_t *chip, esschan_t *es,
931 snd_pcm_runtime_t *runtime)
933 /* we acquire 4 interrupts per period for precise control.. */
934 int freq = runtime->rate * 4;
935 if (es->fmt & ESS_FMT_STEREO)
937 if (es->fmt & ESS_FMT_16BIT)
939 freq /= es->frag_size;
940 if (freq < ESM_BOB_FREQ)
942 else if (freq > ESM_BOB_FREQ_MAX)
943 freq = ESM_BOB_FREQ_MAX;
952 static u32 snd_es1968_compute_rate(es1968_t *chip, u32 freq)
954 u32 rate = (freq << 16) / chip->clock;
955 #if 0 /* XXX: do we need this? */
962 /* get current pointer */
963 inline static unsigned int
964 snd_es1968_get_dma_ptr(es1968_t *chip, esschan_t *es)
968 offset = apu_get_register(chip, es->apu[0], 5);
970 offset -= es->base[0];
972 return (offset & 0xFFFE); /* hardware is in words */
975 static void snd_es1968_apu_set_freq(es1968_t *chip, int apu, int freq)
977 apu_set_register(chip, apu, 2,
978 (apu_get_register(chip, apu, 2) & 0x00FF) |
979 ((freq & 0xff) << 8) | 0x10);
980 apu_set_register(chip, apu, 3, freq >> 8);
984 inline static void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode)
986 /* set the APU mode */
987 __apu_set_register(esm, apu, 0,
988 (__apu_get_register(esm, apu, 0) & 0xff0f) |
992 static void snd_es1968_pcm_start(es1968_t *chip, esschan_t *es)
994 spin_lock(&chip->reg_lock);
995 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
996 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
997 if (es->mode == ESM_MODE_CAPTURE) {
998 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
999 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
1001 if (es->fmt & ESS_FMT_STEREO) {
1002 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
1003 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
1004 if (es->mode == ESM_MODE_CAPTURE) {
1005 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
1006 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
1009 spin_unlock(&chip->reg_lock);
1012 static void snd_es1968_pcm_stop(es1968_t *chip, esschan_t *es)
1014 spin_lock(&chip->reg_lock);
1015 snd_es1968_trigger_apu(chip, es->apu[0], 0);
1016 snd_es1968_trigger_apu(chip, es->apu[1], 0);
1017 if (es->mode == ESM_MODE_CAPTURE) {
1018 snd_es1968_trigger_apu(chip, es->apu[2], 0);
1019 snd_es1968_trigger_apu(chip, es->apu[3], 0);
1021 spin_unlock(&chip->reg_lock);
1024 /* set the wavecache control reg */
1025 static void snd_es1968_program_wavecache(es1968_t *chip, esschan_t *es,
1026 int channel, u32 addr, int capture)
1028 u32 tmpval = (addr - 0x10) & 0xFFF8;
1031 if (!(es->fmt & ESS_FMT_16BIT))
1032 tmpval |= 4; /* 8bit */
1033 if (es->fmt & ESS_FMT_STEREO)
1034 tmpval |= 2; /* stereo */
1037 /* set the wavecache control reg */
1038 wave_set_register(chip, es->apu[channel] << 3, tmpval);
1041 es->wc_map[channel] = tmpval;
1046 static void snd_es1968_playback_setup(es1968_t *chip, esschan_t *es,
1047 snd_pcm_runtime_t *runtime)
1053 unsigned long flags;
1056 size = es->dma_size >> es->wav_shift;
1058 if (es->fmt & ESS_FMT_STEREO)
1061 for (channel = 0; channel <= high_apu; channel++) {
1062 apu = es->apu[channel];
1064 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1066 /* Offset to PCMBAR */
1067 pa = es->memory->buf.addr;
1068 pa -= chip->dma.addr;
1069 pa >>= 1; /* words */
1071 pa |= 0x00400000; /* System RAM (Bit 22) */
1073 if (es->fmt & ESS_FMT_STEREO) {
1076 pa |= 0x00800000; /* (Bit 23) */
1077 if (es->fmt & ESS_FMT_16BIT)
1081 /* base offset of dma calcs when reading the pointer
1083 es->base[channel] = pa & 0xFFFF;
1085 for (i = 0; i < 16; i++)
1086 apu_set_register(chip, apu, i, 0x0000);
1088 /* Load the buffer into the wave engine */
1089 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1090 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1091 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1092 /* setting loop == sample len */
1093 apu_set_register(chip, apu, 7, size);
1095 /* clear effects/env.. */
1096 apu_set_register(chip, apu, 8, 0x0000);
1097 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1098 apu_set_register(chip, apu, 9, 0xD000);
1100 /* clear routing stuff */
1101 apu_set_register(chip, apu, 11, 0x0000);
1102 /* dma on, no envelopes, filter to all 1s) */
1103 apu_set_register(chip, apu, 0, 0x400F);
1105 if (es->fmt & ESS_FMT_16BIT)
1106 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1108 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1110 if (es->fmt & ESS_FMT_STEREO) {
1111 /* set panning: left or right */
1112 /* Check: different panning. On my Canyon 3D Chipset the
1113 Channels are swapped. I don't know, about the output
1114 to the SPDif Link. Perhaps you have to change this
1115 and not the APU Regs 4-5. */
1116 apu_set_register(chip, apu, 10,
1117 0x8F00 | (channel ? 0 : 0x10));
1118 es->apu_mode[channel] += 1; /* stereo */
1120 apu_set_register(chip, apu, 10, 0x8F08);
1123 spin_lock_irqsave(&chip->reg_lock, flags);
1124 /* clear WP interrupts */
1125 outw(1, chip->io_port + 0x04);
1126 /* enable WP ints */
1127 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1128 spin_unlock_irqrestore(&chip->reg_lock, flags);
1130 freq = runtime->rate;
1138 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1141 freq = snd_es1968_compute_rate(chip, freq);
1143 /* Load the frequency, turn on 6dB */
1144 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1145 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1149 static void init_capture_apu(es1968_t *chip, esschan_t *es, int channel,
1150 unsigned int pa, unsigned int bsize,
1151 int mode, int route)
1153 int i, apu = es->apu[channel];
1155 es->apu_mode[channel] = mode;
1157 /* set the wavecache control reg */
1158 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1160 /* Offset to PCMBAR */
1161 pa -= chip->dma.addr;
1162 pa >>= 1; /* words */
1164 /* base offset of dma calcs when reading the pointer
1166 es->base[channel] = pa & 0xFFFF;
1167 pa |= 0x00400000; /* bit 22 -> System RAM */
1169 /* Begin loading the APU */
1170 for (i = 0; i < 16; i++)
1171 apu_set_register(chip, apu, i, 0x0000);
1173 /* need to enable subgroups.. and we should probably
1174 have different groups for different /dev/dsps.. */
1175 apu_set_register(chip, apu, 2, 0x8);
1177 /* Load the buffer into the wave engine */
1178 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1179 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1180 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1181 apu_set_register(chip, apu, 7, bsize);
1182 /* clear effects/env.. */
1183 apu_set_register(chip, apu, 8, 0x00F0);
1184 /* amplitude now? sure. why not. */
1185 apu_set_register(chip, apu, 9, 0x0000);
1186 /* set filter tune, radius, polar pan */
1187 apu_set_register(chip, apu, 10, 0x8F08);
1189 apu_set_register(chip, apu, 11, route);
1190 /* dma on, no envelopes, filter to all 1s) */
1191 apu_set_register(chip, apu, 0, 0x400F);
1194 static void snd_es1968_capture_setup(es1968_t *chip, esschan_t *es,
1195 snd_pcm_runtime_t *runtime)
1199 unsigned long flags;
1201 size = es->dma_size >> es->wav_shift;
1206 2 = mono/left Input Mixer
1207 3 = right Input Mixer
1209 /* data seems to flow from the codec, through an apu into
1210 the 'mixbuf' bit of page, then through the SRC apu
1211 and out to the real 'buffer'. ok. sure. */
1213 /* input mixer (left/mono) */
1214 /* parallel in crap, see maestro reg 0xC [8-11] */
1215 init_capture_apu(chip, es, 2,
1216 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1217 ESM_APU_INPUTMIXER, 0x14);
1218 /* SRC (left/mono); get input from inputing apu */
1219 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1220 ESM_APU_SRCONVERTOR, es->apu[2]);
1221 if (es->fmt & ESS_FMT_STEREO) {
1222 /* input mixer (right) */
1223 init_capture_apu(chip, es, 3,
1224 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1225 ESM_MIXBUF_SIZE/4, /* in words */
1226 ESM_APU_INPUTMIXER, 0x15);
1228 init_capture_apu(chip, es, 1,
1229 es->memory->buf.addr + size*2, size,
1230 ESM_APU_SRCONVERTOR, es->apu[3]);
1233 freq = runtime->rate;
1234 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1240 freq = snd_es1968_compute_rate(chip, freq);
1242 /* Load the frequency, turn on 6dB */
1243 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1244 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1246 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1248 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1249 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1251 spin_lock_irqsave(&chip->reg_lock, flags);
1252 /* clear WP interrupts */
1253 outw(1, chip->io_port + 0x04);
1254 /* enable WP ints */
1255 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1256 spin_unlock_irqrestore(&chip->reg_lock, flags);
1259 /*******************
1261 *******************/
1263 static int snd_es1968_pcm_prepare(snd_pcm_substream_t *substream)
1265 es1968_t *chip = snd_pcm_substream_chip(substream);
1266 snd_pcm_runtime_t *runtime = substream->runtime;
1267 esschan_t *es = runtime->private_data;
1269 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1270 es->frag_size = snd_pcm_lib_period_bytes(substream);
1272 es->wav_shift = 1; /* maestro handles always 16bit */
1274 if (snd_pcm_format_width(runtime->format) == 16)
1275 es->fmt |= ESS_FMT_16BIT;
1276 if (runtime->channels > 1) {
1277 es->fmt |= ESS_FMT_STEREO;
1278 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1281 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1285 snd_es1968_playback_setup(chip, es, runtime);
1287 case ESM_MODE_CAPTURE:
1288 snd_es1968_capture_setup(chip, es, runtime);
1295 static int snd_es1968_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1297 es1968_t *chip = snd_pcm_substream_chip(substream);
1298 esschan_t *es = substream->runtime->private_data;
1300 spin_lock(&chip->substream_lock);
1302 case SNDRV_PCM_TRIGGER_START:
1303 case SNDRV_PCM_TRIGGER_RESUME:
1306 snd_es1968_bob_inc(chip, es->bob_freq);
1309 snd_es1968_pcm_start(chip, es);
1312 case SNDRV_PCM_TRIGGER_STOP:
1313 case SNDRV_PCM_TRIGGER_SUSPEND:
1316 snd_es1968_pcm_stop(chip, es);
1318 snd_es1968_bob_dec(chip);
1321 spin_unlock(&chip->substream_lock);
1325 static snd_pcm_uframes_t snd_es1968_pcm_pointer(snd_pcm_substream_t *substream)
1327 es1968_t *chip = snd_pcm_substream_chip(substream);
1328 esschan_t *es = substream->runtime->private_data;
1331 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1333 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1336 static snd_pcm_hardware_t snd_es1968_playback = {
1337 .info = (SNDRV_PCM_INFO_MMAP |
1338 SNDRV_PCM_INFO_MMAP_VALID |
1339 SNDRV_PCM_INFO_INTERLEAVED |
1340 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1341 /*SNDRV_PCM_INFO_PAUSE |*/
1342 SNDRV_PCM_INFO_RESUME),
1343 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1344 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1349 .buffer_bytes_max = 65536,
1350 .period_bytes_min = 256,
1351 .period_bytes_max = 65536,
1353 .periods_max = 1024,
1357 static snd_pcm_hardware_t snd_es1968_capture = {
1358 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1359 SNDRV_PCM_INFO_MMAP |
1360 SNDRV_PCM_INFO_MMAP_VALID |
1361 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1362 /*SNDRV_PCM_INFO_PAUSE |*/
1363 SNDRV_PCM_INFO_RESUME),
1364 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1365 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1370 .buffer_bytes_max = 65536,
1371 .period_bytes_min = 256,
1372 .period_bytes_max = 65536,
1374 .periods_max = 1024,
1378 /* *************************
1379 * DMA memory management *
1380 *************************/
1382 /* Because the Maestro can only take addresses relative to the PCM base address
1385 static int calc_available_memory_size(es1968_t *chip)
1387 struct list_head *p;
1390 down(&chip->memory_mutex);
1391 list_for_each(p, &chip->buf_list) {
1392 esm_memory_t *buf = list_entry(p, esm_memory_t, list);
1393 if (buf->empty && buf->buf.bytes > max_size)
1394 max_size = buf->buf.bytes;
1396 up(&chip->memory_mutex);
1397 if (max_size >= 128*1024)
1398 max_size = 127*1024;
1402 /* allocate a new memory chunk with the specified size */
1403 static esm_memory_t *snd_es1968_new_memory(es1968_t *chip, int size)
1406 struct list_head *p;
1408 size = ((size + ESM_MEM_ALIGN - 1) / ESM_MEM_ALIGN) * ESM_MEM_ALIGN;
1409 down(&chip->memory_mutex);
1410 list_for_each(p, &chip->buf_list) {
1411 buf = list_entry(p, esm_memory_t, list);
1412 if (buf->empty && buf->buf.bytes >= size)
1415 up(&chip->memory_mutex);
1419 if (buf->buf.bytes > size) {
1420 esm_memory_t *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1421 if (chunk == NULL) {
1422 up(&chip->memory_mutex);
1425 chunk->buf = buf->buf;
1426 chunk->buf.bytes -= size;
1427 chunk->buf.area += size;
1428 chunk->buf.addr += size;
1430 buf->buf.bytes = size;
1431 list_add(&chunk->list, &buf->list);
1434 up(&chip->memory_mutex);
1438 /* free a memory chunk */
1439 static void snd_es1968_free_memory(es1968_t *chip, esm_memory_t *buf)
1441 esm_memory_t *chunk;
1443 down(&chip->memory_mutex);
1445 if (buf->list.prev != &chip->buf_list) {
1446 chunk = list_entry(buf->list.prev, esm_memory_t, list);
1448 chunk->buf.bytes += buf->buf.bytes;
1449 list_del(&buf->list);
1454 if (buf->list.next != &chip->buf_list) {
1455 chunk = list_entry(buf->list.next, esm_memory_t, list);
1457 buf->buf.bytes += chunk->buf.bytes;
1458 list_del(&chunk->list);
1462 up(&chip->memory_mutex);
1465 static void snd_es1968_free_dmabuf(es1968_t *chip)
1467 struct list_head *p;
1469 if (! chip->dma.area)
1471 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1472 while ((p = chip->buf_list.next) != &chip->buf_list) {
1473 esm_memory_t *chunk = list_entry(p, esm_memory_t, list);
1479 static int __devinit
1480 snd_es1968_init_dmabuf(es1968_t *chip)
1483 esm_memory_t *chunk;
1485 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1486 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1487 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1488 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1489 snd_dma_pci_data(chip->pci),
1490 chip->total_bufsize, &chip->dma);
1491 if (err < 0 || ! chip->dma.area) {
1492 snd_printk("es1968: can't allocate dma pages for size %d\n",
1493 chip->total_bufsize);
1496 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1497 snd_dma_free_pages(&chip->dma);
1498 snd_printk("es1968: DMA buffer beyond 256MB.\n");
1503 INIT_LIST_HEAD(&chip->buf_list);
1504 /* allocate an empty chunk */
1505 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1506 if (chunk == NULL) {
1507 snd_es1968_free_dmabuf(chip);
1510 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1511 chunk->buf = chip->dma;
1512 chunk->buf.area += ESM_MEM_ALIGN;
1513 chunk->buf.addr += ESM_MEM_ALIGN;
1514 chunk->buf.bytes -= ESM_MEM_ALIGN;
1516 list_add(&chunk->list, &chip->buf_list);
1521 /* setup the dma_areas */
1522 /* buffer is extracted from the pre-allocated memory chunk */
1523 static int snd_es1968_hw_params(snd_pcm_substream_t *substream,
1524 snd_pcm_hw_params_t *hw_params)
1526 es1968_t *chip = snd_pcm_substream_chip(substream);
1527 snd_pcm_runtime_t *runtime = substream->runtime;
1528 esschan_t *chan = runtime->private_data;
1529 int size = params_buffer_bytes(hw_params);
1532 if (chan->memory->buf.bytes >= size) {
1533 runtime->dma_bytes = size;
1536 snd_es1968_free_memory(chip, chan->memory);
1538 chan->memory = snd_es1968_new_memory(chip, size);
1539 if (chan->memory == NULL) {
1540 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1543 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1544 return 1; /* area was changed */
1547 /* remove dma areas if allocated */
1548 static int snd_es1968_hw_free(snd_pcm_substream_t * substream)
1550 es1968_t *chip = snd_pcm_substream_chip(substream);
1551 snd_pcm_runtime_t *runtime = substream->runtime;
1554 if (runtime->private_data == NULL)
1556 chan = runtime->private_data;
1558 snd_es1968_free_memory(chip, chan->memory);
1559 chan->memory = NULL;
1568 static int snd_es1968_alloc_apu_pair(es1968_t *chip, int type)
1572 for (apu = 0; apu < NR_APUS; apu += 2) {
1573 if (chip->apu[apu] == ESM_APU_FREE &&
1574 chip->apu[apu + 1] == ESM_APU_FREE) {
1575 chip->apu[apu] = chip->apu[apu + 1] = type;
1585 static void snd_es1968_free_apu_pair(es1968_t *chip, int apu)
1587 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1595 static int snd_es1968_playback_open(snd_pcm_substream_t *substream)
1597 es1968_t *chip = snd_pcm_substream_chip(substream);
1598 snd_pcm_runtime_t *runtime = substream->runtime;
1603 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1607 es = kcalloc(1, sizeof(*es), GFP_KERNEL);
1609 snd_es1968_free_apu_pair(chip, apu1);
1614 es->apu[1] = apu1 + 1;
1615 es->apu_mode[0] = 0;
1616 es->apu_mode[1] = 0;
1618 es->substream = substream;
1619 es->mode = ESM_MODE_PLAY;
1621 runtime->private_data = es;
1622 runtime->hw = snd_es1968_playback;
1623 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1624 calc_available_memory_size(chip);
1626 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1629 spin_lock_irq(&chip->substream_lock);
1630 list_add(&es->list, &chip->substream_list);
1631 spin_unlock_irq(&chip->substream_lock);
1636 static int snd_es1968_capture_open(snd_pcm_substream_t *substream)
1638 snd_pcm_runtime_t *runtime = substream->runtime;
1639 es1968_t *chip = snd_pcm_substream_chip(substream);
1643 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1646 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1648 snd_es1968_free_apu_pair(chip, apu1);
1652 es = kcalloc(1, sizeof(*es), GFP_KERNEL);
1654 snd_es1968_free_apu_pair(chip, apu1);
1655 snd_es1968_free_apu_pair(chip, apu2);
1660 es->apu[1] = apu1 + 1;
1662 es->apu[3] = apu2 + 1;
1663 es->apu_mode[0] = 0;
1664 es->apu_mode[1] = 0;
1665 es->apu_mode[2] = 0;
1666 es->apu_mode[3] = 0;
1668 es->substream = substream;
1669 es->mode = ESM_MODE_CAPTURE;
1672 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1673 snd_es1968_free_apu_pair(chip, apu1);
1674 snd_es1968_free_apu_pair(chip, apu2);
1678 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1680 runtime->private_data = es;
1681 runtime->hw = snd_es1968_capture;
1682 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1683 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1685 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1688 spin_lock_irq(&chip->substream_lock);
1689 list_add(&es->list, &chip->substream_list);
1690 spin_unlock_irq(&chip->substream_lock);
1695 static int snd_es1968_playback_close(snd_pcm_substream_t * substream)
1697 es1968_t *chip = snd_pcm_substream_chip(substream);
1700 if (substream->runtime->private_data == NULL)
1702 es = substream->runtime->private_data;
1703 spin_lock_irq(&chip->substream_lock);
1704 list_del(&es->list);
1705 spin_unlock_irq(&chip->substream_lock);
1706 snd_es1968_free_apu_pair(chip, es->apu[0]);
1712 static int snd_es1968_capture_close(snd_pcm_substream_t * substream)
1714 es1968_t *chip = snd_pcm_substream_chip(substream);
1717 if (substream->runtime->private_data == NULL)
1719 es = substream->runtime->private_data;
1720 spin_lock_irq(&chip->substream_lock);
1721 list_del(&es->list);
1722 spin_unlock_irq(&chip->substream_lock);
1723 snd_es1968_free_memory(chip, es->mixbuf);
1724 snd_es1968_free_apu_pair(chip, es->apu[0]);
1725 snd_es1968_free_apu_pair(chip, es->apu[2]);
1731 static snd_pcm_ops_t snd_es1968_playback_ops = {
1732 .open = snd_es1968_playback_open,
1733 .close = snd_es1968_playback_close,
1734 .ioctl = snd_pcm_lib_ioctl,
1735 .hw_params = snd_es1968_hw_params,
1736 .hw_free = snd_es1968_hw_free,
1737 .prepare = snd_es1968_pcm_prepare,
1738 .trigger = snd_es1968_pcm_trigger,
1739 .pointer = snd_es1968_pcm_pointer,
1742 static snd_pcm_ops_t snd_es1968_capture_ops = {
1743 .open = snd_es1968_capture_open,
1744 .close = snd_es1968_capture_close,
1745 .ioctl = snd_pcm_lib_ioctl,
1746 .hw_params = snd_es1968_hw_params,
1747 .hw_free = snd_es1968_hw_free,
1748 .prepare = snd_es1968_pcm_prepare,
1749 .trigger = snd_es1968_pcm_trigger,
1750 .pointer = snd_es1968_pcm_pointer,
1757 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1759 static void __devinit es1968_measure_clock(es1968_t *chip)
1762 unsigned int pa, offset, t;
1763 esm_memory_t *memory;
1764 struct timeval start_time, stop_time;
1766 if (chip->clock == 0)
1767 chip->clock = 48000; /* default clock value */
1769 /* search 2 APUs (although one apu is enough) */
1770 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1771 snd_printk("Hmm, cannot find empty APU pair!?\n");
1774 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1775 snd_printk("cannot allocate dma buffer - using default clock %d\n", chip->clock);
1776 snd_es1968_free_apu_pair(chip, apu);
1780 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1782 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1784 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1785 pa |= 0x00400000; /* System RAM (Bit 22) */
1787 /* initialize apu */
1788 for (i = 0; i < 16; i++)
1789 apu_set_register(chip, apu, i, 0x0000);
1791 apu_set_register(chip, apu, 0, 0x400f);
1792 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1793 apu_set_register(chip, apu, 5, pa & 0xffff);
1794 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1795 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1796 apu_set_register(chip, apu, 8, 0x0000);
1797 apu_set_register(chip, apu, 9, 0xD000);
1798 apu_set_register(chip, apu, 10, 0x8F08);
1799 apu_set_register(chip, apu, 11, 0x0000);
1800 spin_lock_irq(&chip->reg_lock);
1801 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1802 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1803 spin_unlock_irq(&chip->reg_lock);
1805 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1807 spin_lock_irq(&chip->reg_lock);
1808 __apu_set_register(chip, apu, 5, pa & 0xffff);
1809 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1810 do_gettimeofday(&start_time);
1811 spin_unlock_irq(&chip->reg_lock);
1813 set_current_state(TASK_UNINTERRUPTIBLE);
1814 schedule_timeout(HZ / 20); /* 50 msec */
1817 * schedule() above may be too inaccurate and the pointer can
1818 * overlap the boundary..
1822 spin_lock_irq(&chip->reg_lock);
1823 offset = __apu_get_register(chip, apu, 5);
1824 do_gettimeofday(&stop_time);
1825 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1826 spin_unlock_irq(&chip->reg_lock);
1828 /* check the current position */
1829 offset -= (pa & 0xffff);
1832 t = stop_time.tv_sec - start_time.tv_sec;
1834 if (stop_time.tv_usec < start_time.tv_usec)
1835 t -= start_time.tv_usec - stop_time.tv_usec;
1837 t += stop_time.tv_usec - start_time.tv_usec;
1839 snd_printk("?? calculation error..\n");
1842 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1843 if (offset < 47500 || offset > 48500) {
1844 if (offset >= 40000 && offset <= 50000)
1845 chip->clock = (chip->clock * offset) / 48000;
1847 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1849 snd_es1968_free_memory(chip, memory);
1850 snd_es1968_free_apu_pair(chip, apu);
1857 static void snd_es1968_pcm_free(snd_pcm_t *pcm)
1859 es1968_t *esm = pcm->private_data;
1860 snd_es1968_free_dmabuf(esm);
1864 static int __devinit
1865 snd_es1968_pcm(es1968_t *chip, int device)
1870 /* get DMA buffer */
1871 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1875 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1876 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1877 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1878 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1880 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1881 chip->playback_streams,
1882 chip->capture_streams, &pcm)) < 0)
1885 pcm->private_data = chip;
1886 pcm->private_free = snd_es1968_pcm_free;
1888 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1889 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1891 pcm->info_flags = 0;
1893 strcpy(pcm->name, "ESS Maestro");
1903 static void snd_es1968_update_pcm(es1968_t *chip, esschan_t *es)
1907 snd_pcm_substream_t *subs = es->substream;
1909 if (subs == NULL || !es->running)
1912 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1913 hwptr %= es->dma_size;
1915 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1920 if (es->count > es->frag_size) {
1921 spin_unlock(&chip->substream_lock);
1922 snd_pcm_period_elapsed(subs);
1923 spin_lock(&chip->substream_lock);
1924 es->count %= es->frag_size;
1930 static void es1968_update_hw_volume(unsigned long private_data)
1932 es1968_t *chip = (es1968_t *) private_data;
1935 /* Figure out which volume control button was pushed,
1936 based on differences from the default register
1938 x = inb(chip->io_port + 0x1c);
1939 /* Reset the volume control registers. */
1940 outb(0x88, chip->io_port + 0x1c);
1941 outb(0x88, chip->io_port + 0x1d);
1942 outb(0x88, chip->io_port + 0x1e);
1943 outb(0x88, chip->io_port + 0x1f);
1945 if (! chip->master_switch || ! chip->master_volume)
1948 /* FIXME: more clean up is needed.. */
1949 val = chip->ac97->regs[AC97_MASTER];
1952 snd_ac97_write_cache(chip->ac97, AC97_MASTER, val ^ 0x8000);
1953 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1954 &chip->master_switch->id);
1957 if (((x>>1) & 7) > 4) {
1959 if ((val & 0xff) > 0)
1961 if ((val & 0xff00) > 0)
1965 if ((val & 0xff) < 0x1f)
1967 if ((val & 0xff00) < 0x1f00)
1970 snd_ac97_write_cache(chip->ac97, AC97_MASTER, val);
1971 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1972 &chip->master_volume->id);
1979 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1981 es1968_t *chip = dev_id;
1984 if (!(event = inb(chip->io_port + 0x1A)))
1987 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1989 if (event & ESM_HWVOL_IRQ)
1990 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1992 /* else ack 'em all, i imagine */
1993 outb(0xFF, chip->io_port + 0x1A);
1995 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1996 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1999 if (event & ESM_SOUND_IRQ) {
2000 struct list_head *p;
2001 spin_lock(&chip->substream_lock);
2002 list_for_each(p, &chip->substream_list) {
2003 esschan_t *es = list_entry(p, esschan_t, list);
2005 snd_es1968_update_pcm(chip, es);
2007 spin_unlock(&chip->substream_lock);
2017 static int __devinit
2018 snd_es1968_mixer(es1968_t *chip)
2021 ac97_template_t ac97;
2022 snd_ctl_elem_id_t id;
2024 static ac97_bus_ops_t ops = {
2025 .write = snd_es1968_ac97_write,
2026 .read = snd_es1968_ac97_read,
2029 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2032 memset(&ac97, 0, sizeof(ac97));
2033 ac97.private_data = chip;
2034 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2037 /* attach master switch / volumes for h/w volume control */
2038 memset(&id, 0, sizeof(id));
2039 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2040 strcpy(id.name, "Master Playback Switch");
2041 chip->master_switch = snd_ctl_find_id(chip->card, &id);
2042 memset(&id, 0, sizeof(id));
2043 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2044 strcpy(id.name, "Master Playback Volume");
2045 chip->master_volume = snd_ctl_find_id(chip->card, &id);
2054 static void snd_es1968_ac97_reset(es1968_t *chip)
2056 unsigned long ioaddr = chip->io_port;
2058 unsigned short save_ringbus_a;
2059 unsigned short save_68;
2063 /* save configuration */
2064 save_ringbus_a = inw(ioaddr + 0x36);
2066 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2067 /* set command/status address i/o to 1st codec */
2068 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2069 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2071 /* disable ac link */
2072 outw(0x0000, ioaddr + 0x36);
2073 save_68 = inw(ioaddr + 0x68);
2074 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2075 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2078 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2079 outw(0x0001, ioaddr + 0x68); /* gpio write */
2080 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2082 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2085 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2086 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2087 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2088 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2090 /* now the second codec */
2091 /* disable ac link */
2092 outw(0x0000, ioaddr + 0x36);
2093 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2094 save_68 = inw(ioaddr + 0x68);
2095 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2096 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2098 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2100 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2101 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2102 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2104 #if 0 /* the loop here needs to be much better if we want it.. */
2105 snd_printk("trying software reset\n");
2106 /* try and do a software reset */
2107 outb(0x80 | 0x7c, ioaddr + 0x30);
2109 if ((inw(ioaddr + 0x30) & 1) == 0) {
2110 if (inb(ioaddr + 0x32) != 0)
2113 outb(0x80 | 0x7d, ioaddr + 0x30);
2114 if (((inw(ioaddr + 0x30) & 1) == 0)
2115 && (inb(ioaddr + 0x32) != 0))
2117 outb(0x80 | 0x7f, ioaddr + 0x30);
2118 if (((inw(ioaddr + 0x30) & 1) == 0)
2119 && (inb(ioaddr + 0x32) != 0))
2124 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2125 big_mdelay(500); /* oh my.. */
2126 outb(inb(ioaddr + 0x37) & ~0x08,
2129 outw(0x80, ioaddr + 0x30);
2130 for (w = 0; w < 10000; w++) {
2131 if ((inw(ioaddr + 0x30) & 1) == 0)
2137 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2138 /* turn on external amp? */
2139 outw(0xf9ff, ioaddr + 0x64);
2140 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2141 outw(0x0209, ioaddr + 0x60);
2145 outw(save_ringbus_a, ioaddr + 0x36);
2147 /* Turn on the 978 docking chip.
2148 First frob the "master output enable" bit,
2149 then set most of the playback volume control registers to max. */
2150 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2151 outb(0xff, ioaddr+0xc3);
2152 outb(0xff, ioaddr+0xc4);
2153 outb(0xff, ioaddr+0xc6);
2154 outb(0xff, ioaddr+0xc8);
2155 outb(0x3f, ioaddr+0xcf);
2156 outb(0x3f, ioaddr+0xd0);
2159 static void snd_es1968_reset(es1968_t *chip)
2162 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2163 chip->io_port + ESM_PORT_HOST_IRQ);
2165 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2172 static void snd_es1968_set_acpi(es1968_t *chip, int state)
2174 u16 active_mask = acpi_state_mask[state];
2176 pci_set_power_state(chip->pci, state);
2177 /* make sure the units we care about are on
2178 XXX we might want to do this before state flipping? */
2179 pci_write_config_word(chip->pci, 0x54, ~ active_mask);
2180 pci_write_config_word(chip->pci, 0x56, ~ active_mask);
2185 * initialize maestro chip
2187 static void snd_es1968_chip_init(es1968_t *chip)
2189 struct pci_dev *pci = chip->pci;
2191 unsigned long iobase = chip->io_port;
2195 /* We used to muck around with pci config space that
2196 * we had no business messing with. We don't know enough
2197 * about the machine to know which DMA mode is appropriate,
2198 * etc. We were guessing wrong on some machines and making
2199 * them unhappy. We now trust in the BIOS to do things right,
2200 * which almost certainly means a new host of problems will
2201 * arise with broken BIOS implementations. screw 'em.
2202 * We're already intolerant of machines that don't assign
2206 /* do config work at full power */
2207 snd_es1968_set_acpi(chip, ACPI_D0);
2210 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2212 /* Use TDMA for now. TDMA works on all boards, so while its
2213 * not the most efficient its the simplest. */
2214 w &= ~DMA_CLEAR; /* Clear DMA bits */
2215 w |= DMA_TDMA; /* TDMA on */
2216 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2217 w &= ~SAFEGUARD; /* Safeguard off */
2218 w |= POST_WRITE; /* Posted write */
2219 w |= ISA_TIMING; /* ISA timing on */
2220 /* XXX huh? claims to be reserved.. */
2221 w &= ~SWAP_LR; /* swap left/right
2222 seems to only have effect on SB
2224 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2226 pci_write_config_word(pci, ESM_CONFIG_A, w);
2230 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2232 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2233 /* XXX how do we know which to use? */
2234 w &= ~(1 << 14); /* External clock */
2236 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2237 w |= HWV_CONFB; /* HWV on */
2238 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2239 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2240 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2241 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2242 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2243 w &= ~(1 << 1); /* reserved, always write 0 */
2244 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2246 pci_write_config_word(pci, ESM_CONFIG_B, w);
2250 pci_read_config_word(pci, ESM_DDMA, &w);
2252 pci_write_config_word(pci, ESM_DDMA, w);
2258 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2260 w &= ~ESS_ENABLE_AUDIO; /* Disable Legacy Audio */
2261 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2262 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2264 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2266 /* Set up 978 docking control chip. */
2267 pci_read_config_word(pci, 0x58, &w);
2268 w|=1<<2; /* Enable 978. */
2269 w|=1<<3; /* Turn on 978 hardware volume control. */
2270 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2271 pci_write_config_word(pci, 0x58, w);
2275 snd_es1968_reset(chip);
2281 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2282 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2284 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2291 snd_es1968_ac97_reset(chip);
2293 /* Ring Bus Control B */
2295 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2296 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2297 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2298 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2300 /* Set hardware volume control registers to midpoints.
2301 We can tell which button was pushed based on how they change. */
2302 outb(0x88, iobase+0x1c);
2303 outb(0x88, iobase+0x1d);
2304 outb(0x88, iobase+0x1e);
2305 outb(0x88, iobase+0x1f);
2307 /* it appears some maestros (dell 7500) only work if these are set,
2308 regardless of wether we use the assp or not. */
2310 outb(0, iobase + ASSP_CONTROL_B);
2311 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2312 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2317 for (i = 0; i < 16; i++) {
2318 /* Write 0 into the buffer area 0x1E0->1EF */
2319 outw(0x01E0 + i, iobase + WC_INDEX);
2320 outw(0x0000, iobase + WC_DATA);
2322 /* The 1.10 test program seem to write 0 into the buffer area
2323 * 0x1D0-0x1DF too.*/
2324 outw(0x01D0 + i, iobase + WC_INDEX);
2325 outw(0x0000, iobase + WC_DATA);
2327 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2328 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2329 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2330 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2331 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2332 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2333 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2334 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2337 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2338 /* Now back to the DirectSound stuff */
2339 /* audio serial configuration.. ? */
2340 maestro_write(chip, 0x08, 0xB004);
2341 maestro_write(chip, 0x09, 0x001B);
2342 maestro_write(chip, 0x0A, 0x8000);
2343 maestro_write(chip, 0x0B, 0x3F37);
2344 maestro_write(chip, 0x0C, 0x0098);
2346 /* parallel in, has something to do with recording :) */
2347 maestro_write(chip, 0x0C,
2348 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2350 maestro_write(chip, 0x0C,
2351 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2353 maestro_write(chip, 0x0D, 0x7632);
2355 /* Wave cache control on - test off, sg off,
2356 enable, enable extra chans 1Mb */
2358 w = inw(iobase + WC_CONTROL);
2360 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2361 w |= 0xA000; /* reserved... I don't know */
2362 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2363 Seems to crash the Computer if enabled... */
2364 w |= 0x0100; /* Wave Cache Operation Enabled */
2365 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2366 w &= ~0x0060; /* Clear Wavtable Size */
2367 w |= 0x0020; /* Wavetable Size : 1MB */
2368 /* Bit 4 is reserved */
2369 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2370 /* Bit 1 is reserved */
2371 w &= ~0x0001; /* Test Mode off */
2373 outw(w, iobase + WC_CONTROL);
2375 /* Now clear the APU control ram */
2376 for (i = 0; i < NR_APUS; i++) {
2377 for (w = 0; w < NR_APU_REGS; w++)
2378 apu_set_register(chip, i, w, 0);
2384 static void snd_es1968_start_irq(es1968_t *chip)
2387 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2389 w |= ESM_HIRQ_MPU401;
2390 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2397 static int es1968_suspend(snd_card_t *card, unsigned int state)
2399 es1968_t *chip = card->pm_private_data;
2404 snd_pcm_suspend_all(chip->pcm);
2405 snd_ac97_suspend(chip->ac97);
2406 snd_es1968_bob_stop(chip);
2407 snd_es1968_set_acpi(chip, ACPI_D3);
2408 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2412 static int es1968_resume(snd_card_t *card, unsigned int state)
2414 es1968_t *chip = card->pm_private_data;
2419 /* restore all our config */
2420 pci_enable_device(chip->pci);
2421 snd_es1968_chip_init(chip);
2423 /* need to restore the base pointers.. */
2424 if (chip->dma.addr) {
2426 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2429 snd_es1968_start_irq(chip);
2431 /* restore ac97 state */
2432 snd_ac97_resume(chip->ac97);
2434 /* start timer again */
2435 if (chip->bobclient)
2436 snd_es1968_bob_start(chip);
2438 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2441 #endif /* CONFIG_PM */
2443 static int snd_es1968_free(es1968_t *chip)
2445 if (chip->io_port) {
2446 synchronize_irq(chip->irq);
2447 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2448 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2452 free_irq(chip->irq, (void *)chip);
2453 #ifdef SUPPORT_JOYSTICK
2454 if (chip->res_joystick) {
2455 gameport_unregister_port(&chip->gameport);
2456 release_resource(chip->res_joystick);
2457 kfree_nocheck(chip->res_joystick);
2460 snd_es1968_set_acpi(chip, ACPI_D3);
2461 chip->master_switch = NULL;
2462 chip->master_volume = NULL;
2463 pci_release_regions(chip->pci);
2468 static int snd_es1968_dev_free(snd_device_t *device)
2470 es1968_t *chip = device->device_data;
2471 return snd_es1968_free(chip);
2474 struct ess_device_list {
2475 unsigned short type; /* chip type */
2476 unsigned short vendor; /* subsystem vendor id */
2479 static struct ess_device_list pm_whitelist[] __devinitdata = {
2480 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2481 { TYPE_MAESTRO2E, 0x1028 },
2482 { TYPE_MAESTRO2E, 0x103c },
2483 { TYPE_MAESTRO2E, 0x1179 },
2484 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2487 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2488 { TYPE_MAESTRO2, 0x125d },
2491 static int __devinit snd_es1968_create(snd_card_t * card,
2492 struct pci_dev *pci,
2498 es1968_t **chip_ret)
2500 static snd_device_ops_t ops = {
2501 .dev_free = snd_es1968_dev_free,
2508 /* enable PCI device */
2509 if ((err = pci_enable_device(pci)) < 0)
2511 /* check, if we can restrict PCI DMA transfers to 28 bits */
2512 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2513 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2514 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2518 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2523 chip->type = chip_type;
2524 spin_lock_init(&chip->reg_lock);
2525 spin_lock_init(&chip->substream_lock);
2526 INIT_LIST_HEAD(&chip->buf_list);
2527 INIT_LIST_HEAD(&chip->substream_list);
2528 init_MUTEX(&chip->memory_mutex);
2529 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2533 chip->total_bufsize = total_bufsize; /* in bytes */
2534 chip->playback_streams = play_streams;
2535 chip->capture_streams = capt_streams;
2537 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2541 chip->io_port = pci_resource_start(pci, 0);
2542 if (request_irq(pci->irq, snd_es1968_interrupt, SA_INTERRUPT|SA_SHIRQ,
2543 "ESS Maestro", (void*)chip)) {
2544 snd_printk("unable to grab IRQ %d\n", pci->irq);
2545 snd_es1968_free(chip);
2548 chip->irq = pci->irq;
2550 /* Clear Maestro_map */
2551 for (i = 0; i < 32; i++)
2552 chip->maestro_map[i] = 0;
2555 for (i = 0; i < NR_APUS; i++)
2556 chip->apu[i] = ESM_APU_FREE;
2558 /* just to be sure */
2559 pci_set_master(pci);
2562 /* disable power-management if not on the whitelist */
2563 unsigned short vend;
2564 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2565 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2566 if (chip->type == pm_whitelist[i].type &&
2567 vend == pm_whitelist[i].vendor) {
2573 /* not matched; disabling pm */
2574 printk(KERN_INFO "es1968: not attempting power management.\n");
2578 chip->do_pm = do_pm;
2580 snd_es1968_chip_init(chip);
2583 snd_card_set_pm_callback(card, es1968_suspend, es1968_resume, chip);
2585 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2586 snd_es1968_free(chip);
2590 snd_card_set_dev(card, &pci->dev);
2600 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2601 const struct pci_device_id *pci_id)
2609 if (dev >= SNDRV_CARDS)
2616 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2620 if (total_bufsize[dev] < 128)
2621 total_bufsize[dev] = 128;
2622 if (total_bufsize[dev] > 4096)
2623 total_bufsize[dev] = 4096;
2624 if ((err = snd_es1968_create(card, pci,
2625 total_bufsize[dev] * 1024, /* in bytes */
2626 pcm_substreams_p[dev],
2627 pcm_substreams_c[dev],
2628 pci_id->driver_data,
2631 snd_card_free(card);
2635 switch (chip->type) {
2636 case TYPE_MAESTRO2E:
2637 strcpy(card->driver, "ES1978");
2638 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2641 strcpy(card->driver, "ES1968");
2642 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2645 strcpy(card->driver, "ESM1");
2646 strcpy(card->shortname, "ESS Maestro 1");
2650 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2651 snd_card_free(card);
2655 if ((err = snd_es1968_mixer(chip)) < 0) {
2656 snd_card_free(card);
2660 if (enable_mpu[dev] == 2) {
2661 /* check the black list */
2662 unsigned short vend;
2663 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2664 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2665 if (chip->type == mpu_blacklist[i].type &&
2666 vend == mpu_blacklist[i].vendor) {
2667 enable_mpu[dev] = 0;
2672 if (enable_mpu[dev]) {
2673 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2674 chip->io_port + ESM_MPU401_PORT, 1,
2675 chip->irq, 0, &chip->rmidi)) < 0) {
2676 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2680 #ifdef SUPPORT_JOYSTICK
2681 #define JOYSTICK_ADDR 0x200
2682 if (joystick[dev] &&
2683 (chip->res_joystick = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport")) != NULL) {
2685 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2686 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2687 chip->gameport.io = JOYSTICK_ADDR;
2688 gameport_register_port(&chip->gameport);
2692 snd_es1968_start_irq(chip);
2694 chip->clock = clock[dev];
2696 es1968_measure_clock(chip);
2698 sprintf(card->longname, "%s at 0x%lx, irq %i",
2699 card->shortname, chip->io_port, chip->irq);
2701 if ((err = snd_card_register(card)) < 0) {
2702 snd_card_free(card);
2705 pci_set_drvdata(pci, card);
2710 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2712 snd_card_free(pci_get_drvdata(pci));
2713 pci_set_drvdata(pci, NULL);
2716 static struct pci_driver driver = {
2717 .name = "ES1968 (ESS Maestro)",
2718 .id_table = snd_es1968_ids,
2719 .probe = snd_es1968_probe,
2720 .remove = __devexit_p(snd_es1968_remove),
2721 SND_PCI_PM_CALLBACKS
2724 static int __init alsa_card_es1968_init(void)
2726 return pci_module_init(&driver);
2729 static void __exit alsa_card_es1968_exit(void)
2731 pci_unregister_driver(&driver);
2734 module_init(alsa_card_es1968_init)
2735 module_exit(alsa_card_es1968_exit)