sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along with
  21  *  this program; if not, write to the Free Software Foundation, Inc., 59
  22  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23  *
  24  *  CONTACTS:
  25  *
  26  *  Matt Jared          matt.jared@intel.com
  27  *  Andy Kopp           andy.kopp@intel.com
  28  *  Dan Kogan           dan.d.kogan@intel.com
  29  *
  30  *  CHANGES:
  31  *
  32  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  33  *
  34  */
  35
  36 #include <sound/driver.h>
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/init.h>
  43 #include <linux/slab.h>
  44 #include <linux/pci.h>
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include "hda_codec.h"
  48
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  53 static char *model[SNDRV_CARDS];
  54
  55 module_param_array(index, int, NULL, 0444);
  56 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  57 module_param_array(id, charp, NULL, 0444);
  58 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  59 module_param_array(enable, bool, NULL, 0444);
  60 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  61 module_param_array(model, charp, NULL, 0444);
  62 MODULE_PARM_DESC(model, "Use the given board model.");
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  66                          "{Intel, ICH6M},"
  67                          "{Intel, ICH7},"
  68                          "{Intel, ESB2}}");
  69 MODULE_DESCRIPTION("Intel HDA driver");
  70
  71 #define SFX     "hda-intel: "
  72
  73 /*
  74  * registers
  75  */
  76 #define ICH6_REG_GCAP                   0x00
  77 #define ICH6_REG_VMIN                   0x02
  78 #define ICH6_REG_VMAJ                   0x03
  79 #define ICH6_REG_OUTPAY                 0x04
  80 #define ICH6_REG_INPAY                  0x06
  81 #define ICH6_REG_GCTL                   0x08
  82 #define ICH6_REG_WAKEEN                 0x0c
  83 #define ICH6_REG_STATESTS               0x0e
  84 #define ICH6_REG_GSTS                   0x10
  85 #define ICH6_REG_INTCTL                 0x20
  86 #define ICH6_REG_INTSTS                 0x24
  87 #define ICH6_REG_WALCLK                 0x30
  88 #define ICH6_REG_SYNC                   0x34
  89 #define ICH6_REG_CORBLBASE              0x40
  90 #define ICH6_REG_CORBUBASE              0x44
  91 #define ICH6_REG_CORBWP                 0x48
  92 #define ICH6_REG_CORBRP                 0x4A
  93 #define ICH6_REG_CORBCTL                0x4c
  94 #define ICH6_REG_CORBSTS                0x4d
  95 #define ICH6_REG_CORBSIZE               0x4e
  96
  97 #define ICH6_REG_RIRBLBASE              0x50
  98 #define ICH6_REG_RIRBUBASE              0x54
  99 #define ICH6_REG_RIRBWP                 0x58
 100 #define ICH6_REG_RINTCNT                0x5a
 101 #define ICH6_REG_RIRBCTL                0x5c
 102 #define ICH6_REG_RIRBSTS                0x5d
 103 #define ICH6_REG_RIRBSIZE               0x5e
 104
 105 #define ICH6_REG_IC                     0x60
 106 #define ICH6_REG_IR                     0x64
 107 #define ICH6_REG_IRS                    0x68
 108 #define   ICH6_IRS_VALID        (1<<1)
 109 #define   ICH6_IRS_BUSY         (1<<0)
 110
 111 #define ICH6_REG_DPLBASE                0x70
 112 #define ICH6_REG_DPUBASE                0x74
 113 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 114
 115 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 116 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 117
 118 /* stream register offsets from stream base */
 119 #define ICH6_REG_SD_CTL                 0x00
 120 #define ICH6_REG_SD_STS                 0x03
 121 #define ICH6_REG_SD_LPIB                0x04
 122 #define ICH6_REG_SD_CBL                 0x08
 123 #define ICH6_REG_SD_LVI                 0x0c
 124 #define ICH6_REG_SD_FIFOW               0x0e
 125 #define ICH6_REG_SD_FIFOSIZE            0x10
 126 #define ICH6_REG_SD_FORMAT              0x12
 127 #define ICH6_REG_SD_BDLPL               0x18
 128 #define ICH6_REG_SD_BDLPU               0x1c
 129
 130 /* PCI space */
 131 #define ICH6_PCIREG_TCSEL       0x44
 132
 133 /*
 134  * other constants
 135  */
 136
 137 /* max number of SDs */
 138 #define MAX_ICH6_DEV            8
 139 /* max number of fragments - we may use more if allocating more pages for BDL */
 140 #define AZX_MAX_FRAG            (PAGE_SIZE / (MAX_ICH6_DEV * 16))
 141 /* max buffer size - no h/w limit, you can increase as you like */
 142 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 143 /* max number of PCM devics per card */
 144 #define AZX_MAX_PCMS            8
 145
 146 /* RIRB int mask: overrun[2], response[0] */
 147 #define RIRB_INT_RESPONSE       0x01
 148 #define RIRB_INT_OVERRUN        0x04
 149 #define RIRB_INT_MASK           0x05
 150
 151 /* STATESTS int mask: SD2,SD1,SD0 */
 152 #define STATESTS_INT_MASK       0x07
 153 #define AZX_MAX_CODECS          3
 154
 155 /* SD_CTL bits */
 156 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 157 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 158 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 159 #define SD_CTL_STREAM_TAG_SHIFT 20
 160
 161 /* SD_CTL and SD_STS */
 162 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 163 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 164 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 165 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
 166
 167 /* SD_STS */
 168 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 169
 170 /* INTCTL and INTSTS */
 171 #define ICH6_INT_ALL_STREAM     0xff            /* all stream interrupts */
 172 #define ICH6_INT_CTRL_EN        0x40000000      /* controller interrupt enable bit */
 173 #define ICH6_INT_GLOBAL_EN      0x80000000      /* global interrupt enable bit */
 174
 175 /* GCTL reset bit */
 176 #define ICH6_GCTL_RESET         (1<<0)
 177
 178 /* CORB/RIRB control, read/write pointer */
 179 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 180 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 181 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 182 /* below are so far hardcoded - should read registers in future */
 183 #define ICH6_MAX_CORB_ENTRIES   256
 184 #define ICH6_MAX_RIRB_ENTRIES   256
 185
 186
 187 /*
 188  * Use CORB/RIRB for communication from/to codecs.
 189  * This is the way recommended by Intel (see below).
 190  */
 191 #define USE_CORB_RIRB
 192
 193 /*
 194  * Define this if use the position buffer instead of reading SD_LPIB
 195  * It's not used as default since SD_LPIB seems to give more accurate position
 196  */
 197 /* #define USE_POSBUF */
 198
 199 /*
 200  */
 201
 202 typedef struct snd_azx azx_t;
 203 typedef struct snd_azx_rb azx_rb_t;
 204 typedef struct snd_azx_dev azx_dev_t;
 205
 206 struct snd_azx_dev {
 207         u32 *bdl;                       /* virtual address of the BDL */
 208         dma_addr_t bdl_addr;            /* physical address of the BDL */
 209         volatile u32 *posbuf;                   /* position buffer pointer */
 210
 211         unsigned int bufsize;           /* size of the play buffer in bytes */
 212         unsigned int fragsize;          /* size of each period in bytes */
 213         unsigned int frags;             /* number for period in the play buffer */
 214         unsigned int fifo_size;         /* FIFO size */
 215
 216         void __iomem *sd_addr;          /* stream descriptor pointer */
 217
 218         u32 sd_int_sta_mask;            /* stream int status mask */
 219
 220         /* pcm support */
 221         snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
 222         unsigned int format_val;        /* format value to be set in the controller and the codec */
 223         unsigned char stream_tag;       /* assigned stream */
 224         unsigned char index;            /* stream index */
 225
 226         unsigned int opened: 1;
 227         unsigned int running: 1;
 228 };
 229
 230 /* CORB/RIRB */
 231 struct snd_azx_rb {
 232         u32 *buf;               /* CORB/RIRB buffer
 233                                  * Each CORB entry is 4byte, RIRB is 8byte
 234                                  */
 235         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 236         /* for RIRB */
 237         unsigned short rp, wp;  /* read/write pointers */
 238         int cmds;               /* number of pending requests */
 239         u32 res;                /* last read value */
 240 };
 241
 242 struct snd_azx {
 243         snd_card_t *card;
 244         struct pci_dev *pci;
 245
 246         /* pci resources */
 247         unsigned long addr;
 248         void __iomem *remap_addr;
 249         int irq;
 250
 251         /* locks */
 252         spinlock_t reg_lock;
 253         struct semaphore open_mutex;
 254
 255         /* streams */
 256         azx_dev_t azx_dev[MAX_ICH6_DEV];
 257
 258         /* PCM */
 259         unsigned int pcm_devs;
 260         snd_pcm_t *pcm[AZX_MAX_PCMS];
 261
 262         /* HD codec */
 263         unsigned short codec_mask;
 264         struct hda_bus *bus;
 265
 266         /* CORB/RIRB */
 267         azx_rb_t corb;
 268         azx_rb_t rirb;
 269
 270         /* BDL, CORB/RIRB and position buffers */
 271         struct snd_dma_buffer bdl;
 272         struct snd_dma_buffer rb;
 273         struct snd_dma_buffer posbuf;
 274 };
 275
 276 /*
 277  * macros for easy use
 278  */
 279 #define azx_writel(chip,reg,value) \
 280         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 281 #define azx_readl(chip,reg) \
 282         readl((chip)->remap_addr + ICH6_REG_##reg)
 283 #define azx_writew(chip,reg,value) \
 284         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 285 #define azx_readw(chip,reg) \
 286         readw((chip)->remap_addr + ICH6_REG_##reg)
 287 #define azx_writeb(chip,reg,value) \
 288         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 289 #define azx_readb(chip,reg) \
 290         readb((chip)->remap_addr + ICH6_REG_##reg)
 291
 292 #define azx_sd_writel(dev,reg,value) \
 293         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 294 #define azx_sd_readl(dev,reg) \
 295         readl((dev)->sd_addr + ICH6_REG_##reg)
 296 #define azx_sd_writew(dev,reg,value) \
 297         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 298 #define azx_sd_readw(dev,reg) \
 299         readw((dev)->sd_addr + ICH6_REG_##reg)
 300 #define azx_sd_writeb(dev,reg,value) \
 301         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 302 #define azx_sd_readb(dev,reg) \
 303         readb((dev)->sd_addr + ICH6_REG_##reg)
 304
 305 /* for pcm support */
 306 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
 307
 308 /* Get the upper 32bit of the given dma_addr_t
 309  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 310  */
 311 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 312
 313
 314 /*
 315  * Interface for HD codec
 316  */
 317
 318 #ifdef USE_CORB_RIRB
 319 /*
 320  * CORB / RIRB interface
 321  */
 322 static int azx_alloc_cmd_io(azx_t *chip)
 323 {
 324         int err;
 325
 326         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 327         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
 328                                   PAGE_SIZE, &chip->rb);
 329         if (err < 0) {
 330                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 331                 return err;
 332         }
 333         return 0;
 334 }
 335
 336 static void azx_init_cmd_io(azx_t *chip)
 337 {
 338         /* CORB set up */
 339         chip->corb.addr = chip->rb.addr;
 340         chip->corb.buf = (u32 *)chip->rb.area;
 341         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 342         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 343
 344         /* set the corb write pointer to 0 */
 345         azx_writew(chip, CORBWP, 0);
 346         /* reset the corb hw read pointer */
 347         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 348         /* enable corb dma */
 349         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 350
 351         /* RIRB set up */
 352         chip->rirb.addr = chip->rb.addr + 2048;
 353         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 354         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 355         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 356
 357         /* reset the rirb hw write pointer */
 358         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 359         /* set N=1, get RIRB response interrupt for new entry */
 360         azx_writew(chip, RINTCNT, 1);
 361         /* enable rirb dma and response irq */
 362 #ifdef USE_CORB_RIRB
 363         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 364 #else
 365         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
 366 #endif
 367         chip->rirb.rp = chip->rirb.cmds = 0;
 368 }
 369
 370 static void azx_free_cmd_io(azx_t *chip)
 371 {
 372         /* disable ringbuffer DMAs */
 373         azx_writeb(chip, RIRBCTL, 0);
 374         azx_writeb(chip, CORBCTL, 0);
 375 }
 376
 377 /* send a command */
 378 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 379                         unsigned int verb, unsigned int para)
 380 {
 381         azx_t *chip = codec->bus->private_data;
 382         unsigned int wp;
 383         u32 val;
 384
 385         val = (u32)(codec->addr & 0x0f) << 28;
 386         val |= (u32)direct << 27;
 387         val |= (u32)nid << 20;
 388         val |= verb << 8;
 389         val |= para;
 390
 391         /* add command to corb */
 392         wp = azx_readb(chip, CORBWP);
 393         wp++;
 394         wp %= ICH6_MAX_CORB_ENTRIES;
 395
 396         spin_lock_irq(&chip->reg_lock);
 397         chip->rirb.cmds++;
 398         chip->corb.buf[wp] = cpu_to_le32(val);
 399         azx_writel(chip, CORBWP, wp);
 400         spin_unlock_irq(&chip->reg_lock);
 401
 402         return 0;
 403 }
 404
 405 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 406
 407 /* retrieve RIRB entry - called from interrupt handler */
 408 static void azx_update_rirb(azx_t *chip)
 409 {
 410         unsigned int rp, wp;
 411         u32 res, res_ex;
 412
 413         wp = azx_readb(chip, RIRBWP);
 414         if (wp == chip->rirb.wp)
 415                 return;
 416         chip->rirb.wp = wp;
 417
 418         while (chip->rirb.rp != wp) {
 419                 chip->rirb.rp++;
 420                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 421
 422                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 423                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 424                 res = le32_to_cpu(chip->rirb.buf[rp]);
 425                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 426                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 427                 else if (chip->rirb.cmds) {
 428                         chip->rirb.cmds--;
 429                         chip->rirb.res = res;
 430                 }
 431         }
 432 }
 433
 434 /* receive a response */
 435 static unsigned int azx_get_response(struct hda_codec *codec)
 436 {
 437         azx_t *chip = codec->bus->private_data;
 438         int timeout = 50;
 439
 440         while (chip->rirb.cmds) {
 441                 if (! --timeout) {
 442                         snd_printk(KERN_ERR "azx_get_response timeout\n");
 443                         chip->rirb.rp = azx_readb(chip, RIRBWP);
 444                         chip->rirb.cmds = 0;
 445                         return -1;
 446                 }
 447                 msleep(1);
 448         }
 449         return chip->rirb.res; /* the last value */
 450 }
 451
 452 #else
 453 /*
 454  * Use the single immediate command instead of CORB/RIRB for simplicity
 455  *
 456  * Note: according to Intel, this is not preferred use.  The command was
 457  *       intended for the BIOS only, and may get confused with unsolicited
 458  *       responses.  So, we shouldn't use it for normal operation from the
 459  *       driver.
 460  *       I left the codes, however, for debugging/testing purposes.
 461  */
 462
 463 #define azx_alloc_cmd_io(chip)  0
 464 #define azx_init_cmd_io(chip)
 465 #define azx_free_cmd_io(chip)
 466
 467 /* send a command */
 468 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 469                         unsigned int verb, unsigned int para)
 470 {
 471         azx_t *chip = codec->bus->private_data;
 472         u32 val;
 473         int timeout = 50;
 474
 475         val = (u32)(codec->addr & 0x0f) << 28;
 476         val |= (u32)direct << 27;
 477         val |= (u32)nid << 20;
 478         val |= verb << 8;
 479         val |= para;
 480
 481         while (timeout--) {
 482                 /* check ICB busy bit */
 483                 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
 484                         /* Clear IRV valid bit */
 485                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
 486                         azx_writel(chip, IC, val);
 487                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
 488                         return 0;
 489                 }
 490                 udelay(1);
 491         }
 492         snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
 493         return -EIO;
 494 }
 495
 496 /* receive a response */
 497 static unsigned int azx_get_response(struct hda_codec *codec)
 498 {
 499         azx_t *chip = codec->bus->private_data;
 500         int timeout = 50;
 501
 502         while (timeout--) {
 503                 /* check IRV busy bit */
 504                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 505                         return azx_readl(chip, IR);
 506                 udelay(1);
 507         }
 508         snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
 509         return (unsigned int)-1;
 510 }
 511
 512 #define azx_update_rirb(chip)
 513
 514 #endif /* USE_CORB_RIRB */
 515
 516 /* reset codec link */
 517 static int azx_reset(azx_t *chip)
 518 {
 519         int count;
 520
 521         /* reset controller */
 522         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 523
 524         count = 50;
 525         while (azx_readb(chip, GCTL) && --count)
 526                 msleep(1);
 527
 528         /* delay for >= 100us for codec PLL to settle per spec
 529          * Rev 0.9 section 5.5.1
 530          */
 531         msleep(1);
 532
 533         /* Bring controller out of reset */
 534         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 535
 536         count = 50;
 537         while (! azx_readb(chip, GCTL) && --count)
 538                 msleep(1);
 539
 540         /* Brent Chartrand said to wait >= 540us for codecs to intialize */
 541         msleep(1);
 542
 543         /* check to see if controller is ready */
 544         if (! azx_readb(chip, GCTL)) {
 545                 snd_printd("azx_reset: controller not ready!\n");
 546                 return -EBUSY;
 547         }
 548
 549         /* detect codecs */
 550         if (! chip->codec_mask) {
 551                 chip->codec_mask = azx_readw(chip, STATESTS);
 552                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 553         }
 554
 555         return 0;
 556 }
 557
 558
 559 /*
 560  * Lowlevel interface
 561  */
 562
 563 /* enable interrupts */
 564 static void azx_int_enable(azx_t *chip)
 565 {
 566         /* enable controller CIE and GIE */
 567         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 568                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 569 }
 570
 571 /* disable interrupts */
 572 static void azx_int_disable(azx_t *chip)
 573 {
 574         int i;
 575
 576         /* disable interrupts in stream descriptor */
 577         for (i = 0; i < MAX_ICH6_DEV; i++) {
 578                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 579                 azx_sd_writeb(azx_dev, SD_CTL,
 580                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 581         }
 582
 583         /* disable SIE for all streams */
 584         azx_writeb(chip, INTCTL, 0);
 585
 586         /* disable controller CIE and GIE */
 587         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 588                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 589 }
 590
 591 /* clear interrupts */
 592 static void azx_int_clear(azx_t *chip)
 593 {
 594         int i;
 595
 596         /* clear stream status */
 597         for (i = 0; i < MAX_ICH6_DEV; i++) {
 598                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 599                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 600         }
 601
 602         /* clear STATESTS */
 603         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 604
 605         /* clear rirb status */
 606         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 607
 608         /* clear int status */
 609         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 610 }
 611
 612 /* start a stream */
 613 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
 614 {
 615         /* enable SIE */
 616         azx_writeb(chip, INTCTL,
 617                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 618         /* set DMA start and interrupt mask */
 619         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 620                       SD_CTL_DMA_START | SD_INT_MASK);
 621 }
 622
 623 /* stop a stream */
 624 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
 625 {
 626         /* stop DMA */
 627         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 628                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 629         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 630         /* disable SIE */
 631         azx_writeb(chip, INTCTL,
 632                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 633 }
 634
 635
 636 /*
 637  * initialize the chip
 638  */
 639 static void azx_init_chip(azx_t *chip)
 640 {
 641         unsigned char tcsel_reg;
 642
 643         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 644          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 645          * Ensuring these bits are 0 clears playback static on some HD Audio codecs
 646          */
 647         pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
 648         pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
 649
 650         /* reset controller */
 651         azx_reset(chip);
 652
 653         /* initialize interrupts */
 654         azx_int_clear(chip);
 655         azx_int_enable(chip);
 656
 657         /* initialize the codec command I/O */
 658         azx_init_cmd_io(chip);
 659
 660 #ifdef USE_POSBUF
 661         /* program the position buffer */
 662         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 663         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 664 #endif
 665 }
 666
 667
 668 /*
 669  * interrupt handler
 670  */
 671 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
 672 {
 673         azx_t *chip = dev_id;
 674         azx_dev_t *azx_dev;
 675         u32 status;
 676         int i;
 677
 678         spin_lock(&chip->reg_lock);
 679
 680         status = azx_readl(chip, INTSTS);
 681         if (status == 0) {
 682                 spin_unlock(&chip->reg_lock);
 683                 return IRQ_NONE;
 684         }
 685
 686         for (i = 0; i < MAX_ICH6_DEV; i++) {
 687                 azx_dev = &chip->azx_dev[i];
 688                 if (status & azx_dev->sd_int_sta_mask) {
 689                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 690                         if (azx_dev->substream && azx_dev->running) {
 691                                 spin_unlock(&chip->reg_lock);
 692                                 snd_pcm_period_elapsed(azx_dev->substream);
 693                                 spin_lock(&chip->reg_lock);
 694                         }
 695                 }
 696         }
 697
 698         /* clear rirb int */
 699         status = azx_readb(chip, RIRBSTS);
 700         if (status & RIRB_INT_MASK) {
 701                 if (status & RIRB_INT_RESPONSE)
 702                         azx_update_rirb(chip);
 703                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 704         }
 705
 706 #if 0
 707         /* clear state status int */
 708         if (azx_readb(chip, STATESTS) & 0x04)
 709                 azx_writeb(chip, STATESTS, 0x04);
 710 #endif
 711         spin_unlock(&chip->reg_lock);
 712
 713         return IRQ_HANDLED;
 714 }
 715
 716
 717 /*
 718  * set up BDL entries
 719  */
 720 static void azx_setup_periods(azx_dev_t *azx_dev)
 721 {
 722         u32 *bdl = azx_dev->bdl;
 723         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 724         int idx;
 725
 726         /* reset BDL address */
 727         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 728         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 729
 730         /* program the initial BDL entries */
 731         for (idx = 0; idx < azx_dev->frags; idx++) {
 732                 unsigned int off = idx << 2; /* 4 dword step */
 733                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 734                 /* program the address field of the BDL entry */
 735                 bdl[off] = cpu_to_le32((u32)addr);
 736                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 737
 738                 /* program the size field of the BDL entry */
 739                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 740
 741                 /* program the IOC to enable interrupt when buffer completes */
 742                 bdl[off+3] = cpu_to_le32(0x01);
 743         }
 744 }
 745
 746 /*
 747  * set up the SD for streaming
 748  */
 749 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
 750 {
 751         unsigned char val;
 752         int timeout;
 753
 754         /* make sure the run bit is zero for SD */
 755         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 756         /* reset stream */
 757         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 758         udelay(3);
 759         timeout = 300;
 760         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 761                --timeout)
 762                 ;
 763         val &= ~SD_CTL_STREAM_RESET;
 764         azx_sd_writeb(azx_dev, SD_CTL, val);
 765         udelay(3);
 766
 767         timeout = 300;
 768         /* waiting for hardware to report that the stream is out of reset */
 769         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 770                --timeout)
 771                 ;
 772
 773         /* program the stream_tag */
 774         azx_sd_writel(azx_dev, SD_CTL,
 775                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
 776                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
 777
 778         /* program the length of samples in cyclic buffer */
 779         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 780
 781         /* program the stream format */
 782         /* this value needs to be the same as the one programmed */
 783         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 784
 785         /* program the stream LVI (last valid index) of the BDL */
 786         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 787
 788         /* program the BDL address */
 789         /* lower BDL address */
 790         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
 791         /* upper BDL address */
 792         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
 793
 794 #ifdef USE_POSBUF
 795         /* enable the position buffer */
 796         if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
 797                 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
 798 #endif
 799         /* set the interrupt enable bits in the descriptor control register */
 800         azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
 801
 802         return 0;
 803 }
 804
 805
 806 /*
 807  * Codec initialization
 808  */
 809
 810 static int __devinit azx_codec_create(azx_t *chip, const char *model)
 811 {
 812         struct hda_bus_template bus_temp;
 813         int c, codecs, err;
 814
 815         memset(&bus_temp, 0, sizeof(bus_temp));
 816         bus_temp.private_data = chip;
 817         bus_temp.modelname = model;
 818         bus_temp.pci = chip->pci;
 819         bus_temp.ops.command = azx_send_cmd;
 820         bus_temp.ops.get_response = azx_get_response;
 821
 822         if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
 823                 return err;
 824
 825         codecs = 0;
 826         for (c = 0; c < AZX_MAX_CODECS; c++) {
 827                 if (chip->codec_mask & (1 << c)) {
 828                         err = snd_hda_codec_new(chip->bus, c, NULL);
 829                         if (err < 0)
 830                                 continue;
 831                         codecs++;
 832                 }
 833         }
 834         if (! codecs) {
 835                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
 836                 return -ENXIO;
 837         }
 838
 839         return 0;
 840 }
 841
 842
 843 /*
 844  * PCM support
 845  */
 846
 847 /* assign a stream for the PCM */
 848 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
 849 {
 850         int dev, i;
 851         dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
 852         for (i = 0; i < 4; i++, dev++)
 853                 if (! chip->azx_dev[dev].opened) {
 854                         chip->azx_dev[dev].opened = 1;
 855                         return &chip->azx_dev[dev];
 856                 }
 857         return NULL;
 858 }
 859
 860 /* release the assigned stream */
 861 static inline void azx_release_device(azx_dev_t *azx_dev)
 862 {
 863         azx_dev->opened = 0;
 864 }
 865
 866 static snd_pcm_hardware_t azx_pcm_hw = {
 867         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 868                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 869                                  SNDRV_PCM_INFO_MMAP_VALID |
 870                                  SNDRV_PCM_INFO_PAUSE |
 871                                  SNDRV_PCM_INFO_RESUME),
 872         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 873         .rates =                SNDRV_PCM_RATE_48000,
 874         .rate_min =             48000,
 875         .rate_max =             48000,
 876         .channels_min =         2,
 877         .channels_max =         2,
 878         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 879         .period_bytes_min =     128,
 880         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 881         .periods_min =          2,
 882         .periods_max =          AZX_MAX_FRAG,
 883         .fifo_size =            0,
 884 };
 885
 886 struct azx_pcm {
 887         azx_t *chip;
 888         struct hda_codec *codec;
 889         struct hda_pcm_stream *hinfo[2];
 890 };
 891
 892 static int azx_pcm_open(snd_pcm_substream_t *substream)
 893 {
 894         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 895         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 896         azx_t *chip = apcm->chip;
 897         azx_dev_t *azx_dev;
 898         snd_pcm_runtime_t *runtime = substream->runtime;
 899         unsigned long flags;
 900         int err;
 901
 902         down(&chip->open_mutex);
 903         azx_dev = azx_assign_device(chip, substream->stream);
 904         if (azx_dev == NULL) {
 905                 up(&chip->open_mutex);
 906                 return -EBUSY;
 907         }
 908         runtime->hw = azx_pcm_hw;
 909         runtime->hw.channels_min = hinfo->channels_min;
 910         runtime->hw.channels_max = hinfo->channels_max;
 911         runtime->hw.formats = hinfo->formats;
 912         runtime->hw.rates = hinfo->rates;
 913         snd_pcm_limit_hw_rates(runtime);
 914         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 915         if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
 916                 azx_release_device(azx_dev);
 917                 up(&chip->open_mutex);
 918                 return err;
 919         }
 920         spin_lock_irqsave(&chip->reg_lock, flags);
 921         azx_dev->substream = substream;
 922         azx_dev->running = 0;
 923         spin_unlock_irqrestore(&chip->reg_lock, flags);
 924
 925         runtime->private_data = azx_dev;
 926         up(&chip->open_mutex);
 927         return 0;
 928 }
 929
 930 static int azx_pcm_close(snd_pcm_substream_t *substream)
 931 {
 932         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 933         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 934         azx_t *chip = apcm->chip;
 935         azx_dev_t *azx_dev = get_azx_dev(substream);
 936         unsigned long flags;
 937
 938         down(&chip->open_mutex);
 939         spin_lock_irqsave(&chip->reg_lock, flags);
 940         azx_dev->substream = NULL;
 941         azx_dev->running = 0;
 942         spin_unlock_irqrestore(&chip->reg_lock, flags);
 943         azx_release_device(azx_dev);
 944         hinfo->ops.close(hinfo, apcm->codec, substream);
 945         up(&chip->open_mutex);
 946         return 0;
 947 }
 948
 949 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
 950 {
 951         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 952 }
 953
 954 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
 955 {
 956         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 957         azx_dev_t *azx_dev = get_azx_dev(substream);
 958         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 959
 960         /* reset BDL address */
 961         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 962         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 963         azx_sd_writel(azx_dev, SD_CTL, 0);
 964
 965         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
 966
 967         return snd_pcm_lib_free_pages(substream);
 968 }
 969
 970 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
 971 {
 972         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 973         azx_t *chip = apcm->chip;
 974         azx_dev_t *azx_dev = get_azx_dev(substream);
 975         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 976         snd_pcm_runtime_t *runtime = substream->runtime;
 977
 978         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
 979         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
 980         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
 981         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
 982                                                          runtime->channels,
 983                                                          runtime->format,
 984                                                          hinfo->maxbps);
 985         if (! azx_dev->format_val) {
 986                 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
 987                            runtime->rate, runtime->channels, runtime->format);
 988                 return -EINVAL;
 989         }
 990
 991         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
 992                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
 993         azx_setup_periods(azx_dev);
 994         azx_setup_controller(chip, azx_dev);
 995         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 996                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
 997         else
 998                 azx_dev->fifo_size = 0;
 999
1000         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1001                                   azx_dev->format_val, substream);
1002 }
1003
1004 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1005 {
1006         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1007         azx_dev_t *azx_dev = get_azx_dev(substream);
1008         azx_t *chip = apcm->chip;
1009         int err = 0;
1010
1011         spin_lock(&chip->reg_lock);
1012         switch (cmd) {
1013         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1014         case SNDRV_PCM_TRIGGER_RESUME:
1015         case SNDRV_PCM_TRIGGER_START:
1016                 azx_stream_start(chip, azx_dev);
1017                 azx_dev->running = 1;
1018                 break;
1019         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1020         case SNDRV_PCM_TRIGGER_STOP:
1021                 azx_stream_stop(chip, azx_dev);
1022                 azx_dev->running = 0;
1023                 break;
1024         default:
1025                 err = -EINVAL;
1026         }
1027         spin_unlock(&chip->reg_lock);
1028         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1029             cmd == SNDRV_PCM_TRIGGER_STOP) {
1030                 int timeout = 5000;
1031                 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1032                         ;
1033         }
1034         return err;
1035 }
1036
1037 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1038 {
1039         azx_dev_t *azx_dev = get_azx_dev(substream);
1040         unsigned int pos;
1041
1042 #ifdef USE_POSBUF
1043         /* use the position buffer */
1044         pos = *azx_dev->posbuf;
1045 #else
1046         /* read LPIB */
1047         pos = azx_sd_readl(azx_dev, SD_LPIB) + azx_dev->fifo_size;
1048 #endif
1049         if (pos >= azx_dev->bufsize)
1050                 pos = 0;
1051         return bytes_to_frames(substream->runtime, pos);
1052 }
1053
1054 static snd_pcm_ops_t azx_pcm_ops = {
1055         .open = azx_pcm_open,
1056         .close = azx_pcm_close,
1057         .ioctl = snd_pcm_lib_ioctl,
1058         .hw_params = azx_pcm_hw_params,
1059         .hw_free = azx_pcm_hw_free,
1060         .prepare = azx_pcm_prepare,
1061         .trigger = azx_pcm_trigger,
1062         .pointer = azx_pcm_pointer,
1063 };
1064
1065 static void azx_pcm_free(snd_pcm_t *pcm)
1066 {
1067         kfree(pcm->private_data);
1068 }
1069
1070 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1071                                       struct hda_pcm *cpcm, int pcm_dev)
1072 {
1073         int err;
1074         snd_pcm_t *pcm;
1075         struct azx_pcm *apcm;
1076
1077         snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1078         snd_assert(cpcm->name, return -EINVAL);
1079
1080         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1081                           cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1082                           &pcm);
1083         if (err < 0)
1084                 return err;
1085         strcpy(pcm->name, cpcm->name);
1086         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1087         if (apcm == NULL)
1088                 return -ENOMEM;
1089         apcm->chip = chip;
1090         apcm->codec = codec;
1091         apcm->hinfo[0] = &cpcm->stream[0];
1092         apcm->hinfo[1] = &cpcm->stream[1];
1093         pcm->private_data = apcm;
1094         pcm->private_free = azx_pcm_free;
1095         if (cpcm->stream[0].substreams)
1096                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1097         if (cpcm->stream[1].substreams)
1098                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1099         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1100                                               snd_dma_pci_data(chip->pci),
1101                                               1024 * 64, 1024 * 128);
1102         chip->pcm[pcm_dev] = pcm;
1103
1104         return 0;
1105 }
1106
1107 static int __devinit azx_pcm_create(azx_t *chip)
1108 {
1109         struct list_head *p;
1110         struct hda_codec *codec;
1111         int c, err;
1112         int pcm_dev;
1113
1114         if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1115                 return err;
1116
1117         pcm_dev = 0;
1118         list_for_each(p, &chip->bus->codec_list) {
1119                 codec = list_entry(p, struct hda_codec, list);
1120                 for (c = 0; c < codec->num_pcms; c++) {
1121                         if (pcm_dev >= AZX_MAX_PCMS) {
1122                                 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1123                                 return -EINVAL;
1124                         }
1125                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1126                         if (err < 0)
1127                                 return err;
1128                         pcm_dev++;
1129                 }
1130         }
1131         return 0;
1132 }
1133
1134 /*
1135  * mixer creation - all stuff is implemented in hda module
1136  */
1137 static int __devinit azx_mixer_create(azx_t *chip)
1138 {
1139         return snd_hda_build_controls(chip->bus);
1140 }
1141
1142
1143 /*
1144  * initialize SD streams
1145  */
1146 static int __devinit azx_init_stream(azx_t *chip)
1147 {
1148         int i;
1149
1150         /* initialize each stream (aka device)
1151          * assign the starting bdl address to each stream (device) and initialize
1152          */
1153         for (i = 0; i < MAX_ICH6_DEV; i++) {
1154                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1155                 azx_dev_t *azx_dev = &chip->azx_dev[i];
1156                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1157                 azx_dev->bdl_addr = chip->bdl.addr + off;
1158 #ifdef USE_POSBUF
1159                 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1160 #endif
1161                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1162                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1163                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1164                 azx_dev->sd_int_sta_mask = 1 << i;
1165                 /* stream tag: must be non-zero and unique */
1166                 azx_dev->index = i;
1167                 azx_dev->stream_tag = i + 1;
1168         }
1169
1170         return 0;
1171 }
1172
1173
1174 #ifdef CONFIG_PM
1175 /*
1176  * power management
1177  */
1178 static int azx_suspend(snd_card_t *card, pm_message_t state)
1179 {
1180         azx_t *chip = card->pm_private_data;
1181         int i;
1182
1183         for (i = 0; i < chip->pcm_devs; i++)
1184                 if (chip->pcm[i])
1185                         snd_pcm_suspend_all(chip->pcm[i]);
1186         snd_hda_suspend(chip->bus, state);
1187         azx_free_cmd_io(chip);
1188         pci_disable_device(chip->pci);
1189         return 0;
1190 }
1191
1192 static int azx_resume(snd_card_t *card)
1193 {
1194         azx_t *chip = card->pm_private_data;
1195
1196         pci_enable_device(chip->pci);
1197         pci_set_master(chip->pci);
1198         azx_init_chip(chip);
1199         snd_hda_resume(chip->bus);
1200         return 0;
1201 }
1202 #endif /* CONFIG_PM */
1203
1204
1205 /*
1206  * destructor
1207  */
1208 static int azx_free(azx_t *chip)
1209 {
1210         if (chip->remap_addr) {
1211                 int i;
1212
1213                 for (i = 0; i < MAX_ICH6_DEV; i++)
1214                         azx_stream_stop(chip, &chip->azx_dev[i]);
1215
1216                 /* disable interrupts */
1217                 azx_int_disable(chip);
1218                 azx_int_clear(chip);
1219
1220                 /* disable CORB/RIRB */
1221                 azx_free_cmd_io(chip);
1222
1223                 /* disable position buffer */
1224                 azx_writel(chip, DPLBASE, 0);
1225                 azx_writel(chip, DPUBASE, 0);
1226
1227                 /* wait a little for interrupts to finish */
1228                 msleep(1);
1229
1230                 iounmap(chip->remap_addr);
1231         }
1232
1233         if (chip->irq >= 0)
1234                 free_irq(chip->irq, (void*)chip);
1235
1236         if (chip->bdl.area)
1237                 snd_dma_free_pages(&chip->bdl);
1238         if (chip->rb.area)
1239                 snd_dma_free_pages(&chip->rb);
1240 #ifdef USE_POSBUF
1241         if (chip->posbuf.area)
1242                 snd_dma_free_pages(&chip->posbuf);
1243 #endif
1244         pci_release_regions(chip->pci);
1245         pci_disable_device(chip->pci);
1246         kfree(chip);
1247
1248         return 0;
1249 }
1250
1251 static int azx_dev_free(snd_device_t *device)
1252 {
1253         return azx_free(device->device_data);
1254 }
1255
1256 /*
1257  * constructor
1258  */
1259 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci, azx_t **rchip)
1260 {
1261         azx_t *chip;
1262         int err = 0;
1263         static snd_device_ops_t ops = {
1264                 .dev_free = azx_dev_free,
1265         };
1266
1267         *rchip = NULL;
1268
1269         if ((err = pci_enable_device(pci)) < 0)
1270                 return err;
1271
1272         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1273
1274         if (NULL == chip) {
1275                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1276                 pci_disable_device(pci);
1277                 return -ENOMEM;
1278         }
1279
1280         spin_lock_init(&chip->reg_lock);
1281         init_MUTEX(&chip->open_mutex);
1282         chip->card = card;
1283         chip->pci = pci;
1284         chip->irq = -1;
1285
1286         if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1287                 kfree(chip);
1288                 pci_disable_device(pci);
1289                 return err;
1290         }
1291
1292         chip->addr = pci_resource_start(pci,0);
1293         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1294         if (chip->remap_addr == NULL) {
1295                 snd_printk(KERN_ERR SFX "ioremap error\n");
1296                 err = -ENXIO;
1297                 goto errout;
1298         }
1299
1300         if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1301                         "HDA Intel", (void*)chip)) {
1302                 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1303                 err = -EBUSY;
1304                 goto errout;
1305         }
1306         chip->irq = pci->irq;
1307
1308         pci_set_master(pci);
1309         synchronize_irq(chip->irq);
1310
1311         /* allocate memory for the BDL for each stream */
1312         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1313                                        PAGE_SIZE, &chip->bdl)) < 0) {
1314                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1315                 goto errout;
1316         }
1317 #ifdef USE_POSBUF
1318         /* allocate memory for the position buffer */
1319         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1320                                        MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
1321                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1322                 goto errout;
1323         }
1324 #endif
1325         /* allocate CORB/RIRB */
1326         if ((err = azx_alloc_cmd_io(chip)) < 0)
1327                 goto errout;
1328
1329         /* initialize streams */
1330         azx_init_stream(chip);
1331
1332         /* initialize chip */
1333         azx_init_chip(chip);
1334
1335         /* codec detection */
1336         if (! chip->codec_mask) {
1337                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1338                 err = -ENODEV;
1339                 goto errout;
1340         }
1341
1342         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1343                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1344                 goto errout;
1345         }
1346
1347         *rchip = chip;
1348         return 0;
1349
1350  errout:
1351         azx_free(chip);
1352         return err;
1353 }
1354
1355 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1356 {
1357         static int dev;
1358         snd_card_t *card;
1359         azx_t *chip;
1360         int err = 0;
1361
1362         if (dev >= SNDRV_CARDS)
1363                 return -ENODEV;
1364         if (! enable[dev]) {
1365                 dev++;
1366                 return -ENOENT;
1367         }
1368
1369         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1370         if (NULL == card) {
1371                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1372                 return -ENOMEM;
1373         }
1374
1375         if ((err = azx_create(card, pci, &chip)) < 0) {
1376                 snd_card_free(card);
1377                 return err;
1378         }
1379
1380         strcpy(card->driver, "HDA-Intel");
1381         strcpy(card->shortname, "HDA Intel");
1382         sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1383
1384         /* create codec instances */
1385         if ((err = azx_codec_create(chip, model[dev])) < 0) {
1386                 snd_card_free(card);
1387                 return err;
1388         }
1389
1390         /* create PCM streams */
1391         if ((err = azx_pcm_create(chip)) < 0) {
1392                 snd_card_free(card);
1393                 return err;
1394         }
1395
1396         /* create mixer controls */
1397         if ((err = azx_mixer_create(chip)) < 0) {
1398                 snd_card_free(card);
1399                 return err;
1400         }
1401
1402         snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1403         snd_card_set_dev(card, &pci->dev);
1404
1405         if ((err = snd_card_register(card)) < 0) {
1406                 snd_card_free(card);
1407                 return err;
1408         }
1409
1410         pci_set_drvdata(pci, card);
1411         dev++;
1412
1413         return err;
1414 }
1415
1416 static void __devexit azx_remove(struct pci_dev *pci)
1417 {
1418         snd_card_free(pci_get_drvdata(pci));
1419         pci_set_drvdata(pci, NULL);
1420 }
1421
1422 /* PCI IDs */
1423 static struct pci_device_id azx_ids[] = {
1424         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
1425         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
1426         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
1427         { 0, }
1428 };
1429 MODULE_DEVICE_TABLE(pci, azx_ids);
1430
1431 /* pci_driver definition */
1432 static struct pci_driver driver = {
1433         .name = "HDA Intel",
1434         .id_table = azx_ids,
1435         .probe = azx_probe,
1436         .remove = __devexit_p(azx_remove),
1437         SND_PCI_PM_CALLBACKS
1438 };
1439
1440 static int __init alsa_card_azx_init(void)
1441 {
1442         return pci_module_init(&driver);
1443 }
1444
1445 static void __exit alsa_card_azx_exit(void)
1446 {
1447         pci_unregister_driver(&driver);
1448 }
1449
1450 module_init(alsa_card_azx_init)
1451 module_exit(alsa_card_azx_exit)