sound/pci/intel8x0.c

   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/gameport.h>
  37 #include <linux/moduleparam.h>
  38 #include <sound/core.h>
  39 #include <sound/pcm.h>
  40 #include <sound/ac97_codec.h>
  41 #include <sound/info.h>
  42 #include <sound/mpu401.h>
  43 #include <sound/initval.h>
  44 /* for 440MX workaround */
  45 #include <asm/pgtable.h>
  46 #include <asm/cacheflush.h>
  47
  48 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  49 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  50 MODULE_LICENSE("GPL");
  51 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  52                 "{Intel,82901AB-ICH0},"
  53                 "{Intel,82801BA-ICH2},"
  54                 "{Intel,82801CA-ICH3},"
  55                 "{Intel,82801DB-ICH4},"
  56                 "{Intel,ICH5},"
  57                 "{Intel,ICH6},"
  58                 "{Intel,6300ESB},"
  59                 "{Intel,MX440},"
  60                 "{SiS,SI7012},"
  61                 "{NVidia,nForce Audio},"
  62                 "{NVidia,nForce2 Audio},"
  63                 "{AMD,AMD768},"
  64                 "{AMD,AMD8111},"
  65                 "{ALI,M5455}}");
  66
  67 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  68 #define SUPPORT_JOYSTICK 1
  69 #endif
  70 #define SUPPORT_MIDI 1
  71
  72 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  73 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  74 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  75 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  76 static int ac97_quirk[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = AC97_TUNE_DEFAULT};
  77 static int buggy_irq[SNDRV_CARDS];
  78 #ifdef SUPPORT_JOYSTICK
  79 static int joystick[SNDRV_CARDS];
  80 #endif
  81 #ifdef SUPPORT_MIDI
  82 static int mpu_port[SNDRV_CARDS]; /* disabled */
  83 #endif
  84 static int boot_devs;
  85
  86 module_param_array(index, int, boot_devs, 0444);
  87 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  88 module_param_array(id, charp, boot_devs, 0444);
  89 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  90 module_param_array(enable, bool, boot_devs, 0444);
  91 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
  92 module_param_array(ac97_clock, int, boot_devs, 0444);
  93 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  94 module_param_array(ac97_quirk, int, boot_devs, 0444);
  95 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  96 module_param_array(buggy_irq, bool, boot_devs, 0444);
  97 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  98 #ifdef SUPPORT_JOYSTICK
  99 module_param_array(joystick, bool, boot_devs, 0444);
 100 MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
 101 #endif
 102 #ifdef SUPPORT_MIDI
 103 module_param_array(mpu_port, int, boot_devs, 0444);
 104 MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
 105 #endif
 106
 107 /*
 108  *  Direct registers
 109  */
 110
 111 #ifndef PCI_DEVICE_ID_INTEL_82801
 112 #define PCI_DEVICE_ID_INTEL_82801       0x2415
 113 #endif
 114 #ifndef PCI_DEVICE_ID_INTEL_82901
 115 #define PCI_DEVICE_ID_INTEL_82901       0x2425
 116 #endif
 117 #ifndef PCI_DEVICE_ID_INTEL_82801BA
 118 #define PCI_DEVICE_ID_INTEL_82801BA     0x2445
 119 #endif
 120 #ifndef PCI_DEVICE_ID_INTEL_440MX
 121 #define PCI_DEVICE_ID_INTEL_440MX       0x7195
 122 #endif
 123 #ifndef PCI_DEVICE_ID_INTEL_ICH3
 124 #define PCI_DEVICE_ID_INTEL_ICH3        0x2485
 125 #endif
 126 #ifndef PCI_DEVICE_ID_INTEL_ICH4
 127 #define PCI_DEVICE_ID_INTEL_ICH4        0x24c5
 128 #endif
 129 #ifndef PCI_DEVICE_ID_INTEL_ICH5
 130 #define PCI_DEVICE_ID_INTEL_ICH5        0x24d5
 131 #endif
 132 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
 133 #define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
 134 #endif
 135 #ifndef PCI_DEVICE_ID_INTEL_ICH6_3
 136 #define PCI_DEVICE_ID_INTEL_ICH6_3      0x266e
 137 #endif
 138 #ifndef PCI_DEVICE_ID_SI_7012
 139 #define PCI_DEVICE_ID_SI_7012           0x7012
 140 #endif
 141 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
 142 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO  0x01b1
 143 #endif
 144 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
 145 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
 146 #endif
 147 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
 148 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
 149 #endif
 150 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
 151 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO  0x008a
 152 #endif
 153 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
 154 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
 155 #endif
 156 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
 157 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
 158 #endif
 159
 160 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 161
 162 #define ICHREG(x) ICH_REG_##x
 163
 164 #define DEFINE_REGSET(name,base) \
 165 enum { \
 166         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 167         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 168         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 169         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 170         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 171         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 172         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 173 };
 174
 175 /* busmaster blocks */
 176 DEFINE_REGSET(OFF, 0);          /* offset */
 177 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 178 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 179 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 180
 181 /* ICH4 busmaster blocks */
 182 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 183 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 184 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 185
 186 /* values for each busmaster block */
 187
 188 /* LVI */
 189 #define ICH_REG_LVI_MASK                0x1f
 190
 191 /* SR */
 192 #define ICH_FIFOE                       0x10    /* FIFO error */
 193 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 194 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 195 #define ICH_CELV                        0x02    /* current equals last valid */
 196 #define ICH_DCH                         0x01    /* DMA controller halted */
 197
 198 /* PIV */
 199 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 200
 201 /* CR */
 202 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 203 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 204 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 205 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 206 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 207
 208
 209 /* global block */
 210 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 211 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 212 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 213 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 214 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 215 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 216 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 217 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 218 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 219 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 220 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 221 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 222 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 223 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 224 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 225 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 226 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 227 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 228 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 229 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 230 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 231 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 232 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 233 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 234 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 235 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 236 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 237 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 238 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 239 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 240 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 241 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 242 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 243 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 244 #define   ICH_RCS               0x00008000      /* read completion status */
 245 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 246 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 247 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 248 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 249 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 250 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 251 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 252 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 253 #define   ICH_POINT             0x00000040      /* playback interrupt */
 254 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 255 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 256 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 257 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 258 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 259 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 260 #define   ICH_CAS               0x01            /* codec access semaphore */
 261 #define ICH_REG_SDM             0x80
 262 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 263 #define   ICH_DI2L_SHIFT        6
 264 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 265 #define   ICH_DI1L_SHIFT        4
 266 #define   ICH_SE                0x00000008      /* steer enable */
 267 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 268
 269 #define ICH_MAX_FRAGS           32              /* max hw frags */
 270
 271
 272 /*
 273  * registers for Ali5455
 274  */
 275
 276 /* ALi 5455 busmaster blocks */
 277 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 278 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 279 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 280 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 281 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 282 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 283 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 284 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 285 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 286 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 287 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 288
 289 enum {
 290         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 291         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 292         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 293         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 294         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 295         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 296         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 297         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 298         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 299         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 300         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 301         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 302         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 303         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 304         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 305         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 306         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 307         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 308         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 309         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 310         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 311 };
 312
 313 #define ALI_CAS_SEM_BUSY        0x80000000
 314 #define ALI_CPR_ADDR_SECONDARY  0x100
 315 #define ALI_CPR_ADDR_READ       0x80
 316 #define ALI_CSPSR_CODEC_READY   0x08
 317 #define ALI_CSPSR_READ_OK       0x02
 318 #define ALI_CSPSR_WRITE_OK      0x01
 319
 320 /* interrupts for the whole chip by interrupt status register finish */
 321
 322 #define ALI_INT_MICIN2          (1<<26)
 323 #define ALI_INT_PCMIN2          (1<<25)
 324 #define ALI_INT_I2SIN           (1<<24)
 325 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 326 #define ALI_INT_SPDIFIN         (1<<22)
 327 #define ALI_INT_LFEOUT          (1<<21)
 328 #define ALI_INT_CENTEROUT       (1<<20)
 329 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 330 #define ALI_INT_MICIN           (1<<18)
 331 #define ALI_INT_PCMOUT          (1<<17)
 332 #define ALI_INT_PCMIN           (1<<16)
 333 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 334 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 335 #define ALI_INT_GPIO            (1<<1)
 336 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 337
 338 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 339 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 340 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 341 #define ICH_ALI_SC_IN_BITS      (3<<18)
 342 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 343 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 344 #define ICH_ALI_SC_PCM_4        (1<<8)
 345 #define ICH_ALI_SC_PCM_6        (2<<8)
 346 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 347
 348 #define ICH_ALI_SS_SEC_ID       (3<<5)
 349 #define ICH_ALI_SS_PRI_ID       (3<<3)
 350
 351 #define ICH_ALI_IF_AC97SP       (1<<21)
 352 #define ICH_ALI_IF_MC           (1<<20)
 353 #define ICH_ALI_IF_PI           (1<<19)
 354 #define ICH_ALI_IF_MC2          (1<<18)
 355 #define ICH_ALI_IF_PI2          (1<<17)
 356 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 357 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 358 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 359 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 360 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 361 #define ICH_ALI_IF_PO           (1<<1)
 362
 363 /*
 364  *
 365  */
 366
 367 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
 368 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
 369 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
 370
 371 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 372
 373 typedef struct {
 374         unsigned int ichd;                      /* ich device number */
 375         unsigned long reg_offset;               /* offset to bmaddr */
 376         u32 *bdbar;                             /* CPU address (32bit) */
 377         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 378         snd_pcm_substream_t *substream;
 379         unsigned int physbuf;                   /* physical address (32bit) */
 380         unsigned int size;
 381         unsigned int fragsize;
 382         unsigned int fragsize1;
 383         unsigned int position;
 384         unsigned int pos_shift;
 385         int frags;
 386         int lvi;
 387         int lvi_frag;
 388         int civ;
 389         int ack;
 390         int ack_reload;
 391         unsigned int ack_bit;
 392         unsigned int roff_sr;
 393         unsigned int roff_picb;
 394         unsigned int int_sta_mask;              /* interrupt status mask */
 395         unsigned int ali_slot;                  /* ALI DMA slot */
 396         struct ac97_pcm *pcm;
 397         int pcm_open_flag;
 398 } ichdev_t;
 399
 400 typedef struct _snd_intel8x0 intel8x0_t;
 401
 402 struct _snd_intel8x0 {
 403         unsigned int device_type;
 404
 405         int irq;
 406
 407         unsigned int mmio;
 408         unsigned long addr;
 409         void __iomem * remap_addr;
 410         unsigned int bm_mmio;
 411         unsigned long bmaddr;
 412         void __iomem * remap_bmaddr;
 413
 414         struct pci_dev *pci;
 415         snd_card_t *card;
 416
 417         int pcm_devs;
 418         snd_pcm_t *pcm[6];
 419         ichdev_t ichd[6];
 420
 421         unsigned multi4: 1,
 422                  multi6: 1,
 423                  smp20bit: 1;
 424         unsigned in_ac97_init: 1,
 425                  in_sdin_init: 1;
 426         unsigned fix_nocache: 1; /* workaround for 440MX */
 427         unsigned buggy_irq: 1; /* workaround for buggy mobos */
 428
 429         ac97_bus_t *ac97_bus;
 430         ac97_t *ac97[3];
 431         unsigned int ac97_sdin[3];
 432
 433         snd_rawmidi_t *rmidi;
 434
 435         spinlock_t reg_lock;
 436         spinlock_t ac97_lock;
 437
 438         u32 bdbars_count;
 439         struct snd_dma_buffer bdbars;
 440         u32 int_sta_reg;                /* interrupt status register */
 441         u32 int_sta_mask;               /* interrupt status mask */
 442 };
 443
 444 static struct pci_device_id snd_intel8x0_ids[] = {
 445         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 446         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 447         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 448         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 449         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 450         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 451         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 452         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 453         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 454         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 455         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 456         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 457         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 458         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 459         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 460         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 461         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 462         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 463         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 464         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 465         { 0, }
 466 };
 467
 468 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 469
 470 /*
 471  *  Lowlevel I/O - busmaster
 472  */
 473
 474 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 475 {
 476         if (chip->bm_mmio)
 477                 return readb(chip->remap_bmaddr + offset);
 478         else
 479                 return inb(chip->bmaddr + offset);
 480 }
 481
 482 static u16 igetword(intel8x0_t *chip, u32 offset)
 483 {
 484         if (chip->bm_mmio)
 485                 return readw(chip->remap_bmaddr + offset);
 486         else
 487                 return inw(chip->bmaddr + offset);
 488 }
 489
 490 static u32 igetdword(intel8x0_t *chip, u32 offset)
 491 {
 492         if (chip->bm_mmio)
 493                 return readl(chip->remap_bmaddr + offset);
 494         else
 495                 return inl(chip->bmaddr + offset);
 496 }
 497
 498 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 499 {
 500         if (chip->bm_mmio)
 501                 writeb(val, chip->remap_bmaddr + offset);
 502         else
 503                 outb(val, chip->bmaddr + offset);
 504 }
 505
 506 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 507 {
 508         if (chip->bm_mmio)
 509                 writew(val, chip->remap_bmaddr + offset);
 510         else
 511                 outw(val, chip->bmaddr + offset);
 512 }
 513
 514 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 515 {
 516         if (chip->bm_mmio)
 517                 writel(val, chip->remap_bmaddr + offset);
 518         else
 519                 outl(val, chip->bmaddr + offset);
 520 }
 521
 522 /*
 523  *  Lowlevel I/O - AC'97 registers
 524  */
 525
 526 static u16 iagetword(intel8x0_t *chip, u32 offset)
 527 {
 528         if (chip->mmio)
 529                 return readw(chip->remap_addr + offset);
 530         else
 531                 return inw(chip->addr + offset);
 532 }
 533
 534 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 535 {
 536         if (chip->mmio)
 537                 writew(val, chip->remap_addr + offset);
 538         else
 539                 outw(val, chip->addr + offset);
 540 }
 541
 542 /*
 543  *  Basic I/O
 544  */
 545
 546 /*
 547  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 548  */
 549
 550 /* return the GLOB_STA bit for the corresponding codec */
 551 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 552 {
 553         static unsigned int codec_bit[3] = {
 554                 ICH_PCR, ICH_SCR, ICH_TCR
 555         };
 556         snd_assert(codec < 3, return ICH_PCR);
 557         if (chip->device_type == DEVICE_INTEL_ICH4)
 558                 codec = chip->ac97_sdin[codec];
 559         return codec_bit[codec];
 560 }
 561
 562 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 563 {
 564         int time;
 565
 566         if (codec > 2)
 567                 return -EIO;
 568         if (chip->in_sdin_init) {
 569                 /* we don't know the ready bit assignment at the moment */
 570                 /* so we check any */
 571                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
 572         } else {
 573                 codec = get_ich_codec_bit(chip, codec);
 574         }
 575
 576         /* codec ready ? */
 577         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 578                 return -EIO;
 579
 580         /* Anyone holding a semaphore for 1 msec should be shot... */
 581         time = 100;
 582         do {
 583                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 584                         return 0;
 585                 udelay(10);
 586         } while (time--);
 587
 588         /* access to some forbidden (non existant) ac97 registers will not
 589          * reset the semaphore. So even if you don't get the semaphore, still
 590          * continue the access. We don't need the semaphore anyway. */
 591         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 592                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 593         iagetword(chip, 0);     /* clear semaphore flag */
 594         /* I don't care about the semaphore */
 595         return -EBUSY;
 596 }
 597
 598 static void snd_intel8x0_codec_write(ac97_t *ac97,
 599                                      unsigned short reg,
 600                                      unsigned short val)
 601 {
 602         intel8x0_t *chip = ac97->private_data;
 603
 604         spin_lock(&chip->ac97_lock);
 605         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 606                 if (! chip->in_ac97_init)
 607                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 608         }
 609         iaputword(chip, reg + ac97->num * 0x80, val);
 610         spin_unlock(&chip->ac97_lock);
 611 }
 612
 613 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 614                                               unsigned short reg)
 615 {
 616         intel8x0_t *chip = ac97->private_data;
 617         unsigned short res;
 618         unsigned int tmp;
 619
 620         spin_lock(&chip->ac97_lock);
 621         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 622                 if (! chip->in_ac97_init)
 623                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 624                 res = 0xffff;
 625         } else {
 626                 res = iagetword(chip, reg + ac97->num * 0x80);
 627                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 628                         /* reset RCS and preserve other R/WC bits */
 629                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 630                         if (! chip->in_ac97_init)
 631                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 632                         res = 0xffff;
 633                 }
 634         }
 635         spin_unlock(&chip->ac97_lock);
 636         return res;
 637 }
 638
 639 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
 640 {
 641         unsigned int tmp;
 642
 643         spin_lock(&chip->ac97_lock);
 644         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 645                 iagetword(chip, codec * 0x80);
 646                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 647                         /* reset RCS and preserve other R/WC bits */
 648                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 649                 }
 650         }
 651         spin_unlock(&chip->ac97_lock);
 652 }
 653
 654 /*
 655  * access to AC97 for Ali5455
 656  */
 657 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
 658 {
 659         int count = 0;
 660         for (count = 0; count < 0x7f; count++) {
 661                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 662                 if (val & mask)
 663                         return 0;
 664         }
 665         snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 666         return -EBUSY;
 667 }
 668
 669 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
 670 {
 671         int time = 100;
 672         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 673                 udelay(1);
 674         if (! time)
 675                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 676         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 677 }
 678
 679 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
 680 {
 681         intel8x0_t *chip = ac97->private_data;
 682         unsigned short data = 0xffff;
 683
 684         spin_lock(&chip->ac97_lock);
 685         if (snd_intel8x0_ali_codec_semaphore(chip))
 686                 goto __err;
 687         reg |= ALI_CPR_ADDR_READ;
 688         if (ac97->num)
 689                 reg |= ALI_CPR_ADDR_SECONDARY;
 690         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 691         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 692                 goto __err;
 693         data = igetword(chip, ICHREG(ALI_SPR));
 694  __err:
 695         spin_unlock(&chip->ac97_lock);
 696         return data;
 697 }
 698
 699 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
 700 {
 701         intel8x0_t *chip = ac97->private_data;
 702
 703         spin_lock(&chip->ac97_lock);
 704         if (snd_intel8x0_ali_codec_semaphore(chip)) {
 705                 spin_unlock(&chip->ac97_lock);
 706                 return;
 707         }
 708         iputword(chip, ICHREG(ALI_CPR), val);
 709         if (ac97->num)
 710                 reg |= ALI_CPR_ADDR_SECONDARY;
 711         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 712         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 713         spin_unlock(&chip->ac97_lock);
 714 }
 715
 716
 717 /*
 718  * DMA I/O
 719  */
 720 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 721 {
 722         int idx;
 723         u32 *bdbar = ichdev->bdbar;
 724         unsigned long port = ichdev->reg_offset;
 725
 726         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 727         if (ichdev->size == ichdev->fragsize) {
 728                 ichdev->ack_reload = ichdev->ack = 2;
 729                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 730                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 731                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 732                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 733                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 734                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 735                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 736                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 737                 }
 738                 ichdev->frags = 2;
 739         } else {
 740                 ichdev->ack_reload = ichdev->ack = 1;
 741                 ichdev->fragsize1 = ichdev->fragsize;
 742                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 743                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 744                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 745                                                      ichdev->fragsize >> ichdev->pos_shift);
 746                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 747                 }
 748                 ichdev->frags = ichdev->size / ichdev->fragsize;
 749         }
 750         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 751         ichdev->civ = 0;
 752         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 753         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 754         ichdev->position = 0;
 755 #if 0
 756         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 757                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 758 #endif
 759         /* clear interrupts */
 760         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 761 }
 762
 763 #ifdef __i386__
 764 /*
 765  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 766  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 767  * the pages as non-cached.  For details, see the errata in
 768  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 769  */
 770 static void fill_nocache(void *buf, int size, int nocache)
 771 {
 772         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 773         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
 774         global_flush_tlb();
 775 }
 776 #else
 777 #define fill_nocache(buf,size,nocache)
 778 #endif
 779
 780 /*
 781  *  Interrupt handler
 782  */
 783
 784 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 785 {
 786         unsigned long port = ichdev->reg_offset;
 787         int status, civ, i, step;
 788         int ack = 0;
 789
 790         spin_lock(&chip->reg_lock);
 791         status = igetbyte(chip, port + ichdev->roff_sr);
 792         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 793         if (!(status & ICH_BCIS)) {
 794                 step = 0;
 795         } else if (civ == ichdev->civ) {
 796                 // snd_printd("civ same %d\n", civ);
 797                 step = 1;
 798                 ichdev->civ++;
 799                 ichdev->civ &= ICH_REG_LVI_MASK;
 800         } else {
 801                 step = civ - ichdev->civ;
 802                 if (step < 0)
 803                         step += ICH_REG_LVI_MASK + 1;
 804                 // if (step != 1)
 805                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 806                 ichdev->civ = civ;
 807         }
 808
 809         ichdev->position += step * ichdev->fragsize1;
 810         ichdev->position %= ichdev->size;
 811         ichdev->lvi += step;
 812         ichdev->lvi &= ICH_REG_LVI_MASK;
 813         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 814         for (i = 0; i < step; i++) {
 815                 ichdev->lvi_frag++;
 816                 ichdev->lvi_frag %= ichdev->frags;
 817                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 818         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 819                 if (--ichdev->ack == 0) {
 820                         ichdev->ack = ichdev->ack_reload;
 821                         ack = 1;
 822                 }
 823         }
 824         spin_unlock(&chip->reg_lock);
 825         if (ack && ichdev->substream) {
 826                 snd_pcm_period_elapsed(ichdev->substream);
 827         }
 828         iputbyte(chip, port + ichdev->roff_sr,
 829                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 830 }
 831
 832 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 833 {
 834         intel8x0_t *chip = dev_id;
 835         ichdev_t *ichdev;
 836         unsigned int status;
 837         unsigned int i;
 838
 839         status = igetdword(chip, chip->int_sta_reg);
 840         if (status == 0xffffffff)       /* we are not yet resumed */
 841                 return IRQ_NONE;
 842
 843         if ((status & chip->int_sta_mask) == 0) {
 844                 if (status) {
 845                         /* ack */
 846                         iputdword(chip, chip->int_sta_reg, status);
 847                         if (! chip->buggy_irq)
 848                                 status = 0;
 849                 }
 850                 return IRQ_RETVAL(status);
 851         }
 852
 853         for (i = 0; i < chip->bdbars_count; i++) {
 854                 ichdev = &chip->ichd[i];
 855                 if (status & ichdev->int_sta_mask)
 856                         snd_intel8x0_update(chip, ichdev);
 857         }
 858
 859         /* ack them */
 860         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 861
 862         return IRQ_HANDLED;
 863 }
 864
 865 /*
 866  *  PCM part
 867  */
 868
 869 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 870 {
 871         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 872         ichdev_t *ichdev = get_ichdev(substream);
 873         unsigned char val = 0;
 874         unsigned long port = ichdev->reg_offset;
 875
 876         switch (cmd) {
 877         case SNDRV_PCM_TRIGGER_START:
 878         case SNDRV_PCM_TRIGGER_RESUME:
 879                 val = ICH_IOCE | ICH_STARTBM;
 880                 break;
 881         case SNDRV_PCM_TRIGGER_STOP:
 882         case SNDRV_PCM_TRIGGER_SUSPEND:
 883                 val = 0;
 884                 break;
 885         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 886                 val = ICH_IOCE;
 887                 break;
 888         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 889                 val = ICH_IOCE | ICH_STARTBM;
 890                 break;
 891         default:
 892                 return -EINVAL;
 893         }
 894         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 895         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 896                 /* wait until DMA stopped */
 897                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 898                 /* reset whole DMA things */
 899                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 900         }
 901         return 0;
 902 }
 903
 904 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
 905 {
 906         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 907         ichdev_t *ichdev = get_ichdev(substream);
 908         unsigned long port = ichdev->reg_offset;
 909         static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
 910         unsigned int val, fifo;
 911
 912         val = igetdword(chip, ICHREG(ALI_DMACR));
 913         switch (cmd) {
 914         case SNDRV_PCM_TRIGGER_START:
 915         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 916         case SNDRV_PCM_TRIGGER_RESUME:
 917                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 918                         /* clear FIFO for synchronization of channels */
 919                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 920                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 921                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 922                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 923                 }
 924                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 925                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 926                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
 927                 break;
 928         case SNDRV_PCM_TRIGGER_STOP:
 929         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 930         case SNDRV_PCM_TRIGGER_SUSPEND:
 931                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
 932                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 933                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 934                         ;
 935                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 936                         break;
 937                 /* reset whole DMA things */
 938                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 939                 /* clear interrupts */
 940                 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 941                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 942                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 943                 break;
 944         default:
 945                 return -EINVAL;
 946         }
 947         return 0;
 948 }
 949
 950 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 951                                   snd_pcm_hw_params_t * hw_params)
 952 {
 953         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 954         ichdev_t *ichdev = get_ichdev(substream);
 955         snd_pcm_runtime_t *runtime = substream->runtime;
 956         size_t size = params_buffer_bytes(hw_params);
 957         int err;
 958
 959         if (chip->fix_nocache && runtime->dma_area && runtime->dma_bytes < size)
 960                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 961         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 962         if (err < 0)
 963                 return err;
 964         if (chip->fix_nocache && err > 0)
 965                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 966         if (ichdev->pcm_open_flag) {
 967                 snd_ac97_pcm_close(ichdev->pcm);
 968                 ichdev->pcm_open_flag = 0;
 969         }
 970         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 971                                 params_channels(hw_params),
 972                                 ichdev->pcm->r[0].slots);
 973         if (err >= 0) {
 974                 ichdev->pcm_open_flag = 1;
 975                 /* FIXME: hack to enable spdif support */
 976                 if (ichdev->ichd == ICHD_PCMOUT && chip->device_type == DEVICE_SIS)
 977                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
 978         }
 979         return err;
 980 }
 981
 982 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 983 {
 984         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 985         ichdev_t *ichdev = get_ichdev(substream);
 986
 987         if (ichdev->pcm_open_flag) {
 988                 snd_ac97_pcm_close(ichdev->pcm);
 989                 ichdev->pcm_open_flag = 0;
 990         }
 991         if (chip->fix_nocache && substream->runtime->dma_area)
 992                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 993         return snd_pcm_lib_free_pages(substream);
 994 }
 995
 996 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
 997                                        int channels, int sample_bits)
 998 {
 999         unsigned int cnt;
1000         switch (chip->device_type) {
1001         case DEVICE_ALI:
1002                 cnt = igetdword(chip, ICHREG(ALI_SCR));
1003                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1004                 if (chip->multi4 && channels == 4)
1005                         cnt |= ICH_ALI_SC_PCM_4;
1006                 else if (chip->multi6 && channels == 6)
1007                         cnt |= ICH_ALI_SC_PCM_6;
1008                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1009                 break;
1010         case DEVICE_SIS:
1011                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1012                 cnt &= ~ICH_SIS_PCM_246_MASK;
1013                 if (chip->multi4 && channels == 4)
1014                         cnt |= ICH_SIS_PCM_4;
1015                 else if (chip->multi6 && channels == 6)
1016                         cnt |= ICH_SIS_PCM_6;
1017                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1018                 break;
1019         default:
1020                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1021                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1022                 if (chip->multi4 && channels == 4)
1023                         cnt |= ICH_PCM_4;
1024                 else if (chip->multi6 && channels == 6)
1025                         cnt |= ICH_PCM_6;
1026                 if (chip->device_type == DEVICE_NFORCE) {
1027                         /* reset to 2ch once to keep the 6 channel data in alignment,
1028                          * to start from Front Left always
1029                          */
1030                         if (cnt & ICH_PCM_246_MASK) {
1031                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1032                                 msleep(50); /* grrr... */
1033                         }
1034                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1035                         if (sample_bits > 16)
1036                                 cnt |= ICH_PCM_20BIT;
1037                 }
1038                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1039                 break;
1040         }
1041 }
1042
1043 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1044 {
1045         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1046         snd_pcm_runtime_t *runtime = substream->runtime;
1047         ichdev_t *ichdev = get_ichdev(substream);
1048
1049         ichdev->physbuf = runtime->dma_addr;
1050         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1051         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1052         spin_lock_irq(&chip->reg_lock);
1053         if (ichdev->ichd == ICHD_PCMOUT) {
1054                 snd_intel8x0_setup_pcm_out(chip, runtime->channels,
1055                                            runtime->sample_bits);
1056                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1057                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1058                 }
1059         }
1060         snd_intel8x0_setup_periods(chip, ichdev);
1061         spin_unlock_irq(&chip->reg_lock);
1062         return 0;
1063 }
1064
1065 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1066 {
1067         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1068         ichdev_t *ichdev = get_ichdev(substream);
1069         size_t ptr1, ptr;
1070         int civ, timeout = 10;
1071         unsigned int position;
1072
1073         spin_lock(&chip->reg_lock);
1074         do {
1075                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1076                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1077                 position = ichdev->position;
1078                 if (ptr1 == 0)
1079                         udelay(1);
1080                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1081                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1082                         break;
1083         } while (timeout--);
1084         ptr1 <<= ichdev->pos_shift;
1085         ptr = ichdev->fragsize1 - ptr1;
1086         ptr += position;
1087         spin_unlock(&chip->reg_lock);
1088         if (ptr >= ichdev->size)
1089                 return 0;
1090         return bytes_to_frames(substream->runtime, ptr);
1091 }
1092
1093 static snd_pcm_hardware_t snd_intel8x0_stream =
1094 {
1095         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1096                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1097                                  SNDRV_PCM_INFO_MMAP_VALID |
1098                                  SNDRV_PCM_INFO_PAUSE |
1099                                  SNDRV_PCM_INFO_RESUME),
1100         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1101         .rates =                SNDRV_PCM_RATE_48000,
1102         .rate_min =             48000,
1103         .rate_max =             48000,
1104         .channels_min =         2,
1105         .channels_max =         2,
1106         .buffer_bytes_max =     128 * 1024,
1107         .period_bytes_min =     32,
1108         .period_bytes_max =     128 * 1024,
1109         .periods_min =          1,
1110         .periods_max =          1024,
1111         .fifo_size =            0,
1112 };
1113
1114 static unsigned int channels4[] = {
1115         2, 4,
1116 };
1117
1118 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1119         .count = ARRAY_SIZE(channels4),
1120         .list = channels4,
1121         .mask = 0,
1122 };
1123
1124 static unsigned int channels6[] = {
1125         2, 4, 6,
1126 };
1127
1128 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1129         .count = ARRAY_SIZE(channels6),
1130         .list = channels6,
1131         .mask = 0,
1132 };
1133
1134 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1135 {
1136         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1137         snd_pcm_runtime_t *runtime = substream->runtime;
1138         int err;
1139
1140         ichdev->substream = substream;
1141         runtime->hw = snd_intel8x0_stream;
1142         runtime->hw.rates = ichdev->pcm->rates;
1143         snd_pcm_limit_hw_rates(runtime);
1144         if (chip->device_type == DEVICE_SIS) {
1145                 runtime->hw.buffer_bytes_max = 64*1024;
1146                 runtime->hw.period_bytes_max = 64*1024;
1147         }
1148         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1149                 return err;
1150         runtime->private_data = ichdev;
1151         return 0;
1152 }
1153
1154 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1155 {
1156         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1157         snd_pcm_runtime_t *runtime = substream->runtime;
1158         int err;
1159
1160         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1161         if (err < 0)
1162                 return err;
1163
1164         if (chip->multi6) {
1165                 runtime->hw.channels_max = 6;
1166                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1167         } else if (chip->multi4) {
1168                 runtime->hw.channels_max = 4;
1169                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1170         }
1171         if (chip->smp20bit) {
1172                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1173                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1174         }
1175         return 0;
1176 }
1177
1178 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1179 {
1180         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1181
1182         chip->ichd[ICHD_PCMOUT].substream = NULL;
1183         return 0;
1184 }
1185
1186 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1187 {
1188         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1189
1190         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1191 }
1192
1193 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1194 {
1195         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1196
1197         chip->ichd[ICHD_PCMIN].substream = NULL;
1198         return 0;
1199 }
1200
1201 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1202 {
1203         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1204
1205         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1206 }
1207
1208 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1209 {
1210         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1211
1212         chip->ichd[ICHD_MIC].substream = NULL;
1213         return 0;
1214 }
1215
1216 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1217 {
1218         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1219
1220         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1221 }
1222
1223 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1224 {
1225         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1226
1227         chip->ichd[ICHD_MIC2].substream = NULL;
1228         return 0;
1229 }
1230
1231 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1232 {
1233         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1234
1235         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1236 }
1237
1238 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1239 {
1240         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1241
1242         chip->ichd[ICHD_PCM2IN].substream = NULL;
1243         return 0;
1244 }
1245
1246 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1247 {
1248         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1249         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1250
1251         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1252 }
1253
1254 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1255 {
1256         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1257         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1258
1259         chip->ichd[idx].substream = NULL;
1260         return 0;
1261 }
1262
1263 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1264 {
1265         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1266         unsigned int val;
1267
1268         spin_lock_irq(&chip->reg_lock);
1269         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1270         val |= ICH_ALI_IF_AC97SP;
1271         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1272         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1273         spin_unlock_irq(&chip->reg_lock);
1274
1275         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1276 }
1277
1278 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1279 {
1280         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1281         unsigned int val;
1282
1283         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1284         spin_lock_irq(&chip->reg_lock);
1285         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1286         val &= ~ICH_ALI_IF_AC97SP;
1287         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1288         spin_unlock_irq(&chip->reg_lock);
1289
1290         return 0;
1291 }
1292
1293 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1294 {
1295         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1296
1297         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1298 }
1299
1300 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1301 {
1302         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1303
1304         chip->ichd[ALID_SPDIFIN].substream = NULL;
1305         return 0;
1306 }
1307
1308 #if 0 // NYI
1309 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1310 {
1311         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1312
1313         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1314 }
1315
1316 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1317 {
1318         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1319
1320         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1321         return 0;
1322 }
1323 #endif
1324
1325 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1326         .open =         snd_intel8x0_playback_open,
1327         .close =        snd_intel8x0_playback_close,
1328         .ioctl =        snd_pcm_lib_ioctl,
1329         .hw_params =    snd_intel8x0_hw_params,
1330         .hw_free =      snd_intel8x0_hw_free,
1331         .prepare =      snd_intel8x0_pcm_prepare,
1332         .trigger =      snd_intel8x0_pcm_trigger,
1333         .pointer =      snd_intel8x0_pcm_pointer,
1334 };
1335
1336 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1337         .open =         snd_intel8x0_capture_open,
1338         .close =        snd_intel8x0_capture_close,
1339         .ioctl =        snd_pcm_lib_ioctl,
1340         .hw_params =    snd_intel8x0_hw_params,
1341         .hw_free =      snd_intel8x0_hw_free,
1342         .prepare =      snd_intel8x0_pcm_prepare,
1343         .trigger =      snd_intel8x0_pcm_trigger,
1344         .pointer =      snd_intel8x0_pcm_pointer,
1345 };
1346
1347 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1348         .open =         snd_intel8x0_mic_open,
1349         .close =        snd_intel8x0_mic_close,
1350         .ioctl =        snd_pcm_lib_ioctl,
1351         .hw_params =    snd_intel8x0_hw_params,
1352         .hw_free =      snd_intel8x0_hw_free,
1353         .prepare =      snd_intel8x0_pcm_prepare,
1354         .trigger =      snd_intel8x0_pcm_trigger,
1355         .pointer =      snd_intel8x0_pcm_pointer,
1356 };
1357
1358 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1359         .open =         snd_intel8x0_mic2_open,
1360         .close =        snd_intel8x0_mic2_close,
1361         .ioctl =        snd_pcm_lib_ioctl,
1362         .hw_params =    snd_intel8x0_hw_params,
1363         .hw_free =      snd_intel8x0_hw_free,
1364         .prepare =      snd_intel8x0_pcm_prepare,
1365         .trigger =      snd_intel8x0_pcm_trigger,
1366         .pointer =      snd_intel8x0_pcm_pointer,
1367 };
1368
1369 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1370         .open =         snd_intel8x0_capture2_open,
1371         .close =        snd_intel8x0_capture2_close,
1372         .ioctl =        snd_pcm_lib_ioctl,
1373         .hw_params =    snd_intel8x0_hw_params,
1374         .hw_free =      snd_intel8x0_hw_free,
1375         .prepare =      snd_intel8x0_pcm_prepare,
1376         .trigger =      snd_intel8x0_pcm_trigger,
1377         .pointer =      snd_intel8x0_pcm_pointer,
1378 };
1379
1380 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1381         .open =         snd_intel8x0_spdif_open,
1382         .close =        snd_intel8x0_spdif_close,
1383         .ioctl =        snd_pcm_lib_ioctl,
1384         .hw_params =    snd_intel8x0_hw_params,
1385         .hw_free =      snd_intel8x0_hw_free,
1386         .prepare =      snd_intel8x0_pcm_prepare,
1387         .trigger =      snd_intel8x0_pcm_trigger,
1388         .pointer =      snd_intel8x0_pcm_pointer,
1389 };
1390
1391 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1392         .open =         snd_intel8x0_playback_open,
1393         .close =        snd_intel8x0_playback_close,
1394         .ioctl =        snd_pcm_lib_ioctl,
1395         .hw_params =    snd_intel8x0_hw_params,
1396         .hw_free =      snd_intel8x0_hw_free,
1397         .prepare =      snd_intel8x0_pcm_prepare,
1398         .trigger =      snd_intel8x0_ali_trigger,
1399         .pointer =      snd_intel8x0_pcm_pointer,
1400 };
1401
1402 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1403         .open =         snd_intel8x0_capture_open,
1404         .close =        snd_intel8x0_capture_close,
1405         .ioctl =        snd_pcm_lib_ioctl,
1406         .hw_params =    snd_intel8x0_hw_params,
1407         .hw_free =      snd_intel8x0_hw_free,
1408         .prepare =      snd_intel8x0_pcm_prepare,
1409         .trigger =      snd_intel8x0_ali_trigger,
1410         .pointer =      snd_intel8x0_pcm_pointer,
1411 };
1412
1413 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1414         .open =         snd_intel8x0_mic_open,
1415         .close =        snd_intel8x0_mic_close,
1416         .ioctl =        snd_pcm_lib_ioctl,
1417         .hw_params =    snd_intel8x0_hw_params,
1418         .hw_free =      snd_intel8x0_hw_free,
1419         .prepare =      snd_intel8x0_pcm_prepare,
1420         .trigger =      snd_intel8x0_ali_trigger,
1421         .pointer =      snd_intel8x0_pcm_pointer,
1422 };
1423
1424 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1425         .open =         snd_intel8x0_ali_ac97spdifout_open,
1426         .close =        snd_intel8x0_ali_ac97spdifout_close,
1427         .ioctl =        snd_pcm_lib_ioctl,
1428         .hw_params =    snd_intel8x0_hw_params,
1429         .hw_free =      snd_intel8x0_hw_free,
1430         .prepare =      snd_intel8x0_pcm_prepare,
1431         .trigger =      snd_intel8x0_ali_trigger,
1432         .pointer =      snd_intel8x0_pcm_pointer,
1433 };
1434
1435 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1436         .open =         snd_intel8x0_ali_spdifin_open,
1437         .close =        snd_intel8x0_ali_spdifin_close,
1438         .ioctl =        snd_pcm_lib_ioctl,
1439         .hw_params =    snd_intel8x0_hw_params,
1440         .hw_free =      snd_intel8x0_hw_free,
1441         .prepare =      snd_intel8x0_pcm_prepare,
1442         .trigger =      snd_intel8x0_pcm_trigger,
1443         .pointer =      snd_intel8x0_pcm_pointer,
1444 };
1445
1446 #if 0 // NYI
1447 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1448         .open =         snd_intel8x0_ali_spdifout_open,
1449         .close =        snd_intel8x0_ali_spdifout_close,
1450         .ioctl =        snd_pcm_lib_ioctl,
1451         .hw_params =    snd_intel8x0_hw_params,
1452         .hw_free =      snd_intel8x0_hw_free,
1453         .prepare =      snd_intel8x0_pcm_prepare,
1454         .trigger =      snd_intel8x0_pcm_trigger,
1455         .pointer =      snd_intel8x0_pcm_pointer,
1456 };
1457 #endif // NYI
1458
1459 struct ich_pcm_table {
1460         char *suffix;
1461         snd_pcm_ops_t *playback_ops;
1462         snd_pcm_ops_t *capture_ops;
1463         size_t prealloc_size;
1464         size_t prealloc_max_size;
1465         int ac97_idx;
1466 };
1467
1468 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1469 {
1470         snd_pcm_t *pcm;
1471         int err;
1472         char name[32];
1473
1474         if (rec->suffix)
1475                 sprintf(name, "Intel ICH - %s", rec->suffix);
1476         else
1477                 strcpy(name, "Intel ICH");
1478         err = snd_pcm_new(chip->card, name, device,
1479                           rec->playback_ops ? 1 : 0,
1480                           rec->capture_ops ? 1 : 0, &pcm);
1481         if (err < 0)
1482                 return err;
1483
1484         if (rec->playback_ops)
1485                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1486         if (rec->capture_ops)
1487                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1488
1489         pcm->private_data = chip;
1490         pcm->info_flags = 0;
1491         if (rec->suffix)
1492                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1493         else
1494                 strcpy(pcm->name, chip->card->shortname);
1495         chip->pcm[device] = pcm;
1496
1497         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1498                                               rec->prealloc_size, rec->prealloc_max_size);
1499
1500         return 0;
1501 }
1502
1503 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1504         {
1505                 .playback_ops = &snd_intel8x0_playback_ops,
1506                 .capture_ops = &snd_intel8x0_capture_ops,
1507                 .prealloc_size = 64 * 1024,
1508                 .prealloc_max_size = 128 * 1024,
1509         },
1510         {
1511                 .suffix = "MIC ADC",
1512                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1513                 .prealloc_size = 0,
1514                 .prealloc_max_size = 128 * 1024,
1515                 .ac97_idx = ICHD_MIC,
1516         },
1517         {
1518                 .suffix = "MIC2 ADC",
1519                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1520                 .prealloc_size = 0,
1521                 .prealloc_max_size = 128 * 1024,
1522                 .ac97_idx = ICHD_MIC2,
1523         },
1524         {
1525                 .suffix = "ADC2",
1526                 .capture_ops = &snd_intel8x0_capture2_ops,
1527                 .prealloc_size = 0,
1528                 .prealloc_max_size = 128 * 1024,
1529                 .ac97_idx = ICHD_PCM2IN,
1530         },
1531         {
1532                 .suffix = "IEC958",
1533                 .playback_ops = &snd_intel8x0_spdif_ops,
1534                 .prealloc_size = 64 * 1024,
1535                 .prealloc_max_size = 128 * 1024,
1536                 .ac97_idx = ICHD_SPBAR,
1537         },
1538 };
1539
1540 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1541         {
1542                 .playback_ops = &snd_intel8x0_playback_ops,
1543                 .capture_ops = &snd_intel8x0_capture_ops,
1544                 .prealloc_size = 64 * 1024,
1545                 .prealloc_max_size = 128 * 1024,
1546         },
1547         {
1548                 .suffix = "MIC ADC",
1549                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1550                 .prealloc_size = 0,
1551                 .prealloc_max_size = 128 * 1024,
1552                 .ac97_idx = NVD_MIC,
1553         },
1554         {
1555                 .suffix = "IEC958",
1556                 .playback_ops = &snd_intel8x0_spdif_ops,
1557                 .prealloc_size = 64 * 1024,
1558                 .prealloc_max_size = 128 * 1024,
1559                 .ac97_idx = NVD_SPBAR,
1560         },
1561 };
1562
1563 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1564         {
1565                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1566                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1567                 .prealloc_size = 64 * 1024,
1568                 .prealloc_max_size = 128 * 1024,
1569         },
1570         {
1571                 .suffix = "MIC ADC",
1572                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1573                 .prealloc_size = 0,
1574                 .prealloc_max_size = 128 * 1024,
1575                 .ac97_idx = ALID_MIC,
1576         },
1577         {
1578                 .suffix = "IEC958",
1579                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1580                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1581                 .prealloc_size = 64 * 1024,
1582                 .prealloc_max_size = 128 * 1024,
1583                 .ac97_idx = ALID_AC97SPDIFOUT,
1584         },
1585 #if 0 // NYI
1586         {
1587                 .suffix = "HW IEC958",
1588                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1589                 .prealloc_size = 64 * 1024,
1590                 .prealloc_max_size = 128 * 1024,
1591         },
1592 #endif
1593 };
1594
1595 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1596 {
1597         int i, tblsize, device, err;
1598         struct ich_pcm_table *tbl, *rec;
1599
1600         switch (chip->device_type) {
1601         case DEVICE_INTEL_ICH4:
1602                 tbl = intel_pcms;
1603                 tblsize = ARRAY_SIZE(intel_pcms);
1604                 break;
1605         case DEVICE_NFORCE:
1606                 tbl = nforce_pcms;
1607                 tblsize = ARRAY_SIZE(nforce_pcms);
1608                 break;
1609         case DEVICE_ALI:
1610                 tbl = ali_pcms;
1611                 tblsize = ARRAY_SIZE(ali_pcms);
1612                 break;
1613         default:
1614                 tbl = intel_pcms;
1615                 tblsize = 2;
1616                 break;
1617         }
1618
1619         device = 0;
1620         for (i = 0; i < tblsize; i++) {
1621                 rec = tbl + i;
1622                 if (i > 0 && rec->ac97_idx) {
1623                         /* activate PCM only when associated AC'97 codec */
1624                         if (! chip->ichd[rec->ac97_idx].pcm)
1625                                 continue;
1626                 }
1627                 err = snd_intel8x0_pcm1(chip, device, rec);
1628                 if (err < 0)
1629                         return err;
1630                 device++;
1631         }
1632
1633         chip->pcm_devs = device;
1634         return 0;
1635 }
1636
1637
1638 /*
1639  *  Mixer part
1640  */
1641
1642 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1643 {
1644         intel8x0_t *chip = bus->private_data;
1645         chip->ac97_bus = NULL;
1646 }
1647
1648 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1649 {
1650         intel8x0_t *chip = ac97->private_data;
1651         chip->ac97[ac97->num] = NULL;
1652 }
1653
1654 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1655         /* front PCM */
1656         {
1657                 .exclusive = 1,
1658                 .r = {  {
1659                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1660                                          (1 << AC97_SLOT_PCM_RIGHT) |
1661                                          (1 << AC97_SLOT_PCM_CENTER) |
1662                                          (1 << AC97_SLOT_PCM_SLEFT) |
1663                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1664                                          (1 << AC97_SLOT_LFE)
1665                         }
1666                 }
1667         },
1668         /* PCM IN #1 */
1669         {
1670                 .stream = 1,
1671                 .exclusive = 1,
1672                 .r = {  {
1673                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1674                                          (1 << AC97_SLOT_PCM_RIGHT)
1675                         }
1676                 }
1677         },
1678         /* MIC IN #1 */
1679         {
1680                 .stream = 1,
1681                 .exclusive = 1,
1682                 .r = {  {
1683                                 .slots = (1 << AC97_SLOT_MIC)
1684                         }
1685                 }
1686         },
1687         /* S/PDIF PCM */
1688         {
1689                 .exclusive = 1,
1690                 .spdif = 1,
1691                 .r = {  {
1692                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1693                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1694                         }
1695                 }
1696         },
1697         /* PCM IN #2 */
1698         {
1699                 .stream = 1,
1700                 .exclusive = 1,
1701                 .r = {  {
1702                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1703                                          (1 << AC97_SLOT_PCM_RIGHT)
1704                         }
1705                 }
1706         },
1707         /* MIC IN #2 */
1708         {
1709                 .stream = 1,
1710                 .exclusive = 1,
1711                 .r = {  {
1712                                 .slots = (1 << AC97_SLOT_MIC)
1713                         }
1714                 }
1715         },
1716 };
1717
1718 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1719         {
1720                 .vendor = 0x0e11,
1721                 .device = 0x00b8,
1722                 .name = "Compaq Evo D510C",
1723                 .type = AC97_TUNE_HP_ONLY
1724         },
1725         {
1726                 .vendor = 0x1014,
1727                 .device = 0x1f00,
1728                 .name = "MS-9128",
1729                 .type = AC97_TUNE_ALC_JACK
1730         },
1731         {
1732                 .vendor = 0x1028,
1733                 .device = 0x00d8,
1734                 .name = "Dell Precision 530",   /* AD1885 */
1735                 .type = AC97_TUNE_HP_ONLY
1736         },
1737         {
1738                 .vendor = 0x1028,
1739                 .device = 0x0126,
1740                 .name = "Dell Optiplex GX260",  /* AD1981A */
1741                 .type = AC97_TUNE_HP_ONLY
1742         },
1743         {
1744                 .vendor = 0x1028,
1745                 .device = 0x012d,
1746                 .name = "Dell Precision 450",   /* AD1981B*/
1747                 .type = AC97_TUNE_HP_ONLY
1748         },
1749         {       /* FIXME: which codec? */
1750                 .vendor = 0x103c,
1751                 .device = 0x00c3,
1752                 .name = "Hewlett-Packard onboard",
1753                 .type = AC97_TUNE_HP_ONLY
1754         },
1755         {
1756                 .vendor = 0x103c,
1757                 .device = 0x12f1,
1758                 .name = "HP xw8200",    /* AD1981B*/
1759                 .type = AC97_TUNE_HP_ONLY
1760         },
1761         {
1762                 .vendor = 0x103c,
1763                 .device = 0x3008,
1764                 .name = "HP xw4200",    /* AD1981B*/
1765                 .type = AC97_TUNE_HP_ONLY
1766         },
1767         {
1768                 .vendor = 0x1043,
1769                 .device = 0x80f3,
1770                 .name = "ASUS ICH5/AD1985",
1771                 .type = AC97_TUNE_AD_SHARING
1772         },
1773         {
1774                 .vendor = 0x10f1,
1775                 .device = 0x2665,
1776                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1777                 .type = AC97_TUNE_HP_ONLY
1778         },
1779         {
1780                 .vendor = 0x10f1,
1781                 .device = 0x2885,
1782                 .name = "AMD64 Mobo",   /* ALC650 */
1783                 .type = AC97_TUNE_HP_ONLY
1784         },
1785         {
1786                 .vendor = 0x110a,
1787                 .device = 0x0056,
1788                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1789                 .type = AC97_TUNE_HP_ONLY
1790         },
1791         {
1792                 .vendor = 0x11d4,
1793                 .device = 0x5375,
1794                 .name = "ADI AD1985 (discrete)",
1795                 .type = AC97_TUNE_HP_ONLY
1796         },
1797         {
1798                 .vendor = 0x1462,
1799                 .device = 0x5470,
1800                 .name = "MSI P4 ATX 645 Ultra",
1801                 .type = AC97_TUNE_HP_ONLY
1802         },
1803         {
1804                 .vendor = 0x1734,
1805                 .device = 0x0088,
1806                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1807                 .type = AC97_TUNE_HP_ONLY
1808         },
1809         {
1810                 .vendor = 0x8086,
1811                 .device = 0x2000,
1812                 .mask = 0xfff0,
1813                 .name = "Intel ICH5/AD1985",
1814                 .type = AC97_TUNE_AD_SHARING
1815         },
1816         {
1817                 .vendor = 0x8086,
1818                 .device = 0x4000,
1819                 .mask = 0xfff0,
1820                 .name = "Intel ICH5/AD1985",
1821                 .type = AC97_TUNE_AD_SHARING
1822         },
1823         {
1824                 .vendor = 0x8086,
1825                 .device = 0x4856,
1826                 .name = "Intel D845WN (82801BA)",
1827                 .type = AC97_TUNE_SWAP_HP
1828         },
1829         {
1830                 .vendor = 0x8086,
1831                 .device = 0x4d44,
1832                 .name = "Intel D850EMV2",       /* AD1885 */
1833                 .type = AC97_TUNE_HP_ONLY
1834         },
1835         {
1836                 .vendor = 0x8086,
1837                 .device = 0x4d56,
1838                 .name = "Intel ICH/AD1885",
1839                 .type = AC97_TUNE_HP_ONLY
1840         },
1841         {
1842                 .vendor = 0x8086,
1843                 .device = 0x6000,
1844                 .mask = 0xfff0,
1845                 .name = "Intel ICH5/AD1985",
1846                 .type = AC97_TUNE_AD_SHARING
1847         },
1848         {
1849                 .vendor = 0x8086,
1850                 .device = 0xe000,
1851                 .mask = 0xfff0,
1852                 .name = "Intel ICH5/AD1985",
1853                 .type = AC97_TUNE_AD_SHARING
1854         },
1855 #if 0 /* FIXME: this seems wrong on most boards */
1856         {
1857                 .vendor = 0x8086,
1858                 .device = 0xa000,
1859                 .mask = 0xfff0,
1860                 .name = "Intel ICH5/AD1985",
1861                 .type = AC97_TUNE_HP_ONLY
1862         },
1863 #endif
1864         { } /* terminator */
1865 };
1866
1867 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, int ac97_quirk)
1868 {
1869         ac97_bus_t *pbus;
1870         ac97_template_t ac97;
1871         int err;
1872         unsigned int i, codecs;
1873         unsigned int glob_sta = 0;
1874         int spdif_idx = -1; /* disabled */
1875         ac97_bus_ops_t *ops;
1876         static ac97_bus_ops_t standard_bus_ops = {
1877                 .write = snd_intel8x0_codec_write,
1878                 .read = snd_intel8x0_codec_read,
1879         };
1880         static ac97_bus_ops_t ali_bus_ops = {
1881                 .write = snd_intel8x0_ali_codec_write,
1882                 .read = snd_intel8x0_ali_codec_read,
1883         };
1884
1885         switch (chip->device_type) {
1886         case DEVICE_NFORCE:
1887                 spdif_idx = NVD_SPBAR;
1888                 break;
1889         case DEVICE_ALI:
1890                 spdif_idx = ALID_AC97SPDIFOUT;
1891                 break;
1892         default:
1893                 if (chip->device_type == DEVICE_INTEL_ICH4)
1894                         spdif_idx = ICHD_SPBAR;
1895                 break;
1896         };
1897
1898         chip->in_ac97_init = 1;
1899
1900         memset(&ac97, 0, sizeof(ac97));
1901         ac97.private_data = chip;
1902         ac97.private_free = snd_intel8x0_mixer_free_ac97;
1903         ac97.scaps = AC97_SCAP_SKIP_MODEM;
1904         if (chip->device_type != DEVICE_ALI) {
1905                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1906                 ops = &standard_bus_ops;
1907                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1908                         codecs = 0;
1909                         if (glob_sta & ICH_PCR)
1910                                 codecs++;
1911                         if (glob_sta & ICH_SCR)
1912                                 codecs++;
1913                         if (glob_sta & ICH_TCR)
1914                                 codecs++;
1915                         chip->in_sdin_init = 1;
1916                         for (i = 0; i < codecs; i++) {
1917                                 snd_intel8x0_codec_read_test(chip, i);
1918                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1919                         }
1920                         chip->in_sdin_init = 0;
1921                 } else {
1922                         codecs = glob_sta & ICH_SCR ? 2 : 1;
1923                 }
1924         } else {
1925                 ops = &ali_bus_ops;
1926                 codecs = 1;
1927                 /* detect the secondary codec */
1928                 for (i = 0; i < 100; i++) {
1929                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1930                         if (reg & 0x40) {
1931                                 codecs = 2;
1932                                 break;
1933                         }
1934                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
1935                         udelay(1);
1936                 }
1937         }
1938         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
1939                 goto __err;
1940         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1941         pbus->shared_type = AC97_SHARED_TYPE_ICH;       /* shared with modem driver */
1942         if (ac97_clock >= 8000 && ac97_clock <= 48000)
1943                 pbus->clock = ac97_clock;
1944         /* FIXME: my test board doesn't work well with VRA... */
1945         if (chip->device_type == DEVICE_ALI)
1946                 pbus->no_vra = 1;
1947         chip->ac97_bus = pbus;
1948
1949         ac97.pci = chip->pci;
1950         for (i = 0; i < codecs; i++) {
1951                 ac97.num = i;
1952                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1953                         if (err != -EACCES)
1954                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
1955                         if (i == 0)
1956                                 goto __err;
1957                         continue;
1958                 }
1959         }
1960         /* tune up the primary codec */
1961         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, ac97_quirk);
1962         /* enable separate SDINs for ICH4 */
1963         if (chip->device_type == DEVICE_INTEL_ICH4)
1964                 pbus->isdin = 1;
1965         /* find the available PCM streams */
1966         i = ARRAY_SIZE(ac97_pcm_defs);
1967         if (chip->device_type != DEVICE_INTEL_ICH4)
1968                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
1969         if (spdif_idx < 0)
1970                 i--;            /* do not allocate S/PDIF */
1971         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
1972         if (err < 0)
1973                 goto __err;
1974         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
1975         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
1976         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
1977         if (spdif_idx >= 0)
1978                 chip->ichd[spdif_idx].pcm = &pbus->pcms[3];
1979         if (chip->device_type == DEVICE_INTEL_ICH4) {
1980                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
1981                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
1982         }
1983         /* enable separate SDINs for ICH4 */
1984         if (chip->device_type == DEVICE_INTEL_ICH4) {
1985                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
1986                 u8 tmp = igetbyte(chip, ICHREG(SDM));
1987                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
1988                 if (pcm) {
1989                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
1990                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
1991                         for (i = 1; i < 4; i++) {
1992                                 if (pcm->r[0].codec[i]) {
1993                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
1994                                         break;
1995                                 }
1996                         }
1997                 } else {
1998                         tmp &= ~ICH_SE; /* steer disable */
1999                 }
2000                 iputbyte(chip, ICHREG(SDM), tmp);
2001         }
2002         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2003                 chip->multi4 = 1;
2004                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2005                         chip->multi6 = 1;
2006         }
2007         if (chip->device_type == DEVICE_INTEL_ICH4) {
2008                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2009                         chip->smp20bit = 1;
2010         }
2011         if (chip->device_type == DEVICE_NFORCE) {
2012                 /* 48kHz only */
2013                 chip->ichd[spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2014         }
2015         chip->in_ac97_init = 0;
2016         return 0;
2017
2018  __err:
2019         /* clear the cold-reset bit for the next chance */
2020         if (chip->device_type != DEVICE_ALI)
2021                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2022         return err;
2023 }
2024
2025
2026 /*
2027  *
2028  */
2029
2030 static void do_ali_reset(intel8x0_t *chip)
2031 {
2032         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2033         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2034         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2035         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2036         iputdword(chip, ICHREG(ALI_INTERFACECR),
2037                   ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2038         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2039         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2040 }
2041
2042 #define do_delay(chip) do {\
2043         set_current_state(TASK_UNINTERRUPTIBLE);\
2044         schedule_timeout(1);\
2045 } while (0)
2046
2047 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2048 {
2049         unsigned long end_time;
2050         unsigned int cnt, status, nstatus;
2051
2052         /* put logic to right state */
2053         /* first clear status bits */
2054         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2055         if (chip->device_type == DEVICE_NFORCE)
2056                 status |= ICH_NVSPINT;
2057         cnt = igetdword(chip, ICHREG(GLOB_STA));
2058         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2059
2060         /* ACLink on, 2 channels */
2061         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2062         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2063         /* finish cold or do warm reset */
2064         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2065         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2066         end_time = (jiffies + (HZ / 4)) + 1;
2067         do {
2068                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2069                         goto __ok;
2070                 do_delay(chip);
2071         } while (time_after_eq(end_time, jiffies));
2072         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2073         return -EIO;
2074
2075       __ok:
2076         if (probing) {
2077                 /* wait for any codec ready status.
2078                  * Once it becomes ready it should remain ready
2079                  * as long as we do not disable the ac97 link.
2080                  */
2081                 end_time = jiffies + HZ;
2082                 do {
2083                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2084                         if (status)
2085                                 break;
2086                         do_delay(chip);
2087                 } while (time_after_eq(end_time, jiffies));
2088                 if (! status) {
2089                         /* no codec is found */
2090                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2091                         return -EIO;
2092                 }
2093
2094                 if (chip->device_type == DEVICE_INTEL_ICH4)
2095                         /* ICH4 can have three codecs */
2096                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2097                 else
2098                         /* others up to two codecs */
2099                         nstatus = ICH_PCR | ICH_SCR;
2100
2101                 /* wait for other codecs ready status. */
2102                 end_time = jiffies + HZ / 4;
2103                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2104                         do_delay(chip);
2105                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2106                 }
2107
2108         } else {
2109                 /* resume phase */
2110                 int i;
2111                 status = 0;
2112                 for (i = 0; i < 3; i++)
2113                         if (chip->ac97[i])
2114                                 status |= get_ich_codec_bit(chip, i);
2115                 /* wait until all the probed codecs are ready */
2116                 end_time = jiffies + HZ;
2117                 do {
2118                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2119                         if (status == nstatus)
2120                                 break;
2121                         do_delay(chip);
2122                 } while (time_after_eq(end_time, jiffies));
2123         }
2124
2125         if (chip->device_type == DEVICE_SIS) {
2126                 /* unmute the output on SIS7012 */
2127                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2128         }
2129         if (chip->device_type == DEVICE_NFORCE) {
2130                 /* enable SPDIF interrupt */
2131                 unsigned int val;
2132                 pci_read_config_dword(chip->pci, 0x4c, &val);
2133                 val |= 0x1000000;
2134                 pci_write_config_dword(chip->pci, 0x4c, val);
2135         }
2136         return 0;
2137 }
2138
2139 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2140 {
2141         u32 reg;
2142         int i = 0;
2143
2144         reg = igetdword(chip, ICHREG(ALI_SCR));
2145         if ((reg & 2) == 0)     /* Cold required */
2146                 reg |= 2;
2147         else
2148                 reg |= 1;       /* Warm */
2149         reg &= ~0x80000000;     /* ACLink on */
2150         iputdword(chip, ICHREG(ALI_SCR), reg);
2151
2152         for (i = 0; i < HZ / 2; i++) {
2153                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2154                         goto __ok;
2155                 do_delay(chip);
2156         }
2157         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2158         if (probing)
2159                 return -EIO;
2160
2161  __ok:
2162         for (i = 0; i < HZ / 2; i++) {
2163                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2164                 if (reg & 0x80) /* primary codec */
2165                         break;
2166                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2167                 do_delay(chip);
2168         }
2169
2170         do_ali_reset(chip);
2171         return 0;
2172 }
2173
2174 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2175 {
2176         unsigned int i;
2177         int err;
2178
2179         if (chip->device_type != DEVICE_ALI) {
2180                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2181                         return err;
2182                 iagetword(chip, 0);     /* clear semaphore flag */
2183         } else {
2184                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2185                         return err;
2186         }
2187
2188         /* disable interrupts */
2189         for (i = 0; i < chip->bdbars_count; i++)
2190                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2191         /* reset channels */
2192         for (i = 0; i < chip->bdbars_count; i++)
2193                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2194         /* initialize Buffer Descriptor Lists */
2195         for (i = 0; i < chip->bdbars_count; i++)
2196                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2197         return 0;
2198 }
2199
2200 static int snd_intel8x0_free(intel8x0_t *chip)
2201 {
2202         unsigned int i;
2203
2204         if (chip->irq < 0)
2205                 goto __hw_end;
2206         /* disable interrupts */
2207         for (i = 0; i < chip->bdbars_count; i++)
2208                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2209         /* reset channels */
2210         for (i = 0; i < chip->bdbars_count; i++)
2211                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2212         if (chip->device_type == DEVICE_NFORCE) {
2213                 /* stop the spdif interrupt */
2214                 unsigned int val;
2215                 pci_read_config_dword(chip->pci, 0x4c, &val);
2216                 val &= ~0x1000000;
2217                 pci_write_config_dword(chip->pci, 0x4c, val);
2218         }
2219         /* --- */
2220         synchronize_irq(chip->irq);
2221       __hw_end:
2222         if (chip->irq >= 0)
2223                 free_irq(chip->irq, (void *)chip);
2224         if (chip->bdbars.area) {
2225                 if (chip->fix_nocache)
2226                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2227                 snd_dma_free_pages(&chip->bdbars);
2228         }
2229         if (chip->remap_addr)
2230                 iounmap(chip->remap_addr);
2231         if (chip->remap_bmaddr)
2232                 iounmap(chip->remap_bmaddr);
2233         pci_release_regions(chip->pci);
2234         kfree(chip);
2235         return 0;
2236 }
2237
2238 #ifdef CONFIG_PM
2239 /*
2240  * power management
2241  */
2242 static int intel8x0_suspend(snd_card_t *card, unsigned int state)
2243 {
2244         intel8x0_t *chip = card->pm_private_data;
2245         int i;
2246
2247         for (i = 0; i < chip->pcm_devs; i++)
2248                 snd_pcm_suspend_all(chip->pcm[i]);
2249         for (i = 0; i < 3; i++)
2250                 if (chip->ac97[i])
2251                         snd_ac97_suspend(chip->ac97[i]);
2252         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2253         return 0;
2254 }
2255
2256 static int intel8x0_resume(snd_card_t *card, unsigned int state)
2257 {
2258         intel8x0_t *chip = card->pm_private_data;
2259         int i;
2260
2261         pci_enable_device(chip->pci);
2262         pci_set_master(chip->pci);
2263         snd_intel8x0_chip_init(chip, 0);
2264
2265         /* refill nocache */
2266         if (chip->fix_nocache)
2267                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2268
2269         for (i = 0; i < 3; i++)
2270                 if (chip->ac97[i])
2271                         snd_ac97_resume(chip->ac97[i]);
2272
2273         /* refill nocache */
2274         if (chip->fix_nocache) {
2275                 for (i = 0; i < chip->bdbars_count; i++) {
2276                         ichdev_t *ichdev = &chip->ichd[i];
2277                         if (ichdev->substream) {
2278                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2279                                 if (runtime->dma_area)
2280                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2281                         }
2282                 }
2283         }
2284
2285         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2286         return 0;
2287 }
2288 #endif /* CONFIG_PM */
2289
2290 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2291
2292 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2293 {
2294         snd_pcm_substream_t *subs;
2295         ichdev_t *ichdev;
2296         unsigned long port;
2297         unsigned long pos, t;
2298         struct timeval start_time, stop_time;
2299
2300         if (chip->ac97_bus->clock != 48000)
2301                 return; /* specified in module option */
2302
2303         subs = chip->pcm[0]->streams[0].substream;
2304         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2305                 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2306                 return;
2307         }
2308         ichdev = &chip->ichd[ICHD_PCMOUT];
2309         ichdev->physbuf = subs->dma_buffer.addr;
2310         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2311         ichdev->substream = NULL; /* don't process interrupts */
2312
2313         /* set rate */
2314         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2315                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2316                 return;
2317         }
2318         snd_intel8x0_setup_periods(chip, ichdev);
2319         port = ichdev->reg_offset;
2320         spin_lock_irq(&chip->reg_lock);
2321         /* trigger */
2322         if (chip->device_type != DEVICE_ALI)
2323                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2324         else {
2325                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2326                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2327         }
2328         do_gettimeofday(&start_time);
2329         spin_unlock_irq(&chip->reg_lock);
2330 #if 0
2331         set_current_state(TASK_UNINTERRUPTIBLE);
2332         schedule_timeout(HZ / 20);
2333 #else
2334         /* FIXME: schedule() can take too long time and overlap the boundary.. */
2335         mdelay(50);
2336 #endif
2337         spin_lock_irq(&chip->reg_lock);
2338         /* check the position */
2339         pos = ichdev->fragsize1;
2340         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2341         pos += ichdev->position;
2342         do_gettimeofday(&stop_time);
2343         /* stop */
2344         if (chip->device_type == DEVICE_ALI) {
2345                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2346                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2347                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2348                         ;
2349         } else {
2350                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2351                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2352                         ;
2353         }
2354         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2355         spin_unlock_irq(&chip->reg_lock);
2356
2357         t = stop_time.tv_sec - start_time.tv_sec;
2358         t *= 1000000;
2359         t += stop_time.tv_usec - start_time.tv_usec;
2360         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2361         if (t == 0) {
2362                 snd_printk(KERN_ERR "?? calculation error..\n");
2363                 return;
2364         }
2365         pos = (pos / 4) * 1000;
2366         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2367         if (pos < 40000 || pos >= 60000)
2368                 /* abnormal value. hw problem? */
2369                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2370         else if (pos < 47500 || pos > 48500)
2371                 /* not 48000Hz, tuning the clock.. */
2372                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2373         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2374 }
2375
2376 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2377                                    snd_info_buffer_t * buffer)
2378 {
2379         intel8x0_t *chip = entry->private_data;
2380         unsigned int tmp;
2381
2382         snd_iprintf(buffer, "Intel8x0\n\n");
2383         if (chip->device_type == DEVICE_ALI)
2384                 return;
2385         tmp = igetdword(chip, ICHREG(GLOB_STA));
2386         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2387         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2388         if (chip->device_type == DEVICE_INTEL_ICH4)
2389                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2390         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2391                         tmp & ICH_PCR ? " primary" : "",
2392                         tmp & ICH_SCR ? " secondary" : "",
2393                         tmp & ICH_TCR ? " tertiary" : "",
2394                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2395         if (chip->device_type == DEVICE_INTEL_ICH4)
2396                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2397                         chip->ac97_sdin[0],
2398                         chip->ac97_sdin[1],
2399                         chip->ac97_sdin[2]);
2400 }
2401
2402 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2403 {
2404         snd_info_entry_t *entry;
2405
2406         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2407                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2408 }
2409
2410 static int snd_intel8x0_dev_free(snd_device_t *device)
2411 {
2412         intel8x0_t *chip = device->device_data;
2413         return snd_intel8x0_free(chip);
2414 }
2415
2416 struct ich_reg_info {
2417         unsigned int int_sta_mask;
2418         unsigned int offset;
2419 };
2420
2421 static int __devinit snd_intel8x0_create(snd_card_t * card,
2422                                          struct pci_dev *pci,
2423                                          unsigned long device_type,
2424                                          intel8x0_t ** r_intel8x0)
2425 {
2426         intel8x0_t *chip;
2427         int err;
2428         unsigned int i;
2429         unsigned int int_sta_masks;
2430         ichdev_t *ichdev;
2431         static snd_device_ops_t ops = {
2432                 .dev_free =     snd_intel8x0_dev_free,
2433         };
2434
2435         static unsigned int bdbars[] = {
2436                 3, /* DEVICE_INTEL */
2437                 6, /* DEVICE_INTEL_ICH4 */
2438                 3, /* DEVICE_SIS */
2439                 6, /* DEVICE_ALI */
2440                 4, /* DEVICE_NFORCE */
2441         };
2442         static struct ich_reg_info intel_regs[6] = {
2443                 { ICH_PIINT, 0 },
2444                 { ICH_POINT, 0x10 },
2445                 { ICH_MCINT, 0x20 },
2446                 { ICH_M2INT, 0x40 },
2447                 { ICH_P2INT, 0x50 },
2448                 { ICH_SPINT, 0x60 },
2449         };
2450         static struct ich_reg_info nforce_regs[4] = {
2451                 { ICH_PIINT, 0 },
2452                 { ICH_POINT, 0x10 },
2453                 { ICH_MCINT, 0x20 },
2454                 { ICH_NVSPINT, 0x70 },
2455         };
2456         static struct ich_reg_info ali_regs[6] = {
2457                 { ALI_INT_PCMIN, 0x40 },
2458                 { ALI_INT_PCMOUT, 0x50 },
2459                 { ALI_INT_MICIN, 0x60 },
2460                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2461                 { ALI_INT_SPDIFIN, 0xa0 },
2462                 { ALI_INT_SPDIFOUT, 0xb0 },
2463         };
2464         struct ich_reg_info *tbl;
2465
2466         *r_intel8x0 = NULL;
2467
2468         if ((err = pci_enable_device(pci)) < 0)
2469                 return err;
2470
2471         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2472         if (chip == NULL)
2473                 return -ENOMEM;
2474         spin_lock_init(&chip->reg_lock);
2475         spin_lock_init(&chip->ac97_lock);
2476         chip->device_type = device_type;
2477         chip->card = card;
2478         chip->pci = pci;
2479         chip->irq = -1;
2480
2481         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2482             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2483                 chip->fix_nocache = 1; /* enable workaround */
2484
2485         /* some Nforce[2] and ICH boards have problems with IRQ handling.
2486          * Needs to return IRQ_HANDLED for unknown irqs.
2487          */
2488         if (device_type == DEVICE_NFORCE)
2489                 chip->buggy_irq = 1;
2490
2491         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2492                 kfree(chip);
2493                 return err;
2494         }
2495
2496         if (device_type == DEVICE_ALI) {
2497                 /* ALI5455 has no ac97 region */
2498                 chip->bmaddr = pci_resource_start(pci, 0);
2499                 goto port_inited;
2500         }
2501
2502         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2503                 chip->mmio = 1;
2504                 chip->addr = pci_resource_start(pci, 2);
2505                 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 2));
2506                 if (!chip->remap_addr) {
2507                         snd_printk("AC'97 space ioremap problem\n");
2508                         snd_intel8x0_free(chip);
2509                         return -EIO;
2510                 }
2511         } else {
2512                 chip->addr = pci_resource_start(pci, 0);
2513         }
2514         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2515                 chip->bm_mmio = 1;
2516                 chip->bmaddr = pci_resource_start(pci, 3);
2517                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, pci_resource_len(pci, 3));
2518                 if (!chip->remap_bmaddr) {
2519                         snd_printk("Controller space ioremap problem\n");
2520                         snd_intel8x0_free(chip);
2521                         return -EIO;
2522                 }
2523         } else {
2524                 chip->bmaddr = pci_resource_start(pci, 1);
2525         }
2526
2527  port_inited:
2528         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2529                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2530                 snd_intel8x0_free(chip);
2531                 return -EBUSY;
2532         }
2533         chip->irq = pci->irq;
2534         pci_set_master(pci);
2535         synchronize_irq(chip->irq);
2536
2537         chip->bdbars_count = bdbars[device_type];
2538
2539         /* initialize offsets */
2540         switch (device_type) {
2541         case DEVICE_NFORCE:
2542                 tbl = nforce_regs;
2543                 break;
2544         case DEVICE_ALI:
2545                 tbl = ali_regs;
2546                 break;
2547         default:
2548                 tbl = intel_regs;
2549                 break;
2550         }
2551         for (i = 0; i < chip->bdbars_count; i++) {
2552                 ichdev = &chip->ichd[i];
2553                 ichdev->ichd = i;
2554                 ichdev->reg_offset = tbl[i].offset;
2555                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2556                 if (device_type == DEVICE_SIS) {
2557                         /* SiS 7012 swaps the registers */
2558                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2559                         ichdev->roff_picb = ICH_REG_OFF_SR;
2560                 } else {
2561                         ichdev->roff_sr = ICH_REG_OFF_SR;
2562                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2563                 }
2564                 if (device_type == DEVICE_ALI)
2565                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2566                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2567                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2568         }
2569
2570         /* allocate buffer descriptor lists */
2571         /* the start of each lists must be aligned to 8 bytes */
2572         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2573                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2574                                 &chip->bdbars) < 0) {
2575                 snd_intel8x0_free(chip);
2576                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2577                 return -ENOMEM;
2578         }
2579         /* tables must be aligned to 8 bytes here, but the kernel pages
2580            are much bigger, so we don't care (on i386) */
2581         /* workaround for 440MX */
2582         if (chip->fix_nocache)
2583                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2584         int_sta_masks = 0;
2585         for (i = 0; i < chip->bdbars_count; i++) {
2586                 ichdev = &chip->ichd[i];
2587                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2588                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2589                 int_sta_masks |= ichdev->int_sta_mask;
2590         }
2591         chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2592         chip->int_sta_mask = int_sta_masks;
2593
2594         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2595                 snd_intel8x0_free(chip);
2596                 return err;
2597         }
2598
2599         snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2600
2601         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2602                 snd_intel8x0_free(chip);
2603                 return err;
2604         }
2605
2606         snd_card_set_dev(card, &pci->dev);
2607
2608         *r_intel8x0 = chip;
2609         return 0;
2610 }
2611
2612 static struct shortname_table {
2613         unsigned int id;
2614         const char *s;
2615 } shortnames[] __devinitdata = {
2616         { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2617         { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2618         { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2619         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2620         { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2621         { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2622         { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2623         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2624         { PCI_DEVICE_ID_INTEL_ICH6_3, "Intel ICH6" },
2625         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2626         { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2627         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2628         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2629         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2630         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2631         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2632         { 0x003a, "NVidia MCP04" },
2633         { 0x746d, "AMD AMD8111" },
2634         { 0x7445, "AMD AMD768" },
2635         { 0x5455, "ALi M5455" },
2636         { 0, NULL },
2637 };
2638
2639 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2640                                         const struct pci_device_id *pci_id)
2641 {
2642         static int dev;
2643         snd_card_t *card;
2644         intel8x0_t *chip;
2645         int err;
2646         struct shortname_table *name;
2647
2648         if (dev >= SNDRV_CARDS)
2649                 return -ENODEV;
2650         if (!enable[dev]) {
2651                 dev++;
2652                 return -ENOENT;
2653         }
2654
2655         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2656         if (card == NULL)
2657                 return -ENOMEM;
2658
2659         switch (pci_id->driver_data) {
2660         case DEVICE_NFORCE:
2661                 strcpy(card->driver, "NFORCE");
2662                 break;
2663         default:
2664                 strcpy(card->driver, "ICH");
2665                 break;
2666         }
2667
2668         strcpy(card->shortname, "Intel ICH");
2669         for (name = shortnames; name->id; name++) {
2670                 if (pci->device == name->id) {
2671                         strcpy(card->shortname, name->s);
2672                         break;
2673                 }
2674         }
2675
2676         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2677                 snd_card_free(card);
2678                 return err;
2679         }
2680         if (buggy_irq[dev])
2681                 chip->buggy_irq = 1;
2682
2683         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2684                 snd_card_free(card);
2685                 return err;
2686         }
2687         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2688                 snd_card_free(card);
2689                 return err;
2690         }
2691
2692         if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2693                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
2694                                                mpu_port[dev], 0,
2695                                                -1, 0, &chip->rmidi)) < 0) {
2696                         printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
2697                         mpu_port[dev] = 0;
2698                 }
2699         } else
2700                 mpu_port[dev] = 0;
2701
2702         snd_intel8x0_proc_init(chip);
2703
2704         sprintf(card->longname, "%s at 0x%lx, irq %i",
2705                 card->shortname, chip->addr, chip->irq);
2706
2707         if (! ac97_clock[dev])
2708                 intel8x0_measure_ac97_clock(chip);
2709
2710         if ((err = snd_card_register(card)) < 0) {
2711                 snd_card_free(card);
2712                 return err;
2713         }
2714         pci_set_drvdata(pci, card);
2715         dev++;
2716         return 0;
2717 }
2718
2719 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2720 {
2721         snd_card_free(pci_get_drvdata(pci));
2722         pci_set_drvdata(pci, NULL);
2723 }
2724
2725 static struct pci_driver driver = {
2726         .name = "Intel ICH",
2727         .id_table = snd_intel8x0_ids,
2728         .probe = snd_intel8x0_probe,
2729         .remove = __devexit_p(snd_intel8x0_remove),
2730         SND_PCI_PM_CALLBACKS
2731 };
2732
2733
2734 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2735 /*
2736  * initialize joystick/midi addresses
2737  */
2738
2739 #ifdef SUPPORT_JOYSTICK
2740 /* there is only one available device, so we keep it here */
2741 static struct pci_dev *ich_gameport_pci;
2742 static struct gameport ich_gameport = { .io = 0x200 };
2743 #endif
2744
2745 static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
2746                                                  const struct pci_device_id *id)
2747 {
2748         u16 val;
2749         static int dev;
2750         if (dev >= SNDRV_CARDS)
2751                 return -ENODEV;
2752         if (!enable[dev]) {
2753                 dev++;
2754                 return -ENOENT;
2755         }
2756
2757         pci_read_config_word(pci, 0xe6, &val);
2758 #ifdef SUPPORT_JOYSTICK
2759         val &= ~0x100;
2760         if (joystick[dev]) {
2761                 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
2762                         printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n",  ich_gameport.io);
2763                         joystick[dev] = 0;
2764                 } else {
2765                         ich_gameport_pci = pci;
2766                         gameport_register_port(&ich_gameport);
2767                         val |= 0x100;
2768                 }
2769         }
2770 #endif
2771 #ifdef SUPPORT_MIDI
2772         val &= ~0x20;
2773         if (mpu_port[dev] > 0) {
2774                 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2775                         u8 b;
2776                         val |= 0x20;
2777                         pci_read_config_byte(pci, 0xe2, &b);
2778                         if (mpu_port[dev] == 0x300)
2779                                 b |= 0x08;
2780                         else
2781                                 b &= ~0x08;
2782                         pci_write_config_byte(pci, 0xe2, b);
2783                 }
2784         }
2785 #endif
2786         pci_write_config_word(pci, 0xe6, val);
2787         return 0;
2788 }
2789
2790 static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
2791 {
2792         u16 val;
2793 #ifdef SUPPORT_JOYSTICK
2794         if (ich_gameport_pci == pci) {
2795                 gameport_unregister_port(&ich_gameport);
2796                 release_region(ich_gameport.io, 8);
2797                 ich_gameport_pci = NULL;
2798         }
2799 #endif
2800         /* disable joystick and MIDI */
2801         pci_read_config_word(pci, 0xe6, &val);
2802         val &= ~0x120;
2803         pci_write_config_word(pci, 0xe6, val);
2804 }
2805
2806 static struct pci_device_id snd_intel8x0_joystick_ids[] = {
2807         { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* 82801AA */
2808         { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* 82901AB */
2809         { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
2810         { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
2811         { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* ICH3 */
2812         // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
2813         // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
2814         { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* NFORCE */
2815         { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* NFORCE2 */
2816         { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },    /* NFORCE3 */
2817         { 0, }
2818 };
2819
2820 static struct pci_driver joystick_driver = {
2821         .name = "Intel ICH Joystick",
2822         .id_table = snd_intel8x0_joystick_ids,
2823         .probe = snd_intel8x0_joystick_probe,
2824         .remove = __devexit_p(snd_intel8x0_joystick_remove),
2825 };
2826
2827 static int have_joystick;
2828 #endif
2829
2830 static int __init alsa_card_intel8x0_init(void)
2831 {
2832         int err;
2833
2834         if ((err = pci_module_init(&driver)) < 0)
2835                 return err;
2836
2837 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2838         if (pci_module_init(&joystick_driver) < 0) {
2839                 snd_printdd(KERN_INFO "no joystick found\n");
2840                 have_joystick = 0;
2841         } else {
2842                 snd_printdd(KERN_INFO "joystick(s) found\n");
2843                 have_joystick = 1;
2844         }
2845 #endif
2846         return 0;
2847
2848 }
2849
2850 static void __exit alsa_card_intel8x0_exit(void)
2851 {
2852         pci_unregister_driver(&driver);
2853 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2854         if (have_joystick)
2855                 pci_unregister_driver(&joystick_driver);
2856 #endif
2857 }
2858
2859 module_init(alsa_card_intel8x0_init)
2860 module_exit(alsa_card_intel8x0_exit)