sound/pci/intel8x0.c

   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/moduleparam.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/ac97_codec.h>
  40 #include <sound/info.h>
  41 #include <sound/initval.h>
  42 /* for 440MX workaround */
  43 #include <asm/pgtable.h>
  44 #include <asm/cacheflush.h>
  45
  46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  50                 "{Intel,82901AB-ICH0},"
  51                 "{Intel,82801BA-ICH2},"
  52                 "{Intel,82801CA-ICH3},"
  53                 "{Intel,82801DB-ICH4},"
  54                 "{Intel,ICH5},"
  55                 "{Intel,ICH6},"
  56                 "{Intel,ICH7},"
  57                 "{Intel,6300ESB},"
  58                 "{Intel,MX440},"
  59                 "{SiS,SI7012},"
  60                 "{NVidia,nForce Audio},"
  61                 "{NVidia,nForce2 Audio},"
  62                 "{AMD,AMD768},"
  63                 "{AMD,AMD8111},"
  64                 "{ALI,M5455}}");
  65
  66 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  67 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  68 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  69 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  70 static char *ac97_quirk[SNDRV_CARDS];
  71 static int buggy_irq[SNDRV_CARDS];
  72 static int xbox[SNDRV_CARDS];
  73
  74 #ifdef SUPPORT_MIDI
  75 static int mpu_port[SNDRV_CARDS]; /* disabled */
  76 #endif
  77
  78 module_param_array(index, int, NULL, 0444);
  79 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  80 module_param_array(id, charp, NULL, 0444);
  81 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  82 module_param_array(enable, bool, NULL, 0444);
  83 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
  84 module_param_array(ac97_clock, int, NULL, 0444);
  85 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  86 module_param_array(ac97_quirk, charp, NULL, 0444);
  87 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  88 module_param_array(buggy_irq, bool, NULL, 0444);
  89 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  90 module_param_array(xbox, bool, NULL, 0444);
  91 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  92
  93 /*
  94  *  Direct registers
  95  */
  96
  97 #ifndef PCI_DEVICE_ID_INTEL_82801
  98 #define PCI_DEVICE_ID_INTEL_82801       0x2415
  99 #endif
 100 #ifndef PCI_DEVICE_ID_INTEL_82901
 101 #define PCI_DEVICE_ID_INTEL_82901       0x2425
 102 #endif
 103 #ifndef PCI_DEVICE_ID_INTEL_82801BA
 104 #define PCI_DEVICE_ID_INTEL_82801BA     0x2445
 105 #endif
 106 #ifndef PCI_DEVICE_ID_INTEL_440MX
 107 #define PCI_DEVICE_ID_INTEL_440MX       0x7195
 108 #endif
 109 #ifndef PCI_DEVICE_ID_INTEL_ICH3
 110 #define PCI_DEVICE_ID_INTEL_ICH3        0x2485
 111 #endif
 112 #ifndef PCI_DEVICE_ID_INTEL_ICH4
 113 #define PCI_DEVICE_ID_INTEL_ICH4        0x24c5
 114 #endif
 115 #ifndef PCI_DEVICE_ID_INTEL_ICH5
 116 #define PCI_DEVICE_ID_INTEL_ICH5        0x24d5
 117 #endif
 118 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
 119 #define PCI_DEVICE_ID_INTEL_ESB_5       0x25a6
 120 #endif
 121 #ifndef PCI_DEVICE_ID_INTEL_ICH6_3
 122 #define PCI_DEVICE_ID_INTEL_ICH6_3      0x266e
 123 #endif
 124 #ifndef PCI_DEVICE_ID_INTEL_ICH7_20
 125 #define PCI_DEVICE_ID_INTEL_ICH7_20     0x27de
 126 #endif
 127 #ifndef PCI_DEVICE_ID_SI_7012
 128 #define PCI_DEVICE_ID_SI_7012           0x7012
 129 #endif
 130 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
 131 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO  0x01b1
 132 #endif
 133 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
 134 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
 135 #endif
 136 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
 137 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
 138 #endif
 139 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
 140 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO  0x008a
 141 #endif
 142 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
 143 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
 144 #endif
 145 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
 146 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
 147 #endif
 148
 149 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 150
 151 #define ICHREG(x) ICH_REG_##x
 152
 153 #define DEFINE_REGSET(name,base) \
 154 enum { \
 155         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 156         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 157         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 158         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 159         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 160         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 161         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 162 };
 163
 164 /* busmaster blocks */
 165 DEFINE_REGSET(OFF, 0);          /* offset */
 166 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 167 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 168 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 169
 170 /* ICH4 busmaster blocks */
 171 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 172 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 173 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 174
 175 /* values for each busmaster block */
 176
 177 /* LVI */
 178 #define ICH_REG_LVI_MASK                0x1f
 179
 180 /* SR */
 181 #define ICH_FIFOE                       0x10    /* FIFO error */
 182 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 183 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 184 #define ICH_CELV                        0x02    /* current equals last valid */
 185 #define ICH_DCH                         0x01    /* DMA controller halted */
 186
 187 /* PIV */
 188 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 189
 190 /* CR */
 191 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 192 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 193 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 194 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 195 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 196
 197
 198 /* global block */
 199 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 200 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 201 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 202 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 203 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 204 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 205 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 206 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 207 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 208 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 209 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 210 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 211 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 212 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 213 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 214 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 215 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 216 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 217 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 218 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 219 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 220 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 221 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 222 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 223 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 224 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 225 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 226 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 227 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 228 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 229 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 230 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 231 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 232 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 233 #define   ICH_RCS               0x00008000      /* read completion status */
 234 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 235 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 236 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 237 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 238 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 239 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 240 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 241 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 242 #define   ICH_POINT             0x00000040      /* playback interrupt */
 243 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 244 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 245 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 246 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 247 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 248 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 249 #define   ICH_CAS               0x01            /* codec access semaphore */
 250 #define ICH_REG_SDM             0x80
 251 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 252 #define   ICH_DI2L_SHIFT        6
 253 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 254 #define   ICH_DI1L_SHIFT        4
 255 #define   ICH_SE                0x00000008      /* steer enable */
 256 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 257
 258 #define ICH_MAX_FRAGS           32              /* max hw frags */
 259
 260
 261 /*
 262  * registers for Ali5455
 263  */
 264
 265 /* ALi 5455 busmaster blocks */
 266 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 267 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 268 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 269 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 270 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 271 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 272 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 273 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 274 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 275 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 276 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 277
 278 enum {
 279         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 280         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 281         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 282         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 283         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 284         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 285         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 286         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 287         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 288         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 289         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 290         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 291         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 292         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 293         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 294         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 295         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 296         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 297         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 298         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 299         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 300 };
 301
 302 #define ALI_CAS_SEM_BUSY        0x80000000
 303 #define ALI_CPR_ADDR_SECONDARY  0x100
 304 #define ALI_CPR_ADDR_READ       0x80
 305 #define ALI_CSPSR_CODEC_READY   0x08
 306 #define ALI_CSPSR_READ_OK       0x02
 307 #define ALI_CSPSR_WRITE_OK      0x01
 308
 309 /* interrupts for the whole chip by interrupt status register finish */
 310
 311 #define ALI_INT_MICIN2          (1<<26)
 312 #define ALI_INT_PCMIN2          (1<<25)
 313 #define ALI_INT_I2SIN           (1<<24)
 314 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 315 #define ALI_INT_SPDIFIN         (1<<22)
 316 #define ALI_INT_LFEOUT          (1<<21)
 317 #define ALI_INT_CENTEROUT       (1<<20)
 318 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 319 #define ALI_INT_MICIN           (1<<18)
 320 #define ALI_INT_PCMOUT          (1<<17)
 321 #define ALI_INT_PCMIN           (1<<16)
 322 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 323 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 324 #define ALI_INT_GPIO            (1<<1)
 325 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 326
 327 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 328 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 329 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 330 #define ICH_ALI_SC_IN_BITS      (3<<18)
 331 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 332 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 333 #define ICH_ALI_SC_PCM_4        (1<<8)
 334 #define ICH_ALI_SC_PCM_6        (2<<8)
 335 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 336
 337 #define ICH_ALI_SS_SEC_ID       (3<<5)
 338 #define ICH_ALI_SS_PRI_ID       (3<<3)
 339
 340 #define ICH_ALI_IF_AC97SP       (1<<21)
 341 #define ICH_ALI_IF_MC           (1<<20)
 342 #define ICH_ALI_IF_PI           (1<<19)
 343 #define ICH_ALI_IF_MC2          (1<<18)
 344 #define ICH_ALI_IF_PI2          (1<<17)
 345 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 346 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 347 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 348 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 349 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 350 #define ICH_ALI_IF_PO           (1<<1)
 351
 352 /*
 353  *
 354  */
 355
 356 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
 357 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
 358 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
 359
 360 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 361
 362 typedef struct {
 363         unsigned int ichd;                      /* ich device number */
 364         unsigned long reg_offset;               /* offset to bmaddr */
 365         u32 *bdbar;                             /* CPU address (32bit) */
 366         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 367         snd_pcm_substream_t *substream;
 368         unsigned int physbuf;                   /* physical address (32bit) */
 369         unsigned int size;
 370         unsigned int fragsize;
 371         unsigned int fragsize1;
 372         unsigned int position;
 373         unsigned int pos_shift;
 374         int frags;
 375         int lvi;
 376         int lvi_frag;
 377         int civ;
 378         int ack;
 379         int ack_reload;
 380         unsigned int ack_bit;
 381         unsigned int roff_sr;
 382         unsigned int roff_picb;
 383         unsigned int int_sta_mask;              /* interrupt status mask */
 384         unsigned int ali_slot;                  /* ALI DMA slot */
 385         struct ac97_pcm *pcm;
 386         int pcm_open_flag;
 387         unsigned int page_attr_changed: 1;
 388 } ichdev_t;
 389
 390 typedef struct _snd_intel8x0 intel8x0_t;
 391
 392 struct _snd_intel8x0 {
 393         unsigned int device_type;
 394
 395         int irq;
 396
 397         unsigned int mmio;
 398         unsigned long addr;
 399         void __iomem *remap_addr;
 400         unsigned int bm_mmio;
 401         unsigned long bmaddr;
 402         void __iomem *remap_bmaddr;
 403
 404         struct pci_dev *pci;
 405         snd_card_t *card;
 406
 407         int pcm_devs;
 408         snd_pcm_t *pcm[6];
 409         ichdev_t ichd[6];
 410
 411         unsigned multi4: 1,
 412                  multi6: 1,
 413                  dra: 1,
 414                  smp20bit: 1;
 415         unsigned in_ac97_init: 1,
 416                  in_sdin_init: 1;
 417         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 418         unsigned fix_nocache: 1;        /* workaround for 440MX */
 419         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 420         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 421
 422         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 423
 424         ac97_bus_t *ac97_bus;
 425         ac97_t *ac97[3];
 426         unsigned int ac97_sdin[3];
 427
 428         spinlock_t reg_lock;
 429
 430         u32 bdbars_count;
 431         struct snd_dma_buffer bdbars;
 432         u32 int_sta_reg;                /* interrupt status register */
 433         u32 int_sta_mask;               /* interrupt status mask */
 434 };
 435
 436 static struct pci_device_id snd_intel8x0_ids[] = {
 437         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 438         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 439         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 440         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 441         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 442         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 443         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 444         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 445         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 446         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 447         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 448         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 449         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 450         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 451         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 452         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 453         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 454         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 455         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 456         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 457         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 458         { 0, }
 459 };
 460
 461 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 462
 463 /*
 464  *  Lowlevel I/O - busmaster
 465  */
 466
 467 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 468 {
 469         if (chip->bm_mmio)
 470                 return readb(chip->remap_bmaddr + offset);
 471         else
 472                 return inb(chip->bmaddr + offset);
 473 }
 474
 475 static u16 igetword(intel8x0_t *chip, u32 offset)
 476 {
 477         if (chip->bm_mmio)
 478                 return readw(chip->remap_bmaddr + offset);
 479         else
 480                 return inw(chip->bmaddr + offset);
 481 }
 482
 483 static u32 igetdword(intel8x0_t *chip, u32 offset)
 484 {
 485         if (chip->bm_mmio)
 486                 return readl(chip->remap_bmaddr + offset);
 487         else
 488                 return inl(chip->bmaddr + offset);
 489 }
 490
 491 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 492 {
 493         if (chip->bm_mmio)
 494                 writeb(val, chip->remap_bmaddr + offset);
 495         else
 496                 outb(val, chip->bmaddr + offset);
 497 }
 498
 499 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 500 {
 501         if (chip->bm_mmio)
 502                 writew(val, chip->remap_bmaddr + offset);
 503         else
 504                 outw(val, chip->bmaddr + offset);
 505 }
 506
 507 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 508 {
 509         if (chip->bm_mmio)
 510                 writel(val, chip->remap_bmaddr + offset);
 511         else
 512                 outl(val, chip->bmaddr + offset);
 513 }
 514
 515 /*
 516  *  Lowlevel I/O - AC'97 registers
 517  */
 518
 519 static u16 iagetword(intel8x0_t *chip, u32 offset)
 520 {
 521         if (chip->mmio)
 522                 return readw(chip->remap_addr + offset);
 523         else
 524                 return inw(chip->addr + offset);
 525 }
 526
 527 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 528 {
 529         if (chip->mmio)
 530                 writew(val, chip->remap_addr + offset);
 531         else
 532                 outw(val, chip->addr + offset);
 533 }
 534
 535 /*
 536  *  Basic I/O
 537  */
 538
 539 /*
 540  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 541  */
 542
 543 /* return the GLOB_STA bit for the corresponding codec */
 544 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 545 {
 546         static unsigned int codec_bit[3] = {
 547                 ICH_PCR, ICH_SCR, ICH_TCR
 548         };
 549         snd_assert(codec < 3, return ICH_PCR);
 550         if (chip->device_type == DEVICE_INTEL_ICH4)
 551                 codec = chip->ac97_sdin[codec];
 552         return codec_bit[codec];
 553 }
 554
 555 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 556 {
 557         int time;
 558
 559         if (codec > 2)
 560                 return -EIO;
 561         if (chip->in_sdin_init) {
 562                 /* we don't know the ready bit assignment at the moment */
 563                 /* so we check any */
 564                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
 565         } else {
 566                 codec = get_ich_codec_bit(chip, codec);
 567         }
 568
 569         /* codec ready ? */
 570         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 571                 return -EIO;
 572
 573         /* Anyone holding a semaphore for 1 msec should be shot... */
 574         time = 100;
 575         do {
 576                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 577                         return 0;
 578                 udelay(10);
 579         } while (time--);
 580
 581         /* access to some forbidden (non existant) ac97 registers will not
 582          * reset the semaphore. So even if you don't get the semaphore, still
 583          * continue the access. We don't need the semaphore anyway. */
 584         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 585                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 586         iagetword(chip, 0);     /* clear semaphore flag */
 587         /* I don't care about the semaphore */
 588         return -EBUSY;
 589 }
 590
 591 static void snd_intel8x0_codec_write(ac97_t *ac97,
 592                                      unsigned short reg,
 593                                      unsigned short val)
 594 {
 595         intel8x0_t *chip = ac97->private_data;
 596
 597         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 598                 if (! chip->in_ac97_init)
 599                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 600         }
 601         iaputword(chip, reg + ac97->num * 0x80, val);
 602 }
 603
 604 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 605                                               unsigned short reg)
 606 {
 607         intel8x0_t *chip = ac97->private_data;
 608         unsigned short res;
 609         unsigned int tmp;
 610
 611         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 612                 if (! chip->in_ac97_init)
 613                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 614                 res = 0xffff;
 615         } else {
 616                 res = iagetword(chip, reg + ac97->num * 0x80);
 617                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 618                         /* reset RCS and preserve other R/WC bits */
 619                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 620                         if (! chip->in_ac97_init)
 621                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 622                         res = 0xffff;
 623                 }
 624         }
 625         return res;
 626 }
 627
 628 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
 629 {
 630         unsigned int tmp;
 631
 632         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 633                 iagetword(chip, codec * 0x80);
 634                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 635                         /* reset RCS and preserve other R/WC bits */
 636                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 637                 }
 638         }
 639 }
 640
 641 /*
 642  * access to AC97 for Ali5455
 643  */
 644 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
 645 {
 646         int count = 0;
 647         for (count = 0; count < 0x7f; count++) {
 648                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 649                 if (val & mask)
 650                         return 0;
 651         }
 652         snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 653         return -EBUSY;
 654 }
 655
 656 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
 657 {
 658         int time = 100;
 659         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 660                 udelay(1);
 661         if (! time)
 662                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 663         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 664 }
 665
 666 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
 667 {
 668         intel8x0_t *chip = ac97->private_data;
 669         unsigned short data = 0xffff;
 670
 671         if (snd_intel8x0_ali_codec_semaphore(chip))
 672                 goto __err;
 673         reg |= ALI_CPR_ADDR_READ;
 674         if (ac97->num)
 675                 reg |= ALI_CPR_ADDR_SECONDARY;
 676         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 677         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 678                 goto __err;
 679         data = igetword(chip, ICHREG(ALI_SPR));
 680  __err:
 681         return data;
 682 }
 683
 684 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
 685 {
 686         intel8x0_t *chip = ac97->private_data;
 687
 688         if (snd_intel8x0_ali_codec_semaphore(chip))
 689                 return;
 690         iputword(chip, ICHREG(ALI_CPR), val);
 691         if (ac97->num)
 692                 reg |= ALI_CPR_ADDR_SECONDARY;
 693         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 694         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 695 }
 696
 697
 698 /*
 699  * DMA I/O
 700  */
 701 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 702 {
 703         int idx;
 704         u32 *bdbar = ichdev->bdbar;
 705         unsigned long port = ichdev->reg_offset;
 706
 707         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 708         if (ichdev->size == ichdev->fragsize) {
 709                 ichdev->ack_reload = ichdev->ack = 2;
 710                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 711                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 712                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 713                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 714                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 715                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 716                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 717                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 718                 }
 719                 ichdev->frags = 2;
 720         } else {
 721                 ichdev->ack_reload = ichdev->ack = 1;
 722                 ichdev->fragsize1 = ichdev->fragsize;
 723                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 724                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 725                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 726                                                      ichdev->fragsize >> ichdev->pos_shift);
 727                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 728                 }
 729                 ichdev->frags = ichdev->size / ichdev->fragsize;
 730         }
 731         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 732         ichdev->civ = 0;
 733         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 734         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 735         ichdev->position = 0;
 736 #if 0
 737         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 738                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 739 #endif
 740         /* clear interrupts */
 741         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 742 }
 743
 744 #ifdef __i386__
 745 /*
 746  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 747  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 748  * the pages as non-cached.  For details, see the errata in
 749  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 750  */
 751 static void fill_nocache(void *buf, int size, int nocache)
 752 {
 753         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 754         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
 755         global_flush_tlb();
 756 }
 757 #else
 758 #define fill_nocache(buf,size,nocache)
 759 #endif
 760
 761 /*
 762  *  Interrupt handler
 763  */
 764
 765 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 766 {
 767         unsigned long port = ichdev->reg_offset;
 768         int status, civ, i, step;
 769         int ack = 0;
 770
 771         spin_lock(&chip->reg_lock);
 772         status = igetbyte(chip, port + ichdev->roff_sr);
 773         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 774         if (!(status & ICH_BCIS)) {
 775                 step = 0;
 776         } else if (civ == ichdev->civ) {
 777                 // snd_printd("civ same %d\n", civ);
 778                 step = 1;
 779                 ichdev->civ++;
 780                 ichdev->civ &= ICH_REG_LVI_MASK;
 781         } else {
 782                 step = civ - ichdev->civ;
 783                 if (step < 0)
 784                         step += ICH_REG_LVI_MASK + 1;
 785                 // if (step != 1)
 786                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 787                 ichdev->civ = civ;
 788         }
 789
 790         ichdev->position += step * ichdev->fragsize1;
 791         if (! chip->in_measurement)
 792                 ichdev->position %= ichdev->size;
 793         ichdev->lvi += step;
 794         ichdev->lvi &= ICH_REG_LVI_MASK;
 795         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 796         for (i = 0; i < step; i++) {
 797                 ichdev->lvi_frag++;
 798                 ichdev->lvi_frag %= ichdev->frags;
 799                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 800         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 801                 if (--ichdev->ack == 0) {
 802                         ichdev->ack = ichdev->ack_reload;
 803                         ack = 1;
 804                 }
 805         }
 806         spin_unlock(&chip->reg_lock);
 807         if (ack && ichdev->substream) {
 808                 snd_pcm_period_elapsed(ichdev->substream);
 809         }
 810         iputbyte(chip, port + ichdev->roff_sr,
 811                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 812 }
 813
 814 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 815 {
 816         intel8x0_t *chip = dev_id;
 817         ichdev_t *ichdev;
 818         unsigned int status;
 819         unsigned int i;
 820
 821         status = igetdword(chip, chip->int_sta_reg);
 822         if (status == 0xffffffff)       /* we are not yet resumed */
 823                 return IRQ_NONE;
 824
 825         if ((status & chip->int_sta_mask) == 0) {
 826                 if (status) {
 827                         /* ack */
 828                         iputdword(chip, chip->int_sta_reg, status);
 829                         if (! chip->buggy_irq)
 830                                 status = 0;
 831                 }
 832                 return IRQ_RETVAL(status);
 833         }
 834
 835         for (i = 0; i < chip->bdbars_count; i++) {
 836                 ichdev = &chip->ichd[i];
 837                 if (status & ichdev->int_sta_mask)
 838                         snd_intel8x0_update(chip, ichdev);
 839         }
 840
 841         /* ack them */
 842         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 843
 844         return IRQ_HANDLED;
 845 }
 846
 847 /*
 848  *  PCM part
 849  */
 850
 851 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 852 {
 853         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 854         ichdev_t *ichdev = get_ichdev(substream);
 855         unsigned char val = 0;
 856         unsigned long port = ichdev->reg_offset;
 857
 858         switch (cmd) {
 859         case SNDRV_PCM_TRIGGER_START:
 860         case SNDRV_PCM_TRIGGER_RESUME:
 861                 val = ICH_IOCE | ICH_STARTBM;
 862                 break;
 863         case SNDRV_PCM_TRIGGER_STOP:
 864         case SNDRV_PCM_TRIGGER_SUSPEND:
 865                 val = 0;
 866                 break;
 867         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 868                 val = ICH_IOCE;
 869                 break;
 870         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 871                 val = ICH_IOCE | ICH_STARTBM;
 872                 break;
 873         default:
 874                 return -EINVAL;
 875         }
 876         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 877         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 878                 /* wait until DMA stopped */
 879                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 880                 /* reset whole DMA things */
 881                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 882         }
 883         return 0;
 884 }
 885
 886 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
 887 {
 888         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 889         ichdev_t *ichdev = get_ichdev(substream);
 890         unsigned long port = ichdev->reg_offset;
 891         static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
 892         unsigned int val, fifo;
 893
 894         val = igetdword(chip, ICHREG(ALI_DMACR));
 895         switch (cmd) {
 896         case SNDRV_PCM_TRIGGER_START:
 897         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 898         case SNDRV_PCM_TRIGGER_RESUME:
 899                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 900                         /* clear FIFO for synchronization of channels */
 901                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 902                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 903                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 904                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 905                 }
 906                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 907                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 908                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
 909                 break;
 910         case SNDRV_PCM_TRIGGER_STOP:
 911         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 912         case SNDRV_PCM_TRIGGER_SUSPEND:
 913                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
 914                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 915                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 916                         ;
 917                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 918                         break;
 919                 /* reset whole DMA things */
 920                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 921                 /* clear interrupts */
 922                 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 923                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 924                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 925                 break;
 926         default:
 927                 return -EINVAL;
 928         }
 929         return 0;
 930 }
 931
 932 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 933                                   snd_pcm_hw_params_t * hw_params)
 934 {
 935         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 936         ichdev_t *ichdev = get_ichdev(substream);
 937         snd_pcm_runtime_t *runtime = substream->runtime;
 938         int dbl = params_rate(hw_params) > 48000;
 939         int err;
 940
 941         if (chip->fix_nocache && ichdev->page_attr_changed) {
 942                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 943                 ichdev->page_attr_changed = 0;
 944         }
 945         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 946         if (err < 0)
 947                 return err;
 948         if (chip->fix_nocache) {
 949                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 950                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 951                         ichdev->page_attr_changed = 1;
 952                 }
 953         }
 954         if (ichdev->pcm_open_flag) {
 955                 snd_ac97_pcm_close(ichdev->pcm);
 956                 ichdev->pcm_open_flag = 0;
 957         }
 958         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 959                                 params_channels(hw_params),
 960                                 ichdev->pcm->r[dbl].slots);
 961         if (err >= 0) {
 962                 ichdev->pcm_open_flag = 1;
 963                 /* Force SPDIF setting */
 964                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 965                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
 966         }
 967         return err;
 968 }
 969
 970 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 971 {
 972         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 973         ichdev_t *ichdev = get_ichdev(substream);
 974
 975         if (ichdev->pcm_open_flag) {
 976                 snd_ac97_pcm_close(ichdev->pcm);
 977                 ichdev->pcm_open_flag = 0;
 978         }
 979         if (chip->fix_nocache && ichdev->page_attr_changed) {
 980                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 981                 ichdev->page_attr_changed = 0;
 982         }
 983         return snd_pcm_lib_free_pages(substream);
 984 }
 985
 986 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
 987                                        snd_pcm_runtime_t *runtime)
 988 {
 989         unsigned int cnt;
 990         int dbl = runtime->rate > 48000;
 991         switch (chip->device_type) {
 992         case DEVICE_ALI:
 993                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 994                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 995                 if (runtime->channels == 4 || dbl)
 996                         cnt |= ICH_ALI_SC_PCM_4;
 997                 else if (runtime->channels == 6)
 998                         cnt |= ICH_ALI_SC_PCM_6;
 999                 iputdword(chip, ICHREG(ALI_SCR), cnt);
1000                 break;
1001         case DEVICE_SIS:
1002                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1003                 cnt &= ~ICH_SIS_PCM_246_MASK;
1004                 if (runtime->channels == 4 || dbl)
1005                         cnt |= ICH_SIS_PCM_4;
1006                 else if (runtime->channels == 6)
1007                         cnt |= ICH_SIS_PCM_6;
1008                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1009                 break;
1010         default:
1011                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1012                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1013                 if (runtime->channels == 4 || dbl)
1014                         cnt |= ICH_PCM_4;
1015                 else if (runtime->channels == 6)
1016                         cnt |= ICH_PCM_6;
1017                 if (chip->device_type == DEVICE_NFORCE) {
1018                         /* reset to 2ch once to keep the 6 channel data in alignment,
1019                          * to start from Front Left always
1020                          */
1021                         if (cnt & ICH_PCM_246_MASK) {
1022                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1023                                 spin_unlock_irq(&chip->reg_lock);
1024                                 msleep(50); /* grrr... */
1025                                 spin_lock_irq(&chip->reg_lock);
1026                         }
1027                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1028                         if (runtime->sample_bits > 16)
1029                                 cnt |= ICH_PCM_20BIT;
1030                 }
1031                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1032                 break;
1033         }
1034 }
1035
1036 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1037 {
1038         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1039         snd_pcm_runtime_t *runtime = substream->runtime;
1040         ichdev_t *ichdev = get_ichdev(substream);
1041
1042         ichdev->physbuf = runtime->dma_addr;
1043         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1044         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1045         spin_lock_irq(&chip->reg_lock);
1046         if (ichdev->ichd == ICHD_PCMOUT) {
1047                 snd_intel8x0_setup_pcm_out(chip, runtime);
1048                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1049                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1050                 }
1051         }
1052         snd_intel8x0_setup_periods(chip, ichdev);
1053         spin_unlock_irq(&chip->reg_lock);
1054         return 0;
1055 }
1056
1057 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1058 {
1059         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1060         ichdev_t *ichdev = get_ichdev(substream);
1061         size_t ptr1, ptr;
1062         int civ, timeout = 10;
1063         unsigned int position;
1064
1065         spin_lock(&chip->reg_lock);
1066         do {
1067                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1068                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1069                 position = ichdev->position;
1070                 if (ptr1 == 0)
1071                         udelay(1);
1072                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1073                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1074                         break;
1075         } while (timeout--);
1076         ptr1 <<= ichdev->pos_shift;
1077         ptr = ichdev->fragsize1 - ptr1;
1078         ptr += position;
1079         spin_unlock(&chip->reg_lock);
1080         if (ptr >= ichdev->size)
1081                 return 0;
1082         return bytes_to_frames(substream->runtime, ptr);
1083 }
1084
1085 static snd_pcm_hardware_t snd_intel8x0_stream =
1086 {
1087         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1088                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1089                                  SNDRV_PCM_INFO_MMAP_VALID |
1090                                  SNDRV_PCM_INFO_PAUSE |
1091                                  SNDRV_PCM_INFO_RESUME),
1092         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1093         .rates =                SNDRV_PCM_RATE_48000,
1094         .rate_min =             48000,
1095         .rate_max =             48000,
1096         .channels_min =         2,
1097         .channels_max =         2,
1098         .buffer_bytes_max =     128 * 1024,
1099         .period_bytes_min =     32,
1100         .period_bytes_max =     128 * 1024,
1101         .periods_min =          1,
1102         .periods_max =          1024,
1103         .fifo_size =            0,
1104 };
1105
1106 static unsigned int channels4[] = {
1107         2, 4,
1108 };
1109
1110 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1111         .count = ARRAY_SIZE(channels4),
1112         .list = channels4,
1113         .mask = 0,
1114 };
1115
1116 static unsigned int channels6[] = {
1117         2, 4, 6,
1118 };
1119
1120 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1121         .count = ARRAY_SIZE(channels6),
1122         .list = channels6,
1123         .mask = 0,
1124 };
1125
1126 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1127 {
1128         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1129         snd_pcm_runtime_t *runtime = substream->runtime;
1130         int err;
1131
1132         ichdev->substream = substream;
1133         runtime->hw = snd_intel8x0_stream;
1134         runtime->hw.rates = ichdev->pcm->rates;
1135         snd_pcm_limit_hw_rates(runtime);
1136         if (chip->device_type == DEVICE_SIS) {
1137                 runtime->hw.buffer_bytes_max = 64*1024;
1138                 runtime->hw.period_bytes_max = 64*1024;
1139         }
1140         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1141                 return err;
1142         runtime->private_data = ichdev;
1143         return 0;
1144 }
1145
1146 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1147 {
1148         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1149         snd_pcm_runtime_t *runtime = substream->runtime;
1150         int err;
1151
1152         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1153         if (err < 0)
1154                 return err;
1155
1156         if (chip->multi6) {
1157                 runtime->hw.channels_max = 6;
1158                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1159         } else if (chip->multi4) {
1160                 runtime->hw.channels_max = 4;
1161                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1162         }
1163         if (chip->dra) {
1164                 snd_ac97_pcm_double_rate_rules(runtime);
1165         }
1166         if (chip->smp20bit) {
1167                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1168                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1169         }
1170         return 0;
1171 }
1172
1173 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1174 {
1175         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1176
1177         chip->ichd[ICHD_PCMOUT].substream = NULL;
1178         return 0;
1179 }
1180
1181 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1182 {
1183         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1184
1185         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1186 }
1187
1188 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1189 {
1190         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1191
1192         chip->ichd[ICHD_PCMIN].substream = NULL;
1193         return 0;
1194 }
1195
1196 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1197 {
1198         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1199
1200         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1201 }
1202
1203 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1204 {
1205         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1206
1207         chip->ichd[ICHD_MIC].substream = NULL;
1208         return 0;
1209 }
1210
1211 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1212 {
1213         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1214
1215         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1216 }
1217
1218 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1219 {
1220         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1221
1222         chip->ichd[ICHD_MIC2].substream = NULL;
1223         return 0;
1224 }
1225
1226 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1227 {
1228         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1229
1230         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1231 }
1232
1233 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1234 {
1235         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1236
1237         chip->ichd[ICHD_PCM2IN].substream = NULL;
1238         return 0;
1239 }
1240
1241 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1242 {
1243         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1244         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1245
1246         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1247 }
1248
1249 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1250 {
1251         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1252         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1253
1254         chip->ichd[idx].substream = NULL;
1255         return 0;
1256 }
1257
1258 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1259 {
1260         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1261         unsigned int val;
1262
1263         spin_lock_irq(&chip->reg_lock);
1264         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1265         val |= ICH_ALI_IF_AC97SP;
1266         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1267         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1268         spin_unlock_irq(&chip->reg_lock);
1269
1270         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1271 }
1272
1273 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1274 {
1275         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1276         unsigned int val;
1277
1278         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1279         spin_lock_irq(&chip->reg_lock);
1280         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1281         val &= ~ICH_ALI_IF_AC97SP;
1282         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1283         spin_unlock_irq(&chip->reg_lock);
1284
1285         return 0;
1286 }
1287
1288 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1289 {
1290         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1291
1292         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1293 }
1294
1295 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1296 {
1297         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1298
1299         chip->ichd[ALID_SPDIFIN].substream = NULL;
1300         return 0;
1301 }
1302
1303 #if 0 // NYI
1304 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1305 {
1306         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1307
1308         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1309 }
1310
1311 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1312 {
1313         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1314
1315         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1316         return 0;
1317 }
1318 #endif
1319
1320 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1321         .open =         snd_intel8x0_playback_open,
1322         .close =        snd_intel8x0_playback_close,
1323         .ioctl =        snd_pcm_lib_ioctl,
1324         .hw_params =    snd_intel8x0_hw_params,
1325         .hw_free =      snd_intel8x0_hw_free,
1326         .prepare =      snd_intel8x0_pcm_prepare,
1327         .trigger =      snd_intel8x0_pcm_trigger,
1328         .pointer =      snd_intel8x0_pcm_pointer,
1329 };
1330
1331 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1332         .open =         snd_intel8x0_capture_open,
1333         .close =        snd_intel8x0_capture_close,
1334         .ioctl =        snd_pcm_lib_ioctl,
1335         .hw_params =    snd_intel8x0_hw_params,
1336         .hw_free =      snd_intel8x0_hw_free,
1337         .prepare =      snd_intel8x0_pcm_prepare,
1338         .trigger =      snd_intel8x0_pcm_trigger,
1339         .pointer =      snd_intel8x0_pcm_pointer,
1340 };
1341
1342 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1343         .open =         snd_intel8x0_mic_open,
1344         .close =        snd_intel8x0_mic_close,
1345         .ioctl =        snd_pcm_lib_ioctl,
1346         .hw_params =    snd_intel8x0_hw_params,
1347         .hw_free =      snd_intel8x0_hw_free,
1348         .prepare =      snd_intel8x0_pcm_prepare,
1349         .trigger =      snd_intel8x0_pcm_trigger,
1350         .pointer =      snd_intel8x0_pcm_pointer,
1351 };
1352
1353 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1354         .open =         snd_intel8x0_mic2_open,
1355         .close =        snd_intel8x0_mic2_close,
1356         .ioctl =        snd_pcm_lib_ioctl,
1357         .hw_params =    snd_intel8x0_hw_params,
1358         .hw_free =      snd_intel8x0_hw_free,
1359         .prepare =      snd_intel8x0_pcm_prepare,
1360         .trigger =      snd_intel8x0_pcm_trigger,
1361         .pointer =      snd_intel8x0_pcm_pointer,
1362 };
1363
1364 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1365         .open =         snd_intel8x0_capture2_open,
1366         .close =        snd_intel8x0_capture2_close,
1367         .ioctl =        snd_pcm_lib_ioctl,
1368         .hw_params =    snd_intel8x0_hw_params,
1369         .hw_free =      snd_intel8x0_hw_free,
1370         .prepare =      snd_intel8x0_pcm_prepare,
1371         .trigger =      snd_intel8x0_pcm_trigger,
1372         .pointer =      snd_intel8x0_pcm_pointer,
1373 };
1374
1375 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1376         .open =         snd_intel8x0_spdif_open,
1377         .close =        snd_intel8x0_spdif_close,
1378         .ioctl =        snd_pcm_lib_ioctl,
1379         .hw_params =    snd_intel8x0_hw_params,
1380         .hw_free =      snd_intel8x0_hw_free,
1381         .prepare =      snd_intel8x0_pcm_prepare,
1382         .trigger =      snd_intel8x0_pcm_trigger,
1383         .pointer =      snd_intel8x0_pcm_pointer,
1384 };
1385
1386 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1387         .open =         snd_intel8x0_playback_open,
1388         .close =        snd_intel8x0_playback_close,
1389         .ioctl =        snd_pcm_lib_ioctl,
1390         .hw_params =    snd_intel8x0_hw_params,
1391         .hw_free =      snd_intel8x0_hw_free,
1392         .prepare =      snd_intel8x0_pcm_prepare,
1393         .trigger =      snd_intel8x0_ali_trigger,
1394         .pointer =      snd_intel8x0_pcm_pointer,
1395 };
1396
1397 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1398         .open =         snd_intel8x0_capture_open,
1399         .close =        snd_intel8x0_capture_close,
1400         .ioctl =        snd_pcm_lib_ioctl,
1401         .hw_params =    snd_intel8x0_hw_params,
1402         .hw_free =      snd_intel8x0_hw_free,
1403         .prepare =      snd_intel8x0_pcm_prepare,
1404         .trigger =      snd_intel8x0_ali_trigger,
1405         .pointer =      snd_intel8x0_pcm_pointer,
1406 };
1407
1408 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1409         .open =         snd_intel8x0_mic_open,
1410         .close =        snd_intel8x0_mic_close,
1411         .ioctl =        snd_pcm_lib_ioctl,
1412         .hw_params =    snd_intel8x0_hw_params,
1413         .hw_free =      snd_intel8x0_hw_free,
1414         .prepare =      snd_intel8x0_pcm_prepare,
1415         .trigger =      snd_intel8x0_ali_trigger,
1416         .pointer =      snd_intel8x0_pcm_pointer,
1417 };
1418
1419 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1420         .open =         snd_intel8x0_ali_ac97spdifout_open,
1421         .close =        snd_intel8x0_ali_ac97spdifout_close,
1422         .ioctl =        snd_pcm_lib_ioctl,
1423         .hw_params =    snd_intel8x0_hw_params,
1424         .hw_free =      snd_intel8x0_hw_free,
1425         .prepare =      snd_intel8x0_pcm_prepare,
1426         .trigger =      snd_intel8x0_ali_trigger,
1427         .pointer =      snd_intel8x0_pcm_pointer,
1428 };
1429
1430 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1431         .open =         snd_intel8x0_ali_spdifin_open,
1432         .close =        snd_intel8x0_ali_spdifin_close,
1433         .ioctl =        snd_pcm_lib_ioctl,
1434         .hw_params =    snd_intel8x0_hw_params,
1435         .hw_free =      snd_intel8x0_hw_free,
1436         .prepare =      snd_intel8x0_pcm_prepare,
1437         .trigger =      snd_intel8x0_pcm_trigger,
1438         .pointer =      snd_intel8x0_pcm_pointer,
1439 };
1440
1441 #if 0 // NYI
1442 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1443         .open =         snd_intel8x0_ali_spdifout_open,
1444         .close =        snd_intel8x0_ali_spdifout_close,
1445         .ioctl =        snd_pcm_lib_ioctl,
1446         .hw_params =    snd_intel8x0_hw_params,
1447         .hw_free =      snd_intel8x0_hw_free,
1448         .prepare =      snd_intel8x0_pcm_prepare,
1449         .trigger =      snd_intel8x0_pcm_trigger,
1450         .pointer =      snd_intel8x0_pcm_pointer,
1451 };
1452 #endif // NYI
1453
1454 struct ich_pcm_table {
1455         char *suffix;
1456         snd_pcm_ops_t *playback_ops;
1457         snd_pcm_ops_t *capture_ops;
1458         size_t prealloc_size;
1459         size_t prealloc_max_size;
1460         int ac97_idx;
1461 };
1462
1463 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1464 {
1465         snd_pcm_t *pcm;
1466         int err;
1467         char name[32];
1468
1469         if (rec->suffix)
1470                 sprintf(name, "Intel ICH - %s", rec->suffix);
1471         else
1472                 strcpy(name, "Intel ICH");
1473         err = snd_pcm_new(chip->card, name, device,
1474                           rec->playback_ops ? 1 : 0,
1475                           rec->capture_ops ? 1 : 0, &pcm);
1476         if (err < 0)
1477                 return err;
1478
1479         if (rec->playback_ops)
1480                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1481         if (rec->capture_ops)
1482                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1483
1484         pcm->private_data = chip;
1485         pcm->info_flags = 0;
1486         if (rec->suffix)
1487                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1488         else
1489                 strcpy(pcm->name, chip->card->shortname);
1490         chip->pcm[device] = pcm;
1491
1492         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1493                                               rec->prealloc_size, rec->prealloc_max_size);
1494
1495         return 0;
1496 }
1497
1498 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1499         {
1500                 .playback_ops = &snd_intel8x0_playback_ops,
1501                 .capture_ops = &snd_intel8x0_capture_ops,
1502                 .prealloc_size = 64 * 1024,
1503                 .prealloc_max_size = 128 * 1024,
1504         },
1505         {
1506                 .suffix = "MIC ADC",
1507                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1508                 .prealloc_size = 0,
1509                 .prealloc_max_size = 128 * 1024,
1510                 .ac97_idx = ICHD_MIC,
1511         },
1512         {
1513                 .suffix = "MIC2 ADC",
1514                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1515                 .prealloc_size = 0,
1516                 .prealloc_max_size = 128 * 1024,
1517                 .ac97_idx = ICHD_MIC2,
1518         },
1519         {
1520                 .suffix = "ADC2",
1521                 .capture_ops = &snd_intel8x0_capture2_ops,
1522                 .prealloc_size = 0,
1523                 .prealloc_max_size = 128 * 1024,
1524                 .ac97_idx = ICHD_PCM2IN,
1525         },
1526         {
1527                 .suffix = "IEC958",
1528                 .playback_ops = &snd_intel8x0_spdif_ops,
1529                 .prealloc_size = 64 * 1024,
1530                 .prealloc_max_size = 128 * 1024,
1531                 .ac97_idx = ICHD_SPBAR,
1532         },
1533 };
1534
1535 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1536         {
1537                 .playback_ops = &snd_intel8x0_playback_ops,
1538                 .capture_ops = &snd_intel8x0_capture_ops,
1539                 .prealloc_size = 64 * 1024,
1540                 .prealloc_max_size = 128 * 1024,
1541         },
1542         {
1543                 .suffix = "MIC ADC",
1544                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1545                 .prealloc_size = 0,
1546                 .prealloc_max_size = 128 * 1024,
1547                 .ac97_idx = NVD_MIC,
1548         },
1549         {
1550                 .suffix = "IEC958",
1551                 .playback_ops = &snd_intel8x0_spdif_ops,
1552                 .prealloc_size = 64 * 1024,
1553                 .prealloc_max_size = 128 * 1024,
1554                 .ac97_idx = NVD_SPBAR,
1555         },
1556 };
1557
1558 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1559         {
1560                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1561                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1562                 .prealloc_size = 64 * 1024,
1563                 .prealloc_max_size = 128 * 1024,
1564         },
1565         {
1566                 .suffix = "MIC ADC",
1567                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1568                 .prealloc_size = 0,
1569                 .prealloc_max_size = 128 * 1024,
1570                 .ac97_idx = ALID_MIC,
1571         },
1572         {
1573                 .suffix = "IEC958",
1574                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1575                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1576                 .prealloc_size = 64 * 1024,
1577                 .prealloc_max_size = 128 * 1024,
1578                 .ac97_idx = ALID_AC97SPDIFOUT,
1579         },
1580 #if 0 // NYI
1581         {
1582                 .suffix = "HW IEC958",
1583                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1584                 .prealloc_size = 64 * 1024,
1585                 .prealloc_max_size = 128 * 1024,
1586         },
1587 #endif
1588 };
1589
1590 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1591 {
1592         int i, tblsize, device, err;
1593         struct ich_pcm_table *tbl, *rec;
1594
1595         switch (chip->device_type) {
1596         case DEVICE_INTEL_ICH4:
1597                 tbl = intel_pcms;
1598                 tblsize = ARRAY_SIZE(intel_pcms);
1599                 break;
1600         case DEVICE_NFORCE:
1601                 tbl = nforce_pcms;
1602                 tblsize = ARRAY_SIZE(nforce_pcms);
1603                 break;
1604         case DEVICE_ALI:
1605                 tbl = ali_pcms;
1606                 tblsize = ARRAY_SIZE(ali_pcms);
1607                 break;
1608         default:
1609                 tbl = intel_pcms;
1610                 tblsize = 2;
1611                 break;
1612         }
1613
1614         device = 0;
1615         for (i = 0; i < tblsize; i++) {
1616                 rec = tbl + i;
1617                 if (i > 0 && rec->ac97_idx) {
1618                         /* activate PCM only when associated AC'97 codec */
1619                         if (! chip->ichd[rec->ac97_idx].pcm)
1620                                 continue;
1621                 }
1622                 err = snd_intel8x0_pcm1(chip, device, rec);
1623                 if (err < 0)
1624                         return err;
1625                 device++;
1626         }
1627
1628         chip->pcm_devs = device;
1629         return 0;
1630 }
1631
1632
1633 /*
1634  *  Mixer part
1635  */
1636
1637 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1638 {
1639         intel8x0_t *chip = bus->private_data;
1640         chip->ac97_bus = NULL;
1641 }
1642
1643 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1644 {
1645         intel8x0_t *chip = ac97->private_data;
1646         chip->ac97[ac97->num] = NULL;
1647 }
1648
1649 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1650         /* front PCM */
1651         {
1652                 .exclusive = 1,
1653                 .r = {  {
1654                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1655                                          (1 << AC97_SLOT_PCM_RIGHT) |
1656                                          (1 << AC97_SLOT_PCM_CENTER) |
1657                                          (1 << AC97_SLOT_PCM_SLEFT) |
1658                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1659                                          (1 << AC97_SLOT_LFE)
1660                         },
1661                         {
1662                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1663                                          (1 << AC97_SLOT_PCM_RIGHT) |
1664                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1665                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1666                         }
1667                 }
1668         },
1669         /* PCM IN #1 */
1670         {
1671                 .stream = 1,
1672                 .exclusive = 1,
1673                 .r = {  {
1674                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1675                                          (1 << AC97_SLOT_PCM_RIGHT)
1676                         }
1677                 }
1678         },
1679         /* MIC IN #1 */
1680         {
1681                 .stream = 1,
1682                 .exclusive = 1,
1683                 .r = {  {
1684                                 .slots = (1 << AC97_SLOT_MIC)
1685                         }
1686                 }
1687         },
1688         /* S/PDIF PCM */
1689         {
1690                 .exclusive = 1,
1691                 .spdif = 1,
1692                 .r = {  {
1693                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1694                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1695                         }
1696                 }
1697         },
1698         /* PCM IN #2 */
1699         {
1700                 .stream = 1,
1701                 .exclusive = 1,
1702                 .r = {  {
1703                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1704                                          (1 << AC97_SLOT_PCM_RIGHT)
1705                         }
1706                 }
1707         },
1708         /* MIC IN #2 */
1709         {
1710                 .stream = 1,
1711                 .exclusive = 1,
1712                 .r = {  {
1713                                 .slots = (1 << AC97_SLOT_MIC)
1714                         }
1715                 }
1716         },
1717 };
1718
1719 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1720         {
1721                 .vendor = 0x0e11,
1722                 .device = 0x008a,
1723                 .name = "Compaq Evo W4000",     /* AD1885 */
1724                 .type = AC97_TUNE_HP_ONLY
1725         },
1726         {
1727                 .vendor = 0x0e11,
1728                 .device = 0x00b8,
1729                 .name = "Compaq Evo D510C",
1730                 .type = AC97_TUNE_HP_ONLY
1731         },
1732         {
1733                 .vendor = 0x0e11,
1734                 .device = 0x0860,
1735                 .name = "HP/Compaq nx7010",
1736                 .type = AC97_TUNE_MUTE_LED
1737         },
1738         {
1739                 .vendor = 0x1014,
1740                 .device = 0x1f00,
1741                 .name = "MS-9128",
1742                 .type = AC97_TUNE_ALC_JACK
1743         },
1744         {
1745                 .vendor = 0x1028,
1746                 .device = 0x00d8,
1747                 .name = "Dell Precision 530",   /* AD1885 */
1748                 .type = AC97_TUNE_HP_ONLY
1749         },
1750         {
1751                 .vendor = 0x1028,
1752                 .device = 0x010d,
1753                 .name = "Dell", /* which model?  AD1885 */
1754                 .type = AC97_TUNE_HP_ONLY
1755         },
1756         {
1757                 .vendor = 0x1028,
1758                 .device = 0x0126,
1759                 .name = "Dell Optiplex GX260",  /* AD1981A */
1760                 .type = AC97_TUNE_HP_ONLY
1761         },
1762         {
1763                 .vendor = 0x1028,
1764                 .device = 0x012d,
1765                 .name = "Dell Precision 450",   /* AD1981B*/
1766                 .type = AC97_TUNE_HP_ONLY
1767         },
1768         {
1769                 .vendor = 0x1028,
1770                 .device = 0x0147,
1771                 .name = "Dell", /* which model?  AD1981B*/
1772                 .type = AC97_TUNE_HP_ONLY
1773         },
1774         {
1775                 .vendor = 0x103c,
1776                 .device = 0x006d,
1777                 .name = "HP zv5000",
1778                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1779         },
1780         {       /* FIXME: which codec? */
1781                 .vendor = 0x103c,
1782                 .device = 0x00c3,
1783                 .name = "HP xw6000",
1784                 .type = AC97_TUNE_HP_ONLY
1785         },
1786         {
1787                 .vendor = 0x103c,
1788                 .device = 0x088c,
1789                 .name = "HP nc8000",
1790                 .type = AC97_TUNE_MUTE_LED
1791         },
1792         {
1793                 .vendor = 0x103c,
1794                 .device = 0x0890,
1795                 .name = "HP nc6000",
1796                 .type = AC97_TUNE_MUTE_LED
1797         },
1798         {
1799                 .vendor = 0x103c,
1800                 .device = 0x129d,
1801                 .name = "HP xw8000",
1802                 .type = AC97_TUNE_HP_ONLY
1803         },
1804         {
1805                 .vendor = 0x103c,
1806                 .device = 0x12f1,
1807                 .name = "HP xw8200",    /* AD1981B*/
1808                 .type = AC97_TUNE_HP_ONLY
1809         },
1810         {
1811                 .vendor = 0x103c,
1812                 .device = 0x12f2,
1813                 .name = "HP xw6200",
1814                 .type = AC97_TUNE_HP_ONLY
1815         },
1816         {
1817                 .vendor = 0x103c,
1818                 .device = 0x3008,
1819                 .name = "HP xw4200",    /* AD1981B*/
1820                 .type = AC97_TUNE_HP_ONLY
1821         },
1822         {
1823                 .vendor = 0x104d,
1824                 .device = 0x8197,
1825                 .name = "Sony S1XP",
1826                 .type = AC97_TUNE_INV_EAPD
1827         },
1828         {
1829                 .vendor = 0x1043,
1830                 .device = 0x80f3,
1831                 .name = "ASUS ICH5/AD1985",
1832                 .type = AC97_TUNE_AD_SHARING
1833         },
1834         {
1835                 .vendor = 0x10cf,
1836                 .device = 0x11c3,
1837                 .name = "Fujitsu-Siemens E4010",
1838                 .type = AC97_TUNE_HP_ONLY
1839         },
1840         {
1841                 .vendor = 0x10f1,
1842                 .device = 0x2665,
1843                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1844                 .type = AC97_TUNE_HP_ONLY
1845         },
1846         {
1847                 .vendor = 0x10f1,
1848                 .device = 0x2885,
1849                 .name = "AMD64 Mobo",   /* ALC650 */
1850                 .type = AC97_TUNE_HP_ONLY
1851         },
1852         {
1853                 .vendor = 0x110a,
1854                 .device = 0x0056,
1855                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1856                 .type = AC97_TUNE_HP_ONLY
1857         },
1858         {
1859                 .vendor = 0x11d4,
1860                 .device = 0x5375,
1861                 .name = "ADI AD1985 (discrete)",
1862                 .type = AC97_TUNE_HP_ONLY
1863         },
1864         {
1865                 .vendor = 0x1462,
1866                 .device = 0x5470,
1867                 .name = "MSI P4 ATX 645 Ultra",
1868                 .type = AC97_TUNE_HP_ONLY
1869         },
1870         {
1871                 .vendor = 0x1734,
1872                 .device = 0x0088,
1873                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1874                 .type = AC97_TUNE_HP_ONLY
1875         },
1876         {
1877                 .vendor = 0x8086,
1878                 .device = 0x2000,
1879                 .mask = 0xfff0,
1880                 .name = "Intel ICH5/AD1985",
1881                 .type = AC97_TUNE_AD_SHARING
1882         },
1883         {
1884                 .vendor = 0x8086,
1885                 .device = 0x4000,
1886                 .mask = 0xfff0,
1887                 .name = "Intel ICH5/AD1985",
1888                 .type = AC97_TUNE_AD_SHARING
1889         },
1890         {
1891                 .vendor = 0x8086,
1892                 .device = 0x4856,
1893                 .name = "Intel D845WN (82801BA)",
1894                 .type = AC97_TUNE_SWAP_HP
1895         },
1896         {
1897                 .vendor = 0x8086,
1898                 .device = 0x4d44,
1899                 .name = "Intel D850EMV2",       /* AD1885 */
1900                 .type = AC97_TUNE_HP_ONLY
1901         },
1902         {
1903                 .vendor = 0x8086,
1904                 .device = 0x4d56,
1905                 .name = "Intel ICH/AD1885",
1906                 .type = AC97_TUNE_HP_ONLY
1907         },
1908         {
1909                 .vendor = 0x8086,
1910                 .device = 0x6000,
1911                 .mask = 0xfff0,
1912                 .name = "Intel ICH5/AD1985",
1913                 .type = AC97_TUNE_AD_SHARING
1914         },
1915         {
1916                 .vendor = 0x8086,
1917                 .device = 0xe000,
1918                 .mask = 0xfff0,
1919                 .name = "Intel ICH5/AD1985",
1920                 .type = AC97_TUNE_AD_SHARING
1921         },
1922 #if 0 /* FIXME: this seems wrong on most boards */
1923         {
1924                 .vendor = 0x8086,
1925                 .device = 0xa000,
1926                 .mask = 0xfff0,
1927                 .name = "Intel ICH5/AD1985",
1928                 .type = AC97_TUNE_HP_ONLY
1929         },
1930 #endif
1931         { } /* terminator */
1932 };
1933
1934 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1935 {
1936         ac97_bus_t *pbus;
1937         ac97_template_t ac97;
1938         int err;
1939         unsigned int i, codecs;
1940         unsigned int glob_sta = 0;
1941         ac97_bus_ops_t *ops;
1942         static ac97_bus_ops_t standard_bus_ops = {
1943                 .write = snd_intel8x0_codec_write,
1944                 .read = snd_intel8x0_codec_read,
1945         };
1946         static ac97_bus_ops_t ali_bus_ops = {
1947                 .write = snd_intel8x0_ali_codec_write,
1948                 .read = snd_intel8x0_ali_codec_read,
1949         };
1950
1951         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1952         switch (chip->device_type) {
1953         case DEVICE_NFORCE:
1954                 chip->spdif_idx = NVD_SPBAR;
1955                 break;
1956         case DEVICE_ALI:
1957                 chip->spdif_idx = ALID_AC97SPDIFOUT;
1958                 break;
1959         case DEVICE_INTEL_ICH4:
1960                 chip->spdif_idx = ICHD_SPBAR;
1961                 break;
1962         };
1963
1964         chip->in_ac97_init = 1;
1965
1966         memset(&ac97, 0, sizeof(ac97));
1967         ac97.private_data = chip;
1968         ac97.private_free = snd_intel8x0_mixer_free_ac97;
1969         ac97.scaps = AC97_SCAP_SKIP_MODEM;
1970         if (chip->xbox)
1971                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1972         if (chip->device_type != DEVICE_ALI) {
1973                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1974                 ops = &standard_bus_ops;
1975                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1976                         codecs = 0;
1977                         if (glob_sta & ICH_PCR)
1978                                 codecs++;
1979                         if (glob_sta & ICH_SCR)
1980                                 codecs++;
1981                         if (glob_sta & ICH_TCR)
1982                                 codecs++;
1983                         chip->in_sdin_init = 1;
1984                         for (i = 0; i < codecs; i++) {
1985                                 snd_intel8x0_codec_read_test(chip, i);
1986                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1987                         }
1988                         chip->in_sdin_init = 0;
1989                 } else {
1990                         codecs = glob_sta & ICH_SCR ? 2 : 1;
1991                 }
1992         } else {
1993                 ops = &ali_bus_ops;
1994                 codecs = 1;
1995                 /* detect the secondary codec */
1996                 for (i = 0; i < 100; i++) {
1997                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1998                         if (reg & 0x40) {
1999                                 codecs = 2;
2000                                 break;
2001                         }
2002                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2003                         udelay(1);
2004                 }
2005         }
2006         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2007                 goto __err;
2008         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2009         pbus->shared_type = AC97_SHARED_TYPE_ICH;       /* shared with modem driver */
2010         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2011                 pbus->clock = ac97_clock;
2012         /* FIXME: my test board doesn't work well with VRA... */
2013         if (chip->device_type == DEVICE_ALI)
2014                 pbus->no_vra = 1;
2015         pbus->dra = 1;
2016         chip->ac97_bus = pbus;
2017
2018         ac97.pci = chip->pci;
2019         for (i = 0; i < codecs; i++) {
2020                 ac97.num = i;
2021                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2022                         if (err != -EACCES)
2023                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2024                         if (i == 0)
2025                                 goto __err;
2026                         continue;
2027                 }
2028         }
2029         /* tune up the primary codec */
2030         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2031         /* enable separate SDINs for ICH4 */
2032         if (chip->device_type == DEVICE_INTEL_ICH4)
2033                 pbus->isdin = 1;
2034         /* find the available PCM streams */
2035         i = ARRAY_SIZE(ac97_pcm_defs);
2036         if (chip->device_type != DEVICE_INTEL_ICH4)
2037                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2038         if (chip->spdif_idx < 0)
2039                 i--;            /* do not allocate S/PDIF */
2040         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2041         if (err < 0)
2042                 goto __err;
2043         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2044         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2045         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2046         if (chip->spdif_idx >= 0)
2047                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2048         if (chip->device_type == DEVICE_INTEL_ICH4) {
2049                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2050                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2051         }
2052         /* enable separate SDINs for ICH4 */
2053         if (chip->device_type == DEVICE_INTEL_ICH4) {
2054                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2055                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2056                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2057                 if (pcm) {
2058                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2059                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2060                         for (i = 1; i < 4; i++) {
2061                                 if (pcm->r[0].codec[i]) {
2062                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2063                                         break;
2064                                 }
2065                         }
2066                 } else {
2067                         tmp &= ~ICH_SE; /* steer disable */
2068                 }
2069                 iputbyte(chip, ICHREG(SDM), tmp);
2070         }
2071         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2072                 chip->multi4 = 1;
2073                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2074                         chip->multi6 = 1;
2075         }
2076         if (pbus->pcms[0].r[1].rslots[0]) {
2077                 chip->dra = 1;
2078         }
2079         if (chip->device_type == DEVICE_INTEL_ICH4) {
2080                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2081                         chip->smp20bit = 1;
2082         }
2083         if (chip->device_type == DEVICE_NFORCE) {
2084                 /* 48kHz only */
2085                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2086         }
2087         if (chip->device_type == DEVICE_INTEL_ICH4) {
2088                 /* use slot 10/11 for SPDIF */
2089                 u32 val;
2090                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2091                 val |= ICH_PCM_SPDIF_1011;
2092                 iputdword(chip, ICHREG(GLOB_CNT), val);
2093                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2094         }
2095         chip->in_ac97_init = 0;
2096         return 0;
2097
2098  __err:
2099         /* clear the cold-reset bit for the next chance */
2100         if (chip->device_type != DEVICE_ALI)
2101                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2102         return err;
2103 }
2104
2105
2106 /*
2107  *
2108  */
2109
2110 static void do_ali_reset(intel8x0_t *chip)
2111 {
2112         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2113         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2114         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2115         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2116         iputdword(chip, ICHREG(ALI_INTERFACECR),
2117                   ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2118         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2119         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2120 }
2121
2122 #define do_delay(chip) do {\
2123         set_current_state(TASK_UNINTERRUPTIBLE);\
2124         schedule_timeout(1);\
2125 } while (0)
2126
2127 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2128 {
2129         unsigned long end_time;
2130         unsigned int cnt, status, nstatus;
2131
2132         /* put logic to right state */
2133         /* first clear status bits */
2134         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2135         if (chip->device_type == DEVICE_NFORCE)
2136                 status |= ICH_NVSPINT;
2137         cnt = igetdword(chip, ICHREG(GLOB_STA));
2138         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2139
2140         /* ACLink on, 2 channels */
2141         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2142         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2143         /* finish cold or do warm reset */
2144         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2145         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2146         end_time = (jiffies + (HZ / 4)) + 1;
2147         do {
2148                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2149                         goto __ok;
2150                 do_delay(chip);
2151         } while (time_after_eq(end_time, jiffies));
2152         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2153         return -EIO;
2154
2155       __ok:
2156         if (probing) {
2157                 /* wait for any codec ready status.
2158                  * Once it becomes ready it should remain ready
2159                  * as long as we do not disable the ac97 link.
2160                  */
2161                 end_time = jiffies + HZ;
2162                 do {
2163                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2164                         if (status)
2165                                 break;
2166                         do_delay(chip);
2167                 } while (time_after_eq(end_time, jiffies));
2168                 if (! status) {
2169                         /* no codec is found */
2170                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2171                         return -EIO;
2172                 }
2173
2174                 if (chip->device_type == DEVICE_INTEL_ICH4)
2175                         /* ICH4 can have three codecs */
2176                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2177                 else
2178                         /* others up to two codecs */
2179                         nstatus = ICH_PCR | ICH_SCR;
2180
2181                 /* wait for other codecs ready status. */
2182                 end_time = jiffies + HZ / 4;
2183                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2184                         do_delay(chip);
2185                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2186                 }
2187
2188         } else {
2189                 /* resume phase */
2190                 int i;
2191                 status = 0;
2192                 for (i = 0; i < 3; i++)
2193                         if (chip->ac97[i])
2194                                 status |= get_ich_codec_bit(chip, i);
2195                 /* wait until all the probed codecs are ready */
2196                 end_time = jiffies + HZ;
2197                 do {
2198                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2199                         if (status == nstatus)
2200                                 break;
2201                         do_delay(chip);
2202                 } while (time_after_eq(end_time, jiffies));
2203         }
2204
2205         if (chip->device_type == DEVICE_SIS) {
2206                 /* unmute the output on SIS7012 */
2207                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2208         }
2209         if (chip->device_type == DEVICE_NFORCE) {
2210                 /* enable SPDIF interrupt */
2211                 unsigned int val;
2212                 pci_read_config_dword(chip->pci, 0x4c, &val);
2213                 val |= 0x1000000;
2214                 pci_write_config_dword(chip->pci, 0x4c, val);
2215         }
2216         return 0;
2217 }
2218
2219 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2220 {
2221         u32 reg;
2222         int i = 0;
2223
2224         reg = igetdword(chip, ICHREG(ALI_SCR));
2225         if ((reg & 2) == 0)     /* Cold required */
2226                 reg |= 2;
2227         else
2228                 reg |= 1;       /* Warm */
2229         reg &= ~0x80000000;     /* ACLink on */
2230         iputdword(chip, ICHREG(ALI_SCR), reg);
2231
2232         for (i = 0; i < HZ / 2; i++) {
2233                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2234                         goto __ok;
2235                 do_delay(chip);
2236         }
2237         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2238         if (probing)
2239                 return -EIO;
2240
2241  __ok:
2242         for (i = 0; i < HZ / 2; i++) {
2243                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2244                 if (reg & 0x80) /* primary codec */
2245                         break;
2246                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2247                 do_delay(chip);
2248         }
2249
2250         do_ali_reset(chip);
2251         return 0;
2252 }
2253
2254 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2255 {
2256         unsigned int i;
2257         int err;
2258
2259         if (chip->device_type != DEVICE_ALI) {
2260                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2261                         return err;
2262                 iagetword(chip, 0);     /* clear semaphore flag */
2263         } else {
2264                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2265                         return err;
2266         }
2267
2268         /* disable interrupts */
2269         for (i = 0; i < chip->bdbars_count; i++)
2270                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2271         /* reset channels */
2272         for (i = 0; i < chip->bdbars_count; i++)
2273                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2274         /* initialize Buffer Descriptor Lists */
2275         for (i = 0; i < chip->bdbars_count; i++)
2276                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2277         return 0;
2278 }
2279
2280 static int snd_intel8x0_free(intel8x0_t *chip)
2281 {
2282         unsigned int i;
2283
2284         if (chip->irq < 0)
2285                 goto __hw_end;
2286         /* disable interrupts */
2287         for (i = 0; i < chip->bdbars_count; i++)
2288                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2289         /* reset channels */
2290         for (i = 0; i < chip->bdbars_count; i++)
2291                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2292         if (chip->device_type == DEVICE_NFORCE) {
2293                 /* stop the spdif interrupt */
2294                 unsigned int val;
2295                 pci_read_config_dword(chip->pci, 0x4c, &val);
2296                 val &= ~0x1000000;
2297                 pci_write_config_dword(chip->pci, 0x4c, val);
2298         }
2299         /* --- */
2300         synchronize_irq(chip->irq);
2301       __hw_end:
2302         if (chip->irq >= 0)
2303                 free_irq(chip->irq, (void *)chip);
2304         if (chip->bdbars.area) {
2305                 if (chip->fix_nocache)
2306                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2307                 snd_dma_free_pages(&chip->bdbars);
2308         }
2309         if (chip->remap_addr)
2310                 iounmap(chip->remap_addr);
2311         if (chip->remap_bmaddr)
2312                 iounmap(chip->remap_bmaddr);
2313         pci_release_regions(chip->pci);
2314         pci_disable_device(chip->pci);
2315         kfree(chip);
2316         return 0;
2317 }
2318
2319 #ifdef CONFIG_PM
2320 /*
2321  * power management
2322  */
2323 static int intel8x0_suspend(snd_card_t *card, unsigned int state)
2324 {
2325         intel8x0_t *chip = card->pm_private_data;
2326         int i;
2327
2328         for (i = 0; i < chip->pcm_devs; i++)
2329                 snd_pcm_suspend_all(chip->pcm[i]);
2330         /* clear nocache */
2331         if (chip->fix_nocache) {
2332                 for (i = 0; i < chip->bdbars_count; i++) {
2333                         ichdev_t *ichdev = &chip->ichd[i];
2334                         if (ichdev->substream && ichdev->page_attr_changed) {
2335                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2336                                 if (runtime->dma_area)
2337                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2338                         }
2339                 }
2340         }
2341         for (i = 0; i < 3; i++)
2342                 if (chip->ac97[i])
2343                         snd_ac97_suspend(chip->ac97[i]);
2344         pci_disable_device(chip->pci);
2345         return 0;
2346 }
2347
2348 static int intel8x0_resume(snd_card_t *card, unsigned int state)
2349 {
2350         intel8x0_t *chip = card->pm_private_data;
2351         int i;
2352
2353         pci_enable_device(chip->pci);
2354         pci_set_master(chip->pci);
2355         snd_intel8x0_chip_init(chip, 0);
2356
2357         /* refill nocache */
2358         if (chip->fix_nocache)
2359                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2360
2361         for (i = 0; i < 3; i++)
2362                 if (chip->ac97[i])
2363                         snd_ac97_resume(chip->ac97[i]);
2364
2365         /* refill nocache */
2366         if (chip->fix_nocache) {
2367                 for (i = 0; i < chip->bdbars_count; i++) {
2368                         ichdev_t *ichdev = &chip->ichd[i];
2369                         if (ichdev->substream && ichdev->page_attr_changed) {
2370                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2371                                 if (runtime->dma_area)
2372                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2373                         }
2374                 }
2375         }
2376
2377         return 0;
2378 }
2379 #endif /* CONFIG_PM */
2380
2381 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2382
2383 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2384 {
2385         snd_pcm_substream_t *subs;
2386         ichdev_t *ichdev;
2387         unsigned long port;
2388         unsigned long pos, t;
2389         struct timeval start_time, stop_time;
2390
2391         if (chip->ac97_bus->clock != 48000)
2392                 return; /* specified in module option */
2393
2394         subs = chip->pcm[0]->streams[0].substream;
2395         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2396                 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2397                 return;
2398         }
2399         ichdev = &chip->ichd[ICHD_PCMOUT];
2400         ichdev->physbuf = subs->dma_buffer.addr;
2401         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2402         ichdev->substream = NULL; /* don't process interrupts */
2403
2404         /* set rate */
2405         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2406                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2407                 return;
2408         }
2409         snd_intel8x0_setup_periods(chip, ichdev);
2410         port = ichdev->reg_offset;
2411         spin_lock_irq(&chip->reg_lock);
2412         chip->in_measurement = 1;
2413         /* trigger */
2414         if (chip->device_type != DEVICE_ALI)
2415                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2416         else {
2417                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2418                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2419         }
2420         do_gettimeofday(&start_time);
2421         spin_unlock_irq(&chip->reg_lock);
2422         set_current_state(TASK_UNINTERRUPTIBLE);
2423         schedule_timeout(HZ / 20);
2424         spin_lock_irq(&chip->reg_lock);
2425         /* check the position */
2426         pos = ichdev->fragsize1;
2427         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2428         pos += ichdev->position;
2429         chip->in_measurement = 0;
2430         do_gettimeofday(&stop_time);
2431         /* stop */
2432         if (chip->device_type == DEVICE_ALI) {
2433                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2434                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2435                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2436                         ;
2437         } else {
2438                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2439                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2440                         ;
2441         }
2442         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2443         spin_unlock_irq(&chip->reg_lock);
2444
2445         t = stop_time.tv_sec - start_time.tv_sec;
2446         t *= 1000000;
2447         t += stop_time.tv_usec - start_time.tv_usec;
2448         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2449         if (t == 0) {
2450                 snd_printk(KERN_ERR "?? calculation error..\n");
2451                 return;
2452         }
2453         pos = (pos / 4) * 1000;
2454         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2455         if (pos < 40000 || pos >= 60000)
2456                 /* abnormal value. hw problem? */
2457                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2458         else if (pos < 47500 || pos > 48500)
2459                 /* not 48000Hz, tuning the clock.. */
2460                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2461         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2462 }
2463
2464 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2465                                    snd_info_buffer_t * buffer)
2466 {
2467         intel8x0_t *chip = entry->private_data;
2468         unsigned int tmp;
2469
2470         snd_iprintf(buffer, "Intel8x0\n\n");
2471         if (chip->device_type == DEVICE_ALI)
2472                 return;
2473         tmp = igetdword(chip, ICHREG(GLOB_STA));
2474         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2475         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2476         if (chip->device_type == DEVICE_INTEL_ICH4)
2477                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2478         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2479                         tmp & ICH_PCR ? " primary" : "",
2480                         tmp & ICH_SCR ? " secondary" : "",
2481                         tmp & ICH_TCR ? " tertiary" : "",
2482                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2483         if (chip->device_type == DEVICE_INTEL_ICH4)
2484                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2485                         chip->ac97_sdin[0],
2486                         chip->ac97_sdin[1],
2487                         chip->ac97_sdin[2]);
2488 }
2489
2490 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2491 {
2492         snd_info_entry_t *entry;
2493
2494         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2495                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2496 }
2497
2498 static int snd_intel8x0_dev_free(snd_device_t *device)
2499 {
2500         intel8x0_t *chip = device->device_data;
2501         return snd_intel8x0_free(chip);
2502 }
2503
2504 struct ich_reg_info {
2505         unsigned int int_sta_mask;
2506         unsigned int offset;
2507 };
2508
2509 static int __devinit snd_intel8x0_create(snd_card_t * card,
2510                                          struct pci_dev *pci,
2511                                          unsigned long device_type,
2512                                          intel8x0_t ** r_intel8x0)
2513 {
2514         intel8x0_t *chip;
2515         int err;
2516         unsigned int i;
2517         unsigned int int_sta_masks;
2518         ichdev_t *ichdev;
2519         static snd_device_ops_t ops = {
2520                 .dev_free =     snd_intel8x0_dev_free,
2521         };
2522
2523         static unsigned int bdbars[] = {
2524                 3, /* DEVICE_INTEL */
2525                 6, /* DEVICE_INTEL_ICH4 */
2526                 3, /* DEVICE_SIS */
2527                 6, /* DEVICE_ALI */
2528                 4, /* DEVICE_NFORCE */
2529         };
2530         static struct ich_reg_info intel_regs[6] = {
2531                 { ICH_PIINT, 0 },
2532                 { ICH_POINT, 0x10 },
2533                 { ICH_MCINT, 0x20 },
2534                 { ICH_M2INT, 0x40 },
2535                 { ICH_P2INT, 0x50 },
2536                 { ICH_SPINT, 0x60 },
2537         };
2538         static struct ich_reg_info nforce_regs[4] = {
2539                 { ICH_PIINT, 0 },
2540                 { ICH_POINT, 0x10 },
2541                 { ICH_MCINT, 0x20 },
2542                 { ICH_NVSPINT, 0x70 },
2543         };
2544         static struct ich_reg_info ali_regs[6] = {
2545                 { ALI_INT_PCMIN, 0x40 },
2546                 { ALI_INT_PCMOUT, 0x50 },
2547                 { ALI_INT_MICIN, 0x60 },
2548                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2549                 { ALI_INT_SPDIFIN, 0xa0 },
2550                 { ALI_INT_SPDIFOUT, 0xb0 },
2551         };
2552         struct ich_reg_info *tbl;
2553
2554         *r_intel8x0 = NULL;
2555
2556         if ((err = pci_enable_device(pci)) < 0)
2557                 return err;
2558
2559         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2560         if (chip == NULL) {
2561                 pci_disable_device(pci);
2562                 return -ENOMEM;
2563         }
2564         spin_lock_init(&chip->reg_lock);
2565         chip->device_type = device_type;
2566         chip->card = card;
2567         chip->pci = pci;
2568         chip->irq = -1;
2569
2570         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2571             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2572                 chip->fix_nocache = 1; /* enable workaround */
2573
2574         /* some Nforce[2] and ICH boards have problems with IRQ handling.
2575          * Needs to return IRQ_HANDLED for unknown irqs.
2576          */
2577         if (device_type == DEVICE_NFORCE)
2578                 chip->buggy_irq = 1;
2579
2580         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2581                 kfree(chip);
2582                 pci_disable_device(pci);
2583                 return err;
2584         }
2585
2586         if (device_type == DEVICE_ALI) {
2587                 /* ALI5455 has no ac97 region */
2588                 chip->bmaddr = pci_resource_start(pci, 0);
2589                 goto port_inited;
2590         }
2591
2592         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2593                 chip->mmio = 1;
2594                 chip->addr = pci_resource_start(pci, 2);
2595                 chip->remap_addr = ioremap_nocache(chip->addr,
2596                                                    pci_resource_len(pci, 2));
2597                 if (chip->remap_addr == NULL) {
2598                         snd_printk("AC'97 space ioremap problem\n");
2599                         snd_intel8x0_free(chip);
2600                         return -EIO;
2601                 }
2602         } else {
2603                 chip->addr = pci_resource_start(pci, 0);
2604         }
2605         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2606                 chip->bm_mmio = 1;
2607                 chip->bmaddr = pci_resource_start(pci, 3);
2608                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2609                                                      pci_resource_len(pci, 3));
2610                 if (chip->remap_bmaddr == NULL) {
2611                         snd_printk("Controller space ioremap problem\n");
2612                         snd_intel8x0_free(chip);
2613                         return -EIO;
2614                 }
2615         } else {
2616                 chip->bmaddr = pci_resource_start(pci, 1);
2617         }
2618
2619  port_inited:
2620         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2621                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2622                 snd_intel8x0_free(chip);
2623                 return -EBUSY;
2624         }
2625         chip->irq = pci->irq;
2626         pci_set_master(pci);
2627         synchronize_irq(chip->irq);
2628
2629         chip->bdbars_count = bdbars[device_type];
2630
2631         /* initialize offsets */
2632         switch (device_type) {
2633         case DEVICE_NFORCE:
2634                 tbl = nforce_regs;
2635                 break;
2636         case DEVICE_ALI:
2637                 tbl = ali_regs;
2638                 break;
2639         default:
2640                 tbl = intel_regs;
2641                 break;
2642         }
2643         for (i = 0; i < chip->bdbars_count; i++) {
2644                 ichdev = &chip->ichd[i];
2645                 ichdev->ichd = i;
2646                 ichdev->reg_offset = tbl[i].offset;
2647                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2648                 if (device_type == DEVICE_SIS) {
2649                         /* SiS 7012 swaps the registers */
2650                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2651                         ichdev->roff_picb = ICH_REG_OFF_SR;
2652                 } else {
2653                         ichdev->roff_sr = ICH_REG_OFF_SR;
2654                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2655                 }
2656                 if (device_type == DEVICE_ALI)
2657                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2658                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2659                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2660         }
2661
2662         /* allocate buffer descriptor lists */
2663         /* the start of each lists must be aligned to 8 bytes */
2664         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2665                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2666                                 &chip->bdbars) < 0) {
2667                 snd_intel8x0_free(chip);
2668                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2669                 return -ENOMEM;
2670         }
2671         /* tables must be aligned to 8 bytes here, but the kernel pages
2672            are much bigger, so we don't care (on i386) */
2673         /* workaround for 440MX */
2674         if (chip->fix_nocache)
2675                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2676         int_sta_masks = 0;
2677         for (i = 0; i < chip->bdbars_count; i++) {
2678                 ichdev = &chip->ichd[i];
2679                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2680                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2681                 int_sta_masks |= ichdev->int_sta_mask;
2682         }
2683         chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2684         chip->int_sta_mask = int_sta_masks;
2685
2686         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2687                 snd_intel8x0_free(chip);
2688                 return err;
2689         }
2690
2691         snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2692
2693         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2694                 snd_intel8x0_free(chip);
2695                 return err;
2696         }
2697
2698         snd_card_set_dev(card, &pci->dev);
2699
2700         *r_intel8x0 = chip;
2701         return 0;
2702 }
2703
2704 static struct shortname_table {
2705         unsigned int id;
2706         const char *s;
2707 } shortnames[] __devinitdata = {
2708         { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2709         { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2710         { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2711         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2712         { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2713         { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2714         { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2715         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2716         { PCI_DEVICE_ID_INTEL_ICH6_3, "Intel ICH6" },
2717         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2718         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2719         { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2720         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2721         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2722         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2723         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2724         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2725         { 0x003a, "NVidia MCP04" },
2726         { 0x746d, "AMD AMD8111" },
2727         { 0x7445, "AMD AMD768" },
2728         { 0x5455, "ALi M5455" },
2729         { 0, NULL },
2730 };
2731
2732 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2733                                         const struct pci_device_id *pci_id)
2734 {
2735         static int dev;
2736         snd_card_t *card;
2737         intel8x0_t *chip;
2738         int err;
2739         struct shortname_table *name;
2740
2741         if (dev >= SNDRV_CARDS)
2742                 return -ENODEV;
2743         if (!enable[dev]) {
2744                 dev++;
2745                 return -ENOENT;
2746         }
2747
2748         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2749         if (card == NULL)
2750                 return -ENOMEM;
2751
2752         switch (pci_id->driver_data) {
2753         case DEVICE_NFORCE:
2754                 strcpy(card->driver, "NFORCE");
2755                 break;
2756         case DEVICE_INTEL_ICH4:
2757                 strcpy(card->driver, "ICH4");
2758                 break;
2759         default:
2760                 strcpy(card->driver, "ICH");
2761                 break;
2762         }
2763
2764         strcpy(card->shortname, "Intel ICH");
2765         for (name = shortnames; name->id; name++) {
2766                 if (pci->device == name->id) {
2767                         strcpy(card->shortname, name->s);
2768                         break;
2769                 }
2770         }
2771
2772         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2773                 snd_card_free(card);
2774                 return err;
2775         }
2776         if (buggy_irq[dev])
2777                 chip->buggy_irq = 1;
2778         if (xbox[dev])
2779                 chip->xbox = 1;
2780
2781         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2782                 snd_card_free(card);
2783                 return err;
2784         }
2785         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2786                 snd_card_free(card);
2787                 return err;
2788         }
2789
2790         snd_intel8x0_proc_init(chip);
2791
2792         snprintf(card->longname, sizeof(card->longname),
2793                  "%s with %s at %#lx, irq %i", card->shortname,
2794                  snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2795
2796         if (! ac97_clock[dev])
2797                 intel8x0_measure_ac97_clock(chip);
2798
2799         if ((err = snd_card_register(card)) < 0) {
2800                 snd_card_free(card);
2801                 return err;
2802         }
2803         pci_set_drvdata(pci, card);
2804         dev++;
2805         return 0;
2806 }
2807
2808 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2809 {
2810         snd_card_free(pci_get_drvdata(pci));
2811         pci_set_drvdata(pci, NULL);
2812 }
2813
2814 static struct pci_driver driver = {
2815         .name = "Intel ICH",
2816         .id_table = snd_intel8x0_ids,
2817         .probe = snd_intel8x0_probe,
2818         .remove = __devexit_p(snd_intel8x0_remove),
2819         SND_PCI_PM_CALLBACKS
2820 };
2821
2822
2823 static int __init alsa_card_intel8x0_init(void)
2824 {
2825         return pci_module_init(&driver);
2826 }
2827
2828 static void __exit alsa_card_intel8x0_exit(void)
2829 {
2830         pci_unregister_driver(&driver);
2831 }
2832
2833 module_init(alsa_card_intel8x0_init)
2834 module_exit(alsa_card_intel8x0_exit)