2 * ALSA driver for Intel ICH (i8x0) chipsets
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <sound/driver.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/gameport.h>
37 #include <linux/moduleparam.h>
38 #include <sound/core.h>
39 #include <sound/pcm.h>
40 #include <sound/ac97_codec.h>
41 #include <sound/info.h>
42 #include <sound/mpu401.h>
43 #include <sound/initval.h>
44 /* for 440MX workaround */
45 #include <asm/pgtable.h>
46 #include <asm/cacheflush.h>
48 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
49 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
50 MODULE_LICENSE("GPL");
51 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
52 "{Intel,82901AB-ICH0},"
53 "{Intel,82801BA-ICH2},"
54 "{Intel,82801CA-ICH3},"
55 "{Intel,82801DB-ICH4},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
67 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
68 #define SUPPORT_JOYSTICK 1
70 #define SUPPORT_MIDI 1
72 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
73 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
74 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
75 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
76 static int ac97_quirk[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = AC97_TUNE_DEFAULT};
77 static int buggy_irq[SNDRV_CARDS];
78 #ifdef SUPPORT_JOYSTICK
79 static int joystick[SNDRV_CARDS];
82 static int mpu_port[SNDRV_CARDS]; /* disabled */
86 module_param_array(index, int, boot_devs, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
88 module_param_array(id, charp, boot_devs, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
90 module_param_array(enable, bool, boot_devs, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
92 module_param_array(ac97_clock, int, boot_devs, 0444);
93 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
94 module_param_array(ac97_quirk, int, boot_devs, 0444);
95 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
96 module_param_array(buggy_irq, bool, boot_devs, 0444);
97 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
98 #ifdef SUPPORT_JOYSTICK
99 module_param_array(joystick, bool, boot_devs, 0444);
100 MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
103 module_param_array(mpu_port, int, boot_devs, 0444);
104 MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
111 #ifndef PCI_DEVICE_ID_INTEL_82801
112 #define PCI_DEVICE_ID_INTEL_82801 0x2415
114 #ifndef PCI_DEVICE_ID_INTEL_82901
115 #define PCI_DEVICE_ID_INTEL_82901 0x2425
117 #ifndef PCI_DEVICE_ID_INTEL_82801BA
118 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445
120 #ifndef PCI_DEVICE_ID_INTEL_440MX
121 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
123 #ifndef PCI_DEVICE_ID_INTEL_ICH3
124 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
126 #ifndef PCI_DEVICE_ID_INTEL_ICH4
127 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
129 #ifndef PCI_DEVICE_ID_INTEL_ICH5
130 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
132 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
133 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
135 #ifndef PCI_DEVICE_ID_INTEL_ICH6_3
136 #define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e
138 #ifndef PCI_DEVICE_ID_SI_7012
139 #define PCI_DEVICE_ID_SI_7012 0x7012
141 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
142 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
144 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
145 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
147 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
148 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
150 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
151 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
153 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
154 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
156 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
157 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
160 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
162 #define ICHREG(x) ICH_REG_##x
164 #define DEFINE_REGSET(name,base) \
166 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
167 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
168 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
169 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
170 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
171 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
172 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
175 /* busmaster blocks */
176 DEFINE_REGSET(OFF, 0); /* offset */
177 DEFINE_REGSET(PI, 0x00); /* PCM in */
178 DEFINE_REGSET(PO, 0x10); /* PCM out */
179 DEFINE_REGSET(MC, 0x20); /* Mic in */
181 /* ICH4 busmaster blocks */
182 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
183 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
184 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
186 /* values for each busmaster block */
189 #define ICH_REG_LVI_MASK 0x1f
192 #define ICH_FIFOE 0x10 /* FIFO error */
193 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
194 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
195 #define ICH_CELV 0x02 /* current equals last valid */
196 #define ICH_DCH 0x01 /* DMA controller halted */
199 #define ICH_REG_PIV_MASK 0x1f /* mask */
202 #define ICH_IOCE 0x10 /* interrupt on completion enable */
203 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
204 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
205 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
206 #define ICH_STARTBM 0x01 /* start busmaster operation */
210 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
211 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
212 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
213 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
214 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
215 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
216 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
217 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
218 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
219 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
220 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
221 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
222 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
223 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
224 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
225 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
226 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
227 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
228 #define ICH_ACLINK 0x00000008 /* AClink shut off */
229 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
230 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
231 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
232 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
233 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
234 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
235 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
236 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
237 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
238 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
239 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
240 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
241 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
242 #define ICH_MD3 0x00020000 /* modem power down semaphore */
243 #define ICH_AD3 0x00010000 /* audio power down semaphore */
244 #define ICH_RCS 0x00008000 /* read completion status */
245 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
246 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
247 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
248 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
249 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
250 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
251 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
252 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
253 #define ICH_POINT 0x00000040 /* playback interrupt */
254 #define ICH_PIINT 0x00000020 /* capture interrupt */
255 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
256 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
257 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
258 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
259 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
260 #define ICH_CAS 0x01 /* codec access semaphore */
261 #define ICH_REG_SDM 0x80
262 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
263 #define ICH_DI2L_SHIFT 6
264 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
265 #define ICH_DI1L_SHIFT 4
266 #define ICH_SE 0x00000008 /* steer enable */
267 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
269 #define ICH_MAX_FRAGS 32 /* max hw frags */
273 * registers for Ali5455
276 /* ALi 5455 busmaster blocks */
277 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
278 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
279 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
280 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
281 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
282 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
283 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
284 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
285 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
286 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
287 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
290 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
291 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
292 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
293 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
294 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
295 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
296 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
297 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
298 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
299 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
300 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
301 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
302 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
303 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
304 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
305 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
306 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
307 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
308 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
309 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
310 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
313 #define ALI_CAS_SEM_BUSY 0x80000000
314 #define ALI_CPR_ADDR_SECONDARY 0x100
315 #define ALI_CPR_ADDR_READ 0x80
316 #define ALI_CSPSR_CODEC_READY 0x08
317 #define ALI_CSPSR_READ_OK 0x02
318 #define ALI_CSPSR_WRITE_OK 0x01
320 /* interrupts for the whole chip by interrupt status register finish */
322 #define ALI_INT_MICIN2 (1<<26)
323 #define ALI_INT_PCMIN2 (1<<25)
324 #define ALI_INT_I2SIN (1<<24)
325 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
326 #define ALI_INT_SPDIFIN (1<<22)
327 #define ALI_INT_LFEOUT (1<<21)
328 #define ALI_INT_CENTEROUT (1<<20)
329 #define ALI_INT_CODECSPDIFOUT (1<<19)
330 #define ALI_INT_MICIN (1<<18)
331 #define ALI_INT_PCMOUT (1<<17)
332 #define ALI_INT_PCMIN (1<<16)
333 #define ALI_INT_CPRAIS (1<<7) /* command port available */
334 #define ALI_INT_SPRAIS (1<<5) /* status port available */
335 #define ALI_INT_GPIO (1<<1)
336 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
338 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
339 #define ICH_ALI_SC_AC97_DBL (1<<30)
340 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
341 #define ICH_ALI_SC_IN_BITS (3<<18)
342 #define ICH_ALI_SC_OUT_BITS (3<<16)
343 #define ICH_ALI_SC_6CH_CFG (3<<14)
344 #define ICH_ALI_SC_PCM_4 (1<<8)
345 #define ICH_ALI_SC_PCM_6 (2<<8)
346 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
348 #define ICH_ALI_SS_SEC_ID (3<<5)
349 #define ICH_ALI_SS_PRI_ID (3<<3)
351 #define ICH_ALI_IF_AC97SP (1<<21)
352 #define ICH_ALI_IF_MC (1<<20)
353 #define ICH_ALI_IF_PI (1<<19)
354 #define ICH_ALI_IF_MC2 (1<<18)
355 #define ICH_ALI_IF_PI2 (1<<17)
356 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
357 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
358 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
359 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
360 #define ICH_ALI_IF_PO_SPDF (1<<3)
361 #define ICH_ALI_IF_PO (1<<1)
367 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
368 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
369 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
371 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
374 unsigned int ichd; /* ich device number */
375 unsigned long reg_offset; /* offset to bmaddr */
376 u32 *bdbar; /* CPU address (32bit) */
377 unsigned int bdbar_addr; /* PCI bus address (32bit) */
378 snd_pcm_substream_t *substream;
379 unsigned int physbuf; /* physical address (32bit) */
381 unsigned int fragsize;
382 unsigned int fragsize1;
383 unsigned int position;
384 unsigned int pos_shift;
391 unsigned int ack_bit;
392 unsigned int roff_sr;
393 unsigned int roff_picb;
394 unsigned int int_sta_mask; /* interrupt status mask */
395 unsigned int ali_slot; /* ALI DMA slot */
396 struct ac97_pcm *pcm;
400 typedef struct _snd_intel8x0 intel8x0_t;
402 struct _snd_intel8x0 {
403 unsigned int device_type;
409 void __iomem * remap_addr;
410 unsigned int bm_mmio;
411 unsigned long bmaddr;
412 void __iomem * remap_bmaddr;
424 unsigned in_ac97_init: 1,
426 unsigned fix_nocache: 1; /* workaround for 440MX */
427 unsigned buggy_irq: 1; /* workaround for buggy mobos */
429 ac97_bus_t *ac97_bus;
431 unsigned int ac97_sdin[3];
433 snd_rawmidi_t *rmidi;
436 spinlock_t ac97_lock;
439 struct snd_dma_buffer bdbars;
440 u32 int_sta_reg; /* interrupt status register */
441 u32 int_sta_mask; /* interrupt status mask */
444 static struct pci_device_id snd_intel8x0_ids[] = {
445 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
446 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
447 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
448 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
449 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
450 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
451 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
452 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
453 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
454 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
455 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
456 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
457 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
458 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
459 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
460 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
461 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
462 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
463 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
464 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
468 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
471 * Lowlevel I/O - busmaster
474 static u8 igetbyte(intel8x0_t *chip, u32 offset)
477 return readb(chip->remap_bmaddr + offset);
479 return inb(chip->bmaddr + offset);
482 static u16 igetword(intel8x0_t *chip, u32 offset)
485 return readw(chip->remap_bmaddr + offset);
487 return inw(chip->bmaddr + offset);
490 static u32 igetdword(intel8x0_t *chip, u32 offset)
493 return readl(chip->remap_bmaddr + offset);
495 return inl(chip->bmaddr + offset);
498 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
501 writeb(val, chip->remap_bmaddr + offset);
503 outb(val, chip->bmaddr + offset);
506 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
509 writew(val, chip->remap_bmaddr + offset);
511 outw(val, chip->bmaddr + offset);
514 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
517 writel(val, chip->remap_bmaddr + offset);
519 outl(val, chip->bmaddr + offset);
523 * Lowlevel I/O - AC'97 registers
526 static u16 iagetword(intel8x0_t *chip, u32 offset)
529 return readw(chip->remap_addr + offset);
531 return inw(chip->addr + offset);
534 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
537 writew(val, chip->remap_addr + offset);
539 outw(val, chip->addr + offset);
547 * access to AC97 codec via normal i/o (for ICH and SIS7012)
550 /* return the GLOB_STA bit for the corresponding codec */
551 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
553 static unsigned int codec_bit[3] = {
554 ICH_PCR, ICH_SCR, ICH_TCR
556 snd_assert(codec < 3, return ICH_PCR);
557 if (chip->device_type == DEVICE_INTEL_ICH4)
558 codec = chip->ac97_sdin[codec];
559 return codec_bit[codec];
562 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
568 if (chip->in_sdin_init) {
569 /* we don't know the ready bit assignment at the moment */
570 /* so we check any */
571 codec = ICH_PCR | ICH_SCR | ICH_TCR;
573 codec = get_ich_codec_bit(chip, codec);
577 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
580 /* Anyone holding a semaphore for 1 msec should be shot... */
583 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
588 /* access to some forbidden (non existant) ac97 registers will not
589 * reset the semaphore. So even if you don't get the semaphore, still
590 * continue the access. We don't need the semaphore anyway. */
591 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
592 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
593 iagetword(chip, 0); /* clear semaphore flag */
594 /* I don't care about the semaphore */
598 static void snd_intel8x0_codec_write(ac97_t *ac97,
602 intel8x0_t *chip = ac97->private_data;
604 spin_lock(&chip->ac97_lock);
605 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
606 if (! chip->in_ac97_init)
607 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
609 iaputword(chip, reg + ac97->num * 0x80, val);
610 spin_unlock(&chip->ac97_lock);
613 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
616 intel8x0_t *chip = ac97->private_data;
620 spin_lock(&chip->ac97_lock);
621 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
622 if (! chip->in_ac97_init)
623 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
626 res = iagetword(chip, reg + ac97->num * 0x80);
627 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
628 /* reset RCS and preserve other R/WC bits */
629 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
630 if (! chip->in_ac97_init)
631 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
635 spin_unlock(&chip->ac97_lock);
639 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
643 spin_lock(&chip->ac97_lock);
644 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
645 iagetword(chip, codec * 0x80);
646 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
647 /* reset RCS and preserve other R/WC bits */
648 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
651 spin_unlock(&chip->ac97_lock);
655 * access to AC97 for Ali5455
657 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
660 for (count = 0; count < 0x7f; count++) {
661 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
665 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
669 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
672 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
675 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
676 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
679 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
681 intel8x0_t *chip = ac97->private_data;
682 unsigned short data = 0xffff;
684 spin_lock(&chip->ac97_lock);
685 if (snd_intel8x0_ali_codec_semaphore(chip))
687 reg |= ALI_CPR_ADDR_READ;
689 reg |= ALI_CPR_ADDR_SECONDARY;
690 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
691 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
693 data = igetword(chip, ICHREG(ALI_SPR));
695 spin_unlock(&chip->ac97_lock);
699 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
701 intel8x0_t *chip = ac97->private_data;
703 spin_lock(&chip->ac97_lock);
704 if (snd_intel8x0_ali_codec_semaphore(chip)) {
705 spin_unlock(&chip->ac97_lock);
708 iputword(chip, ICHREG(ALI_CPR), val);
710 reg |= ALI_CPR_ADDR_SECONDARY;
711 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
712 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
713 spin_unlock(&chip->ac97_lock);
720 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
723 u32 *bdbar = ichdev->bdbar;
724 unsigned long port = ichdev->reg_offset;
726 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
727 if (ichdev->size == ichdev->fragsize) {
728 ichdev->ack_reload = ichdev->ack = 2;
729 ichdev->fragsize1 = ichdev->fragsize >> 1;
730 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
731 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
732 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
733 ichdev->fragsize1 >> ichdev->pos_shift);
734 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
735 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
736 ichdev->fragsize1 >> ichdev->pos_shift);
740 ichdev->ack_reload = ichdev->ack = 1;
741 ichdev->fragsize1 = ichdev->fragsize;
742 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
743 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
744 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
745 ichdev->fragsize >> ichdev->pos_shift);
746 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
748 ichdev->frags = ichdev->size / ichdev->fragsize;
750 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
752 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
753 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
754 ichdev->position = 0;
756 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
757 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
759 /* clear interrupts */
760 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
765 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
766 * which aborts PCI busmaster for audio transfer. A workaround is to set
767 * the pages as non-cached. For details, see the errata in
768 * http://www.intel.com/design/chipsets/specupdt/245051.htm
770 static void fill_nocache(void *buf, int size, int nocache)
772 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
773 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
777 #define fill_nocache(buf,size,nocache)
784 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
786 unsigned long port = ichdev->reg_offset;
787 int status, civ, i, step;
790 spin_lock(&chip->reg_lock);
791 status = igetbyte(chip, port + ichdev->roff_sr);
792 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
793 if (!(status & ICH_BCIS)) {
795 } else if (civ == ichdev->civ) {
796 // snd_printd("civ same %d\n", civ);
799 ichdev->civ &= ICH_REG_LVI_MASK;
801 step = civ - ichdev->civ;
803 step += ICH_REG_LVI_MASK + 1;
805 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
809 ichdev->position += step * ichdev->fragsize1;
810 ichdev->position %= ichdev->size;
812 ichdev->lvi &= ICH_REG_LVI_MASK;
813 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
814 for (i = 0; i < step; i++) {
816 ichdev->lvi_frag %= ichdev->frags;
817 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
818 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
819 if (--ichdev->ack == 0) {
820 ichdev->ack = ichdev->ack_reload;
824 spin_unlock(&chip->reg_lock);
825 if (ack && ichdev->substream) {
826 snd_pcm_period_elapsed(ichdev->substream);
828 iputbyte(chip, port + ichdev->roff_sr,
829 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
832 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
834 intel8x0_t *chip = dev_id;
839 status = igetdword(chip, chip->int_sta_reg);
840 if (status == 0xffffffff) /* we are not yet resumed */
843 if ((status & chip->int_sta_mask) == 0) {
846 iputdword(chip, chip->int_sta_reg, status);
847 if (! chip->buggy_irq)
850 return IRQ_RETVAL(status);
853 for (i = 0; i < chip->bdbars_count; i++) {
854 ichdev = &chip->ichd[i];
855 if (status & ichdev->int_sta_mask)
856 snd_intel8x0_update(chip, ichdev);
860 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
869 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
871 intel8x0_t *chip = snd_pcm_substream_chip(substream);
872 ichdev_t *ichdev = get_ichdev(substream);
873 unsigned char val = 0;
874 unsigned long port = ichdev->reg_offset;
877 case SNDRV_PCM_TRIGGER_START:
878 case SNDRV_PCM_TRIGGER_RESUME:
879 val = ICH_IOCE | ICH_STARTBM;
881 case SNDRV_PCM_TRIGGER_STOP:
882 case SNDRV_PCM_TRIGGER_SUSPEND:
885 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
888 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
889 val = ICH_IOCE | ICH_STARTBM;
894 iputbyte(chip, port + ICH_REG_OFF_CR, val);
895 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
896 /* wait until DMA stopped */
897 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
898 /* reset whole DMA things */
899 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
904 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
906 intel8x0_t *chip = snd_pcm_substream_chip(substream);
907 ichdev_t *ichdev = get_ichdev(substream);
908 unsigned long port = ichdev->reg_offset;
909 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
910 unsigned int val, fifo;
912 val = igetdword(chip, ICHREG(ALI_DMACR));
914 case SNDRV_PCM_TRIGGER_START:
915 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
916 case SNDRV_PCM_TRIGGER_RESUME:
917 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
918 /* clear FIFO for synchronization of channels */
919 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
920 fifo &= ~(0xff << (ichdev->ali_slot % 4));
921 fifo |= 0x83 << (ichdev->ali_slot % 4);
922 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
924 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
925 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
926 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
928 case SNDRV_PCM_TRIGGER_STOP:
929 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
930 case SNDRV_PCM_TRIGGER_SUSPEND:
931 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
932 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
933 while (igetbyte(chip, port + ICH_REG_OFF_CR))
935 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
937 /* reset whole DMA things */
938 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
939 /* clear interrupts */
940 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
941 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
942 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
950 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
951 snd_pcm_hw_params_t * hw_params)
953 intel8x0_t *chip = snd_pcm_substream_chip(substream);
954 ichdev_t *ichdev = get_ichdev(substream);
955 snd_pcm_runtime_t *runtime = substream->runtime;
956 size_t size = params_buffer_bytes(hw_params);
959 if (chip->fix_nocache && runtime->dma_area && runtime->dma_bytes < size)
960 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
961 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
964 if (chip->fix_nocache && err > 0)
965 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
966 if (ichdev->pcm_open_flag) {
967 snd_ac97_pcm_close(ichdev->pcm);
968 ichdev->pcm_open_flag = 0;
970 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
971 params_channels(hw_params),
972 ichdev->pcm->r[0].slots);
974 ichdev->pcm_open_flag = 1;
975 /* FIXME: hack to enable spdif support */
976 if (ichdev->ichd == ICHD_PCMOUT && chip->device_type == DEVICE_SIS)
977 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
982 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
984 intel8x0_t *chip = snd_pcm_substream_chip(substream);
985 ichdev_t *ichdev = get_ichdev(substream);
987 if (ichdev->pcm_open_flag) {
988 snd_ac97_pcm_close(ichdev->pcm);
989 ichdev->pcm_open_flag = 0;
991 if (chip->fix_nocache && substream->runtime->dma_area)
992 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
993 return snd_pcm_lib_free_pages(substream);
996 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
997 int channels, int sample_bits)
1000 switch (chip->device_type) {
1002 cnt = igetdword(chip, ICHREG(ALI_SCR));
1003 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1004 if (chip->multi4 && channels == 4)
1005 cnt |= ICH_ALI_SC_PCM_4;
1006 else if (chip->multi6 && channels == 6)
1007 cnt |= ICH_ALI_SC_PCM_6;
1008 iputdword(chip, ICHREG(ALI_SCR), cnt);
1011 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1012 cnt &= ~ICH_SIS_PCM_246_MASK;
1013 if (chip->multi4 && channels == 4)
1014 cnt |= ICH_SIS_PCM_4;
1015 else if (chip->multi6 && channels == 6)
1016 cnt |= ICH_SIS_PCM_6;
1017 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1020 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1021 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1022 if (chip->multi4 && channels == 4)
1024 else if (chip->multi6 && channels == 6)
1026 if (chip->device_type == DEVICE_NFORCE) {
1027 /* reset to 2ch once to keep the 6 channel data in alignment,
1028 * to start from Front Left always
1030 if (cnt & ICH_PCM_246_MASK) {
1031 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1032 spin_unlock_irq(&chip->reg_lock);
1033 msleep(50); /* grrr... */
1034 spin_lock_irq(&chip->reg_lock);
1036 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1037 if (sample_bits > 16)
1038 cnt |= ICH_PCM_20BIT;
1040 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1045 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1047 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1048 snd_pcm_runtime_t *runtime = substream->runtime;
1049 ichdev_t *ichdev = get_ichdev(substream);
1051 ichdev->physbuf = runtime->dma_addr;
1052 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1053 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1054 spin_lock_irq(&chip->reg_lock);
1055 if (ichdev->ichd == ICHD_PCMOUT) {
1056 snd_intel8x0_setup_pcm_out(chip, runtime->channels,
1057 runtime->sample_bits);
1058 if (chip->device_type == DEVICE_INTEL_ICH4) {
1059 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1062 snd_intel8x0_setup_periods(chip, ichdev);
1063 spin_unlock_irq(&chip->reg_lock);
1067 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1069 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1070 ichdev_t *ichdev = get_ichdev(substream);
1072 int civ, timeout = 10;
1073 unsigned int position;
1075 spin_lock(&chip->reg_lock);
1077 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1078 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1079 position = ichdev->position;
1082 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1083 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1085 } while (timeout--);
1086 ptr1 <<= ichdev->pos_shift;
1087 ptr = ichdev->fragsize1 - ptr1;
1089 spin_unlock(&chip->reg_lock);
1090 if (ptr >= ichdev->size)
1092 return bytes_to_frames(substream->runtime, ptr);
1095 static snd_pcm_hardware_t snd_intel8x0_stream =
1097 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE |
1101 SNDRV_PCM_INFO_RESUME),
1102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1103 .rates = SNDRV_PCM_RATE_48000,
1108 .buffer_bytes_max = 128 * 1024,
1109 .period_bytes_min = 32,
1110 .period_bytes_max = 128 * 1024,
1112 .periods_max = 1024,
1116 static unsigned int channels4[] = {
1120 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1121 .count = ARRAY_SIZE(channels4),
1126 static unsigned int channels6[] = {
1130 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1131 .count = ARRAY_SIZE(channels6),
1136 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1138 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1139 snd_pcm_runtime_t *runtime = substream->runtime;
1142 ichdev->substream = substream;
1143 runtime->hw = snd_intel8x0_stream;
1144 runtime->hw.rates = ichdev->pcm->rates;
1145 snd_pcm_limit_hw_rates(runtime);
1146 if (chip->device_type == DEVICE_SIS) {
1147 runtime->hw.buffer_bytes_max = 64*1024;
1148 runtime->hw.period_bytes_max = 64*1024;
1150 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1152 runtime->private_data = ichdev;
1156 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1158 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1159 snd_pcm_runtime_t *runtime = substream->runtime;
1162 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1167 runtime->hw.channels_max = 6;
1168 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1169 } else if (chip->multi4) {
1170 runtime->hw.channels_max = 4;
1171 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1173 if (chip->smp20bit) {
1174 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1175 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1180 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1182 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1184 chip->ichd[ICHD_PCMOUT].substream = NULL;
1188 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1190 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1192 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1195 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1197 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1199 chip->ichd[ICHD_PCMIN].substream = NULL;
1203 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1205 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1207 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1210 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1212 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1214 chip->ichd[ICHD_MIC].substream = NULL;
1218 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1220 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1222 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1225 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1227 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1229 chip->ichd[ICHD_MIC2].substream = NULL;
1233 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1235 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1237 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1240 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1242 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1244 chip->ichd[ICHD_PCM2IN].substream = NULL;
1248 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1250 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1251 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1253 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1256 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1258 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1259 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1261 chip->ichd[idx].substream = NULL;
1265 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1267 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1270 spin_lock_irq(&chip->reg_lock);
1271 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1272 val |= ICH_ALI_IF_AC97SP;
1273 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1274 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1275 spin_unlock_irq(&chip->reg_lock);
1277 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1280 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1282 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1285 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1286 spin_lock_irq(&chip->reg_lock);
1287 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1288 val &= ~ICH_ALI_IF_AC97SP;
1289 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1290 spin_unlock_irq(&chip->reg_lock);
1295 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1297 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1299 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1302 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1304 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1306 chip->ichd[ALID_SPDIFIN].substream = NULL;
1311 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1313 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1315 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1318 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1320 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1322 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1327 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1328 .open = snd_intel8x0_playback_open,
1329 .close = snd_intel8x0_playback_close,
1330 .ioctl = snd_pcm_lib_ioctl,
1331 .hw_params = snd_intel8x0_hw_params,
1332 .hw_free = snd_intel8x0_hw_free,
1333 .prepare = snd_intel8x0_pcm_prepare,
1334 .trigger = snd_intel8x0_pcm_trigger,
1335 .pointer = snd_intel8x0_pcm_pointer,
1338 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1339 .open = snd_intel8x0_capture_open,
1340 .close = snd_intel8x0_capture_close,
1341 .ioctl = snd_pcm_lib_ioctl,
1342 .hw_params = snd_intel8x0_hw_params,
1343 .hw_free = snd_intel8x0_hw_free,
1344 .prepare = snd_intel8x0_pcm_prepare,
1345 .trigger = snd_intel8x0_pcm_trigger,
1346 .pointer = snd_intel8x0_pcm_pointer,
1349 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1350 .open = snd_intel8x0_mic_open,
1351 .close = snd_intel8x0_mic_close,
1352 .ioctl = snd_pcm_lib_ioctl,
1353 .hw_params = snd_intel8x0_hw_params,
1354 .hw_free = snd_intel8x0_hw_free,
1355 .prepare = snd_intel8x0_pcm_prepare,
1356 .trigger = snd_intel8x0_pcm_trigger,
1357 .pointer = snd_intel8x0_pcm_pointer,
1360 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1361 .open = snd_intel8x0_mic2_open,
1362 .close = snd_intel8x0_mic2_close,
1363 .ioctl = snd_pcm_lib_ioctl,
1364 .hw_params = snd_intel8x0_hw_params,
1365 .hw_free = snd_intel8x0_hw_free,
1366 .prepare = snd_intel8x0_pcm_prepare,
1367 .trigger = snd_intel8x0_pcm_trigger,
1368 .pointer = snd_intel8x0_pcm_pointer,
1371 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1372 .open = snd_intel8x0_capture2_open,
1373 .close = snd_intel8x0_capture2_close,
1374 .ioctl = snd_pcm_lib_ioctl,
1375 .hw_params = snd_intel8x0_hw_params,
1376 .hw_free = snd_intel8x0_hw_free,
1377 .prepare = snd_intel8x0_pcm_prepare,
1378 .trigger = snd_intel8x0_pcm_trigger,
1379 .pointer = snd_intel8x0_pcm_pointer,
1382 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1383 .open = snd_intel8x0_spdif_open,
1384 .close = snd_intel8x0_spdif_close,
1385 .ioctl = snd_pcm_lib_ioctl,
1386 .hw_params = snd_intel8x0_hw_params,
1387 .hw_free = snd_intel8x0_hw_free,
1388 .prepare = snd_intel8x0_pcm_prepare,
1389 .trigger = snd_intel8x0_pcm_trigger,
1390 .pointer = snd_intel8x0_pcm_pointer,
1393 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1394 .open = snd_intel8x0_playback_open,
1395 .close = snd_intel8x0_playback_close,
1396 .ioctl = snd_pcm_lib_ioctl,
1397 .hw_params = snd_intel8x0_hw_params,
1398 .hw_free = snd_intel8x0_hw_free,
1399 .prepare = snd_intel8x0_pcm_prepare,
1400 .trigger = snd_intel8x0_ali_trigger,
1401 .pointer = snd_intel8x0_pcm_pointer,
1404 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1405 .open = snd_intel8x0_capture_open,
1406 .close = snd_intel8x0_capture_close,
1407 .ioctl = snd_pcm_lib_ioctl,
1408 .hw_params = snd_intel8x0_hw_params,
1409 .hw_free = snd_intel8x0_hw_free,
1410 .prepare = snd_intel8x0_pcm_prepare,
1411 .trigger = snd_intel8x0_ali_trigger,
1412 .pointer = snd_intel8x0_pcm_pointer,
1415 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1416 .open = snd_intel8x0_mic_open,
1417 .close = snd_intel8x0_mic_close,
1418 .ioctl = snd_pcm_lib_ioctl,
1419 .hw_params = snd_intel8x0_hw_params,
1420 .hw_free = snd_intel8x0_hw_free,
1421 .prepare = snd_intel8x0_pcm_prepare,
1422 .trigger = snd_intel8x0_ali_trigger,
1423 .pointer = snd_intel8x0_pcm_pointer,
1426 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1427 .open = snd_intel8x0_ali_ac97spdifout_open,
1428 .close = snd_intel8x0_ali_ac97spdifout_close,
1429 .ioctl = snd_pcm_lib_ioctl,
1430 .hw_params = snd_intel8x0_hw_params,
1431 .hw_free = snd_intel8x0_hw_free,
1432 .prepare = snd_intel8x0_pcm_prepare,
1433 .trigger = snd_intel8x0_ali_trigger,
1434 .pointer = snd_intel8x0_pcm_pointer,
1437 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1438 .open = snd_intel8x0_ali_spdifin_open,
1439 .close = snd_intel8x0_ali_spdifin_close,
1440 .ioctl = snd_pcm_lib_ioctl,
1441 .hw_params = snd_intel8x0_hw_params,
1442 .hw_free = snd_intel8x0_hw_free,
1443 .prepare = snd_intel8x0_pcm_prepare,
1444 .trigger = snd_intel8x0_pcm_trigger,
1445 .pointer = snd_intel8x0_pcm_pointer,
1449 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1450 .open = snd_intel8x0_ali_spdifout_open,
1451 .close = snd_intel8x0_ali_spdifout_close,
1452 .ioctl = snd_pcm_lib_ioctl,
1453 .hw_params = snd_intel8x0_hw_params,
1454 .hw_free = snd_intel8x0_hw_free,
1455 .prepare = snd_intel8x0_pcm_prepare,
1456 .trigger = snd_intel8x0_pcm_trigger,
1457 .pointer = snd_intel8x0_pcm_pointer,
1461 struct ich_pcm_table {
1463 snd_pcm_ops_t *playback_ops;
1464 snd_pcm_ops_t *capture_ops;
1465 size_t prealloc_size;
1466 size_t prealloc_max_size;
1470 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1477 sprintf(name, "Intel ICH - %s", rec->suffix);
1479 strcpy(name, "Intel ICH");
1480 err = snd_pcm_new(chip->card, name, device,
1481 rec->playback_ops ? 1 : 0,
1482 rec->capture_ops ? 1 : 0, &pcm);
1486 if (rec->playback_ops)
1487 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1488 if (rec->capture_ops)
1489 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1491 pcm->private_data = chip;
1492 pcm->info_flags = 0;
1494 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1496 strcpy(pcm->name, chip->card->shortname);
1497 chip->pcm[device] = pcm;
1499 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1500 rec->prealloc_size, rec->prealloc_max_size);
1505 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1507 .playback_ops = &snd_intel8x0_playback_ops,
1508 .capture_ops = &snd_intel8x0_capture_ops,
1509 .prealloc_size = 64 * 1024,
1510 .prealloc_max_size = 128 * 1024,
1513 .suffix = "MIC ADC",
1514 .capture_ops = &snd_intel8x0_capture_mic_ops,
1516 .prealloc_max_size = 128 * 1024,
1517 .ac97_idx = ICHD_MIC,
1520 .suffix = "MIC2 ADC",
1521 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1523 .prealloc_max_size = 128 * 1024,
1524 .ac97_idx = ICHD_MIC2,
1528 .capture_ops = &snd_intel8x0_capture2_ops,
1530 .prealloc_max_size = 128 * 1024,
1531 .ac97_idx = ICHD_PCM2IN,
1535 .playback_ops = &snd_intel8x0_spdif_ops,
1536 .prealloc_size = 64 * 1024,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = ICHD_SPBAR,
1542 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1544 .playback_ops = &snd_intel8x0_playback_ops,
1545 .capture_ops = &snd_intel8x0_capture_ops,
1546 .prealloc_size = 64 * 1024,
1547 .prealloc_max_size = 128 * 1024,
1550 .suffix = "MIC ADC",
1551 .capture_ops = &snd_intel8x0_capture_mic_ops,
1553 .prealloc_max_size = 128 * 1024,
1554 .ac97_idx = NVD_MIC,
1558 .playback_ops = &snd_intel8x0_spdif_ops,
1559 .prealloc_size = 64 * 1024,
1560 .prealloc_max_size = 128 * 1024,
1561 .ac97_idx = NVD_SPBAR,
1565 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1567 .playback_ops = &snd_intel8x0_ali_playback_ops,
1568 .capture_ops = &snd_intel8x0_ali_capture_ops,
1569 .prealloc_size = 64 * 1024,
1570 .prealloc_max_size = 128 * 1024,
1573 .suffix = "MIC ADC",
1574 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1576 .prealloc_max_size = 128 * 1024,
1577 .ac97_idx = ALID_MIC,
1581 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1582 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1583 .prealloc_size = 64 * 1024,
1584 .prealloc_max_size = 128 * 1024,
1585 .ac97_idx = ALID_AC97SPDIFOUT,
1589 .suffix = "HW IEC958",
1590 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1591 .prealloc_size = 64 * 1024,
1592 .prealloc_max_size = 128 * 1024,
1597 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1599 int i, tblsize, device, err;
1600 struct ich_pcm_table *tbl, *rec;
1602 switch (chip->device_type) {
1603 case DEVICE_INTEL_ICH4:
1605 tblsize = ARRAY_SIZE(intel_pcms);
1609 tblsize = ARRAY_SIZE(nforce_pcms);
1613 tblsize = ARRAY_SIZE(ali_pcms);
1622 for (i = 0; i < tblsize; i++) {
1624 if (i > 0 && rec->ac97_idx) {
1625 /* activate PCM only when associated AC'97 codec */
1626 if (! chip->ichd[rec->ac97_idx].pcm)
1629 err = snd_intel8x0_pcm1(chip, device, rec);
1635 chip->pcm_devs = device;
1644 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1646 intel8x0_t *chip = bus->private_data;
1647 chip->ac97_bus = NULL;
1650 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1652 intel8x0_t *chip = ac97->private_data;
1653 chip->ac97[ac97->num] = NULL;
1656 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1661 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1662 (1 << AC97_SLOT_PCM_RIGHT) |
1663 (1 << AC97_SLOT_PCM_CENTER) |
1664 (1 << AC97_SLOT_PCM_SLEFT) |
1665 (1 << AC97_SLOT_PCM_SRIGHT) |
1666 (1 << AC97_SLOT_LFE)
1675 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1676 (1 << AC97_SLOT_PCM_RIGHT)
1685 .slots = (1 << AC97_SLOT_MIC)
1694 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1695 (1 << AC97_SLOT_SPDIF_RIGHT2)
1704 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1705 (1 << AC97_SLOT_PCM_RIGHT)
1714 .slots = (1 << AC97_SLOT_MIC)
1720 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1724 .name = "Compaq Evo D510C",
1725 .type = AC97_TUNE_HP_ONLY
1731 .type = AC97_TUNE_ALC_JACK
1736 .name = "Dell Precision 530", /* AD1885 */
1737 .type = AC97_TUNE_HP_ONLY
1742 .name = "Dell Optiplex GX260", /* AD1981A */
1743 .type = AC97_TUNE_HP_ONLY
1748 .name = "Dell Precision 450", /* AD1981B*/
1749 .type = AC97_TUNE_HP_ONLY
1751 { /* FIXME: which codec? */
1754 .name = "Hewlett-Packard onboard",
1755 .type = AC97_TUNE_HP_ONLY
1760 .name = "HP xw8200", /* AD1981B*/
1761 .type = AC97_TUNE_HP_ONLY
1766 .name = "HP xw4200", /* AD1981B*/
1767 .type = AC97_TUNE_HP_ONLY
1772 .name = "ASUS ICH5/AD1985",
1773 .type = AC97_TUNE_AD_SHARING
1778 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1779 .type = AC97_TUNE_HP_ONLY
1784 .name = "AMD64 Mobo", /* ALC650 */
1785 .type = AC97_TUNE_HP_ONLY
1790 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1791 .type = AC97_TUNE_HP_ONLY
1796 .name = "ADI AD1985 (discrete)",
1797 .type = AC97_TUNE_HP_ONLY
1802 .name = "MSI P4 ATX 645 Ultra",
1803 .type = AC97_TUNE_HP_ONLY
1808 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1809 .type = AC97_TUNE_HP_ONLY
1815 .name = "Intel ICH5/AD1985",
1816 .type = AC97_TUNE_AD_SHARING
1822 .name = "Intel ICH5/AD1985",
1823 .type = AC97_TUNE_AD_SHARING
1828 .name = "Intel D845WN (82801BA)",
1829 .type = AC97_TUNE_SWAP_HP
1834 .name = "Intel D850EMV2", /* AD1885 */
1835 .type = AC97_TUNE_HP_ONLY
1840 .name = "Intel ICH/AD1885",
1841 .type = AC97_TUNE_HP_ONLY
1847 .name = "Intel ICH5/AD1985",
1848 .type = AC97_TUNE_AD_SHARING
1854 .name = "Intel ICH5/AD1985",
1855 .type = AC97_TUNE_AD_SHARING
1857 #if 0 /* FIXME: this seems wrong on most boards */
1862 .name = "Intel ICH5/AD1985",
1863 .type = AC97_TUNE_HP_ONLY
1869 .name = "Dell Precision 450", /* AD1981B*/
1870 .type = AC97_TUNE_HP_ONLY
1875 .name = "HP xw4200", /* AD1981B*/
1876 .type = AC97_TUNE_HP_ONLY
1881 .name = "HP xw8200", /* AD1981B*/
1882 .type = AC97_TUNE_HP_ONLY
1884 { } /* terminator */
1887 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, int ac97_quirk)
1890 ac97_template_t ac97;
1892 unsigned int i, codecs;
1893 unsigned int glob_sta = 0;
1894 int spdif_idx = -1; /* disabled */
1895 ac97_bus_ops_t *ops;
1896 static ac97_bus_ops_t standard_bus_ops = {
1897 .write = snd_intel8x0_codec_write,
1898 .read = snd_intel8x0_codec_read,
1900 static ac97_bus_ops_t ali_bus_ops = {
1901 .write = snd_intel8x0_ali_codec_write,
1902 .read = snd_intel8x0_ali_codec_read,
1905 switch (chip->device_type) {
1907 spdif_idx = NVD_SPBAR;
1910 spdif_idx = ALID_AC97SPDIFOUT;
1913 if (chip->device_type == DEVICE_INTEL_ICH4)
1914 spdif_idx = ICHD_SPBAR;
1918 chip->in_ac97_init = 1;
1920 memset(&ac97, 0, sizeof(ac97));
1921 ac97.private_data = chip;
1922 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1923 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1924 if (chip->device_type != DEVICE_ALI) {
1925 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1926 ops = &standard_bus_ops;
1927 if (chip->device_type == DEVICE_INTEL_ICH4) {
1929 if (glob_sta & ICH_PCR)
1931 if (glob_sta & ICH_SCR)
1933 if (glob_sta & ICH_TCR)
1935 chip->in_sdin_init = 1;
1936 for (i = 0; i < codecs; i++) {
1937 snd_intel8x0_codec_read_test(chip, i);
1938 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1940 chip->in_sdin_init = 0;
1942 codecs = glob_sta & ICH_SCR ? 2 : 1;
1947 /* detect the secondary codec */
1948 for (i = 0; i < 100; i++) {
1949 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
1954 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
1958 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
1960 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1961 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
1962 if (ac97_clock >= 8000 && ac97_clock <= 48000)
1963 pbus->clock = ac97_clock;
1964 /* FIXME: my test board doesn't work well with VRA... */
1965 if (chip->device_type == DEVICE_ALI)
1967 chip->ac97_bus = pbus;
1969 ac97.pci = chip->pci;
1970 for (i = 0; i < codecs; i++) {
1972 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1974 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
1980 /* tune up the primary codec */
1981 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, ac97_quirk);
1982 /* enable separate SDINs for ICH4 */
1983 if (chip->device_type == DEVICE_INTEL_ICH4)
1985 /* find the available PCM streams */
1986 i = ARRAY_SIZE(ac97_pcm_defs);
1987 if (chip->device_type != DEVICE_INTEL_ICH4)
1988 i -= 2; /* do not allocate PCM2IN and MIC2 */
1990 i--; /* do not allocate S/PDIF */
1991 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
1994 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
1995 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
1996 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
1998 chip->ichd[spdif_idx].pcm = &pbus->pcms[3];
1999 if (chip->device_type == DEVICE_INTEL_ICH4) {
2000 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2001 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2003 /* enable separate SDINs for ICH4 */
2004 if (chip->device_type == DEVICE_INTEL_ICH4) {
2005 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2006 u8 tmp = igetbyte(chip, ICHREG(SDM));
2007 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2009 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2010 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2011 for (i = 1; i < 4; i++) {
2012 if (pcm->r[0].codec[i]) {
2013 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2018 tmp &= ~ICH_SE; /* steer disable */
2020 iputbyte(chip, ICHREG(SDM), tmp);
2022 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2024 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2027 if (chip->device_type == DEVICE_INTEL_ICH4) {
2028 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2031 if (chip->device_type == DEVICE_NFORCE) {
2033 chip->ichd[spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2035 chip->in_ac97_init = 0;
2039 /* clear the cold-reset bit for the next chance */
2040 if (chip->device_type != DEVICE_ALI)
2041 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2050 static void do_ali_reset(intel8x0_t *chip)
2052 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2053 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2054 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2055 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2056 iputdword(chip, ICHREG(ALI_INTERFACECR),
2057 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2058 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2059 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2062 #define do_delay(chip) do {\
2063 set_current_state(TASK_UNINTERRUPTIBLE);\
2064 schedule_timeout(1);\
2067 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2069 unsigned long end_time;
2070 unsigned int cnt, status, nstatus;
2072 /* put logic to right state */
2073 /* first clear status bits */
2074 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2075 if (chip->device_type == DEVICE_NFORCE)
2076 status |= ICH_NVSPINT;
2077 cnt = igetdword(chip, ICHREG(GLOB_STA));
2078 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2080 /* ACLink on, 2 channels */
2081 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2082 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2083 /* finish cold or do warm reset */
2084 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2085 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2086 end_time = (jiffies + (HZ / 4)) + 1;
2088 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2091 } while (time_after_eq(end_time, jiffies));
2092 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2097 /* wait for any codec ready status.
2098 * Once it becomes ready it should remain ready
2099 * as long as we do not disable the ac97 link.
2101 end_time = jiffies + HZ;
2103 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2107 } while (time_after_eq(end_time, jiffies));
2109 /* no codec is found */
2110 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2114 if (chip->device_type == DEVICE_INTEL_ICH4)
2115 /* ICH4 can have three codecs */
2116 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2118 /* others up to two codecs */
2119 nstatus = ICH_PCR | ICH_SCR;
2121 /* wait for other codecs ready status. */
2122 end_time = jiffies + HZ / 4;
2123 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2125 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2132 for (i = 0; i < 3; i++)
2134 status |= get_ich_codec_bit(chip, i);
2135 /* wait until all the probed codecs are ready */
2136 end_time = jiffies + HZ;
2138 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2139 if (status == nstatus)
2142 } while (time_after_eq(end_time, jiffies));
2145 if (chip->device_type == DEVICE_SIS) {
2146 /* unmute the output on SIS7012 */
2147 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2149 if (chip->device_type == DEVICE_NFORCE) {
2150 /* enable SPDIF interrupt */
2152 pci_read_config_dword(chip->pci, 0x4c, &val);
2154 pci_write_config_dword(chip->pci, 0x4c, val);
2159 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2164 reg = igetdword(chip, ICHREG(ALI_SCR));
2165 if ((reg & 2) == 0) /* Cold required */
2168 reg |= 1; /* Warm */
2169 reg &= ~0x80000000; /* ACLink on */
2170 iputdword(chip, ICHREG(ALI_SCR), reg);
2172 for (i = 0; i < HZ / 2; i++) {
2173 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2177 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2182 for (i = 0; i < HZ / 2; i++) {
2183 reg = igetdword(chip, ICHREG(ALI_RTSR));
2184 if (reg & 0x80) /* primary codec */
2186 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2194 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2199 if (chip->device_type != DEVICE_ALI) {
2200 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2202 iagetword(chip, 0); /* clear semaphore flag */
2204 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2208 /* disable interrupts */
2209 for (i = 0; i < chip->bdbars_count; i++)
2210 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2211 /* reset channels */
2212 for (i = 0; i < chip->bdbars_count; i++)
2213 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2214 /* initialize Buffer Descriptor Lists */
2215 for (i = 0; i < chip->bdbars_count; i++)
2216 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2220 static int snd_intel8x0_free(intel8x0_t *chip)
2226 /* disable interrupts */
2227 for (i = 0; i < chip->bdbars_count; i++)
2228 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2229 /* reset channels */
2230 for (i = 0; i < chip->bdbars_count; i++)
2231 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2232 if (chip->device_type == DEVICE_NFORCE) {
2233 /* stop the spdif interrupt */
2235 pci_read_config_dword(chip->pci, 0x4c, &val);
2237 pci_write_config_dword(chip->pci, 0x4c, val);
2240 synchronize_irq(chip->irq);
2243 free_irq(chip->irq, (void *)chip);
2244 if (chip->bdbars.area) {
2245 if (chip->fix_nocache)
2246 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2247 snd_dma_free_pages(&chip->bdbars);
2249 if (chip->remap_addr)
2250 iounmap(chip->remap_addr);
2251 if (chip->remap_bmaddr)
2252 iounmap(chip->remap_bmaddr);
2253 pci_release_regions(chip->pci);
2262 static int intel8x0_suspend(snd_card_t *card, unsigned int state)
2264 intel8x0_t *chip = card->pm_private_data;
2267 for (i = 0; i < chip->pcm_devs; i++)
2268 snd_pcm_suspend_all(chip->pcm[i]);
2269 for (i = 0; i < 3; i++)
2271 snd_ac97_suspend(chip->ac97[i]);
2272 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2276 static int intel8x0_resume(snd_card_t *card, unsigned int state)
2278 intel8x0_t *chip = card->pm_private_data;
2281 pci_enable_device(chip->pci);
2282 pci_set_master(chip->pci);
2283 snd_intel8x0_chip_init(chip, 0);
2285 /* refill nocache */
2286 if (chip->fix_nocache)
2287 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2289 for (i = 0; i < 3; i++)
2291 snd_ac97_resume(chip->ac97[i]);
2293 /* refill nocache */
2294 if (chip->fix_nocache) {
2295 for (i = 0; i < chip->bdbars_count; i++) {
2296 ichdev_t *ichdev = &chip->ichd[i];
2297 if (ichdev->substream) {
2298 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2299 if (runtime->dma_area)
2300 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2305 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2308 #endif /* CONFIG_PM */
2310 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2312 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2314 snd_pcm_substream_t *subs;
2317 unsigned long pos, t;
2318 struct timeval start_time, stop_time;
2320 if (chip->ac97_bus->clock != 48000)
2321 return; /* specified in module option */
2323 subs = chip->pcm[0]->streams[0].substream;
2324 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2325 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2328 ichdev = &chip->ichd[ICHD_PCMOUT];
2329 ichdev->physbuf = subs->dma_buffer.addr;
2330 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2331 ichdev->substream = NULL; /* don't process interrupts */
2334 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2335 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2338 snd_intel8x0_setup_periods(chip, ichdev);
2339 port = ichdev->reg_offset;
2340 spin_lock_irq(&chip->reg_lock);
2342 if (chip->device_type != DEVICE_ALI)
2343 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2345 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2346 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2348 do_gettimeofday(&start_time);
2349 spin_unlock_irq(&chip->reg_lock);
2351 set_current_state(TASK_UNINTERRUPTIBLE);
2352 schedule_timeout(HZ / 20);
2354 /* FIXME: schedule() can take too long time and overlap the boundary.. */
2357 spin_lock_irq(&chip->reg_lock);
2358 /* check the position */
2359 pos = ichdev->fragsize1;
2360 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2361 pos += ichdev->position;
2362 do_gettimeofday(&stop_time);
2364 if (chip->device_type == DEVICE_ALI) {
2365 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2366 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2367 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2370 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2371 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2374 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2375 spin_unlock_irq(&chip->reg_lock);
2377 t = stop_time.tv_sec - start_time.tv_sec;
2379 t += stop_time.tv_usec - start_time.tv_usec;
2380 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2382 snd_printk(KERN_ERR "?? calculation error..\n");
2385 pos = (pos / 4) * 1000;
2386 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2387 if (pos < 40000 || pos >= 60000)
2388 /* abnormal value. hw problem? */
2389 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2390 else if (pos < 47500 || pos > 48500)
2391 /* not 48000Hz, tuning the clock.. */
2392 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2393 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2396 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2397 snd_info_buffer_t * buffer)
2399 intel8x0_t *chip = entry->private_data;
2402 snd_iprintf(buffer, "Intel8x0\n\n");
2403 if (chip->device_type == DEVICE_ALI)
2405 tmp = igetdword(chip, ICHREG(GLOB_STA));
2406 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2407 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2408 if (chip->device_type == DEVICE_INTEL_ICH4)
2409 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2410 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2411 tmp & ICH_PCR ? " primary" : "",
2412 tmp & ICH_SCR ? " secondary" : "",
2413 tmp & ICH_TCR ? " tertiary" : "",
2414 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2415 if (chip->device_type == DEVICE_INTEL_ICH4)
2416 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2419 chip->ac97_sdin[2]);
2422 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2424 snd_info_entry_t *entry;
2426 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2427 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2430 static int snd_intel8x0_dev_free(snd_device_t *device)
2432 intel8x0_t *chip = device->device_data;
2433 return snd_intel8x0_free(chip);
2436 struct ich_reg_info {
2437 unsigned int int_sta_mask;
2438 unsigned int offset;
2441 static int __devinit snd_intel8x0_create(snd_card_t * card,
2442 struct pci_dev *pci,
2443 unsigned long device_type,
2444 intel8x0_t ** r_intel8x0)
2449 unsigned int int_sta_masks;
2451 static snd_device_ops_t ops = {
2452 .dev_free = snd_intel8x0_dev_free,
2455 static unsigned int bdbars[] = {
2456 3, /* DEVICE_INTEL */
2457 6, /* DEVICE_INTEL_ICH4 */
2460 4, /* DEVICE_NFORCE */
2462 static struct ich_reg_info intel_regs[6] = {
2464 { ICH_POINT, 0x10 },
2465 { ICH_MCINT, 0x20 },
2466 { ICH_M2INT, 0x40 },
2467 { ICH_P2INT, 0x50 },
2468 { ICH_SPINT, 0x60 },
2470 static struct ich_reg_info nforce_regs[4] = {
2472 { ICH_POINT, 0x10 },
2473 { ICH_MCINT, 0x20 },
2474 { ICH_NVSPINT, 0x70 },
2476 static struct ich_reg_info ali_regs[6] = {
2477 { ALI_INT_PCMIN, 0x40 },
2478 { ALI_INT_PCMOUT, 0x50 },
2479 { ALI_INT_MICIN, 0x60 },
2480 { ALI_INT_CODECSPDIFOUT, 0x70 },
2481 { ALI_INT_SPDIFIN, 0xa0 },
2482 { ALI_INT_SPDIFOUT, 0xb0 },
2484 struct ich_reg_info *tbl;
2488 if ((err = pci_enable_device(pci)) < 0)
2491 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2494 spin_lock_init(&chip->reg_lock);
2495 spin_lock_init(&chip->ac97_lock);
2496 chip->device_type = device_type;
2501 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2502 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2503 chip->fix_nocache = 1; /* enable workaround */
2505 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2506 * Needs to return IRQ_HANDLED for unknown irqs.
2508 if (device_type == DEVICE_NFORCE)
2509 chip->buggy_irq = 1;
2511 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2516 if (device_type == DEVICE_ALI) {
2517 /* ALI5455 has no ac97 region */
2518 chip->bmaddr = pci_resource_start(pci, 0);
2522 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2524 chip->addr = pci_resource_start(pci, 2);
2525 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 2));
2526 if (!chip->remap_addr) {
2527 snd_printk("AC'97 space ioremap problem\n");
2528 snd_intel8x0_free(chip);
2532 chip->addr = pci_resource_start(pci, 0);
2534 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2536 chip->bmaddr = pci_resource_start(pci, 3);
2537 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, pci_resource_len(pci, 3));
2538 if (!chip->remap_bmaddr) {
2539 snd_printk("Controller space ioremap problem\n");
2540 snd_intel8x0_free(chip);
2544 chip->bmaddr = pci_resource_start(pci, 1);
2548 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2549 snd_printk("unable to grab IRQ %d\n", pci->irq);
2550 snd_intel8x0_free(chip);
2553 chip->irq = pci->irq;
2554 pci_set_master(pci);
2555 synchronize_irq(chip->irq);
2557 chip->bdbars_count = bdbars[device_type];
2559 /* initialize offsets */
2560 switch (device_type) {
2571 for (i = 0; i < chip->bdbars_count; i++) {
2572 ichdev = &chip->ichd[i];
2574 ichdev->reg_offset = tbl[i].offset;
2575 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2576 if (device_type == DEVICE_SIS) {
2577 /* SiS 7012 swaps the registers */
2578 ichdev->roff_sr = ICH_REG_OFF_PICB;
2579 ichdev->roff_picb = ICH_REG_OFF_SR;
2581 ichdev->roff_sr = ICH_REG_OFF_SR;
2582 ichdev->roff_picb = ICH_REG_OFF_PICB;
2584 if (device_type == DEVICE_ALI)
2585 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2586 /* SIS7012 handles the pcm data in bytes, others are in samples */
2587 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2590 /* allocate buffer descriptor lists */
2591 /* the start of each lists must be aligned to 8 bytes */
2592 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2593 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2594 &chip->bdbars) < 0) {
2595 snd_intel8x0_free(chip);
2596 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2599 /* tables must be aligned to 8 bytes here, but the kernel pages
2600 are much bigger, so we don't care (on i386) */
2601 /* workaround for 440MX */
2602 if (chip->fix_nocache)
2603 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2605 for (i = 0; i < chip->bdbars_count; i++) {
2606 ichdev = &chip->ichd[i];
2607 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2608 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2609 int_sta_masks |= ichdev->int_sta_mask;
2611 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2612 chip->int_sta_mask = int_sta_masks;
2614 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2615 snd_intel8x0_free(chip);
2619 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2621 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2622 snd_intel8x0_free(chip);
2626 snd_card_set_dev(card, &pci->dev);
2632 static struct shortname_table {
2635 } shortnames[] __devinitdata = {
2636 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2637 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2638 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2639 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2640 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2641 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2642 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2643 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2644 { PCI_DEVICE_ID_INTEL_ICH6_3, "Intel ICH6" },
2645 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2646 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2647 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2648 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2649 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2650 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2651 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2652 { 0x003a, "NVidia MCP04" },
2653 { 0x746d, "AMD AMD8111" },
2654 { 0x7445, "AMD AMD768" },
2655 { 0x5455, "ALi M5455" },
2659 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2660 const struct pci_device_id *pci_id)
2666 struct shortname_table *name;
2668 if (dev >= SNDRV_CARDS)
2675 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2679 switch (pci_id->driver_data) {
2681 strcpy(card->driver, "NFORCE");
2684 strcpy(card->driver, "ICH");
2688 strcpy(card->shortname, "Intel ICH");
2689 for (name = shortnames; name->id; name++) {
2690 if (pci->device == name->id) {
2691 strcpy(card->shortname, name->s);
2696 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2697 snd_card_free(card);
2701 chip->buggy_irq = 1;
2703 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2704 snd_card_free(card);
2707 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2708 snd_card_free(card);
2712 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2713 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
2715 -1, 0, &chip->rmidi)) < 0) {
2716 printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
2722 snd_intel8x0_proc_init(chip);
2724 sprintf(card->longname, "%s at 0x%lx, irq %i",
2725 card->shortname, chip->addr, chip->irq);
2727 if (! ac97_clock[dev])
2728 intel8x0_measure_ac97_clock(chip);
2730 if ((err = snd_card_register(card)) < 0) {
2731 snd_card_free(card);
2734 pci_set_drvdata(pci, card);
2739 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2741 snd_card_free(pci_get_drvdata(pci));
2742 pci_set_drvdata(pci, NULL);
2745 static struct pci_driver driver = {
2746 .name = "Intel ICH",
2747 .id_table = snd_intel8x0_ids,
2748 .probe = snd_intel8x0_probe,
2749 .remove = __devexit_p(snd_intel8x0_remove),
2750 SND_PCI_PM_CALLBACKS
2754 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2756 * initialize joystick/midi addresses
2759 #ifdef SUPPORT_JOYSTICK
2760 /* there is only one available device, so we keep it here */
2761 static struct pci_dev *ich_gameport_pci;
2762 static struct gameport ich_gameport = { .io = 0x200 };
2765 static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
2766 const struct pci_device_id *id)
2770 if (dev >= SNDRV_CARDS)
2777 pci_read_config_word(pci, 0xe6, &val);
2778 #ifdef SUPPORT_JOYSTICK
2780 if (joystick[dev]) {
2781 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
2782 printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n", ich_gameport.io);
2785 ich_gameport_pci = pci;
2786 gameport_register_port(&ich_gameport);
2793 if (mpu_port[dev] > 0) {
2794 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
2797 pci_read_config_byte(pci, 0xe2, &b);
2798 if (mpu_port[dev] == 0x300)
2802 pci_write_config_byte(pci, 0xe2, b);
2806 pci_write_config_word(pci, 0xe6, val);
2810 static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
2813 #ifdef SUPPORT_JOYSTICK
2814 if (ich_gameport_pci == pci) {
2815 gameport_unregister_port(&ich_gameport);
2816 release_region(ich_gameport.io, 8);
2817 ich_gameport_pci = NULL;
2820 /* disable joystick and MIDI */
2821 pci_read_config_word(pci, 0xe6, &val);
2823 pci_write_config_word(pci, 0xe6, val);
2826 static struct pci_device_id snd_intel8x0_joystick_ids[] = {
2827 { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82801AA */
2828 { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82901AB */
2829 { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
2830 { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
2831 { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH3 */
2832 // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
2833 // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
2834 { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE */
2835 { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE2 */
2836 { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE3 */
2840 static struct pci_driver joystick_driver = {
2841 .name = "Intel ICH Joystick",
2842 .id_table = snd_intel8x0_joystick_ids,
2843 .probe = snd_intel8x0_joystick_probe,
2844 .remove = __devexit_p(snd_intel8x0_joystick_remove),
2847 static int have_joystick;
2850 static int __init alsa_card_intel8x0_init(void)
2854 if ((err = pci_module_init(&driver)) < 0)
2857 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2858 if (pci_module_init(&joystick_driver) < 0) {
2859 snd_printdd(KERN_INFO "no joystick found\n");
2862 snd_printdd(KERN_INFO "joystick(s) found\n");
2870 static void __exit alsa_card_intel8x0_exit(void)
2872 pci_unregister_driver(&driver);
2873 #if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
2875 pci_unregister_driver(&joystick_driver);
2879 module_init(alsa_card_intel8x0_init)
2880 module_exit(alsa_card_intel8x0_exit)