sound/pci/intel8x0m.c

   1 /*
   2  *   ALSA modem driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *   This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
   7  *   of ALSA ICH sound driver intel8x0.c .
   8  *
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <sound/driver.h>
  27 #include <asm/io.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/slab.h>
  33 #include <linux/gameport.h>
  34 #include <linux/moduleparam.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/ac97_codec.h>
  38 #include <sound/info.h>
  39 #include <sound/mpu401.h>
  40 #include <sound/initval.h>
  41
  42 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  43 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440 modem");
  44 MODULE_LICENSE("GPL");
  45 MODULE_CLASSES("{sound}");
  46 MODULE_DEVICES("{{Intel,82801AA-ICH},"
  47                 "{Intel,82901AB-ICH0},"
  48                 "{Intel,82801BA-ICH2},"
  49                 "{Intel,82801CA-ICH3},"
  50                 "{Intel,82801DB-ICH4},"
  51                 "{Intel,ICH5},"
  52                 "{Intel,MX440}}");
  53
  54
  55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  58 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  59 static int boot_devs;
  60
  61 module_param_array(index, int, boot_devs, 0444);
  62 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
  63 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  64 module_param_array(id, charp, boot_devs, 0444);
  65 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
  66 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  67 module_param_array(enable, bool, boot_devs, 0444);
  68 MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard.");
  69 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  70 module_param_array(ac97_clock, int, boot_devs, 0444);
  71 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  72 MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
  73
  74 /*
  75  *  Direct registers
  76  */
  77
  78 #ifndef PCI_DEVICE_ID_INTEL_82801_6
  79 #define PCI_DEVICE_ID_INTEL_82801_6     0x2416
  80 #endif
  81 #ifndef PCI_DEVICE_ID_INTEL_82901_6
  82 #define PCI_DEVICE_ID_INTEL_82901_6     0x2426
  83 #endif
  84 #ifndef PCI_DEVICE_ID_INTEL_82801BA_6
  85 #define PCI_DEVICE_ID_INTEL_82801BA_6   0x2446
  86 #endif
  87 #ifndef PCI_DEVICE_ID_INTEL_440MX_6
  88 #define PCI_DEVICE_ID_INTEL_440MX_6     0x7196
  89 #endif
  90 #ifndef PCI_DEVICE_ID_INTEL_ICH3_6
  91 #define PCI_DEVICE_ID_INTEL_ICH3_6      0x2486
  92 #endif
  93 #ifndef PCI_DEVICE_ID_INTEL_ICH4_6
  94 #define PCI_DEVICE_ID_INTEL_ICH4_6      0x24c6
  95 #endif
  96 #ifndef PCI_DEVICE_ID_INTEL_ICH5_6
  97 #define PCI_DEVICE_ID_INTEL_ICH5_6      0x24d6
  98 #endif
  99 #ifndef PCI_DEVICE_ID_SI_7013
 100 #define PCI_DEVICE_ID_SI_7013           0x7013
 101 #endif
 102 #if 0
 103 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
 104 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO  0x01b1
 105 #endif
 106 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
 107 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
 108 #endif
 109 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
 110 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
 111 #endif
 112 #endif
 113
 114 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 115
 116 #define ICHREG(x) ICH_REG_##x
 117
 118 #define DEFINE_REGSET(name,base) \
 119 enum { \
 120         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 121         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 122         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 123         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 124         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 125         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 126         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 127 };
 128
 129 /* busmaster blocks */
 130 DEFINE_REGSET(OFF, 0);          /* offset */
 131
 132 /* values for each busmaster block */
 133
 134 /* LVI */
 135 #define ICH_REG_LVI_MASK                0x1f
 136
 137 /* SR */
 138 #define ICH_FIFOE                       0x10    /* FIFO error */
 139 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 140 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 141 #define ICH_CELV                        0x02    /* current equals last valid */
 142 #define ICH_DCH                         0x01    /* DMA controller halted */
 143
 144 /* PIV */
 145 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 146
 147 /* CR */
 148 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 149 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 150 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 151 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 152 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 153
 154
 155 /* global block */
 156 #define ICH_REG_GLOB_CNT                0x3c    /* dword - global control */
 157 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 158 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 159 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 160 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 161 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 162 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 163 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 164 #define ICH_REG_GLOB_STA                0x40    /* dword - global status */
 165 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 166 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 167 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 168 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 169 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 170 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 171 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 172 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 173 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 174 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 175 #define   ICH_RCS               0x00008000      /* read completion status */
 176 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 177 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 178 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 179 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 180 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 181 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 182 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 183 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 184 #define   ICH_POINT             0x00000040      /* playback interrupt */
 185 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 186 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 187 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 188 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 189 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 190 #define ICH_REG_ACC_SEMA                0x44    /* byte - codec write semaphore */
 191 #define   ICH_CAS               0x01            /* codec access semaphore */
 192
 193 #define ICH_MAX_FRAGS           32              /* max hw frags */
 194
 195
 196 /*
 197  *
 198  */
 199
 200 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
 201 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
 202
 203 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 204
 205 typedef struct {
 206         unsigned int ichd;                      /* ich device number */
 207         unsigned long reg_offset;               /* offset to bmaddr */
 208         u32 *bdbar;                             /* CPU address (32bit) */
 209         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 210         snd_pcm_substream_t *substream;
 211         unsigned int physbuf;                   /* physical address (32bit) */
 212         unsigned int size;
 213         unsigned int fragsize;
 214         unsigned int fragsize1;
 215         unsigned int position;
 216         int frags;
 217         int lvi;
 218         int lvi_frag;
 219         int civ;
 220         int ack;
 221         int ack_reload;
 222         unsigned int ack_bit;
 223         unsigned int roff_sr;
 224         unsigned int roff_picb;
 225         unsigned int int_sta_mask;              /* interrupt status mask */
 226         unsigned int ali_slot;                  /* ALI DMA slot */
 227         ac97_t *ac97;
 228 } ichdev_t;
 229
 230 typedef struct _snd_intel8x0m intel8x0_t;
 231 #define chip_t intel8x0_t
 232
 233 struct _snd_intel8x0m {
 234         unsigned int device_type;
 235         char ac97_name[64];
 236         char ctrl_name[64];
 237
 238         int irq;
 239
 240         unsigned int mmio;
 241         unsigned long addr;
 242         unsigned long remap_addr;
 243         struct resource *res;
 244         unsigned int bm_mmio;
 245         unsigned long bmaddr;
 246         unsigned long remap_bmaddr;
 247         struct resource *res_bm;
 248
 249         struct pci_dev *pci;
 250         snd_card_t *card;
 251
 252         int pcm_devs;
 253         snd_pcm_t *pcm[2];
 254         ichdev_t ichd[2];
 255
 256         int in_ac97_init: 1;
 257
 258         ac97_bus_t *ac97_bus;
 259         ac97_t *ac97;
 260
 261         spinlock_t reg_lock;
 262         spinlock_t ac97_lock;
 263
 264         struct snd_dma_device dma_dev;
 265         struct snd_dma_buffer bdbars;
 266         u32 bdbars_count;
 267         u32 int_sta_reg;                /* interrupt status register */
 268         u32 int_sta_mask;               /* interrupt status mask */
 269         unsigned int pcm_pos_shift;
 270 };
 271
 272 static struct pci_device_id snd_intel8x0m_ids[] = {
 273         { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 274         { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 275         { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 276         { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 277         { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
 278         { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
 279         { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 280         { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 281 #if 0
 282         /* TODO: support needed */
 283         { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7013 */
 284         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 285         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 286         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 287         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 288         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 289 #endif
 290         { 0, }
 291 };
 292
 293 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
 294
 295 /*
 296  *  Lowlevel I/O - busmaster
 297  */
 298
 299 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 300 {
 301         if (chip->bm_mmio)
 302                 return readb(chip->remap_bmaddr + offset);
 303         else
 304                 return inb(chip->bmaddr + offset);
 305 }
 306
 307 static u16 igetword(intel8x0_t *chip, u32 offset)
 308 {
 309         if (chip->bm_mmio)
 310                 return readw(chip->remap_bmaddr + offset);
 311         else
 312                 return inw(chip->bmaddr + offset);
 313 }
 314
 315 static u32 igetdword(intel8x0_t *chip, u32 offset)
 316 {
 317         if (chip->bm_mmio)
 318                 return readl(chip->remap_bmaddr + offset);
 319         else
 320                 return inl(chip->bmaddr + offset);
 321 }
 322
 323 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 324 {
 325         if (chip->bm_mmio)
 326                 writeb(val, chip->remap_bmaddr + offset);
 327         else
 328                 outb(val, chip->bmaddr + offset);
 329 }
 330
 331 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 332 {
 333         if (chip->bm_mmio)
 334                 writel(val, chip->remap_bmaddr + offset);
 335         else
 336                 outl(val, chip->bmaddr + offset);
 337 }
 338
 339 /*
 340  *  Lowlevel I/O - AC'97 registers
 341  */
 342
 343 static u16 iagetword(intel8x0_t *chip, u32 offset)
 344 {
 345         if (chip->mmio)
 346                 return readw(chip->remap_addr + offset);
 347         else
 348                 return inw(chip->addr + offset);
 349 }
 350
 351 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 352 {
 353         if (chip->mmio)
 354                 writew(val, chip->remap_addr + offset);
 355         else
 356                 outw(val, chip->addr + offset);
 357 }
 358
 359 /*
 360  *  Basic I/O
 361  */
 362
 363 /*
 364  * access to AC97 codec via normal i/o (for ICH and SIS7013)
 365  */
 366
 367 /* return the GLOB_STA bit for the corresponding codec */
 368 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 369 {
 370         static unsigned int codec_bit[3] = {
 371                 ICH_PCR, ICH_SCR, ICH_TCR
 372         };
 373         snd_assert(codec < 3, return ICH_PCR);
 374         return codec_bit[codec];
 375 }
 376
 377 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 378 {
 379         int time;
 380
 381         if (codec > 1)
 382                 return -EIO;
 383         codec = get_ich_codec_bit(chip, codec);
 384
 385         /* codec ready ? */
 386         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 387                 return -EIO;
 388
 389         /* Anyone holding a semaphore for 1 msec should be shot... */
 390         time = 100;
 391         do {
 392                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 393                         return 0;
 394                 udelay(10);
 395         } while (time--);
 396
 397         /* access to some forbidden (non existant) ac97 registers will not
 398          * reset the semaphore. So even if you don't get the semaphore, still
 399          * continue the access. We don't need the semaphore anyway. */
 400         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 401                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 402         iagetword(chip, 0);     /* clear semaphore flag */
 403         /* I don't care about the semaphore */
 404         return -EBUSY;
 405 }
 406
 407 static void snd_intel8x0_codec_write(ac97_t *ac97,
 408                                      unsigned short reg,
 409                                      unsigned short val)
 410 {
 411         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
 412
 413         spin_lock(&chip->ac97_lock);
 414         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 415                 if (! chip->in_ac97_init)
 416                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 417         }
 418         iaputword(chip, reg + ac97->num * 0x80, val);
 419         spin_unlock(&chip->ac97_lock);
 420 }
 421
 422 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 423                                               unsigned short reg)
 424 {
 425         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
 426         unsigned short res;
 427         unsigned int tmp;
 428
 429         spin_lock(&chip->ac97_lock);
 430         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 431                 if (! chip->in_ac97_init)
 432                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 433                 res = 0xffff;
 434         } else {
 435                 res = iagetword(chip, reg + ac97->num * 0x80);
 436                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 437                         /* reset RCS and preserve other R/WC bits */
 438                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 439                         if (! chip->in_ac97_init)
 440                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 441                         res = 0xffff;
 442                 }
 443         }
 444         spin_unlock(&chip->ac97_lock);
 445         return res;
 446 }
 447
 448
 449 /*
 450  * DMA I/O
 451  */
 452 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 453 {
 454         int idx;
 455         u32 *bdbar = ichdev->bdbar;
 456         unsigned long port = ichdev->reg_offset;
 457
 458         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 459         if (ichdev->size == ichdev->fragsize) {
 460                 ichdev->ack_reload = ichdev->ack = 2;
 461                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 462                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 463                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 464                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 465                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 466                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 467                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 468                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 469                 }
 470                 ichdev->frags = 2;
 471         } else {
 472                 ichdev->ack_reload = ichdev->ack = 1;
 473                 ichdev->fragsize1 = ichdev->fragsize;
 474                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 475                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 476                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 477                                                      ichdev->fragsize >> chip->pcm_pos_shift);
 478                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 479                 }
 480                 ichdev->frags = ichdev->size / ichdev->fragsize;
 481         }
 482         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 483         ichdev->civ = 0;
 484         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 485         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 486         ichdev->position = 0;
 487 #if 0
 488         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 489                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 490 #endif
 491         /* clear interrupts */
 492         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 493 }
 494
 495 /*
 496  *  Interrupt handler
 497  */
 498
 499 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 500 {
 501         unsigned long port = ichdev->reg_offset;
 502         int civ, i, step;
 503         int ack = 0;
 504
 505         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 506         if (civ == ichdev->civ) {
 507                 // snd_printd("civ same %d\n", civ);
 508                 step = 1;
 509                 ichdev->civ++;
 510                 ichdev->civ &= ICH_REG_LVI_MASK;
 511         } else {
 512                 step = civ - ichdev->civ;
 513                 if (step < 0)
 514                         step += ICH_REG_LVI_MASK + 1;
 515                 // if (step != 1)
 516                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 517                 ichdev->civ = civ;
 518         }
 519
 520         ichdev->position += step * ichdev->fragsize1;
 521         ichdev->position %= ichdev->size;
 522         ichdev->lvi += step;
 523         ichdev->lvi &= ICH_REG_LVI_MASK;
 524         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 525         for (i = 0; i < step; i++) {
 526                 ichdev->lvi_frag++;
 527                 ichdev->lvi_frag %= ichdev->frags;
 528                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 529         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 530                 if (--ichdev->ack == 0) {
 531                         ichdev->ack = ichdev->ack_reload;
 532                         ack = 1;
 533                 }
 534         }
 535         if (ack && ichdev->substream) {
 536                 spin_unlock(&chip->reg_lock);
 537                 snd_pcm_period_elapsed(ichdev->substream);
 538                 spin_lock(&chip->reg_lock);
 539         }
 540         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 541 }
 542
 543 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 544 {
 545         intel8x0_t *chip = snd_magic_cast(intel8x0_t, dev_id, return IRQ_NONE);
 546         ichdev_t *ichdev;
 547         unsigned int status;
 548         unsigned int i;
 549
 550         spin_lock(&chip->reg_lock);
 551         status = igetdword(chip, chip->int_sta_reg);
 552         if ((status & chip->int_sta_mask) == 0) {
 553                 if (status)
 554                         iputdword(chip, chip->int_sta_reg, status);
 555                 spin_unlock(&chip->reg_lock);
 556                 return IRQ_NONE;
 557         }
 558
 559         for (i = 0; i < chip->bdbars_count; i++) {
 560                 ichdev = &chip->ichd[i];
 561                 if (status & ichdev->int_sta_mask)
 562                         snd_intel8x0_update(chip, ichdev);
 563         }
 564
 565         /* ack them */
 566         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 567         spin_unlock(&chip->reg_lock);
 568
 569         return IRQ_HANDLED;
 570 }
 571
 572 /*
 573  *  PCM part
 574  */
 575
 576 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 577 {
 578         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 579         ichdev_t *ichdev = get_ichdev(substream);
 580         unsigned char val = 0;
 581         unsigned long port = ichdev->reg_offset;
 582
 583         switch (cmd) {
 584         case SNDRV_PCM_TRIGGER_START:
 585         case SNDRV_PCM_TRIGGER_RESUME:
 586                 val = ICH_IOCE | ICH_STARTBM;
 587                 break;
 588         case SNDRV_PCM_TRIGGER_STOP:
 589         case SNDRV_PCM_TRIGGER_SUSPEND:
 590                 val = 0;
 591                 break;
 592         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 593                 val = ICH_IOCE;
 594                 break;
 595         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 596                 val = ICH_IOCE | ICH_STARTBM;
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 602         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 603                 /* wait until DMA stopped */
 604                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 605                 /* reset whole DMA things */
 606                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 607         }
 608         return 0;
 609 }
 610
 611 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 612                                   snd_pcm_hw_params_t * hw_params)
 613 {
 614         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 615 }
 616
 617 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 618 {
 619         return snd_pcm_lib_free_pages(substream);
 620 }
 621
 622 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
 623 {
 624         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 625         ichdev_t *ichdev = get_ichdev(substream);
 626         size_t ptr1, ptr;
 627
 628         ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
 629         if (ptr1 != 0)
 630                 ptr = ichdev->fragsize1 - ptr1;
 631         else
 632                 ptr = 0;
 633         ptr += ichdev->position;
 634         if (ptr >= ichdev->size)
 635                 return 0;
 636         return bytes_to_frames(substream->runtime, ptr);
 637 }
 638
 639 static int snd_intel8x0m_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 640 {
 641         ichdev_t *ichdev = get_ichdev(substream);
 642         /* hook off/on on start/stop */
 643         /* TODO: move it to ac97 controls */
 644         switch (cmd) {
 645         case SNDRV_PCM_TRIGGER_START:
 646                 snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
 647                                      AC97_GPIO_LINE1_OH, AC97_GPIO_LINE1_OH);
 648                 break;
 649         case SNDRV_PCM_TRIGGER_STOP:
 650                 snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
 651                                      AC97_GPIO_LINE1_OH, ~AC97_GPIO_LINE1_OH);
 652                 break;
 653         default:
 654                 return -EINVAL;
 655         }
 656         return snd_intel8x0_pcm_trigger(substream,cmd);
 657 }
 658
 659 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
 660 {
 661         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 662         snd_pcm_runtime_t *runtime = substream->runtime;
 663         ichdev_t *ichdev = get_ichdev(substream);
 664
 665         ichdev->physbuf = runtime->dma_addr;
 666         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
 667         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
 668         snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
 669         snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
 670         snd_intel8x0_setup_periods(chip, ichdev);
 671         return 0;
 672 }
 673
 674 static snd_pcm_hardware_t snd_intel8x0m_stream =
 675 {
 676         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 677                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 678                                  SNDRV_PCM_INFO_MMAP_VALID |
 679                                  SNDRV_PCM_INFO_PAUSE |
 680                                  SNDRV_PCM_INFO_RESUME),
 681         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 682         .rates =                SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
 683         .rate_min =             8000,
 684         .rate_max =             16000,
 685         .channels_min =         1,
 686         .channels_max =         1,
 687         .buffer_bytes_max =     32 * 1024,
 688         .period_bytes_min =     32,
 689         .period_bytes_max =     32 * 1024,
 690         .periods_min =          1,
 691         .periods_max =          1024,
 692         .fifo_size =            0,
 693 };
 694
 695
 696 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
 697 {
 698         static unsigned int rates[] = { 8000,  9600, 12000, 16000 };
 699         static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
 700                 .count = ARRAY_SIZE(rates),
 701                 .list = rates,
 702                 .mask = 0,
 703         };
 704         snd_pcm_runtime_t *runtime = substream->runtime;
 705         int err;
 706
 707         ichdev->substream = substream;
 708         runtime->hw = snd_intel8x0m_stream;
 709         err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
 710         if ( err < 0 )
 711                 return err;
 712         runtime->private_data = ichdev;
 713         return 0;
 714 }
 715
 716 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
 717 {
 718         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 719
 720         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
 721 }
 722
 723 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
 724 {
 725         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 726
 727         chip->ichd[ICHD_MDMOUT].substream = NULL;
 728         return 0;
 729 }
 730
 731 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
 732 {
 733         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 734
 735         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
 736 }
 737
 738 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
 739 {
 740         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 741
 742         chip->ichd[ICHD_MDMIN].substream = NULL;
 743         return 0;
 744 }
 745
 746
 747 static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
 748         .open =         snd_intel8x0m_playback_open,
 749         .close =        snd_intel8x0m_playback_close,
 750         .ioctl =        snd_pcm_lib_ioctl,
 751         .hw_params =    snd_intel8x0_hw_params,
 752         .hw_free =      snd_intel8x0_hw_free,
 753         .prepare =      snd_intel8x0m_pcm_prepare,
 754         .trigger =      snd_intel8x0m_pcm_trigger,
 755         .pointer =      snd_intel8x0_pcm_pointer,
 756 };
 757
 758 static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
 759         .open =         snd_intel8x0m_capture_open,
 760         .close =        snd_intel8x0m_capture_close,
 761         .ioctl =        snd_pcm_lib_ioctl,
 762         .hw_params =    snd_intel8x0_hw_params,
 763         .hw_free =      snd_intel8x0_hw_free,
 764         .prepare =      snd_intel8x0m_pcm_prepare,
 765         .trigger =      snd_intel8x0m_pcm_trigger,
 766         .pointer =      snd_intel8x0_pcm_pointer,
 767 };
 768
 769
 770 struct ich_pcm_table {
 771         char *suffix;
 772         snd_pcm_ops_t *playback_ops;
 773         snd_pcm_ops_t *capture_ops;
 774         size_t prealloc_size;
 775         size_t prealloc_max_size;
 776         int ac97_idx;
 777 };
 778
 779 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
 780 {
 781         snd_pcm_t *pcm;
 782         int err;
 783         char name[32];
 784
 785         if (rec->suffix)
 786                 sprintf(name, "Intel ICH - %s", rec->suffix);
 787         else
 788                 strcpy(name, "Intel ICH");
 789         err = snd_pcm_new(chip->card, name, device,
 790                           rec->playback_ops ? 1 : 0,
 791                           rec->capture_ops ? 1 : 0, &pcm);
 792         if (err < 0)
 793                 return err;
 794
 795         if (rec->playback_ops)
 796                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
 797         if (rec->capture_ops)
 798                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
 799
 800         pcm->private_data = chip;
 801         pcm->info_flags = 0;
 802         if (rec->suffix)
 803                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
 804         else
 805                 strcpy(pcm->name, chip->card->shortname);
 806         chip->pcm[device] = pcm;
 807
 808         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 809                                               snd_dma_pci_data(chip->pci),
 810                                               rec->prealloc_size,
 811                                               rec->prealloc_max_size);
 812
 813         return 0;
 814 }
 815
 816 static struct ich_pcm_table intel_pcms[] __devinitdata = {
 817         {
 818                 .suffix = "Modem",
 819                 .playback_ops = &snd_intel8x0m_playback_ops,
 820                 .capture_ops = &snd_intel8x0m_capture_ops,
 821                 .prealloc_size = 4 * 1024,
 822                 .prealloc_max_size = 16 * 1024,
 823         },
 824 };
 825
 826 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
 827 {
 828         int i, tblsize, device, err;
 829         struct ich_pcm_table *tbl, *rec;
 830
 831 #if 1
 832         tbl = intel_pcms;
 833         tblsize = 1;
 834 #else
 835         switch (chip->device_type) {
 836         case DEVICE_NFORCE:
 837                 tbl = nforce_pcms;
 838                 tblsize = ARRAY_SIZE(nforce_pcms);
 839                 break;
 840         case DEVICE_ALI:
 841                 tbl = ali_pcms;
 842                 tblsize = ARRAY_SIZE(ali_pcms);
 843                 break;
 844         default:
 845                 tbl = intel_pcms;
 846                 tblsize = 2;
 847                 break;
 848         }
 849 #endif
 850         device = 0;
 851         for (i = 0; i < tblsize; i++) {
 852                 rec = tbl + i;
 853                 if (i > 0 && rec->ac97_idx) {
 854                         /* activate PCM only when associated AC'97 codec */
 855                         if (! chip->ichd[rec->ac97_idx].ac97)
 856                                 continue;
 857                 }
 858                 err = snd_intel8x0_pcm1(chip, device, rec);
 859                 if (err < 0)
 860                         return err;
 861                 device++;
 862         }
 863
 864         chip->pcm_devs = device;
 865         return 0;
 866 }
 867
 868
 869 /*
 870  *  Mixer part
 871  */
 872
 873 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
 874 {
 875         intel8x0_t *chip = snd_magic_cast(intel8x0_t, bus->private_data, return);
 876         chip->ac97_bus = NULL;
 877 }
 878
 879 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
 880 {
 881         intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
 882         chip->ac97 = NULL;
 883 }
 884
 885
 886 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
 887 {
 888         ac97_bus_t bus, *pbus;
 889         ac97_t ac97, *x97;
 890         int err;
 891         unsigned int glob_sta = 0;
 892
 893         chip->in_ac97_init = 1;
 894         memset(&bus, 0, sizeof(bus));
 895         bus.private_data = chip;
 896         bus.private_free = snd_intel8x0_mixer_free_ac97_bus;
 897         if (ac97_clock >= 8000 && ac97_clock <= 48000)
 898                 bus.clock = ac97_clock;
 899         else
 900                 bus.clock = 48000;
 901
 902         memset(&ac97, 0, sizeof(ac97));
 903         ac97.private_data = chip;
 904         ac97.private_free = snd_intel8x0_mixer_free_ac97;
 905         ac97.scaps = AC97_SCAP_SKIP_AUDIO;
 906
 907         glob_sta = igetdword(chip, ICHREG(GLOB_STA));
 908         bus.write = snd_intel8x0_codec_write;
 909         bus.read = snd_intel8x0_codec_read;
 910         bus.vra = 1;
 911
 912         if ((err = snd_ac97_bus(chip->card, &bus, &pbus)) < 0)
 913                 goto __err;
 914         chip->ac97_bus = pbus;
 915         ac97.pci = chip->pci;
 916         ac97.num = glob_sta & ICH_SCR ? 1 : 0;
 917         if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
 918                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
 919                 if (ac97.num == 0)
 920                         goto __err;
 921                 return err;
 922         }
 923         chip->ac97 = x97;
 924         if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97 ) {
 925                 chip->ichd[ICHD_MDMIN].ac97 = x97;
 926                 chip->ichd[ICHD_MDMOUT].ac97 = x97;
 927         }
 928
 929         chip->in_ac97_init = 0;
 930         return 0;
 931
 932  __err:
 933         /* clear the cold-reset bit for the next chance */
 934         if (chip->device_type != DEVICE_ALI)
 935                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
 936         return err;
 937 }
 938
 939
 940 /*
 941  *
 942  */
 943
 944 #define do_delay(chip) do {\
 945         set_current_state(TASK_UNINTERRUPTIBLE);\
 946         schedule_timeout(1);\
 947 } while (0)
 948
 949 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
 950 {
 951         unsigned long end_time;
 952         unsigned int cnt, status, nstatus;
 953
 954         /* put logic to right state */
 955         /* first clear status bits */
 956         status = ICH_RCS | ICH_MIINT | ICH_MOINT;
 957         cnt = igetdword(chip, ICHREG(GLOB_STA));
 958         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
 959
 960         /* ACLink on, 2 channels */
 961         cnt = igetdword(chip, ICHREG(GLOB_CNT));
 962         cnt &= ~(ICH_ACLINK);
 963         /* finish cold or do warm reset */
 964         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
 965         iputdword(chip, ICHREG(GLOB_CNT), cnt);
 966         end_time = (jiffies + (HZ / 4)) + 1;
 967         do {
 968                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
 969                         goto __ok;
 970                 do_delay(chip);
 971         } while (time_after_eq(end_time, jiffies));
 972         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
 973         return -EIO;
 974
 975       __ok:
 976         if (probing) {
 977                 /* wait for any codec ready status.
 978                  * Once it becomes ready it should remain ready
 979                  * as long as we do not disable the ac97 link.
 980                  */
 981                 end_time = jiffies + HZ;
 982                 do {
 983                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
 984                         if (status)
 985                                 break;
 986                         do_delay(chip);
 987                 } while (time_after_eq(end_time, jiffies));
 988                 if (! status) {
 989                         /* no codec is found */
 990                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
 991                         return -EIO;
 992                 }
 993
 994                 /* up to two codecs (modem cannot be tertiary with ICH4) */
 995                 nstatus = ICH_PCR | ICH_SCR;
 996
 997                 /* wait for other codecs ready status. */
 998                 end_time = jiffies + HZ / 4;
 999                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
1000                         do_delay(chip);
1001                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1002                 }
1003
1004         } else {
1005                 /* resume phase */
1006                 status = 0;
1007                 if (chip->ac97)
1008                         status |= get_ich_codec_bit(chip, chip->ac97->num);
1009                 /* wait until all the probed codecs are ready */
1010                 end_time = jiffies + HZ;
1011                 do {
1012                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1013                         if (status == nstatus)
1014                                 break;
1015                         do_delay(chip);
1016                 } while (time_after_eq(end_time, jiffies));
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
1023 {
1024         unsigned int i;
1025         int err;
1026
1027         if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
1028                 return err;
1029         iagetword(chip, 0);     /* clear semaphore flag */
1030
1031         /* disable interrupts */
1032         for (i = 0; i < chip->bdbars_count; i++)
1033                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1034         /* reset channels */
1035         for (i = 0; i < chip->bdbars_count; i++)
1036                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1037         /* initialize Buffer Descriptor Lists */
1038         for (i = 0; i < chip->bdbars_count; i++)
1039                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
1040         return 0;
1041 }
1042
1043 static int snd_intel8x0_free(intel8x0_t *chip)
1044 {
1045         unsigned int i;
1046
1047         if (chip->irq < 0)
1048                 goto __hw_end;
1049         /* disable interrupts */
1050         for (i = 0; i < chip->bdbars_count; i++)
1051                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1052         /* reset channels */
1053         for (i = 0; i < chip->bdbars_count; i++)
1054                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1055         /* --- */
1056         synchronize_irq(chip->irq);
1057       __hw_end:
1058         if (chip->bdbars.area)
1059                 snd_dma_free_pages(&chip->dma_dev, &chip->bdbars);
1060         if (chip->remap_addr)
1061                 iounmap((void *) chip->remap_addr);
1062         if (chip->remap_bmaddr)
1063                 iounmap((void *) chip->remap_bmaddr);
1064         if (chip->res) {
1065                 release_resource(chip->res);
1066                 kfree_nocheck(chip->res);
1067         }
1068         if (chip->res_bm) {
1069                 release_resource(chip->res_bm);
1070                 kfree_nocheck(chip->res_bm);
1071         }
1072         if (chip->irq >= 0)
1073                 free_irq(chip->irq, (void *)chip);
1074         snd_magic_kfree(chip);
1075         return 0;
1076 }
1077
1078 #ifdef CONFIG_PM
1079 /*
1080  * power management
1081  */
1082 static int intel8x0m_suspend(snd_card_t *card, unsigned int state)
1083 {
1084         intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->pm_private_data, return -EINVAL);
1085         int i;
1086
1087         for (i = 0; i < chip->pcm_devs; i++)
1088                 snd_pcm_suspend_all(chip->pcm[i]);
1089         if (chip->ac97)
1090                 snd_ac97_suspend(chip->ac97);
1091         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1092         return 0;
1093 }
1094
1095 static int intel8x0m_resume(snd_card_t *card, unsigned int state)
1096 {
1097         intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->pm_private_data, return -EINVAL);
1098         pci_enable_device(chip->pci);
1099         pci_set_master(chip->pci);
1100         snd_intel8x0_chip_init(chip, 0);
1101         if (chip->ac97)
1102                 snd_ac97_resume(chip->ac97);
1103
1104         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1105         return 0;
1106 }
1107 #endif /* CONFIG_PM */
1108
1109 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1110                                    snd_info_buffer_t * buffer)
1111 {
1112         intel8x0_t *chip = snd_magic_cast(intel8x0_t, entry->private_data, return);
1113         unsigned int tmp;
1114
1115         snd_iprintf(buffer, "Intel8x0m\n\n");
1116         if (chip->device_type == DEVICE_ALI)
1117                 return;
1118         tmp = igetdword(chip, ICHREG(GLOB_STA));
1119         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1120         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
1121         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
1122                         tmp & ICH_PCR ? " primary" : "",
1123                         tmp & ICH_SCR ? " secondary" : "",
1124                         tmp & ICH_TCR ? " tertiary" : "",
1125                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1126 }
1127
1128 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1129 {
1130         snd_info_entry_t *entry;
1131
1132         if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1133                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
1134 }
1135
1136 static int snd_intel8x0_dev_free(snd_device_t *device)
1137 {
1138         intel8x0_t *chip = snd_magic_cast(intel8x0_t, device->device_data, return -ENXIO);
1139         return snd_intel8x0_free(chip);
1140 }
1141
1142 struct ich_reg_info {
1143         unsigned int int_sta_mask;
1144         unsigned int offset;
1145 };
1146
1147 static int __devinit snd_intel8x0m_create(snd_card_t * card,
1148                                          struct pci_dev *pci,
1149                                          unsigned long device_type,
1150                                          intel8x0_t ** r_intel8x0)
1151 {
1152         intel8x0_t *chip;
1153         int err;
1154         unsigned int i;
1155         unsigned int int_sta_masks;
1156         ichdev_t *ichdev;
1157         static snd_device_ops_t ops = {
1158                 .dev_free =     snd_intel8x0_dev_free,
1159         };
1160         static struct ich_reg_info intel_regs[2] = {
1161                 { ICH_MIINT, 0 },
1162                 { ICH_MOINT, 0x10 },
1163         };
1164         struct ich_reg_info *tbl;
1165
1166         *r_intel8x0 = NULL;
1167
1168         if ((err = pci_enable_device(pci)) < 0)
1169                 return err;
1170
1171         chip = snd_magic_kcalloc(intel8x0_t, 0, GFP_KERNEL);
1172         if (chip == NULL)
1173                 return -ENOMEM;
1174         spin_lock_init(&chip->reg_lock);
1175         spin_lock_init(&chip->ac97_lock);
1176         chip->device_type = device_type;
1177         chip->card = card;
1178         chip->pci = pci;
1179         chip->irq = -1;
1180         snd_intel8x0m_proc_init(chip);
1181         sprintf(chip->ac97_name, "%s - AC'97", card->shortname);
1182         sprintf(chip->ctrl_name, "%s - Controller", card->shortname);
1183         if (device_type == DEVICE_ALI) {
1184                 /* ALI5455 has no ac97 region */
1185                 chip->bmaddr = pci_resource_start(pci, 0);
1186                 if ((chip->res_bm = request_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
1187                         snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 256 - 1);
1188                         snd_intel8x0_free(chip);
1189                         return -EBUSY;
1190                 }
1191                 goto port_inited;
1192         }
1193
1194         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
1195                 chip->mmio = 1;
1196                 chip->addr = pci_resource_start(pci, 2);
1197                 if ((chip->res = request_mem_region(chip->addr, 512, chip->ac97_name)) == NULL) {
1198                         snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->addr, chip->addr + 512 - 1);
1199                         snd_intel8x0_free(chip);
1200                         return -EBUSY;
1201                 }
1202                 chip->remap_addr = (unsigned long) ioremap_nocache(chip->addr, 512);
1203                 if (chip->remap_addr == 0) {
1204                         snd_printk("AC'97 space ioremap problem\n");
1205                         snd_intel8x0_free(chip);
1206                         return -EIO;
1207                 }
1208         } else {
1209                 chip->addr = pci_resource_start(pci, 0);
1210                 if ((chip->res = request_region(chip->addr, 256, chip->ac97_name)) == NULL) {
1211                         snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->addr, chip->addr + 256 - 1);
1212                         snd_intel8x0_free(chip);
1213                         return -EBUSY;
1214                 }
1215         }
1216         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
1217                 chip->bm_mmio = 1;
1218                 chip->bmaddr = pci_resource_start(pci, 3);
1219                 if ((chip->res_bm = request_mem_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
1220                         snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 512 - 1);
1221                         snd_intel8x0_free(chip);
1222                         return -EBUSY;
1223                 }
1224                 chip->remap_bmaddr = (unsigned long) ioremap_nocache(chip->bmaddr, 256);
1225                 if (chip->remap_bmaddr == 0) {
1226                         snd_printk("Controller space ioremap problem\n");
1227                         snd_intel8x0_free(chip);
1228                         return -EIO;
1229                 }
1230         } else {
1231                 chip->bmaddr = pci_resource_start(pci, 1);
1232                 if ((chip->res_bm = request_region(chip->bmaddr, 128, chip->ctrl_name)) == NULL) {
1233                         snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 128 - 1);
1234                         snd_intel8x0_free(chip);
1235                         return -EBUSY;
1236                 }
1237         }
1238
1239  port_inited:
1240         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1241                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1242                 snd_intel8x0_free(chip);
1243                 return -EBUSY;
1244         }
1245         chip->irq = pci->irq;
1246         pci_set_master(pci);
1247         synchronize_irq(chip->irq);
1248
1249         /* initialize offsets */
1250         chip->bdbars_count = 2;
1251         tbl = intel_regs;
1252
1253         for (i = 0; i < chip->bdbars_count; i++) {
1254                 ichdev = &chip->ichd[i];
1255                 ichdev->ichd = i;
1256                 ichdev->reg_offset = tbl[i].offset;
1257                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1258                 if (device_type == DEVICE_SIS) {
1259                         /* SiS 7013 swaps the registers */
1260                         ichdev->roff_sr = ICH_REG_OFF_PICB;
1261                         ichdev->roff_picb = ICH_REG_OFF_SR;
1262                 } else {
1263                         ichdev->roff_sr = ICH_REG_OFF_SR;
1264                         ichdev->roff_picb = ICH_REG_OFF_PICB;
1265                 }
1266                 if (device_type == DEVICE_ALI)
1267                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1268         }
1269         /* SIS7013 handles the pcm data in bytes, others are in words */
1270         chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1271
1272         /* allocate buffer descriptor lists */
1273         /* the start of each lists must be aligned to 8 bytes */
1274         memset(&chip->dma_dev, 0, sizeof(chip->dma_dev));
1275         chip->dma_dev.type = SNDRV_DMA_TYPE_DEV;
1276         chip->dma_dev.dev = snd_dma_pci_data(pci);
1277         if (snd_dma_alloc_pages(&chip->dma_dev, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, &chip->bdbars) < 0) {
1278                 snd_intel8x0_free(chip);
1279                 return -ENOMEM;
1280         }
1281         /* tables must be aligned to 8 bytes here, but the kernel pages
1282            are much bigger, so we don't care (on i386) */
1283         int_sta_masks = 0;
1284         for (i = 0; i < chip->bdbars_count; i++) {
1285                 ichdev = &chip->ichd[i];
1286                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1287                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1288                 int_sta_masks |= ichdev->int_sta_mask;
1289         }
1290         chip->int_sta_reg = ICH_REG_GLOB_STA;
1291         chip->int_sta_mask = int_sta_masks;
1292
1293         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1294                 snd_intel8x0_free(chip);
1295                 return err;
1296         }
1297
1298         snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
1299
1300         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1301                 snd_intel8x0_free(chip);
1302                 return err;
1303         }
1304
1305         snd_card_set_dev(card, &pci->dev);
1306
1307         *r_intel8x0 = chip;
1308         return 0;
1309 }
1310
1311 static struct shortname_table {
1312         unsigned int id;
1313         const char *s;
1314 } shortnames[] __devinitdata = {
1315         { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" },
1316         { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" },
1317         { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1318         { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1319         { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" },
1320         { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" },
1321         { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" },
1322         { 0x7446, "AMD AMD768" },
1323 #if 0
1324         { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1325         { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
1326         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
1327         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
1328         { 0x5455, "ALi M5455" },
1329         { 0x746d, "AMD AMD8111" },
1330 #endif
1331         { 0, 0 },
1332 };
1333
1334 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1335                                         const struct pci_device_id *pci_id)
1336 {
1337         static int dev;
1338         snd_card_t *card;
1339         intel8x0_t *chip;
1340         int err;
1341         struct shortname_table *name;
1342
1343         if (dev >= SNDRV_CARDS)
1344                 return -ENODEV;
1345         if (!enable[dev]) {
1346                 dev++;
1347                 return -ENOENT;
1348         }
1349
1350         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1351         if (card == NULL)
1352                 return -ENOMEM;
1353
1354         switch (pci_id->driver_data) {
1355         case DEVICE_NFORCE:
1356                 strcpy(card->driver, "NFORCE");
1357                 break;
1358         default:
1359                 strcpy(card->driver, "ICH");
1360                 break;
1361         }
1362
1363         strcpy(card->shortname, "Intel ICH");
1364         for (name = shortnames; name->id; name++) {
1365                 if (pci->device == name->id) {
1366                         strcpy(card->shortname, name->s);
1367                         break;
1368                 }
1369         }
1370         strcat(card->shortname," Modem");
1371
1372         if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1373                 snd_card_free(card);
1374                 return err;
1375         }
1376
1377         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
1378                 snd_card_free(card);
1379                 return err;
1380         }
1381         if ((err = snd_intel8x0_pcm(chip)) < 0) {
1382                 snd_card_free(card);
1383                 return err;
1384         }
1385
1386         sprintf(card->longname, "%s at 0x%lx, irq %i",
1387                 card->shortname, chip->addr, chip->irq);
1388
1389         if ((err = snd_card_register(card)) < 0) {
1390                 snd_card_free(card);
1391                 return err;
1392         }
1393         pci_set_drvdata(pci, card);
1394         dev++;
1395         return 0;
1396 }
1397
1398 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1399 {
1400         snd_card_free(pci_get_drvdata(pci));
1401         pci_set_drvdata(pci, NULL);
1402 }
1403
1404 static struct pci_driver driver = {
1405         .name = "Intel ICH Modem",
1406         .id_table = snd_intel8x0m_ids,
1407         .probe = snd_intel8x0m_probe,
1408         .remove = __devexit_p(snd_intel8x0m_remove),
1409         SND_PCI_PM_CALLBACKS
1410 };
1411
1412
1413 static int __init alsa_card_intel8x0m_init(void)
1414 {
1415         return pci_module_init(&driver);
1416 }
1417
1418 static void __exit alsa_card_intel8x0m_exit(void)
1419 {
1420         pci_unregister_driver(&driver);
1421 }
1422
1423 module_init(alsa_card_intel8x0m_init)
1424 module_exit(alsa_card_intel8x0m_exit)