sound/pci/intel8x0m.c

   1 /*
   2  *   ALSA modem driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *   This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
   7  *   of ALSA ICH sound driver intel8x0.c .
   8  *
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <sound/driver.h>
  27 #include <asm/io.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/slab.h>
  33 #include <linux/gameport.h>
  34 #include <linux/moduleparam.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/ac97_codec.h>
  38 #include <sound/info.h>
  39 #include <sound/mpu401.h>
  40 #include <sound/initval.h>
  41
  42 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  43 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
  44 MODULE_LICENSE("GPL");
  45 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  46                 "{Intel,82901AB-ICH0},"
  47                 "{Intel,82801BA-ICH2},"
  48                 "{Intel,82801CA-ICH3},"
  49                 "{Intel,82801DB-ICH4},"
  50                 "{Intel,ICH5},"
  51                 "{Intel,MX440}}");
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  57 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  58 static int boot_devs;
  59
  60 module_param_array(index, int, boot_devs, 0444);
  61 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
  62 module_param_array(id, charp, boot_devs, 0444);
  63 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
  64 module_param_array(enable, bool, boot_devs, 0444);
  65 MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard.");
  66 module_param_array(ac97_clock, int, boot_devs, 0444);
  67 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  68
  69 /*
  70  *  Direct registers
  71  */
  72
  73 #ifndef PCI_DEVICE_ID_INTEL_82801_6
  74 #define PCI_DEVICE_ID_INTEL_82801_6     0x2416
  75 #endif
  76 #ifndef PCI_DEVICE_ID_INTEL_82901_6
  77 #define PCI_DEVICE_ID_INTEL_82901_6     0x2426
  78 #endif
  79 #ifndef PCI_DEVICE_ID_INTEL_82801BA_6
  80 #define PCI_DEVICE_ID_INTEL_82801BA_6   0x2446
  81 #endif
  82 #ifndef PCI_DEVICE_ID_INTEL_440MX_6
  83 #define PCI_DEVICE_ID_INTEL_440MX_6     0x7196
  84 #endif
  85 #ifndef PCI_DEVICE_ID_INTEL_ICH3_6
  86 #define PCI_DEVICE_ID_INTEL_ICH3_6      0x2486
  87 #endif
  88 #ifndef PCI_DEVICE_ID_INTEL_ICH4_6
  89 #define PCI_DEVICE_ID_INTEL_ICH4_6      0x24c6
  90 #endif
  91 #ifndef PCI_DEVICE_ID_INTEL_ICH5_6
  92 #define PCI_DEVICE_ID_INTEL_ICH5_6      0x24d6
  93 #endif
  94 #ifndef PCI_DEVICE_ID_SI_7013
  95 #define PCI_DEVICE_ID_SI_7013           0x7013
  96 #endif
  97 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_MODEM
  98 #define PCI_DEVICE_ID_NVIDIA_MCP_MODEM  0x01c1
  99 #endif
 100 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_MODEM
 101 #define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069
 102 #endif
 103 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM
 104 #define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089
 105 #endif
 106 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_MODEM
 107 #define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9
 108 #endif
 109
 110
 111 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 112
 113 #define ICHREG(x) ICH_REG_##x
 114
 115 #define DEFINE_REGSET(name,base) \
 116 enum { \
 117         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 118         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 119         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 120         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 121         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 122         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 123         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 124 };
 125
 126 /* busmaster blocks */
 127 DEFINE_REGSET(OFF, 0);          /* offset */
 128
 129 /* values for each busmaster block */
 130
 131 /* LVI */
 132 #define ICH_REG_LVI_MASK                0x1f
 133
 134 /* SR */
 135 #define ICH_FIFOE                       0x10    /* FIFO error */
 136 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 137 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 138 #define ICH_CELV                        0x02    /* current equals last valid */
 139 #define ICH_DCH                         0x01    /* DMA controller halted */
 140
 141 /* PIV */
 142 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 143
 144 /* CR */
 145 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 146 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 147 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 148 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 149 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 150
 151
 152 /* global block */
 153 #define ICH_REG_GLOB_CNT                0x3c    /* dword - global control */
 154 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 155 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 156 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 157 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 158 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 159 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 160 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 161 #define ICH_REG_GLOB_STA                0x40    /* dword - global status */
 162 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 163 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 164 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 165 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 166 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 167 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 168 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 169 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 170 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 171 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 172 #define   ICH_RCS               0x00008000      /* read completion status */
 173 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 174 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 175 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 176 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 177 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 178 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 179 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 180 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 181 #define   ICH_POINT             0x00000040      /* playback interrupt */
 182 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 183 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 184 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 185 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 186 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 187 #define ICH_REG_ACC_SEMA                0x44    /* byte - codec write semaphore */
 188 #define   ICH_CAS               0x01            /* codec access semaphore */
 189
 190 #define ICH_MAX_FRAGS           32              /* max hw frags */
 191
 192
 193 /*
 194  *
 195  */
 196
 197 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
 198 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
 199
 200 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 201
 202 typedef struct {
 203         unsigned int ichd;                      /* ich device number */
 204         unsigned long reg_offset;               /* offset to bmaddr */
 205         u32 *bdbar;                             /* CPU address (32bit) */
 206         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 207         snd_pcm_substream_t *substream;
 208         unsigned int physbuf;                   /* physical address (32bit) */
 209         unsigned int size;
 210         unsigned int fragsize;
 211         unsigned int fragsize1;
 212         unsigned int position;
 213         int frags;
 214         int lvi;
 215         int lvi_frag;
 216         int civ;
 217         int ack;
 218         int ack_reload;
 219         unsigned int ack_bit;
 220         unsigned int roff_sr;
 221         unsigned int roff_picb;
 222         unsigned int int_sta_mask;              /* interrupt status mask */
 223         unsigned int ali_slot;                  /* ALI DMA slot */
 224         ac97_t *ac97;
 225 } ichdev_t;
 226
 227 typedef struct _snd_intel8x0m intel8x0_t;
 228
 229 struct _snd_intel8x0m {
 230         unsigned int device_type;
 231
 232         int irq;
 233
 234         unsigned int mmio;
 235         unsigned long addr;
 236         unsigned long remap_addr;
 237         unsigned int bm_mmio;
 238         unsigned long bmaddr;
 239         unsigned long remap_bmaddr;
 240
 241         struct pci_dev *pci;
 242         snd_card_t *card;
 243
 244         int pcm_devs;
 245         snd_pcm_t *pcm[2];
 246         ichdev_t ichd[2];
 247
 248         int in_ac97_init: 1;
 249
 250         ac97_bus_t *ac97_bus;
 251         ac97_t *ac97;
 252
 253         spinlock_t reg_lock;
 254         spinlock_t ac97_lock;
 255
 256         struct snd_dma_buffer bdbars;
 257         u32 bdbars_count;
 258         u32 int_sta_reg;                /* interrupt status register */
 259         u32 int_sta_mask;               /* interrupt status mask */
 260         unsigned int pcm_pos_shift;
 261 };
 262
 263 static struct pci_device_id snd_intel8x0m_ids[] = {
 264         { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 265         { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 266         { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 267         { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 268         { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
 269         { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
 270         { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 271         { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 272         { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7013 */
 273         { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
 274         { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
 275         { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
 276         { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
 277 #if 0
 278         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 279         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 280 #endif
 281         { 0, }
 282 };
 283
 284 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
 285
 286 /*
 287  *  Lowlevel I/O - busmaster
 288  */
 289
 290 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 291 {
 292         if (chip->bm_mmio)
 293                 return readb(chip->remap_bmaddr + offset);
 294         else
 295                 return inb(chip->bmaddr + offset);
 296 }
 297
 298 static u16 igetword(intel8x0_t *chip, u32 offset)
 299 {
 300         if (chip->bm_mmio)
 301                 return readw(chip->remap_bmaddr + offset);
 302         else
 303                 return inw(chip->bmaddr + offset);
 304 }
 305
 306 static u32 igetdword(intel8x0_t *chip, u32 offset)
 307 {
 308         if (chip->bm_mmio)
 309                 return readl(chip->remap_bmaddr + offset);
 310         else
 311                 return inl(chip->bmaddr + offset);
 312 }
 313
 314 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 315 {
 316         if (chip->bm_mmio)
 317                 writeb(val, chip->remap_bmaddr + offset);
 318         else
 319                 outb(val, chip->bmaddr + offset);
 320 }
 321
 322 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 323 {
 324         if (chip->bm_mmio)
 325                 writew(val, chip->remap_bmaddr + offset);
 326         else
 327                 outw(val, chip->bmaddr + offset);
 328 }
 329
 330 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 331 {
 332         if (chip->bm_mmio)
 333                 writel(val, chip->remap_bmaddr + offset);
 334         else
 335                 outl(val, chip->bmaddr + offset);
 336 }
 337
 338 /*
 339  *  Lowlevel I/O - AC'97 registers
 340  */
 341
 342 static u16 iagetword(intel8x0_t *chip, u32 offset)
 343 {
 344         if (chip->mmio)
 345                 return readw(chip->remap_addr + offset);
 346         else
 347                 return inw(chip->addr + offset);
 348 }
 349
 350 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 351 {
 352         if (chip->mmio)
 353                 writew(val, chip->remap_addr + offset);
 354         else
 355                 outw(val, chip->addr + offset);
 356 }
 357
 358 /*
 359  *  Basic I/O
 360  */
 361
 362 /*
 363  * access to AC97 codec via normal i/o (for ICH and SIS7013)
 364  */
 365
 366 /* return the GLOB_STA bit for the corresponding codec */
 367 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 368 {
 369         static unsigned int codec_bit[3] = {
 370                 ICH_PCR, ICH_SCR, ICH_TCR
 371         };
 372         snd_assert(codec < 3, return ICH_PCR);
 373         return codec_bit[codec];
 374 }
 375
 376 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 377 {
 378         int time;
 379
 380         if (codec > 1)
 381                 return -EIO;
 382         codec = get_ich_codec_bit(chip, codec);
 383
 384         /* codec ready ? */
 385         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 386                 return -EIO;
 387
 388         /* Anyone holding a semaphore for 1 msec should be shot... */
 389         time = 100;
 390         do {
 391                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 392                         return 0;
 393                 udelay(10);
 394         } while (time--);
 395
 396         /* access to some forbidden (non existant) ac97 registers will not
 397          * reset the semaphore. So even if you don't get the semaphore, still
 398          * continue the access. We don't need the semaphore anyway. */
 399         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 400                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 401         iagetword(chip, 0);     /* clear semaphore flag */
 402         /* I don't care about the semaphore */
 403         return -EBUSY;
 404 }
 405
 406 static void snd_intel8x0_codec_write(ac97_t *ac97,
 407                                      unsigned short reg,
 408                                      unsigned short val)
 409 {
 410         intel8x0_t *chip = ac97->private_data;
 411
 412         spin_lock(&chip->ac97_lock);
 413         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 414                 if (! chip->in_ac97_init)
 415                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 416         }
 417         iaputword(chip, reg + ac97->num * 0x80, val);
 418         spin_unlock(&chip->ac97_lock);
 419 }
 420
 421 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 422                                               unsigned short reg)
 423 {
 424         intel8x0_t *chip = ac97->private_data;
 425         unsigned short res;
 426         unsigned int tmp;
 427
 428         spin_lock(&chip->ac97_lock);
 429         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 430                 if (! chip->in_ac97_init)
 431                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 432                 res = 0xffff;
 433         } else {
 434                 res = iagetword(chip, reg + ac97->num * 0x80);
 435                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 436                         /* reset RCS and preserve other R/WC bits */
 437                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 438                         if (! chip->in_ac97_init)
 439                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 440                         res = 0xffff;
 441                 }
 442         }
 443         spin_unlock(&chip->ac97_lock);
 444         return res;
 445 }
 446
 447
 448 /*
 449  * DMA I/O
 450  */
 451 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 452 {
 453         int idx;
 454         u32 *bdbar = ichdev->bdbar;
 455         unsigned long port = ichdev->reg_offset;
 456
 457         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 458         if (ichdev->size == ichdev->fragsize) {
 459                 ichdev->ack_reload = ichdev->ack = 2;
 460                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 461                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 462                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 463                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 464                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 465                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 466                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 467                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 468                 }
 469                 ichdev->frags = 2;
 470         } else {
 471                 ichdev->ack_reload = ichdev->ack = 1;
 472                 ichdev->fragsize1 = ichdev->fragsize;
 473                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 474                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 475                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 476                                                      ichdev->fragsize >> chip->pcm_pos_shift);
 477                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 478                 }
 479                 ichdev->frags = ichdev->size / ichdev->fragsize;
 480         }
 481         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 482         ichdev->civ = 0;
 483         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 484         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 485         ichdev->position = 0;
 486 #if 0
 487         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 488                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 489 #endif
 490         /* clear interrupts */
 491         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 492 }
 493
 494 /*
 495  *  Interrupt handler
 496  */
 497
 498 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 499 {
 500         unsigned long port = ichdev->reg_offset;
 501         int civ, i, step;
 502         int ack = 0;
 503
 504         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 505         if (civ == ichdev->civ) {
 506                 // snd_printd("civ same %d\n", civ);
 507                 step = 1;
 508                 ichdev->civ++;
 509                 ichdev->civ &= ICH_REG_LVI_MASK;
 510         } else {
 511                 step = civ - ichdev->civ;
 512                 if (step < 0)
 513                         step += ICH_REG_LVI_MASK + 1;
 514                 // if (step != 1)
 515                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 516                 ichdev->civ = civ;
 517         }
 518
 519         ichdev->position += step * ichdev->fragsize1;
 520         ichdev->position %= ichdev->size;
 521         ichdev->lvi += step;
 522         ichdev->lvi &= ICH_REG_LVI_MASK;
 523         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 524         for (i = 0; i < step; i++) {
 525                 ichdev->lvi_frag++;
 526                 ichdev->lvi_frag %= ichdev->frags;
 527                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 528         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 529                 if (--ichdev->ack == 0) {
 530                         ichdev->ack = ichdev->ack_reload;
 531                         ack = 1;
 532                 }
 533         }
 534         if (ack && ichdev->substream) {
 535                 spin_unlock(&chip->reg_lock);
 536                 snd_pcm_period_elapsed(ichdev->substream);
 537                 spin_lock(&chip->reg_lock);
 538         }
 539         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 540 }
 541
 542 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 543 {
 544         intel8x0_t *chip = dev_id;
 545         ichdev_t *ichdev;
 546         unsigned int status;
 547         unsigned int i;
 548
 549         spin_lock(&chip->reg_lock);
 550         status = igetdword(chip, chip->int_sta_reg);
 551         if (status == 0xffffffff) { /* we are not yet resumed */
 552                 spin_unlock(&chip->reg_lock);
 553                 return IRQ_NONE;
 554         }
 555         if ((status & chip->int_sta_mask) == 0) {
 556                 if (status)
 557                         iputdword(chip, chip->int_sta_reg, status);
 558                 spin_unlock(&chip->reg_lock);
 559                 return IRQ_NONE;
 560         }
 561
 562         for (i = 0; i < chip->bdbars_count; i++) {
 563                 ichdev = &chip->ichd[i];
 564                 if (status & ichdev->int_sta_mask)
 565                         snd_intel8x0_update(chip, ichdev);
 566         }
 567
 568         /* ack them */
 569         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 570         spin_unlock(&chip->reg_lock);
 571
 572         return IRQ_HANDLED;
 573 }
 574
 575 /*
 576  *  PCM part
 577  */
 578
 579 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 580 {
 581         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 582         ichdev_t *ichdev = get_ichdev(substream);
 583         unsigned char val = 0;
 584         unsigned long port = ichdev->reg_offset;
 585
 586         switch (cmd) {
 587         case SNDRV_PCM_TRIGGER_START:
 588         case SNDRV_PCM_TRIGGER_RESUME:
 589                 val = ICH_IOCE | ICH_STARTBM;
 590                 break;
 591         case SNDRV_PCM_TRIGGER_STOP:
 592         case SNDRV_PCM_TRIGGER_SUSPEND:
 593                 val = 0;
 594                 break;
 595         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 596                 val = ICH_IOCE;
 597                 break;
 598         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 599                 val = ICH_IOCE | ICH_STARTBM;
 600                 break;
 601         default:
 602                 return -EINVAL;
 603         }
 604         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 605         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 606                 /* wait until DMA stopped */
 607                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 608                 /* reset whole DMA things */
 609                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 610         }
 611         return 0;
 612 }
 613
 614 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 615                                   snd_pcm_hw_params_t * hw_params)
 616 {
 617         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 618 }
 619
 620 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 621 {
 622         return snd_pcm_lib_free_pages(substream);
 623 }
 624
 625 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
 626 {
 627         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 628         ichdev_t *ichdev = get_ichdev(substream);
 629         size_t ptr1, ptr;
 630
 631         ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
 632         if (ptr1 != 0)
 633                 ptr = ichdev->fragsize1 - ptr1;
 634         else
 635                 ptr = 0;
 636         ptr += ichdev->position;
 637         if (ptr >= ichdev->size)
 638                 return 0;
 639         return bytes_to_frames(substream->runtime, ptr);
 640 }
 641
 642 static int snd_intel8x0m_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 643 {
 644         ichdev_t *ichdev = get_ichdev(substream);
 645         /* hook off/on on start/stop */
 646         /* TODO: move it to ac97 controls */
 647         switch (cmd) {
 648         case SNDRV_PCM_TRIGGER_START:
 649                 snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
 650                                      AC97_GPIO_LINE1_OH, AC97_GPIO_LINE1_OH);
 651                 break;
 652         case SNDRV_PCM_TRIGGER_STOP:
 653                 snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
 654                                      AC97_GPIO_LINE1_OH, ~AC97_GPIO_LINE1_OH);
 655                 break;
 656         default:
 657                 return -EINVAL;
 658         }
 659         return snd_intel8x0_pcm_trigger(substream,cmd);
 660 }
 661
 662 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
 663 {
 664         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 665         snd_pcm_runtime_t *runtime = substream->runtime;
 666         ichdev_t *ichdev = get_ichdev(substream);
 667
 668         ichdev->physbuf = runtime->dma_addr;
 669         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
 670         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
 671         snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
 672         snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
 673         snd_intel8x0_setup_periods(chip, ichdev);
 674         return 0;
 675 }
 676
 677 static snd_pcm_hardware_t snd_intel8x0m_stream =
 678 {
 679         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 680                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 681                                  SNDRV_PCM_INFO_MMAP_VALID |
 682                                  SNDRV_PCM_INFO_PAUSE |
 683                                  SNDRV_PCM_INFO_RESUME),
 684         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 685         .rates =                SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
 686         .rate_min =             8000,
 687         .rate_max =             16000,
 688         .channels_min =         1,
 689         .channels_max =         1,
 690         .buffer_bytes_max =     64 * 1024,
 691         .period_bytes_min =     32,
 692         .period_bytes_max =     64 * 1024,
 693         .periods_min =          1,
 694         .periods_max =          1024,
 695         .fifo_size =            0,
 696 };
 697
 698
 699 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
 700 {
 701         static unsigned int rates[] = { 8000,  9600, 12000, 16000 };
 702         static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
 703                 .count = ARRAY_SIZE(rates),
 704                 .list = rates,
 705                 .mask = 0,
 706         };
 707         snd_pcm_runtime_t *runtime = substream->runtime;
 708         int err;
 709
 710         ichdev->substream = substream;
 711         runtime->hw = snd_intel8x0m_stream;
 712         err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
 713         if ( err < 0 )
 714                 return err;
 715         runtime->private_data = ichdev;
 716         return 0;
 717 }
 718
 719 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
 720 {
 721         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 722
 723         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
 724 }
 725
 726 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
 727 {
 728         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 729
 730         chip->ichd[ICHD_MDMOUT].substream = NULL;
 731         return 0;
 732 }
 733
 734 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
 735 {
 736         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 737
 738         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
 739 }
 740
 741 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
 742 {
 743         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 744
 745         chip->ichd[ICHD_MDMIN].substream = NULL;
 746         return 0;
 747 }
 748
 749
 750 static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
 751         .open =         snd_intel8x0m_playback_open,
 752         .close =        snd_intel8x0m_playback_close,
 753         .ioctl =        snd_pcm_lib_ioctl,
 754         .hw_params =    snd_intel8x0_hw_params,
 755         .hw_free =      snd_intel8x0_hw_free,
 756         .prepare =      snd_intel8x0m_pcm_prepare,
 757         .trigger =      snd_intel8x0m_pcm_trigger,
 758         .pointer =      snd_intel8x0_pcm_pointer,
 759 };
 760
 761 static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
 762         .open =         snd_intel8x0m_capture_open,
 763         .close =        snd_intel8x0m_capture_close,
 764         .ioctl =        snd_pcm_lib_ioctl,
 765         .hw_params =    snd_intel8x0_hw_params,
 766         .hw_free =      snd_intel8x0_hw_free,
 767         .prepare =      snd_intel8x0m_pcm_prepare,
 768         .trigger =      snd_intel8x0m_pcm_trigger,
 769         .pointer =      snd_intel8x0_pcm_pointer,
 770 };
 771
 772
 773 struct ich_pcm_table {
 774         char *suffix;
 775         snd_pcm_ops_t *playback_ops;
 776         snd_pcm_ops_t *capture_ops;
 777         size_t prealloc_size;
 778         size_t prealloc_max_size;
 779         int ac97_idx;
 780 };
 781
 782 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
 783 {
 784         snd_pcm_t *pcm;
 785         int err;
 786         char name[32];
 787
 788         if (rec->suffix)
 789                 sprintf(name, "Intel ICH - %s", rec->suffix);
 790         else
 791                 strcpy(name, "Intel ICH");
 792         err = snd_pcm_new(chip->card, name, device,
 793                           rec->playback_ops ? 1 : 0,
 794                           rec->capture_ops ? 1 : 0, &pcm);
 795         if (err < 0)
 796                 return err;
 797
 798         if (rec->playback_ops)
 799                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
 800         if (rec->capture_ops)
 801                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
 802
 803         pcm->private_data = chip;
 804         pcm->info_flags = 0;
 805         if (rec->suffix)
 806                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
 807         else
 808                 strcpy(pcm->name, chip->card->shortname);
 809         chip->pcm[device] = pcm;
 810
 811         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 812                                               snd_dma_pci_data(chip->pci),
 813                                               rec->prealloc_size,
 814                                               rec->prealloc_max_size);
 815
 816         return 0;
 817 }
 818
 819 static struct ich_pcm_table intel_pcms[] __devinitdata = {
 820         {
 821                 .suffix = "Modem",
 822                 .playback_ops = &snd_intel8x0m_playback_ops,
 823                 .capture_ops = &snd_intel8x0m_capture_ops,
 824                 .prealloc_size = 32 * 1024,
 825                 .prealloc_max_size = 64 * 1024,
 826         },
 827 };
 828
 829 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
 830 {
 831         int i, tblsize, device, err;
 832         struct ich_pcm_table *tbl, *rec;
 833
 834 #if 1
 835         tbl = intel_pcms;
 836         tblsize = 1;
 837 #else
 838         switch (chip->device_type) {
 839         case DEVICE_NFORCE:
 840                 tbl = nforce_pcms;
 841                 tblsize = ARRAY_SIZE(nforce_pcms);
 842                 break;
 843         case DEVICE_ALI:
 844                 tbl = ali_pcms;
 845                 tblsize = ARRAY_SIZE(ali_pcms);
 846                 break;
 847         default:
 848                 tbl = intel_pcms;
 849                 tblsize = 2;
 850                 break;
 851         }
 852 #endif
 853         device = 0;
 854         for (i = 0; i < tblsize; i++) {
 855                 rec = tbl + i;
 856                 if (i > 0 && rec->ac97_idx) {
 857                         /* activate PCM only when associated AC'97 codec */
 858                         if (! chip->ichd[rec->ac97_idx].ac97)
 859                                 continue;
 860                 }
 861                 err = snd_intel8x0_pcm1(chip, device, rec);
 862                 if (err < 0)
 863                         return err;
 864                 device++;
 865         }
 866
 867         chip->pcm_devs = device;
 868         return 0;
 869 }
 870
 871
 872 /*
 873  *  Mixer part
 874  */
 875
 876 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
 877 {
 878         intel8x0_t *chip = bus->private_data;
 879         chip->ac97_bus = NULL;
 880 }
 881
 882 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
 883 {
 884         intel8x0_t *chip = ac97->private_data;
 885         chip->ac97 = NULL;
 886 }
 887
 888
 889 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
 890 {
 891         ac97_bus_t *pbus;
 892         ac97_template_t ac97;
 893         ac97_t *x97;
 894         int err;
 895         unsigned int glob_sta = 0;
 896         static ac97_bus_ops_t ops = {
 897                 .write = snd_intel8x0_codec_write,
 898                 .read = snd_intel8x0_codec_read,
 899         };
 900
 901         chip->in_ac97_init = 1;
 902
 903         memset(&ac97, 0, sizeof(ac97));
 904         ac97.private_data = chip;
 905         ac97.private_free = snd_intel8x0_mixer_free_ac97;
 906         ac97.scaps = AC97_SCAP_SKIP_AUDIO;
 907
 908         glob_sta = igetdword(chip, ICHREG(GLOB_STA));
 909
 910         if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
 911                 goto __err;
 912         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
 913         pbus->shared_type = AC97_SHARED_TYPE_ICH;       /* shared with audio driver */
 914         if (ac97_clock >= 8000 && ac97_clock <= 48000)
 915                 pbus->clock = ac97_clock;
 916         chip->ac97_bus = pbus;
 917
 918         ac97.pci = chip->pci;
 919         ac97.num = glob_sta & ICH_SCR ? 1 : 0;
 920         if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
 921                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
 922                 if (ac97.num == 0)
 923                         goto __err;
 924                 return err;
 925         }
 926         chip->ac97 = x97;
 927         if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97 ) {
 928                 chip->ichd[ICHD_MDMIN].ac97 = x97;
 929                 chip->ichd[ICHD_MDMOUT].ac97 = x97;
 930         }
 931
 932         chip->in_ac97_init = 0;
 933         return 0;
 934
 935  __err:
 936         /* clear the cold-reset bit for the next chance */
 937         if (chip->device_type != DEVICE_ALI)
 938                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
 939         return err;
 940 }
 941
 942
 943 /*
 944  *
 945  */
 946
 947 #define do_delay(chip) do {\
 948         set_current_state(TASK_UNINTERRUPTIBLE);\
 949         schedule_timeout(1);\
 950 } while (0)
 951
 952 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
 953 {
 954         unsigned long end_time;
 955         unsigned int cnt, status, nstatus;
 956
 957         /* put logic to right state */
 958         /* first clear status bits */
 959         status = ICH_RCS | ICH_MIINT | ICH_MOINT;
 960         cnt = igetdword(chip, ICHREG(GLOB_STA));
 961         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
 962
 963         /* ACLink on, 2 channels */
 964         cnt = igetdword(chip, ICHREG(GLOB_CNT));
 965         cnt &= ~(ICH_ACLINK);
 966         /* finish cold or do warm reset */
 967         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
 968         iputdword(chip, ICHREG(GLOB_CNT), cnt);
 969         end_time = (jiffies + (HZ / 4)) + 1;
 970         do {
 971                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
 972                         goto __ok;
 973                 do_delay(chip);
 974         } while (time_after_eq(end_time, jiffies));
 975         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
 976         return -EIO;
 977
 978       __ok:
 979         if (probing) {
 980                 /* wait for any codec ready status.
 981                  * Once it becomes ready it should remain ready
 982                  * as long as we do not disable the ac97 link.
 983                  */
 984                 end_time = jiffies + HZ;
 985                 do {
 986                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
 987                         if (status)
 988                                 break;
 989                         do_delay(chip);
 990                 } while (time_after_eq(end_time, jiffies));
 991                 if (! status) {
 992                         /* no codec is found */
 993                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
 994                         return -EIO;
 995                 }
 996
 997                 /* up to two codecs (modem cannot be tertiary with ICH4) */
 998                 nstatus = ICH_PCR | ICH_SCR;
 999
1000                 /* wait for other codecs ready status. */
1001                 end_time = jiffies + HZ / 4;
1002                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
1003                         do_delay(chip);
1004                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1005                 }
1006
1007         } else {
1008                 /* resume phase */
1009                 status = 0;
1010                 if (chip->ac97)
1011                         status |= get_ich_codec_bit(chip, chip->ac97->num);
1012                 /* wait until all the probed codecs are ready */
1013                 end_time = jiffies + HZ;
1014                 do {
1015                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1016                         if (status == nstatus)
1017                                 break;
1018                         do_delay(chip);
1019                 } while (time_after_eq(end_time, jiffies));
1020         }
1021
1022         if (chip->device_type == DEVICE_SIS) {
1023                 /* unmute the output on SIS7012 */
1024                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
1031 {
1032         unsigned int i;
1033         int err;
1034
1035         if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
1036                 return err;
1037         iagetword(chip, 0);     /* clear semaphore flag */
1038
1039         /* disable interrupts */
1040         for (i = 0; i < chip->bdbars_count; i++)
1041                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1042         /* reset channels */
1043         for (i = 0; i < chip->bdbars_count; i++)
1044                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1045         /* initialize Buffer Descriptor Lists */
1046         for (i = 0; i < chip->bdbars_count; i++)
1047                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
1048         return 0;
1049 }
1050
1051 static int snd_intel8x0_free(intel8x0_t *chip)
1052 {
1053         unsigned int i;
1054
1055         if (chip->irq < 0)
1056                 goto __hw_end;
1057         /* disable interrupts */
1058         for (i = 0; i < chip->bdbars_count; i++)
1059                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1060         /* reset channels */
1061         for (i = 0; i < chip->bdbars_count; i++)
1062                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1063         /* --- */
1064         synchronize_irq(chip->irq);
1065       __hw_end:
1066         if (chip->bdbars.area)
1067                 snd_dma_free_pages(&chip->bdbars);
1068         if (chip->remap_addr)
1069                 iounmap((void *) chip->remap_addr);
1070         if (chip->remap_bmaddr)
1071                 iounmap((void *) chip->remap_bmaddr);
1072         if (chip->irq >= 0)
1073                 free_irq(chip->irq, (void *)chip);
1074         pci_release_regions(chip->pci);
1075         kfree(chip);
1076         return 0;
1077 }
1078
1079 #ifdef CONFIG_PM
1080 /*
1081  * power management
1082  */
1083 static int intel8x0m_suspend(snd_card_t *card, unsigned int state)
1084 {
1085         intel8x0_t *chip = card->pm_private_data;
1086         int i;
1087
1088         for (i = 0; i < chip->pcm_devs; i++)
1089                 snd_pcm_suspend_all(chip->pcm[i]);
1090         if (chip->ac97)
1091                 snd_ac97_suspend(chip->ac97);
1092         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1093         return 0;
1094 }
1095
1096 static int intel8x0m_resume(snd_card_t *card, unsigned int state)
1097 {
1098         intel8x0_t *chip = card->pm_private_data;
1099         pci_enable_device(chip->pci);
1100         pci_set_master(chip->pci);
1101         snd_intel8x0_chip_init(chip, 0);
1102         if (chip->ac97)
1103                 snd_ac97_resume(chip->ac97);
1104
1105         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1106         return 0;
1107 }
1108 #endif /* CONFIG_PM */
1109
1110 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1111                                    snd_info_buffer_t * buffer)
1112 {
1113         intel8x0_t *chip = entry->private_data;
1114         unsigned int tmp;
1115
1116         snd_iprintf(buffer, "Intel8x0m\n\n");
1117         if (chip->device_type == DEVICE_ALI)
1118                 return;
1119         tmp = igetdword(chip, ICHREG(GLOB_STA));
1120         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1121         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
1122         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
1123                         tmp & ICH_PCR ? " primary" : "",
1124                         tmp & ICH_SCR ? " secondary" : "",
1125                         tmp & ICH_TCR ? " tertiary" : "",
1126                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1127 }
1128
1129 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1130 {
1131         snd_info_entry_t *entry;
1132
1133         if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1134                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
1135 }
1136
1137 static int snd_intel8x0_dev_free(snd_device_t *device)
1138 {
1139         intel8x0_t *chip = device->device_data;
1140         return snd_intel8x0_free(chip);
1141 }
1142
1143 struct ich_reg_info {
1144         unsigned int int_sta_mask;
1145         unsigned int offset;
1146 };
1147
1148 static int __devinit snd_intel8x0m_create(snd_card_t * card,
1149                                          struct pci_dev *pci,
1150                                          unsigned long device_type,
1151                                          intel8x0_t ** r_intel8x0)
1152 {
1153         intel8x0_t *chip;
1154         int err;
1155         unsigned int i;
1156         unsigned int int_sta_masks;
1157         ichdev_t *ichdev;
1158         static snd_device_ops_t ops = {
1159                 .dev_free =     snd_intel8x0_dev_free,
1160         };
1161         static struct ich_reg_info intel_regs[2] = {
1162                 { ICH_MIINT, 0 },
1163                 { ICH_MOINT, 0x10 },
1164         };
1165         struct ich_reg_info *tbl;
1166
1167         *r_intel8x0 = NULL;
1168
1169         if ((err = pci_enable_device(pci)) < 0)
1170                 return err;
1171
1172         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1173         if (chip == NULL)
1174                 return -ENOMEM;
1175         spin_lock_init(&chip->reg_lock);
1176         spin_lock_init(&chip->ac97_lock);
1177         chip->device_type = device_type;
1178         chip->card = card;
1179         chip->pci = pci;
1180         chip->irq = -1;
1181
1182         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1183                 kfree(chip);
1184                 return err;
1185         }
1186
1187         if (device_type == DEVICE_ALI) {
1188                 /* ALI5455 has no ac97 region */
1189                 chip->bmaddr = pci_resource_start(pci, 0);
1190                 goto port_inited;
1191         }
1192
1193         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
1194                 chip->mmio = 1;
1195                 chip->addr = pci_resource_start(pci, 2);
1196                 chip->remap_addr = (unsigned long) ioremap_nocache(chip->addr,
1197                                                                    pci_resource_len(pci, 2));
1198                 if (chip->remap_addr == 0) {
1199                         snd_printk("AC'97 space ioremap problem\n");
1200                         snd_intel8x0_free(chip);
1201                         return -EIO;
1202                 }
1203         } else {
1204                 chip->addr = pci_resource_start(pci, 0);
1205         }
1206         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
1207                 chip->bm_mmio = 1;
1208                 chip->bmaddr = pci_resource_start(pci, 3);
1209                 chip->remap_bmaddr = (unsigned long) ioremap_nocache(chip->bmaddr,
1210                                                                      pci_resource_len(pci, 3));
1211                 if (chip->remap_bmaddr == 0) {
1212                         snd_printk("Controller space ioremap problem\n");
1213                         snd_intel8x0_free(chip);
1214                         return -EIO;
1215                 }
1216         } else {
1217                 chip->bmaddr = pci_resource_start(pci, 1);
1218         }
1219
1220  port_inited:
1221         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1222                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1223                 snd_intel8x0_free(chip);
1224                 return -EBUSY;
1225         }
1226         chip->irq = pci->irq;
1227         pci_set_master(pci);
1228         synchronize_irq(chip->irq);
1229
1230         /* initialize offsets */
1231         chip->bdbars_count = 2;
1232         tbl = intel_regs;
1233
1234         for (i = 0; i < chip->bdbars_count; i++) {
1235                 ichdev = &chip->ichd[i];
1236                 ichdev->ichd = i;
1237                 ichdev->reg_offset = tbl[i].offset;
1238                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1239                 if (device_type == DEVICE_SIS) {
1240                         /* SiS 7013 swaps the registers */
1241                         ichdev->roff_sr = ICH_REG_OFF_PICB;
1242                         ichdev->roff_picb = ICH_REG_OFF_SR;
1243                 } else {
1244                         ichdev->roff_sr = ICH_REG_OFF_SR;
1245                         ichdev->roff_picb = ICH_REG_OFF_PICB;
1246                 }
1247                 if (device_type == DEVICE_ALI)
1248                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1249         }
1250         /* SIS7013 handles the pcm data in bytes, others are in words */
1251         chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1252
1253         /* allocate buffer descriptor lists */
1254         /* the start of each lists must be aligned to 8 bytes */
1255         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1256                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1257                                 &chip->bdbars) < 0) {
1258                 snd_intel8x0_free(chip);
1259                 return -ENOMEM;
1260         }
1261         /* tables must be aligned to 8 bytes here, but the kernel pages
1262            are much bigger, so we don't care (on i386) */
1263         int_sta_masks = 0;
1264         for (i = 0; i < chip->bdbars_count; i++) {
1265                 ichdev = &chip->ichd[i];
1266                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1267                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1268                 int_sta_masks |= ichdev->int_sta_mask;
1269         }
1270         chip->int_sta_reg = ICH_REG_GLOB_STA;
1271         chip->int_sta_mask = int_sta_masks;
1272
1273         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1274                 snd_intel8x0_free(chip);
1275                 return err;
1276         }
1277
1278         snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
1279
1280         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1281                 snd_intel8x0_free(chip);
1282                 return err;
1283         }
1284
1285         snd_card_set_dev(card, &pci->dev);
1286
1287         *r_intel8x0 = chip;
1288         return 0;
1289 }
1290
1291 static struct shortname_table {
1292         unsigned int id;
1293         const char *s;
1294 } shortnames[] __devinitdata = {
1295         { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" },
1296         { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" },
1297         { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1298         { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1299         { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" },
1300         { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" },
1301         { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" },
1302         { 0x7446, "AMD AMD768" },
1303         { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1304         { PCI_DEVICE_ID_NVIDIA_MCP_MODEM, "NVidia nForce" },
1305         { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1306         { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1307         { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1308 #if 0
1309         { 0x5455, "ALi M5455" },
1310         { 0x746d, "AMD AMD8111" },
1311 #endif
1312         { 0 },
1313 };
1314
1315 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1316                                         const struct pci_device_id *pci_id)
1317 {
1318         static int dev;
1319         snd_card_t *card;
1320         intel8x0_t *chip;
1321         int err;
1322         struct shortname_table *name;
1323
1324         if (dev >= SNDRV_CARDS)
1325                 return -ENODEV;
1326         if (!enable[dev]) {
1327                 dev++;
1328                 return -ENOENT;
1329         }
1330
1331         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1332         if (card == NULL)
1333                 return -ENOMEM;
1334
1335         switch (pci_id->driver_data) {
1336         case DEVICE_NFORCE:
1337                 strcpy(card->driver, "NFORCE-MODEM");
1338                 break;
1339         default:
1340                 strcpy(card->driver, "ICH-MODEM");
1341                 break;
1342         }
1343
1344         strcpy(card->shortname, "Intel ICH");
1345         for (name = shortnames; name->id; name++) {
1346                 if (pci->device == name->id) {
1347                         strcpy(card->shortname, name->s);
1348                         break;
1349                 }
1350         }
1351         strcat(card->shortname," Modem");
1352
1353         if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1354                 snd_card_free(card);
1355                 return err;
1356         }
1357
1358         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
1359                 snd_card_free(card);
1360                 return err;
1361         }
1362         if ((err = snd_intel8x0_pcm(chip)) < 0) {
1363                 snd_card_free(card);
1364                 return err;
1365         }
1366
1367         snd_intel8x0m_proc_init(chip);
1368
1369         sprintf(card->longname, "%s at 0x%lx, irq %i",
1370                 card->shortname, chip->addr, chip->irq);
1371
1372         if ((err = snd_card_register(card)) < 0) {
1373                 snd_card_free(card);
1374                 return err;
1375         }
1376         pci_set_drvdata(pci, card);
1377         dev++;
1378         return 0;
1379 }
1380
1381 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1382 {
1383         snd_card_free(pci_get_drvdata(pci));
1384         pci_set_drvdata(pci, NULL);
1385 }
1386
1387 static struct pci_driver driver = {
1388         .name = "Intel ICH Modem",
1389         .id_table = snd_intel8x0m_ids,
1390         .probe = snd_intel8x0m_probe,
1391         .remove = __devexit_p(snd_intel8x0m_remove),
1392         SND_PCI_PM_CALLBACKS
1393 };
1394
1395
1396 static int __init alsa_card_intel8x0m_init(void)
1397 {
1398         return pci_module_init(&driver);
1399 }
1400
1401 static void __exit alsa_card_intel8x0m_exit(void)
1402 {
1403         pci_unregister_driver(&driver);
1404 }
1405
1406 module_init(alsa_card_intel8x0m_init)
1407 module_exit(alsa_card_intel8x0m_exit)