sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <sound/core.h>
  43 #include <sound/info.h>
  44 #include <sound/control.h>
  45 #include <sound/pcm.h>
  46 #include <sound/mpu401.h>
  47 #include <sound/ac97_codec.h>
  48 #define SNDRV_GET_ID
  49 #include <sound/initval.h>
  50
  51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  53 MODULE_LICENSE("GPL");
  54 MODULE_CLASSES("{sound}");
  55 MODULE_DEVICES("{{ESS,Maestro3 PCI},"
  56                 "{ESS,ES1988},"
  57                 "{ESS,Allegro PCI},"
  58                 "{ESS,Allegro-1 PCI},"
  59                 "{ESS,Canyon3D-2/LE PCI}}");
  60
  61 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  62 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  63 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  64 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  65 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  66
  67 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  68 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  69 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  70 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
  71 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  72 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  73 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  74 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  75 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  76 MODULE_PARM(external_amp, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  77 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  78 MODULE_PARM_SYNTAX(external_amp, SNDRV_ENABLED "," SNDRV_BOOLEAN_TRUE_DESC);
  79 MODULE_PARM(amp_gpio, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  80 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  81 MODULE_PARM_SYNTAX(amp_gpio, SNDRV_ENABLED);
  82
  83 #define MAX_PLAYBACKS   2
  84 #define MAX_CAPTURES    1
  85 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  86
  87
  88 /*
  89  * maestro3 registers
  90  */
  91
  92 /* Allegro PCI configuration registers */
  93 #define PCI_LEGACY_AUDIO_CTRL   0x40
  94 #define SOUND_BLASTER_ENABLE    0x00000001
  95 #define FM_SYNTHESIS_ENABLE     0x00000002
  96 #define GAME_PORT_ENABLE        0x00000004
  97 #define MPU401_IO_ENABLE        0x00000008
  98 #define MPU401_IRQ_ENABLE       0x00000010
  99 #define ALIAS_10BIT_IO          0x00000020
 100 #define SB_DMA_MASK             0x000000C0
 101 #define SB_DMA_0                0x00000040
 102 #define SB_DMA_1                0x00000040
 103 #define SB_DMA_R                0x00000080
 104 #define SB_DMA_3                0x000000C0
 105 #define SB_IRQ_MASK             0x00000700
 106 #define SB_IRQ_5                0x00000000
 107 #define SB_IRQ_7                0x00000100
 108 #define SB_IRQ_9                0x00000200
 109 #define SB_IRQ_10               0x00000300
 110 #define MIDI_IRQ_MASK           0x00003800
 111 #define SERIAL_IRQ_ENABLE       0x00004000
 112 #define DISABLE_LEGACY          0x00008000
 113
 114 #define PCI_ALLEGRO_CONFIG      0x50
 115 #define SB_ADDR_240             0x00000004
 116 #define MPU_ADDR_MASK           0x00000018
 117 #define MPU_ADDR_330            0x00000000
 118 #define MPU_ADDR_300            0x00000008
 119 #define MPU_ADDR_320            0x00000010
 120 #define MPU_ADDR_340            0x00000018
 121 #define USE_PCI_TIMING          0x00000040
 122 #define POSTED_WRITE_ENABLE     0x00000080
 123 #define DMA_POLICY_MASK         0x00000700
 124 #define DMA_DDMA                0x00000000
 125 #define DMA_TDMA                0x00000100
 126 #define DMA_PCPCI               0x00000200
 127 #define DMA_WBDMA16             0x00000400
 128 #define DMA_WBDMA4              0x00000500
 129 #define DMA_WBDMA2              0x00000600
 130 #define DMA_WBDMA1              0x00000700
 131 #define DMA_SAFE_GUARD          0x00000800
 132 #define HI_PERF_GP_ENABLE       0x00001000
 133 #define PIC_SNOOP_MODE_0        0x00002000
 134 #define PIC_SNOOP_MODE_1        0x00004000
 135 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 136 #define RING_IN_ENABLE          0x00010000
 137 #define SPDIF_TEST_MODE         0x00020000
 138 #define CLK_MULT_MODE_SELECT_2  0x00040000
 139 #define EEPROM_WRITE_ENABLE     0x00080000
 140 #define CODEC_DIR_IN            0x00100000
 141 #define HV_BUTTON_FROM_GD       0x00200000
 142 #define REDUCED_DEBOUNCE        0x00400000
 143 #define HV_CTRL_ENABLE          0x00800000
 144 #define SPDIF_ENABLE            0x01000000
 145 #define CLK_DIV_SELECT          0x06000000
 146 #define CLK_DIV_BY_48           0x00000000
 147 #define CLK_DIV_BY_49           0x02000000
 148 #define CLK_DIV_BY_50           0x04000000
 149 #define CLK_DIV_RESERVED        0x06000000
 150 #define PM_CTRL_ENABLE          0x08000000
 151 #define CLK_MULT_MODE_SELECT    0x30000000
 152 #define CLK_MULT_MODE_SHIFT     28
 153 #define CLK_MULT_MODE_0         0x00000000
 154 #define CLK_MULT_MODE_1         0x10000000
 155 #define CLK_MULT_MODE_2         0x20000000
 156 #define CLK_MULT_MODE_3         0x30000000
 157 #define INT_CLK_SELECT          0x40000000
 158 #define INT_CLK_MULT_RESET      0x80000000
 159
 160 /* M3 */
 161 #define INT_CLK_SRC_NOT_PCI     0x00100000
 162 #define INT_CLK_MULT_ENABLE     0x80000000
 163
 164 #define PCI_ACPI_CONTROL        0x54
 165 #define PCI_ACPI_D0             0x00000000
 166 #define PCI_ACPI_D1             0xB4F70000
 167 #define PCI_ACPI_D2             0xB4F7B4F7
 168
 169 #define PCI_USER_CONFIG         0x58
 170 #define EXT_PCI_MASTER_ENABLE   0x00000001
 171 #define SPDIF_OUT_SELECT        0x00000002
 172 #define TEST_PIN_DIR_CTRL       0x00000004
 173 #define AC97_CODEC_TEST         0x00000020
 174 #define TRI_STATE_BUFFER        0x00000080
 175 #define IN_CLK_12MHZ_SELECT     0x00000100
 176 #define MULTI_FUNC_DISABLE      0x00000200
 177 #define EXT_MASTER_PAIR_SEL     0x00000400
 178 #define PCI_MASTER_SUPPORT      0x00000800
 179 #define STOP_CLOCK_ENABLE       0x00001000
 180 #define EAPD_DRIVE_ENABLE       0x00002000
 181 #define REQ_TRI_STATE_ENABLE    0x00004000
 182 #define REQ_LOW_ENABLE          0x00008000
 183 #define MIDI_1_ENABLE           0x00010000
 184 #define MIDI_2_ENABLE           0x00020000
 185 #define SB_AUDIO_SYNC           0x00040000
 186 #define HV_CTRL_TEST            0x00100000
 187 #define SOUNDBLASTER_TEST       0x00400000
 188
 189 #define PCI_USER_CONFIG_C       0x5C
 190
 191 #define PCI_DDMA_CTRL           0x60
 192 #define DDMA_ENABLE             0x00000001
 193
 194
 195 /* Allegro registers */
 196 #define HOST_INT_CTRL           0x18
 197 #define SB_INT_ENABLE           0x0001
 198 #define MPU401_INT_ENABLE       0x0002
 199 #define ASSP_INT_ENABLE         0x0010
 200 #define RING_INT_ENABLE         0x0020
 201 #define HV_INT_ENABLE           0x0040
 202 #define CLKRUN_GEN_ENABLE       0x0100
 203 #define HV_CTRL_TO_PME          0x0400
 204 #define SOFTWARE_RESET_ENABLE   0x8000
 205
 206 /*
 207  * should be using the above defines, probably.
 208  */
 209 #define REGB_ENABLE_RESET               0x01
 210 #define REGB_STOP_CLOCK                 0x10
 211
 212 #define HOST_INT_STATUS         0x1A
 213 #define SB_INT_PENDING          0x01
 214 #define MPU401_INT_PENDING      0x02
 215 #define ASSP_INT_PENDING        0x10
 216 #define RING_INT_PENDING        0x20
 217 #define HV_INT_PENDING          0x40
 218
 219 #define HARDWARE_VOL_CTRL       0x1B
 220 #define SHADOW_MIX_REG_VOICE    0x1C
 221 #define HW_VOL_COUNTER_VOICE    0x1D
 222 #define SHADOW_MIX_REG_MASTER   0x1E
 223 #define HW_VOL_COUNTER_MASTER   0x1F
 224
 225 #define CODEC_COMMAND           0x30
 226 #define CODEC_READ_B            0x80
 227
 228 #define CODEC_STATUS            0x30
 229 #define CODEC_BUSY_B            0x01
 230
 231 #define CODEC_DATA              0x32
 232
 233 #define RING_BUS_CTRL_A         0x36
 234 #define RAC_PME_ENABLE          0x0100
 235 #define RAC_SDFS_ENABLE         0x0200
 236 #define LAC_PME_ENABLE          0x0400
 237 #define LAC_SDFS_ENABLE         0x0800
 238 #define SERIAL_AC_LINK_ENABLE   0x1000
 239 #define IO_SRAM_ENABLE          0x2000
 240 #define IIS_INPUT_ENABLE        0x8000
 241
 242 #define RING_BUS_CTRL_B         0x38
 243 #define SECOND_CODEC_ID_MASK    0x0003
 244 #define SPDIF_FUNC_ENABLE       0x0010
 245 #define SECOND_AC_ENABLE        0x0020
 246 #define SB_MODULE_INTF_ENABLE   0x0040
 247 #define SSPE_ENABLE             0x0040
 248 #define M3I_DOCK_ENABLE         0x0080
 249
 250 #define SDO_OUT_DEST_CTRL       0x3A
 251 #define COMMAND_ADDR_OUT        0x0003
 252 #define PCM_LR_OUT_LOCAL        0x0000
 253 #define PCM_LR_OUT_REMOTE       0x0004
 254 #define PCM_LR_OUT_MUTE         0x0008
 255 #define PCM_LR_OUT_BOTH         0x000C
 256 #define LINE1_DAC_OUT_LOCAL     0x0000
 257 #define LINE1_DAC_OUT_REMOTE    0x0010
 258 #define LINE1_DAC_OUT_MUTE      0x0020
 259 #define LINE1_DAC_OUT_BOTH      0x0030
 260 #define PCM_CLS_OUT_LOCAL       0x0000
 261 #define PCM_CLS_OUT_REMOTE      0x0040
 262 #define PCM_CLS_OUT_MUTE        0x0080
 263 #define PCM_CLS_OUT_BOTH        0x00C0
 264 #define PCM_RLF_OUT_LOCAL       0x0000
 265 #define PCM_RLF_OUT_REMOTE      0x0100
 266 #define PCM_RLF_OUT_MUTE        0x0200
 267 #define PCM_RLF_OUT_BOTH        0x0300
 268 #define LINE2_DAC_OUT_LOCAL     0x0000
 269 #define LINE2_DAC_OUT_REMOTE    0x0400
 270 #define LINE2_DAC_OUT_MUTE      0x0800
 271 #define LINE2_DAC_OUT_BOTH      0x0C00
 272 #define HANDSET_OUT_LOCAL       0x0000
 273 #define HANDSET_OUT_REMOTE      0x1000
 274 #define HANDSET_OUT_MUTE        0x2000
 275 #define HANDSET_OUT_BOTH        0x3000
 276 #define IO_CTRL_OUT_LOCAL       0x0000
 277 #define IO_CTRL_OUT_REMOTE      0x4000
 278 #define IO_CTRL_OUT_MUTE        0x8000
 279 #define IO_CTRL_OUT_BOTH        0xC000
 280
 281 #define SDO_IN_DEST_CTRL        0x3C
 282 #define STATUS_ADDR_IN          0x0003
 283 #define PCM_LR_IN_LOCAL         0x0000
 284 #define PCM_LR_IN_REMOTE        0x0004
 285 #define PCM_LR_RESERVED         0x0008
 286 #define PCM_LR_IN_BOTH          0x000C
 287 #define LINE1_ADC_IN_LOCAL      0x0000
 288 #define LINE1_ADC_IN_REMOTE     0x0010
 289 #define LINE1_ADC_IN_MUTE       0x0020
 290 #define MIC_ADC_IN_LOCAL        0x0000
 291 #define MIC_ADC_IN_REMOTE       0x0040
 292 #define MIC_ADC_IN_MUTE         0x0080
 293 #define LINE2_DAC_IN_LOCAL      0x0000
 294 #define LINE2_DAC_IN_REMOTE     0x0400
 295 #define LINE2_DAC_IN_MUTE       0x0800
 296 #define HANDSET_IN_LOCAL        0x0000
 297 #define HANDSET_IN_REMOTE       0x1000
 298 #define HANDSET_IN_MUTE         0x2000
 299 #define IO_STATUS_IN_LOCAL      0x0000
 300 #define IO_STATUS_IN_REMOTE     0x4000
 301
 302 #define SPDIF_IN_CTRL           0x3E
 303 #define SPDIF_IN_ENABLE         0x0001
 304
 305 #define GPIO_DATA               0x60
 306 #define GPIO_DATA_MASK          0x0FFF
 307 #define GPIO_HV_STATUS          0x3000
 308 #define GPIO_PME_STATUS         0x4000
 309
 310 #define GPIO_MASK               0x64
 311 #define GPIO_DIRECTION          0x68
 312 #define GPO_PRIMARY_AC97        0x0001
 313 #define GPI_LINEOUT_SENSE       0x0004
 314 #define GPO_SECONDARY_AC97      0x0008
 315 #define GPI_VOL_DOWN            0x0010
 316 #define GPI_VOL_UP              0x0020
 317 #define GPI_IIS_CLK             0x0040
 318 #define GPI_IIS_LRCLK           0x0080
 319 #define GPI_IIS_DATA            0x0100
 320 #define GPI_DOCKING_STATUS      0x0100
 321 #define GPI_HEADPHONE_SENSE     0x0200
 322 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 323
 324 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 325 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 326
 327 /* M3 */
 328 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 329
 330 #define ASSP_INDEX_PORT         0x80
 331 #define ASSP_MEMORY_PORT        0x82
 332 #define ASSP_DATA_PORT          0x84
 333
 334 #define MPU401_DATA_PORT        0x98
 335 #define MPU401_STATUS_PORT      0x99
 336
 337 #define CLK_MULT_DATA_PORT      0x9C
 338
 339 #define ASSP_CONTROL_A          0xA2
 340 #define ASSP_0_WS_ENABLE        0x01
 341 #define ASSP_CTRL_A_RESERVED1   0x02
 342 #define ASSP_CTRL_A_RESERVED2   0x04
 343 #define ASSP_CLK_49MHZ_SELECT   0x08
 344 #define FAST_PLU_ENABLE         0x10
 345 #define ASSP_CTRL_A_RESERVED3   0x20
 346 #define DSP_CLK_36MHZ_SELECT    0x40
 347
 348 #define ASSP_CONTROL_B          0xA4
 349 #define RESET_ASSP              0x00
 350 #define RUN_ASSP                0x01
 351 #define ENABLE_ASSP_CLOCK       0x00
 352 #define STOP_ASSP_CLOCK         0x10
 353 #define RESET_TOGGLE            0x40
 354
 355 #define ASSP_CONTROL_C          0xA6
 356 #define ASSP_HOST_INT_ENABLE    0x01
 357 #define FM_ADDR_REMAP_DISABLE   0x02
 358 #define HOST_WRITE_PORT_ENABLE  0x08
 359
 360 #define ASSP_HOST_INT_STATUS    0xAC
 361 #define DSP2HOST_REQ_PIORECORD  0x01
 362 #define DSP2HOST_REQ_I2SRATE    0x02
 363 #define DSP2HOST_REQ_TIMER      0x04
 364
 365 /* AC97 registers */
 366 /* XXX fix this crap up */
 367 /*#define AC97_RESET              0x00*/
 368
 369 #define AC97_VOL_MUTE_B         0x8000
 370 #define AC97_VOL_M              0x1F
 371 #define AC97_LEFT_VOL_S         8
 372
 373 #define AC97_MASTER_VOL         0x02
 374 #define AC97_LINE_LEVEL_VOL     0x04
 375 #define AC97_MASTER_MONO_VOL    0x06
 376 #define AC97_PC_BEEP_VOL        0x0A
 377 #define AC97_PC_BEEP_VOL_M      0x0F
 378 #define AC97_SROUND_MASTER_VOL  0x38
 379 #define AC97_PC_BEEP_VOL_S      1
 380
 381 /*#define AC97_PHONE_VOL          0x0C
 382 #define AC97_MIC_VOL            0x0E*/
 383 #define AC97_MIC_20DB_ENABLE    0x40
 384
 385 /*#define AC97_LINEIN_VOL         0x10
 386 #define AC97_CD_VOL             0x12
 387 #define AC97_VIDEO_VOL          0x14
 388 #define AC97_AUX_VOL            0x16*/
 389 #define AC97_PCM_OUT_VOL        0x18
 390 /*#define AC97_RECORD_SELECT      0x1A*/
 391 #define AC97_RECORD_MIC         0x00
 392 #define AC97_RECORD_CD          0x01
 393 #define AC97_RECORD_VIDEO       0x02
 394 #define AC97_RECORD_AUX         0x03
 395 #define AC97_RECORD_MONO_MUX    0x02
 396 #define AC97_RECORD_DIGITAL     0x03
 397 #define AC97_RECORD_LINE        0x04
 398 #define AC97_RECORD_STEREO      0x05
 399 #define AC97_RECORD_MONO        0x06
 400 #define AC97_RECORD_PHONE       0x07
 401
 402 /*#define AC97_RECORD_GAIN        0x1C*/
 403 #define AC97_RECORD_VOL_M       0x0F
 404
 405 /*#define AC97_GENERAL_PURPOSE    0x20*/
 406 #define AC97_POWER_DOWN_CTRL    0x26
 407 #define AC97_ADC_READY          0x0001
 408 #define AC97_DAC_READY          0x0002
 409 #define AC97_ANALOG_READY       0x0004
 410 #define AC97_VREF_ON            0x0008
 411 #define AC97_PR0                0x0100
 412 #define AC97_PR1                0x0200
 413 #define AC97_PR2                0x0400
 414 #define AC97_PR3                0x0800
 415 #define AC97_PR4                0x1000
 416
 417 #define AC97_RESERVED1          0x28
 418
 419 #define AC97_VENDOR_TEST        0x5A
 420
 421 #define AC97_CLOCK_DELAY        0x5C
 422 #define AC97_LINEOUT_MUX_SEL    0x0001
 423 #define AC97_MONO_MUX_SEL       0x0002
 424 #define AC97_CLOCK_DELAY_SEL    0x1F
 425 #define AC97_DAC_CDS_SHIFT      6
 426 #define AC97_ADC_CDS_SHIFT      11
 427
 428 #define AC97_MULTI_CHANNEL_SEL  0x74
 429
 430 /*#define AC97_VENDOR_ID1         0x7C
 431 #define AC97_VENDOR_ID2         0x7E*/
 432
 433 /*
 434  * ASSP control regs
 435  */
 436 #define DSP_PORT_TIMER_COUNT    0x06
 437
 438 #define DSP_PORT_MEMORY_INDEX   0x80
 439
 440 #define DSP_PORT_MEMORY_TYPE    0x82
 441 #define MEMTYPE_INTERNAL_CODE   0x0002
 442 #define MEMTYPE_INTERNAL_DATA   0x0003
 443 #define MEMTYPE_MASK            0x0003
 444
 445 #define DSP_PORT_MEMORY_DATA    0x84
 446
 447 #define DSP_PORT_CONTROL_REG_A  0xA2
 448 #define DSP_PORT_CONTROL_REG_B  0xA4
 449 #define DSP_PORT_CONTROL_REG_C  0xA6
 450
 451 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 452 #define REV_A_CODE_MEMORY_END           0x0FFF
 453 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 454 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 455
 456 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 457 #define REV_B_CODE_MEMORY_END           0x0BFF
 458 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 459 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 460
 461 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 462 #define REV_A_DATA_MEMORY_END           0x2FFF
 463 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 464 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 465
 466 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 467 #define REV_B_DATA_MEMORY_END           0x2BFF
 468 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 469 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 470
 471
 472 #define NUM_UNITS_KERNEL_CODE          16
 473 #define NUM_UNITS_KERNEL_DATA           2
 474
 475 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 476 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 477
 478 /*
 479  * Kernel data layout
 480  */
 481
 482 #define DP_SHIFT_COUNT                  7
 483
 484 #define KDATA_BASE_ADDR                 0x1000
 485 #define KDATA_BASE_ADDR2                0x1080
 486
 487 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 488 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 489 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 490 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 491 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 492 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 493 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 494 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 495 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 496
 497 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 498 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 499
 500 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 501 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 502 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 503 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 504 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 505 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 506 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 507 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 508 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 509 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 510
 511 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 512 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 513
 514 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 515 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 516
 517 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 518 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 519
 520 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 521 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 522 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 523
 524 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 525 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 526 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 527 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 528 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 529
 530 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 531 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 532 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 533
 534 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 535 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 536 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 537
 538 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 539 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 540 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 541 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 542 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 543 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 544 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 545 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 546 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 547 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 548
 549 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 550 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 551 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 552
 553 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 554 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 555
 556 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 557 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 558 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 559
 560 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 561 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 562 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 563 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 564 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 565 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 566
 567 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 568 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 569 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 570 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 571 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 572 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 573
 574 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 575 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 576 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 577 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 578 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 579 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 580
 581 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 582 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 583 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 584 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 585
 586 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 587 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 588
 589 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 590 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 591
 592 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 593 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 594 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 595 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 596 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 597
 598 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 599 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 600
 601 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 602 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 603 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 604
 605 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 606 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 607
 608 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 609
 610 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 611 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 612 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 613 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 614 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 615 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 616 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 617 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 618 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 619 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 620 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 621 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 622
 623 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 624 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 625 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 626 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 627
 628 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 629 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 630
 631 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 632 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 633 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 634 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 635
 636 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 637 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 638 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 639 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 640 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 641
 642 /*
 643  * second 'segment' (?) reserved for mixer
 644  * buffers..
 645  */
 646
 647 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 648 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 649 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 650 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 651 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 652 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 653 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 654 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 655 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 656 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 657 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 658 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 659 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 660 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 661 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 662 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 663
 664 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 665 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 666 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 667 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 668 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 669 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 670 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 671 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 672 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 673 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 674 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 675
 676 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 677 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 678 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 679 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 680 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 681 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 682
 683 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 684 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 685 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 686 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 687
 688 /*
 689  * client data area offsets
 690  */
 691 #define CDATA_INSTANCE_READY            0x00
 692
 693 #define CDATA_HOST_SRC_ADDRL            0x01
 694 #define CDATA_HOST_SRC_ADDRH            0x02
 695 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 696 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 697 #define CDATA_HOST_SRC_CURRENTL         0x05
 698 #define CDATA_HOST_SRC_CURRENTH         0x06
 699
 700 #define CDATA_IN_BUF_CONNECT            0x07
 701 #define CDATA_OUT_BUF_CONNECT           0x08
 702
 703 #define CDATA_IN_BUF_BEGIN              0x09
 704 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 705 #define CDATA_IN_BUF_HEAD               0x0B
 706 #define CDATA_IN_BUF_TAIL               0x0C
 707 #define CDATA_OUT_BUF_BEGIN             0x0D
 708 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 709 #define CDATA_OUT_BUF_HEAD              0x0F
 710 #define CDATA_OUT_BUF_TAIL              0x10
 711
 712 #define CDATA_DMA_CONTROL               0x11
 713 #define CDATA_RESERVED                  0x12
 714
 715 #define CDATA_FREQUENCY                 0x13
 716 #define CDATA_LEFT_VOLUME               0x14
 717 #define CDATA_RIGHT_VOLUME              0x15
 718 #define CDATA_LEFT_SUR_VOL              0x16
 719 #define CDATA_RIGHT_SUR_VOL             0x17
 720
 721 #define CDATA_HEADER_LEN                0x18
 722
 723 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 724 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 725 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 726 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 727 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 728 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 729 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 730 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 731
 732 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 733 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 734 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 735 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 736 #define MINISRC_BIQUAD_STAGE    2
 737 #define MINISRC_COEF_LOC          0x175
 738
 739 #define DMACONTROL_BLOCK_MASK           0x000F
 740 #define  DMAC_BLOCK0_SELECTOR           0x0000
 741 #define  DMAC_BLOCK1_SELECTOR           0x0001
 742 #define  DMAC_BLOCK2_SELECTOR           0x0002
 743 #define  DMAC_BLOCK3_SELECTOR           0x0003
 744 #define  DMAC_BLOCK4_SELECTOR           0x0004
 745 #define  DMAC_BLOCK5_SELECTOR           0x0005
 746 #define  DMAC_BLOCK6_SELECTOR           0x0006
 747 #define  DMAC_BLOCK7_SELECTOR           0x0007
 748 #define  DMAC_BLOCK8_SELECTOR           0x0008
 749 #define  DMAC_BLOCK9_SELECTOR           0x0009
 750 #define  DMAC_BLOCKA_SELECTOR           0x000A
 751 #define  DMAC_BLOCKB_SELECTOR           0x000B
 752 #define  DMAC_BLOCKC_SELECTOR           0x000C
 753 #define  DMAC_BLOCKD_SELECTOR           0x000D
 754 #define  DMAC_BLOCKE_SELECTOR           0x000E
 755 #define  DMAC_BLOCKF_SELECTOR           0x000F
 756 #define DMACONTROL_PAGE_MASK            0x00F0
 757 #define  DMAC_PAGE0_SELECTOR            0x0030
 758 #define  DMAC_PAGE1_SELECTOR            0x0020
 759 #define  DMAC_PAGE2_SELECTOR            0x0010
 760 #define  DMAC_PAGE3_SELECTOR            0x0000
 761 #define DMACONTROL_AUTOREPEAT           0x1000
 762 #define DMACONTROL_STOPPED              0x2000
 763 #define DMACONTROL_DIRECTION            0x0100
 764
 765 /*
 766  * an arbitrary volume we set the internal
 767  * volume settings to so that the ac97 volume
 768  * range is a little less insane.  0x7fff is
 769  * max.
 770  */
 771 #define ARB_VOLUME ( 0x6800 )
 772
 773 /*
 774  */
 775
 776 typedef struct snd_m3_dma m3_dma_t;
 777 typedef struct snd_m3 m3_t;
 778 #define chip_t m3_t
 779
 780
 781 /* quirk lists */
 782 struct m3_quirk {
 783         const char *name;       /* device name */
 784         u16 vendor, device;     /* subsystem ids */
 785         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 786         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 787                                    (e.g. for IrDA on Dell Inspirons) */
 788 };
 789
 790 struct m3_list {
 791         int curlen;
 792         int mem_addr;
 793         int max;
 794 };
 795
 796 struct snd_m3_dma {
 797
 798         int number;
 799         m3_t *chip;
 800         snd_pcm_substream_t *substream;
 801
 802         struct assp_instance {
 803                 unsigned short code, data;
 804         } inst;
 805
 806         int running;
 807         int opened;
 808
 809         unsigned long buffer_addr;
 810         int dma_size;
 811         int period_size;
 812         unsigned int hwptr;
 813         int count;
 814
 815         int index[3];
 816         struct m3_list *index_list[3];
 817
 818         int in_lists;
 819
 820         struct list_head list;
 821
 822 };
 823
 824 struct snd_m3 {
 825
 826         snd_card_t *card;
 827
 828         unsigned long iobase;
 829         struct resource *iobase_res;
 830
 831         int irq;
 832         int allegro_flag : 1;
 833
 834         ac97_t *ac97;
 835
 836         snd_pcm_t *pcm;
 837
 838         struct pci_dev *pci;
 839         struct m3_quirk *quirk;
 840
 841         int dacs_active;
 842         int timer_users;
 843
 844         struct m3_list  msrc_list;
 845         struct m3_list  mixer_list;
 846         struct m3_list  adc1_list;
 847         struct m3_list  dma_list;
 848
 849         /* for storing reset state..*/
 850         u8 reset_state;
 851
 852         int external_amp;
 853         int amp_gpio;
 854
 855         /* midi */
 856         snd_rawmidi_t *rmidi;
 857
 858         /* pcm streams */
 859         int num_substreams;
 860         m3_dma_t *substreams;
 861
 862         spinlock_t reg_lock;
 863
 864 #ifdef CONFIG_PM
 865         u16 *suspend_mem;
 866 #endif
 867 };
 868
 869 /*
 870  * pci ids
 871  */
 872
 873 #ifndef PCI_VENDOR_ID_ESS
 874 #define PCI_VENDOR_ID_ESS         0x125D
 875 #endif
 876 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
 877 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 878 #endif
 879 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
 880 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
 881 #endif
 882 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
 883 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE  0x1990
 884 #endif
 885 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
 886 #define PCI_DEVICE_ID_ESS_CANYON3D_2    0x1992
 887 #endif
 888 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
 889 #define PCI_DEVICE_ID_ESS_MAESTRO3      0x1998
 890 #endif
 891 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
 892 #define PCI_DEVICE_ID_ESS_MAESTRO3_1    0x1999
 893 #endif
 894 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
 895 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW   0x199a
 896 #endif
 897 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
 898 #define PCI_DEVICE_ID_ESS_MAESTRO3_2    0x199b
 899 #endif
 900
 901 static struct pci_device_id snd_m3_ids[] = {
 902         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 903          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 904         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 905          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 906         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 907          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 908         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 909          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 910         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 911          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 912         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 913          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 914         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 915          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 916         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 917          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 918         {0,},
 919 };
 920
 921 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 922
 923 static struct m3_quirk m3_quirk_list[] = {
 924         /* panasonic CF-28 "toughbook" */
 925         {
 926                 .name = "Panasonic CF-28",
 927                 .vendor = 0x10f7,
 928                 .device = 0x833e,
 929                 .amp_gpio = 0x0d,
 930         },
 931         /* panasonic CF-72 "toughbook" */
 932         {
 933                 .name = "Panasonic CF-72",
 934                 .vendor = 0x10f7,
 935                 .device = 0x833d,
 936                 .amp_gpio = 0x0d,
 937         },
 938         /* Dell Inspiron 4000 */
 939         {
 940                 .name = "Dell Inspiron 4000",
 941                 .vendor = 0x1028,
 942                 .device = 0x00b0,
 943                 .amp_gpio = -1,
 944                 .irda_workaround = 1,
 945         },
 946         /* Dell Inspiron 8000 */
 947         {
 948                 .name = "Dell Inspiron 8000",
 949                 .vendor = 0x1028,
 950                 .device = 0x00a4,
 951                 .amp_gpio = -1,
 952                 .irda_workaround = 1,
 953         },
 954         /* Dell Inspiron 8100 */
 955         {
 956                 .name = "Dell Inspiron 8100",
 957                 .vendor = 0x1028,
 958                 .device = 0x00e6,
 959                 .amp_gpio = -1,
 960                 .irda_workaround = 1,
 961         },
 962         /* NEC LM800J/7 */
 963         {
 964                 .name = "NEC LM800J/7",
 965                 .vendor = 0x1033,
 966                 .device = 0x80f1,
 967                 .amp_gpio = 0x03,
 968         },
 969         /* END */
 970         { 0 }
 971 };
 972
 973
 974 /*
 975  * lowlevel functions
 976  */
 977
 978 #define big_mdelay(msec) do {\
 979         set_current_state(TASK_UNINTERRUPTIBLE);\
 980         schedule_timeout(((msec) * HZ) / 1000);\
 981 } while (0)
 982
 983 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
 984 {
 985         outw(value, chip->iobase + reg);
 986 }
 987
 988 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
 989 {
 990         return inw(chip->iobase + reg);
 991 }
 992
 993 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
 994 {
 995         outb(value, chip->iobase + reg);
 996 }
 997
 998 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
 999 {
1000         return inb(chip->iobase + reg);
1001 }
1002
1003 /*
1004  * access 16bit words to the code or data regions of the dsp's memory.
1005  * index addresses 16bit words.
1006  */
1007 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1008 {
1009         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1010         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1011         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1012 }
1013
1014 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1015 {
1016         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1017         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1018         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1019 }
1020
1021 static void snd_m3_assp_halt(m3_t *chip)
1022 {
1023         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1024         big_mdelay(10);
1025         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1026 }
1027
1028 static void snd_m3_assp_continue(m3_t *chip)
1029 {
1030         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1031 }
1032
1033
1034 /*
1035  * This makes me sad. the maestro3 has lists
1036  * internally that must be packed.. 0 terminates,
1037  * apparently, or maybe all unused entries have
1038  * to be 0, the lists have static lengths set
1039  * by the binary code images.
1040  */
1041
1042 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1043 {
1044         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1045                           list->mem_addr + list->curlen,
1046                           val);
1047         return list->curlen++;
1048 }
1049
1050 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1051 {
1052         u16  val;
1053         int lastindex = list->curlen - 1;
1054
1055         if (index != lastindex) {
1056                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1057                                        list->mem_addr + lastindex);
1058                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1059                                   list->mem_addr + index,
1060                                   val);
1061         }
1062
1063         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1064                           list->mem_addr + lastindex,
1065                           0);
1066
1067         list->curlen--;
1068 }
1069
1070 static void snd_m3_inc_timer_users(m3_t *chip)
1071 {
1072         chip->timer_users++;
1073         if (chip->timer_users != 1)
1074                 return;
1075
1076         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1077                           KDATA_TIMER_COUNT_RELOAD,
1078                           240);
1079
1080         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1081                           KDATA_TIMER_COUNT_CURRENT,
1082                           240);
1083
1084         snd_m3_outw(chip,
1085                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1086                     HOST_INT_CTRL);
1087 }
1088
1089 static void snd_m3_dec_timer_users(m3_t *chip)
1090 {
1091         chip->timer_users--;
1092         if (chip->timer_users > 0)
1093                 return;
1094
1095         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1096                           KDATA_TIMER_COUNT_RELOAD,
1097                           0);
1098
1099         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1100                           KDATA_TIMER_COUNT_CURRENT,
1101                           0);
1102
1103         snd_m3_outw(chip,
1104                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1105                     HOST_INT_CTRL);
1106 }
1107
1108 /*
1109  * start/stop
1110  */
1111
1112 /* spinlock held! */
1113 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1114 {
1115         if (! s || ! subs)
1116                 return -EINVAL;
1117
1118         snd_m3_inc_timer_users(chip);
1119         switch (subs->stream) {
1120         case SNDRV_PCM_STREAM_PLAYBACK:
1121                 chip->dacs_active++;
1122                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1123                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1124                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1125                                   KDATA_MIXER_TASK_NUMBER,
1126                                   chip->dacs_active);
1127                 break;
1128         case SNDRV_PCM_STREAM_CAPTURE:
1129                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1130                                   KDATA_ADC1_REQUEST, 1);
1131                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1132                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1133                 break;
1134         }
1135         return 0;
1136 }
1137
1138 /* spinlock held! */
1139 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1140 {
1141         if (! s || ! subs)
1142                 return -EINVAL;
1143
1144         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1145                           s->inst.data + CDATA_INSTANCE_READY, 0);
1146         snd_m3_dec_timer_users(chip);
1147         switch (subs->stream) {
1148         case SNDRV_PCM_STREAM_PLAYBACK:
1149                 chip->dacs_active--;
1150                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1151                                   KDATA_MIXER_TASK_NUMBER,
1152                                   chip->dacs_active);
1153                 break;
1154         case SNDRV_PCM_STREAM_CAPTURE:
1155                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1156                                   KDATA_ADC1_REQUEST, 0);
1157                 break;
1158         }
1159         return 0;
1160 }
1161
1162 static int
1163 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1164 {
1165         m3_t *chip = snd_pcm_substream_chip(subs);
1166         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1167         unsigned long flags;
1168         int err = -EINVAL;
1169
1170         snd_assert(s != NULL, return -ENXIO);
1171
1172         spin_lock_irqsave(&chip->reg_lock, flags);
1173         switch (cmd) {
1174         case SNDRV_PCM_TRIGGER_START:
1175         case SNDRV_PCM_TRIGGER_RESUME:
1176                 if (s->running)
1177                         err = -EBUSY;
1178                 else {
1179                         s->running = 1;
1180                         err = snd_m3_pcm_start(chip, s, subs);
1181                 }
1182                 break;
1183         case SNDRV_PCM_TRIGGER_STOP:
1184         case SNDRV_PCM_TRIGGER_SUSPEND:
1185                 if (! s->running)
1186                         err = 0; /* should return error? */
1187                 else {
1188                         s->running = 0;
1189                         err = snd_m3_pcm_stop(chip, s, subs);
1190                 }
1191                 break;
1192         }
1193         spin_unlock_irqrestore(&chip->reg_lock, flags);
1194         return err;
1195 }
1196
1197 /*
1198  * setup
1199  */
1200 static void
1201 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1202 {
1203         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1204         snd_pcm_runtime_t *runtime = subs->runtime;
1205
1206         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1207                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1208                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1209         } else {
1210                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1211                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1212         }
1213         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1214         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1215
1216         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1217         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1218         s->hwptr = 0;
1219         s->count = 0;
1220
1221 #define LO(x) ((x) & 0xffff)
1222 #define HI(x) LO((x) >> 16)
1223
1224         /* host dma buffer pointers */
1225         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1226                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1227                           LO(s->buffer_addr));
1228
1229         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1230                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1231                           HI(s->buffer_addr));
1232
1233         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1234                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1235                           LO(s->buffer_addr + s->dma_size));
1236
1237         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1238                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1239                           HI(s->buffer_addr + s->dma_size));
1240
1241         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1242                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1243                           LO(s->buffer_addr));
1244
1245         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1246                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1247                           HI(s->buffer_addr));
1248 #undef LO
1249 #undef HI
1250
1251         /* dsp buffers */
1252
1253         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1254                           s->inst.data + CDATA_IN_BUF_BEGIN,
1255                           dsp_in_buffer);
1256
1257         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1258                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1259                           dsp_in_buffer + (dsp_in_size / 2));
1260
1261         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1262                           s->inst.data + CDATA_IN_BUF_HEAD,
1263                           dsp_in_buffer);
1264
1265         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1266                           s->inst.data + CDATA_IN_BUF_TAIL,
1267                           dsp_in_buffer);
1268
1269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1271                           dsp_out_buffer);
1272
1273         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1275                           dsp_out_buffer + (dsp_out_size / 2));
1276
1277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278                           s->inst.data + CDATA_OUT_BUF_HEAD,
1279                           dsp_out_buffer);
1280
1281         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282                           s->inst.data + CDATA_OUT_BUF_TAIL,
1283                           dsp_out_buffer);
1284 }
1285
1286 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1287 {
1288         u32 freq;
1289
1290         /*
1291          * put us in the lists if we're not already there
1292          */
1293         if (! s->in_lists) {
1294                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1295                                               s->inst.data >> DP_SHIFT_COUNT);
1296                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1297                                               s->inst.data >> DP_SHIFT_COUNT);
1298                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1299                                               s->inst.data >> DP_SHIFT_COUNT);
1300                 s->in_lists = 1;
1301         }
1302
1303         /* write to 'mono' word */
1304         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1305                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1306                           runtime->channels == 2 ? 0 : 1);
1307         /* write to '8bit' word */
1308         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1309                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1310                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1311
1312         /* set up dac/adc rate */
1313         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1314         if (freq)
1315                 freq--;
1316
1317         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318                           s->inst.data + CDATA_FREQUENCY,
1319                           freq);
1320 }
1321
1322
1323 static struct play_vals {
1324         u16 addr, val;
1325 } pv[] = {
1326         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1327         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1328         {SRC3_DIRECTION_OFFSET, 0} ,
1329         /* +1, +2 are stereo/16 bit */
1330         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1331         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1332         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1333         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1334         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1335         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1336         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1337         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1338         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1339         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1340         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1341         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1342         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1343         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1344         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1345         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1346         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1347 };
1348
1349
1350 /* the mode passed should be already shifted and masked */
1351 static void
1352 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1353 {
1354         unsigned int i;
1355
1356         /*
1357          * some per client initializers
1358          */
1359
1360         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1361                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1362                           s->inst.data + 40 + 8);
1363
1364         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1365                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1366                           s->inst.code + MINISRC_COEF_LOC);
1367
1368         /* enable or disable low pass filter? */
1369         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1370                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1371                           subs->runtime->rate > 45000 ? 0xff : 0);
1372
1373         /* tell it which way dma is going? */
1374         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1375                           s->inst.data + CDATA_DMA_CONTROL,
1376                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1377
1378         /*
1379          * set an armload of static initializers
1380          */
1381         for (i = 0; i < ARRAY_SIZE(pv); i++)
1382                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1383                                   s->inst.data + pv[i].addr, pv[i].val);
1384 }
1385
1386 /*
1387  *    Native record driver
1388  */
1389 static struct rec_vals {
1390         u16 addr, val;
1391 } rv[] = {
1392         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1393         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1394         {SRC3_DIRECTION_OFFSET, 1} ,
1395         /* +1, +2 are stereo/16 bit */
1396         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1397         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1398         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1399         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1400         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1401         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1402         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1403         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1404         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1405         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1406         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1407         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1408         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1409         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1410         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1411         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1412         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1413         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1414         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1415 };
1416
1417 static void
1418 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1419 {
1420         unsigned int i;
1421
1422         /*
1423          * some per client initializers
1424          */
1425
1426         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1427                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1428                           s->inst.data + 40 + 8);
1429
1430         /* tell it which way dma is going? */
1431         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1432                           s->inst.data + CDATA_DMA_CONTROL,
1433                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1434                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1435
1436         /*
1437          * set an armload of static initializers
1438          */
1439         for (i = 0; i < ARRAY_SIZE(rv); i++)
1440                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1441                                   s->inst.data + rv[i].addr, rv[i].val);
1442 }
1443
1444 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1445                                 snd_pcm_hw_params_t * hw_params)
1446 {
1447         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1448         int err;
1449
1450         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1451                 return err;
1452         /* set buffer address */
1453         s->buffer_addr = substream->runtime->dma_addr;
1454         if (s->buffer_addr & 0x3) {
1455                 snd_printk("oh my, not aligned\n");
1456                 s->buffer_addr = s->buffer_addr & ~0x3;
1457         }
1458         return 0;
1459 }
1460
1461 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1462 {
1463         m3_dma_t *s;
1464
1465         if (substream->runtime->private_data == NULL)
1466                 return 0;
1467         s = (m3_dma_t*) substream->runtime->private_data;
1468         snd_pcm_lib_free_pages(substream);
1469         s->buffer_addr = 0;
1470         return 0;
1471 }
1472
1473 static int
1474 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1475 {
1476         m3_t *chip = snd_pcm_substream_chip(subs);
1477         snd_pcm_runtime_t *runtime = subs->runtime;
1478         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1479         unsigned long flags;
1480
1481         snd_assert(s != NULL, return -ENXIO);
1482
1483         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1484             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1485                 return -EINVAL;
1486         if (runtime->rate > 48000 ||
1487             runtime->rate < 8000)
1488                 return -EINVAL;
1489
1490         spin_lock_irqsave(&chip->reg_lock, flags);
1491
1492         snd_m3_pcm_setup1(chip, s, subs);
1493
1494         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1495                 snd_m3_playback_setup(chip, s, subs);
1496         else
1497                 snd_m3_capture_setup(chip, s, subs);
1498
1499         snd_m3_pcm_setup2(chip, s, runtime);
1500
1501         spin_unlock_irqrestore(&chip->reg_lock, flags);
1502
1503         return 0;
1504 }
1505
1506 /*
1507  * get current pointer
1508  */
1509 static unsigned int
1510 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1511 {
1512         u16 hi = 0, lo = 0;
1513         int retry = 10;
1514         u32 addr;
1515
1516         /*
1517          * try and get a valid answer
1518          */
1519         while (retry--) {
1520                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1521                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1522
1523                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1524                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1525
1526                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1527                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1528                         break;
1529         }
1530         addr = lo | ((u32)hi<<16);
1531         return (unsigned int)(addr - s->buffer_addr);
1532 }
1533
1534 static snd_pcm_uframes_t
1535 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1536 {
1537         m3_t *chip = snd_pcm_substream_chip(subs);
1538         unsigned int ptr;
1539         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1540         snd_assert(s != NULL, return 0);
1541
1542         spin_lock(&chip->reg_lock);
1543         ptr = snd_m3_get_pointer(chip, s, subs);
1544         spin_unlock(&chip->reg_lock);
1545         return bytes_to_frames(subs->runtime, ptr);
1546 }
1547
1548
1549 /* update pointer */
1550 /* spinlock held! */
1551 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1552 {
1553         snd_pcm_substream_t *subs = s->substream;
1554         unsigned int hwptr;
1555         int diff;
1556
1557         if (! s->running)
1558                 return;
1559
1560         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1561         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1562         s->hwptr = hwptr;
1563         s->count += diff;
1564         if (s->count >= (signed)s->period_size) {
1565                 s->count %= s->period_size;
1566                 spin_unlock(&chip->reg_lock);
1567                 snd_pcm_period_elapsed(subs);
1568                 spin_lock(&chip->reg_lock);
1569         }
1570 }
1571
1572 static irqreturn_t
1573 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1574 {
1575         m3_t *chip = snd_magic_cast(m3_t, dev_id, );
1576         u8 status;
1577         int i;
1578
1579         status = inb(chip->iobase + HOST_INT_STATUS);
1580
1581         if (status == 0xff)
1582                 return IRQ_NONE;
1583
1584         /*
1585          * ack an assp int if its running
1586          * and has an int pending
1587          */
1588         if (status & ASSP_INT_PENDING) {
1589                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1590                 if (!(ctl & STOP_ASSP_CLOCK)) {
1591                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1592                         if (ctl & DSP2HOST_REQ_TIMER) {
1593                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1594                                 /* update adc/dac info if it was a timer int */
1595                                 spin_lock(&chip->reg_lock);
1596                                 for (i = 0; i < chip->num_substreams; i++) {
1597                                         m3_dma_t *s = &chip->substreams[i];
1598                                         if (s->running)
1599                                                 snd_m3_update_ptr(chip, s);
1600                                 }
1601                                 spin_unlock(&chip->reg_lock);
1602                         }
1603                 }
1604         }
1605
1606 #if 0 /* TODO: not supported yet */
1607         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1608                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1609 #endif
1610
1611         /* ack ints */
1612         snd_m3_outw(chip, HOST_INT_STATUS, status);
1613
1614         return IRQ_HANDLED;
1615 }
1616
1617
1618 /*
1619  */
1620
1621 static snd_pcm_hardware_t snd_m3_playback =
1622 {
1623         .info =                 (SNDRV_PCM_INFO_MMAP |
1624                                  SNDRV_PCM_INFO_INTERLEAVED |
1625                                  SNDRV_PCM_INFO_MMAP_VALID |
1626                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1627                                  /*SNDRV_PCM_INFO_PAUSE |*/
1628                                  SNDRV_PCM_INFO_RESUME),
1629         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1630         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1631         .rate_min =             8000,
1632         .rate_max =             48000,
1633         .channels_min =         1,
1634         .channels_max =         2,
1635         .buffer_bytes_max =     (512*1024),
1636         .period_bytes_min =     64,
1637         .period_bytes_max =     (512*1024),
1638         .periods_min =          1,
1639         .periods_max =          1024,
1640 };
1641
1642 static snd_pcm_hardware_t snd_m3_capture =
1643 {
1644         .info =                 (SNDRV_PCM_INFO_MMAP |
1645                                  SNDRV_PCM_INFO_INTERLEAVED |
1646                                  SNDRV_PCM_INFO_MMAP_VALID |
1647                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1648                                  /*SNDRV_PCM_INFO_PAUSE |*/
1649                                  SNDRV_PCM_INFO_RESUME),
1650         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1651         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1652         .rate_min =             8000,
1653         .rate_max =             48000,
1654         .channels_min =         1,
1655         .channels_max =         2,
1656         .buffer_bytes_max =     (512*1024),
1657         .period_bytes_min =     64,
1658         .period_bytes_max =     (512*1024),
1659         .periods_min =          1,
1660         .periods_max =          1024,
1661 };
1662
1663
1664 /*
1665  */
1666
1667 static int
1668 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1669 {
1670         int i;
1671         m3_dma_t *s;
1672         unsigned long flags;
1673
1674         spin_lock_irqsave(&chip->reg_lock, flags);
1675         for (i = 0; i < chip->num_substreams; i++) {
1676                 s = &chip->substreams[i];
1677                 if (! s->opened)
1678                         goto __found;
1679         }
1680         spin_unlock_irqrestore(&chip->reg_lock, flags);
1681         return -ENOMEM;
1682 __found:
1683         s->opened = 1;
1684         s->running = 0;
1685         spin_unlock_irqrestore(&chip->reg_lock, flags);
1686
1687         subs->runtime->private_data = s;
1688         s->substream = subs;
1689
1690         /* set list owners */
1691         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1692                 s->index_list[0] = &chip->mixer_list;
1693         } else
1694                 s->index_list[0] = &chip->adc1_list;
1695         s->index_list[1] = &chip->msrc_list;
1696         s->index_list[2] = &chip->dma_list;
1697
1698         return 0;
1699 }
1700
1701 static void
1702 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1703 {
1704         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1705         unsigned long flags;
1706
1707         if (s == NULL)
1708                 return; /* not opened properly */
1709
1710         spin_lock_irqsave(&chip->reg_lock, flags);
1711         if (s->substream && s->running)
1712                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1713         if (s->in_lists) {
1714                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1715                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1716                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1717                 s->in_lists = 0;
1718         }
1719         s->running = 0;
1720         s->opened = 0;
1721         spin_unlock_irqrestore(&chip->reg_lock, flags);
1722 }
1723
1724 static int
1725 snd_m3_playback_open(snd_pcm_substream_t *subs)
1726 {
1727         m3_t *chip = snd_pcm_substream_chip(subs);
1728         snd_pcm_runtime_t *runtime = subs->runtime;
1729         int err;
1730
1731         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1732                 return err;
1733
1734         runtime->hw = snd_m3_playback;
1735         snd_pcm_set_sync(subs);
1736
1737         return 0;
1738 }
1739
1740 static int
1741 snd_m3_playback_close(snd_pcm_substream_t *subs)
1742 {
1743         m3_t *chip = snd_pcm_substream_chip(subs);
1744
1745         snd_m3_substream_close(chip, subs);
1746         return 0;
1747 }
1748
1749 static int
1750 snd_m3_capture_open(snd_pcm_substream_t *subs)
1751 {
1752         m3_t *chip = snd_pcm_substream_chip(subs);
1753         snd_pcm_runtime_t *runtime = subs->runtime;
1754         int err;
1755
1756         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1757                 return err;
1758
1759         runtime->hw = snd_m3_capture;
1760         snd_pcm_set_sync(subs);
1761
1762         return 0;
1763 }
1764
1765 static int
1766 snd_m3_capture_close(snd_pcm_substream_t *subs)
1767 {
1768         m3_t *chip = snd_pcm_substream_chip(subs);
1769
1770         snd_m3_substream_close(chip, subs);
1771         return 0;
1772 }
1773
1774 /*
1775  * create pcm instance
1776  */
1777
1778 static snd_pcm_ops_t snd_m3_playback_ops = {
1779         .open =         snd_m3_playback_open,
1780         .close =        snd_m3_playback_close,
1781         .ioctl =        snd_pcm_lib_ioctl,
1782         .hw_params =    snd_m3_pcm_hw_params,
1783         .hw_free =      snd_m3_pcm_hw_free,
1784         .prepare =      snd_m3_pcm_prepare,
1785         .trigger =      snd_m3_pcm_trigger,
1786         .pointer =      snd_m3_pcm_pointer,
1787 };
1788
1789 static snd_pcm_ops_t snd_m3_capture_ops = {
1790         .open =         snd_m3_capture_open,
1791         .close =        snd_m3_capture_close,
1792         .ioctl =        snd_pcm_lib_ioctl,
1793         .hw_params =    snd_m3_pcm_hw_params,
1794         .hw_free =      snd_m3_pcm_hw_free,
1795         .prepare =      snd_m3_pcm_prepare,
1796         .trigger =      snd_m3_pcm_trigger,
1797         .pointer =      snd_m3_pcm_pointer,
1798 };
1799
1800 static int __devinit
1801 snd_m3_pcm(m3_t * chip, int device)
1802 {
1803         snd_pcm_t *pcm;
1804         int err;
1805
1806         err = snd_pcm_new(chip->card, chip->card->driver, device,
1807                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1808         if (err < 0)
1809                 return err;
1810
1811         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1812         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1813
1814         pcm->private_data = chip;
1815         pcm->info_flags = 0;
1816         strcpy(pcm->name, chip->card->driver);
1817         chip->pcm = pcm;
1818
1819         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1820                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1821
1822         return 0;
1823 }
1824
1825
1826 /*
1827  * ac97 interface
1828  */
1829
1830 /*
1831  * Wait for the ac97 serial bus to be free.
1832  * return nonzero if the bus is still busy.
1833  */
1834 static int snd_m3_ac97_wait(m3_t *chip)
1835 {
1836         int i = 10000;
1837
1838         do {
1839                 if (! (snd_m3_inb(chip, 0x30) & 1))
1840                         return 0;
1841         } while (i-- > 0);
1842
1843         snd_printk("ac97 serial bus busy\n");
1844         return 1;
1845 }
1846
1847 static unsigned short
1848 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1849 {
1850         m3_t *chip = snd_magic_cast(m3_t, ac97->private_data, return -ENXIO);
1851         unsigned short ret = 0;
1852         unsigned long flags;
1853
1854         spin_lock_irqsave(&chip->reg_lock, flags);
1855         if (snd_m3_ac97_wait(chip))
1856                 goto __error;
1857         snd_m3_outb(chip, 0x80 | (reg & 0x7f), 0x30);
1858         if (snd_m3_ac97_wait(chip))
1859                 goto __error;
1860         ret = snd_m3_inw(chip, 0x32);
1861 __error:
1862         spin_unlock_irqrestore(&chip->reg_lock, flags);
1863         return ret;
1864 }
1865
1866 static void
1867 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1868 {
1869         m3_t *chip = snd_magic_cast(m3_t, ac97->private_data, return);
1870         unsigned long flags;
1871
1872         spin_lock_irqsave(&chip->reg_lock, flags);
1873         if (snd_m3_ac97_wait(chip))
1874                 goto __error;
1875         snd_m3_outw(chip, val, 0x32);
1876         snd_m3_outb(chip, reg & 0x7f, 0x30);
1877 __error:
1878         spin_unlock_irqrestore(&chip->reg_lock, flags);
1879 }
1880
1881
1882 static void snd_m3_remote_codec_config(int io, int isremote)
1883 {
1884         isremote = isremote ? 1 : 0;
1885
1886         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1887              io + RING_BUS_CTRL_B);
1888         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1889              io + SDO_OUT_DEST_CTRL);
1890         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1891              io + SDO_IN_DEST_CTRL);
1892 }
1893
1894 /*
1895  * hack, returns non zero on err
1896  */
1897 static int snd_m3_try_read_vendor(m3_t *chip)
1898 {
1899         u16 ret;
1900
1901         if (snd_m3_ac97_wait(chip))
1902                 return 1;
1903
1904         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1905
1906         if (snd_m3_ac97_wait(chip))
1907                 return 1;
1908
1909         ret = snd_m3_inw(chip, 0x32);
1910
1911         return (ret == 0) || (ret == 0xffff);
1912 }
1913
1914 static void snd_m3_ac97_reset(m3_t *chip)
1915 {
1916         u16 dir;
1917         int delay1 = 0, delay2 = 0, i;
1918         int io = chip->iobase;
1919
1920         if (chip->allegro_flag) {
1921                 /*
1922                  * the onboard codec on the allegro seems
1923                  * to want to wait a very long time before
1924                  * coming back to life
1925                  */
1926                 delay1 = 50;
1927                 delay2 = 800;
1928         } else {
1929                 /* maestro3 */
1930                 delay1 = 20;
1931                 delay2 = 500;
1932         }
1933
1934         for (i = 0; i < 5; i++) {
1935                 dir = inw(io + GPIO_DIRECTION);
1936                 if (! chip->quirk || ! chip->quirk->irda_workaround)
1937                         dir |= 0x10; /* assuming pci bus master? */
1938
1939                 snd_m3_remote_codec_config(io, 0);
1940
1941                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1942                 udelay(20);
1943
1944                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1945                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1946                 outw(0, io + GPIO_DATA);
1947                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1948
1949                 set_current_state(TASK_UNINTERRUPTIBLE);
1950                 schedule_timeout((delay1 * HZ) / 1000);
1951
1952                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1953                 udelay(5);
1954                 /* ok, bring back the ac-link */
1955                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1956                 outw(~0, io + GPIO_MASK);
1957
1958                 set_current_state(TASK_UNINTERRUPTIBLE);
1959                 schedule_timeout((delay2 * HZ) / 1000);
1960
1961                 if (! snd_m3_try_read_vendor(chip))
1962                         break;
1963
1964                 delay1 += 10;
1965                 delay2 += 100;
1966
1967                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
1968                            delay1, delay2);
1969         }
1970
1971 #if 0
1972         /* more gung-ho reset that doesn't
1973          * seem to work anywhere :)
1974          */
1975         tmp = inw(io + RING_BUS_CTRL_A);
1976         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
1977         big_mdelay(20);
1978         outw(tmp, io + RING_BUS_CTRL_A);
1979         big_mdelay(50);
1980 #endif
1981 }
1982
1983 static int __devinit snd_m3_mixer(m3_t *chip)
1984 {
1985         ac97_bus_t bus, *pbus;
1986         ac97_t ac97;
1987         int err;
1988
1989         memset(&bus, 0, sizeof(bus));
1990         bus.write = snd_m3_ac97_write;
1991         bus.read = snd_m3_ac97_read;
1992         if ((err = snd_ac97_bus(chip->card, &bus, &pbus)) < 0)
1993                 return err;
1994
1995         memset(&ac97, 0, sizeof(ac97));
1996         ac97.private_data = chip;
1997         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1998                 return err;
1999
2000         /* seems ac97 PCM needs initialization.. hack hack.. */
2001         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2002         set_current_state(TASK_UNINTERRUPTIBLE);
2003         schedule_timeout(HZ / 10);
2004         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2005
2006         return 0;
2007 }
2008
2009
2010 /*
2011  * DSP Code images
2012  */
2013
2014 static u16 assp_kernel_image[] __devinitdata = {
2015     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2016     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2017     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2018     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2019     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2020     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2021     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2022     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2023     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2024     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2025     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2026     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2027     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2028     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2029     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2030     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2031     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2032     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2033     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2034     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2035     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2036     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2037     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2038     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2039     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2040     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2041     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2042     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2043     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2044     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2045     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2046     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2047     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2048     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2049     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2050     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2051     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2052     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2053     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2054     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2055     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2056     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2057     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2058     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2059     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2060     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2061     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2062     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2063     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2064     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2065     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2066     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2067     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2068     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2069     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2070     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2071     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2072     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2073     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2074     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2075     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2076     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2077     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2078     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2079     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2080     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2081     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2082     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2083     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2084     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2085     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2086     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2087     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2088     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2089     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2090     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2091     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2092     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2093     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2094     0xBE3A,
2095 };
2096
2097 /*
2098  * Mini sample rate converter code image
2099  * that is to be loaded at 0x400 on the DSP.
2100  */
2101 static u16 assp_minisrc_image[] __devinitdata = {
2102
2103     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2104     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2105     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2106     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2107     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2108     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2109     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2110     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2111     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2112     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2113     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2114     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2115     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2116     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2117     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2118     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2119     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2120     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2121     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2122     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2123     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2124     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2125     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2126     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2127     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2128     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2129     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2130     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2131     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2132     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2133     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2134     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2135     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2136 };
2137
2138
2139 /*
2140  * initialize ASSP
2141  */
2142
2143 #define MINISRC_LPF_LEN 10
2144 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2145         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2146         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2147 };
2148
2149 static void __devinit snd_m3_assp_init(m3_t *chip)
2150 {
2151         unsigned int i;
2152
2153         /* zero kernel data */
2154         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2155                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2156                                   KDATA_BASE_ADDR + i, 0);
2157
2158         /* zero mixer data? */
2159         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2160                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2161                                   KDATA_BASE_ADDR2 + i, 0);
2162
2163         /* init dma pointer */
2164         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2165                           KDATA_CURRENT_DMA,
2166                           KDATA_DMA_XFER0);
2167
2168         /* write kernel into code memory.. */
2169         for (i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2170                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2171                                   REV_B_CODE_MEMORY_BEGIN + i,
2172                                   assp_kernel_image[i]);
2173         }
2174
2175         /*
2176          * We only have this one client and we know that 0x400
2177          * is free in our kernel's mem map, so lets just
2178          * drop it there.  It seems that the minisrc doesn't
2179          * need vectors, so we won't bother with them..
2180          */
2181         for (i = 0; i < sizeof(assp_minisrc_image) / 2; i++) {
2182                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2183                                   0x400 + i,
2184                                   assp_minisrc_image[i]);
2185         }
2186
2187         /*
2188          * write the coefficients for the low pass filter?
2189          */
2190         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2191                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2192                                   0x400 + MINISRC_COEF_LOC + i,
2193                                   minisrc_lpf[i]);
2194         }
2195
2196         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2197                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2198                           0x8000);
2199
2200         /*
2201          * the minisrc is the only thing on
2202          * our task list..
2203          */
2204         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2205                           KDATA_TASK0,
2206                           0x400);
2207
2208         /*
2209          * init the mixer number..
2210          */
2211
2212         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2213                           KDATA_MIXER_TASK_NUMBER,0);
2214
2215         /*
2216          * EXTREME KERNEL MASTER VOLUME
2217          */
2218         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2219                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2220         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2221                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2222
2223         chip->mixer_list.curlen = 0;
2224         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2225         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2226         chip->adc1_list.curlen = 0;
2227         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2228         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2229         chip->dma_list.curlen = 0;
2230         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2231         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2232         chip->msrc_list.curlen = 0;
2233         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2234         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2235 }
2236
2237
2238 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2239 {
2240         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2241                                MINISRC_IN_BUFFER_SIZE / 2 +
2242                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2243         int address, i;
2244
2245         /*
2246          * the revb memory map has 0x1100 through 0x1c00
2247          * free.
2248          */
2249
2250         /*
2251          * align instance address to 256 bytes so that it's
2252          * shifted list address is aligned.
2253          * list address = (mem address >> 1) >> 7;
2254          */
2255         data_bytes = (data_bytes + 255) & ~255;
2256         address = 0x1100 + ((data_bytes/2) * index);
2257
2258         if ((address + (data_bytes/2)) >= 0x1c00) {
2259                 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2260                            data_bytes, index, address);
2261                 return -ENOMEM;
2262         }
2263
2264         s->number = index;
2265         s->inst.code = 0x400;
2266         s->inst.data = address;
2267
2268         for (i = data_bytes / 2; i > 0; address++, i--) {
2269                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2270                                   address, 0);
2271         }
2272
2273         return 0;
2274 }
2275
2276
2277 /*
2278  * this works for the reference board, have to find
2279  * out about others
2280  *
2281  * this needs more magic for 4 speaker, but..
2282  */
2283 static void
2284 snd_m3_amp_enable(m3_t *chip, int enable)
2285 {
2286         int io = chip->iobase;
2287         u16 gpo, polarity;
2288
2289         if (! chip->external_amp)
2290                 return;
2291
2292         polarity = enable ? 0 : 1;
2293         polarity = polarity << chip->amp_gpio;
2294         gpo = 1 << chip->amp_gpio;
2295
2296         outw(~gpo, io + GPIO_MASK);
2297
2298         outw(inw(io + GPIO_DIRECTION) | gpo,
2299              io + GPIO_DIRECTION);
2300
2301         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2302              io + GPIO_DATA);
2303
2304         outw(0xffff, io + GPIO_MASK);
2305 }
2306
2307 static int
2308 snd_m3_chip_init(m3_t *chip)
2309 {
2310         struct pci_dev *pcidev = chip->pci;
2311         u32 n;
2312         u16 w;
2313         u8 t; /* makes as much sense as 'n', no? */
2314
2315         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2316         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2317                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2318                DISABLE_LEGACY);
2319         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2320
2321         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2322         n &= REDUCED_DEBOUNCE;
2323         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2324         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2325
2326         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2327         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2328         n &= ~INT_CLK_SELECT;
2329         if (!chip->allegro_flag) {
2330                 n &= ~INT_CLK_MULT_ENABLE;
2331                 n |= INT_CLK_SRC_NOT_PCI;
2332         }
2333         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2334         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2335
2336         if (chip->allegro_flag) {
2337                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2338                 n |= IN_CLK_12MHZ_SELECT;
2339                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2340         }
2341
2342         t = inb(chip->iobase + ASSP_CONTROL_A);
2343         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2344         t |= ASSP_CLK_49MHZ_SELECT;
2345         t |= ASSP_0_WS_ENABLE;
2346         outb(t, chip->iobase + ASSP_CONTROL_A);
2347
2348         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2349
2350         return 0;
2351 }
2352
2353 static void
2354 snd_m3_enable_ints(m3_t *chip)
2355 {
2356         unsigned long io = chip->iobase;
2357
2358         /* TODO: MPU401 not supported yet */
2359         outw(ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
2360         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2361              io + ASSP_CONTROL_C);
2362 }
2363
2364
2365 /*
2366  */
2367
2368 static int snd_m3_free(m3_t *chip)
2369 {
2370         unsigned long flags;
2371         m3_dma_t *s;
2372         int i;
2373
2374         if (chip->substreams) {
2375                 spin_lock_irqsave(&chip->reg_lock, flags);
2376                 for (i = 0; i < chip->num_substreams; i++) {
2377                         s = &chip->substreams[i];
2378                         /* check surviving pcms; this should not happen though.. */
2379                         if (s->substream && s->running)
2380                                 snd_m3_pcm_stop(chip, s, s->substream);
2381                 }
2382                 spin_unlock_irqrestore(&chip->reg_lock, flags);
2383                 kfree(chip->substreams);
2384         }
2385         if (chip->iobase_res) {
2386                 snd_m3_outw(chip, HOST_INT_CTRL, 0); /* disable ints */
2387         }
2388
2389 #ifdef CONFIG_PM
2390         if (chip->suspend_mem)
2391                 vfree(chip->suspend_mem);
2392 #endif
2393
2394         if (chip->irq >= 0)
2395                 synchronize_irq(chip->irq);
2396
2397         if (chip->iobase_res) {
2398                 release_resource(chip->iobase_res);
2399                 kfree_nocheck(chip->iobase_res);
2400         }
2401         if (chip->irq >= 0)
2402                 free_irq(chip->irq, (void *)chip);
2403
2404         snd_magic_kfree(chip);
2405         return 0;
2406 }
2407
2408
2409 /*
2410  * APM support
2411  */
2412 #ifdef CONFIG_PM
2413
2414 static void m3_suspend(m3_t *chip)
2415 {
2416         snd_card_t *card = chip->card;
2417         int i, index;
2418
2419         if (chip->suspend_mem == NULL)
2420                 return;
2421         if (card->power_state == SNDRV_CTL_POWER_D3hot)
2422                 return;
2423
2424         snd_pcm_suspend_all(chip->pcm);
2425
2426         big_mdelay(10); /* give the assp a chance to idle.. */
2427
2428         snd_m3_assp_halt(chip);
2429
2430         /* save dsp image */
2431         index = 0;
2432         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2433                 chip->suspend_mem[index++] =
2434                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2435         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2436                 chip->suspend_mem[index++] =
2437                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2438
2439         /* power down apci registers */
2440         snd_m3_outw(chip, 0xffff, 0x54);
2441         snd_m3_outw(chip, 0xffff, 0x56);
2442         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2443 }
2444
2445 static void m3_resume(m3_t *chip)
2446 {
2447         snd_card_t *card = chip->card;
2448         int i, index;
2449
2450         if (chip->suspend_mem == NULL)
2451                 return;
2452         if (card->power_state == SNDRV_CTL_POWER_D0)
2453                 return;
2454
2455         /* first lets just bring everything back. .*/
2456         snd_m3_outw(chip, 0, 0x54);
2457         snd_m3_outw(chip, 0, 0x56);
2458
2459         snd_m3_chip_init(chip);
2460         snd_m3_assp_halt(chip);
2461         snd_m3_ac97_reset(chip);
2462
2463         /* restore dsp image */
2464         index = 0;
2465         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2466                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2467                                   chip->suspend_mem[index++]);
2468         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2469                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2470                                   chip->suspend_mem[index++]);
2471
2472         /* tell the dma engine to restart itself */
2473         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2474                           KDATA_DMA_ACTIVE, 0);
2475
2476         /* restore ac97 registers */
2477         snd_ac97_resume(chip->ac97);
2478
2479         snd_m3_assp_continue(chip);
2480         snd_m3_enable_ints(chip);
2481         snd_m3_amp_enable(chip, 1);
2482
2483         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2484 }
2485
2486 static int snd_m3_suspend(struct pci_dev *pci, u32 state)
2487 {
2488         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return -ENXIO);
2489         m3_suspend(chip);
2490         return 0;
2491 }
2492 static int snd_m3_resume(struct pci_dev *pci)
2493 {
2494         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return -ENXIO);
2495         m3_resume(chip);
2496         return 0;
2497 }
2498
2499 /* callback */
2500 static int snd_m3_set_power_state(snd_card_t *card, unsigned int power_state)
2501 {
2502         m3_t *chip = snd_magic_cast(m3_t, card->power_state_private_data, return -ENXIO);
2503         switch (power_state) {
2504         case SNDRV_CTL_POWER_D0:
2505         case SNDRV_CTL_POWER_D1:
2506         case SNDRV_CTL_POWER_D2:
2507                 m3_resume(chip);
2508                 break;
2509         case SNDRV_CTL_POWER_D3hot:
2510         case SNDRV_CTL_POWER_D3cold:
2511                 m3_suspend(chip);
2512                 break;
2513         default:
2514                 return -EINVAL;
2515         }
2516         return 0;
2517 }
2518
2519 #endif /* CONFIG_PM */
2520
2521
2522 /*
2523  */
2524
2525 static int snd_m3_dev_free(snd_device_t *device)
2526 {
2527         m3_t *chip = snd_magic_cast(m3_t, device->device_data, return -ENXIO);
2528         return snd_m3_free(chip);
2529 }
2530
2531 static int __devinit
2532 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2533               int enable_amp,
2534               int amp_gpio,
2535               m3_t **chip_ret)
2536 {
2537         m3_t *chip;
2538         int i, err;
2539         struct m3_quirk *quirk;
2540         u16 subsystem_vendor, subsystem_device;
2541         static snd_device_ops_t ops = {
2542                 .dev_free =     snd_m3_dev_free,
2543         };
2544
2545         *chip_ret = NULL;
2546
2547         if (pci_enable_device(pci))
2548                 return -EIO;
2549
2550         /* check, if we can restrict PCI DMA transfers to 28 bits */
2551         if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2552             pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2553                 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2554                 return -ENXIO;
2555         }
2556
2557         chip = snd_magic_kcalloc(m3_t, 0, GFP_KERNEL);
2558         if (chip == NULL)
2559                 return -ENOMEM;
2560
2561         spin_lock_init(&chip->reg_lock);
2562         switch (pci->device) {
2563         case PCI_DEVICE_ID_ESS_ALLEGRO:
2564         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2565         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2566         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2567                 chip->allegro_flag = 1;
2568                 break;
2569         }
2570
2571         chip->card = card;
2572         chip->pci = pci;
2573         chip->irq = -1;
2574
2575         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2576         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2577
2578         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2579                 if (subsystem_vendor == quirk->vendor &&
2580                     subsystem_device == quirk->device) {
2581                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2582                         chip->quirk = quirk;
2583                         break;
2584                 }
2585         }
2586
2587         chip->external_amp = enable_amp;
2588         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2589                 chip->amp_gpio = amp_gpio;
2590         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2591                 chip->amp_gpio = chip->quirk->amp_gpio;
2592         else if (chip->allegro_flag)
2593                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2594         else /* presumably this is for all 'maestro3's.. */
2595                 chip->amp_gpio = GPO_EXT_AMP_M3;
2596
2597         chip->num_substreams = NR_DSPS;
2598         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2599         if (chip->substreams == NULL) {
2600                 snd_magic_kfree(chip);
2601                 return -ENOMEM;
2602         }
2603         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2604
2605         chip->iobase = pci_resource_start(pci, 0);
2606         if ((chip->iobase_res = request_region(chip->iobase, 256,
2607                                                card->driver)) == NULL) {
2608                 snd_printk("unable to grab i/o ports %ld\n", chip->iobase);
2609                 snd_m3_free(chip);
2610                 return -EBUSY;
2611         }
2612
2613         /* just to be sure */
2614         pci_set_master(pci);
2615
2616         snd_m3_chip_init(chip);
2617         snd_m3_assp_halt(chip);
2618
2619         snd_m3_ac97_reset(chip);
2620
2621         snd_m3_assp_init(chip);
2622         snd_m3_amp_enable(chip, 1);
2623
2624         if ((err = snd_m3_mixer(chip)) < 0) {
2625                 snd_m3_free(chip);
2626                 return err;
2627         }
2628
2629         for (i = 0; i < chip->num_substreams; i++) {
2630                 m3_dma_t *s = &chip->substreams[i];
2631                 s->chip = chip;
2632                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) {
2633                         snd_m3_free(chip);
2634                         return err;
2635                 }
2636         }
2637
2638         if ((err = snd_m3_pcm(chip, 0)) < 0) {
2639                 snd_m3_free(chip);
2640                 return err;
2641         }
2642
2643         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2644                         card->driver, (void *)chip)) {
2645                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2646                 snd_m3_free(chip);
2647                 return -ENOMEM;
2648         }
2649         chip->irq = pci->irq;
2650
2651 #ifdef CONFIG_PM
2652         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2653         if (chip->suspend_mem == NULL)
2654                 snd_printk("can't allocate apm buffer\n");
2655         else {
2656                 card->set_power_state = snd_m3_set_power_state;
2657                 card->power_state_private_data = chip;
2658         }
2659 #endif
2660
2661         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2662                 snd_m3_free(chip);
2663                 return err;
2664         }
2665
2666         snd_m3_enable_ints(chip);
2667         snd_m3_assp_continue(chip);
2668
2669         snd_card_set_dev(card, &pci->dev);
2670
2671         *chip_ret = chip;
2672
2673         return 0;
2674 }
2675
2676 /*
2677  */
2678 static int __devinit
2679 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2680 {
2681         static int dev;
2682         snd_card_t *card;
2683         m3_t *chip;
2684         int err;
2685
2686         /* don't pick up modems */
2687         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2688                 return -ENODEV;
2689
2690         if (dev >= SNDRV_CARDS)
2691                 return -ENODEV;
2692         if (!enable[dev]) {
2693                 dev++;
2694                 return -ENOENT;
2695         }
2696
2697         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2698         if (card == NULL)
2699                 return -ENOMEM;
2700
2701         switch (pci->device) {
2702         case PCI_DEVICE_ID_ESS_ALLEGRO:
2703         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2704                 strcpy(card->driver, "Allegro");
2705                 break;
2706         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2707         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2708                 strcpy(card->driver, "Canyon3D-2");
2709                 break;
2710         default:
2711                 strcpy(card->driver, "Maestro3");
2712                 break;
2713         }
2714
2715         if ((err = snd_m3_create(card, pci,
2716                                  external_amp[dev],
2717                                  amp_gpio[dev],
2718                                  &chip)) < 0) {
2719                 snd_card_free(card);
2720                 return err;
2721         }
2722
2723         sprintf(card->shortname, "ESS %s PCI", card->driver);
2724         sprintf(card->longname, "%s at 0x%lx, irq %d",
2725                 card->shortname, chip->iobase, chip->irq);
2726
2727         if ((err = snd_card_register(card)) < 0) {
2728                 snd_card_free(card);
2729                 return err;
2730         }
2731
2732 #if 0 /* TODO: not supported yet */
2733         /* TODO enable midi irq and i/o */
2734         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2735                                   chip->iobase + MPU401_DATA_PORT, 1,
2736                                   chip->irq, 0, &chip->rmidi);
2737         if (err < 0)
2738                 printk(KERN_WARNING "maestro3: no midi support.\n");
2739 #endif
2740
2741         pci_set_drvdata(pci, chip);
2742         dev++;
2743         return 0;
2744 }
2745
2746 static void __devexit snd_m3_remove(struct pci_dev *pci)
2747 {
2748         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return);
2749         if (chip)
2750                 snd_card_free(chip->card);
2751         pci_set_drvdata(pci, NULL);
2752 }
2753
2754 static struct pci_driver driver = {
2755         .name = "Maestro3",
2756         .id_table = snd_m3_ids,
2757         .probe = snd_m3_probe,
2758         .remove = __devexit_p(snd_m3_remove),
2759 #ifdef CONFIG_PM
2760         .suspend = snd_m3_suspend,
2761         .resume = snd_m3_resume,
2762 #endif
2763 };
2764
2765 static int __init alsa_card_m3_init(void)
2766 {
2767         int err;
2768
2769         if ((err = pci_module_init(&driver)) < 0) {
2770 #ifdef MODULE
2771                 printk(KERN_ERR "Maestro3/Allegro soundcard not found or device busy\n");
2772 #endif
2773                 return err;
2774         }
2775         return 0;
2776 }
2777
2778 static void __exit alsa_card_m3_exit(void)
2779 {
2780         pci_unregister_driver(&driver);
2781 }
2782
2783 module_init(alsa_card_m3_init)
2784 module_exit(alsa_card_m3_exit)
2785
2786 #ifndef MODULE
2787
2788 /* format is: snd-maestro3=enable,index,id,external_amp,amp_gpio */
2789
2790 static int __init alsa_card_maestro3_setup(char *str)
2791 {
2792         static unsigned __initdata nr_dev = 0;
2793
2794         if (nr_dev >= SNDRV_CARDS)
2795                 return 0;
2796         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2797                get_option(&str,&index[nr_dev]) == 2 &&
2798                get_id(&str,&id[nr_dev]) == 2 &&
2799                get_option(&str,&external_amp[nr_dev]) == 2 &&
2800                get_option(&str,&amp_gpio[nr_dev]) == 2);
2801         nr_dev++;
2802         return 1;
2803 }
2804
2805 __setup("snd-maestro3=", alsa_card_maestro3_setup);
2806
2807 #endif /* ifndef MODULE */