2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
34 #include <sound/driver.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <sound/core.h>
44 #include <sound/info.h>
45 #include <sound/control.h>
46 #include <sound/pcm.h>
47 #include <sound/mpu401.h>
48 #include <sound/ac97_codec.h>
49 #include <sound/initval.h>
51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
53 MODULE_LICENSE("GPL");
54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57 "{ESS,Allegro-1 PCI},"
58 "{ESS,Canyon3D-2/LE PCI}}");
60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable this soundcard.");
72 module_param_array(external_amp, bool, NULL, 0444);
73 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
74 module_param_array(amp_gpio, int, NULL, 0444);
75 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
77 #define MAX_PLAYBACKS 2
78 #define MAX_CAPTURES 1
79 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
86 /* Allegro PCI configuration registers */
87 #define PCI_LEGACY_AUDIO_CTRL 0x40
88 #define SOUND_BLASTER_ENABLE 0x00000001
89 #define FM_SYNTHESIS_ENABLE 0x00000002
90 #define GAME_PORT_ENABLE 0x00000004
91 #define MPU401_IO_ENABLE 0x00000008
92 #define MPU401_IRQ_ENABLE 0x00000010
93 #define ALIAS_10BIT_IO 0x00000020
94 #define SB_DMA_MASK 0x000000C0
95 #define SB_DMA_0 0x00000040
96 #define SB_DMA_1 0x00000040
97 #define SB_DMA_R 0x00000080
98 #define SB_DMA_3 0x000000C0
99 #define SB_IRQ_MASK 0x00000700
100 #define SB_IRQ_5 0x00000000
101 #define SB_IRQ_7 0x00000100
102 #define SB_IRQ_9 0x00000200
103 #define SB_IRQ_10 0x00000300
104 #define MIDI_IRQ_MASK 0x00003800
105 #define SERIAL_IRQ_ENABLE 0x00004000
106 #define DISABLE_LEGACY 0x00008000
108 #define PCI_ALLEGRO_CONFIG 0x50
109 #define SB_ADDR_240 0x00000004
110 #define MPU_ADDR_MASK 0x00000018
111 #define MPU_ADDR_330 0x00000000
112 #define MPU_ADDR_300 0x00000008
113 #define MPU_ADDR_320 0x00000010
114 #define MPU_ADDR_340 0x00000018
115 #define USE_PCI_TIMING 0x00000040
116 #define POSTED_WRITE_ENABLE 0x00000080
117 #define DMA_POLICY_MASK 0x00000700
118 #define DMA_DDMA 0x00000000
119 #define DMA_TDMA 0x00000100
120 #define DMA_PCPCI 0x00000200
121 #define DMA_WBDMA16 0x00000400
122 #define DMA_WBDMA4 0x00000500
123 #define DMA_WBDMA2 0x00000600
124 #define DMA_WBDMA1 0x00000700
125 #define DMA_SAFE_GUARD 0x00000800
126 #define HI_PERF_GP_ENABLE 0x00001000
127 #define PIC_SNOOP_MODE_0 0x00002000
128 #define PIC_SNOOP_MODE_1 0x00004000
129 #define SOUNDBLASTER_IRQ_MASK 0x00008000
130 #define RING_IN_ENABLE 0x00010000
131 #define SPDIF_TEST_MODE 0x00020000
132 #define CLK_MULT_MODE_SELECT_2 0x00040000
133 #define EEPROM_WRITE_ENABLE 0x00080000
134 #define CODEC_DIR_IN 0x00100000
135 #define HV_BUTTON_FROM_GD 0x00200000
136 #define REDUCED_DEBOUNCE 0x00400000
137 #define HV_CTRL_ENABLE 0x00800000
138 #define SPDIF_ENABLE 0x01000000
139 #define CLK_DIV_SELECT 0x06000000
140 #define CLK_DIV_BY_48 0x00000000
141 #define CLK_DIV_BY_49 0x02000000
142 #define CLK_DIV_BY_50 0x04000000
143 #define CLK_DIV_RESERVED 0x06000000
144 #define PM_CTRL_ENABLE 0x08000000
145 #define CLK_MULT_MODE_SELECT 0x30000000
146 #define CLK_MULT_MODE_SHIFT 28
147 #define CLK_MULT_MODE_0 0x00000000
148 #define CLK_MULT_MODE_1 0x10000000
149 #define CLK_MULT_MODE_2 0x20000000
150 #define CLK_MULT_MODE_3 0x30000000
151 #define INT_CLK_SELECT 0x40000000
152 #define INT_CLK_MULT_RESET 0x80000000
155 #define INT_CLK_SRC_NOT_PCI 0x00100000
156 #define INT_CLK_MULT_ENABLE 0x80000000
158 #define PCI_ACPI_CONTROL 0x54
159 #define PCI_ACPI_D0 0x00000000
160 #define PCI_ACPI_D1 0xB4F70000
161 #define PCI_ACPI_D2 0xB4F7B4F7
163 #define PCI_USER_CONFIG 0x58
164 #define EXT_PCI_MASTER_ENABLE 0x00000001
165 #define SPDIF_OUT_SELECT 0x00000002
166 #define TEST_PIN_DIR_CTRL 0x00000004
167 #define AC97_CODEC_TEST 0x00000020
168 #define TRI_STATE_BUFFER 0x00000080
169 #define IN_CLK_12MHZ_SELECT 0x00000100
170 #define MULTI_FUNC_DISABLE 0x00000200
171 #define EXT_MASTER_PAIR_SEL 0x00000400
172 #define PCI_MASTER_SUPPORT 0x00000800
173 #define STOP_CLOCK_ENABLE 0x00001000
174 #define EAPD_DRIVE_ENABLE 0x00002000
175 #define REQ_TRI_STATE_ENABLE 0x00004000
176 #define REQ_LOW_ENABLE 0x00008000
177 #define MIDI_1_ENABLE 0x00010000
178 #define MIDI_2_ENABLE 0x00020000
179 #define SB_AUDIO_SYNC 0x00040000
180 #define HV_CTRL_TEST 0x00100000
181 #define SOUNDBLASTER_TEST 0x00400000
183 #define PCI_USER_CONFIG_C 0x5C
185 #define PCI_DDMA_CTRL 0x60
186 #define DDMA_ENABLE 0x00000001
189 /* Allegro registers */
190 #define HOST_INT_CTRL 0x18
191 #define SB_INT_ENABLE 0x0001
192 #define MPU401_INT_ENABLE 0x0002
193 #define ASSP_INT_ENABLE 0x0010
194 #define RING_INT_ENABLE 0x0020
195 #define HV_INT_ENABLE 0x0040
196 #define CLKRUN_GEN_ENABLE 0x0100
197 #define HV_CTRL_TO_PME 0x0400
198 #define SOFTWARE_RESET_ENABLE 0x8000
201 * should be using the above defines, probably.
203 #define REGB_ENABLE_RESET 0x01
204 #define REGB_STOP_CLOCK 0x10
206 #define HOST_INT_STATUS 0x1A
207 #define SB_INT_PENDING 0x01
208 #define MPU401_INT_PENDING 0x02
209 #define ASSP_INT_PENDING 0x10
210 #define RING_INT_PENDING 0x20
211 #define HV_INT_PENDING 0x40
213 #define HARDWARE_VOL_CTRL 0x1B
214 #define SHADOW_MIX_REG_VOICE 0x1C
215 #define HW_VOL_COUNTER_VOICE 0x1D
216 #define SHADOW_MIX_REG_MASTER 0x1E
217 #define HW_VOL_COUNTER_MASTER 0x1F
219 #define CODEC_COMMAND 0x30
220 #define CODEC_READ_B 0x80
222 #define CODEC_STATUS 0x30
223 #define CODEC_BUSY_B 0x01
225 #define CODEC_DATA 0x32
227 #define RING_BUS_CTRL_A 0x36
228 #define RAC_PME_ENABLE 0x0100
229 #define RAC_SDFS_ENABLE 0x0200
230 #define LAC_PME_ENABLE 0x0400
231 #define LAC_SDFS_ENABLE 0x0800
232 #define SERIAL_AC_LINK_ENABLE 0x1000
233 #define IO_SRAM_ENABLE 0x2000
234 #define IIS_INPUT_ENABLE 0x8000
236 #define RING_BUS_CTRL_B 0x38
237 #define SECOND_CODEC_ID_MASK 0x0003
238 #define SPDIF_FUNC_ENABLE 0x0010
239 #define SECOND_AC_ENABLE 0x0020
240 #define SB_MODULE_INTF_ENABLE 0x0040
241 #define SSPE_ENABLE 0x0040
242 #define M3I_DOCK_ENABLE 0x0080
244 #define SDO_OUT_DEST_CTRL 0x3A
245 #define COMMAND_ADDR_OUT 0x0003
246 #define PCM_LR_OUT_LOCAL 0x0000
247 #define PCM_LR_OUT_REMOTE 0x0004
248 #define PCM_LR_OUT_MUTE 0x0008
249 #define PCM_LR_OUT_BOTH 0x000C
250 #define LINE1_DAC_OUT_LOCAL 0x0000
251 #define LINE1_DAC_OUT_REMOTE 0x0010
252 #define LINE1_DAC_OUT_MUTE 0x0020
253 #define LINE1_DAC_OUT_BOTH 0x0030
254 #define PCM_CLS_OUT_LOCAL 0x0000
255 #define PCM_CLS_OUT_REMOTE 0x0040
256 #define PCM_CLS_OUT_MUTE 0x0080
257 #define PCM_CLS_OUT_BOTH 0x00C0
258 #define PCM_RLF_OUT_LOCAL 0x0000
259 #define PCM_RLF_OUT_REMOTE 0x0100
260 #define PCM_RLF_OUT_MUTE 0x0200
261 #define PCM_RLF_OUT_BOTH 0x0300
262 #define LINE2_DAC_OUT_LOCAL 0x0000
263 #define LINE2_DAC_OUT_REMOTE 0x0400
264 #define LINE2_DAC_OUT_MUTE 0x0800
265 #define LINE2_DAC_OUT_BOTH 0x0C00
266 #define HANDSET_OUT_LOCAL 0x0000
267 #define HANDSET_OUT_REMOTE 0x1000
268 #define HANDSET_OUT_MUTE 0x2000
269 #define HANDSET_OUT_BOTH 0x3000
270 #define IO_CTRL_OUT_LOCAL 0x0000
271 #define IO_CTRL_OUT_REMOTE 0x4000
272 #define IO_CTRL_OUT_MUTE 0x8000
273 #define IO_CTRL_OUT_BOTH 0xC000
275 #define SDO_IN_DEST_CTRL 0x3C
276 #define STATUS_ADDR_IN 0x0003
277 #define PCM_LR_IN_LOCAL 0x0000
278 #define PCM_LR_IN_REMOTE 0x0004
279 #define PCM_LR_RESERVED 0x0008
280 #define PCM_LR_IN_BOTH 0x000C
281 #define LINE1_ADC_IN_LOCAL 0x0000
282 #define LINE1_ADC_IN_REMOTE 0x0010
283 #define LINE1_ADC_IN_MUTE 0x0020
284 #define MIC_ADC_IN_LOCAL 0x0000
285 #define MIC_ADC_IN_REMOTE 0x0040
286 #define MIC_ADC_IN_MUTE 0x0080
287 #define LINE2_DAC_IN_LOCAL 0x0000
288 #define LINE2_DAC_IN_REMOTE 0x0400
289 #define LINE2_DAC_IN_MUTE 0x0800
290 #define HANDSET_IN_LOCAL 0x0000
291 #define HANDSET_IN_REMOTE 0x1000
292 #define HANDSET_IN_MUTE 0x2000
293 #define IO_STATUS_IN_LOCAL 0x0000
294 #define IO_STATUS_IN_REMOTE 0x4000
296 #define SPDIF_IN_CTRL 0x3E
297 #define SPDIF_IN_ENABLE 0x0001
299 #define GPIO_DATA 0x60
300 #define GPIO_DATA_MASK 0x0FFF
301 #define GPIO_HV_STATUS 0x3000
302 #define GPIO_PME_STATUS 0x4000
304 #define GPIO_MASK 0x64
305 #define GPIO_DIRECTION 0x68
306 #define GPO_PRIMARY_AC97 0x0001
307 #define GPI_LINEOUT_SENSE 0x0004
308 #define GPO_SECONDARY_AC97 0x0008
309 #define GPI_VOL_DOWN 0x0010
310 #define GPI_VOL_UP 0x0020
311 #define GPI_IIS_CLK 0x0040
312 #define GPI_IIS_LRCLK 0x0080
313 #define GPI_IIS_DATA 0x0100
314 #define GPI_DOCKING_STATUS 0x0100
315 #define GPI_HEADPHONE_SENSE 0x0200
316 #define GPO_EXT_AMP_SHUTDOWN 0x1000
318 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
319 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
322 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
324 #define ASSP_INDEX_PORT 0x80
325 #define ASSP_MEMORY_PORT 0x82
326 #define ASSP_DATA_PORT 0x84
328 #define MPU401_DATA_PORT 0x98
329 #define MPU401_STATUS_PORT 0x99
331 #define CLK_MULT_DATA_PORT 0x9C
333 #define ASSP_CONTROL_A 0xA2
334 #define ASSP_0_WS_ENABLE 0x01
335 #define ASSP_CTRL_A_RESERVED1 0x02
336 #define ASSP_CTRL_A_RESERVED2 0x04
337 #define ASSP_CLK_49MHZ_SELECT 0x08
338 #define FAST_PLU_ENABLE 0x10
339 #define ASSP_CTRL_A_RESERVED3 0x20
340 #define DSP_CLK_36MHZ_SELECT 0x40
342 #define ASSP_CONTROL_B 0xA4
343 #define RESET_ASSP 0x00
344 #define RUN_ASSP 0x01
345 #define ENABLE_ASSP_CLOCK 0x00
346 #define STOP_ASSP_CLOCK 0x10
347 #define RESET_TOGGLE 0x40
349 #define ASSP_CONTROL_C 0xA6
350 #define ASSP_HOST_INT_ENABLE 0x01
351 #define FM_ADDR_REMAP_DISABLE 0x02
352 #define HOST_WRITE_PORT_ENABLE 0x08
354 #define ASSP_HOST_INT_STATUS 0xAC
355 #define DSP2HOST_REQ_PIORECORD 0x01
356 #define DSP2HOST_REQ_I2SRATE 0x02
357 #define DSP2HOST_REQ_TIMER 0x04
360 /* XXX fix this crap up */
361 /*#define AC97_RESET 0x00*/
363 #define AC97_VOL_MUTE_B 0x8000
364 #define AC97_VOL_M 0x1F
365 #define AC97_LEFT_VOL_S 8
367 #define AC97_MASTER_VOL 0x02
368 #define AC97_LINE_LEVEL_VOL 0x04
369 #define AC97_MASTER_MONO_VOL 0x06
370 #define AC97_PC_BEEP_VOL 0x0A
371 #define AC97_PC_BEEP_VOL_M 0x0F
372 #define AC97_SROUND_MASTER_VOL 0x38
373 #define AC97_PC_BEEP_VOL_S 1
375 /*#define AC97_PHONE_VOL 0x0C
376 #define AC97_MIC_VOL 0x0E*/
377 #define AC97_MIC_20DB_ENABLE 0x40
379 /*#define AC97_LINEIN_VOL 0x10
380 #define AC97_CD_VOL 0x12
381 #define AC97_VIDEO_VOL 0x14
382 #define AC97_AUX_VOL 0x16*/
383 #define AC97_PCM_OUT_VOL 0x18
384 /*#define AC97_RECORD_SELECT 0x1A*/
385 #define AC97_RECORD_MIC 0x00
386 #define AC97_RECORD_CD 0x01
387 #define AC97_RECORD_VIDEO 0x02
388 #define AC97_RECORD_AUX 0x03
389 #define AC97_RECORD_MONO_MUX 0x02
390 #define AC97_RECORD_DIGITAL 0x03
391 #define AC97_RECORD_LINE 0x04
392 #define AC97_RECORD_STEREO 0x05
393 #define AC97_RECORD_MONO 0x06
394 #define AC97_RECORD_PHONE 0x07
396 /*#define AC97_RECORD_GAIN 0x1C*/
397 #define AC97_RECORD_VOL_M 0x0F
399 /*#define AC97_GENERAL_PURPOSE 0x20*/
400 #define AC97_POWER_DOWN_CTRL 0x26
401 #define AC97_ADC_READY 0x0001
402 #define AC97_DAC_READY 0x0002
403 #define AC97_ANALOG_READY 0x0004
404 #define AC97_VREF_ON 0x0008
405 #define AC97_PR0 0x0100
406 #define AC97_PR1 0x0200
407 #define AC97_PR2 0x0400
408 #define AC97_PR3 0x0800
409 #define AC97_PR4 0x1000
411 #define AC97_RESERVED1 0x28
413 #define AC97_VENDOR_TEST 0x5A
415 #define AC97_CLOCK_DELAY 0x5C
416 #define AC97_LINEOUT_MUX_SEL 0x0001
417 #define AC97_MONO_MUX_SEL 0x0002
418 #define AC97_CLOCK_DELAY_SEL 0x1F
419 #define AC97_DAC_CDS_SHIFT 6
420 #define AC97_ADC_CDS_SHIFT 11
422 #define AC97_MULTI_CHANNEL_SEL 0x74
424 /*#define AC97_VENDOR_ID1 0x7C
425 #define AC97_VENDOR_ID2 0x7E*/
430 #define DSP_PORT_TIMER_COUNT 0x06
432 #define DSP_PORT_MEMORY_INDEX 0x80
434 #define DSP_PORT_MEMORY_TYPE 0x82
435 #define MEMTYPE_INTERNAL_CODE 0x0002
436 #define MEMTYPE_INTERNAL_DATA 0x0003
437 #define MEMTYPE_MASK 0x0003
439 #define DSP_PORT_MEMORY_DATA 0x84
441 #define DSP_PORT_CONTROL_REG_A 0xA2
442 #define DSP_PORT_CONTROL_REG_B 0xA4
443 #define DSP_PORT_CONTROL_REG_C 0xA6
445 #define REV_A_CODE_MEMORY_BEGIN 0x0000
446 #define REV_A_CODE_MEMORY_END 0x0FFF
447 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
448 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
450 #define REV_B_CODE_MEMORY_BEGIN 0x0000
451 #define REV_B_CODE_MEMORY_END 0x0BFF
452 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
453 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
455 #define REV_A_DATA_MEMORY_BEGIN 0x1000
456 #define REV_A_DATA_MEMORY_END 0x2FFF
457 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
458 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
460 #define REV_B_DATA_MEMORY_BEGIN 0x1000
461 #define REV_B_DATA_MEMORY_END 0x2BFF
462 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
463 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
466 #define NUM_UNITS_KERNEL_CODE 16
467 #define NUM_UNITS_KERNEL_DATA 2
469 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
470 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
476 #define DP_SHIFT_COUNT 7
478 #define KDATA_BASE_ADDR 0x1000
479 #define KDATA_BASE_ADDR2 0x1080
481 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
482 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
483 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
484 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
485 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
486 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
487 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
488 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
489 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
491 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
492 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
494 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
495 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
496 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
497 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
498 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
499 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
500 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
501 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
502 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
503 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
505 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
506 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
508 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
509 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
511 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
512 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
514 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
515 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
516 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
518 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
519 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
520 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
521 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
522 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
524 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
525 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
526 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
528 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
529 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
530 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
532 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
533 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
534 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
535 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
536 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
537 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
538 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
539 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
540 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
541 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
543 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
544 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
545 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
547 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
548 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
550 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
551 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
552 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
554 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
555 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
556 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
557 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
558 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
559 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
561 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
562 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
563 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
564 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
565 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
566 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
568 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
569 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
570 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
571 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
572 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
573 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
575 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
576 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
577 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
578 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
580 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
581 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
583 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
584 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
586 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
587 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
588 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
589 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
590 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
592 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
593 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
595 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
596 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
597 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
599 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
600 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
602 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
604 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
605 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
606 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
607 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
608 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
609 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
610 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
611 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
612 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
613 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
614 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
615 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
617 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
618 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
619 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
620 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
622 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
623 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
625 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
626 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
627 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
628 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
630 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
631 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
632 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
633 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
634 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
637 * second 'segment' (?) reserved for mixer
641 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
642 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
643 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
644 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
645 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
646 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
647 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
648 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
649 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
650 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
651 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
652 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
653 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
654 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
655 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
656 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
658 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
659 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
660 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
661 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
662 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
663 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
664 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
665 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
666 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
667 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
668 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
670 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
671 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
672 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
673 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
674 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
675 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
677 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
678 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
679 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
680 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
683 * client data area offsets
685 #define CDATA_INSTANCE_READY 0x00
687 #define CDATA_HOST_SRC_ADDRL 0x01
688 #define CDATA_HOST_SRC_ADDRH 0x02
689 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
690 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
691 #define CDATA_HOST_SRC_CURRENTL 0x05
692 #define CDATA_HOST_SRC_CURRENTH 0x06
694 #define CDATA_IN_BUF_CONNECT 0x07
695 #define CDATA_OUT_BUF_CONNECT 0x08
697 #define CDATA_IN_BUF_BEGIN 0x09
698 #define CDATA_IN_BUF_END_PLUS_1 0x0A
699 #define CDATA_IN_BUF_HEAD 0x0B
700 #define CDATA_IN_BUF_TAIL 0x0C
701 #define CDATA_OUT_BUF_BEGIN 0x0D
702 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
703 #define CDATA_OUT_BUF_HEAD 0x0F
704 #define CDATA_OUT_BUF_TAIL 0x10
706 #define CDATA_DMA_CONTROL 0x11
707 #define CDATA_RESERVED 0x12
709 #define CDATA_FREQUENCY 0x13
710 #define CDATA_LEFT_VOLUME 0x14
711 #define CDATA_RIGHT_VOLUME 0x15
712 #define CDATA_LEFT_SUR_VOL 0x16
713 #define CDATA_RIGHT_SUR_VOL 0x17
715 #define CDATA_HEADER_LEN 0x18
717 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
718 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
719 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
720 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
721 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
722 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
723 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
724 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
726 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
727 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
728 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
729 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
730 #define MINISRC_BIQUAD_STAGE 2
731 #define MINISRC_COEF_LOC 0x175
733 #define DMACONTROL_BLOCK_MASK 0x000F
734 #define DMAC_BLOCK0_SELECTOR 0x0000
735 #define DMAC_BLOCK1_SELECTOR 0x0001
736 #define DMAC_BLOCK2_SELECTOR 0x0002
737 #define DMAC_BLOCK3_SELECTOR 0x0003
738 #define DMAC_BLOCK4_SELECTOR 0x0004
739 #define DMAC_BLOCK5_SELECTOR 0x0005
740 #define DMAC_BLOCK6_SELECTOR 0x0006
741 #define DMAC_BLOCK7_SELECTOR 0x0007
742 #define DMAC_BLOCK8_SELECTOR 0x0008
743 #define DMAC_BLOCK9_SELECTOR 0x0009
744 #define DMAC_BLOCKA_SELECTOR 0x000A
745 #define DMAC_BLOCKB_SELECTOR 0x000B
746 #define DMAC_BLOCKC_SELECTOR 0x000C
747 #define DMAC_BLOCKD_SELECTOR 0x000D
748 #define DMAC_BLOCKE_SELECTOR 0x000E
749 #define DMAC_BLOCKF_SELECTOR 0x000F
750 #define DMACONTROL_PAGE_MASK 0x00F0
751 #define DMAC_PAGE0_SELECTOR 0x0030
752 #define DMAC_PAGE1_SELECTOR 0x0020
753 #define DMAC_PAGE2_SELECTOR 0x0010
754 #define DMAC_PAGE3_SELECTOR 0x0000
755 #define DMACONTROL_AUTOREPEAT 0x1000
756 #define DMACONTROL_STOPPED 0x2000
757 #define DMACONTROL_DIRECTION 0x0100
760 * an arbitrary volume we set the internal
761 * volume settings to so that the ac97 volume
762 * range is a little less insane. 0x7fff is
765 #define ARB_VOLUME ( 0x6800 )
770 typedef struct snd_m3_dma m3_dma_t;
771 typedef struct snd_m3 m3_t;
775 const char *name; /* device name */
776 u16 vendor, device; /* subsystem ids */
777 int amp_gpio; /* gpio pin # for external amp, -1 = default */
778 int irda_workaround; /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
779 (e.g. for IrDA on Dell Inspirons) */
792 snd_pcm_substream_t *substream;
794 struct assp_instance {
795 unsigned short code, data;
801 unsigned long buffer_addr;
808 struct m3_list *index_list[3];
812 struct list_head list;
820 unsigned long iobase;
823 int allegro_flag : 1;
830 struct m3_quirk *quirk;
835 struct m3_list msrc_list;
836 struct m3_list mixer_list;
837 struct m3_list adc1_list;
838 struct m3_list dma_list;
840 /* for storing reset state..*/
847 snd_rawmidi_t *rmidi;
851 m3_dma_t *substreams;
864 #ifndef PCI_VENDOR_ID_ESS
865 #define PCI_VENDOR_ID_ESS 0x125D
867 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
868 #define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988
870 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
871 #define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989
873 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
874 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990
876 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
877 #define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992
879 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
880 #define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998
882 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
883 #define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999
885 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
886 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a
888 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
889 #define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b
892 static struct pci_device_id snd_m3_ids[] = {
893 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
894 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
895 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
896 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
897 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
898 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
899 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
900 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
901 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
902 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
903 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
904 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
905 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
906 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
907 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
908 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
912 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
914 static struct m3_quirk m3_quirk_list[] = {
915 /* panasonic CF-28 "toughbook" */
917 .name = "Panasonic CF-28",
922 /* panasonic CF-72 "toughbook" */
924 .name = "Panasonic CF-72",
929 /* Dell Inspiron 4000 */
931 .name = "Dell Inspiron 4000",
935 .irda_workaround = 1,
937 /* Dell Inspiron 8000 */
939 .name = "Dell Inspiron 8000",
943 .irda_workaround = 1,
945 /* Dell Inspiron 8100 */
947 .name = "Dell Inspiron 8100",
951 .irda_workaround = 1,
955 .name = "NEC LM800J/7",
969 #define big_mdelay(msec) do {\
970 set_current_state(TASK_UNINTERRUPTIBLE);\
971 schedule_timeout(((msec) * HZ) / 1000);\
974 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
976 outw(value, chip->iobase + reg);
979 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
981 return inw(chip->iobase + reg);
984 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
986 outb(value, chip->iobase + reg);
989 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
991 return inb(chip->iobase + reg);
995 * access 16bit words to the code or data regions of the dsp's memory.
996 * index addresses 16bit words.
998 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1000 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1001 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1002 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1005 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1007 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1008 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1009 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1012 static void snd_m3_assp_halt(m3_t *chip)
1014 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1016 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1019 static void snd_m3_assp_continue(m3_t *chip)
1021 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1026 * This makes me sad. the maestro3 has lists
1027 * internally that must be packed.. 0 terminates,
1028 * apparently, or maybe all unused entries have
1029 * to be 0, the lists have static lengths set
1030 * by the binary code images.
1033 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1035 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1036 list->mem_addr + list->curlen,
1038 return list->curlen++;
1041 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1044 int lastindex = list->curlen - 1;
1046 if (index != lastindex) {
1047 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1048 list->mem_addr + lastindex);
1049 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1050 list->mem_addr + index,
1054 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1055 list->mem_addr + lastindex,
1061 static void snd_m3_inc_timer_users(m3_t *chip)
1063 chip->timer_users++;
1064 if (chip->timer_users != 1)
1067 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1068 KDATA_TIMER_COUNT_RELOAD,
1071 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1072 KDATA_TIMER_COUNT_CURRENT,
1076 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1080 static void snd_m3_dec_timer_users(m3_t *chip)
1082 chip->timer_users--;
1083 if (chip->timer_users > 0)
1086 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1087 KDATA_TIMER_COUNT_RELOAD,
1090 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1091 KDATA_TIMER_COUNT_CURRENT,
1095 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1103 /* spinlock held! */
1104 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1109 snd_m3_inc_timer_users(chip);
1110 switch (subs->stream) {
1111 case SNDRV_PCM_STREAM_PLAYBACK:
1112 chip->dacs_active++;
1113 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1114 s->inst.data + CDATA_INSTANCE_READY, 1);
1115 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1116 KDATA_MIXER_TASK_NUMBER,
1119 case SNDRV_PCM_STREAM_CAPTURE:
1120 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1121 KDATA_ADC1_REQUEST, 1);
1122 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1123 s->inst.data + CDATA_INSTANCE_READY, 1);
1129 /* spinlock held! */
1130 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1135 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1136 s->inst.data + CDATA_INSTANCE_READY, 0);
1137 snd_m3_dec_timer_users(chip);
1138 switch (subs->stream) {
1139 case SNDRV_PCM_STREAM_PLAYBACK:
1140 chip->dacs_active--;
1141 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142 KDATA_MIXER_TASK_NUMBER,
1145 case SNDRV_PCM_STREAM_CAPTURE:
1146 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1147 KDATA_ADC1_REQUEST, 0);
1154 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1156 m3_t *chip = snd_pcm_substream_chip(subs);
1157 m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1160 snd_assert(s != NULL, return -ENXIO);
1162 spin_lock(&chip->reg_lock);
1164 case SNDRV_PCM_TRIGGER_START:
1165 case SNDRV_PCM_TRIGGER_RESUME:
1170 err = snd_m3_pcm_start(chip, s, subs);
1173 case SNDRV_PCM_TRIGGER_STOP:
1174 case SNDRV_PCM_TRIGGER_SUSPEND:
1176 err = 0; /* should return error? */
1179 err = snd_m3_pcm_stop(chip, s, subs);
1183 spin_unlock(&chip->reg_lock);
1191 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1193 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1194 snd_pcm_runtime_t *runtime = subs->runtime;
1196 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1197 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1198 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1200 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1201 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1203 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1204 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1206 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1207 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1211 #define LO(x) ((x) & 0xffff)
1212 #define HI(x) LO((x) >> 16)
1214 /* host dma buffer pointers */
1215 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1216 s->inst.data + CDATA_HOST_SRC_ADDRL,
1217 LO(s->buffer_addr));
1219 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1220 s->inst.data + CDATA_HOST_SRC_ADDRH,
1221 HI(s->buffer_addr));
1223 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1224 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1225 LO(s->buffer_addr + s->dma_size));
1227 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1228 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1229 HI(s->buffer_addr + s->dma_size));
1231 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1232 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1233 LO(s->buffer_addr));
1235 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1236 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1237 HI(s->buffer_addr));
1243 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1244 s->inst.data + CDATA_IN_BUF_BEGIN,
1247 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1248 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1249 dsp_in_buffer + (dsp_in_size / 2));
1251 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1252 s->inst.data + CDATA_IN_BUF_HEAD,
1255 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1256 s->inst.data + CDATA_IN_BUF_TAIL,
1259 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1260 s->inst.data + CDATA_OUT_BUF_BEGIN,
1263 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1264 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1265 dsp_out_buffer + (dsp_out_size / 2));
1267 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1268 s->inst.data + CDATA_OUT_BUF_HEAD,
1271 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1272 s->inst.data + CDATA_OUT_BUF_TAIL,
1276 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1281 * put us in the lists if we're not already there
1283 if (! s->in_lists) {
1284 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1285 s->inst.data >> DP_SHIFT_COUNT);
1286 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1287 s->inst.data >> DP_SHIFT_COUNT);
1288 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1289 s->inst.data >> DP_SHIFT_COUNT);
1293 /* write to 'mono' word */
1294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1295 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1296 runtime->channels == 2 ? 0 : 1);
1297 /* write to '8bit' word */
1298 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1299 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1300 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1302 /* set up dac/adc rate */
1303 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1307 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1308 s->inst.data + CDATA_FREQUENCY,
1313 static struct play_vals {
1316 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1317 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1318 {SRC3_DIRECTION_OFFSET, 0} ,
1319 /* +1, +2 are stereo/16 bit */
1320 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1321 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1322 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1323 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1324 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1325 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1326 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1327 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1328 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1329 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1330 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1331 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1332 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1333 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1334 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1335 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1336 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1340 /* the mode passed should be already shifted and masked */
1342 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1347 * some per client initializers
1350 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1351 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1352 s->inst.data + 40 + 8);
1354 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1355 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1356 s->inst.code + MINISRC_COEF_LOC);
1358 /* enable or disable low pass filter? */
1359 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1360 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1361 subs->runtime->rate > 45000 ? 0xff : 0);
1363 /* tell it which way dma is going? */
1364 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1365 s->inst.data + CDATA_DMA_CONTROL,
1366 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1369 * set an armload of static initializers
1371 for (i = 0; i < ARRAY_SIZE(pv); i++)
1372 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1373 s->inst.data + pv[i].addr, pv[i].val);
1377 * Native record driver
1379 static struct rec_vals {
1382 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1383 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1384 {SRC3_DIRECTION_OFFSET, 1} ,
1385 /* +1, +2 are stereo/16 bit */
1386 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1387 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1388 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1389 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1390 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1391 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1392 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1393 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1394 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1395 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1396 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1397 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1398 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1399 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1400 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1401 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1402 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1403 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1404 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1408 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1413 * some per client initializers
1416 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1417 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1418 s->inst.data + 40 + 8);
1420 /* tell it which way dma is going? */
1421 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1422 s->inst.data + CDATA_DMA_CONTROL,
1423 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1424 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1427 * set an armload of static initializers
1429 for (i = 0; i < ARRAY_SIZE(rv); i++)
1430 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1431 s->inst.data + rv[i].addr, rv[i].val);
1434 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1435 snd_pcm_hw_params_t * hw_params)
1437 m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1440 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1442 /* set buffer address */
1443 s->buffer_addr = substream->runtime->dma_addr;
1444 if (s->buffer_addr & 0x3) {
1445 snd_printk("oh my, not aligned\n");
1446 s->buffer_addr = s->buffer_addr & ~0x3;
1451 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1455 if (substream->runtime->private_data == NULL)
1457 s = (m3_dma_t*) substream->runtime->private_data;
1458 snd_pcm_lib_free_pages(substream);
1464 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1466 m3_t *chip = snd_pcm_substream_chip(subs);
1467 snd_pcm_runtime_t *runtime = subs->runtime;
1468 m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1470 snd_assert(s != NULL, return -ENXIO);
1472 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1473 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1475 if (runtime->rate > 48000 ||
1476 runtime->rate < 8000)
1479 spin_lock_irq(&chip->reg_lock);
1481 snd_m3_pcm_setup1(chip, s, subs);
1483 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1484 snd_m3_playback_setup(chip, s, subs);
1486 snd_m3_capture_setup(chip, s, subs);
1488 snd_m3_pcm_setup2(chip, s, runtime);
1490 spin_unlock_irq(&chip->reg_lock);
1496 * get current pointer
1499 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1506 * try and get a valid answer
1509 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1510 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1512 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1513 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1515 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1516 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1519 addr = lo | ((u32)hi<<16);
1520 return (unsigned int)(addr - s->buffer_addr);
1523 static snd_pcm_uframes_t
1524 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1526 m3_t *chip = snd_pcm_substream_chip(subs);
1528 m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1529 snd_assert(s != NULL, return 0);
1531 spin_lock(&chip->reg_lock);
1532 ptr = snd_m3_get_pointer(chip, s, subs);
1533 spin_unlock(&chip->reg_lock);
1534 return bytes_to_frames(subs->runtime, ptr);
1538 /* update pointer */
1539 /* spinlock held! */
1540 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1542 snd_pcm_substream_t *subs = s->substream;
1549 hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1550 diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1553 if (s->count >= (signed)s->period_size) {
1554 s->count %= s->period_size;
1555 spin_unlock(&chip->reg_lock);
1556 snd_pcm_period_elapsed(subs);
1557 spin_lock(&chip->reg_lock);
1562 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1564 m3_t *chip = dev_id;
1568 status = inb(chip->iobase + HOST_INT_STATUS);
1574 * ack an assp int if its running
1575 * and has an int pending
1577 if (status & ASSP_INT_PENDING) {
1578 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1579 if (!(ctl & STOP_ASSP_CLOCK)) {
1580 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1581 if (ctl & DSP2HOST_REQ_TIMER) {
1582 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1583 /* update adc/dac info if it was a timer int */
1584 spin_lock(&chip->reg_lock);
1585 for (i = 0; i < chip->num_substreams; i++) {
1586 m3_dma_t *s = &chip->substreams[i];
1588 snd_m3_update_ptr(chip, s);
1590 spin_unlock(&chip->reg_lock);
1595 #if 0 /* TODO: not supported yet */
1596 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1597 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1601 snd_m3_outw(chip, HOST_INT_STATUS, status);
1610 static snd_pcm_hardware_t snd_m3_playback =
1612 .info = (SNDRV_PCM_INFO_MMAP |
1613 SNDRV_PCM_INFO_INTERLEAVED |
1614 SNDRV_PCM_INFO_MMAP_VALID |
1615 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1616 /*SNDRV_PCM_INFO_PAUSE |*/
1617 SNDRV_PCM_INFO_RESUME),
1618 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1619 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1624 .buffer_bytes_max = (512*1024),
1625 .period_bytes_min = 64,
1626 .period_bytes_max = (512*1024),
1628 .periods_max = 1024,
1631 static snd_pcm_hardware_t snd_m3_capture =
1633 .info = (SNDRV_PCM_INFO_MMAP |
1634 SNDRV_PCM_INFO_INTERLEAVED |
1635 SNDRV_PCM_INFO_MMAP_VALID |
1636 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1637 /*SNDRV_PCM_INFO_PAUSE |*/
1638 SNDRV_PCM_INFO_RESUME),
1639 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1640 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1645 .buffer_bytes_max = (512*1024),
1646 .period_bytes_min = 64,
1647 .period_bytes_max = (512*1024),
1649 .periods_max = 1024,
1657 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1662 spin_lock_irq(&chip->reg_lock);
1663 for (i = 0; i < chip->num_substreams; i++) {
1664 s = &chip->substreams[i];
1668 spin_unlock_irq(&chip->reg_lock);
1673 spin_unlock_irq(&chip->reg_lock);
1675 subs->runtime->private_data = s;
1676 s->substream = subs;
1678 /* set list owners */
1679 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1680 s->index_list[0] = &chip->mixer_list;
1682 s->index_list[0] = &chip->adc1_list;
1683 s->index_list[1] = &chip->msrc_list;
1684 s->index_list[2] = &chip->dma_list;
1690 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1692 m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1695 return; /* not opened properly */
1697 spin_lock_irq(&chip->reg_lock);
1698 if (s->substream && s->running)
1699 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1701 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1702 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1703 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1708 spin_unlock_irq(&chip->reg_lock);
1712 snd_m3_playback_open(snd_pcm_substream_t *subs)
1714 m3_t *chip = snd_pcm_substream_chip(subs);
1715 snd_pcm_runtime_t *runtime = subs->runtime;
1718 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1721 runtime->hw = snd_m3_playback;
1722 snd_pcm_set_sync(subs);
1728 snd_m3_playback_close(snd_pcm_substream_t *subs)
1730 m3_t *chip = snd_pcm_substream_chip(subs);
1732 snd_m3_substream_close(chip, subs);
1737 snd_m3_capture_open(snd_pcm_substream_t *subs)
1739 m3_t *chip = snd_pcm_substream_chip(subs);
1740 snd_pcm_runtime_t *runtime = subs->runtime;
1743 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1746 runtime->hw = snd_m3_capture;
1747 snd_pcm_set_sync(subs);
1753 snd_m3_capture_close(snd_pcm_substream_t *subs)
1755 m3_t *chip = snd_pcm_substream_chip(subs);
1757 snd_m3_substream_close(chip, subs);
1762 * create pcm instance
1765 static snd_pcm_ops_t snd_m3_playback_ops = {
1766 .open = snd_m3_playback_open,
1767 .close = snd_m3_playback_close,
1768 .ioctl = snd_pcm_lib_ioctl,
1769 .hw_params = snd_m3_pcm_hw_params,
1770 .hw_free = snd_m3_pcm_hw_free,
1771 .prepare = snd_m3_pcm_prepare,
1772 .trigger = snd_m3_pcm_trigger,
1773 .pointer = snd_m3_pcm_pointer,
1776 static snd_pcm_ops_t snd_m3_capture_ops = {
1777 .open = snd_m3_capture_open,
1778 .close = snd_m3_capture_close,
1779 .ioctl = snd_pcm_lib_ioctl,
1780 .hw_params = snd_m3_pcm_hw_params,
1781 .hw_free = snd_m3_pcm_hw_free,
1782 .prepare = snd_m3_pcm_prepare,
1783 .trigger = snd_m3_pcm_trigger,
1784 .pointer = snd_m3_pcm_pointer,
1787 static int __devinit
1788 snd_m3_pcm(m3_t * chip, int device)
1793 err = snd_pcm_new(chip->card, chip->card->driver, device,
1794 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1798 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1799 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1801 pcm->private_data = chip;
1802 pcm->info_flags = 0;
1803 strcpy(pcm->name, chip->card->driver);
1806 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1807 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1818 * Wait for the ac97 serial bus to be free.
1819 * return nonzero if the bus is still busy.
1821 static int snd_m3_ac97_wait(m3_t *chip)
1826 if (! (snd_m3_inb(chip, 0x30) & 1))
1830 snd_printk("ac97 serial bus busy\n");
1834 static unsigned short
1835 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1837 m3_t *chip = ac97->private_data;
1839 if (snd_m3_ac97_wait(chip))
1841 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1842 if (snd_m3_ac97_wait(chip))
1844 return snd_m3_inw(chip, CODEC_DATA);
1848 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1850 m3_t *chip = ac97->private_data;
1852 if (snd_m3_ac97_wait(chip))
1854 snd_m3_outw(chip, val, CODEC_DATA);
1855 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1859 static void snd_m3_remote_codec_config(int io, int isremote)
1861 isremote = isremote ? 1 : 0;
1863 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1864 io + RING_BUS_CTRL_B);
1865 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1866 io + SDO_OUT_DEST_CTRL);
1867 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1868 io + SDO_IN_DEST_CTRL);
1872 * hack, returns non zero on err
1874 static int snd_m3_try_read_vendor(m3_t *chip)
1878 if (snd_m3_ac97_wait(chip))
1881 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1883 if (snd_m3_ac97_wait(chip))
1886 ret = snd_m3_inw(chip, 0x32);
1888 return (ret == 0) || (ret == 0xffff);
1891 static void snd_m3_ac97_reset(m3_t *chip)
1894 int delay1 = 0, delay2 = 0, i;
1895 int io = chip->iobase;
1897 if (chip->allegro_flag) {
1899 * the onboard codec on the allegro seems
1900 * to want to wait a very long time before
1901 * coming back to life
1911 for (i = 0; i < 5; i++) {
1912 dir = inw(io + GPIO_DIRECTION);
1913 if (! chip->quirk || ! chip->quirk->irda_workaround)
1914 dir |= 0x10; /* assuming pci bus master? */
1916 snd_m3_remote_codec_config(io, 0);
1918 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1921 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1922 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1923 outw(0, io + GPIO_DATA);
1924 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1926 set_current_state(TASK_UNINTERRUPTIBLE);
1927 schedule_timeout((delay1 * HZ) / 1000);
1929 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1931 /* ok, bring back the ac-link */
1932 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1933 outw(~0, io + GPIO_MASK);
1935 set_current_state(TASK_UNINTERRUPTIBLE);
1936 schedule_timeout((delay2 * HZ) / 1000);
1938 if (! snd_m3_try_read_vendor(chip))
1944 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
1949 /* more gung-ho reset that doesn't
1950 * seem to work anywhere :)
1952 tmp = inw(io + RING_BUS_CTRL_A);
1953 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
1955 outw(tmp, io + RING_BUS_CTRL_A);
1960 static int __devinit snd_m3_mixer(m3_t *chip)
1963 ac97_template_t ac97;
1965 static ac97_bus_ops_t ops = {
1966 .write = snd_m3_ac97_write,
1967 .read = snd_m3_ac97_read,
1970 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1973 memset(&ac97, 0, sizeof(ac97));
1974 ac97.private_data = chip;
1975 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1978 /* seems ac97 PCM needs initialization.. hack hack.. */
1979 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
1980 set_current_state(TASK_UNINTERRUPTIBLE);
1981 schedule_timeout(HZ / 10);
1982 snd_ac97_write(chip->ac97, AC97_PCM, 0);
1992 static u16 assp_kernel_image[] __devinitdata = {
1993 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
1994 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
1995 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
1996 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
1997 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
1998 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
1999 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2000 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2001 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2002 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2003 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2004 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2005 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2006 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2007 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2008 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2009 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2010 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2011 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2012 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2013 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2014 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2015 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2016 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2017 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2018 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2019 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2020 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2021 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2022 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2023 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2024 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2025 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2026 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2027 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2028 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2029 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2030 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2031 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2032 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2033 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2034 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2035 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2036 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2037 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2038 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2039 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2040 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2041 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2042 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2043 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2044 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2045 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2046 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2047 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2048 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2049 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2050 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2051 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2052 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2053 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2054 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2055 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2056 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2057 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2058 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2059 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2060 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2061 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2062 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2063 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2064 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2065 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2066 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2067 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2068 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2069 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2070 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2071 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2076 * Mini sample rate converter code image
2077 * that is to be loaded at 0x400 on the DSP.
2079 static u16 assp_minisrc_image[] __devinitdata = {
2081 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2082 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2083 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2084 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2085 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2086 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2087 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2088 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2089 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2090 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2091 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2092 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2093 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2094 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2095 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2096 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2097 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2098 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2099 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2100 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2101 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2102 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2103 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2104 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2105 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2106 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2107 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2108 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2109 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2110 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2111 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2112 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2121 #define MINISRC_LPF_LEN 10
2122 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2123 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2124 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2127 static void __devinit snd_m3_assp_init(m3_t *chip)
2131 /* zero kernel data */
2132 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2133 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2134 KDATA_BASE_ADDR + i, 0);
2136 /* zero mixer data? */
2137 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2138 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2139 KDATA_BASE_ADDR2 + i, 0);
2141 /* init dma pointer */
2142 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2146 /* write kernel into code memory.. */
2147 for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2148 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2149 REV_B_CODE_MEMORY_BEGIN + i,
2150 assp_kernel_image[i]);
2154 * We only have this one client and we know that 0x400
2155 * is free in our kernel's mem map, so lets just
2156 * drop it there. It seems that the minisrc doesn't
2157 * need vectors, so we won't bother with them..
2159 for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2160 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2162 assp_minisrc_image[i]);
2166 * write the coefficients for the low pass filter?
2168 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2169 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2170 0x400 + MINISRC_COEF_LOC + i,
2174 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2175 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2179 * the minisrc is the only thing on
2182 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2187 * init the mixer number..
2190 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2191 KDATA_MIXER_TASK_NUMBER,0);
2194 * EXTREME KERNEL MASTER VOLUME
2196 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2197 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2198 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2199 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2201 chip->mixer_list.curlen = 0;
2202 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2203 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2204 chip->adc1_list.curlen = 0;
2205 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2206 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2207 chip->dma_list.curlen = 0;
2208 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2209 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2210 chip->msrc_list.curlen = 0;
2211 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2212 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2216 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2218 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2219 MINISRC_IN_BUFFER_SIZE / 2 +
2220 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2224 * the revb memory map has 0x1100 through 0x1c00
2229 * align instance address to 256 bytes so that it's
2230 * shifted list address is aligned.
2231 * list address = (mem address >> 1) >> 7;
2233 data_bytes = (data_bytes + 255) & ~255;
2234 address = 0x1100 + ((data_bytes/2) * index);
2236 if ((address + (data_bytes/2)) >= 0x1c00) {
2237 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2238 data_bytes, index, address);
2243 s->inst.code = 0x400;
2244 s->inst.data = address;
2246 for (i = data_bytes / 2; i > 0; address++, i--) {
2247 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2256 * this works for the reference board, have to find
2259 * this needs more magic for 4 speaker, but..
2262 snd_m3_amp_enable(m3_t *chip, int enable)
2264 int io = chip->iobase;
2267 if (! chip->external_amp)
2270 polarity = enable ? 0 : 1;
2271 polarity = polarity << chip->amp_gpio;
2272 gpo = 1 << chip->amp_gpio;
2274 outw(~gpo, io + GPIO_MASK);
2276 outw(inw(io + GPIO_DIRECTION) | gpo,
2277 io + GPIO_DIRECTION);
2279 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2282 outw(0xffff, io + GPIO_MASK);
2286 snd_m3_chip_init(m3_t *chip)
2288 struct pci_dev *pcidev = chip->pci;
2291 u8 t; /* makes as much sense as 'n', no? */
2293 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2294 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2295 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2297 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2299 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2300 n &= REDUCED_DEBOUNCE;
2301 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2302 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2304 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2305 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2306 n &= ~INT_CLK_SELECT;
2307 if (!chip->allegro_flag) {
2308 n &= ~INT_CLK_MULT_ENABLE;
2309 n |= INT_CLK_SRC_NOT_PCI;
2311 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2312 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2314 if (chip->allegro_flag) {
2315 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2316 n |= IN_CLK_12MHZ_SELECT;
2317 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2320 t = inb(chip->iobase + ASSP_CONTROL_A);
2321 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2322 t |= ASSP_CLK_49MHZ_SELECT;
2323 t |= ASSP_0_WS_ENABLE;
2324 outb(t, chip->iobase + ASSP_CONTROL_A);
2326 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2332 snd_m3_enable_ints(m3_t *chip)
2334 unsigned long io = chip->iobase;
2336 /* TODO: MPU401 not supported yet */
2337 outw(ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
2338 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2339 io + ASSP_CONTROL_C);
2346 static int snd_m3_free(m3_t *chip)
2351 if (chip->substreams) {
2352 spin_lock_irq(&chip->reg_lock);
2353 for (i = 0; i < chip->num_substreams; i++) {
2354 s = &chip->substreams[i];
2355 /* check surviving pcms; this should not happen though.. */
2356 if (s->substream && s->running)
2357 snd_m3_pcm_stop(chip, s, s->substream);
2359 spin_unlock_irq(&chip->reg_lock);
2360 kfree(chip->substreams);
2363 snd_m3_outw(chip, HOST_INT_CTRL, 0); /* disable ints */
2367 vfree(chip->suspend_mem);
2370 if (chip->irq >= 0) {
2371 synchronize_irq(chip->irq);
2372 free_irq(chip->irq, (void *)chip);
2376 pci_release_regions(chip->pci);
2378 pci_disable_device(chip->pci);
2388 static int m3_suspend(snd_card_t *card, unsigned int state)
2390 m3_t *chip = card->pm_private_data;
2393 if (chip->suspend_mem == NULL)
2396 snd_pcm_suspend_all(chip->pcm);
2397 snd_ac97_suspend(chip->ac97);
2399 big_mdelay(10); /* give the assp a chance to idle.. */
2401 snd_m3_assp_halt(chip);
2403 /* save dsp image */
2405 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2406 chip->suspend_mem[index++] =
2407 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2408 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2409 chip->suspend_mem[index++] =
2410 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2412 /* power down apci registers */
2413 snd_m3_outw(chip, 0xffff, 0x54);
2414 snd_m3_outw(chip, 0xffff, 0x56);
2416 pci_disable_device(chip->pci);
2420 static int m3_resume(snd_card_t *card, unsigned int state)
2422 m3_t *chip = card->pm_private_data;
2425 if (chip->suspend_mem == NULL)
2428 pci_enable_device(chip->pci);
2429 pci_set_master(chip->pci);
2431 /* first lets just bring everything back. .*/
2432 snd_m3_outw(chip, 0, 0x54);
2433 snd_m3_outw(chip, 0, 0x56);
2435 snd_m3_chip_init(chip);
2436 snd_m3_assp_halt(chip);
2437 snd_m3_ac97_reset(chip);
2439 /* restore dsp image */
2441 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2442 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2443 chip->suspend_mem[index++]);
2444 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2445 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2446 chip->suspend_mem[index++]);
2448 /* tell the dma engine to restart itself */
2449 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2450 KDATA_DMA_ACTIVE, 0);
2452 /* restore ac97 registers */
2453 snd_ac97_resume(chip->ac97);
2455 snd_m3_assp_continue(chip);
2456 snd_m3_enable_ints(chip);
2457 snd_m3_amp_enable(chip, 1);
2461 #endif /* CONFIG_PM */
2467 static int snd_m3_dev_free(snd_device_t *device)
2469 m3_t *chip = device->device_data;
2470 return snd_m3_free(chip);
2473 static int __devinit
2474 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2481 struct m3_quirk *quirk;
2482 u16 subsystem_vendor, subsystem_device;
2483 static snd_device_ops_t ops = {
2484 .dev_free = snd_m3_dev_free,
2489 if (pci_enable_device(pci))
2492 /* check, if we can restrict PCI DMA transfers to 28 bits */
2493 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2494 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2495 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2496 pci_disable_device(pci);
2500 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2502 pci_disable_device(pci);
2506 spin_lock_init(&chip->reg_lock);
2507 switch (pci->device) {
2508 case PCI_DEVICE_ID_ESS_ALLEGRO:
2509 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2510 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2511 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2512 chip->allegro_flag = 1;
2520 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2521 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2523 for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2524 if (subsystem_vendor == quirk->vendor &&
2525 subsystem_device == quirk->device) {
2526 printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2527 chip->quirk = quirk;
2532 chip->external_amp = enable_amp;
2533 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2534 chip->amp_gpio = amp_gpio;
2535 else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2536 chip->amp_gpio = chip->quirk->amp_gpio;
2537 else if (chip->allegro_flag)
2538 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2539 else /* presumably this is for all 'maestro3's.. */
2540 chip->amp_gpio = GPO_EXT_AMP_M3;
2542 chip->num_substreams = NR_DSPS;
2543 chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2544 if (chip->substreams == NULL) {
2546 pci_disable_device(pci);
2549 memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2551 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2555 chip->iobase = pci_resource_start(pci, 0);
2557 /* just to be sure */
2558 pci_set_master(pci);
2560 snd_m3_chip_init(chip);
2561 snd_m3_assp_halt(chip);
2563 snd_m3_ac97_reset(chip);
2565 snd_m3_assp_init(chip);
2566 snd_m3_amp_enable(chip, 1);
2568 if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2569 card->driver, (void *)chip)) {
2570 snd_printk("unable to grab IRQ %d\n", pci->irq);
2574 chip->irq = pci->irq;
2577 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2578 if (chip->suspend_mem == NULL)
2579 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2581 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2584 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2589 if ((err = snd_m3_mixer(chip)) < 0)
2592 for (i = 0; i < chip->num_substreams; i++) {
2593 m3_dma_t *s = &chip->substreams[i];
2595 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2599 if ((err = snd_m3_pcm(chip, 0)) < 0)
2602 snd_m3_enable_ints(chip);
2603 snd_m3_assp_continue(chip);
2605 snd_card_set_dev(card, &pci->dev);
2614 static int __devinit
2615 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2622 /* don't pick up modems */
2623 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2626 if (dev >= SNDRV_CARDS)
2633 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2637 switch (pci->device) {
2638 case PCI_DEVICE_ID_ESS_ALLEGRO:
2639 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2640 strcpy(card->driver, "Allegro");
2642 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2643 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2644 strcpy(card->driver, "Canyon3D-2");
2647 strcpy(card->driver, "Maestro3");
2651 if ((err = snd_m3_create(card, pci,
2655 snd_card_free(card);
2659 sprintf(card->shortname, "ESS %s PCI", card->driver);
2660 sprintf(card->longname, "%s at 0x%lx, irq %d",
2661 card->shortname, chip->iobase, chip->irq);
2663 if ((err = snd_card_register(card)) < 0) {
2664 snd_card_free(card);
2668 #if 0 /* TODO: not supported yet */
2669 /* TODO enable midi irq and i/o */
2670 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2671 chip->iobase + MPU401_DATA_PORT, 1,
2672 chip->irq, 0, &chip->rmidi);
2674 printk(KERN_WARNING "maestro3: no midi support.\n");
2677 pci_set_drvdata(pci, card);
2682 static void __devexit snd_m3_remove(struct pci_dev *pci)
2684 snd_card_free(pci_get_drvdata(pci));
2685 pci_set_drvdata(pci, NULL);
2688 static struct pci_driver driver = {
2690 .id_table = snd_m3_ids,
2691 .probe = snd_m3_probe,
2692 .remove = __devexit_p(snd_m3_remove),
2693 SND_PCI_PM_CALLBACKS
2696 static int __init alsa_card_m3_init(void)
2698 return pci_module_init(&driver);
2701 static void __exit alsa_card_m3_exit(void)
2703 pci_unregister_driver(&driver);
2706 module_init(alsa_card_m3_init)
2707 module_exit(alsa_card_m3_exit)