sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/moduleparam.h>
  43 #include <sound/core.h>
  44 #include <sound/info.h>
  45 #include <sound/control.h>
  46 #include <sound/pcm.h>
  47 #include <sound/mpu401.h>
  48 #include <sound/ac97_codec.h>
  49 #include <sound/initval.h>
  50
  51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  52 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  53 MODULE_LICENSE("GPL");
  54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  55                 "{ESS,ES1988},"
  56                 "{ESS,Allegro PCI},"
  57                 "{ESS,Allegro-1 PCI},"
  58                 "{ESS,Canyon3D-2/LE PCI}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  65 static int boot_devs;
  66
  67 module_param_array(index, int, boot_devs, 0444);
  68 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  69 module_param_array(id, charp, boot_devs, 0444);
  70 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  71 module_param_array(enable, bool, boot_devs, 0444);
  72 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  73 module_param_array(external_amp, bool, boot_devs, 0444);
  74 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  75 module_param_array(amp_gpio, int, boot_devs, 0444);
  76 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  77
  78 #define MAX_PLAYBACKS   2
  79 #define MAX_CAPTURES    1
  80 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  81
  82
  83 /*
  84  * maestro3 registers
  85  */
  86
  87 /* Allegro PCI configuration registers */
  88 #define PCI_LEGACY_AUDIO_CTRL   0x40
  89 #define SOUND_BLASTER_ENABLE    0x00000001
  90 #define FM_SYNTHESIS_ENABLE     0x00000002
  91 #define GAME_PORT_ENABLE        0x00000004
  92 #define MPU401_IO_ENABLE        0x00000008
  93 #define MPU401_IRQ_ENABLE       0x00000010
  94 #define ALIAS_10BIT_IO          0x00000020
  95 #define SB_DMA_MASK             0x000000C0
  96 #define SB_DMA_0                0x00000040
  97 #define SB_DMA_1                0x00000040
  98 #define SB_DMA_R                0x00000080
  99 #define SB_DMA_3                0x000000C0
 100 #define SB_IRQ_MASK             0x00000700
 101 #define SB_IRQ_5                0x00000000
 102 #define SB_IRQ_7                0x00000100
 103 #define SB_IRQ_9                0x00000200
 104 #define SB_IRQ_10               0x00000300
 105 #define MIDI_IRQ_MASK           0x00003800
 106 #define SERIAL_IRQ_ENABLE       0x00004000
 107 #define DISABLE_LEGACY          0x00008000
 108
 109 #define PCI_ALLEGRO_CONFIG      0x50
 110 #define SB_ADDR_240             0x00000004
 111 #define MPU_ADDR_MASK           0x00000018
 112 #define MPU_ADDR_330            0x00000000
 113 #define MPU_ADDR_300            0x00000008
 114 #define MPU_ADDR_320            0x00000010
 115 #define MPU_ADDR_340            0x00000018
 116 #define USE_PCI_TIMING          0x00000040
 117 #define POSTED_WRITE_ENABLE     0x00000080
 118 #define DMA_POLICY_MASK         0x00000700
 119 #define DMA_DDMA                0x00000000
 120 #define DMA_TDMA                0x00000100
 121 #define DMA_PCPCI               0x00000200
 122 #define DMA_WBDMA16             0x00000400
 123 #define DMA_WBDMA4              0x00000500
 124 #define DMA_WBDMA2              0x00000600
 125 #define DMA_WBDMA1              0x00000700
 126 #define DMA_SAFE_GUARD          0x00000800
 127 #define HI_PERF_GP_ENABLE       0x00001000
 128 #define PIC_SNOOP_MODE_0        0x00002000
 129 #define PIC_SNOOP_MODE_1        0x00004000
 130 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 131 #define RING_IN_ENABLE          0x00010000
 132 #define SPDIF_TEST_MODE         0x00020000
 133 #define CLK_MULT_MODE_SELECT_2  0x00040000
 134 #define EEPROM_WRITE_ENABLE     0x00080000
 135 #define CODEC_DIR_IN            0x00100000
 136 #define HV_BUTTON_FROM_GD       0x00200000
 137 #define REDUCED_DEBOUNCE        0x00400000
 138 #define HV_CTRL_ENABLE          0x00800000
 139 #define SPDIF_ENABLE            0x01000000
 140 #define CLK_DIV_SELECT          0x06000000
 141 #define CLK_DIV_BY_48           0x00000000
 142 #define CLK_DIV_BY_49           0x02000000
 143 #define CLK_DIV_BY_50           0x04000000
 144 #define CLK_DIV_RESERVED        0x06000000
 145 #define PM_CTRL_ENABLE          0x08000000
 146 #define CLK_MULT_MODE_SELECT    0x30000000
 147 #define CLK_MULT_MODE_SHIFT     28
 148 #define CLK_MULT_MODE_0         0x00000000
 149 #define CLK_MULT_MODE_1         0x10000000
 150 #define CLK_MULT_MODE_2         0x20000000
 151 #define CLK_MULT_MODE_3         0x30000000
 152 #define INT_CLK_SELECT          0x40000000
 153 #define INT_CLK_MULT_RESET      0x80000000
 154
 155 /* M3 */
 156 #define INT_CLK_SRC_NOT_PCI     0x00100000
 157 #define INT_CLK_MULT_ENABLE     0x80000000
 158
 159 #define PCI_ACPI_CONTROL        0x54
 160 #define PCI_ACPI_D0             0x00000000
 161 #define PCI_ACPI_D1             0xB4F70000
 162 #define PCI_ACPI_D2             0xB4F7B4F7
 163
 164 #define PCI_USER_CONFIG         0x58
 165 #define EXT_PCI_MASTER_ENABLE   0x00000001
 166 #define SPDIF_OUT_SELECT        0x00000002
 167 #define TEST_PIN_DIR_CTRL       0x00000004
 168 #define AC97_CODEC_TEST         0x00000020
 169 #define TRI_STATE_BUFFER        0x00000080
 170 #define IN_CLK_12MHZ_SELECT     0x00000100
 171 #define MULTI_FUNC_DISABLE      0x00000200
 172 #define EXT_MASTER_PAIR_SEL     0x00000400
 173 #define PCI_MASTER_SUPPORT      0x00000800
 174 #define STOP_CLOCK_ENABLE       0x00001000
 175 #define EAPD_DRIVE_ENABLE       0x00002000
 176 #define REQ_TRI_STATE_ENABLE    0x00004000
 177 #define REQ_LOW_ENABLE          0x00008000
 178 #define MIDI_1_ENABLE           0x00010000
 179 #define MIDI_2_ENABLE           0x00020000
 180 #define SB_AUDIO_SYNC           0x00040000
 181 #define HV_CTRL_TEST            0x00100000
 182 #define SOUNDBLASTER_TEST       0x00400000
 183
 184 #define PCI_USER_CONFIG_C       0x5C
 185
 186 #define PCI_DDMA_CTRL           0x60
 187 #define DDMA_ENABLE             0x00000001
 188
 189
 190 /* Allegro registers */
 191 #define HOST_INT_CTRL           0x18
 192 #define SB_INT_ENABLE           0x0001
 193 #define MPU401_INT_ENABLE       0x0002
 194 #define ASSP_INT_ENABLE         0x0010
 195 #define RING_INT_ENABLE         0x0020
 196 #define HV_INT_ENABLE           0x0040
 197 #define CLKRUN_GEN_ENABLE       0x0100
 198 #define HV_CTRL_TO_PME          0x0400
 199 #define SOFTWARE_RESET_ENABLE   0x8000
 200
 201 /*
 202  * should be using the above defines, probably.
 203  */
 204 #define REGB_ENABLE_RESET               0x01
 205 #define REGB_STOP_CLOCK                 0x10
 206
 207 #define HOST_INT_STATUS         0x1A
 208 #define SB_INT_PENDING          0x01
 209 #define MPU401_INT_PENDING      0x02
 210 #define ASSP_INT_PENDING        0x10
 211 #define RING_INT_PENDING        0x20
 212 #define HV_INT_PENDING          0x40
 213
 214 #define HARDWARE_VOL_CTRL       0x1B
 215 #define SHADOW_MIX_REG_VOICE    0x1C
 216 #define HW_VOL_COUNTER_VOICE    0x1D
 217 #define SHADOW_MIX_REG_MASTER   0x1E
 218 #define HW_VOL_COUNTER_MASTER   0x1F
 219
 220 #define CODEC_COMMAND           0x30
 221 #define CODEC_READ_B            0x80
 222
 223 #define CODEC_STATUS            0x30
 224 #define CODEC_BUSY_B            0x01
 225
 226 #define CODEC_DATA              0x32
 227
 228 #define RING_BUS_CTRL_A         0x36
 229 #define RAC_PME_ENABLE          0x0100
 230 #define RAC_SDFS_ENABLE         0x0200
 231 #define LAC_PME_ENABLE          0x0400
 232 #define LAC_SDFS_ENABLE         0x0800
 233 #define SERIAL_AC_LINK_ENABLE   0x1000
 234 #define IO_SRAM_ENABLE          0x2000
 235 #define IIS_INPUT_ENABLE        0x8000
 236
 237 #define RING_BUS_CTRL_B         0x38
 238 #define SECOND_CODEC_ID_MASK    0x0003
 239 #define SPDIF_FUNC_ENABLE       0x0010
 240 #define SECOND_AC_ENABLE        0x0020
 241 #define SB_MODULE_INTF_ENABLE   0x0040
 242 #define SSPE_ENABLE             0x0040
 243 #define M3I_DOCK_ENABLE         0x0080
 244
 245 #define SDO_OUT_DEST_CTRL       0x3A
 246 #define COMMAND_ADDR_OUT        0x0003
 247 #define PCM_LR_OUT_LOCAL        0x0000
 248 #define PCM_LR_OUT_REMOTE       0x0004
 249 #define PCM_LR_OUT_MUTE         0x0008
 250 #define PCM_LR_OUT_BOTH         0x000C
 251 #define LINE1_DAC_OUT_LOCAL     0x0000
 252 #define LINE1_DAC_OUT_REMOTE    0x0010
 253 #define LINE1_DAC_OUT_MUTE      0x0020
 254 #define LINE1_DAC_OUT_BOTH      0x0030
 255 #define PCM_CLS_OUT_LOCAL       0x0000
 256 #define PCM_CLS_OUT_REMOTE      0x0040
 257 #define PCM_CLS_OUT_MUTE        0x0080
 258 #define PCM_CLS_OUT_BOTH        0x00C0
 259 #define PCM_RLF_OUT_LOCAL       0x0000
 260 #define PCM_RLF_OUT_REMOTE      0x0100
 261 #define PCM_RLF_OUT_MUTE        0x0200
 262 #define PCM_RLF_OUT_BOTH        0x0300
 263 #define LINE2_DAC_OUT_LOCAL     0x0000
 264 #define LINE2_DAC_OUT_REMOTE    0x0400
 265 #define LINE2_DAC_OUT_MUTE      0x0800
 266 #define LINE2_DAC_OUT_BOTH      0x0C00
 267 #define HANDSET_OUT_LOCAL       0x0000
 268 #define HANDSET_OUT_REMOTE      0x1000
 269 #define HANDSET_OUT_MUTE        0x2000
 270 #define HANDSET_OUT_BOTH        0x3000
 271 #define IO_CTRL_OUT_LOCAL       0x0000
 272 #define IO_CTRL_OUT_REMOTE      0x4000
 273 #define IO_CTRL_OUT_MUTE        0x8000
 274 #define IO_CTRL_OUT_BOTH        0xC000
 275
 276 #define SDO_IN_DEST_CTRL        0x3C
 277 #define STATUS_ADDR_IN          0x0003
 278 #define PCM_LR_IN_LOCAL         0x0000
 279 #define PCM_LR_IN_REMOTE        0x0004
 280 #define PCM_LR_RESERVED         0x0008
 281 #define PCM_LR_IN_BOTH          0x000C
 282 #define LINE1_ADC_IN_LOCAL      0x0000
 283 #define LINE1_ADC_IN_REMOTE     0x0010
 284 #define LINE1_ADC_IN_MUTE       0x0020
 285 #define MIC_ADC_IN_LOCAL        0x0000
 286 #define MIC_ADC_IN_REMOTE       0x0040
 287 #define MIC_ADC_IN_MUTE         0x0080
 288 #define LINE2_DAC_IN_LOCAL      0x0000
 289 #define LINE2_DAC_IN_REMOTE     0x0400
 290 #define LINE2_DAC_IN_MUTE       0x0800
 291 #define HANDSET_IN_LOCAL        0x0000
 292 #define HANDSET_IN_REMOTE       0x1000
 293 #define HANDSET_IN_MUTE         0x2000
 294 #define IO_STATUS_IN_LOCAL      0x0000
 295 #define IO_STATUS_IN_REMOTE     0x4000
 296
 297 #define SPDIF_IN_CTRL           0x3E
 298 #define SPDIF_IN_ENABLE         0x0001
 299
 300 #define GPIO_DATA               0x60
 301 #define GPIO_DATA_MASK          0x0FFF
 302 #define GPIO_HV_STATUS          0x3000
 303 #define GPIO_PME_STATUS         0x4000
 304
 305 #define GPIO_MASK               0x64
 306 #define GPIO_DIRECTION          0x68
 307 #define GPO_PRIMARY_AC97        0x0001
 308 #define GPI_LINEOUT_SENSE       0x0004
 309 #define GPO_SECONDARY_AC97      0x0008
 310 #define GPI_VOL_DOWN            0x0010
 311 #define GPI_VOL_UP              0x0020
 312 #define GPI_IIS_CLK             0x0040
 313 #define GPI_IIS_LRCLK           0x0080
 314 #define GPI_IIS_DATA            0x0100
 315 #define GPI_DOCKING_STATUS      0x0100
 316 #define GPI_HEADPHONE_SENSE     0x0200
 317 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 318
 319 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 320 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 321
 322 /* M3 */
 323 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 324
 325 #define ASSP_INDEX_PORT         0x80
 326 #define ASSP_MEMORY_PORT        0x82
 327 #define ASSP_DATA_PORT          0x84
 328
 329 #define MPU401_DATA_PORT        0x98
 330 #define MPU401_STATUS_PORT      0x99
 331
 332 #define CLK_MULT_DATA_PORT      0x9C
 333
 334 #define ASSP_CONTROL_A          0xA2
 335 #define ASSP_0_WS_ENABLE        0x01
 336 #define ASSP_CTRL_A_RESERVED1   0x02
 337 #define ASSP_CTRL_A_RESERVED2   0x04
 338 #define ASSP_CLK_49MHZ_SELECT   0x08
 339 #define FAST_PLU_ENABLE         0x10
 340 #define ASSP_CTRL_A_RESERVED3   0x20
 341 #define DSP_CLK_36MHZ_SELECT    0x40
 342
 343 #define ASSP_CONTROL_B          0xA4
 344 #define RESET_ASSP              0x00
 345 #define RUN_ASSP                0x01
 346 #define ENABLE_ASSP_CLOCK       0x00
 347 #define STOP_ASSP_CLOCK         0x10
 348 #define RESET_TOGGLE            0x40
 349
 350 #define ASSP_CONTROL_C          0xA6
 351 #define ASSP_HOST_INT_ENABLE    0x01
 352 #define FM_ADDR_REMAP_DISABLE   0x02
 353 #define HOST_WRITE_PORT_ENABLE  0x08
 354
 355 #define ASSP_HOST_INT_STATUS    0xAC
 356 #define DSP2HOST_REQ_PIORECORD  0x01
 357 #define DSP2HOST_REQ_I2SRATE    0x02
 358 #define DSP2HOST_REQ_TIMER      0x04
 359
 360 /* AC97 registers */
 361 /* XXX fix this crap up */
 362 /*#define AC97_RESET              0x00*/
 363
 364 #define AC97_VOL_MUTE_B         0x8000
 365 #define AC97_VOL_M              0x1F
 366 #define AC97_LEFT_VOL_S         8
 367
 368 #define AC97_MASTER_VOL         0x02
 369 #define AC97_LINE_LEVEL_VOL     0x04
 370 #define AC97_MASTER_MONO_VOL    0x06
 371 #define AC97_PC_BEEP_VOL        0x0A
 372 #define AC97_PC_BEEP_VOL_M      0x0F
 373 #define AC97_SROUND_MASTER_VOL  0x38
 374 #define AC97_PC_BEEP_VOL_S      1
 375
 376 /*#define AC97_PHONE_VOL          0x0C
 377 #define AC97_MIC_VOL            0x0E*/
 378 #define AC97_MIC_20DB_ENABLE    0x40
 379
 380 /*#define AC97_LINEIN_VOL         0x10
 381 #define AC97_CD_VOL             0x12
 382 #define AC97_VIDEO_VOL          0x14
 383 #define AC97_AUX_VOL            0x16*/
 384 #define AC97_PCM_OUT_VOL        0x18
 385 /*#define AC97_RECORD_SELECT      0x1A*/
 386 #define AC97_RECORD_MIC         0x00
 387 #define AC97_RECORD_CD          0x01
 388 #define AC97_RECORD_VIDEO       0x02
 389 #define AC97_RECORD_AUX         0x03
 390 #define AC97_RECORD_MONO_MUX    0x02
 391 #define AC97_RECORD_DIGITAL     0x03
 392 #define AC97_RECORD_LINE        0x04
 393 #define AC97_RECORD_STEREO      0x05
 394 #define AC97_RECORD_MONO        0x06
 395 #define AC97_RECORD_PHONE       0x07
 396
 397 /*#define AC97_RECORD_GAIN        0x1C*/
 398 #define AC97_RECORD_VOL_M       0x0F
 399
 400 /*#define AC97_GENERAL_PURPOSE    0x20*/
 401 #define AC97_POWER_DOWN_CTRL    0x26
 402 #define AC97_ADC_READY          0x0001
 403 #define AC97_DAC_READY          0x0002
 404 #define AC97_ANALOG_READY       0x0004
 405 #define AC97_VREF_ON            0x0008
 406 #define AC97_PR0                0x0100
 407 #define AC97_PR1                0x0200
 408 #define AC97_PR2                0x0400
 409 #define AC97_PR3                0x0800
 410 #define AC97_PR4                0x1000
 411
 412 #define AC97_RESERVED1          0x28
 413
 414 #define AC97_VENDOR_TEST        0x5A
 415
 416 #define AC97_CLOCK_DELAY        0x5C
 417 #define AC97_LINEOUT_MUX_SEL    0x0001
 418 #define AC97_MONO_MUX_SEL       0x0002
 419 #define AC97_CLOCK_DELAY_SEL    0x1F
 420 #define AC97_DAC_CDS_SHIFT      6
 421 #define AC97_ADC_CDS_SHIFT      11
 422
 423 #define AC97_MULTI_CHANNEL_SEL  0x74
 424
 425 /*#define AC97_VENDOR_ID1         0x7C
 426 #define AC97_VENDOR_ID2         0x7E*/
 427
 428 /*
 429  * ASSP control regs
 430  */
 431 #define DSP_PORT_TIMER_COUNT    0x06
 432
 433 #define DSP_PORT_MEMORY_INDEX   0x80
 434
 435 #define DSP_PORT_MEMORY_TYPE    0x82
 436 #define MEMTYPE_INTERNAL_CODE   0x0002
 437 #define MEMTYPE_INTERNAL_DATA   0x0003
 438 #define MEMTYPE_MASK            0x0003
 439
 440 #define DSP_PORT_MEMORY_DATA    0x84
 441
 442 #define DSP_PORT_CONTROL_REG_A  0xA2
 443 #define DSP_PORT_CONTROL_REG_B  0xA4
 444 #define DSP_PORT_CONTROL_REG_C  0xA6
 445
 446 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 447 #define REV_A_CODE_MEMORY_END           0x0FFF
 448 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 449 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 450
 451 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 452 #define REV_B_CODE_MEMORY_END           0x0BFF
 453 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 454 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 455
 456 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 457 #define REV_A_DATA_MEMORY_END           0x2FFF
 458 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 459 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 460
 461 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 462 #define REV_B_DATA_MEMORY_END           0x2BFF
 463 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 464 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 465
 466
 467 #define NUM_UNITS_KERNEL_CODE          16
 468 #define NUM_UNITS_KERNEL_DATA           2
 469
 470 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 471 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 472
 473 /*
 474  * Kernel data layout
 475  */
 476
 477 #define DP_SHIFT_COUNT                  7
 478
 479 #define KDATA_BASE_ADDR                 0x1000
 480 #define KDATA_BASE_ADDR2                0x1080
 481
 482 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 483 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 484 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 485 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 486 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 487 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 488 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 489 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 490 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 491
 492 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 493 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 494
 495 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 496 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 497 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 498 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 499 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 500 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 501 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 502 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 503 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 504 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 505
 506 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 507 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 508
 509 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 510 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 511
 512 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 513 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 514
 515 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 516 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 517 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 518
 519 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 520 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 521 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 522 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 523 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 524
 525 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 526 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 527 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 528
 529 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 530 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 531 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 532
 533 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 534 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 535 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 536 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 537 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 538 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 539 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 540 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 541 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 542 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 543
 544 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 545 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 546 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 547
 548 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 549 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 550
 551 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 552 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 553 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 554
 555 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 556 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 557 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 558 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 559 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 560 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 561
 562 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 563 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 564 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 565 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 566 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 567 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 568
 569 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 570 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 571 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 572 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 573 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 574 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 575
 576 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 577 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 578 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 579 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 580
 581 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 582 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 583
 584 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 585 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 586
 587 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 588 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 589 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 590 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 591 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 592
 593 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 594 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 595
 596 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 597 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 598 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 599
 600 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 601 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 602
 603 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 604
 605 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 606 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 607 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 608 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 609 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 610 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 611 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 612 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 613 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 614 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 615 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 616 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 617
 618 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 619 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 620 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 621 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 622
 623 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 624 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 625
 626 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 627 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 628 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 629 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 630
 631 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 632 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 633 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 634 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 635 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 636
 637 /*
 638  * second 'segment' (?) reserved for mixer
 639  * buffers..
 640  */
 641
 642 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 643 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 644 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 645 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 646 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 647 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 648 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 649 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 650 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 651 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 652 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 653 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 654 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 655 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 656 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 657 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 658
 659 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 660 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 661 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 662 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 663 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 664 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 665 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 666 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 667 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 668 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 669 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 670
 671 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 672 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 673 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 674 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 675 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 676 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 677
 678 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 679 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 680 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 681 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 682
 683 /*
 684  * client data area offsets
 685  */
 686 #define CDATA_INSTANCE_READY            0x00
 687
 688 #define CDATA_HOST_SRC_ADDRL            0x01
 689 #define CDATA_HOST_SRC_ADDRH            0x02
 690 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 691 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 692 #define CDATA_HOST_SRC_CURRENTL         0x05
 693 #define CDATA_HOST_SRC_CURRENTH         0x06
 694
 695 #define CDATA_IN_BUF_CONNECT            0x07
 696 #define CDATA_OUT_BUF_CONNECT           0x08
 697
 698 #define CDATA_IN_BUF_BEGIN              0x09
 699 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 700 #define CDATA_IN_BUF_HEAD               0x0B
 701 #define CDATA_IN_BUF_TAIL               0x0C
 702 #define CDATA_OUT_BUF_BEGIN             0x0D
 703 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 704 #define CDATA_OUT_BUF_HEAD              0x0F
 705 #define CDATA_OUT_BUF_TAIL              0x10
 706
 707 #define CDATA_DMA_CONTROL               0x11
 708 #define CDATA_RESERVED                  0x12
 709
 710 #define CDATA_FREQUENCY                 0x13
 711 #define CDATA_LEFT_VOLUME               0x14
 712 #define CDATA_RIGHT_VOLUME              0x15
 713 #define CDATA_LEFT_SUR_VOL              0x16
 714 #define CDATA_RIGHT_SUR_VOL             0x17
 715
 716 #define CDATA_HEADER_LEN                0x18
 717
 718 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 719 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 720 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 721 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 722 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 723 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 724 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 725 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 726
 727 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 728 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 729 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 730 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 731 #define MINISRC_BIQUAD_STAGE    2
 732 #define MINISRC_COEF_LOC          0x175
 733
 734 #define DMACONTROL_BLOCK_MASK           0x000F
 735 #define  DMAC_BLOCK0_SELECTOR           0x0000
 736 #define  DMAC_BLOCK1_SELECTOR           0x0001
 737 #define  DMAC_BLOCK2_SELECTOR           0x0002
 738 #define  DMAC_BLOCK3_SELECTOR           0x0003
 739 #define  DMAC_BLOCK4_SELECTOR           0x0004
 740 #define  DMAC_BLOCK5_SELECTOR           0x0005
 741 #define  DMAC_BLOCK6_SELECTOR           0x0006
 742 #define  DMAC_BLOCK7_SELECTOR           0x0007
 743 #define  DMAC_BLOCK8_SELECTOR           0x0008
 744 #define  DMAC_BLOCK9_SELECTOR           0x0009
 745 #define  DMAC_BLOCKA_SELECTOR           0x000A
 746 #define  DMAC_BLOCKB_SELECTOR           0x000B
 747 #define  DMAC_BLOCKC_SELECTOR           0x000C
 748 #define  DMAC_BLOCKD_SELECTOR           0x000D
 749 #define  DMAC_BLOCKE_SELECTOR           0x000E
 750 #define  DMAC_BLOCKF_SELECTOR           0x000F
 751 #define DMACONTROL_PAGE_MASK            0x00F0
 752 #define  DMAC_PAGE0_SELECTOR            0x0030
 753 #define  DMAC_PAGE1_SELECTOR            0x0020
 754 #define  DMAC_PAGE2_SELECTOR            0x0010
 755 #define  DMAC_PAGE3_SELECTOR            0x0000
 756 #define DMACONTROL_AUTOREPEAT           0x1000
 757 #define DMACONTROL_STOPPED              0x2000
 758 #define DMACONTROL_DIRECTION            0x0100
 759
 760 /*
 761  * an arbitrary volume we set the internal
 762  * volume settings to so that the ac97 volume
 763  * range is a little less insane.  0x7fff is
 764  * max.
 765  */
 766 #define ARB_VOLUME ( 0x6800 )
 767
 768 /*
 769  */
 770
 771 typedef struct snd_m3_dma m3_dma_t;
 772 typedef struct snd_m3 m3_t;
 773
 774 /* quirk lists */
 775 struct m3_quirk {
 776         const char *name;       /* device name */
 777         u16 vendor, device;     /* subsystem ids */
 778         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 779         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 780                                    (e.g. for IrDA on Dell Inspirons) */
 781 };
 782
 783 struct m3_list {
 784         int curlen;
 785         int mem_addr;
 786         int max;
 787 };
 788
 789 struct snd_m3_dma {
 790
 791         int number;
 792         m3_t *chip;
 793         snd_pcm_substream_t *substream;
 794
 795         struct assp_instance {
 796                 unsigned short code, data;
 797         } inst;
 798
 799         int running;
 800         int opened;
 801
 802         unsigned long buffer_addr;
 803         int dma_size;
 804         int period_size;
 805         unsigned int hwptr;
 806         int count;
 807
 808         int index[3];
 809         struct m3_list *index_list[3];
 810
 811         int in_lists;
 812
 813         struct list_head list;
 814
 815 };
 816
 817 struct snd_m3 {
 818
 819         snd_card_t *card;
 820
 821         unsigned long iobase;
 822
 823         int irq;
 824         int allegro_flag : 1;
 825
 826         ac97_t *ac97;
 827
 828         snd_pcm_t *pcm;
 829
 830         struct pci_dev *pci;
 831         struct m3_quirk *quirk;
 832
 833         int dacs_active;
 834         int timer_users;
 835
 836         struct m3_list  msrc_list;
 837         struct m3_list  mixer_list;
 838         struct m3_list  adc1_list;
 839         struct m3_list  dma_list;
 840
 841         /* for storing reset state..*/
 842         u8 reset_state;
 843
 844         int external_amp;
 845         int amp_gpio;
 846
 847         /* midi */
 848         snd_rawmidi_t *rmidi;
 849
 850         /* pcm streams */
 851         int num_substreams;
 852         m3_dma_t *substreams;
 853
 854         spinlock_t reg_lock;
 855
 856 #ifdef CONFIG_PM
 857         u16 *suspend_mem;
 858 #endif
 859 };
 860
 861 /*
 862  * pci ids
 863  */
 864
 865 #ifndef PCI_VENDOR_ID_ESS
 866 #define PCI_VENDOR_ID_ESS         0x125D
 867 #endif
 868 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
 869 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 870 #endif
 871 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
 872 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
 873 #endif
 874 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
 875 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE  0x1990
 876 #endif
 877 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
 878 #define PCI_DEVICE_ID_ESS_CANYON3D_2    0x1992
 879 #endif
 880 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
 881 #define PCI_DEVICE_ID_ESS_MAESTRO3      0x1998
 882 #endif
 883 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
 884 #define PCI_DEVICE_ID_ESS_MAESTRO3_1    0x1999
 885 #endif
 886 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
 887 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW   0x199a
 888 #endif
 889 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
 890 #define PCI_DEVICE_ID_ESS_MAESTRO3_2    0x199b
 891 #endif
 892
 893 static struct pci_device_id snd_m3_ids[] = {
 894         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 895          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 896         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 897          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 898         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 899          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 900         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 901          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 902         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 903          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 904         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 905          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 906         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 907          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 908         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 909          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 910         {0,},
 911 };
 912
 913 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 914
 915 static struct m3_quirk m3_quirk_list[] = {
 916         /* panasonic CF-28 "toughbook" */
 917         {
 918                 .name = "Panasonic CF-28",
 919                 .vendor = 0x10f7,
 920                 .device = 0x833e,
 921                 .amp_gpio = 0x0d,
 922         },
 923         /* panasonic CF-72 "toughbook" */
 924         {
 925                 .name = "Panasonic CF-72",
 926                 .vendor = 0x10f7,
 927                 .device = 0x833d,
 928                 .amp_gpio = 0x0d,
 929         },
 930         /* Dell Inspiron 4000 */
 931         {
 932                 .name = "Dell Inspiron 4000",
 933                 .vendor = 0x1028,
 934                 .device = 0x00b0,
 935                 .amp_gpio = -1,
 936                 .irda_workaround = 1,
 937         },
 938         /* Dell Inspiron 8000 */
 939         {
 940                 .name = "Dell Inspiron 8000",
 941                 .vendor = 0x1028,
 942                 .device = 0x00a4,
 943                 .amp_gpio = -1,
 944                 .irda_workaround = 1,
 945         },
 946         /* Dell Inspiron 8100 */
 947         {
 948                 .name = "Dell Inspiron 8100",
 949                 .vendor = 0x1028,
 950                 .device = 0x00e6,
 951                 .amp_gpio = -1,
 952                 .irda_workaround = 1,
 953         },
 954         /* NEC LM800J/7 */
 955         {
 956                 .name = "NEC LM800J/7",
 957                 .vendor = 0x1033,
 958                 .device = 0x80f1,
 959                 .amp_gpio = 0x03,
 960         },
 961         /* END */
 962         { NULL }
 963 };
 964
 965
 966 /*
 967  * lowlevel functions
 968  */
 969
 970 #define big_mdelay(msec) do {\
 971         set_current_state(TASK_UNINTERRUPTIBLE);\
 972         schedule_timeout(((msec) * HZ) / 1000);\
 973 } while (0)
 974
 975 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
 976 {
 977         outw(value, chip->iobase + reg);
 978 }
 979
 980 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
 981 {
 982         return inw(chip->iobase + reg);
 983 }
 984
 985 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
 986 {
 987         outb(value, chip->iobase + reg);
 988 }
 989
 990 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
 991 {
 992         return inb(chip->iobase + reg);
 993 }
 994
 995 /*
 996  * access 16bit words to the code or data regions of the dsp's memory.
 997  * index addresses 16bit words.
 998  */
 999 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
1000 {
1001         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1002         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1003         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1004 }
1005
1006 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1007 {
1008         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1009         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1010         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1011 }
1012
1013 static void snd_m3_assp_halt(m3_t *chip)
1014 {
1015         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1016         big_mdelay(10);
1017         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1018 }
1019
1020 static void snd_m3_assp_continue(m3_t *chip)
1021 {
1022         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1023 }
1024
1025
1026 /*
1027  * This makes me sad. the maestro3 has lists
1028  * internally that must be packed.. 0 terminates,
1029  * apparently, or maybe all unused entries have
1030  * to be 0, the lists have static lengths set
1031  * by the binary code images.
1032  */
1033
1034 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1035 {
1036         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1037                           list->mem_addr + list->curlen,
1038                           val);
1039         return list->curlen++;
1040 }
1041
1042 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1043 {
1044         u16  val;
1045         int lastindex = list->curlen - 1;
1046
1047         if (index != lastindex) {
1048                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1049                                        list->mem_addr + lastindex);
1050                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1051                                   list->mem_addr + index,
1052                                   val);
1053         }
1054
1055         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1056                           list->mem_addr + lastindex,
1057                           0);
1058
1059         list->curlen--;
1060 }
1061
1062 static void snd_m3_inc_timer_users(m3_t *chip)
1063 {
1064         chip->timer_users++;
1065         if (chip->timer_users != 1)
1066                 return;
1067
1068         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1069                           KDATA_TIMER_COUNT_RELOAD,
1070                           240);
1071
1072         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1073                           KDATA_TIMER_COUNT_CURRENT,
1074                           240);
1075
1076         snd_m3_outw(chip,
1077                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1078                     HOST_INT_CTRL);
1079 }
1080
1081 static void snd_m3_dec_timer_users(m3_t *chip)
1082 {
1083         chip->timer_users--;
1084         if (chip->timer_users > 0)
1085                 return;
1086
1087         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088                           KDATA_TIMER_COUNT_RELOAD,
1089                           0);
1090
1091         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1092                           KDATA_TIMER_COUNT_CURRENT,
1093                           0);
1094
1095         snd_m3_outw(chip,
1096                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1097                     HOST_INT_CTRL);
1098 }
1099
1100 /*
1101  * start/stop
1102  */
1103
1104 /* spinlock held! */
1105 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1106 {
1107         if (! s || ! subs)
1108                 return -EINVAL;
1109
1110         snd_m3_inc_timer_users(chip);
1111         switch (subs->stream) {
1112         case SNDRV_PCM_STREAM_PLAYBACK:
1113                 chip->dacs_active++;
1114                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1115                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1116                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1117                                   KDATA_MIXER_TASK_NUMBER,
1118                                   chip->dacs_active);
1119                 break;
1120         case SNDRV_PCM_STREAM_CAPTURE:
1121                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1122                                   KDATA_ADC1_REQUEST, 1);
1123                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1124                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1125                 break;
1126         }
1127         return 0;
1128 }
1129
1130 /* spinlock held! */
1131 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1132 {
1133         if (! s || ! subs)
1134                 return -EINVAL;
1135
1136         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1137                           s->inst.data + CDATA_INSTANCE_READY, 0);
1138         snd_m3_dec_timer_users(chip);
1139         switch (subs->stream) {
1140         case SNDRV_PCM_STREAM_PLAYBACK:
1141                 chip->dacs_active--;
1142                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1143                                   KDATA_MIXER_TASK_NUMBER,
1144                                   chip->dacs_active);
1145                 break;
1146         case SNDRV_PCM_STREAM_CAPTURE:
1147                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1148                                   KDATA_ADC1_REQUEST, 0);
1149                 break;
1150         }
1151         return 0;
1152 }
1153
1154 static int
1155 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1156 {
1157         m3_t *chip = snd_pcm_substream_chip(subs);
1158         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1159         int err = -EINVAL;
1160
1161         snd_assert(s != NULL, return -ENXIO);
1162
1163         spin_lock(&chip->reg_lock);
1164         switch (cmd) {
1165         case SNDRV_PCM_TRIGGER_START:
1166         case SNDRV_PCM_TRIGGER_RESUME:
1167                 if (s->running)
1168                         err = -EBUSY;
1169                 else {
1170                         s->running = 1;
1171                         err = snd_m3_pcm_start(chip, s, subs);
1172                 }
1173                 break;
1174         case SNDRV_PCM_TRIGGER_STOP:
1175         case SNDRV_PCM_TRIGGER_SUSPEND:
1176                 if (! s->running)
1177                         err = 0; /* should return error? */
1178                 else {
1179                         s->running = 0;
1180                         err = snd_m3_pcm_stop(chip, s, subs);
1181                 }
1182                 break;
1183         }
1184         spin_unlock(&chip->reg_lock);
1185         return err;
1186 }
1187
1188 /*
1189  * setup
1190  */
1191 static void
1192 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1193 {
1194         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1195         snd_pcm_runtime_t *runtime = subs->runtime;
1196
1197         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1198                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1199                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1200         } else {
1201                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1202                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1203         }
1204         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1205         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1206
1207         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1208         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1209         s->hwptr = 0;
1210         s->count = 0;
1211
1212 #define LO(x) ((x) & 0xffff)
1213 #define HI(x) LO((x) >> 16)
1214
1215         /* host dma buffer pointers */
1216         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1217                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1218                           LO(s->buffer_addr));
1219
1220         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1221                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1222                           HI(s->buffer_addr));
1223
1224         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1225                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1226                           LO(s->buffer_addr + s->dma_size));
1227
1228         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1229                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1230                           HI(s->buffer_addr + s->dma_size));
1231
1232         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1233                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1234                           LO(s->buffer_addr));
1235
1236         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1237                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1238                           HI(s->buffer_addr));
1239 #undef LO
1240 #undef HI
1241
1242         /* dsp buffers */
1243
1244         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1245                           s->inst.data + CDATA_IN_BUF_BEGIN,
1246                           dsp_in_buffer);
1247
1248         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1249                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1250                           dsp_in_buffer + (dsp_in_size / 2));
1251
1252         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1253                           s->inst.data + CDATA_IN_BUF_HEAD,
1254                           dsp_in_buffer);
1255
1256         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1257                           s->inst.data + CDATA_IN_BUF_TAIL,
1258                           dsp_in_buffer);
1259
1260         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1261                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1262                           dsp_out_buffer);
1263
1264         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1265                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1266                           dsp_out_buffer + (dsp_out_size / 2));
1267
1268         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1269                           s->inst.data + CDATA_OUT_BUF_HEAD,
1270                           dsp_out_buffer);
1271
1272         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1273                           s->inst.data + CDATA_OUT_BUF_TAIL,
1274                           dsp_out_buffer);
1275 }
1276
1277 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1278 {
1279         u32 freq;
1280
1281         /*
1282          * put us in the lists if we're not already there
1283          */
1284         if (! s->in_lists) {
1285                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1286                                               s->inst.data >> DP_SHIFT_COUNT);
1287                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1288                                               s->inst.data >> DP_SHIFT_COUNT);
1289                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1290                                               s->inst.data >> DP_SHIFT_COUNT);
1291                 s->in_lists = 1;
1292         }
1293
1294         /* write to 'mono' word */
1295         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1296                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1297                           runtime->channels == 2 ? 0 : 1);
1298         /* write to '8bit' word */
1299         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1300                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1301                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1302
1303         /* set up dac/adc rate */
1304         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1305         if (freq)
1306                 freq--;
1307
1308         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1309                           s->inst.data + CDATA_FREQUENCY,
1310                           freq);
1311 }
1312
1313
1314 static struct play_vals {
1315         u16 addr, val;
1316 } pv[] = {
1317         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1318         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1319         {SRC3_DIRECTION_OFFSET, 0} ,
1320         /* +1, +2 are stereo/16 bit */
1321         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1322         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1323         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1324         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1325         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1326         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1327         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1328         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1329         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1330         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1331         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1332         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1333         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1334         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1335         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1336         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1337         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1338 };
1339
1340
1341 /* the mode passed should be already shifted and masked */
1342 static void
1343 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1344 {
1345         unsigned int i;
1346
1347         /*
1348          * some per client initializers
1349          */
1350
1351         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1352                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1353                           s->inst.data + 40 + 8);
1354
1355         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1356                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1357                           s->inst.code + MINISRC_COEF_LOC);
1358
1359         /* enable or disable low pass filter? */
1360         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1361                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1362                           subs->runtime->rate > 45000 ? 0xff : 0);
1363
1364         /* tell it which way dma is going? */
1365         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1366                           s->inst.data + CDATA_DMA_CONTROL,
1367                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1368
1369         /*
1370          * set an armload of static initializers
1371          */
1372         for (i = 0; i < ARRAY_SIZE(pv); i++)
1373                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374                                   s->inst.data + pv[i].addr, pv[i].val);
1375 }
1376
1377 /*
1378  *    Native record driver
1379  */
1380 static struct rec_vals {
1381         u16 addr, val;
1382 } rv[] = {
1383         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1384         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1385         {SRC3_DIRECTION_OFFSET, 1} ,
1386         /* +1, +2 are stereo/16 bit */
1387         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1388         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1389         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1390         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1391         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1392         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1393         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1394         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1395         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1396         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1397         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1398         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1399         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1400         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1401         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1402         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1403         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1404         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1405         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1406 };
1407
1408 static void
1409 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1410 {
1411         unsigned int i;
1412
1413         /*
1414          * some per client initializers
1415          */
1416
1417         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1418                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1419                           s->inst.data + 40 + 8);
1420
1421         /* tell it which way dma is going? */
1422         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1423                           s->inst.data + CDATA_DMA_CONTROL,
1424                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1425                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1426
1427         /*
1428          * set an armload of static initializers
1429          */
1430         for (i = 0; i < ARRAY_SIZE(rv); i++)
1431                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1432                                   s->inst.data + rv[i].addr, rv[i].val);
1433 }
1434
1435 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1436                                 snd_pcm_hw_params_t * hw_params)
1437 {
1438         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1439         int err;
1440
1441         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1442                 return err;
1443         /* set buffer address */
1444         s->buffer_addr = substream->runtime->dma_addr;
1445         if (s->buffer_addr & 0x3) {
1446                 snd_printk("oh my, not aligned\n");
1447                 s->buffer_addr = s->buffer_addr & ~0x3;
1448         }
1449         return 0;
1450 }
1451
1452 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1453 {
1454         m3_dma_t *s;
1455
1456         if (substream->runtime->private_data == NULL)
1457                 return 0;
1458         s = (m3_dma_t*) substream->runtime->private_data;
1459         snd_pcm_lib_free_pages(substream);
1460         s->buffer_addr = 0;
1461         return 0;
1462 }
1463
1464 static int
1465 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1466 {
1467         m3_t *chip = snd_pcm_substream_chip(subs);
1468         snd_pcm_runtime_t *runtime = subs->runtime;
1469         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1470
1471         snd_assert(s != NULL, return -ENXIO);
1472
1473         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1474             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1475                 return -EINVAL;
1476         if (runtime->rate > 48000 ||
1477             runtime->rate < 8000)
1478                 return -EINVAL;
1479
1480         spin_lock_irq(&chip->reg_lock);
1481
1482         snd_m3_pcm_setup1(chip, s, subs);
1483
1484         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1485                 snd_m3_playback_setup(chip, s, subs);
1486         else
1487                 snd_m3_capture_setup(chip, s, subs);
1488
1489         snd_m3_pcm_setup2(chip, s, runtime);
1490
1491         spin_unlock_irq(&chip->reg_lock);
1492
1493         return 0;
1494 }
1495
1496 /*
1497  * get current pointer
1498  */
1499 static unsigned int
1500 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1501 {
1502         u16 hi = 0, lo = 0;
1503         int retry = 10;
1504         u32 addr;
1505
1506         /*
1507          * try and get a valid answer
1508          */
1509         while (retry--) {
1510                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1511                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1512
1513                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1514                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1515
1516                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1517                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1518                         break;
1519         }
1520         addr = lo | ((u32)hi<<16);
1521         return (unsigned int)(addr - s->buffer_addr);
1522 }
1523
1524 static snd_pcm_uframes_t
1525 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1526 {
1527         m3_t *chip = snd_pcm_substream_chip(subs);
1528         unsigned int ptr;
1529         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1530         snd_assert(s != NULL, return 0);
1531
1532         spin_lock(&chip->reg_lock);
1533         ptr = snd_m3_get_pointer(chip, s, subs);
1534         spin_unlock(&chip->reg_lock);
1535         return bytes_to_frames(subs->runtime, ptr);
1536 }
1537
1538
1539 /* update pointer */
1540 /* spinlock held! */
1541 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1542 {
1543         snd_pcm_substream_t *subs = s->substream;
1544         unsigned int hwptr;
1545         int diff;
1546
1547         if (! s->running)
1548                 return;
1549
1550         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1551         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1552         s->hwptr = hwptr;
1553         s->count += diff;
1554         if (s->count >= (signed)s->period_size) {
1555                 s->count %= s->period_size;
1556                 spin_unlock(&chip->reg_lock);
1557                 snd_pcm_period_elapsed(subs);
1558                 spin_lock(&chip->reg_lock);
1559         }
1560 }
1561
1562 static irqreturn_t
1563 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1564 {
1565         m3_t *chip = dev_id;
1566         u8 status;
1567         int i;
1568
1569         status = inb(chip->iobase + HOST_INT_STATUS);
1570
1571         if (status == 0xff)
1572                 return IRQ_NONE;
1573
1574         /*
1575          * ack an assp int if its running
1576          * and has an int pending
1577          */
1578         if (status & ASSP_INT_PENDING) {
1579                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1580                 if (!(ctl & STOP_ASSP_CLOCK)) {
1581                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1582                         if (ctl & DSP2HOST_REQ_TIMER) {
1583                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1584                                 /* update adc/dac info if it was a timer int */
1585                                 spin_lock(&chip->reg_lock);
1586                                 for (i = 0; i < chip->num_substreams; i++) {
1587                                         m3_dma_t *s = &chip->substreams[i];
1588                                         if (s->running)
1589                                                 snd_m3_update_ptr(chip, s);
1590                                 }
1591                                 spin_unlock(&chip->reg_lock);
1592                         }
1593                 }
1594         }
1595
1596 #if 0 /* TODO: not supported yet */
1597         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1598                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1599 #endif
1600
1601         /* ack ints */
1602         snd_m3_outw(chip, HOST_INT_STATUS, status);
1603
1604         return IRQ_HANDLED;
1605 }
1606
1607
1608 /*
1609  */
1610
1611 static snd_pcm_hardware_t snd_m3_playback =
1612 {
1613         .info =                 (SNDRV_PCM_INFO_MMAP |
1614                                  SNDRV_PCM_INFO_INTERLEAVED |
1615                                  SNDRV_PCM_INFO_MMAP_VALID |
1616                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1617                                  /*SNDRV_PCM_INFO_PAUSE |*/
1618                                  SNDRV_PCM_INFO_RESUME),
1619         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1620         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1621         .rate_min =             8000,
1622         .rate_max =             48000,
1623         .channels_min =         1,
1624         .channels_max =         2,
1625         .buffer_bytes_max =     (512*1024),
1626         .period_bytes_min =     64,
1627         .period_bytes_max =     (512*1024),
1628         .periods_min =          1,
1629         .periods_max =          1024,
1630 };
1631
1632 static snd_pcm_hardware_t snd_m3_capture =
1633 {
1634         .info =                 (SNDRV_PCM_INFO_MMAP |
1635                                  SNDRV_PCM_INFO_INTERLEAVED |
1636                                  SNDRV_PCM_INFO_MMAP_VALID |
1637                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1638                                  /*SNDRV_PCM_INFO_PAUSE |*/
1639                                  SNDRV_PCM_INFO_RESUME),
1640         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1641         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1642         .rate_min =             8000,
1643         .rate_max =             48000,
1644         .channels_min =         1,
1645         .channels_max =         2,
1646         .buffer_bytes_max =     (512*1024),
1647         .period_bytes_min =     64,
1648         .period_bytes_max =     (512*1024),
1649         .periods_min =          1,
1650         .periods_max =          1024,
1651 };
1652
1653
1654 /*
1655  */
1656
1657 static int
1658 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1659 {
1660         int i;
1661         m3_dma_t *s;
1662
1663         spin_lock_irq(&chip->reg_lock);
1664         for (i = 0; i < chip->num_substreams; i++) {
1665                 s = &chip->substreams[i];
1666                 if (! s->opened)
1667                         goto __found;
1668         }
1669         spin_unlock_irq(&chip->reg_lock);
1670         return -ENOMEM;
1671 __found:
1672         s->opened = 1;
1673         s->running = 0;
1674         spin_unlock_irq(&chip->reg_lock);
1675
1676         subs->runtime->private_data = s;
1677         s->substream = subs;
1678
1679         /* set list owners */
1680         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1681                 s->index_list[0] = &chip->mixer_list;
1682         } else
1683                 s->index_list[0] = &chip->adc1_list;
1684         s->index_list[1] = &chip->msrc_list;
1685         s->index_list[2] = &chip->dma_list;
1686
1687         return 0;
1688 }
1689
1690 static void
1691 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1692 {
1693         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1694
1695         if (s == NULL)
1696                 return; /* not opened properly */
1697
1698         spin_lock_irq(&chip->reg_lock);
1699         if (s->substream && s->running)
1700                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1701         if (s->in_lists) {
1702                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1703                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1704                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1705                 s->in_lists = 0;
1706         }
1707         s->running = 0;
1708         s->opened = 0;
1709         spin_unlock_irq(&chip->reg_lock);
1710 }
1711
1712 static int
1713 snd_m3_playback_open(snd_pcm_substream_t *subs)
1714 {
1715         m3_t *chip = snd_pcm_substream_chip(subs);
1716         snd_pcm_runtime_t *runtime = subs->runtime;
1717         int err;
1718
1719         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1720                 return err;
1721
1722         runtime->hw = snd_m3_playback;
1723         snd_pcm_set_sync(subs);
1724
1725         return 0;
1726 }
1727
1728 static int
1729 snd_m3_playback_close(snd_pcm_substream_t *subs)
1730 {
1731         m3_t *chip = snd_pcm_substream_chip(subs);
1732
1733         snd_m3_substream_close(chip, subs);
1734         return 0;
1735 }
1736
1737 static int
1738 snd_m3_capture_open(snd_pcm_substream_t *subs)
1739 {
1740         m3_t *chip = snd_pcm_substream_chip(subs);
1741         snd_pcm_runtime_t *runtime = subs->runtime;
1742         int err;
1743
1744         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1745                 return err;
1746
1747         runtime->hw = snd_m3_capture;
1748         snd_pcm_set_sync(subs);
1749
1750         return 0;
1751 }
1752
1753 static int
1754 snd_m3_capture_close(snd_pcm_substream_t *subs)
1755 {
1756         m3_t *chip = snd_pcm_substream_chip(subs);
1757
1758         snd_m3_substream_close(chip, subs);
1759         return 0;
1760 }
1761
1762 /*
1763  * create pcm instance
1764  */
1765
1766 static snd_pcm_ops_t snd_m3_playback_ops = {
1767         .open =         snd_m3_playback_open,
1768         .close =        snd_m3_playback_close,
1769         .ioctl =        snd_pcm_lib_ioctl,
1770         .hw_params =    snd_m3_pcm_hw_params,
1771         .hw_free =      snd_m3_pcm_hw_free,
1772         .prepare =      snd_m3_pcm_prepare,
1773         .trigger =      snd_m3_pcm_trigger,
1774         .pointer =      snd_m3_pcm_pointer,
1775 };
1776
1777 static snd_pcm_ops_t snd_m3_capture_ops = {
1778         .open =         snd_m3_capture_open,
1779         .close =        snd_m3_capture_close,
1780         .ioctl =        snd_pcm_lib_ioctl,
1781         .hw_params =    snd_m3_pcm_hw_params,
1782         .hw_free =      snd_m3_pcm_hw_free,
1783         .prepare =      snd_m3_pcm_prepare,
1784         .trigger =      snd_m3_pcm_trigger,
1785         .pointer =      snd_m3_pcm_pointer,
1786 };
1787
1788 static int __devinit
1789 snd_m3_pcm(m3_t * chip, int device)
1790 {
1791         snd_pcm_t *pcm;
1792         int err;
1793
1794         err = snd_pcm_new(chip->card, chip->card->driver, device,
1795                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1796         if (err < 0)
1797                 return err;
1798
1799         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1800         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1801
1802         pcm->private_data = chip;
1803         pcm->info_flags = 0;
1804         strcpy(pcm->name, chip->card->driver);
1805         chip->pcm = pcm;
1806
1807         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1808                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1809
1810         return 0;
1811 }
1812
1813
1814 /*
1815  * ac97 interface
1816  */
1817
1818 /*
1819  * Wait for the ac97 serial bus to be free.
1820  * return nonzero if the bus is still busy.
1821  */
1822 static int snd_m3_ac97_wait(m3_t *chip)
1823 {
1824         int i = 10000;
1825
1826         do {
1827                 if (! (snd_m3_inb(chip, 0x30) & 1))
1828                         return 0;
1829         } while (i-- > 0);
1830
1831         snd_printk("ac97 serial bus busy\n");
1832         return 1;
1833 }
1834
1835 static unsigned short
1836 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1837 {
1838         m3_t *chip = ac97->private_data;
1839         unsigned short ret = 0;
1840         unsigned long flags;
1841
1842         spin_lock_irqsave(&chip->reg_lock, flags);
1843         if (snd_m3_ac97_wait(chip))
1844                 goto __error;
1845         snd_m3_outb(chip, 0x80 | (reg & 0x7f), 0x30);
1846         if (snd_m3_ac97_wait(chip))
1847                 goto __error;
1848         ret = snd_m3_inw(chip, 0x32);
1849 __error:
1850         spin_unlock_irqrestore(&chip->reg_lock, flags);
1851         return ret;
1852 }
1853
1854 static void
1855 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1856 {
1857         m3_t *chip = ac97->private_data;
1858         unsigned long flags;
1859
1860         spin_lock_irqsave(&chip->reg_lock, flags);
1861         if (snd_m3_ac97_wait(chip))
1862                 goto __error;
1863         snd_m3_outw(chip, val, 0x32);
1864         snd_m3_outb(chip, reg & 0x7f, 0x30);
1865 __error:
1866         spin_unlock_irqrestore(&chip->reg_lock, flags);
1867 }
1868
1869
1870 static void snd_m3_remote_codec_config(int io, int isremote)
1871 {
1872         isremote = isremote ? 1 : 0;
1873
1874         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1875              io + RING_BUS_CTRL_B);
1876         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1877              io + SDO_OUT_DEST_CTRL);
1878         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1879              io + SDO_IN_DEST_CTRL);
1880 }
1881
1882 /*
1883  * hack, returns non zero on err
1884  */
1885 static int snd_m3_try_read_vendor(m3_t *chip)
1886 {
1887         u16 ret;
1888
1889         if (snd_m3_ac97_wait(chip))
1890                 return 1;
1891
1892         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1893
1894         if (snd_m3_ac97_wait(chip))
1895                 return 1;
1896
1897         ret = snd_m3_inw(chip, 0x32);
1898
1899         return (ret == 0) || (ret == 0xffff);
1900 }
1901
1902 static void snd_m3_ac97_reset(m3_t *chip)
1903 {
1904         u16 dir;
1905         int delay1 = 0, delay2 = 0, i;
1906         int io = chip->iobase;
1907
1908         if (chip->allegro_flag) {
1909                 /*
1910                  * the onboard codec on the allegro seems
1911                  * to want to wait a very long time before
1912                  * coming back to life
1913                  */
1914                 delay1 = 50;
1915                 delay2 = 800;
1916         } else {
1917                 /* maestro3 */
1918                 delay1 = 20;
1919                 delay2 = 500;
1920         }
1921
1922         for (i = 0; i < 5; i++) {
1923                 dir = inw(io + GPIO_DIRECTION);
1924                 if (! chip->quirk || ! chip->quirk->irda_workaround)
1925                         dir |= 0x10; /* assuming pci bus master? */
1926
1927                 snd_m3_remote_codec_config(io, 0);
1928
1929                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1930                 udelay(20);
1931
1932                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1933                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1934                 outw(0, io + GPIO_DATA);
1935                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1936
1937                 set_current_state(TASK_UNINTERRUPTIBLE);
1938                 schedule_timeout((delay1 * HZ) / 1000);
1939
1940                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1941                 udelay(5);
1942                 /* ok, bring back the ac-link */
1943                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1944                 outw(~0, io + GPIO_MASK);
1945
1946                 set_current_state(TASK_UNINTERRUPTIBLE);
1947                 schedule_timeout((delay2 * HZ) / 1000);
1948
1949                 if (! snd_m3_try_read_vendor(chip))
1950                         break;
1951
1952                 delay1 += 10;
1953                 delay2 += 100;
1954
1955                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
1956                            delay1, delay2);
1957         }
1958
1959 #if 0
1960         /* more gung-ho reset that doesn't
1961          * seem to work anywhere :)
1962          */
1963         tmp = inw(io + RING_BUS_CTRL_A);
1964         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
1965         big_mdelay(20);
1966         outw(tmp, io + RING_BUS_CTRL_A);
1967         big_mdelay(50);
1968 #endif
1969 }
1970
1971 static int __devinit snd_m3_mixer(m3_t *chip)
1972 {
1973         ac97_bus_t *pbus;
1974         ac97_template_t ac97;
1975         int err;
1976         static ac97_bus_ops_t ops = {
1977                 .write = snd_m3_ac97_write,
1978                 .read = snd_m3_ac97_read,
1979         };
1980
1981         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1982                 return err;
1983
1984         memset(&ac97, 0, sizeof(ac97));
1985         ac97.private_data = chip;
1986         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1987                 return err;
1988
1989         /* seems ac97 PCM needs initialization.. hack hack.. */
1990         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
1991         set_current_state(TASK_UNINTERRUPTIBLE);
1992         schedule_timeout(HZ / 10);
1993         snd_ac97_write(chip->ac97, AC97_PCM, 0);
1994
1995         return 0;
1996 }
1997
1998
1999 /*
2000  * DSP Code images
2001  */
2002
2003 static u16 assp_kernel_image[] __devinitdata = {
2004     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2005     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2006     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2007     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2008     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2009     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2010     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2011     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2012     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2013     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2014     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2015     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2016     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2017     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2018     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2019     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2020     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2021     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2022     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2023     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2024     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2025     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2026     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2027     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2028     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2029     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2030     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2031     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2032     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2033     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2034     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2035     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2036     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2037     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2038     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2039     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2040     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2041     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2042     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2043     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2044     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2045     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2046     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2047     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2048     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2049     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2050     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2051     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2052     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2053     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2054     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2055     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2056     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2057     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2058     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2059     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2060     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2061     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2062     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2063     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2064     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2065     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2066     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2067     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2068     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2069     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2070     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2071     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2072     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2073     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2074     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2075     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2076     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2077     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2078     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2079     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2080     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2081     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2082     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2083     0xBE3A,
2084 };
2085
2086 /*
2087  * Mini sample rate converter code image
2088  * that is to be loaded at 0x400 on the DSP.
2089  */
2090 static u16 assp_minisrc_image[] __devinitdata = {
2091
2092     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2093     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2094     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2095     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2096     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2097     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2098     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2099     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2100     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2101     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2102     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2103     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2104     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2105     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2106     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2107     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2108     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2109     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2110     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2111     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2112     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2113     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2114     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2115     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2116     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2117     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2118     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2119     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2120     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2121     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2122     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2123     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2124     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2125 };
2126
2127
2128 /*
2129  * initialize ASSP
2130  */
2131
2132 #define MINISRC_LPF_LEN 10
2133 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2134         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2135         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2136 };
2137
2138 static void __devinit snd_m3_assp_init(m3_t *chip)
2139 {
2140         unsigned int i;
2141
2142         /* zero kernel data */
2143         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2144                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2145                                   KDATA_BASE_ADDR + i, 0);
2146
2147         /* zero mixer data? */
2148         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2149                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2150                                   KDATA_BASE_ADDR2 + i, 0);
2151
2152         /* init dma pointer */
2153         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2154                           KDATA_CURRENT_DMA,
2155                           KDATA_DMA_XFER0);
2156
2157         /* write kernel into code memory.. */
2158         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2159                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2160                                   REV_B_CODE_MEMORY_BEGIN + i,
2161                                   assp_kernel_image[i]);
2162         }
2163
2164         /*
2165          * We only have this one client and we know that 0x400
2166          * is free in our kernel's mem map, so lets just
2167          * drop it there.  It seems that the minisrc doesn't
2168          * need vectors, so we won't bother with them..
2169          */
2170         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2171                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2172                                   0x400 + i,
2173                                   assp_minisrc_image[i]);
2174         }
2175
2176         /*
2177          * write the coefficients for the low pass filter?
2178          */
2179         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2180                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2181                                   0x400 + MINISRC_COEF_LOC + i,
2182                                   minisrc_lpf[i]);
2183         }
2184
2185         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2186                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2187                           0x8000);
2188
2189         /*
2190          * the minisrc is the only thing on
2191          * our task list..
2192          */
2193         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2194                           KDATA_TASK0,
2195                           0x400);
2196
2197         /*
2198          * init the mixer number..
2199          */
2200
2201         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2202                           KDATA_MIXER_TASK_NUMBER,0);
2203
2204         /*
2205          * EXTREME KERNEL MASTER VOLUME
2206          */
2207         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2208                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2209         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2210                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2211
2212         chip->mixer_list.curlen = 0;
2213         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2214         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2215         chip->adc1_list.curlen = 0;
2216         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2217         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2218         chip->dma_list.curlen = 0;
2219         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2220         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2221         chip->msrc_list.curlen = 0;
2222         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2223         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2224 }
2225
2226
2227 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2228 {
2229         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2230                                MINISRC_IN_BUFFER_SIZE / 2 +
2231                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2232         int address, i;
2233
2234         /*
2235          * the revb memory map has 0x1100 through 0x1c00
2236          * free.
2237          */
2238
2239         /*
2240          * align instance address to 256 bytes so that it's
2241          * shifted list address is aligned.
2242          * list address = (mem address >> 1) >> 7;
2243          */
2244         data_bytes = (data_bytes + 255) & ~255;
2245         address = 0x1100 + ((data_bytes/2) * index);
2246
2247         if ((address + (data_bytes/2)) >= 0x1c00) {
2248                 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2249                            data_bytes, index, address);
2250                 return -ENOMEM;
2251         }
2252
2253         s->number = index;
2254         s->inst.code = 0x400;
2255         s->inst.data = address;
2256
2257         for (i = data_bytes / 2; i > 0; address++, i--) {
2258                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2259                                   address, 0);
2260         }
2261
2262         return 0;
2263 }
2264
2265
2266 /*
2267  * this works for the reference board, have to find
2268  * out about others
2269  *
2270  * this needs more magic for 4 speaker, but..
2271  */
2272 static void
2273 snd_m3_amp_enable(m3_t *chip, int enable)
2274 {
2275         int io = chip->iobase;
2276         u16 gpo, polarity;
2277
2278         if (! chip->external_amp)
2279                 return;
2280
2281         polarity = enable ? 0 : 1;
2282         polarity = polarity << chip->amp_gpio;
2283         gpo = 1 << chip->amp_gpio;
2284
2285         outw(~gpo, io + GPIO_MASK);
2286
2287         outw(inw(io + GPIO_DIRECTION) | gpo,
2288              io + GPIO_DIRECTION);
2289
2290         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2291              io + GPIO_DATA);
2292
2293         outw(0xffff, io + GPIO_MASK);
2294 }
2295
2296 static int
2297 snd_m3_chip_init(m3_t *chip)
2298 {
2299         struct pci_dev *pcidev = chip->pci;
2300         u32 n;
2301         u16 w;
2302         u8 t; /* makes as much sense as 'n', no? */
2303
2304         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2305         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2306                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2307                DISABLE_LEGACY);
2308         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2309
2310         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2311         n &= REDUCED_DEBOUNCE;
2312         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2313         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2314
2315         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2316         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2317         n &= ~INT_CLK_SELECT;
2318         if (!chip->allegro_flag) {
2319                 n &= ~INT_CLK_MULT_ENABLE;
2320                 n |= INT_CLK_SRC_NOT_PCI;
2321         }
2322         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2323         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2324
2325         if (chip->allegro_flag) {
2326                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2327                 n |= IN_CLK_12MHZ_SELECT;
2328                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2329         }
2330
2331         t = inb(chip->iobase + ASSP_CONTROL_A);
2332         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2333         t |= ASSP_CLK_49MHZ_SELECT;
2334         t |= ASSP_0_WS_ENABLE;
2335         outb(t, chip->iobase + ASSP_CONTROL_A);
2336
2337         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2338
2339         return 0;
2340 }
2341
2342 static void
2343 snd_m3_enable_ints(m3_t *chip)
2344 {
2345         unsigned long io = chip->iobase;
2346
2347         /* TODO: MPU401 not supported yet */
2348         outw(ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
2349         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2350              io + ASSP_CONTROL_C);
2351 }
2352
2353
2354 /*
2355  */
2356
2357 static int snd_m3_free(m3_t *chip)
2358 {
2359         m3_dma_t *s;
2360         int i;
2361
2362         if (chip->substreams) {
2363                 spin_lock_irq(&chip->reg_lock);
2364                 for (i = 0; i < chip->num_substreams; i++) {
2365                         s = &chip->substreams[i];
2366                         /* check surviving pcms; this should not happen though.. */
2367                         if (s->substream && s->running)
2368                                 snd_m3_pcm_stop(chip, s, s->substream);
2369                 }
2370                 spin_unlock_irq(&chip->reg_lock);
2371                 kfree(chip->substreams);
2372         }
2373         if (chip->iobase) {
2374                 snd_m3_outw(chip, HOST_INT_CTRL, 0); /* disable ints */
2375         }
2376
2377 #ifdef CONFIG_PM
2378         if (chip->suspend_mem)
2379                 vfree(chip->suspend_mem);
2380 #endif
2381
2382         if (chip->irq >= 0) {
2383                 synchronize_irq(chip->irq);
2384                 free_irq(chip->irq, (void *)chip);
2385         }
2386
2387         if (chip->iobase)
2388                 pci_release_regions(chip->pci);
2389
2390         kfree(chip);
2391         return 0;
2392 }
2393
2394
2395 /*
2396  * APM support
2397  */
2398 #ifdef CONFIG_PM
2399 static int m3_suspend(snd_card_t *card, unsigned int state)
2400 {
2401         m3_t *chip = card->pm_private_data;
2402         int i, index;
2403
2404         if (chip->suspend_mem == NULL)
2405                 return 0;
2406
2407         snd_pcm_suspend_all(chip->pcm);
2408         snd_ac97_suspend(chip->ac97);
2409
2410         big_mdelay(10); /* give the assp a chance to idle.. */
2411
2412         snd_m3_assp_halt(chip);
2413
2414         /* save dsp image */
2415         index = 0;
2416         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2417                 chip->suspend_mem[index++] =
2418                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2419         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2420                 chip->suspend_mem[index++] =
2421                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2422
2423         /* power down apci registers */
2424         snd_m3_outw(chip, 0xffff, 0x54);
2425         snd_m3_outw(chip, 0xffff, 0x56);
2426         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2427         return 0;
2428 }
2429
2430 static int m3_resume(snd_card_t *card, unsigned int state)
2431 {
2432         m3_t *chip = card->pm_private_data;
2433         int i, index;
2434
2435         if (chip->suspend_mem == NULL)
2436                 return 0;
2437
2438         pci_set_master(chip->pci);
2439
2440         /* first lets just bring everything back. .*/
2441         snd_m3_outw(chip, 0, 0x54);
2442         snd_m3_outw(chip, 0, 0x56);
2443
2444         snd_m3_chip_init(chip);
2445         snd_m3_assp_halt(chip);
2446         snd_m3_ac97_reset(chip);
2447
2448         /* restore dsp image */
2449         index = 0;
2450         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2451                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2452                                   chip->suspend_mem[index++]);
2453         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2454                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2455                                   chip->suspend_mem[index++]);
2456
2457         /* tell the dma engine to restart itself */
2458         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2459                           KDATA_DMA_ACTIVE, 0);
2460
2461         /* restore ac97 registers */
2462         snd_ac97_resume(chip->ac97);
2463
2464         snd_m3_assp_continue(chip);
2465         snd_m3_enable_ints(chip);
2466         snd_m3_amp_enable(chip, 1);
2467
2468         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2469         return 0;
2470 }
2471 #endif /* CONFIG_PM */
2472
2473
2474 /*
2475  */
2476
2477 static int snd_m3_dev_free(snd_device_t *device)
2478 {
2479         m3_t *chip = device->device_data;
2480         return snd_m3_free(chip);
2481 }
2482
2483 static int __devinit
2484 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2485               int enable_amp,
2486               int amp_gpio,
2487               m3_t **chip_ret)
2488 {
2489         m3_t *chip;
2490         int i, err;
2491         struct m3_quirk *quirk;
2492         u16 subsystem_vendor, subsystem_device;
2493         static snd_device_ops_t ops = {
2494                 .dev_free =     snd_m3_dev_free,
2495         };
2496
2497         *chip_ret = NULL;
2498
2499         if (pci_enable_device(pci))
2500                 return -EIO;
2501
2502         /* check, if we can restrict PCI DMA transfers to 28 bits */
2503         if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2504             pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2505                 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2506                 return -ENXIO;
2507         }
2508
2509         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2510         if (chip == NULL)
2511                 return -ENOMEM;
2512
2513         spin_lock_init(&chip->reg_lock);
2514         switch (pci->device) {
2515         case PCI_DEVICE_ID_ESS_ALLEGRO:
2516         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2517         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2518         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2519                 chip->allegro_flag = 1;
2520                 break;
2521         }
2522
2523         chip->card = card;
2524         chip->pci = pci;
2525         chip->irq = -1;
2526
2527         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2528         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2529
2530         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2531                 if (subsystem_vendor == quirk->vendor &&
2532                     subsystem_device == quirk->device) {
2533                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2534                         chip->quirk = quirk;
2535                         break;
2536                 }
2537         }
2538
2539         chip->external_amp = enable_amp;
2540         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2541                 chip->amp_gpio = amp_gpio;
2542         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2543                 chip->amp_gpio = chip->quirk->amp_gpio;
2544         else if (chip->allegro_flag)
2545                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2546         else /* presumably this is for all 'maestro3's.. */
2547                 chip->amp_gpio = GPO_EXT_AMP_M3;
2548
2549         chip->num_substreams = NR_DSPS;
2550         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2551         if (chip->substreams == NULL) {
2552                 kfree(chip);
2553                 return -ENOMEM;
2554         }
2555         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2556
2557         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2558                 snd_m3_free(chip);
2559                 return err;
2560         }
2561         chip->iobase = pci_resource_start(pci, 0);
2562
2563         /* just to be sure */
2564         pci_set_master(pci);
2565
2566         snd_m3_chip_init(chip);
2567         snd_m3_assp_halt(chip);
2568
2569         snd_m3_ac97_reset(chip);
2570
2571         snd_m3_assp_init(chip);
2572         snd_m3_amp_enable(chip, 1);
2573
2574         if ((err = snd_m3_mixer(chip)) < 0) {
2575                 snd_m3_free(chip);
2576                 return err;
2577         }
2578
2579         for (i = 0; i < chip->num_substreams; i++) {
2580                 m3_dma_t *s = &chip->substreams[i];
2581                 s->chip = chip;
2582                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) {
2583                         snd_m3_free(chip);
2584                         return err;
2585                 }
2586         }
2587
2588         if ((err = snd_m3_pcm(chip, 0)) < 0) {
2589                 snd_m3_free(chip);
2590                 return err;
2591         }
2592
2593         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2594                         card->driver, (void *)chip)) {
2595                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2596                 snd_m3_free(chip);
2597                 return -ENOMEM;
2598         }
2599         chip->irq = pci->irq;
2600
2601 #ifdef CONFIG_PM
2602         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2603         if (chip->suspend_mem == NULL)
2604                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2605         else
2606                 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip);
2607 #endif
2608
2609         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2610                 snd_m3_free(chip);
2611                 return err;
2612         }
2613
2614         snd_m3_enable_ints(chip);
2615         snd_m3_assp_continue(chip);
2616
2617         snd_card_set_dev(card, &pci->dev);
2618
2619         *chip_ret = chip;
2620
2621         return 0;
2622 }
2623
2624 /*
2625  */
2626 static int __devinit
2627 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2628 {
2629         static int dev;
2630         snd_card_t *card;
2631         m3_t *chip;
2632         int err;
2633
2634         /* don't pick up modems */
2635         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2636                 return -ENODEV;
2637
2638         if (dev >= SNDRV_CARDS)
2639                 return -ENODEV;
2640         if (!enable[dev]) {
2641                 dev++;
2642                 return -ENOENT;
2643         }
2644
2645         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2646         if (card == NULL)
2647                 return -ENOMEM;
2648
2649         switch (pci->device) {
2650         case PCI_DEVICE_ID_ESS_ALLEGRO:
2651         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2652                 strcpy(card->driver, "Allegro");
2653                 break;
2654         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2655         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2656                 strcpy(card->driver, "Canyon3D-2");
2657                 break;
2658         default:
2659                 strcpy(card->driver, "Maestro3");
2660                 break;
2661         }
2662
2663         if ((err = snd_m3_create(card, pci,
2664                                  external_amp[dev],
2665                                  amp_gpio[dev],
2666                                  &chip)) < 0) {
2667                 snd_card_free(card);
2668                 return err;
2669         }
2670
2671         sprintf(card->shortname, "ESS %s PCI", card->driver);
2672         sprintf(card->longname, "%s at 0x%lx, irq %d",
2673                 card->shortname, chip->iobase, chip->irq);
2674
2675         if ((err = snd_card_register(card)) < 0) {
2676                 snd_card_free(card);
2677                 return err;
2678         }
2679
2680 #if 0 /* TODO: not supported yet */
2681         /* TODO enable midi irq and i/o */
2682         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2683                                   chip->iobase + MPU401_DATA_PORT, 1,
2684                                   chip->irq, 0, &chip->rmidi);
2685         if (err < 0)
2686                 printk(KERN_WARNING "maestro3: no midi support.\n");
2687 #endif
2688
2689         pci_set_drvdata(pci, card);
2690         dev++;
2691         return 0;
2692 }
2693
2694 static void __devexit snd_m3_remove(struct pci_dev *pci)
2695 {
2696         snd_card_free(pci_get_drvdata(pci));
2697         pci_set_drvdata(pci, NULL);
2698 }
2699
2700 static struct pci_driver driver = {
2701         .name = "Maestro3",
2702         .id_table = snd_m3_ids,
2703         .probe = snd_m3_probe,
2704         .remove = __devexit_p(snd_m3_remove),
2705         SND_PCI_PM_CALLBACKS
2706 };
2707
2708 static int __init alsa_card_m3_init(void)
2709 {
2710         return pci_module_init(&driver);
2711 }
2712
2713 static void __exit alsa_card_m3_exit(void)
2714 {
2715         pci_unregister_driver(&driver);
2716 }
2717
2718 module_init(alsa_card_m3_init)
2719 module_exit(alsa_card_m3_exit)