sound/pci/rme96.c

   1 /*
   2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   3  *   interfaces
   4  *
   5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   6  *
   7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   8  *      code.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <sound/driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/pci.h>
  31 #include <linux/slab.h>
  32
  33 #include <sound/core.h>
  34 #include <sound/info.h>
  35 #include <sound/control.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/asoundef.h>
  39 #define SNDRV_GET_ID
  40 #include <sound/initval.h>
  41
  42 #include <asm/io.h>
  43
  44 /* note, two last pcis should be equal, it is not a bug */
  45
  46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  48                    "Digi96/8 PAD");
  49 MODULE_LICENSE("GPL");
  50 MODULE_CLASSES("{sound}");
  51 MODULE_DEVICES("{{RME,Digi96},"
  52                 "{RME,Digi96/8},"
  53                 "{RME,Digi96/8 PRO},"
  54                 "{RME,Digi96/8 PST},"
  55                 "{RME,Digi96/8 PAD}}");
  56
  57 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  58 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  59 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  60
  61 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  62 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  63 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  64 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
  65 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  66 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  67 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  68 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  69 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  70
  71 /*
  72  * Defines for RME Digi96 series, from internal RME reference documents
  73  * dated 12.01.00
  74  */
  75
  76 #define RME96_SPDIF_NCHANNELS 2
  77
  78 /* Playback and capture buffer size */
  79 #define RME96_BUFFER_SIZE 0x10000
  80
  81 /* IO area size */
  82 #define RME96_IO_SIZE 0x60000
  83
  84 /* IO area offsets */
  85 #define RME96_IO_PLAY_BUFFER      0x0
  86 #define RME96_IO_REC_BUFFER       0x10000
  87 #define RME96_IO_CONTROL_REGISTER 0x20000
  88 #define RME96_IO_ADDITIONAL_REG   0x20004
  89 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  90 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  91 #define RME96_IO_SET_PLAY_POS     0x40000
  92 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  93 #define RME96_IO_SET_REC_POS      0x50000
  94 #define RME96_IO_RESET_REC_POS    0x5FFFC
  95 #define RME96_IO_GET_PLAY_POS     0x20000
  96 #define RME96_IO_GET_REC_POS      0x30000
  97
  98 /* Write control register bits */
  99 #define RME96_WCR_START     (1 << 0)
 100 #define RME96_WCR_START_2   (1 << 1)
 101 #define RME96_WCR_GAIN_0    (1 << 2)
 102 #define RME96_WCR_GAIN_1    (1 << 3)
 103 #define RME96_WCR_MODE24    (1 << 4)
 104 #define RME96_WCR_MODE24_2  (1 << 5)
 105 #define RME96_WCR_BM        (1 << 6)
 106 #define RME96_WCR_BM_2      (1 << 7)
 107 #define RME96_WCR_ADAT      (1 << 8)
 108 #define RME96_WCR_FREQ_0    (1 << 9)
 109 #define RME96_WCR_FREQ_1    (1 << 10)
 110 #define RME96_WCR_DS        (1 << 11)
 111 #define RME96_WCR_PRO       (1 << 12)
 112 #define RME96_WCR_EMP       (1 << 13)
 113 #define RME96_WCR_SEL       (1 << 14)
 114 #define RME96_WCR_MASTER    (1 << 15)
 115 #define RME96_WCR_PD        (1 << 16)
 116 #define RME96_WCR_INP_0     (1 << 17)
 117 #define RME96_WCR_INP_1     (1 << 18)
 118 #define RME96_WCR_THRU_0    (1 << 19)
 119 #define RME96_WCR_THRU_1    (1 << 20)
 120 #define RME96_WCR_THRU_2    (1 << 21)
 121 #define RME96_WCR_THRU_3    (1 << 22)
 122 #define RME96_WCR_THRU_4    (1 << 23)
 123 #define RME96_WCR_THRU_5    (1 << 24)
 124 #define RME96_WCR_THRU_6    (1 << 25)
 125 #define RME96_WCR_THRU_7    (1 << 26)
 126 #define RME96_WCR_DOLBY     (1 << 27)
 127 #define RME96_WCR_MONITOR_0 (1 << 28)
 128 #define RME96_WCR_MONITOR_1 (1 << 29)
 129 #define RME96_WCR_ISEL      (1 << 30)
 130 #define RME96_WCR_IDIS      (1 << 31)
 131
 132 #define RME96_WCR_BITPOS_GAIN_0 2
 133 #define RME96_WCR_BITPOS_GAIN_1 3
 134 #define RME96_WCR_BITPOS_FREQ_0 9
 135 #define RME96_WCR_BITPOS_FREQ_1 10
 136 #define RME96_WCR_BITPOS_INP_0 17
 137 #define RME96_WCR_BITPOS_INP_1 18
 138 #define RME96_WCR_BITPOS_MONITOR_0 28
 139 #define RME96_WCR_BITPOS_MONITOR_1 29
 140
 141 /* Read control register bits */
 142 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 143 #define RME96_RCR_IRQ_2     (1 << 16)
 144 #define RME96_RCR_T_OUT     (1 << 17)
 145 #define RME96_RCR_DEV_ID_0  (1 << 21)
 146 #define RME96_RCR_DEV_ID_1  (1 << 22)
 147 #define RME96_RCR_LOCK      (1 << 23)
 148 #define RME96_RCR_VERF      (1 << 26)
 149 #define RME96_RCR_F0        (1 << 27)
 150 #define RME96_RCR_F1        (1 << 28)
 151 #define RME96_RCR_F2        (1 << 29)
 152 #define RME96_RCR_AUTOSYNC  (1 << 30)
 153 #define RME96_RCR_IRQ       (1 << 31)
 154
 155 #define RME96_RCR_BITPOS_F0 27
 156 #define RME96_RCR_BITPOS_F1 28
 157 #define RME96_RCR_BITPOS_F2 29
 158
 159 /* Additonal register bits */
 160 #define RME96_AR_WSEL       (1 << 0)
 161 #define RME96_AR_ANALOG     (1 << 1)
 162 #define RME96_AR_FREQPAD_0  (1 << 2)
 163 #define RME96_AR_FREQPAD_1  (1 << 3)
 164 #define RME96_AR_FREQPAD_2  (1 << 4)
 165 #define RME96_AR_PD2        (1 << 5)
 166 #define RME96_AR_DAC_EN     (1 << 6)
 167 #define RME96_AR_CLATCH     (1 << 7)
 168 #define RME96_AR_CCLK       (1 << 8)
 169 #define RME96_AR_CDATA      (1 << 9)
 170
 171 #define RME96_AR_BITPOS_F0 2
 172 #define RME96_AR_BITPOS_F1 3
 173 #define RME96_AR_BITPOS_F2 4
 174
 175 /* Monitor tracks */
 176 #define RME96_MONITOR_TRACKS_1_2 0
 177 #define RME96_MONITOR_TRACKS_3_4 1
 178 #define RME96_MONITOR_TRACKS_5_6 2
 179 #define RME96_MONITOR_TRACKS_7_8 3
 180
 181 /* Attenuation */
 182 #define RME96_ATTENUATION_0 0
 183 #define RME96_ATTENUATION_6 1
 184 #define RME96_ATTENUATION_12 2
 185 #define RME96_ATTENUATION_18 3
 186
 187 /* Input types */
 188 #define RME96_INPUT_OPTICAL 0
 189 #define RME96_INPUT_COAXIAL 1
 190 #define RME96_INPUT_INTERNAL 2
 191 #define RME96_INPUT_XLR 3
 192 #define RME96_INPUT_ANALOG 4
 193
 194 /* Clock modes */
 195 #define RME96_CLOCKMODE_SLAVE 0
 196 #define RME96_CLOCKMODE_MASTER 1
 197 #define RME96_CLOCKMODE_WORDCLOCK 2
 198
 199 /* Block sizes in bytes */
 200 #define RME96_SMALL_BLOCK_SIZE 2048
 201 #define RME96_LARGE_BLOCK_SIZE 8192
 202
 203 /* Volume control */
 204 #define RME96_AD1852_VOL_BITS 14
 205 #define RME96_AD1855_VOL_BITS 10
 206
 207 /*
 208  * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
 209  * therefore #ifndef is used.
 210  */
 211 #ifndef PCI_VENDOR_ID_XILINX
 212 #define PCI_VENDOR_ID_XILINX 0x10ee
 213 #endif
 214 #ifndef PCI_DEVICE_ID_DIGI96
 215 #define PCI_DEVICE_ID_DIGI96 0x3fc0
 216 #endif
 217 #ifndef PCI_DEVICE_ID_DIGI96_8
 218 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1
 219 #endif
 220 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO
 221 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
 222 #endif
 223 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
 224 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
 225 #endif
 226
 227 typedef struct snd_rme96 {
 228         spinlock_t    lock;
 229         int irq;
 230         unsigned long port;
 231         struct resource *res_port;
 232         unsigned long iobase;
 233
 234         u32 wcreg;    /* cached write control register value */
 235         u32 wcreg_spdif;                /* S/PDIF setup */
 236         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 237         u32 rcreg;    /* cached read control register value */
 238         u32 areg;     /* cached additional register value */
 239         u16 vol[2]; /* cached volume of analog output */
 240
 241         u8 rev; /* card revision number */
 242
 243         snd_pcm_substream_t *playback_substream;
 244         snd_pcm_substream_t *capture_substream;
 245
 246         int playback_frlog; /* log2 of framesize */
 247         int capture_frlog;
 248
 249         size_t playback_periodsize; /* in bytes, zero if not used */
 250         size_t capture_periodsize; /* in bytes, zero if not used */
 251
 252         snd_pcm_uframes_t playback_last_appl_ptr;
 253         size_t playback_ptr;
 254         size_t capture_ptr;
 255
 256         snd_card_t         *card;
 257         snd_pcm_t          *spdif_pcm;
 258         snd_pcm_t          *adat_pcm;
 259         struct pci_dev     *pci;
 260         snd_kcontrol_t     *spdif_ctl;
 261 } rme96_t;
 262
 263 static struct pci_device_id snd_rme96_ids[] = {
 264         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
 265           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 266         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
 267           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 268         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
 269           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 270         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
 271           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 272         { 0, }
 273 };
 274
 275 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 276
 277 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 278 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 279 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
 280 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
 281                                      (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
 282 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 283 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 284                                   ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
 285 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 286
 287 static int
 288 snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
 289
 290 static int
 291 snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
 292
 293 static int
 294 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
 295                            int cmd);
 296
 297 static int
 298 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
 299                           int cmd);
 300
 301 static snd_pcm_uframes_t
 302 snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
 303
 304 static snd_pcm_uframes_t
 305 snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
 306
 307 static void __devinit
 308 snd_rme96_proc_init(rme96_t *rme96);
 309
 310 static int
 311 snd_rme96_create_switches(snd_card_t *card,
 312                           rme96_t *rme96);
 313
 314 static int
 315 snd_rme96_getinputtype(rme96_t *rme96);
 316
 317 static inline unsigned int
 318 snd_rme96_playback_ptr(rme96_t *rme96)
 319 {
 320         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 321                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 322 }
 323
 324 static inline unsigned int
 325 snd_rme96_capture_ptr(rme96_t *rme96)
 326 {
 327         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 328                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 329 }
 330
 331 static int
 332 snd_rme96_ratecode(int rate)
 333 {
 334     switch (rate) {
 335     case 32000: return SNDRV_PCM_RATE_32000;
 336     case 44100: return SNDRV_PCM_RATE_44100;
 337     case 48000: return SNDRV_PCM_RATE_48000;
 338     case 64000: return SNDRV_PCM_RATE_64000;
 339     case 88200: return SNDRV_PCM_RATE_88200;
 340     case 96000: return SNDRV_PCM_RATE_96000;
 341     }
 342     return 0;
 343 }
 344
 345 static int
 346 snd_rme96_playback_silence(snd_pcm_substream_t *substream,
 347                            int channel, /* not used (interleaved data) */
 348                            snd_pcm_uframes_t pos,
 349                            snd_pcm_uframes_t count)
 350 {
 351         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
 352         count <<= rme96->playback_frlog;
 353         pos <<= rme96->playback_frlog;
 354         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 355                   0, count);
 356         return 0;
 357 }
 358
 359 static int
 360 snd_rme96_playback_copy(snd_pcm_substream_t *substream,
 361                         int channel, /* not used (interleaved data) */
 362                         snd_pcm_uframes_t pos,
 363                         void *src,
 364                         snd_pcm_uframes_t count)
 365 {
 366         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
 367         count <<= rme96->playback_frlog;
 368         pos <<= rme96->playback_frlog;
 369         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
 370                             count);
 371         return 0;
 372 }
 373
 374 static int
 375 snd_rme96_capture_copy(snd_pcm_substream_t *substream,
 376                        int channel, /* not used (interleaved data) */
 377                        snd_pcm_uframes_t pos,
 378                        void *dst,
 379                        snd_pcm_uframes_t count)
 380 {
 381         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
 382         count <<= rme96->capture_frlog;
 383         pos <<= rme96->capture_frlog;
 384         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
 385                             count);
 386         return 0;
 387 }
 388
 389 /*
 390  * Digital output capabilites (S/PDIF)
 391  */
 392 static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
 393 {
 394         .info =              (SNDRV_PCM_INFO_MMAP |
 395                               SNDRV_PCM_INFO_MMAP_VALID |
 396                               SNDRV_PCM_INFO_INTERLEAVED |
 397                               SNDRV_PCM_INFO_PAUSE),
 398         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 399                               SNDRV_PCM_FMTBIT_S32_LE),
 400         .rates =             (SNDRV_PCM_RATE_32000 |
 401                               SNDRV_PCM_RATE_44100 |
 402                               SNDRV_PCM_RATE_48000 |
 403                               SNDRV_PCM_RATE_64000 |
 404                               SNDRV_PCM_RATE_88200 |
 405                               SNDRV_PCM_RATE_96000),
 406         .rate_min =          32000,
 407         .rate_max =          96000,
 408         .channels_min =      2,
 409         .channels_max =      2,
 410         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 411         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 412         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 413         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 414         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 415         .fifo_size =         0,
 416 };
 417
 418 /*
 419  * Digital input capabilites (S/PDIF)
 420  */
 421 static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
 422 {
 423         .info =              (SNDRV_PCM_INFO_MMAP |
 424                               SNDRV_PCM_INFO_MMAP_VALID |
 425                               SNDRV_PCM_INFO_INTERLEAVED |
 426                               SNDRV_PCM_INFO_PAUSE),
 427         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 428                               SNDRV_PCM_FMTBIT_S32_LE),
 429         .rates =             (SNDRV_PCM_RATE_32000 |
 430                               SNDRV_PCM_RATE_44100 |
 431                               SNDRV_PCM_RATE_48000 |
 432                               SNDRV_PCM_RATE_64000 |
 433                               SNDRV_PCM_RATE_88200 |
 434                               SNDRV_PCM_RATE_96000),
 435         .rate_min =          32000,
 436         .rate_max =          96000,
 437         .channels_min =      2,
 438         .channels_max =      2,
 439         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 440         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 441         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 442         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 443         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 444         .fifo_size =         0,
 445 };
 446
 447 /*
 448  * Digital output capabilites (ADAT)
 449  */
 450 static snd_pcm_hardware_t snd_rme96_playback_adat_info =
 451 {
 452         .info =              (SNDRV_PCM_INFO_MMAP |
 453                               SNDRV_PCM_INFO_MMAP_VALID |
 454                               SNDRV_PCM_INFO_INTERLEAVED |
 455                               SNDRV_PCM_INFO_PAUSE),
 456         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 457                               SNDRV_PCM_FMTBIT_S32_LE),
 458         .rates =             (SNDRV_PCM_RATE_44100 |
 459                               SNDRV_PCM_RATE_48000),
 460         .rate_min =          44100,
 461         .rate_max =          48000,
 462         .channels_min =      8,
 463         .channels_max =      8,
 464         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 465         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 466         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 467         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 468         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 469         .fifo_size =         0,
 470 };
 471
 472 /*
 473  * Digital input capabilites (ADAT)
 474  */
 475 static snd_pcm_hardware_t snd_rme96_capture_adat_info =
 476 {
 477         .info =              (SNDRV_PCM_INFO_MMAP |
 478                               SNDRV_PCM_INFO_MMAP_VALID |
 479                               SNDRV_PCM_INFO_INTERLEAVED |
 480                               SNDRV_PCM_INFO_PAUSE),
 481         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 482                               SNDRV_PCM_FMTBIT_S32_LE),
 483         .rates =             (SNDRV_PCM_RATE_44100 |
 484                               SNDRV_PCM_RATE_48000),
 485         .rate_min =          44100,
 486         .rate_max =          48000,
 487         .channels_min =      8,
 488         .channels_max =      8,
 489         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 490         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 491         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 492         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 493         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 494         .fifo_size =         0,
 495 };
 496
 497 /*
 498  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 499  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 500  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 501  * edge of CLATCH after the last data bit clocks in the whole data word.
 502  * A fast processor could probably drive the SPI interface faster than the
 503  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 504  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 505  *
 506  * NOTE: increased delay from 1 to 10, since there where problems setting
 507  * the volume.
 508  */
 509 static void
 510 snd_rme96_write_SPI(rme96_t *rme96, u16 val)
 511 {
 512         int i;
 513
 514         for (i = 0; i < 16; i++) {
 515                 if (val & 0x8000) {
 516                         rme96->areg |= RME96_AR_CDATA;
 517                 } else {
 518                         rme96->areg &= ~RME96_AR_CDATA;
 519                 }
 520                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 521                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 522                 udelay(10);
 523                 rme96->areg |= RME96_AR_CCLK;
 524                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 525                 udelay(10);
 526                 val <<= 1;
 527         }
 528         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 529         rme96->areg |= RME96_AR_CLATCH;
 530         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 531         udelay(10);
 532         rme96->areg &= ~RME96_AR_CLATCH;
 533         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 534 }
 535
 536 static void
 537 snd_rme96_apply_dac_volume(rme96_t *rme96)
 538 {
 539         if (RME96_DAC_IS_1852(rme96)) {
 540                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 541                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 542         } else if (RME96_DAC_IS_1855(rme96)) {
 543                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 544                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 545         }
 546 }
 547
 548 static void
 549 snd_rme96_reset_dac(rme96_t *rme96)
 550 {
 551         writel(rme96->wcreg | RME96_WCR_PD,
 552                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 553         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 554 }
 555
 556 static int
 557 snd_rme96_getmontracks(rme96_t *rme96)
 558 {
 559         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 560                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 561 }
 562
 563 static int
 564 snd_rme96_setmontracks(rme96_t *rme96,
 565                        int montracks)
 566 {
 567         if (montracks & 1) {
 568                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 569         } else {
 570                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 571         }
 572         if (montracks & 2) {
 573                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 574         } else {
 575                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 576         }
 577         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 578         return 0;
 579 }
 580
 581 static int
 582 snd_rme96_getattenuation(rme96_t *rme96)
 583 {
 584         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 585                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 586 }
 587
 588 static int
 589 snd_rme96_setattenuation(rme96_t *rme96,
 590                          int attenuation)
 591 {
 592         switch (attenuation) {
 593         case 0:
 594                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 595                         ~RME96_WCR_GAIN_1;
 596                 break;
 597         case 1:
 598                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 599                         ~RME96_WCR_GAIN_1;
 600                 break;
 601         case 2:
 602                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 603                         RME96_WCR_GAIN_1;
 604                 break;
 605         case 3:
 606                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 607                         RME96_WCR_GAIN_1;
 608                 break;
 609         default:
 610                 return -EINVAL;
 611         }
 612         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 613         return 0;
 614 }
 615
 616 static int
 617 snd_rme96_capture_getrate(rme96_t *rme96,
 618                           int *is_adat)
 619 {
 620         int n, rate;
 621
 622         *is_adat = 0;
 623         if (rme96->areg & RME96_AR_ANALOG) {
 624                 /* Analog input, overrides S/PDIF setting */
 625                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 626                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 627                 switch (n) {
 628                 case 1:
 629                         rate = 32000;
 630                         break;
 631                 case 2:
 632                         rate = 44100;
 633                         break;
 634                 case 3:
 635                         rate = 48000;
 636                         break;
 637                 default:
 638                         return -1;
 639                 }
 640                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 641         }
 642
 643         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 644         if (rme96->rcreg & RME96_RCR_LOCK) {
 645                 /* ADAT rate */
 646                 *is_adat = 1;
 647                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 648                         return 48000;
 649                 }
 650                 return 44100;
 651         }
 652
 653         if (rme96->rcreg & RME96_RCR_VERF) {
 654                 return -1;
 655         }
 656
 657         /* S/PDIF rate */
 658         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 659                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 660                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 661
 662         switch (n) {
 663         case 0:
 664                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 665                         return 64000;
 666                 }
 667                 return -1;
 668         case 3: return 96000;
 669         case 4: return 88200;
 670         case 5: return 48000;
 671         case 6: return 44100;
 672         case 7: return 32000;
 673         default:
 674                 break;
 675         }
 676         return -1;
 677 }
 678
 679 static int
 680 snd_rme96_playback_getrate(rme96_t *rme96)
 681 {
 682         int rate, dummy;
 683
 684         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 685             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 686             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 687         {
 688                 /* slave clock */
 689                 return rate;
 690         }
 691         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 692                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 693         switch (rate) {
 694         case 1:
 695                 rate = 32000;
 696                 break;
 697         case 2:
 698                 rate = 44100;
 699                 break;
 700         case 3:
 701                 rate = 48000;
 702                 break;
 703         default:
 704                 return -1;
 705         }
 706         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 707 }
 708
 709 static int
 710 snd_rme96_playback_setrate(rme96_t *rme96,
 711                            int rate)
 712 {
 713         int ds;
 714
 715         ds = rme96->wcreg & RME96_WCR_DS;
 716         switch (rate) {
 717         case 32000:
 718                 rme96->wcreg &= ~RME96_WCR_DS;
 719                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 720                         ~RME96_WCR_FREQ_1;
 721                 break;
 722         case 44100:
 723                 rme96->wcreg &= ~RME96_WCR_DS;
 724                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 725                         ~RME96_WCR_FREQ_0;
 726                 break;
 727         case 48000:
 728                 rme96->wcreg &= ~RME96_WCR_DS;
 729                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 730                         RME96_WCR_FREQ_1;
 731                 break;
 732         case 64000:
 733                 rme96->wcreg |= RME96_WCR_DS;
 734                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 735                         ~RME96_WCR_FREQ_1;
 736                 break;
 737         case 88200:
 738                 rme96->wcreg |= RME96_WCR_DS;
 739                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 740                         ~RME96_WCR_FREQ_0;
 741                 break;
 742         case 96000:
 743                 rme96->wcreg |= RME96_WCR_DS;
 744                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 745                         RME96_WCR_FREQ_1;
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 751             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 752         {
 753                 /* change to/from double-speed: reset the DAC (if available) */
 754                 snd_rme96_reset_dac(rme96);
 755         } else {
 756                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 757         }
 758         return 0;
 759 }
 760
 761 static int
 762 snd_rme96_capture_analog_setrate(rme96_t *rme96,
 763                                  int rate)
 764 {
 765         switch (rate) {
 766         case 32000:
 767                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 768                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 769                 break;
 770         case 44100:
 771                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 772                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 773                 break;
 774         case 48000:
 775                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 776                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 777                 break;
 778         case 64000:
 779                 if (rme96->rev < 4) {
 780                         return -EINVAL;
 781                 }
 782                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 783                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 784                 break;
 785         case 88200:
 786                 if (rme96->rev < 4) {
 787                         return -EINVAL;
 788                 }
 789                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 790                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 791                 break;
 792         case 96000:
 793                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 794                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 795                 break;
 796         default:
 797                 return -EINVAL;
 798         }
 799         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 800         return 0;
 801 }
 802
 803 static int
 804 snd_rme96_setclockmode(rme96_t *rme96,
 805                        int mode)
 806 {
 807         switch (mode) {
 808         case RME96_CLOCKMODE_SLAVE:
 809                 /* AutoSync */
 810                 rme96->wcreg &= ~RME96_WCR_MASTER;
 811                 rme96->areg &= ~RME96_AR_WSEL;
 812                 break;
 813         case RME96_CLOCKMODE_MASTER:
 814                 /* Internal */
 815                 rme96->wcreg |= RME96_WCR_MASTER;
 816                 rme96->areg &= ~RME96_AR_WSEL;
 817                 break;
 818         case RME96_CLOCKMODE_WORDCLOCK:
 819                 /* Word clock is a master mode */
 820                 rme96->wcreg |= RME96_WCR_MASTER;
 821                 rme96->areg |= RME96_AR_WSEL;
 822                 break;
 823         default:
 824                 return -EINVAL;
 825         }
 826         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 827         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 828         return 0;
 829 }
 830
 831 static int
 832 snd_rme96_getclockmode(rme96_t *rme96)
 833 {
 834         if (rme96->areg & RME96_AR_WSEL) {
 835                 return RME96_CLOCKMODE_WORDCLOCK;
 836         }
 837         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 838                 RME96_CLOCKMODE_SLAVE;
 839 }
 840
 841 static int
 842 snd_rme96_setinputtype(rme96_t *rme96,
 843                        int type)
 844 {
 845         int n;
 846
 847         switch (type) {
 848         case RME96_INPUT_OPTICAL:
 849                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 850                         ~RME96_WCR_INP_1;
 851                 break;
 852         case RME96_INPUT_COAXIAL:
 853                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 854                         ~RME96_WCR_INP_1;
 855                 break;
 856         case RME96_INPUT_INTERNAL:
 857                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 858                         RME96_WCR_INP_1;
 859                 break;
 860         case RME96_INPUT_XLR:
 861                 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
 862                      rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) ||
 863                     (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
 864                      rme96->rev > 4))
 865                 {
 866                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 867                         return -EINVAL;
 868                 }
 869                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 870                         RME96_WCR_INP_1;
 871                 break;
 872         case RME96_INPUT_ANALOG:
 873                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 874                         return -EINVAL;
 875                 }
 876                 rme96->areg |= RME96_AR_ANALOG;
 877                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 878                 if (rme96->rev < 4) {
 879                         /*
 880                          * Revision less than 004 does not support 64 and
 881                          * 88.2 kHz
 882                          */
 883                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 884                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 885                         }
 886                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 887                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 888                         }
 889                 }
 890                 return 0;
 891         default:
 892                 return -EINVAL;
 893         }
 894         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 895                 rme96->areg &= ~RME96_AR_ANALOG;
 896                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 897         }
 898         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 899         return 0;
 900 }
 901
 902 static int
 903 snd_rme96_getinputtype(rme96_t *rme96)
 904 {
 905         if (rme96->areg & RME96_AR_ANALOG) {
 906                 return RME96_INPUT_ANALOG;
 907         }
 908         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 909                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 910 }
 911
 912 static void
 913 snd_rme96_setframelog(rme96_t *rme96,
 914                       int n_channels,
 915                       int is_playback)
 916 {
 917         int frlog;
 918
 919         if (n_channels == 2) {
 920                 frlog = 1;
 921         } else {
 922                 /* assume 8 channels */
 923                 frlog = 3;
 924         }
 925         if (is_playback) {
 926                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 927                 rme96->playback_frlog = frlog;
 928         } else {
 929                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 930                 rme96->capture_frlog = frlog;
 931         }
 932 }
 933
 934 static int
 935 snd_rme96_playback_setformat(rme96_t *rme96,
 936                              int format)
 937 {
 938         switch (format) {
 939         case SNDRV_PCM_FORMAT_S16_LE:
 940                 rme96->wcreg &= ~RME96_WCR_MODE24;
 941                 break;
 942         case SNDRV_PCM_FORMAT_S32_LE:
 943                 rme96->wcreg |= RME96_WCR_MODE24;
 944                 break;
 945         default:
 946                 return -EINVAL;
 947         }
 948         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 949         return 0;
 950 }
 951
 952 static int
 953 snd_rme96_capture_setformat(rme96_t *rme96,
 954                             int format)
 955 {
 956         switch (format) {
 957         case SNDRV_PCM_FORMAT_S16_LE:
 958                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 959                 break;
 960         case SNDRV_PCM_FORMAT_S32_LE:
 961                 rme96->wcreg |= RME96_WCR_MODE24_2;
 962                 break;
 963         default:
 964                 return -EINVAL;
 965         }
 966         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 967         return 0;
 968 }
 969
 970 static void
 971 snd_rme96_set_period_properties(rme96_t *rme96,
 972                                 size_t period_bytes)
 973 {
 974         switch (period_bytes) {
 975         case RME96_LARGE_BLOCK_SIZE:
 976                 rme96->wcreg &= ~RME96_WCR_ISEL;
 977                 break;
 978         case RME96_SMALL_BLOCK_SIZE:
 979                 rme96->wcreg |= RME96_WCR_ISEL;
 980                 break;
 981         default:
 982                 snd_BUG();
 983                 break;
 984         }
 985         rme96->wcreg &= ~RME96_WCR_IDIS;
 986         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 987 }
 988
 989 static int
 990 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
 991                              snd_pcm_hw_params_t *params)
 992 {
 993         unsigned long flags;
 994         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
 995         int err, rate, dummy;
 996
 997         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
 998                 return err;
 999         spin_lock_irqsave(&rme96->lock, flags);
1000         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1001             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1002             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1003         {
1004                 /* slave clock */
1005                 if ((int)params_rate(params) != rate) {
1006                         spin_unlock_irqrestore(&rme96->lock, flags);
1007                         return -EIO;
1008                 }
1009         } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1010                 spin_unlock_irqrestore(&rme96->lock, flags);
1011                 return err;
1012         }
1013         if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1014                 spin_unlock_irqrestore(&rme96->lock, flags);
1015                 return err;
1016         }
1017         snd_rme96_setframelog(rme96, params_channels(params), 1);
1018         if (rme96->capture_periodsize != 0) {
1019                 if (params_period_size(params) << rme96->playback_frlog !=
1020                     rme96->capture_periodsize)
1021                 {
1022                         spin_unlock_irqrestore(&rme96->lock, flags);
1023                         return -EBUSY;
1024                 }
1025         }
1026         rme96->playback_periodsize =
1027                 params_period_size(params) << rme96->playback_frlog;
1028         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1029         /* S/PDIF setup */
1030         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1031                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1032                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1033         }
1034         spin_unlock_irqrestore(&rme96->lock, flags);
1035
1036         return 0;
1037 }
1038
1039 static int
1040 snd_rme96_playback_hw_free(snd_pcm_substream_t *substream)
1041 {
1042         snd_pcm_lib_free_pages(substream);
1043         return 0;
1044 }
1045
1046 static int
1047 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
1048                             snd_pcm_hw_params_t *params)
1049 {
1050         unsigned long flags;
1051         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1052         snd_pcm_runtime_t *runtime = substream->runtime;
1053         int err, isadat, rate;
1054
1055         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
1056                 return err;
1057         spin_lock_irqsave(&rme96->lock, flags);
1058         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1059                 spin_unlock_irqrestore(&rme96->lock, flags);
1060                 return err;
1061         }
1062         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1063                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1064                                                             params_rate(params))) < 0)
1065                 {
1066                         spin_unlock_irqrestore(&rme96->lock, flags);
1067                         return err;
1068                 }
1069         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1070                 if ((int)params_rate(params) != rate) {
1071                         spin_unlock_irqrestore(&rme96->lock, flags);
1072                         return -EIO;
1073                 }
1074                 if ((isadat && runtime->hw.channels_min == 2) ||
1075                     (!isadat && runtime->hw.channels_min == 8))
1076                 {
1077                         spin_unlock_irqrestore(&rme96->lock, flags);
1078                         return -EIO;
1079                 }
1080         }
1081         snd_rme96_setframelog(rme96, params_channels(params), 0);
1082         if (rme96->playback_periodsize != 0) {
1083                 if (params_period_size(params) << rme96->capture_frlog !=
1084                     rme96->playback_periodsize)
1085                 {
1086                         spin_unlock_irqrestore(&rme96->lock, flags);
1087                         return -EBUSY;
1088                 }
1089         }
1090         rme96->capture_periodsize =
1091                 params_period_size(params) << rme96->capture_frlog;
1092         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1093         spin_unlock_irqrestore(&rme96->lock, flags);
1094
1095         return 0;
1096 }
1097
1098 static int
1099 snd_rme96_capture_hw_free(snd_pcm_substream_t *substream)
1100 {
1101         snd_pcm_lib_free_pages(substream);
1102         return 0;
1103 }
1104
1105 static void
1106 snd_rme96_playback_start(rme96_t *rme96,
1107                          int from_pause)
1108 {
1109         if (!from_pause) {
1110                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1111                 rme96->playback_last_appl_ptr = 0;
1112                 rme96->playback_ptr = 0;
1113         }
1114
1115         rme96->wcreg |= RME96_WCR_START;
1116         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1117 }
1118
1119 static void
1120 snd_rme96_capture_start(rme96_t *rme96,
1121                         int from_pause)
1122 {
1123         if (!from_pause) {
1124                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1125                 rme96->capture_ptr = 0;
1126         }
1127
1128         rme96->wcreg |= RME96_WCR_START_2;
1129         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1130 }
1131
1132 static void
1133 snd_rme96_playback_stop(rme96_t *rme96)
1134 {
1135         /*
1136          * Check if there is an unconfirmed IRQ, if so confirm it, or else
1137          * the hardware will not stop generating interrupts
1138          */
1139         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1140         if (rme96->rcreg & RME96_RCR_IRQ) {
1141                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1142         }
1143         rme96->wcreg &= ~RME96_WCR_START;
1144         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1145 }
1146
1147 static void
1148 snd_rme96_capture_stop(rme96_t *rme96)
1149 {
1150         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1151         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1152                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1153         }
1154         rme96->wcreg &= ~RME96_WCR_START_2;
1155         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1156 }
1157
1158 static irqreturn_t
1159 snd_rme96_interrupt(int irq,
1160                     void *dev_id,
1161                     struct pt_regs *regs)
1162 {
1163         rme96_t *rme96 = (rme96_t *)dev_id;
1164
1165         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1166         /* fastpath out, to ease interrupt sharing */
1167         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1168               (rme96->rcreg & RME96_RCR_IRQ_2)))
1169         {
1170                 return IRQ_NONE;
1171         }
1172
1173         if (rme96->rcreg & RME96_RCR_IRQ) {
1174                 /* playback */
1175                 snd_pcm_period_elapsed(rme96->playback_substream);
1176                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1177         }
1178         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1179                 /* capture */
1180                 snd_pcm_period_elapsed(rme96->capture_substream);
1181                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1182         }
1183         return IRQ_HANDLED;
1184 }
1185
1186 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1187
1188 #define PERIOD_BYTES sizeof(period_bytes) / sizeof(period_bytes[0])
1189
1190 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1191         .count = PERIOD_BYTES,
1192         .list = period_bytes,
1193         .mask = 0
1194 };
1195
1196 static int
1197 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1198 {
1199         unsigned long flags;
1200         int rate, dummy;
1201         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1202         snd_pcm_runtime_t *runtime = substream->runtime;
1203
1204         snd_pcm_set_sync(substream);
1205
1206         spin_lock_irqsave(&rme96->lock, flags);
1207         if (rme96->playback_substream != NULL) {
1208                 spin_unlock_irqrestore(&rme96->lock, flags);
1209                 return -EBUSY;
1210         }
1211         rme96->wcreg &= ~RME96_WCR_ADAT;
1212         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1213         rme96->playback_substream = substream;
1214         rme96->playback_last_appl_ptr = 0;
1215         rme96->playback_ptr = 0;
1216         spin_unlock_irqrestore(&rme96->lock, flags);
1217
1218         runtime->hw = snd_rme96_playback_spdif_info;
1219         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1220             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1221             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1222         {
1223                 /* slave clock */
1224                 runtime->hw.rates = snd_rme96_ratecode(rate);
1225                 runtime->hw.rate_min = rate;
1226                 runtime->hw.rate_max = rate;
1227         }
1228         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1229         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1230
1231         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1232         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1233         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1234                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1235         return 0;
1236 }
1237
1238 static int
1239 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1240 {
1241         unsigned long flags;
1242         int isadat, rate;
1243         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1244         snd_pcm_runtime_t *runtime = substream->runtime;
1245
1246         snd_pcm_set_sync(substream);
1247
1248         runtime->hw = snd_rme96_capture_spdif_info;
1249         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1250             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1251         {
1252                 if (isadat) {
1253                         return -EIO;
1254                 }
1255                 runtime->hw.rates = snd_rme96_ratecode(rate);
1256                 runtime->hw.rate_min = rate;
1257                 runtime->hw.rate_max = rate;
1258         }
1259
1260         spin_lock_irqsave(&rme96->lock, flags);
1261         if (rme96->capture_substream != NULL) {
1262                 spin_unlock_irqrestore(&rme96->lock, flags);
1263                 return -EBUSY;
1264         }
1265         rme96->capture_substream = substream;
1266         rme96->capture_ptr = 0;
1267         spin_unlock_irqrestore(&rme96->lock, flags);
1268
1269         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1270         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1271
1272         return 0;
1273 }
1274
1275 static int
1276 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1277 {
1278         unsigned long flags;
1279         int rate, dummy;
1280         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1281         snd_pcm_runtime_t *runtime = substream->runtime;
1282
1283         snd_pcm_set_sync(substream);
1284
1285         spin_lock_irqsave(&rme96->lock, flags);
1286         if (rme96->playback_substream != NULL) {
1287                 spin_unlock_irqrestore(&rme96->lock, flags);
1288                 return -EBUSY;
1289         }
1290         rme96->wcreg |= RME96_WCR_ADAT;
1291         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1292         rme96->playback_substream = substream;
1293         rme96->playback_last_appl_ptr = 0;
1294         rme96->playback_ptr = 0;
1295         spin_unlock_irqrestore(&rme96->lock, flags);
1296
1297         runtime->hw = snd_rme96_playback_adat_info;
1298         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1299             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1300             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1301         {
1302                 /* slave clock */
1303                 runtime->hw.rates = snd_rme96_ratecode(rate);
1304                 runtime->hw.rate_min = rate;
1305                 runtime->hw.rate_max = rate;
1306         }
1307         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1308         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1309         return 0;
1310 }
1311
1312 static int
1313 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1314 {
1315         unsigned long flags;
1316         int isadat, rate;
1317         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1318         snd_pcm_runtime_t *runtime = substream->runtime;
1319
1320         snd_pcm_set_sync(substream);
1321
1322         runtime->hw = snd_rme96_capture_adat_info;
1323         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1324                 /* makes no sense to use analog input. Note that analog
1325                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1326                 return -EIO;
1327         }
1328         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1329                 if (!isadat) {
1330                         return -EIO;
1331                 }
1332                 runtime->hw.rates = snd_rme96_ratecode(rate);
1333                 runtime->hw.rate_min = rate;
1334                 runtime->hw.rate_max = rate;
1335         }
1336
1337         spin_lock_irqsave(&rme96->lock, flags);
1338         if (rme96->capture_substream != NULL) {
1339                 spin_unlock_irqrestore(&rme96->lock, flags);
1340                 return -EBUSY;
1341         }
1342         rme96->capture_substream = substream;
1343         rme96->capture_ptr = 0;
1344         spin_unlock_irqrestore(&rme96->lock, flags);
1345
1346         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1347         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1348         return 0;
1349 }
1350
1351 static int
1352 snd_rme96_playback_close(snd_pcm_substream_t *substream)
1353 {
1354         unsigned long flags;
1355         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1356         int spdif = 0;
1357
1358         spin_lock_irqsave(&rme96->lock, flags);
1359         if (RME96_ISPLAYING(rme96)) {
1360                 snd_rme96_playback_stop(rme96);
1361         }
1362         rme96->playback_substream = NULL;
1363         rme96->playback_periodsize = 0;
1364         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1365         spin_unlock_irqrestore(&rme96->lock, flags);
1366         if (spdif) {
1367                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1368                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1369                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1370         }
1371         return 0;
1372 }
1373
1374 static int
1375 snd_rme96_capture_close(snd_pcm_substream_t *substream)
1376 {
1377         unsigned long flags;
1378         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1379
1380         spin_lock_irqsave(&rme96->lock, flags);
1381         if (RME96_ISRECORDING(rme96)) {
1382                 snd_rme96_capture_stop(rme96);
1383         }
1384         rme96->capture_substream = NULL;
1385         rme96->capture_periodsize = 0;
1386         spin_unlock_irqrestore(&rme96->lock, flags);
1387         return 0;
1388 }
1389
1390 static int
1391 snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1392 {
1393         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1394         unsigned long flags;
1395
1396         spin_lock_irqsave(&rme96->lock, flags);
1397         if (RME96_ISPLAYING(rme96)) {
1398                 snd_rme96_playback_stop(rme96);
1399         }
1400         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1401         spin_unlock_irqrestore(&rme96->lock, flags);
1402         return 0;
1403 }
1404
1405 static int
1406 snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1407 {
1408         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1409         unsigned long flags;
1410
1411         spin_lock_irqsave(&rme96->lock, flags);
1412         if (RME96_ISRECORDING(rme96)) {
1413                 snd_rme96_capture_stop(rme96);
1414         }
1415         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1416         spin_unlock_irqrestore(&rme96->lock, flags);
1417         return 0;
1418 }
1419
1420 static int
1421 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1422                            int cmd)
1423 {
1424         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1425
1426         switch (cmd) {
1427         case SNDRV_PCM_TRIGGER_START:
1428                 if (!RME96_ISPLAYING(rme96)) {
1429                         if (substream != rme96->playback_substream) {
1430                                 return -EBUSY;
1431                         }
1432                         snd_rme96_playback_start(rme96, 0);
1433                 }
1434                 break;
1435
1436         case SNDRV_PCM_TRIGGER_STOP:
1437                 if (RME96_ISPLAYING(rme96)) {
1438                         if (substream != rme96->playback_substream) {
1439                                 return -EBUSY;
1440                         }
1441                         snd_rme96_playback_stop(rme96);
1442                 }
1443                 break;
1444
1445         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1446                 if (RME96_ISPLAYING(rme96)) {
1447                         snd_rme96_playback_stop(rme96);
1448                 }
1449                 break;
1450
1451         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1452                 if (!RME96_ISPLAYING(rme96)) {
1453                         snd_rme96_playback_start(rme96, 1);
1454                 }
1455                 break;
1456
1457         default:
1458                 return -EINVAL;
1459         }
1460         return 0;
1461 }
1462
1463 static int
1464 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1465                           int cmd)
1466 {
1467         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1468
1469         switch (cmd) {
1470         case SNDRV_PCM_TRIGGER_START:
1471                 if (!RME96_ISRECORDING(rme96)) {
1472                         if (substream != rme96->capture_substream) {
1473                                 return -EBUSY;
1474                         }
1475                         snd_rme96_capture_start(rme96, 0);
1476                 }
1477                 break;
1478
1479         case SNDRV_PCM_TRIGGER_STOP:
1480                 if (RME96_ISRECORDING(rme96)) {
1481                         if (substream != rme96->capture_substream) {
1482                                 return -EBUSY;
1483                         }
1484                         snd_rme96_capture_stop(rme96);
1485                 }
1486                 break;
1487
1488         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1489                 if (RME96_ISRECORDING(rme96)) {
1490                         snd_rme96_capture_stop(rme96);
1491                 }
1492                 break;
1493
1494         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1495                 if (!RME96_ISRECORDING(rme96)) {
1496                         snd_rme96_capture_start(rme96, 1);
1497                 }
1498                 break;
1499
1500         default:
1501                 return -EINVAL;
1502         }
1503
1504         return 0;
1505 }
1506
1507 static snd_pcm_uframes_t
1508 snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1509 {
1510         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1511         snd_pcm_runtime_t *runtime = substream->runtime;
1512         snd_pcm_sframes_t diff;
1513         size_t bytes;
1514
1515         if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1516                 diff = runtime->control->appl_ptr -
1517                     rme96->playback_last_appl_ptr;
1518                 rme96->playback_last_appl_ptr = runtime->control->appl_ptr;
1519                 if (diff != 0 &&
1520                     diff < -(snd_pcm_sframes_t)(runtime->boundary >> 1))
1521                 {
1522                         diff += runtime->boundary;
1523                 }
1524                 bytes = diff << rme96->playback_frlog;
1525
1526                 if (bytes > RME96_BUFFER_SIZE - rme96->playback_ptr) {
1527                         memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER +
1528                                              rme96->playback_ptr),
1529                                     runtime->dma_area + rme96->playback_ptr,
1530                                     RME96_BUFFER_SIZE - rme96->playback_ptr);
1531                         bytes -= RME96_BUFFER_SIZE - rme96->playback_ptr;
1532                         if (bytes > RME96_BUFFER_SIZE) {
1533                                 bytes = RME96_BUFFER_SIZE;
1534                         }
1535                         memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER),
1536                                     runtime->dma_area,
1537                                     bytes);
1538                         rme96->playback_ptr = bytes;
1539                 } else if (bytes != 0) {
1540                         memcpy_toio((void *)(rme96->iobase + RME96_IO_PLAY_BUFFER +
1541                                              rme96->playback_ptr),
1542                                     runtime->dma_area + rme96->playback_ptr,
1543                                     bytes);
1544                         rme96->playback_ptr += bytes;
1545                 }
1546         }
1547         return snd_rme96_playback_ptr(rme96);
1548 }
1549
1550 static snd_pcm_uframes_t
1551 snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1552 {
1553         rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1554         snd_pcm_runtime_t *runtime = substream->runtime;
1555         snd_pcm_uframes_t frameptr;
1556         size_t ptr;
1557
1558         frameptr = snd_rme96_capture_ptr(rme96);
1559         if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1560                 ptr = frameptr << rme96->capture_frlog;
1561                 if (ptr > rme96->capture_ptr) {
1562                         memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1563                                       (void *)(rme96->iobase + RME96_IO_REC_BUFFER +
1564                                                rme96->capture_ptr),
1565                                       ptr - rme96->capture_ptr);
1566                         rme96->capture_ptr += ptr - rme96->capture_ptr;
1567                 } else if (ptr < rme96->capture_ptr) {
1568                         memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1569                                       (void *)(rme96->iobase + RME96_IO_REC_BUFFER +
1570                                                rme96->capture_ptr),
1571                                       RME96_BUFFER_SIZE - rme96->capture_ptr);
1572                         memcpy_fromio(runtime->dma_area,
1573                                       (void *)(rme96->iobase + RME96_IO_REC_BUFFER),
1574                                       ptr);
1575                         rme96->capture_ptr = ptr;
1576                 }
1577         }
1578         return frameptr;
1579 }
1580
1581 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1582         .open =         snd_rme96_playback_spdif_open,
1583         .close =        snd_rme96_playback_close,
1584         .ioctl =        snd_pcm_lib_ioctl,
1585         .hw_params =    snd_rme96_playback_hw_params,
1586         .hw_free =      snd_rme96_playback_hw_free,
1587         .prepare =      snd_rme96_playback_prepare,
1588         .trigger =      snd_rme96_playback_trigger,
1589         .pointer =      snd_rme96_playback_pointer,
1590         .copy =         snd_rme96_playback_copy,
1591         .silence =      snd_rme96_playback_silence,
1592 };
1593
1594 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1595         .open =         snd_rme96_capture_spdif_open,
1596         .close =        snd_rme96_capture_close,
1597         .ioctl =        snd_pcm_lib_ioctl,
1598         .hw_params =    snd_rme96_capture_hw_params,
1599         .hw_free =      snd_rme96_capture_hw_free,
1600         .prepare =      snd_rme96_capture_prepare,
1601         .trigger =      snd_rme96_capture_trigger,
1602         .pointer =      snd_rme96_capture_pointer,
1603         .copy =         snd_rme96_capture_copy,
1604 };
1605
1606 static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1607         .open =         snd_rme96_playback_adat_open,
1608         .close =        snd_rme96_playback_close,
1609         .ioctl =        snd_pcm_lib_ioctl,
1610         .hw_params =    snd_rme96_playback_hw_params,
1611         .hw_free =      snd_rme96_playback_hw_free,
1612         .prepare =      snd_rme96_playback_prepare,
1613         .trigger =      snd_rme96_playback_trigger,
1614         .pointer =      snd_rme96_playback_pointer,
1615         .copy =         snd_rme96_playback_copy,
1616         .silence =      snd_rme96_playback_silence,
1617 };
1618
1619 static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1620         .open =         snd_rme96_capture_adat_open,
1621         .close =        snd_rme96_capture_close,
1622         .ioctl =        snd_pcm_lib_ioctl,
1623         .hw_params =    snd_rme96_capture_hw_params,
1624         .hw_free =      snd_rme96_capture_hw_free,
1625         .prepare =      snd_rme96_capture_prepare,
1626         .trigger =      snd_rme96_capture_trigger,
1627         .pointer =      snd_rme96_capture_pointer,
1628         .copy =         snd_rme96_capture_copy,
1629 };
1630
1631 static void
1632 snd_rme96_free(void *private_data)
1633 {
1634         rme96_t *rme96 = (rme96_t *)private_data;
1635
1636         if (rme96 == NULL) {
1637                 return;
1638         }
1639         if (rme96->irq >= 0) {
1640                 snd_rme96_playback_stop(rme96);
1641                 snd_rme96_capture_stop(rme96);
1642                 rme96->areg &= ~RME96_AR_DAC_EN;
1643                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1644                 free_irq(rme96->irq, (void *)rme96);
1645                 rme96->irq = -1;
1646         }
1647         if (rme96->iobase) {
1648                 iounmap((void *)rme96->iobase);
1649                 rme96->iobase = 0;
1650         }
1651         if (rme96->res_port != NULL) {
1652                 release_resource(rme96->res_port);
1653                 kfree_nocheck(rme96->res_port);
1654                 rme96->res_port = NULL;
1655         }
1656 }
1657
1658 static void
1659 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1660 {
1661         rme96_t *rme96 = (rme96_t *) pcm->private_data;
1662         rme96->spdif_pcm = NULL;
1663         snd_pcm_lib_preallocate_free_for_all(pcm);
1664 }
1665
1666 static void
1667 snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1668 {
1669         rme96_t *rme96 = (rme96_t *) pcm->private_data;
1670         rme96->adat_pcm = NULL;
1671         snd_pcm_lib_preallocate_free_for_all(pcm);
1672 }
1673
1674 static int __devinit
1675 snd_rme96_create(rme96_t *rme96)
1676 {
1677         struct pci_dev *pci = rme96->pci;
1678         int err;
1679
1680         rme96->irq = -1;
1681
1682         if ((err = pci_enable_device(pci)) < 0)
1683                 return err;
1684
1685         rme96->port = pci_resource_start(rme96->pci, 0);
1686
1687         if ((rme96->res_port = request_mem_region(rme96->port, RME96_IO_SIZE, "RME96")) == NULL) {
1688                 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1689                 return -EBUSY;
1690         }
1691
1692         if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1693                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1694                 return -EBUSY;
1695         }
1696         rme96->irq = pci->irq;
1697
1698         spin_lock_init(&rme96->lock);
1699         if ((rme96->iobase = (unsigned long) ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1700                 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1701                 return -ENOMEM;
1702         }
1703
1704         /* read the card's revision number */
1705         pci_read_config_byte(pci, 8, &rme96->rev);
1706
1707         /* set up ALSA pcm device for S/PDIF */
1708         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1709                                1, 1, &rme96->spdif_pcm)) < 0)
1710         {
1711                 return err;
1712         }
1713         rme96->spdif_pcm->private_data = rme96;
1714         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1715         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1716         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1717         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1718
1719         rme96->spdif_pcm->info_flags = 0;
1720
1721         snd_pcm_lib_preallocate_pages_for_all(rme96->spdif_pcm,
1722                                               SNDRV_DMA_TYPE_CONTINUOUS,
1723                                               snd_dma_continuous_data(GFP_KERNEL),
1724                                               RME96_BUFFER_SIZE,
1725                                               RME96_BUFFER_SIZE);
1726
1727         /* set up ALSA pcm device for ADAT */
1728         if (pci->device == PCI_DEVICE_ID_DIGI96) {
1729                 /* ADAT is not available on the base model */
1730                 rme96->adat_pcm = NULL;
1731         } else {
1732                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1733                                        1, 1, &rme96->adat_pcm)) < 0)
1734                 {
1735                         return err;
1736                 }
1737                 rme96->adat_pcm->private_data = rme96;
1738                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1739                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1740                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1741                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1742
1743                 rme96->adat_pcm->info_flags = 0;
1744
1745                 snd_pcm_lib_preallocate_pages_for_all(rme96->adat_pcm,
1746                                                       SNDRV_DMA_TYPE_CONTINUOUS,
1747                                                       snd_dma_continuous_data(GFP_KERNEL),
1748                                                       RME96_BUFFER_SIZE,
1749                                                       RME96_BUFFER_SIZE);
1750         }
1751
1752         rme96->playback_periodsize = 0;
1753         rme96->capture_periodsize = 0;
1754
1755         /* make sure playback/capture is stopped, if by some reason active */
1756         snd_rme96_playback_stop(rme96);
1757         snd_rme96_capture_stop(rme96);
1758
1759         /* set default values in registers */
1760         rme96->wcreg =
1761                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1762                 RME96_WCR_SEL |    /* normal playback */
1763                 RME96_WCR_MASTER | /* set to master clock mode */
1764                 RME96_WCR_INP_0;   /* set coaxial input */
1765
1766         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1767
1768         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1769         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1770
1771         /* reset the ADC */
1772         writel(rme96->areg | RME96_AR_PD2,
1773                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1774         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1775
1776         /* reset and enable the DAC (order is important). */
1777         snd_rme96_reset_dac(rme96);
1778         rme96->areg |= RME96_AR_DAC_EN;
1779         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1780
1781         /* reset playback and record buffer pointers */
1782         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1783         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1784
1785         /* reset volume */
1786         rme96->vol[0] = rme96->vol[1] = 0;
1787         if (RME96_HAS_ANALOG_OUT(rme96)) {
1788                 snd_rme96_apply_dac_volume(rme96);
1789         }
1790
1791         /* init switch interface */
1792         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1793                 return err;
1794         }
1795
1796         /* init proc interface */
1797         snd_rme96_proc_init(rme96);
1798
1799         return 0;
1800 }
1801
1802 /*
1803  * proc interface
1804  */
1805
1806 static void
1807 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1808 {
1809         int n;
1810         rme96_t *rme96 = (rme96_t *)entry->private_data;
1811
1812         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1813
1814         snd_iprintf(buffer, rme96->card->longname);
1815         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1816
1817         snd_iprintf(buffer, "\nGeneral settings\n");
1818         if (rme96->wcreg & RME96_WCR_IDIS) {
1819                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1820                             "disabled)\n");
1821         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1822                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1823         } else {
1824                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1825         }
1826         snd_iprintf(buffer, "\nInput settings\n");
1827         switch (snd_rme96_getinputtype(rme96)) {
1828         case RME96_INPUT_OPTICAL:
1829                 snd_iprintf(buffer, "  input: optical");
1830                 break;
1831         case RME96_INPUT_COAXIAL:
1832                 snd_iprintf(buffer, "  input: coaxial");
1833                 break;
1834         case RME96_INPUT_INTERNAL:
1835                 snd_iprintf(buffer, "  input: internal");
1836                 break;
1837         case RME96_INPUT_XLR:
1838                 snd_iprintf(buffer, "  input: XLR");
1839                 break;
1840         case RME96_INPUT_ANALOG:
1841                 snd_iprintf(buffer, "  input: analog");
1842                 break;
1843         }
1844         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1845                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1846         } else {
1847                 if (n) {
1848                         snd_iprintf(buffer, " (8 channels)\n");
1849                 } else {
1850                         snd_iprintf(buffer, " (2 channels)\n");
1851                 }
1852                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1853                             snd_rme96_capture_getrate(rme96, &n));
1854         }
1855         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1856                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1857         } else {
1858                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1859         }
1860
1861         snd_iprintf(buffer, "\nOutput settings\n");
1862         if (rme96->wcreg & RME96_WCR_SEL) {
1863                 snd_iprintf(buffer, "  output signal: normal playback\n");
1864         } else {
1865                 snd_iprintf(buffer, "  output signal: same as input\n");
1866         }
1867         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1868                     snd_rme96_playback_getrate(rme96));
1869         if (rme96->wcreg & RME96_WCR_MODE24) {
1870                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1871         } else {
1872                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1873         }
1874         if (rme96->areg & RME96_AR_WSEL) {
1875                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1876         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1877                 snd_iprintf(buffer, "  sample clock source: internal\n");
1878         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1879                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1880         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1881                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1882         } else {
1883                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1884         }
1885         if (rme96->wcreg & RME96_WCR_PRO) {
1886                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1887         } else {
1888                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1889         }
1890         if (rme96->wcreg & RME96_WCR_EMP) {
1891                 snd_iprintf(buffer, "  emphasis: on\n");
1892         } else {
1893                 snd_iprintf(buffer, "  emphasis: off\n");
1894         }
1895         if (rme96->wcreg & RME96_WCR_DOLBY) {
1896                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1897         } else {
1898                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1899         }
1900         if (RME96_HAS_ANALOG_IN(rme96)) {
1901                 snd_iprintf(buffer, "\nAnalog output settings\n");
1902                 switch (snd_rme96_getmontracks(rme96)) {
1903                 case RME96_MONITOR_TRACKS_1_2:
1904                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1905                         break;
1906                 case RME96_MONITOR_TRACKS_3_4:
1907                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1908                         break;
1909                 case RME96_MONITOR_TRACKS_5_6:
1910                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1911                         break;
1912                 case RME96_MONITOR_TRACKS_7_8:
1913                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1914                         break;
1915                 }
1916                 switch (snd_rme96_getattenuation(rme96)) {
1917                 case RME96_ATTENUATION_0:
1918                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1919                         break;
1920                 case RME96_ATTENUATION_6:
1921                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1922                         break;
1923                 case RME96_ATTENUATION_12:
1924                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1925                         break;
1926                 case RME96_ATTENUATION_18:
1927                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1928                         break;
1929                 }
1930                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1931                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1932         }
1933 }
1934
1935 static void __devinit
1936 snd_rme96_proc_init(rme96_t *rme96)
1937 {
1938         snd_info_entry_t *entry;
1939
1940         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1941                 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1942 }
1943
1944 /*
1945  * control interface
1946  */
1947
1948 static int
1949 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1950 {
1951         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1952         uinfo->count = 1;
1953         uinfo->value.integer.min = 0;
1954         uinfo->value.integer.max = 1;
1955         return 0;
1956 }
1957 static int
1958 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1959 {
1960         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1961         unsigned long flags;
1962
1963         spin_lock_irqsave(&rme96->lock, flags);
1964         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1965         spin_unlock_irqrestore(&rme96->lock, flags);
1966         return 0;
1967 }
1968 static int
1969 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1970 {
1971         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1972         unsigned long flags;
1973         unsigned int val;
1974         int change;
1975
1976         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1977         spin_lock_irqsave(&rme96->lock, flags);
1978         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1979         change = val != rme96->wcreg;
1980         writel(rme96->wcreg = val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1981         spin_unlock_irqrestore(&rme96->lock, flags);
1982         return change;
1983 }
1984
1985 static int
1986 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1987 {
1988         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1989         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1990         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1991
1992         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1993         uinfo->count = 1;
1994         switch (rme96->pci->device) {
1995         case PCI_DEVICE_ID_DIGI96:
1996         case PCI_DEVICE_ID_DIGI96_8:
1997                 uinfo->value.enumerated.items = 3;
1998                 break;
1999         case PCI_DEVICE_ID_DIGI96_8_PRO:
2000                 uinfo->value.enumerated.items = 4;
2001                 break;
2002         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2003                 if (rme96->rev > 4) {
2004                         /* PST */
2005                         uinfo->value.enumerated.items = 4;
2006                         texts[3] = _texts[4]; /* Analog instead of XLR */
2007                 } else {
2008                         /* PAD */
2009                         uinfo->value.enumerated.items = 5;
2010                 }
2011                 break;
2012         default:
2013                 snd_BUG();
2014                 break;
2015         }
2016         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
2017                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2018         }
2019         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2020         return 0;
2021 }
2022 static int
2023 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2024 {
2025         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2026         unsigned long flags;
2027         unsigned int items = 3;
2028
2029         spin_lock_irqsave(&rme96->lock, flags);
2030         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
2031
2032         switch (rme96->pci->device) {
2033         case PCI_DEVICE_ID_DIGI96:
2034         case PCI_DEVICE_ID_DIGI96_8:
2035                 items = 3;
2036                 break;
2037         case PCI_DEVICE_ID_DIGI96_8_PRO:
2038                 items = 4;
2039                 break;
2040         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2041                 if (rme96->rev > 4) {
2042                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
2043                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
2044                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
2045                         }
2046                         items = 4;
2047                 } else {
2048                         items = 5;
2049                 }
2050                 break;
2051         default:
2052                 snd_BUG();
2053                 break;
2054         }
2055         if (ucontrol->value.enumerated.item[0] >= items) {
2056                 ucontrol->value.enumerated.item[0] = items - 1;
2057         }
2058
2059         spin_unlock_irqrestore(&rme96->lock, flags);
2060         return 0;
2061 }
2062 static int
2063 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2064 {
2065         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2066         unsigned long flags;
2067         unsigned int val;
2068         int change, items = 3;
2069
2070         switch (rme96->pci->device) {
2071         case PCI_DEVICE_ID_DIGI96:
2072         case PCI_DEVICE_ID_DIGI96_8:
2073                 items = 3;
2074                 break;
2075         case PCI_DEVICE_ID_DIGI96_8_PRO:
2076                 items = 4;
2077                 break;
2078         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2079                 if (rme96->rev > 4) {
2080                         items = 4;
2081                 } else {
2082                         items = 5;
2083                 }
2084                 break;
2085         default:
2086                 snd_BUG();
2087                 break;
2088         }
2089         val = ucontrol->value.enumerated.item[0] % items;
2090
2091         /* special case for PST */
2092         if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
2093                 if (val == RME96_INPUT_XLR) {
2094                         val = RME96_INPUT_ANALOG;
2095                 }
2096         }
2097
2098         spin_lock_irqsave(&rme96->lock, flags);
2099         change = (int)val != snd_rme96_getinputtype(rme96);
2100         snd_rme96_setinputtype(rme96, val);
2101         spin_unlock_irqrestore(&rme96->lock, flags);
2102         return change;
2103 }
2104
2105 static int
2106 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2107 {
2108         static char *texts[3] = { "AutoSync", "Internal", "Word" };
2109
2110         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2111         uinfo->count = 1;
2112         uinfo->value.enumerated.items = 3;
2113         if (uinfo->value.enumerated.item > 2) {
2114                 uinfo->value.enumerated.item = 2;
2115         }
2116         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2117         return 0;
2118 }
2119 static int
2120 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2121 {
2122         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2123         unsigned long flags;
2124
2125         spin_lock_irqsave(&rme96->lock, flags);
2126         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2127         spin_unlock_irqrestore(&rme96->lock, flags);
2128         return 0;
2129 }
2130 static int
2131 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2132 {
2133         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2134         unsigned long flags;
2135         unsigned int val;
2136         int change;
2137
2138         val = ucontrol->value.enumerated.item[0] % 3;
2139         spin_lock_irqsave(&rme96->lock, flags);
2140         change = (int)val != snd_rme96_getclockmode(rme96);
2141         snd_rme96_setclockmode(rme96, val);
2142         spin_unlock_irqrestore(&rme96->lock, flags);
2143         return change;
2144 }
2145
2146 static int
2147 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2148 {
2149         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2150
2151         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2152         uinfo->count = 1;
2153         uinfo->value.enumerated.items = 4;
2154         if (uinfo->value.enumerated.item > 3) {
2155                 uinfo->value.enumerated.item = 3;
2156         }
2157         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2158         return 0;
2159 }
2160 static int
2161 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2162 {
2163         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2164         unsigned long flags;
2165
2166         spin_lock_irqsave(&rme96->lock, flags);
2167         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2168         spin_unlock_irqrestore(&rme96->lock, flags);
2169         return 0;
2170 }
2171 static int
2172 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2173 {
2174         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2175         unsigned long flags;
2176         unsigned int val;
2177         int change;
2178
2179         val = ucontrol->value.enumerated.item[0] % 4;
2180         spin_lock_irqsave(&rme96->lock, flags);
2181
2182         change = (int)val != snd_rme96_getattenuation(rme96);
2183         snd_rme96_setattenuation(rme96, val);
2184         spin_unlock_irqrestore(&rme96->lock, flags);
2185         return change;
2186 }
2187
2188 static int
2189 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2190 {
2191         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2192
2193         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2194         uinfo->count = 1;
2195         uinfo->value.enumerated.items = 4;
2196         if (uinfo->value.enumerated.item > 3) {
2197                 uinfo->value.enumerated.item = 3;
2198         }
2199         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2200         return 0;
2201 }
2202 static int
2203 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2204 {
2205         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2206         unsigned long flags;
2207
2208         spin_lock_irqsave(&rme96->lock, flags);
2209         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2210         spin_unlock_irqrestore(&rme96->lock, flags);
2211         return 0;
2212 }
2213 static int
2214 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2215 {
2216         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2217         unsigned long flags;
2218         unsigned int val;
2219         int change;
2220
2221         val = ucontrol->value.enumerated.item[0] % 4;
2222         spin_lock_irqsave(&rme96->lock, flags);
2223         change = (int)val != snd_rme96_getmontracks(rme96);
2224         snd_rme96_setmontracks(rme96, val);
2225         spin_unlock_irqrestore(&rme96->lock, flags);
2226         return change;
2227 }
2228
2229 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2230 {
2231         u32 val = 0;
2232         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2233         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2234         if (val & RME96_WCR_PRO)
2235                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2236         else
2237                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2238         return val;
2239 }
2240
2241 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2242 {
2243         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2244                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2245         if (val & RME96_WCR_PRO)
2246                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2247         else
2248                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2249 }
2250
2251 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2252 {
2253         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2254         uinfo->count = 1;
2255         return 0;
2256 }
2257
2258 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2259 {
2260         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2261
2262         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2263         return 0;
2264 }
2265
2266 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2267 {
2268         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2269         unsigned long flags;
2270         int change;
2271         u32 val;
2272
2273         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2274         spin_lock_irqsave(&rme96->lock, flags);
2275         change = val != rme96->wcreg_spdif;
2276         rme96->wcreg_spdif = val;
2277         spin_unlock_irqrestore(&rme96->lock, flags);
2278         return change;
2279 }
2280
2281 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2282 {
2283         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2284         uinfo->count = 1;
2285         return 0;
2286 }
2287
2288 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2289 {
2290         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2291
2292         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2293         return 0;
2294 }
2295
2296 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2297 {
2298         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2299         unsigned long flags;
2300         int change;
2301         u32 val;
2302
2303         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2304         spin_lock_irqsave(&rme96->lock, flags);
2305         change = val != rme96->wcreg_spdif_stream;
2306         rme96->wcreg_spdif_stream = val;
2307         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2308         writel(rme96->wcreg |= val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2309         spin_unlock_irqrestore(&rme96->lock, flags);
2310         return change;
2311 }
2312
2313 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2314 {
2315         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2316         uinfo->count = 1;
2317         return 0;
2318 }
2319
2320 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2321 {
2322         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2323         return 0;
2324 }
2325
2326 static int
2327 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2328 {
2329         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2330
2331         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2332         uinfo->count = 2;
2333         uinfo->value.integer.min = 0;
2334         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2335         return 0;
2336 }
2337
2338 static int
2339 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2340 {
2341         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2342         unsigned long flags;
2343
2344         spin_lock_irqsave(&rme96->lock, flags);
2345         u->value.integer.value[0] = rme96->vol[0];
2346         u->value.integer.value[1] = rme96->vol[1];
2347         spin_unlock_irqrestore(&rme96->lock, flags);
2348
2349         return 0;
2350 }
2351
2352 static int
2353 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2354 {
2355         rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2356         unsigned long flags;
2357         int change = 0;
2358
2359         if (!RME96_HAS_ANALOG_OUT(rme96)) {
2360                 return -EINVAL;
2361         }
2362         spin_lock_irqsave(&rme96->lock, flags);
2363         if (u->value.integer.value[0] != rme96->vol[0]) {
2364                 rme96->vol[0] = u->value.integer.value[0];
2365                 change = 1;
2366         }
2367         if (u->value.integer.value[1] != rme96->vol[1]) {
2368                 rme96->vol[1] = u->value.integer.value[1];
2369                 change = 1;
2370         }
2371         if (change) {
2372                 snd_rme96_apply_dac_volume(rme96);
2373         }
2374         spin_unlock_irqrestore(&rme96->lock, flags);
2375
2376         return change;
2377 }
2378
2379 static snd_kcontrol_new_t snd_rme96_controls[] = {
2380 {
2381         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2382         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2383         .info =         snd_rme96_control_spdif_info,
2384         .get =          snd_rme96_control_spdif_get,
2385         .put =          snd_rme96_control_spdif_put
2386 },
2387 {
2388         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2389         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2390         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2391         .info =         snd_rme96_control_spdif_stream_info,
2392         .get =          snd_rme96_control_spdif_stream_get,
2393         .put =          snd_rme96_control_spdif_stream_put
2394 },
2395 {
2396         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2397         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2398         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2399         .info =         snd_rme96_control_spdif_mask_info,
2400         .get =          snd_rme96_control_spdif_mask_get,
2401         .private_value = IEC958_AES0_NONAUDIO |
2402                         IEC958_AES0_PROFESSIONAL |
2403                         IEC958_AES0_CON_EMPHASIS
2404 },
2405 {
2406         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2407         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2408         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2409         .info =         snd_rme96_control_spdif_mask_info,
2410         .get =          snd_rme96_control_spdif_mask_get,
2411         .private_value = IEC958_AES0_NONAUDIO |
2412                         IEC958_AES0_PROFESSIONAL |
2413                         IEC958_AES0_PRO_EMPHASIS
2414 },
2415 {
2416         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2417         .name =         "Input Connector",
2418         .info =         snd_rme96_info_inputtype_control,
2419         .get =          snd_rme96_get_inputtype_control,
2420         .put =          snd_rme96_put_inputtype_control
2421 },
2422 {
2423         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2424         .name =         "Loopback Input",
2425         .info =         snd_rme96_info_loopback_control,
2426         .get =          snd_rme96_get_loopback_control,
2427         .put =          snd_rme96_put_loopback_control
2428 },
2429 {
2430         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2431         .name =         "Sample Clock Source",
2432         .info =         snd_rme96_info_clockmode_control,
2433         .get =          snd_rme96_get_clockmode_control,
2434         .put =          snd_rme96_put_clockmode_control
2435 },
2436 {
2437         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2438         .name =         "Monitor Tracks",
2439         .info =         snd_rme96_info_montracks_control,
2440         .get =          snd_rme96_get_montracks_control,
2441         .put =          snd_rme96_put_montracks_control
2442 },
2443 {
2444         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2445         .name =         "Attenuation",
2446         .info =         snd_rme96_info_attenuation_control,
2447         .get =          snd_rme96_get_attenuation_control,
2448         .put =          snd_rme96_put_attenuation_control
2449 },
2450 {
2451         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2452         .name =         "DAC Playback Volume",
2453         .info =         snd_rme96_dac_volume_info,
2454         .get =          snd_rme96_dac_volume_get,
2455         .put =          snd_rme96_dac_volume_put
2456 }
2457 };
2458
2459 static int
2460 snd_rme96_create_switches(snd_card_t *card,
2461                           rme96_t *rme96)
2462 {
2463         int idx, err;
2464         snd_kcontrol_t *kctl;
2465
2466         for (idx = 0; idx < 7; idx++) {
2467                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2468                         return err;
2469                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2470                         rme96->spdif_ctl = kctl;
2471         }
2472
2473         if (RME96_HAS_ANALOG_OUT(rme96)) {
2474                 for (idx = 7; idx < 10; idx++)
2475                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2476                                 return err;
2477         }
2478
2479         return 0;
2480 }
2481
2482 /*
2483  * Card initialisation
2484  */
2485
2486 static void snd_rme96_card_free(snd_card_t *card)
2487 {
2488         snd_rme96_free(card->private_data);
2489 }
2490
2491 static int __devinit
2492 snd_rme96_probe(struct pci_dev *pci,
2493                 const struct pci_device_id *pci_id)
2494 {
2495         static int dev;
2496         rme96_t *rme96;
2497         snd_card_t *card;
2498         int err;
2499         u8 val;
2500
2501         if (dev >= SNDRV_CARDS) {
2502                 return -ENODEV;
2503         }
2504         if (!enable[dev]) {
2505                 dev++;
2506                 return -ENOENT;
2507         }
2508         if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2509                                  sizeof(rme96_t))) == NULL)
2510                 return -ENOMEM;
2511         card->private_free = snd_rme96_card_free;
2512         rme96 = (rme96_t *)card->private_data;
2513         rme96->card = card;
2514         rme96->pci = pci;
2515         snd_card_set_dev(card, &pci->dev);
2516         if ((err = snd_rme96_create(rme96)) < 0) {
2517                 snd_card_free(card);
2518                 return err;
2519         }
2520
2521         strcpy(card->driver, "Digi96");
2522         switch (rme96->pci->device) {
2523         case PCI_DEVICE_ID_DIGI96:
2524                 strcpy(card->shortname, "RME Digi96");
2525                 break;
2526         case PCI_DEVICE_ID_DIGI96_8:
2527                 strcpy(card->shortname, "RME Digi96/8");
2528                 break;
2529         case PCI_DEVICE_ID_DIGI96_8_PRO:
2530                 strcpy(card->shortname, "RME Digi96/8 PRO");
2531                 break;
2532         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2533                 pci_read_config_byte(rme96->pci, 8, &val);
2534                 if (val < 5) {
2535                         strcpy(card->shortname, "RME Digi96/8 PAD");
2536                 } else {
2537                         strcpy(card->shortname, "RME Digi96/8 PST");
2538                 }
2539                 break;
2540         }
2541         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2542                 rme96->port, rme96->irq);
2543
2544         if ((err = snd_card_register(card)) < 0) {
2545                 snd_card_free(card);
2546                 return err;
2547         }
2548         pci_set_drvdata(pci, card);
2549         dev++;
2550         return 0;
2551 }
2552
2553 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2554 {
2555         snd_card_free(pci_get_drvdata(pci));
2556         pci_set_drvdata(pci, NULL);
2557 }
2558
2559 static struct pci_driver driver = {
2560         .name = "RME Digi96",
2561         .id_table = snd_rme96_ids,
2562         .probe = snd_rme96_probe,
2563         .remove = __devexit_p(snd_rme96_remove),
2564 };
2565
2566 static int __init alsa_card_rme96_init(void)
2567 {
2568         int err;
2569
2570         if ((err = pci_module_init(&driver)) < 0) {
2571 #ifdef MODULE
2572                 printk(KERN_ERR "No RME Digi96 cards found\n");
2573 #endif
2574                 return err;
2575         }
2576         return 0;
2577 }
2578
2579 static void __exit alsa_card_rme96_exit(void)
2580 {
2581         pci_unregister_driver(&driver);
2582 }
2583
2584 module_init(alsa_card_rme96_init)
2585 module_exit(alsa_card_rme96_exit)
2586
2587 #ifndef MODULE
2588
2589 /* format is: snd-rme96=enable,index,id */
2590
2591 static int __init alsa_card_rme96_setup(char *str)
2592 {
2593         static unsigned __initdata nr_dev = 0;
2594
2595         if (nr_dev >= SNDRV_CARDS)
2596                 return 0;
2597         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2598                get_option(&str,&index[nr_dev]) == 2 &&
2599                get_id(&str,&id[nr_dev]) == 2);
2600         nr_dev++;
2601         return 1;
2602 }
2603
2604 __setup("snd-rme96=", alsa_card_rme96_setup);
2605
2606 #endif /* ifndef MODULE */