sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <sound/driver.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/control.h>
  34 #include <sound/pcm.h>
  35 #include <sound/info.h>
  36 #include <sound/asoundef.h>
  37 #include <sound/rawmidi.h>
  38 #include <sound/hwdep.h>
  39 #include <sound/initval.h>
  40 #include <sound/hdsp.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/current.h>
  44 #include <asm/io.h>
  45
  46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  49 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
  50 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
  51 static int boot_devs;
  52
  53 module_param_array(index, int, boot_devs, 0444);
  54 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  55 module_param_array(id, charp, boot_devs, 0444);
  56 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  57 module_param_array(enable, bool, boot_devs, 0444);
  58 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  59 module_param_array(precise_ptr, bool, boot_devs, 0444);
  60 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
  61 module_param_array(line_outs_monitor, bool, boot_devs, 0444);
  62 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
  63 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  64 MODULE_DESCRIPTION("RME Hammerfall DSP");
  65 MODULE_LICENSE("GPL");
  66 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  67                 "{RME HDSP-9652},"
  68                 "{RME HDSP-9632}}");
  69
  70 #define HDSP_MAX_CHANNELS        26
  71 #define HDSP_MAX_DS_CHANNELS     14
  72 #define HDSP_MAX_QS_CHANNELS     8
  73 #define DIGIFACE_SS_CHANNELS     26
  74 #define DIGIFACE_DS_CHANNELS     14
  75 #define MULTIFACE_SS_CHANNELS    18
  76 #define MULTIFACE_DS_CHANNELS    14
  77 #define H9652_SS_CHANNELS        26
  78 #define H9652_DS_CHANNELS        14
  79 /* This does not include possible Analog Extension Boards
  80    AEBs are detected at card initialization
  81 */
  82 #define H9632_SS_CHANNELS        12
  83 #define H9632_DS_CHANNELS        8
  84 #define H9632_QS_CHANNELS        4
  85
  86 /* Write registers. These are defined as byte-offsets from the iobase value.
  87  */
  88 #define HDSP_resetPointer               0
  89 #define HDSP_outputBufferAddress        32
  90 #define HDSP_inputBufferAddress         36
  91 #define HDSP_controlRegister            64
  92 #define HDSP_interruptConfirmation      96
  93 #define HDSP_outputEnable               128
  94 #define HDSP_control2Reg                256
  95 #define HDSP_midiDataOut0               352
  96 #define HDSP_midiDataOut1               356
  97 #define HDSP_fifoData                   368
  98 #define HDSP_inputEnable                384
  99
 100 /* Read registers. These are defined as byte-offsets from the iobase value
 101  */
 102
 103 #define HDSP_statusRegister    0
 104 #define HDSP_timecode        128
 105 #define HDSP_status2Register 192
 106 #define HDSP_midiDataOut0    352
 107 #define HDSP_midiDataOut1    356
 108 #define HDSP_midiDataIn0     360
 109 #define HDSP_midiDataIn1     364
 110 #define HDSP_midiStatusOut0  384
 111 #define HDSP_midiStatusOut1  388
 112 #define HDSP_midiStatusIn0   392
 113 #define HDSP_midiStatusIn1   396
 114 #define HDSP_fifoStatus      400
 115
 116 /* the meters are regular i/o-mapped registers, but offset
 117    considerably from the rest. the peak registers are reset
 118    when read; the least-significant 4 bits are full-scale counters;
 119    the actual peak value is in the most-significant 24 bits.
 120 */
 121
 122 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 123 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 124 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 125 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 126 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 127
 128
 129 /* This is for H9652 cards
 130    Peak values are read downward from the base
 131    Rms values are read upward
 132    There are rms values for the outputs too
 133    26*3 values are read in ss mode
 134    14*3 in ds mode, with no gap between values
 135 */
 136 #define HDSP_9652_peakBase      7164
 137 #define HDSP_9652_rmsBase       4096
 138
 139 /* c.f. the hdsp_9632_meters_t struct */
 140 #define HDSP_9632_metersBase    4096
 141
 142 #define HDSP_IO_EXTENT     7168
 143
 144 /* control2 register bits */
 145
 146 #define HDSP_TMS                0x01
 147 #define HDSP_TCK                0x02
 148 #define HDSP_TDI                0x04
 149 #define HDSP_JTAG               0x08
 150 #define HDSP_PWDN               0x10
 151 #define HDSP_PROGRAM            0x020
 152 #define HDSP_CONFIG_MODE_0      0x040
 153 #define HDSP_CONFIG_MODE_1      0x080
 154 #define HDSP_VERSION_BIT        0x100
 155 #define HDSP_BIGENDIAN_MODE     0x200
 156 #define HDSP_RD_MULTIPLE        0x400
 157 #define HDSP_9652_ENABLE_MIXER  0x800
 158 #define HDSP_TDO                0x10000000
 159
 160 #define HDSP_S_PROGRAM          (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 161 #define HDSP_S_LOAD             (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 162
 163 /* Control Register bits */
 164
 165 #define HDSP_Start                (1<<0)  /* start engine */
 166 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 167 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 168 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 169 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 170 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 171 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 172 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 173 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 174 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 175 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 176 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 177 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 178 #define HDSP_SyncRef2             (1<<13)
 179 #define HDSP_SPDIFInputSelect0    (1<<14)
 180 #define HDSP_SPDIFInputSelect1    (1<<15)
 181 #define HDSP_SyncRef0             (1<<16)
 182 #define HDSP_SyncRef1             (1<<17)
 183 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 184 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 185 #define HDSP_Midi0InterruptEnable (1<<22)
 186 #define HDSP_Midi1InterruptEnable (1<<23)
 187 #define HDSP_LineOut              (1<<24)
 188 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 189 #define HDSP_ADGain1              (1<<26)
 190 #define HDSP_DAGain0              (1<<27)
 191 #define HDSP_DAGain1              (1<<28)
 192 #define HDSP_PhoneGain0           (1<<29)
 193 #define HDSP_PhoneGain1           (1<<30)
 194 #define HDSP_QuadSpeed            (1<<31)
 195
 196 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 197 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 198 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 199 #define HDSP_ADGainLowGain     0
 200
 201 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 202 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 203 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 204 #define HDSP_DAGainMinus10dBV    0
 205
 206 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 207 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 208 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 209 #define HDSP_PhoneGainMinus12dB  0
 210
 211 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 212 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 213
 214 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 215 #define HDSP_SPDIFInputADAT1    0
 216 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 217 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 218 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 219
 220 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 221 #define HDSP_SyncRef_ADAT1       0
 222 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 223 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 224 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 225 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 226 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 227
 228 /* Sample Clock Sources */
 229
 230 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 231 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 232 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 233 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 234 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 235 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 236 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 237 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 238 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 239 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 240
 241 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 242
 243 #define HDSP_SYNC_FROM_WORD      0
 244 #define HDSP_SYNC_FROM_SPDIF     1
 245 #define HDSP_SYNC_FROM_ADAT1     2
 246 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 247 #define HDSP_SYNC_FROM_ADAT2     4
 248 #define HDSP_SYNC_FROM_ADAT3     5
 249
 250 /* SyncCheck status */
 251
 252 #define HDSP_SYNC_CHECK_NO_LOCK 0
 253 #define HDSP_SYNC_CHECK_LOCK    1
 254 #define HDSP_SYNC_CHECK_SYNC    2
 255
 256 /* AutoSync references - used by "autosync_ref" control switch */
 257
 258 #define HDSP_AUTOSYNC_FROM_WORD      0
 259 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 260 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 261 #define HDSP_AUTOSYNC_FROM_NONE      3
 262 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 263 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 264 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 265
 266 /* Possible sources of S/PDIF input */
 267
 268 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 269 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 270 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 271 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 272
 273 #define HDSP_Frequency32KHz    HDSP_Frequency0
 274 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 275 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 276 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 277 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 278 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 279 /* For H9632 cards */
 280 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 281 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 282 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 283
 284 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 285 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 286
 287 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 288 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 289
 290 /* Status Register bits */
 291
 292 #define HDSP_audioIRQPending    (1<<0)
 293 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 294 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 295 #define HDSP_Lock1              (1<<2)
 296 #define HDSP_Lock0              (1<<3)
 297 #define HDSP_SPDIFSync          (1<<4)
 298 #define HDSP_TimecodeLock       (1<<5)
 299 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 300 #define HDSP_Sync2              (1<<16)
 301 #define HDSP_Sync1              (1<<17)
 302 #define HDSP_Sync0              (1<<18)
 303 #define HDSP_DoubleSpeedStatus  (1<<19)
 304 #define HDSP_ConfigError        (1<<20)
 305 #define HDSP_DllError           (1<<21)
 306 #define HDSP_spdifFrequency0    (1<<22)
 307 #define HDSP_spdifFrequency1    (1<<23)
 308 #define HDSP_spdifFrequency2    (1<<24)
 309 #define HDSP_SPDIFErrorFlag     (1<<25)
 310 #define HDSP_BufferID           (1<<26)
 311 #define HDSP_TimecodeSync       (1<<27)
 312 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 313 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 314 #define HDSP_midi0IRQPending    (1<<30)
 315 #define HDSP_midi1IRQPending    (1<<31)
 316
 317 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 318
 319 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 320 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 321 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 322
 323 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 324 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 325 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 326
 327 /* This is for H9632 cards */
 328 #define HDSP_spdifFrequency128KHz   HDSP_spdifFrequencyMask
 329 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 330 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 331
 332 /* Status2 Register bits */
 333
 334 #define HDSP_version0     (1<<0)
 335 #define HDSP_version1     (1<<1)
 336 #define HDSP_version2     (1<<2)
 337 #define HDSP_wc_lock      (1<<3)
 338 #define HDSP_wc_sync      (1<<4)
 339 #define HDSP_inp_freq0    (1<<5)
 340 #define HDSP_inp_freq1    (1<<6)
 341 #define HDSP_inp_freq2    (1<<7)
 342 #define HDSP_SelSyncRef0  (1<<8)
 343 #define HDSP_SelSyncRef1  (1<<9)
 344 #define HDSP_SelSyncRef2  (1<<10)
 345
 346 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 347
 348 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 349 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 350 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 351 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 352 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 353 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 354 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 355 /* FIXME : more values for 9632 cards ? */
 356
 357 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 358 #define HDSP_SelSyncRef_ADAT1      0
 359 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 360 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 361 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 362 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 363 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 364
 365 /* Card state flags */
 366
 367 #define HDSP_InitializationComplete  (1<<0)
 368 #define HDSP_FirmwareLoaded          (1<<1)
 369 #define HDSP_FirmwareCached          (1<<2)
 370
 371 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 372
 373 #define HDSP_LONG_WAIT   5000
 374 #define HDSP_SHORT_WAIT  30
 375
 376 #define UNITY_GAIN                       32768
 377 #define MINUS_INFINITY_GAIN              0
 378
 379 #ifndef PCI_VENDOR_ID_XILINX
 380 #define PCI_VENDOR_ID_XILINX            0x10ee
 381 #endif
 382 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
 383 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
 384 #endif
 385
 386 /* the size of a substream (1 mono data stream) */
 387
 388 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 389 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 390
 391 /* the size of the area we need to allocate for DMA transfers. the
 392    size is the same regardless of the number of channels - the
 393    Multiface still uses the same memory area.
 394
 395    Note that we allocate 1 more channel than is apparently needed
 396    because the h/w seems to write 1 byte beyond the end of the last
 397    page. Sigh.
 398 */
 399
 400 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 401 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 402
 403 typedef struct _hdsp             hdsp_t;
 404 typedef struct _hdsp_midi        hdsp_midi_t;
 405 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
 406
 407 struct _hdsp_9632_meters {
 408     u32 input_peak[16];
 409     u32 playback_peak[16];
 410     u32 output_peak[16];
 411     u32 xxx_peak[16];
 412     u32 padding[64];
 413     u32 input_rms_low[16];
 414     u32 playback_rms_low[16];
 415     u32 output_rms_low[16];
 416     u32 xxx_rms_low[16];
 417     u32 input_rms_high[16];
 418     u32 playback_rms_high[16];
 419     u32 output_rms_high[16];
 420     u32 xxx_rms_high[16];
 421 };
 422
 423 struct _hdsp_midi {
 424     hdsp_t                  *hdsp;
 425     int                      id;
 426     snd_rawmidi_t           *rmidi;
 427     snd_rawmidi_substream_t *input;
 428     snd_rawmidi_substream_t *output;
 429     char                     istimer; /* timer in use */
 430     struct timer_list        timer;
 431     spinlock_t               lock;
 432     int                      pending;
 433 };
 434
 435 struct _hdsp {
 436         spinlock_t            lock;
 437         snd_pcm_substream_t  *capture_substream;
 438         snd_pcm_substream_t  *playback_substream;
 439         hdsp_midi_t           midi[2];
 440         struct tasklet_struct midi_tasklet;
 441         int                   precise_ptr;
 442         u32                   control_register;      /* cached value */
 443         u32                   control2_register;     /* cached value */
 444         u32                   creg_spdif;
 445         u32                   creg_spdif_stream;
 446         char                 *card_name;             /* digiface/multiface */
 447         HDSP_IO_Type          io_type;               /* ditto, but for code use */
 448         unsigned short        firmware_rev;
 449         unsigned short        state;                 /* stores state bits */
 450         u32                   firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
 451         size_t                period_bytes;          /* guess what this is */
 452         unsigned char         max_channels;
 453         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 454         unsigned char         ds_in_channels;
 455         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 456         unsigned char         qs_out_channels;
 457         unsigned char         ds_out_channels;
 458         unsigned char         ss_out_channels;
 459
 460         struct snd_dma_buffer capture_dma_buf;
 461         struct snd_dma_buffer playback_dma_buf;
 462         unsigned char        *capture_buffer;       /* suitably aligned address */
 463         unsigned char        *playback_buffer;      /* suitably aligned address */
 464
 465         pid_t                 capture_pid;
 466         pid_t                 playback_pid;
 467         int                   running;
 468         int                   passthru;              /* non-zero if doing pass-thru */
 469         int                   system_sample_rate;
 470         char                 *channel_map;
 471         int                   dev;
 472         int                   irq;
 473         unsigned long         port;
 474         unsigned long         iobase;
 475         snd_card_t           *card;
 476         snd_pcm_t            *pcm;
 477         snd_hwdep_t          *hwdep;
 478         struct pci_dev       *pci;
 479         snd_kcontrol_t       *spdif_ctl;
 480         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 481 };
 482
 483 /* These tables map the ALSA channels 1..N to the channels that we
 484    need to use in order to find the relevant channel buffer. RME
 485    refer to this kind of mapping as between "the ADAT channel and
 486    the DMA channel." We index it using the logical audio channel,
 487    and the value is the DMA channel (i.e. channel buffer number)
 488    where the data for that channel can be read/written from/to.
 489 */
 490
 491 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 492         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 493         18, 19, 20, 21, 22, 23, 24, 25
 494 };
 495
 496 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 497         /* Analog */
 498         0, 1, 2, 3, 4, 5, 6, 7,
 499         /* ADAT 2 */
 500         16, 17, 18, 19, 20, 21, 22, 23,
 501         /* SPDIF */
 502         24, 25,
 503         -1, -1, -1, -1, -1, -1, -1, -1
 504 };
 505
 506 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 507         /* ADAT channels are remapped */
 508         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 509         /* channels 12 and 13 are S/PDIF */
 510         24, 25,
 511         /* others don't exist */
 512         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 513 };
 514
 515 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 516         /* ADAT channels */
 517         0, 1, 2, 3, 4, 5, 6, 7,
 518         /* SPDIF */
 519         8, 9,
 520         /* Analog */
 521         10, 11,
 522         /* AO4S-192 and AI4S-192 extension boards */
 523         12, 13, 14, 15,
 524         /* others don't exist */
 525         -1, -1, -1, -1, -1, -1, -1, -1,
 526         -1, -1
 527 };
 528
 529 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 530         /* ADAT */
 531         1, 3, 5, 7,
 532         /* SPDIF */
 533         8, 9,
 534         /* Analog */
 535         10, 11,
 536         /* AO4S-192 and AI4S-192 extension boards */
 537         12, 13, 14, 15,
 538         /* others don't exist */
 539         -1, -1, -1, -1, -1, -1, -1, -1,
 540         -1, -1, -1, -1, -1, -1
 541 };
 542
 543 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 544         /* ADAT is disabled in this mode */
 545         /* SPDIF */
 546         8, 9,
 547         /* Analog */
 548         10, 11,
 549         /* AO4S-192 and AI4S-192 extension boards */
 550         12, 13, 14, 15,
 551         /* others don't exist */
 552         -1, -1, -1, -1, -1, -1, -1, -1,
 553         -1, -1, -1, -1, -1, -1, -1, -1,
 554         -1, -1
 555 };
 556
 557 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 558 {
 559         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 560         dmab->dev.dev = snd_dma_pci_data(pci);
 561         if (! snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
 562                 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 563                                         size, dmab) < 0)
 564                         return -ENOMEM;
 565         }
 566         return 0;
 567 }
 568
 569 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 570 {
 571         if (dmab->area)
 572                 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
 573 }
 574
 575
 576 static struct pci_device_id snd_hdsp_ids[] = {
 577         {
 578                 .vendor = PCI_VENDOR_ID_XILINX,
 579                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 580                 .subvendor = PCI_ANY_ID,
 581                 .subdevice = PCI_ANY_ID,
 582         }, /* RME Hammerfall-DSP */
 583         { 0, },
 584 };
 585
 586 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 587
 588 /* prototypes */
 589 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
 590 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
 591 static int snd_hdsp_enable_io (hdsp_t *hdsp);
 592 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
 593 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
 594 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
 595 static int hdsp_autosync_ref(hdsp_t *hdsp);
 596 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
 597 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
 598
 599 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
 600 {
 601         switch (hdsp->firmware_rev) {
 602         case 0xa:
 603                 return (64 * out) + (32 + (in));
 604         case 0x96:
 605         case 0x97:
 606                 return (32 * out) + (16 + (in));
 607         default:
 608                 return (52 * out) + (26 + (in));
 609         }
 610 }
 611
 612 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
 613 {
 614         switch (hdsp->firmware_rev) {
 615         case 0xa:
 616                 return (64 * out) + in;
 617         case 0x96:
 618         case 0x97:
 619                 return (32 * out) + in;
 620         default:
 621                 return (52 * out) + in;
 622         }
 623 }
 624
 625 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
 626 {
 627         writel(val, hdsp->iobase + reg);
 628 }
 629
 630 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
 631 {
 632         return readl (hdsp->iobase + reg);
 633 }
 634
 635 static int hdsp_check_for_iobox (hdsp_t *hdsp)
 636 {
 637
 638         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 639         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
 640                 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
 641                 hdsp->state &= ~HDSP_FirmwareLoaded;
 642                 return -EIO;
 643         }
 644         return 0;
 645
 646 }
 647
 648 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
 649
 650         int i;
 651         unsigned long flags;
 652
 653         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 654
 655                 snd_printk ("loading firmware\n");
 656
 657                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 658                 hdsp_write (hdsp, HDSP_fifoData, 0);
 659
 660                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 661                         snd_printk ("timeout waiting for download preparation\n");
 662                         return -EIO;
 663                 }
 664
 665                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 666
 667                 for (i = 0; i < 24413; ++i) {
 668                         hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
 669                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 670                                 snd_printk ("timeout during firmware loading\n");
 671                                 return -EIO;
 672                         }
 673                 }
 674
 675                 if ((1000 / HZ) < 3000) {
 676                         set_current_state(TASK_UNINTERRUPTIBLE);
 677                         schedule_timeout((3000 * HZ + 999) / 1000);
 678                 } else {
 679                         mdelay(3000);
 680                 }
 681
 682                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 683                         snd_printk ("timeout at end of firmware loading\n");
 684                         return -EIO;
 685                 }
 686
 687 #ifdef SNDRV_BIG_ENDIAN
 688                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 689 #else
 690                 hdsp->control2_register = 0;
 691 #endif
 692                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 693                 snd_printk ("finished firmware loading\n");
 694
 695         }
 696         if (hdsp->state & HDSP_InitializationComplete) {
 697                 snd_printk("firmware loaded from cache, restoring defaults\n");
 698                 spin_lock_irqsave(&hdsp->lock, flags);
 699                 snd_hdsp_set_defaults(hdsp);
 700                 spin_unlock_irqrestore(&hdsp->lock, flags);
 701         }
 702
 703         hdsp->state |= HDSP_FirmwareLoaded;
 704
 705         return 0;
 706 }
 707
 708 static int hdsp_get_iobox_version (hdsp_t *hdsp)
 709 {
 710         int err;
 711
 712         if (hdsp_check_for_iobox (hdsp)) {
 713                 return -EIO;
 714         }
 715
 716         if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
 717                 return err;
 718         }
 719
 720         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 721
 722                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
 723                 hdsp_write (hdsp, HDSP_fifoData, 0);
 724                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 725                         return -EIO;
 726                 }
 727
 728                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 729                 hdsp_write (hdsp, HDSP_fifoData, 0);
 730
 731                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
 732                         hdsp->io_type = Multiface;
 733                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
 734                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 735                         hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
 736                 } else {
 737                         hdsp->io_type = Digiface;
 738                 }
 739         } else {
 740                 /* firmware was already loaded, get iobox type */
 741                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
 742                         hdsp->io_type = Multiface;
 743                 } else {
 744                         hdsp->io_type = Digiface;
 745                 }
 746         }
 747         return 0;
 748 }
 749
 750
 751 static int hdsp_check_for_firmware (hdsp_t *hdsp)
 752 {
 753         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 754         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 755                 snd_printk("firmware not present.\n");
 756                 hdsp->state &= ~HDSP_FirmwareLoaded;
 757                 return -EIO;
 758         }
 759         return 0;
 760 }
 761
 762
 763 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
 764 {
 765         int i;
 766
 767         /* the fifoStatus registers reports on how many words
 768            are available in the command FIFO.
 769         */
 770
 771         for (i = 0; i < timeout; i++) {
 772
 773                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 774                         return 0;
 775
 776                 /* not very friendly, but we only do this during a firmware
 777                    load and changing the mixer, so we just put up with it.
 778                 */
 779
 780                 udelay (100);
 781         }
 782
 783         snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
 784                     count, timeout);
 785         return -1;
 786 }
 787
 788 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
 789 {
 790         if (addr >= HDSP_MATRIX_MIXER_SIZE) {
 791                 return 0;
 792         }
 793         return hdsp->mixer_matrix[addr];
 794 }
 795
 796 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
 797 {
 798         unsigned int ad;
 799
 800         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 801                 return -1;
 802
 803         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 804
 805                 /* from martin björnsen:
 806
 807                    "You can only write dwords to the
 808                    mixer memory which contain two
 809                    mixer values in the low and high
 810                    word. So if you want to change
 811                    value 0 you have to read value 1
 812                    from the cache and write both to
 813                    the first dword in the mixer
 814                    memory."
 815                 */
 816
 817                 if (hdsp->io_type == H9632 && addr >= 512) {
 818                         return 0;
 819                 }
 820
 821                 if (hdsp->io_type == H9652 && addr >= 1352) {
 822                         return 0;
 823                 }
 824
 825                 hdsp->mixer_matrix[addr] = data;
 826
 827
 828                 /* `addr' addresses a 16-bit wide address, but
 829                    the address space accessed via hdsp_write
 830                    uses byte offsets. put another way, addr
 831                    varies from 0 to 1351, but to access the
 832                    corresponding memory location, we need
 833                    to access 0 to 2703 ...
 834                 */
 835                 ad = addr/2;
 836
 837                 hdsp_write (hdsp, 4096 + (ad*4),
 838                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 839                             hdsp->mixer_matrix[addr&0x7fe]);
 840
 841                 return 0;
 842
 843         } else {
 844
 845                 ad = (addr << 16) + data;
 846
 847                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
 848                         return -1;
 849                 }
 850
 851                 hdsp_write (hdsp, HDSP_fifoData, ad);
 852                 hdsp->mixer_matrix[addr] = data;
 853
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
 860 {
 861         unsigned long flags;
 862         int ret = 1;
 863
 864         spin_lock_irqsave(&hdsp->lock, flags);
 865         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 866             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
 867                 ret = 0;
 868         }
 869         spin_unlock_irqrestore(&hdsp->lock, flags);
 870         return ret;
 871 }
 872
 873 static int hdsp_external_sample_rate (hdsp_t *hdsp)
 874 {
 875         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 876         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 877
 878         switch (rate_bits) {
 879         case HDSP_systemFrequency32:   return 32000;
 880         case HDSP_systemFrequency44_1: return 44100;
 881         case HDSP_systemFrequency48:   return 48000;
 882         case HDSP_systemFrequency64:   return 64000;
 883         case HDSP_systemFrequency88_2: return 88200;
 884         case HDSP_systemFrequency96:   return 96000;
 885         default:
 886                 return 0;
 887         }
 888 }
 889
 890 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
 891 {
 892         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 893         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 894
 895         if (status & HDSP_SPDIFErrorFlag) {
 896                 return 0;
 897         }
 898
 899         switch (rate_bits) {
 900         case HDSP_spdifFrequency32KHz: return 32000;
 901         case HDSP_spdifFrequency44_1KHz: return 44100;
 902         case HDSP_spdifFrequency48KHz: return 48000;
 903         case HDSP_spdifFrequency64KHz: return 64000;
 904         case HDSP_spdifFrequency88_2KHz: return 88200;
 905         case HDSP_spdifFrequency96KHz: return 96000;
 906         case HDSP_spdifFrequency128KHz:
 907                 if (hdsp->io_type == H9632) return 128000;
 908                 break;
 909         case HDSP_spdifFrequency176_4KHz:
 910                 if (hdsp->io_type == H9632) return 176400;
 911                 break;
 912         case HDSP_spdifFrequency192KHz:
 913                 if (hdsp->io_type == H9632) return 192000;
 914                 break;
 915         default:
 916                 break;
 917         }
 918         snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
 919         return 0;
 920 }
 921
 922 static void hdsp_compute_period_size(hdsp_t *hdsp)
 923 {
 924         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
 925 }
 926
 927 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
 928 {
 929         int position;
 930
 931         position = hdsp_read(hdsp, HDSP_statusRegister);
 932
 933         if (!hdsp->precise_ptr) {
 934                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
 935         }
 936
 937         position &= HDSP_BufferPositionMask;
 938         position /= 4;
 939         position -= 32;
 940         position &= (HDSP_CHANNEL_BUFFER_SAMPLES-1);
 941         return position;
 942 }
 943
 944 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
 945 {
 946         hdsp_write (hdsp, HDSP_resetPointer, 0);
 947 }
 948
 949 static void hdsp_start_audio(hdsp_t *s)
 950 {
 951         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
 952         hdsp_write(s, HDSP_controlRegister, s->control_register);
 953 }
 954
 955 static void hdsp_stop_audio(hdsp_t *s)
 956 {
 957         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
 958         hdsp_write(s, HDSP_controlRegister, s->control_register);
 959 }
 960
 961 static void hdsp_silence_playback(hdsp_t *hdsp)
 962 {
 963         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
 964 }
 965
 966 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
 967 {
 968         int n;
 969
 970         spin_lock_irq(&s->lock);
 971
 972         frames >>= 7;
 973         n = 0;
 974         while (frames) {
 975                 n++;
 976                 frames >>= 1;
 977         }
 978
 979         s->control_register &= ~HDSP_LatencyMask;
 980         s->control_register |= hdsp_encode_latency(n);
 981
 982         hdsp_write(s, HDSP_controlRegister, s->control_register);
 983
 984         hdsp_compute_period_size(s);
 985
 986         spin_unlock_irq(&s->lock);
 987
 988         return 0;
 989 }
 990
 991 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
 992 {
 993         int reject_if_open = 0;
 994         int current_rate;
 995         int rate_bits;
 996
 997         /* ASSUMPTION: hdsp->lock is either held, or
 998            there is no need for it (e.g. during module
 999            initialization).
1000         */
1001
1002         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1003                 if (called_internally) {
1004                         /* request from ctl or card initialization */
1005                         snd_printk("device is not running as a clock master: cannot set sample rate.\n");
1006                         return -1;
1007                 } else {
1008                         /* hw_param request while in AutoSync mode */
1009                         int external_freq = hdsp_external_sample_rate(hdsp);
1010                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1011
1012                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1013                                 snd_printk("Detected ADAT in double speed mode\n");
1014                         } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1015                                 snd_printk("Detected ADAT in quad speed mode\n");
1016                         } else if (rate != external_freq) {
1017                                 snd_printk("No AutoSync source for requested rate\n");
1018                                 return -1;
1019                         }
1020                 }
1021         }
1022
1023         current_rate = hdsp->system_sample_rate;
1024
1025         /* Changing from a "single speed" to a "double speed" rate is
1026            not allowed if any substreams are open. This is because
1027            such a change causes a shift in the location of
1028            the DMA buffers and a reduction in the number of available
1029            buffers.
1030
1031            Note that a similar but essentially insoluble problem
1032            exists for externally-driven rate changes. All we can do
1033            is to flag rate changes in the read/write routines.  */
1034
1035         if (rate > 96000 && hdsp->io_type != H9632) {
1036                 return -EINVAL;
1037         }
1038
1039         switch (rate) {
1040         case 32000:
1041                 if (current_rate > 48000) {
1042                         reject_if_open = 1;
1043                 }
1044                 rate_bits = HDSP_Frequency32KHz;
1045                 break;
1046         case 44100:
1047                 if (current_rate > 48000) {
1048                         reject_if_open = 1;
1049                 }
1050                 rate_bits = HDSP_Frequency44_1KHz;
1051                 break;
1052         case 48000:
1053                 if (current_rate > 48000) {
1054                         reject_if_open = 1;
1055                 }
1056                 rate_bits = HDSP_Frequency48KHz;
1057                 break;
1058         case 64000:
1059                 if (current_rate <= 48000 || current_rate > 96000) {
1060                         reject_if_open = 1;
1061                 }
1062                 rate_bits = HDSP_Frequency64KHz;
1063                 break;
1064         case 88200:
1065                 if (current_rate <= 48000 || current_rate > 96000) {
1066                         reject_if_open = 1;
1067                 }
1068                 rate_bits = HDSP_Frequency88_2KHz;
1069                 break;
1070         case 96000:
1071                 if (current_rate <= 48000 || current_rate > 96000) {
1072                         reject_if_open = 1;
1073                 }
1074                 rate_bits = HDSP_Frequency96KHz;
1075                 break;
1076         case 128000:
1077                 if (current_rate < 128000) {
1078                         reject_if_open = 1;
1079                 }
1080                 rate_bits = HDSP_Frequency128KHz;
1081                 break;
1082         case 176400:
1083                 if (current_rate < 128000) {
1084                         reject_if_open = 1;
1085                 }
1086                 rate_bits = HDSP_Frequency176_4KHz;
1087                 break;
1088         case 192000:
1089                 if (current_rate < 128000) {
1090                         reject_if_open = 1;
1091                 }
1092                 rate_bits = HDSP_Frequency192KHz;
1093                 break;
1094         default:
1095                 return -EINVAL;
1096         }
1097
1098         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1099                 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1100                             hdsp->capture_pid,
1101                             hdsp->playback_pid);
1102                 return -EBUSY;
1103         }
1104
1105         hdsp->control_register &= ~HDSP_FrequencyMask;
1106         hdsp->control_register |= rate_bits;
1107         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1108
1109         if (rate >= 128000) {
1110                 hdsp->channel_map = channel_map_H9632_qs;
1111         } else if (rate > 48000) {
1112                 if (hdsp->io_type == H9632) {
1113                         hdsp->channel_map = channel_map_H9632_ds;
1114                 } else {
1115                         hdsp->channel_map = channel_map_ds;
1116                 }
1117         } else {
1118                 switch (hdsp->io_type) {
1119                 case Multiface:
1120                         hdsp->channel_map = channel_map_mf_ss;
1121                         break;
1122                 case Digiface:
1123                 case H9652:
1124                         hdsp->channel_map = channel_map_df_ss;
1125                         break;
1126                 case H9632:
1127                         hdsp->channel_map = channel_map_H9632_ss;
1128                         break;
1129                 default:
1130                         /* should never happen */
1131                         break;
1132                 }
1133         }
1134
1135         hdsp->system_sample_rate = rate;
1136
1137         return 0;
1138 }
1139
1140 static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
1141 {
1142
1143         hdsp->passthru = 0;
1144
1145         if (channel < 0) {
1146
1147                 int i;
1148
1149                 /* set thru for all channels */
1150
1151                 if (enable) {
1152                         for (i = 0; i < hdsp->max_channels; i++) {
1153                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN);
1154                         }
1155                 } else {
1156                         for (i = 0; i < hdsp->max_channels; i++) {
1157                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN);
1158                         }
1159                 }
1160
1161         } else {
1162                 int mapped_channel;
1163
1164                 snd_assert(channel < hdsp->max_channels, return);
1165
1166                 mapped_channel = hdsp->channel_map[channel];
1167
1168                 snd_assert(mapped_channel > -1, return);
1169
1170                 if (enable) {
1171                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN);
1172                 } else {
1173                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN);
1174                 }
1175         }
1176 }
1177
1178 static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
1179 {
1180         if (onoff) {
1181                 hdsp_set_thru(hdsp, -1, 1);
1182                 hdsp_reset_hw_pointer(hdsp);
1183                 hdsp_silence_playback(hdsp);
1184
1185                 /* we don't want interrupts, so do a
1186                    custom version of hdsp_start_audio().
1187                 */
1188
1189                 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
1190
1191                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1192                 hdsp->passthru = 1;
1193         } else {
1194                 hdsp_set_thru(hdsp, -1, 0);
1195                 hdsp_stop_audio(hdsp);
1196                 hdsp->passthru = 0;
1197         }
1198
1199         return 0;
1200 }
1201
1202 /*----------------------------------------------------------------------------
1203    MIDI
1204   ----------------------------------------------------------------------------*/
1205
1206 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1207 {
1208         /* the hardware already does the relevant bit-mask with 0xff */
1209         if (id) {
1210                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1211         } else {
1212                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1213         }
1214 }
1215
1216 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1217 {
1218         /* the hardware already does the relevant bit-mask with 0xff */
1219         if (id) {
1220                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1221         } else {
1222                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1223         }
1224 }
1225
1226 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1227 {
1228         if (id) {
1229                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1230         } else {
1231                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1232         }
1233 }
1234
1235 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1236 {
1237         int fifo_bytes_used;
1238
1239         if (id) {
1240                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1241         } else {
1242                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1243         }
1244
1245         if (fifo_bytes_used < 128) {
1246                 return  128 - fifo_bytes_used;
1247         } else {
1248                 return 0;
1249         }
1250 }
1251
1252 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1253 {
1254         while (snd_hdsp_midi_input_available (hdsp, id)) {
1255                 snd_hdsp_midi_read_byte (hdsp, id);
1256         }
1257 }
1258
1259 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1260 {
1261         unsigned long flags;
1262         int n_pending;
1263         int to_write;
1264         int i;
1265         unsigned char buf[128];
1266
1267         /* Output is not interrupt driven */
1268
1269         spin_lock_irqsave (&hmidi->lock, flags);
1270         if (hmidi->output) {
1271                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1272                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1273                                 if (n_pending > (int)sizeof (buf))
1274                                         n_pending = sizeof (buf);
1275
1276                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1277                                         for (i = 0; i < to_write; ++i)
1278                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1279                                 }
1280                         }
1281                 }
1282         }
1283         spin_unlock_irqrestore (&hmidi->lock, flags);
1284         return 0;
1285 }
1286
1287 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1288 {
1289         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1290         unsigned long flags;
1291         int n_pending;
1292         int i;
1293
1294         spin_lock_irqsave (&hmidi->lock, flags);
1295         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1296                 if (hmidi->input) {
1297                         if (n_pending > (int)sizeof (buf)) {
1298                                 n_pending = sizeof (buf);
1299                         }
1300                         for (i = 0; i < n_pending; ++i) {
1301                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1302                         }
1303                         if (n_pending) {
1304                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1305                         }
1306                 } else {
1307                         /* flush the MIDI input FIFO */
1308                         while (--n_pending) {
1309                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1310                         }
1311                 }
1312         }
1313         hmidi->pending = 0;
1314         if (hmidi->id) {
1315                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1316         } else {
1317                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1318         }
1319         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1320         spin_unlock_irqrestore (&hmidi->lock, flags);
1321         return snd_hdsp_midi_output_write (hmidi);
1322 }
1323
1324 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1325 {
1326         hdsp_t *hdsp;
1327         hdsp_midi_t *hmidi;
1328         unsigned long flags;
1329         u32 ie;
1330
1331         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1332         hdsp = hmidi->hdsp;
1333         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1334         spin_lock_irqsave (&hdsp->lock, flags);
1335         if (up) {
1336                 if (!(hdsp->control_register & ie)) {
1337                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1338                         hdsp->control_register |= ie;
1339                 }
1340         } else {
1341                 hdsp->control_register &= ~ie;
1342         }
1343
1344         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1345         spin_unlock_irqrestore (&hdsp->lock, flags);
1346 }
1347
1348 static void snd_hdsp_midi_output_timer(unsigned long data)
1349 {
1350         hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1351         unsigned long flags;
1352
1353         snd_hdsp_midi_output_write(hmidi);
1354         spin_lock_irqsave (&hmidi->lock, flags);
1355
1356         /* this does not bump hmidi->istimer, because the
1357            kernel automatically removed the timer when it
1358            expired, and we are now adding it back, thus
1359            leaving istimer wherever it was set before.
1360         */
1361
1362         if (hmidi->istimer) {
1363                 hmidi->timer.expires = 1 + jiffies;
1364                 add_timer(&hmidi->timer);
1365         }
1366
1367         spin_unlock_irqrestore (&hmidi->lock, flags);
1368 }
1369
1370 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1371 {
1372         hdsp_midi_t *hmidi;
1373         unsigned long flags;
1374
1375         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1376         spin_lock_irqsave (&hmidi->lock, flags);
1377         if (up) {
1378                 if (!hmidi->istimer) {
1379                         init_timer(&hmidi->timer);
1380                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1381                         hmidi->timer.data = (unsigned long) hmidi;
1382                         hmidi->timer.expires = 1 + jiffies;
1383                         add_timer(&hmidi->timer);
1384                         hmidi->istimer++;
1385                 }
1386         } else {
1387                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1388                         del_timer (&hmidi->timer);
1389                 }
1390         }
1391         spin_unlock_irqrestore (&hmidi->lock, flags);
1392         if (up)
1393                 snd_hdsp_midi_output_write(hmidi);
1394 }
1395
1396 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1397 {
1398         hdsp_midi_t *hmidi;
1399
1400         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1401         spin_lock_irq (&hmidi->lock);
1402         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1403         hmidi->input = substream;
1404         spin_unlock_irq (&hmidi->lock);
1405
1406         return 0;
1407 }
1408
1409 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1410 {
1411         hdsp_midi_t *hmidi;
1412
1413         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1414         spin_lock_irq (&hmidi->lock);
1415         hmidi->output = substream;
1416         spin_unlock_irq (&hmidi->lock);
1417
1418         return 0;
1419 }
1420
1421 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1422 {
1423         hdsp_midi_t *hmidi;
1424
1425         snd_hdsp_midi_input_trigger (substream, 0);
1426
1427         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1428         spin_lock_irq (&hmidi->lock);
1429         hmidi->input = NULL;
1430         spin_unlock_irq (&hmidi->lock);
1431
1432         return 0;
1433 }
1434
1435 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1436 {
1437         hdsp_midi_t *hmidi;
1438
1439         snd_hdsp_midi_output_trigger (substream, 0);
1440
1441         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1442         spin_lock_irq (&hmidi->lock);
1443         hmidi->output = NULL;
1444         spin_unlock_irq (&hmidi->lock);
1445
1446         return 0;
1447 }
1448
1449 snd_rawmidi_ops_t snd_hdsp_midi_output =
1450 {
1451         .open =         snd_hdsp_midi_output_open,
1452         .close =        snd_hdsp_midi_output_close,
1453         .trigger =      snd_hdsp_midi_output_trigger,
1454 };
1455
1456 snd_rawmidi_ops_t snd_hdsp_midi_input =
1457 {
1458         .open =         snd_hdsp_midi_input_open,
1459         .close =        snd_hdsp_midi_input_close,
1460         .trigger =      snd_hdsp_midi_input_trigger,
1461 };
1462
1463 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1464 {
1465         char buf[32];
1466
1467         hdsp->midi[id].id = id;
1468         hdsp->midi[id].rmidi = NULL;
1469         hdsp->midi[id].input = NULL;
1470         hdsp->midi[id].output = NULL;
1471         hdsp->midi[id].hdsp = hdsp;
1472         hdsp->midi[id].istimer = 0;
1473         hdsp->midi[id].pending = 0;
1474         spin_lock_init (&hdsp->midi[id].lock);
1475
1476         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1477         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1478                 return -1;
1479         }
1480
1481         sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1482         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1483
1484         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1485         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1486
1487         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1488                 SNDRV_RAWMIDI_INFO_INPUT |
1489                 SNDRV_RAWMIDI_INFO_DUPLEX;
1490
1491         return 0;
1492 }
1493
1494 /*-----------------------------------------------------------------------------
1495   Control Interface
1496   ----------------------------------------------------------------------------*/
1497
1498 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1499 {
1500         u32 val = 0;
1501         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1502         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1503         if (val & HDSP_SPDIFProfessional)
1504                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1505         else
1506                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1507         return val;
1508 }
1509
1510 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1511 {
1512         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1513                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1514         if (val & HDSP_SPDIFProfessional)
1515                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1516         else
1517                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1518 }
1519
1520 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1521 {
1522         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1523         uinfo->count = 1;
1524         return 0;
1525 }
1526
1527 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1528 {
1529         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1530
1531         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1532         return 0;
1533 }
1534
1535 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1536 {
1537         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1538         int change;
1539         u32 val;
1540
1541         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1542         spin_lock_irq(&hdsp->lock);
1543         change = val != hdsp->creg_spdif;
1544         hdsp->creg_spdif = val;
1545         spin_unlock_irq(&hdsp->lock);
1546         return change;
1547 }
1548
1549 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1550 {
1551         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1552         uinfo->count = 1;
1553         return 0;
1554 }
1555
1556 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1557 {
1558         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1559
1560         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1561         return 0;
1562 }
1563
1564 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1565 {
1566         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1567         int change;
1568         u32 val;
1569
1570         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1571         spin_lock_irq(&hdsp->lock);
1572         change = val != hdsp->creg_spdif_stream;
1573         hdsp->creg_spdif_stream = val;
1574         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1575         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1576         spin_unlock_irq(&hdsp->lock);
1577         return change;
1578 }
1579
1580 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1581 {
1582         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1583         uinfo->count = 1;
1584         return 0;
1585 }
1586
1587 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1588 {
1589         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1590         return 0;
1591 }
1592
1593 #define HDSP_SPDIF_IN(xname, xindex) \
1594 { .iface = SNDRV_CTL_ELEM_IFACE_PCM,  \
1595   .name = xname, \
1596   .index = xindex, \
1597   .info = snd_hdsp_info_spdif_in, \
1598   .get = snd_hdsp_get_spdif_in, \
1599   .put = snd_hdsp_put_spdif_in }
1600
1601 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1602 {
1603         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1604 }
1605
1606 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1607 {
1608         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1609         hdsp->control_register |= hdsp_encode_spdif_in(in);
1610         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1611         return 0;
1612 }
1613
1614 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1615 {
1616         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1617         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1618
1619         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1620         uinfo->count = 1;
1621         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1622         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1623                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1624         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1625         return 0;
1626 }
1627
1628 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1629 {
1630         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1631
1632         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1633         return 0;
1634 }
1635
1636 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1637 {
1638         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1639         int change;
1640         unsigned int val;
1641
1642         if (!snd_hdsp_use_is_exclusive(hdsp))
1643                 return -EBUSY;
1644         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1645         spin_lock_irq(&hdsp->lock);
1646         change = val != hdsp_spdif_in(hdsp);
1647         if (change)
1648                 hdsp_set_spdif_input(hdsp, val);
1649         spin_unlock_irq(&hdsp->lock);
1650         return change;
1651 }
1652
1653 #define HDSP_SPDIF_OUT(xname, xindex) \
1654 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1655   .info = snd_hdsp_info_spdif_bits, \
1656   .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1657
1658 static int hdsp_spdif_out(hdsp_t *hdsp)
1659 {
1660         return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1661 }
1662
1663 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1664 {
1665         if (out) {
1666                 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1667         } else {
1668                 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1669         }
1670         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1671         return 0;
1672 }
1673
1674 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1675 {
1676         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1677         uinfo->count = 1;
1678         uinfo->value.integer.min = 0;
1679         uinfo->value.integer.max = 1;
1680         return 0;
1681 }
1682
1683 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1684 {
1685         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1686
1687         ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1688         return 0;
1689 }
1690
1691 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1692 {
1693         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1694         int change;
1695         unsigned int val;
1696
1697         if (!snd_hdsp_use_is_exclusive(hdsp))
1698                 return -EBUSY;
1699         val = ucontrol->value.integer.value[0] & 1;
1700         spin_lock_irq(&hdsp->lock);
1701         change = (int)val != hdsp_spdif_out(hdsp);
1702         hdsp_set_spdif_output(hdsp, val);
1703         spin_unlock_irq(&hdsp->lock);
1704         return change;
1705 }
1706
1707 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1708 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1709   .info = snd_hdsp_info_spdif_bits, \
1710   .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1711
1712 static int hdsp_spdif_professional(hdsp_t *hdsp)
1713 {
1714         return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1715 }
1716
1717 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1718 {
1719         if (val) {
1720                 hdsp->control_register |= HDSP_SPDIFProfessional;
1721         } else {
1722                 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1723         }
1724         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1725         return 0;
1726 }
1727
1728 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1729 {
1730         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1731
1732         ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1733         return 0;
1734 }
1735
1736 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1737 {
1738         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1739         int change;
1740         unsigned int val;
1741
1742         if (!snd_hdsp_use_is_exclusive(hdsp))
1743                 return -EBUSY;
1744         val = ucontrol->value.integer.value[0] & 1;
1745         spin_lock_irq(&hdsp->lock);
1746         change = (int)val != hdsp_spdif_professional(hdsp);
1747         hdsp_set_spdif_professional(hdsp, val);
1748         spin_unlock_irq(&hdsp->lock);
1749         return change;
1750 }
1751
1752 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1753 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1754   .info = snd_hdsp_info_spdif_bits, \
1755   .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1756
1757 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1758 {
1759         return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1760 }
1761
1762 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1763 {
1764         if (val) {
1765                 hdsp->control_register |= HDSP_SPDIFEmphasis;
1766         } else {
1767                 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1768         }
1769         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1770         return 0;
1771 }
1772
1773 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1774 {
1775         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1776
1777         ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1778         return 0;
1779 }
1780
1781 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1782 {
1783         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1784         int change;
1785         unsigned int val;
1786
1787         if (!snd_hdsp_use_is_exclusive(hdsp))
1788                 return -EBUSY;
1789         val = ucontrol->value.integer.value[0] & 1;
1790         spin_lock_irq(&hdsp->lock);
1791         change = (int)val != hdsp_spdif_emphasis(hdsp);
1792         hdsp_set_spdif_emphasis(hdsp, val);
1793         spin_unlock_irq(&hdsp->lock);
1794         return change;
1795 }
1796
1797 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1798 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1799   .info = snd_hdsp_info_spdif_bits, \
1800   .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1801
1802 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1803 {
1804         return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1805 }
1806
1807 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1808 {
1809         if (val) {
1810                 hdsp->control_register |= HDSP_SPDIFNonAudio;
1811         } else {
1812                 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1813         }
1814         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1815         return 0;
1816 }
1817
1818 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1819 {
1820         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1821
1822         ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1823         return 0;
1824 }
1825
1826 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1827 {
1828         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1829         int change;
1830         unsigned int val;
1831
1832         if (!snd_hdsp_use_is_exclusive(hdsp))
1833                 return -EBUSY;
1834         val = ucontrol->value.integer.value[0] & 1;
1835         spin_lock_irq(&hdsp->lock);
1836         change = (int)val != hdsp_spdif_nonaudio(hdsp);
1837         hdsp_set_spdif_nonaudio(hdsp, val);
1838         spin_unlock_irq(&hdsp->lock);
1839         return change;
1840 }
1841
1842 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1843 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1844   .name = xname, \
1845   .index = xindex, \
1846   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1847   .info = snd_hdsp_info_spdif_sample_rate, \
1848   .get = snd_hdsp_get_spdif_sample_rate \
1849 }
1850
1851 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1852 {
1853         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1854         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1855
1856         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1857         uinfo->count = 1;
1858         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1859         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1860                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1861         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1862         return 0;
1863 }
1864
1865 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1866 {
1867         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1868
1869         switch (hdsp_spdif_sample_rate(hdsp)) {
1870         case 32000:
1871                 ucontrol->value.enumerated.item[0] = 0;
1872                 break;
1873         case 44100:
1874                 ucontrol->value.enumerated.item[0] = 1;
1875                 break;
1876         case 48000:
1877                 ucontrol->value.enumerated.item[0] = 2;
1878                 break;
1879         case 64000:
1880                 ucontrol->value.enumerated.item[0] = 3;
1881                 break;
1882         case 88200:
1883                 ucontrol->value.enumerated.item[0] = 4;
1884                 break;
1885         case 96000:
1886                 ucontrol->value.enumerated.item[0] = 5;
1887                 break;
1888         case 128000:
1889                 ucontrol->value.enumerated.item[0] = 7;
1890                 break;
1891         case 176400:
1892                 ucontrol->value.enumerated.item[0] = 8;
1893                 break;
1894         case 192000:
1895                 ucontrol->value.enumerated.item[0] = 9;
1896                 break;
1897         default:
1898                 ucontrol->value.enumerated.item[0] = 6;
1899         }
1900         return 0;
1901 }
1902
1903 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1904 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1905   .name = xname, \
1906   .index = xindex, \
1907   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1908   .info = snd_hdsp_info_system_sample_rate, \
1909   .get = snd_hdsp_get_system_sample_rate \
1910 }
1911
1912 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1913 {
1914         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1915         uinfo->count = 1;
1916         return 0;
1917 }
1918
1919 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1920 {
1921         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1922
1923         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1924         return 0;
1925 }
1926
1927 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1928 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1929   .name = xname, \
1930   .index = xindex, \
1931   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1932   .info = snd_hdsp_info_autosync_sample_rate, \
1933   .get = snd_hdsp_get_autosync_sample_rate \
1934 }
1935
1936 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1937 {
1938         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1939         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1940         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1941         uinfo->count = 1;
1942         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1943         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1944                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1945         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1946         return 0;
1947 }
1948
1949 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1950 {
1951         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1952
1953         switch (hdsp_external_sample_rate(hdsp)) {
1954         case 32000:
1955                 ucontrol->value.enumerated.item[0] = 0;
1956                 break;
1957         case 44100:
1958                 ucontrol->value.enumerated.item[0] = 1;
1959                 break;
1960         case 48000:
1961                 ucontrol->value.enumerated.item[0] = 2;
1962                 break;
1963         case 64000:
1964                 ucontrol->value.enumerated.item[0] = 3;
1965                 break;
1966         case 88200:
1967                 ucontrol->value.enumerated.item[0] = 4;
1968                 break;
1969         case 96000:
1970                 ucontrol->value.enumerated.item[0] = 5;
1971                 break;
1972         case 128000:
1973                 ucontrol->value.enumerated.item[0] = 7;
1974                 break;
1975         case 176400:
1976                 ucontrol->value.enumerated.item[0] = 8;
1977                 break;
1978         case 192000:
1979                 ucontrol->value.enumerated.item[0] = 9;
1980                 break;
1981         default:
1982                 ucontrol->value.enumerated.item[0] = 6;
1983         }
1984         return 0;
1985 }
1986
1987 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1988 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1989   .name = xname, \
1990   .index = xindex, \
1991   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1992   .info = snd_hdsp_info_system_clock_mode, \
1993   .get = snd_hdsp_get_system_clock_mode \
1994 }
1995
1996 static int hdsp_system_clock_mode(hdsp_t *hdsp)
1997 {
1998         if (hdsp->control_register & HDSP_ClockModeMaster) {
1999                 return 0;
2000         } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
2001                         return 0;
2002         }
2003         return 1;
2004 }
2005
2006 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2007 {
2008         static char *texts[] = {"Master", "Slave" };
2009
2010         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2011         uinfo->count = 1;
2012         uinfo->value.enumerated.items = 2;
2013         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2014                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2015         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2016         return 0;
2017 }
2018
2019 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2020 {
2021         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2022
2023         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2024         return 0;
2025 }
2026
2027 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2028 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
2029   .name = xname, \
2030   .index = xindex, \
2031   .info = snd_hdsp_info_clock_source, \
2032   .get = snd_hdsp_get_clock_source, \
2033   .put = snd_hdsp_put_clock_source \
2034 }
2035
2036 static int hdsp_clock_source(hdsp_t *hdsp)
2037 {
2038         if (hdsp->control_register & HDSP_ClockModeMaster) {
2039                 switch (hdsp->system_sample_rate) {
2040                 case 32000:
2041                         return 1;
2042                 case 44100:
2043                         return 2;
2044                 case 48000:
2045                         return 3;
2046                 case 64000:
2047                         return 4;
2048                 case 88200:
2049                         return 5;
2050                 case 96000:
2051                         return 6;
2052                 case 128000:
2053                         return 7;
2054                 case 176400:
2055                         return 8;
2056                 case 192000:
2057                         return 9;
2058                 default:
2059                         return 3;
2060                 }
2061         } else {
2062                 return 0;
2063         }
2064 }
2065
2066 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2067 {
2068         int rate;
2069         switch (mode) {
2070         case HDSP_CLOCK_SOURCE_AUTOSYNC:
2071                 if (hdsp_external_sample_rate(hdsp) != 0) {
2072                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2073                         hdsp->control_register &= ~HDSP_ClockModeMaster;
2074                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2075                         return 0;
2076                     }
2077                 }
2078                 return -1;
2079         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2080                 rate = 32000;
2081                 break;
2082         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2083                 rate = 44100;
2084                 break;
2085         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2086                 rate = 48000;
2087                 break;
2088         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2089                 rate = 64000;
2090                 break;
2091         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2092                 rate = 88200;
2093                 break;
2094         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2095                 rate = 96000;
2096                 break;
2097         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2098                 rate = 128000;
2099                 break;
2100         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2101                 rate = 176400;
2102                 break;
2103         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2104                 rate = 192000;
2105                 break;
2106         default:
2107                 rate = 48000;
2108         }
2109         hdsp->control_register |= HDSP_ClockModeMaster;
2110         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2111         hdsp_set_rate(hdsp, rate, 1);
2112         return 0;
2113 }
2114
2115 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2116 {
2117         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2118         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2119
2120         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2121         uinfo->count = 1;
2122         if (hdsp->io_type == H9632)
2123             uinfo->value.enumerated.items = 10;
2124         else
2125             uinfo->value.enumerated.items = 7;
2126         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2127                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2128         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2129         return 0;
2130 }
2131
2132 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2133 {
2134         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2135
2136         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2137         return 0;
2138 }
2139
2140 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2141 {
2142         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2143         int change;
2144         int val;
2145
2146         if (!snd_hdsp_use_is_exclusive(hdsp))
2147                 return -EBUSY;
2148         val = ucontrol->value.enumerated.item[0];
2149         if (val < 0) val = 0;
2150         if (hdsp->io_type == H9632) {
2151             if (val > 9) val = 9;
2152         } else {
2153             if (val > 6) val = 6;
2154         }
2155         spin_lock_irq(&hdsp->lock);
2156         if (val != hdsp_clock_source(hdsp)) {
2157                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2158         } else {
2159                 change = 0;
2160         }
2161         spin_unlock_irq(&hdsp->lock);
2162         return change;
2163 }
2164
2165 #define HDSP_DA_GAIN(xname, xindex) \
2166 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2167   .name = xname, \
2168   .index = xindex, \
2169   .info = snd_hdsp_info_da_gain, \
2170   .get = snd_hdsp_get_da_gain, \
2171   .put = snd_hdsp_put_da_gain \
2172 }
2173
2174 static int hdsp_da_gain(hdsp_t *hdsp)
2175 {
2176         switch (hdsp->control_register & HDSP_DAGainMask) {
2177         case HDSP_DAGainHighGain:
2178                 return 0;
2179         case HDSP_DAGainPlus4dBu:
2180                 return 1;
2181         case HDSP_DAGainMinus10dBV:
2182                 return 2;
2183         default:
2184                 return 1;
2185         }
2186 }
2187
2188 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2189 {
2190         hdsp->control_register &= ~HDSP_DAGainMask;
2191         switch (mode) {
2192         case 0:
2193                 hdsp->control_register |= HDSP_DAGainHighGain;
2194                 break;
2195         case 1:
2196                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2197                 break;
2198         case 2:
2199                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2200                 break;
2201         default:
2202                 return -1;
2203
2204         }
2205         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2206         return 0;
2207 }
2208
2209 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2210 {
2211         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2212
2213         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2214         uinfo->count = 1;
2215         uinfo->value.enumerated.items = 3;
2216         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2217                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2218         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2219         return 0;
2220 }
2221
2222 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2223 {
2224         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2225
2226         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2227         return 0;
2228 }
2229
2230 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2231 {
2232         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2233         int change;
2234         int val;
2235
2236         if (!snd_hdsp_use_is_exclusive(hdsp))
2237                 return -EBUSY;
2238         val = ucontrol->value.enumerated.item[0];
2239         if (val < 0) val = 0;
2240         if (val > 2) val = 2;
2241         spin_lock_irq(&hdsp->lock);
2242         if (val != hdsp_da_gain(hdsp)) {
2243                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2244         } else {
2245                 change = 0;
2246         }
2247         spin_unlock_irq(&hdsp->lock);
2248         return change;
2249 }
2250
2251 #define HDSP_AD_GAIN(xname, xindex) \
2252 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2253   .name = xname, \
2254   .index = xindex, \
2255   .info = snd_hdsp_info_ad_gain, \
2256   .get = snd_hdsp_get_ad_gain, \
2257   .put = snd_hdsp_put_ad_gain \
2258 }
2259
2260 static int hdsp_ad_gain(hdsp_t *hdsp)
2261 {
2262         switch (hdsp->control_register & HDSP_ADGainMask) {
2263         case HDSP_ADGainMinus10dBV:
2264                 return 0;
2265         case HDSP_ADGainPlus4dBu:
2266                 return 1;
2267         case HDSP_ADGainLowGain:
2268                 return 2;
2269         default:
2270                 return 1;
2271         }
2272 }
2273
2274 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2275 {
2276         hdsp->control_register &= ~HDSP_ADGainMask;
2277         switch (mode) {
2278         case 0:
2279                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2280                 break;
2281         case 1:
2282                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2283                 break;
2284         case 2:
2285                 hdsp->control_register |= HDSP_ADGainLowGain;
2286                 break;
2287         default:
2288                 return -1;
2289
2290         }
2291         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2292         return 0;
2293 }
2294
2295 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2296 {
2297         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2298
2299         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2300         uinfo->count = 1;
2301         uinfo->value.enumerated.items = 3;
2302         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2303                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2304         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2305         return 0;
2306 }
2307
2308 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2309 {
2310         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2311
2312         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2313         return 0;
2314 }
2315
2316 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2317 {
2318         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2319         int change;
2320         int val;
2321
2322         if (!snd_hdsp_use_is_exclusive(hdsp))
2323                 return -EBUSY;
2324         val = ucontrol->value.enumerated.item[0];
2325         if (val < 0) val = 0;
2326         if (val > 2) val = 2;
2327         spin_lock_irq(&hdsp->lock);
2328         if (val != hdsp_ad_gain(hdsp)) {
2329                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2330         } else {
2331                 change = 0;
2332         }
2333         spin_unlock_irq(&hdsp->lock);
2334         return change;
2335 }
2336
2337 #define HDSP_PHONE_GAIN(xname, xindex) \
2338 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2339   .name = xname, \
2340   .index = xindex, \
2341   .info = snd_hdsp_info_phone_gain, \
2342   .get = snd_hdsp_get_phone_gain, \
2343   .put = snd_hdsp_put_phone_gain \
2344 }
2345
2346 static int hdsp_phone_gain(hdsp_t *hdsp)
2347 {
2348         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2349         case HDSP_PhoneGain0dB:
2350                 return 0;
2351         case HDSP_PhoneGainMinus6dB:
2352                 return 1;
2353         case HDSP_PhoneGainMinus12dB:
2354                 return 2;
2355         default:
2356                 return 0;
2357         }
2358 }
2359
2360 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2361 {
2362         hdsp->control_register &= ~HDSP_PhoneGainMask;
2363         switch (mode) {
2364         case 0:
2365                 hdsp->control_register |= HDSP_PhoneGain0dB;
2366                 break;
2367         case 1:
2368                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2369                 break;
2370         case 2:
2371                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2372                 break;
2373         default:
2374                 return -1;
2375
2376         }
2377         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2378         return 0;
2379 }
2380
2381 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2382 {
2383         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2384
2385         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2386         uinfo->count = 1;
2387         uinfo->value.enumerated.items = 3;
2388         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2389                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2390         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2391         return 0;
2392 }
2393
2394 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2395 {
2396         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2397
2398         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2399         return 0;
2400 }
2401
2402 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2403 {
2404         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2405         int change;
2406         int val;
2407
2408         if (!snd_hdsp_use_is_exclusive(hdsp))
2409                 return -EBUSY;
2410         val = ucontrol->value.enumerated.item[0];
2411         if (val < 0) val = 0;
2412         if (val > 2) val = 2;
2413         spin_lock_irq(&hdsp->lock);
2414         if (val != hdsp_phone_gain(hdsp)) {
2415                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2416         } else {
2417                 change = 0;
2418         }
2419         spin_unlock_irq(&hdsp->lock);
2420         return change;
2421 }
2422
2423 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2424 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2425   .name = xname, \
2426   .index = xindex, \
2427   .info = snd_hdsp_info_xlr_breakout_cable, \
2428   .get = snd_hdsp_get_xlr_breakout_cable, \
2429   .put = snd_hdsp_put_xlr_breakout_cable \
2430 }
2431
2432 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2433 {
2434         if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2435                 return 1;
2436         }
2437         return 0;
2438 }
2439
2440 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2441 {
2442         if (mode) {
2443                 hdsp->control_register |= HDSP_XLRBreakoutCable;
2444         } else {
2445                 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2446         }
2447         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2448         return 0;
2449 }
2450
2451 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2452 {
2453         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2454         uinfo->count = 1;
2455         uinfo->value.integer.min = 0;
2456         uinfo->value.integer.max = 1;
2457         return 0;
2458 }
2459
2460 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2461 {
2462         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2463
2464         ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2465         return 0;
2466 }
2467
2468 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2469 {
2470         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2471         int change;
2472         int val;
2473
2474         if (!snd_hdsp_use_is_exclusive(hdsp))
2475                 return -EBUSY;
2476         val = ucontrol->value.integer.value[0] & 1;
2477         spin_lock_irq(&hdsp->lock);
2478         change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2479         hdsp_set_xlr_breakout_cable(hdsp, val);
2480         spin_unlock_irq(&hdsp->lock);
2481         return change;
2482 }
2483
2484 /* (De)activates old RME Analog Extension Board
2485    These are connected to the internal ADAT connector
2486    Switching this on desactivates external ADAT
2487 */
2488 #define HDSP_AEB(xname, xindex) \
2489 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2490   .name = xname, \
2491   .index = xindex, \
2492   .info = snd_hdsp_info_aeb, \
2493   .get = snd_hdsp_get_aeb, \
2494   .put = snd_hdsp_put_aeb \
2495 }
2496
2497 static int hdsp_aeb(hdsp_t *hdsp)
2498 {
2499         if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2500                 return 1;
2501         }
2502         return 0;
2503 }
2504
2505 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2506 {
2507         if (mode) {
2508                 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2509         } else {
2510                 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2511         }
2512         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2513         return 0;
2514 }
2515
2516 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2517 {
2518         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2519         uinfo->count = 1;
2520         uinfo->value.integer.min = 0;
2521         uinfo->value.integer.max = 1;
2522         return 0;
2523 }
2524
2525 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2526 {
2527         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2528
2529         ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2530         return 0;
2531 }
2532
2533 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2534 {
2535         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2536         int change;
2537         int val;
2538
2539         if (!snd_hdsp_use_is_exclusive(hdsp))
2540                 return -EBUSY;
2541         val = ucontrol->value.integer.value[0] & 1;
2542         spin_lock_irq(&hdsp->lock);
2543         change = (int)val != hdsp_aeb(hdsp);
2544         hdsp_set_aeb(hdsp, val);
2545         spin_unlock_irq(&hdsp->lock);
2546         return change;
2547 }
2548
2549 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2550 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2551   .name = xname, \
2552   .index = xindex, \
2553   .info = snd_hdsp_info_pref_sync_ref, \
2554   .get = snd_hdsp_get_pref_sync_ref, \
2555   .put = snd_hdsp_put_pref_sync_ref \
2556 }
2557
2558 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2559 {
2560         /* Notice that this looks at the requested sync source,
2561            not the one actually in use.
2562         */
2563
2564         switch (hdsp->control_register & HDSP_SyncRefMask) {
2565         case HDSP_SyncRef_ADAT1:
2566                 return HDSP_SYNC_FROM_ADAT1;
2567         case HDSP_SyncRef_ADAT2:
2568                 return HDSP_SYNC_FROM_ADAT2;
2569         case HDSP_SyncRef_ADAT3:
2570                 return HDSP_SYNC_FROM_ADAT3;
2571         case HDSP_SyncRef_SPDIF:
2572                 return HDSP_SYNC_FROM_SPDIF;
2573         case HDSP_SyncRef_WORD:
2574                 return HDSP_SYNC_FROM_WORD;
2575         case HDSP_SyncRef_ADAT_SYNC:
2576                 return HDSP_SYNC_FROM_ADAT_SYNC;
2577         default:
2578                 return HDSP_SYNC_FROM_WORD;
2579         }
2580         return 0;
2581 }
2582
2583 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2584 {
2585         hdsp->control_register &= ~HDSP_SyncRefMask;
2586         switch (pref) {
2587         case HDSP_SYNC_FROM_ADAT1:
2588                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2589                 break;
2590         case HDSP_SYNC_FROM_ADAT2:
2591                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2592                 break;
2593         case HDSP_SYNC_FROM_ADAT3:
2594                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2595                 break;
2596         case HDSP_SYNC_FROM_SPDIF:
2597                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2598                 break;
2599         case HDSP_SYNC_FROM_WORD:
2600                 hdsp->control_register |= HDSP_SyncRef_WORD;
2601                 break;
2602         case HDSP_SYNC_FROM_ADAT_SYNC:
2603                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2604                 break;
2605         default:
2606                 return -1;
2607         }
2608         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2609         return 0;
2610 }
2611
2612 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2613 {
2614         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2615         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2616
2617         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2618         uinfo->count = 1;
2619
2620         switch (hdsp->io_type) {
2621         case Digiface:
2622         case H9652:
2623                 uinfo->value.enumerated.items = 6;
2624                 break;
2625         case Multiface:
2626                 uinfo->value.enumerated.items = 4;
2627                 break;
2628         case H9632:
2629                 uinfo->value.enumerated.items = 3;
2630                 break;
2631         default:
2632                 uinfo->value.enumerated.items = 0;
2633                 break;
2634         }
2635
2636         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2637                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2638         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2639         return 0;
2640 }
2641
2642 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2643 {
2644         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2645
2646         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2647         return 0;
2648 }
2649
2650 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2651 {
2652         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2653         int change, max;
2654         unsigned int val;
2655
2656         if (!snd_hdsp_use_is_exclusive(hdsp))
2657                 return -EBUSY;
2658
2659         switch (hdsp->io_type) {
2660         case Digiface:
2661         case H9652:
2662                 max = 6;
2663                 break;
2664         case Multiface:
2665                 max = 4;
2666                 break;
2667         case H9632:
2668                 max = 3;
2669                 break;
2670         default:
2671                 return -EIO;
2672         }
2673
2674         val = ucontrol->value.enumerated.item[0] % max;
2675         spin_lock_irq(&hdsp->lock);
2676         change = (int)val != hdsp_pref_sync_ref(hdsp);
2677         hdsp_set_pref_sync_ref(hdsp, val);
2678         spin_unlock_irq(&hdsp->lock);
2679         return change;
2680 }
2681
2682 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2683 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2684   .name = xname, \
2685   .index = xindex, \
2686   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2687   .info = snd_hdsp_info_autosync_ref, \
2688   .get = snd_hdsp_get_autosync_ref, \
2689 }
2690
2691 static int hdsp_autosync_ref(hdsp_t *hdsp)
2692 {
2693         /* This looks at the autosync selected sync reference */
2694         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2695
2696         switch (status2 & HDSP_SelSyncRefMask) {
2697         case HDSP_SelSyncRef_WORD:
2698                 return HDSP_AUTOSYNC_FROM_WORD;
2699         case HDSP_SelSyncRef_ADAT_SYNC:
2700                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2701         case HDSP_SelSyncRef_SPDIF:
2702                 return HDSP_AUTOSYNC_FROM_SPDIF;
2703         case HDSP_SelSyncRefMask:
2704                 return HDSP_AUTOSYNC_FROM_NONE;
2705         case HDSP_SelSyncRef_ADAT1:
2706                 return HDSP_AUTOSYNC_FROM_ADAT1;
2707         case HDSP_SelSyncRef_ADAT2:
2708                 return HDSP_AUTOSYNC_FROM_ADAT2;
2709         case HDSP_SelSyncRef_ADAT3:
2710                 return HDSP_AUTOSYNC_FROM_ADAT3;
2711         default:
2712                 return HDSP_AUTOSYNC_FROM_WORD;
2713         }
2714         return 0;
2715 }
2716
2717 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2718 {
2719         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2720
2721         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2722         uinfo->count = 1;
2723         uinfo->value.enumerated.items = 7;
2724         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2725                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2726         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2727         return 0;
2728 }
2729
2730 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2731 {
2732         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2733
2734         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2735         return 0;
2736 }
2737
2738 #define HDSP_PASSTHRU(xname, xindex) \
2739 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2740   .name = xname, \
2741   .index = xindex, \
2742   .info = snd_hdsp_info_passthru, \
2743   .put = snd_hdsp_put_passthru, \
2744   .get = snd_hdsp_get_passthru \
2745 }
2746
2747 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
2748 {
2749         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2750         uinfo->count = 1;
2751         uinfo->value.integer.min = 0;
2752         uinfo->value.integer.max = 1;
2753         return 0;
2754 }
2755
2756 static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2757 {
2758         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2759
2760         spin_lock_irq(&hdsp->lock);
2761         ucontrol->value.integer.value[0] = hdsp->passthru;
2762         spin_unlock_irq(&hdsp->lock);
2763         return 0;
2764 }
2765
2766 static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2767 {
2768         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2769         int change;
2770         unsigned int val;
2771         int err = 0;
2772
2773         if (!snd_hdsp_use_is_exclusive(hdsp))
2774                 return -EBUSY;
2775
2776         val = ucontrol->value.integer.value[0] & 1;
2777         spin_lock_irq(&hdsp->lock);
2778         change = (ucontrol->value.integer.value[0] != hdsp->passthru);
2779         if (change)
2780                 err = hdsp_set_passthru(hdsp, val);
2781         spin_unlock_irq(&hdsp->lock);
2782         return err ? err : change;
2783 }
2784
2785 #define HDSP_LINE_OUT(xname, xindex) \
2786 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2787   .name = xname, \
2788   .index = xindex, \
2789   .info = snd_hdsp_info_line_out, \
2790   .get = snd_hdsp_get_line_out, \
2791   .put = snd_hdsp_put_line_out \
2792 }
2793
2794 static int hdsp_line_out(hdsp_t *hdsp)
2795 {
2796         return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2797 }
2798
2799 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2800 {
2801         if (out) {
2802                 hdsp->control_register |= HDSP_LineOut;
2803         } else {
2804                 hdsp->control_register &= ~HDSP_LineOut;
2805         }
2806         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2807         return 0;
2808 }
2809
2810 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2811 {
2812         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2813         uinfo->count = 1;
2814         uinfo->value.integer.min = 0;
2815         uinfo->value.integer.max = 1;
2816         return 0;
2817 }
2818
2819 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2820 {
2821         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2822
2823         spin_lock_irq(&hdsp->lock);
2824         ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2825         spin_unlock_irq(&hdsp->lock);
2826         return 0;
2827 }
2828
2829 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2830 {
2831         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2832         int change;
2833         unsigned int val;
2834
2835         if (!snd_hdsp_use_is_exclusive(hdsp))
2836                 return -EBUSY;
2837         val = ucontrol->value.integer.value[0] & 1;
2838         spin_lock_irq(&hdsp->lock);
2839         change = (int)val != hdsp_line_out(hdsp);
2840         hdsp_set_line_output(hdsp, val);
2841         spin_unlock_irq(&hdsp->lock);
2842         return change;
2843 }
2844
2845 #define HDSP_MIXER(xname, xindex) \
2846 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2847   .name = xname, \
2848   .index = xindex, \
2849   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2850                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2851   .info = snd_hdsp_info_mixer, \
2852   .get = snd_hdsp_get_mixer, \
2853   .put = snd_hdsp_put_mixer \
2854 }
2855
2856 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2857 {
2858         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2859         uinfo->count = 3;
2860         uinfo->value.integer.min = 0;
2861         uinfo->value.integer.max = 65536;
2862         uinfo->value.integer.step = 1;
2863         return 0;
2864 }
2865
2866 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2867 {
2868         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2869         int source;
2870         int destination;
2871         int addr;
2872
2873         source = ucontrol->value.integer.value[0];
2874         destination = ucontrol->value.integer.value[1];
2875
2876         if (source >= hdsp->max_channels) {
2877                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2878         } else {
2879                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2880         }
2881
2882         spin_lock_irq(&hdsp->lock);
2883         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2884         spin_unlock_irq(&hdsp->lock);
2885         return 0;
2886 }
2887
2888 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2889 {
2890         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2891         int change;
2892         int source;
2893         int destination;
2894         int gain;
2895         int addr;
2896
2897         if (!snd_hdsp_use_is_exclusive(hdsp))
2898                 return -EBUSY;
2899
2900         source = ucontrol->value.integer.value[0];
2901         destination = ucontrol->value.integer.value[1];
2902
2903         if (source >= hdsp->max_channels) {
2904                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2905         } else {
2906                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2907         }
2908
2909         gain = ucontrol->value.integer.value[2];
2910
2911         spin_lock_irq(&hdsp->lock);
2912         change = gain != hdsp_read_gain(hdsp, addr);
2913         if (change)
2914                 hdsp_write_gain(hdsp, addr, gain);
2915         spin_unlock_irq(&hdsp->lock);
2916         return change;
2917 }
2918
2919 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2920 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2921   .name = xname, \
2922   .index = xindex, \
2923   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2924   .info = snd_hdsp_info_sync_check, \
2925   .get = snd_hdsp_get_wc_sync_check \
2926 }
2927
2928 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2929 {
2930         static char *texts[] = {"No Lock", "Lock", "Sync" };
2931         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2932         uinfo->count = 1;
2933         uinfo->value.enumerated.items = 3;
2934         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2935                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2936         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2937         return 0;
2938 }
2939
2940 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2941 {
2942         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2943         if (status2 & HDSP_wc_lock) {
2944                 if (status2 & HDSP_wc_sync) {
2945                         return 2;
2946                 } else {
2947                          return 1;
2948                 }
2949         } else {
2950                 return 0;
2951         }
2952         return 0;
2953 }
2954
2955 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2956 {
2957         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2958
2959         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2960         return 0;
2961 }
2962
2963 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2964 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2965   .name = xname, \
2966   .index = xindex, \
2967   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2968   .info = snd_hdsp_info_sync_check, \
2969   .get = snd_hdsp_get_spdif_sync_check \
2970 }
2971
2972 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2973 {
2974         int status = hdsp_read(hdsp, HDSP_statusRegister);
2975         if (status & HDSP_SPDIFErrorFlag) {
2976                 return 0;
2977         } else {
2978                 if (status & HDSP_SPDIFSync) {
2979                         return 2;
2980                 } else {
2981                         return 1;
2982                 }
2983         }
2984         return 0;
2985 }
2986
2987 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2988 {
2989         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2990
2991         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2992         return 0;
2993 }
2994
2995 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2996 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2997   .name = xname, \
2998   .index = xindex, \
2999   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3000   .info = snd_hdsp_info_sync_check, \
3001   .get = snd_hdsp_get_adatsync_sync_check \
3002 }
3003
3004 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3005 {
3006         int status = hdsp_read(hdsp, HDSP_statusRegister);
3007         if (status & HDSP_TimecodeLock) {
3008                 if (status & HDSP_TimecodeSync) {
3009                         return 2;
3010                 } else {
3011                         return 1;
3012                 }
3013         } else {
3014                 return 0;
3015         }
3016 }
3017
3018 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3019 {
3020         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3021
3022         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3023         return 0;
3024 }
3025
3026 #define HDSP_ADAT_SYNC_CHECK \
3027 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3028   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3029   .info = snd_hdsp_info_sync_check, \
3030   .get = snd_hdsp_get_adat_sync_check \
3031 }
3032
3033 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3034 {
3035         int status = hdsp_read(hdsp, HDSP_statusRegister);
3036
3037         if (status & (HDSP_Lock0>>idx)) {
3038                 if (status & (HDSP_Sync0>>idx)) {
3039                         return 2;
3040                 } else {
3041                         return 1;
3042                 }
3043         } else {
3044                 return 0;
3045         }
3046 }
3047
3048 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3049 {
3050         int offset;
3051         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3052
3053         offset = ucontrol->id.index - 1;
3054         snd_assert(offset >= 0);
3055
3056         switch (hdsp->io_type) {
3057         case Digiface:
3058         case H9652:
3059                 if (offset >= 3)
3060                         return -EINVAL;
3061                 break;
3062         case Multiface:
3063         case H9632:
3064                 if (offset >= 1)
3065                         return -EINVAL;
3066                 break;
3067         default:
3068                 return -EIO;
3069         }
3070
3071         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3072         return 0;
3073 }
3074
3075 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3076 HDSP_DA_GAIN("DA Gain", 0),
3077 HDSP_AD_GAIN("AD Gain", 0),
3078 HDSP_PHONE_GAIN("Phones Gain", 0),
3079 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3080 };
3081
3082 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3083 {
3084         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3085         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3086         .info =         snd_hdsp_control_spdif_info,
3087         .get =          snd_hdsp_control_spdif_get,
3088         .put =          snd_hdsp_control_spdif_put,
3089 },
3090 {
3091         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3092         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3093         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3094         .info =         snd_hdsp_control_spdif_stream_info,
3095         .get =          snd_hdsp_control_spdif_stream_get,
3096         .put =          snd_hdsp_control_spdif_stream_put,
3097 },
3098 {
3099         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3100         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3101         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3102         .info =         snd_hdsp_control_spdif_mask_info,
3103         .get =          snd_hdsp_control_spdif_mask_get,
3104         .private_value = IEC958_AES0_NONAUDIO |
3105                          IEC958_AES0_PROFESSIONAL |
3106                          IEC958_AES0_CON_EMPHASIS,
3107 },
3108 {
3109         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3110         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3111         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3112         .info =         snd_hdsp_control_spdif_mask_info,
3113         .get =          snd_hdsp_control_spdif_mask_get,
3114         .private_value = IEC958_AES0_NONAUDIO |
3115                          IEC958_AES0_PROFESSIONAL |
3116                          IEC958_AES0_PRO_EMPHASIS,
3117 },
3118 HDSP_MIXER("Mixer", 0),
3119 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3120 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3121 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3122 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3123 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3124 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3125 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3126 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3127 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3128 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3129 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3130 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3131 /* 'External Rate' complies with the alsa control naming scheme */
3132 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3133 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3134 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3135 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3136 HDSP_PASSTHRU("Passthru", 0),
3137 HDSP_LINE_OUT("Line Out", 0),
3138 };
3139
3140 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3141 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3142
3143 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3144 {
3145         unsigned int idx;
3146         int err;
3147         snd_kcontrol_t *kctl;
3148
3149         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3150                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3151                         return err;
3152                 }
3153                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3154                         hdsp->spdif_ctl = kctl;
3155         }
3156
3157         /* ADAT SyncCheck status */
3158         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3159         snd_hdsp_adat_sync_check.index = 1;
3160         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3161                 return err;
3162         }
3163         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3164                 for (idx = 1; idx < 3; ++idx) {
3165                         snd_hdsp_adat_sync_check.index = idx+1;
3166                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3167                                 return err;
3168                         }
3169                 }
3170         }
3171
3172         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3173         if (hdsp->io_type == H9632) {
3174                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3175                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3176                                 return err;
3177                         }
3178                 }
3179         }
3180
3181         /* AEB control for H96xx card */
3182         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3183                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3184                                 return err;
3185                 }
3186         }
3187
3188         return 0;
3189 }
3190
3191 /*------------------------------------------------------------
3192    /proc interface
3193  ------------------------------------------------------------*/
3194
3195 static void
3196 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3197 {
3198         hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3199         unsigned int status;
3200         unsigned int status2;
3201         char *pref_sync_ref;
3202         char *autosync_ref;
3203         char *system_clock_mode;
3204         char *clock_source;
3205         int x;
3206
3207         if (hdsp_check_for_iobox (hdsp)) {
3208                 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3209                 return;
3210         }
3211
3212         if (hdsp_check_for_firmware(hdsp)) {
3213                 if (hdsp->state & HDSP_FirmwareCached) {
3214                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3215                                 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3216                                 return;
3217                         }
3218                 } else {
3219                         snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3220                         return;
3221                 }
3222         }
3223
3224         status = hdsp_read(hdsp, HDSP_statusRegister);
3225         status2 = hdsp_read(hdsp, HDSP_status2Register);
3226
3227         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3228         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3229                     hdsp->capture_buffer, hdsp->playback_buffer);
3230         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3231                     hdsp->irq, hdsp->port, hdsp->iobase);
3232         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3233         snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3234         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3235         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3236         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3237
3238         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3239         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3240         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3241         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3242
3243         snd_iprintf(buffer, "\n");
3244
3245         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3246
3247         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3248         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3249         snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
3250         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3251
3252         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3253
3254         snd_iprintf(buffer, "\n");
3255
3256
3257         switch (hdsp_clock_source(hdsp)) {
3258         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3259                 clock_source = "AutoSync";
3260                 break;
3261         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3262                 clock_source = "Internal 32 kHz";
3263                 break;
3264         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3265                 clock_source = "Internal 44.1 kHz";
3266                 break;
3267         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3268                 clock_source = "Internal 48 kHz";
3269                 break;
3270         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3271                 clock_source = "Internal 64 kHz";
3272                 break;
3273         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3274                 clock_source = "Internal 88.2 kHz";
3275                 break;
3276         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3277                 clock_source = "Internal 96 kHz";
3278                 break;
3279         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3280                 clock_source = "Internal 128 kHz";
3281                 break;
3282         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3283                 clock_source = "Internal 176.4 kHz";
3284                 break;
3285                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3286                 clock_source = "Internal 192 kHz";
3287                 break;
3288         default:
3289                 clock_source = "Error";
3290         }
3291         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3292
3293         if (hdsp_system_clock_mode(hdsp)) {
3294                 system_clock_mode = "Slave";
3295         } else {
3296                 system_clock_mode = "Master";
3297         }
3298
3299         switch (hdsp_pref_sync_ref (hdsp)) {
3300         case HDSP_SYNC_FROM_WORD:
3301                 pref_sync_ref = "Word Clock";
3302                 break;
3303         case HDSP_SYNC_FROM_ADAT_SYNC:
3304                 pref_sync_ref = "ADAT Sync";
3305                 break;
3306         case HDSP_SYNC_FROM_SPDIF:
3307                 pref_sync_ref = "SPDIF";
3308                 break;
3309         case HDSP_SYNC_FROM_ADAT1:
3310                 pref_sync_ref = "ADAT1";
3311                 break;
3312         case HDSP_SYNC_FROM_ADAT2:
3313                 pref_sync_ref = "ADAT2";
3314                 break;
3315         case HDSP_SYNC_FROM_ADAT3:
3316                 pref_sync_ref = "ADAT3";
3317                 break;
3318         default:
3319                 pref_sync_ref = "Word Clock";
3320                 break;
3321         }
3322         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3323
3324         switch (hdsp_autosync_ref (hdsp)) {
3325         case HDSP_AUTOSYNC_FROM_WORD:
3326                 autosync_ref = "Word Clock";
3327                 break;
3328         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3329                 autosync_ref = "ADAT Sync";
3330                 break;
3331         case HDSP_AUTOSYNC_FROM_SPDIF:
3332                 autosync_ref = "SPDIF";
3333                 break;
3334         case HDSP_AUTOSYNC_FROM_NONE:
3335                 autosync_ref = "None";
3336                 break;
3337         case HDSP_AUTOSYNC_FROM_ADAT1:
3338                 autosync_ref = "ADAT1";
3339                 break;
3340         case HDSP_AUTOSYNC_FROM_ADAT2:
3341                 autosync_ref = "ADAT2";
3342                 break;
3343         case HDSP_AUTOSYNC_FROM_ADAT3:
3344                 autosync_ref = "ADAT3";
3345                 break;
3346         default:
3347                 autosync_ref = "---";
3348                 break;
3349         }
3350         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3351
3352         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3353
3354         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3355
3356         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3357
3358         snd_iprintf(buffer, "\n");
3359
3360         switch (hdsp_spdif_in(hdsp)) {
3361         case HDSP_SPDIFIN_OPTICAL:
3362                 snd_iprintf(buffer, "IEC958 input: Optical\n");
3363                 break;
3364         case HDSP_SPDIFIN_COAXIAL:
3365                 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3366                 break;
3367         case HDSP_SPDIFIN_INTERNAL:
3368                 snd_iprintf(buffer, "IEC958 input: Internal\n");
3369                 break;
3370         case HDSP_SPDIFIN_AES:
3371                 snd_iprintf(buffer, "IEC958 input: AES\n");
3372                 break;
3373         default:
3374                 snd_iprintf(buffer, "IEC958 input: ???\n");
3375                 break;
3376         }
3377
3378         if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3379                 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3380         } else {
3381                 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3382         }
3383
3384         if (hdsp->control_register & HDSP_SPDIFProfessional) {
3385                 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3386         } else {
3387                 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3388         }
3389
3390         if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3391                 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3392         } else {
3393                 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3394         }
3395
3396         if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3397                 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3398         } else {
3399                 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3400         }
3401         if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3402                 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3403         } else {
3404                 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3405         }
3406
3407         snd_iprintf(buffer, "\n");
3408
3409         /* Sync Check */
3410         x = status & HDSP_Sync0;
3411         if (status & HDSP_Lock0) {
3412                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3413         } else {
3414                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3415         }
3416
3417         switch (hdsp->io_type) {
3418         case Digiface:
3419         case H9652:
3420                 x = status & HDSP_Sync1;
3421                 if (status & HDSP_Lock1) {
3422                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3423                 } else {
3424                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3425                 }
3426                 x = status & HDSP_Sync2;
3427                 if (status & HDSP_Lock2) {
3428                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3429                 } else {
3430                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3431                 }
3432         default:
3433                 /* relax */
3434                 break;
3435         }
3436
3437         x = status & HDSP_SPDIFSync;
3438         if (status & HDSP_SPDIFErrorFlag) {
3439                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3440         } else {
3441                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3442         }
3443
3444         x = status2 & HDSP_wc_sync;
3445         if (status2 & HDSP_wc_lock) {
3446                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3447         } else {
3448                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3449         }
3450
3451         x = status & HDSP_TimecodeSync;
3452         if (status & HDSP_TimecodeLock) {
3453                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3454         } else {
3455                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3456         }
3457
3458         snd_iprintf(buffer, "\n");
3459
3460         /* Informations about H9632 specific controls */
3461         if (hdsp->io_type == H9632) {
3462                 char *tmp;
3463
3464                 switch (hdsp_ad_gain(hdsp)) {
3465                 case 0:
3466                         tmp = "-10 dBV";
3467                         break;
3468                 case 1:
3469                         tmp = "+4 dBu";
3470                         break;
3471                 default:
3472                         tmp = "Lo Gain";
3473                         break;
3474                 }
3475                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3476
3477                 switch (hdsp_da_gain(hdsp)) {
3478                 case 0:
3479                         tmp = "Hi Gain";
3480                         break;
3481                 case 1:
3482                         tmp = "+4 dBu";
3483                         break;
3484                 default:
3485                         tmp = "-10 dBV";
3486                         break;
3487                 }
3488                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3489
3490                 switch (hdsp_phone_gain(hdsp)) {
3491                 case 0:
3492                         tmp = "0 dB";
3493                         break;
3494                 case 1:
3495                         tmp = "-6 dB";
3496                         break;
3497                 default:
3498                         tmp = "-12 dB";
3499                         break;
3500                 }
3501                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3502
3503                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3504
3505                 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3506                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3507                 } else {
3508                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3509                 }
3510                 snd_iprintf(buffer, "\n");
3511         }
3512
3513 }
3514
3515 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3516 {
3517         snd_info_entry_t *entry;
3518
3519         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3520                 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3521 }
3522
3523 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3524 {
3525         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3526         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3527 }
3528
3529 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3530 {
3531         unsigned long pb_bus, cb_bus;
3532
3533         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3534             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3535                 if (hdsp->capture_dma_buf.area)
3536                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3537                 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3538                 return -ENOMEM;
3539         }
3540
3541         /* Align to bus-space 64K boundary */
3542
3543         cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3544         pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3545
3546         /* Tell the card where it is */
3547
3548         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3549         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3550
3551         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3552         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3553
3554         return 0;
3555 }
3556
3557 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3558 {
3559         unsigned int i;
3560
3561         /* ASSUMPTION: hdsp->lock is either held, or
3562            there is no need to hold it (e.g. during module
3563            initalization).
3564          */
3565
3566         /* set defaults:
3567
3568            SPDIF Input via Coax
3569            Master clock mode
3570            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3571                             which implies 2 4096 sample, 32Kbyte periods).
3572            Enable line out.
3573          */
3574
3575         hdsp->control_register = HDSP_ClockModeMaster |
3576                                  HDSP_SPDIFInputCoaxial |
3577                                  hdsp_encode_latency(7) |
3578                                  HDSP_LineOut;
3579
3580
3581         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3582
3583 #ifdef SNDRV_BIG_ENDIAN
3584         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3585 #else
3586         hdsp->control2_register = 0;
3587 #endif
3588         if (hdsp->io_type == H9652) {
3589                 snd_hdsp_9652_enable_mixer (hdsp);
3590         } else {
3591             hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3592         }
3593
3594         hdsp_reset_hw_pointer(hdsp);
3595         hdsp_compute_period_size(hdsp);
3596
3597         /* silence everything */
3598
3599         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3600                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3601         }
3602
3603         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3604                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3605                         return -EIO;
3606                 }
3607         }
3608
3609         if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) {
3610
3611                 int lineouts_base;
3612
3613                 snd_printk ("sending all inputs and playback streams to line outs.\n");
3614
3615                 /* route all inputs to the line outs for easy monitoring. send
3616                    odd numbered channels to right, even to left.
3617                 */
3618                 if (hdsp->io_type == H9632) {
3619                         /* this is the phones/analog output */
3620                         lineouts_base = 10;
3621                 } else {
3622                         lineouts_base = 26;
3623                 }
3624
3625                 for (i = 0; i < hdsp->max_channels; i++) {
3626                         if (i & 1) {
3627                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) ||
3628                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) {
3629                                     return -EIO;
3630                                 }
3631                         } else {
3632                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) ||
3633                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) {
3634
3635                                     return -EIO;
3636                                 }
3637                         }
3638                 }
3639         }
3640
3641         hdsp->passthru = 0;
3642
3643         /* H9632 specific defaults */
3644         if (hdsp->io_type == H9632) {
3645                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3646                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3647         }
3648
3649         /* set a default rate so that the channel map is set up.
3650          */
3651
3652         hdsp_set_rate(hdsp, 48000, 1);
3653
3654         return 0;
3655 }
3656
3657 void hdsp_midi_tasklet(unsigned long arg)
3658 {
3659         hdsp_t *hdsp = (hdsp_t *)arg;
3660
3661         if (hdsp->midi[0].pending) {
3662                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3663         }
3664         if (hdsp->midi[1].pending) {
3665                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3666         }
3667 }
3668
3669 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3670 {
3671         hdsp_t *hdsp = (hdsp_t *) dev_id;
3672         unsigned int status;
3673         int audio;
3674         int midi0;
3675         int midi1;
3676         unsigned int midi0status;
3677         unsigned int midi1status;
3678         int schedule = 0;
3679
3680         status = hdsp_read(hdsp, HDSP_statusRegister);
3681
3682         audio = status & HDSP_audioIRQPending;
3683         midi0 = status & HDSP_midi0IRQPending;
3684         midi1 = status & HDSP_midi1IRQPending;
3685
3686         if (!audio && !midi0 && !midi1) {
3687                 return IRQ_NONE;
3688         }
3689
3690         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3691
3692         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3693         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3694
3695         if (audio) {
3696                 if (hdsp->capture_substream) {
3697                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3698                 }
3699
3700                 if (hdsp->playback_substream) {
3701                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3702                 }
3703         }
3704
3705         if (midi0 && midi0status) {
3706                 /* we disable interrupts for this input until processing is done */
3707                 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3708                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3709                 hdsp->midi[0].pending = 1;
3710                 schedule = 1;
3711         }
3712         if (midi1 && midi1status) {
3713                 /* we disable interrupts for this input until processing is done */
3714                 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3715                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3716                 hdsp->midi[1].pending = 1;
3717                 schedule = 1;
3718         }
3719         if (schedule)
3720             tasklet_hi_schedule(&hdsp->midi_tasklet);
3721         return IRQ_HANDLED;
3722 }
3723
3724 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3725 {
3726         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3727         return hdsp_hw_pointer(hdsp);
3728 }
3729
3730 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3731                                              int stream,
3732                                              int channel)
3733
3734 {
3735         int mapped_channel;
3736
3737         snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3738
3739         if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3740                 return NULL;
3741         }
3742
3743         if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3744                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3745         } else {
3746                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3747         }
3748 }
3749
3750 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3751                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3752 {
3753         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3754         char *channel_buf;
3755
3756         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3757
3758         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3759         snd_assert(channel_buf != NULL, return -EIO);
3760         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3761                 return -EFAULT;
3762         return count;
3763 }
3764
3765 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3766                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3767 {
3768         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3769         char *channel_buf;
3770
3771         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3772
3773         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3774         snd_assert(channel_buf != NULL, return -EIO);
3775         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3776                 return -EFAULT;
3777         return count;
3778 }
3779
3780 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3781                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3782 {
3783         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3784         char *channel_buf;
3785
3786         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3787         snd_assert(channel_buf != NULL, return -EIO);
3788         memset(channel_buf + pos * 4, 0, count * 4);
3789         return count;
3790 }
3791
3792 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3793 {
3794         snd_pcm_runtime_t *runtime = substream->runtime;
3795         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3796         snd_pcm_substream_t *other;
3797         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3798                 other = hdsp->capture_substream;
3799         else
3800                 other = hdsp->playback_substream;
3801         if (hdsp->running)
3802                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3803         else
3804                 runtime->status->hw_ptr = 0;
3805         if (other) {
3806                 struct list_head *pos;
3807                 snd_pcm_substream_t *s;
3808                 snd_pcm_runtime_t *oruntime = other->runtime;
3809                 snd_pcm_group_for_each(pos, substream) {
3810                         s = snd_pcm_group_substream_entry(pos);
3811                         if (s == other) {
3812                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3813                                 break;
3814                         }
3815                 }
3816         }
3817         return 0;
3818 }
3819
3820 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3821                                  snd_pcm_hw_params_t *params)
3822 {
3823         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3824         int err;
3825         pid_t this_pid;
3826         pid_t other_pid;
3827
3828         if (hdsp_check_for_iobox (hdsp)) {
3829                 return -EIO;
3830         }
3831
3832         if (hdsp_check_for_firmware(hdsp)) {
3833                 if (hdsp->state & HDSP_FirmwareCached) {
3834                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3835                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3836                         }
3837                 } else {
3838                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3839                 }
3840                 return -EIO;
3841         }
3842
3843         spin_lock_irq(&hdsp->lock);
3844
3845         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3846                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3847                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3848                 this_pid = hdsp->playback_pid;
3849                 other_pid = hdsp->capture_pid;
3850         } else {
3851                 this_pid = hdsp->capture_pid;
3852                 other_pid = hdsp->playback_pid;
3853         }
3854
3855         if ((other_pid > 0) && (this_pid != other_pid)) {
3856
3857                 /* The other stream is open, and not by the same
3858                    task as this one. Make sure that the parameters
3859                    that matter are the same.
3860                  */
3861
3862                 if (params_rate(params) != hdsp->system_sample_rate) {
3863                         spin_unlock_irq(&hdsp->lock);
3864                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3865                         return -EBUSY;
3866                 }
3867
3868                 if (params_period_size(params) != hdsp->period_bytes / 4) {
3869                         spin_unlock_irq(&hdsp->lock);
3870                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3871                         return -EBUSY;
3872                 }
3873
3874                 /* We're fine. */
3875
3876                 spin_unlock_irq(&hdsp->lock);
3877                 return 0;
3878
3879         } else {
3880                 spin_unlock_irq(&hdsp->lock);
3881         }
3882
3883         /* how to make sure that the rate matches an externally-set one ?
3884          */
3885
3886         spin_lock_irq(&hdsp->lock);
3887         if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3888                 spin_unlock_irq(&hdsp->lock);
3889                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3890                 return err;
3891         } else {
3892                 spin_unlock_irq(&hdsp->lock);
3893         }
3894
3895         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3896                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3897                 return err;
3898         }
3899
3900         return 0;
3901 }
3902
3903 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3904                                     snd_pcm_channel_info_t *info)
3905 {
3906         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3907         int mapped_channel;
3908
3909         snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3910
3911         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3912                 return -EINVAL;
3913         }
3914
3915         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3916         info->first = 0;
3917         info->step = 32;
3918         return 0;
3919 }
3920
3921 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3922                              unsigned int cmd, void *arg)
3923 {
3924         switch (cmd) {
3925         case SNDRV_PCM_IOCTL1_RESET:
3926         {
3927                 return snd_hdsp_reset(substream);
3928         }
3929         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3930         {
3931                 snd_pcm_channel_info_t *info = arg;
3932                 return snd_hdsp_channel_info(substream, info);
3933         }
3934         default:
3935                 break;
3936         }
3937
3938         return snd_pcm_lib_ioctl(substream, cmd, arg);
3939 }
3940
3941 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3942 {
3943         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3944         snd_pcm_substream_t *other;
3945         int running;
3946
3947         if (hdsp_check_for_iobox (hdsp)) {
3948                 return -EIO;
3949         }
3950
3951         if (hdsp_check_for_firmware(hdsp)) {
3952                 if (hdsp->state & HDSP_FirmwareCached) {
3953                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3954                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3955                         }
3956                 } else {
3957                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3958                 }
3959                 return -EIO;
3960         }
3961
3962         spin_lock(&hdsp->lock);
3963         running = hdsp->running;
3964         switch (cmd) {
3965         case SNDRV_PCM_TRIGGER_START:
3966                 running |= 1 << substream->stream;
3967                 break;
3968         case SNDRV_PCM_TRIGGER_STOP:
3969                 running &= ~(1 << substream->stream);
3970                 break;
3971         default:
3972                 snd_BUG();
3973                 spin_unlock(&hdsp->lock);
3974                 return -EINVAL;
3975         }
3976         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3977                 other = hdsp->capture_substream;
3978         else
3979                 other = hdsp->playback_substream;
3980
3981         if (other) {
3982                 struct list_head *pos;
3983                 snd_pcm_substream_t *s;
3984                 snd_pcm_group_for_each(pos, substream) {
3985                         s = snd_pcm_group_substream_entry(pos);
3986                         if (s == other) {
3987                                 snd_pcm_trigger_done(s, substream);
3988                                 if (cmd == SNDRV_PCM_TRIGGER_START)
3989                                         running |= 1 << s->stream;
3990                                 else
3991                                         running &= ~(1 << s->stream);
3992                                 goto _ok;
3993                         }
3994                 }
3995                 if (cmd == SNDRV_PCM_TRIGGER_START) {
3996                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3997                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3998                                 hdsp_silence_playback(hdsp);
3999                 } else {
4000                         if (running &&
4001                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4002                                 hdsp_silence_playback(hdsp);
4003                 }
4004         } else {
4005                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4006                                 hdsp_silence_playback(hdsp);
4007         }
4008  _ok:
4009         snd_pcm_trigger_done(substream, substream);
4010         if (!hdsp->running && running)
4011                 hdsp_start_audio(hdsp);
4012         else if (hdsp->running && !running)
4013                 hdsp_stop_audio(hdsp);
4014         hdsp->running = running;
4015         spin_unlock(&hdsp->lock);
4016
4017         return 0;
4018 }
4019
4020 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4021 {
4022         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4023         int result = 0;
4024
4025         if (hdsp_check_for_iobox (hdsp)) {
4026                 return -EIO;
4027         }
4028
4029         if (hdsp_check_for_firmware(hdsp)) {
4030                 if (hdsp->state & HDSP_FirmwareCached) {
4031                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4032                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4033                         }
4034                 } else {
4035                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4036                 }
4037                 return -EIO;
4038         }
4039
4040         spin_lock_irq(&hdsp->lock);
4041         if (!hdsp->running)
4042                 hdsp_reset_hw_pointer(hdsp);
4043         spin_unlock_irq(&hdsp->lock);
4044         return result;
4045 }
4046
4047 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4048 {
4049         .info =                 (SNDRV_PCM_INFO_MMAP |
4050                                  SNDRV_PCM_INFO_MMAP_VALID |
4051                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4052                                  SNDRV_PCM_INFO_SYNC_START |
4053                                  SNDRV_PCM_INFO_DOUBLE),
4054         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4055         .rates =                (SNDRV_PCM_RATE_32000 |
4056                                  SNDRV_PCM_RATE_44100 |
4057                                  SNDRV_PCM_RATE_48000 |
4058                                  SNDRV_PCM_RATE_64000 |
4059                                  SNDRV_PCM_RATE_88200 |
4060                                  SNDRV_PCM_RATE_96000),
4061         .rate_min =             32000,
4062         .rate_max =             96000,
4063         .channels_min =         14,
4064         .channels_max =         HDSP_MAX_CHANNELS,
4065         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4066         .period_bytes_min =     (64 * 4) * 10,
4067         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4068         .periods_min =          2,
4069         .periods_max =          2,
4070         .fifo_size =            0
4071 };
4072
4073 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4074 {
4075         .info =                 (SNDRV_PCM_INFO_MMAP |
4076                                  SNDRV_PCM_INFO_MMAP_VALID |
4077                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4078                                  SNDRV_PCM_INFO_SYNC_START),
4079         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4080         .rates =                (SNDRV_PCM_RATE_32000 |
4081                                  SNDRV_PCM_RATE_44100 |
4082                                  SNDRV_PCM_RATE_48000 |
4083                                  SNDRV_PCM_RATE_64000 |
4084                                  SNDRV_PCM_RATE_88200 |
4085                                  SNDRV_PCM_RATE_96000),
4086         .rate_min =             32000,
4087         .rate_max =             96000,
4088         .channels_min =         14,
4089         .channels_max =         HDSP_MAX_CHANNELS,
4090         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4091         .period_bytes_min =     (64 * 4) * 10,
4092         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4093         .periods_min =          2,
4094         .periods_max =          2,
4095         .fifo_size =            0
4096 };
4097
4098 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4099
4100 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4101         .count = ARRAY_SIZE(hdsp_period_sizes),
4102         .list = hdsp_period_sizes,
4103         .mask = 0
4104 };
4105
4106 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4107
4108 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4109         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4110         .list = hdsp_9632_sample_rates,
4111         .mask = 0
4112 };
4113
4114 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4115                                         snd_pcm_hw_rule_t *rule)
4116 {
4117         hdsp_t *hdsp = rule->private;
4118         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4119         if (hdsp->io_type == H9632) {
4120                 unsigned int list[3];
4121                 list[0] = hdsp->qs_in_channels;
4122                 list[1] = hdsp->ds_in_channels;
4123                 list[2] = hdsp->ss_in_channels;
4124                 return snd_interval_list(c, 3, list, 0);
4125         } else {
4126                 unsigned int list[2];
4127                 list[0] = hdsp->ds_in_channels;
4128                 list[1] = hdsp->ss_in_channels;
4129                 return snd_interval_list(c, 2, list, 0);
4130         }
4131 }
4132
4133 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4134                                         snd_pcm_hw_rule_t *rule)
4135 {
4136         unsigned int list[3];
4137         hdsp_t *hdsp = rule->private;
4138         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4139         if (hdsp->io_type == H9632) {
4140                 list[0] = hdsp->qs_out_channels;
4141                 list[1] = hdsp->ds_out_channels;
4142                 list[2] = hdsp->ss_out_channels;
4143                 return snd_interval_list(c, 3, list, 0);
4144         } else {
4145                 list[0] = hdsp->ds_out_channels;
4146                 list[1] = hdsp->ss_out_channels;
4147         }
4148         return snd_interval_list(c, 2, list, 0);
4149 }
4150
4151 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4152                                              snd_pcm_hw_rule_t *rule)
4153 {
4154         hdsp_t *hdsp = rule->private;
4155         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4156         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4157         if (r->min > 96000 && hdsp->io_type == H9632) {
4158                 snd_interval_t t = {
4159                         .min = hdsp->qs_in_channels,
4160                         .max = hdsp->qs_in_channels,
4161                         .integer = 1,
4162                 };
4163                 return snd_interval_refine(c, &t);
4164         } else if (r->min > 48000 && r->max <= 96000) {
4165                 snd_interval_t t = {
4166                         .min = hdsp->ds_in_channels,
4167                         .max = hdsp->ds_in_channels,
4168                         .integer = 1,
4169                 };
4170                 return snd_interval_refine(c, &t);
4171         } else if (r->max < 64000) {
4172                 snd_interval_t t = {
4173                         .min = hdsp->ss_in_channels,
4174                         .max = hdsp->ss_in_channels,
4175                         .integer = 1,
4176                 };
4177                 return snd_interval_refine(c, &t);
4178         }
4179         return 0;
4180 }
4181
4182 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4183                                              snd_pcm_hw_rule_t *rule)
4184 {
4185         hdsp_t *hdsp = rule->private;
4186         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4187         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4188         if (r->min > 96000 && hdsp->io_type == H9632) {
4189                 snd_interval_t t = {
4190                         .min = hdsp->qs_out_channels,
4191                         .max = hdsp->qs_out_channels,
4192                         .integer = 1,
4193                 };
4194                 return snd_interval_refine(c, &t);
4195         } else if (r->min > 48000 && r->max <= 96000) {
4196                 snd_interval_t t = {
4197                         .min = hdsp->ds_out_channels,
4198                         .max = hdsp->ds_out_channels,
4199                         .integer = 1,
4200                 };
4201                 return snd_interval_refine(c, &t);
4202         } else if (r->max < 64000) {
4203                 snd_interval_t t = {
4204                         .min = hdsp->ss_out_channels,
4205                         .max = hdsp->ss_out_channels,
4206                         .integer = 1,
4207                 };
4208                 return snd_interval_refine(c, &t);
4209         }
4210         return 0;
4211 }
4212
4213 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4214                                              snd_pcm_hw_rule_t *rule)
4215 {
4216         hdsp_t *hdsp = rule->private;
4217         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4218         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4219         if (c->min >= hdsp->ss_out_channels) {
4220                 snd_interval_t t = {
4221                         .min = 32000,
4222                         .max = 48000,
4223                         .integer = 1,
4224                 };
4225                 return snd_interval_refine(r, &t);
4226         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4227                 snd_interval_t t = {
4228                         .min = 128000,
4229                         .max = 192000,
4230                         .integer = 1,
4231                 };
4232                 return snd_interval_refine(r, &t);
4233         } else if (c->max <= hdsp->ds_out_channels) {
4234                 snd_interval_t t = {
4235                         .min = 64000,
4236                         .max = 96000,
4237                         .integer = 1,
4238                 };
4239                 return snd_interval_refine(r, &t);
4240         }
4241         return 0;
4242 }
4243
4244 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4245                                              snd_pcm_hw_rule_t *rule)
4246 {
4247         hdsp_t *hdsp = rule->private;
4248         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4249         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4250         if (c->min >= hdsp->ss_in_channels) {
4251                 snd_interval_t t = {
4252                         .min = 32000,
4253                         .max = 48000,
4254                         .integer = 1,
4255                 };
4256                 return snd_interval_refine(r, &t);
4257         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4258                 snd_interval_t t = {
4259                         .min = 128000,
4260                         .max = 192000,
4261                         .integer = 1,
4262                 };
4263                 return snd_interval_refine(r, &t);
4264         } else if (c->max <= hdsp->ds_in_channels) {
4265                 snd_interval_t t = {
4266                         .min = 64000,
4267                         .max = 96000,
4268                         .integer = 1,
4269                 };
4270                 return snd_interval_refine(r, &t);
4271         }
4272         return 0;
4273 }
4274
4275 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4276 {
4277         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4278         snd_pcm_runtime_t *runtime = substream->runtime;
4279
4280         if (hdsp_check_for_iobox (hdsp)) {
4281                 return -EIO;
4282         }
4283
4284         if (hdsp_check_for_firmware(hdsp)) {
4285                 if (hdsp->state & HDSP_FirmwareCached) {
4286                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4287                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4288                         }
4289                 } else {
4290                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4291                 }
4292                 return -EIO;
4293         }
4294
4295         spin_lock_irq(&hdsp->lock);
4296
4297         snd_pcm_set_sync(substream);
4298
4299         runtime->hw = snd_hdsp_playback_subinfo;
4300         runtime->dma_area = hdsp->playback_buffer;
4301         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4302
4303         if (hdsp->capture_substream == NULL) {
4304                 hdsp_stop_audio(hdsp);
4305                 hdsp_set_thru(hdsp, -1, 0);
4306         }
4307
4308         hdsp->playback_pid = current->pid;
4309         hdsp->playback_substream = substream;
4310
4311         spin_unlock_irq(&hdsp->lock);
4312
4313         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4314         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4315         if (hdsp->io_type == H9632) {
4316                 runtime->hw.channels_min = hdsp->qs_out_channels;
4317                 runtime->hw.channels_max = hdsp->ss_out_channels;
4318                 runtime->hw.rate_max = 192000;
4319                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4320                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4321         }
4322
4323         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4324                              snd_hdsp_hw_rule_out_channels, hdsp,
4325                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4326         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4327                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4328                              SNDRV_PCM_HW_PARAM_RATE, -1);
4329         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4330                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4331                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4332
4333         hdsp->creg_spdif_stream = hdsp->creg_spdif;
4334         hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4335         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4336                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4337         return 0;
4338 }
4339
4340 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4341 {
4342         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4343
4344         spin_lock_irq(&hdsp->lock);
4345
4346         hdsp->playback_pid = -1;
4347         hdsp->playback_substream = NULL;
4348
4349         spin_unlock_irq(&hdsp->lock);
4350
4351         hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4352         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4353                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4354         return 0;
4355 }
4356
4357
4358 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4359 {
4360         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4361         snd_pcm_runtime_t *runtime = substream->runtime;
4362
4363         if (hdsp_check_for_iobox (hdsp)) {
4364                 return -EIO;
4365         }
4366
4367         if (hdsp_check_for_firmware(hdsp)) {
4368                 if (hdsp->state & HDSP_FirmwareCached) {
4369                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4370                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4371                         }
4372                 } else {
4373                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4374                 }
4375                 return -EIO;
4376         }
4377
4378         spin_lock_irq(&hdsp->lock);
4379
4380         snd_pcm_set_sync(substream);
4381
4382         runtime->hw = snd_hdsp_capture_subinfo;
4383         runtime->dma_area = hdsp->capture_buffer;
4384         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4385
4386         if (hdsp->playback_substream == NULL) {
4387                 hdsp_stop_audio(hdsp);
4388                 hdsp_set_thru(hdsp, -1, 0);
4389         }
4390
4391         hdsp->capture_pid = current->pid;
4392         hdsp->capture_substream = substream;
4393
4394         spin_unlock_irq(&hdsp->lock);
4395
4396         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4397         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4398         if (hdsp->io_type == H9632) {
4399                 runtime->hw.channels_min = hdsp->qs_in_channels;
4400                 runtime->hw.channels_max = hdsp->ss_in_channels;
4401                 runtime->hw.rate_max = 192000;
4402                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4403                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4404         }
4405         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4406                              snd_hdsp_hw_rule_in_channels, hdsp,
4407                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4408         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4409                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4410                              SNDRV_PCM_HW_PARAM_RATE, -1);
4411         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4412                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4413                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4414         return 0;
4415 }
4416
4417 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4418 {
4419         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4420
4421         spin_lock_irq(&hdsp->lock);
4422
4423         hdsp->capture_pid = -1;
4424         hdsp->capture_substream = NULL;
4425
4426         spin_unlock_irq(&hdsp->lock);
4427         return 0;
4428 }
4429
4430 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4431 {
4432         /* we have nothing to initialize but the call is required */
4433         return 0;
4434 }
4435
4436
4437 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4438 {
4439         hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4440         void __user *argp = (void __user *)arg;
4441
4442         switch (cmd) {
4443         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4444                 hdsp_peak_rms_t __user *peak_rms;
4445                 int i;
4446
4447                 if (hdsp->io_type == H9652) {
4448                         unsigned long rms_low, rms_high;
4449                         int doublespeed = 0;
4450                         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4451                                 doublespeed = 1;
4452                         peak_rms = (hdsp_peak_rms_t __user *)arg;
4453                         for (i = 0; i < 26; ++i) {
4454                                 if (!(doublespeed && (i & 4))) {
4455                                         if (copy_to_user_fromio((void __user *)peak_rms->input_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-i*4, 4) != 0)
4456                                                 return -EFAULT;
4457                                         if (copy_to_user_fromio((void __user *)peak_rms->playback_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4458                                                 return -EFAULT;
4459                                         if (copy_to_user_fromio((void __user *)peak_rms->output_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-2*(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4460                                                 return -EFAULT;
4461                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8) & 0xFFFFFF00;
4462                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8+4) & 0xFFFFFF00;
4463                                         rms_high += (rms_low >> 24);
4464                                         rms_low <<= 8;
4465                                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8, &rms_low, 4) != 0)
4466                                                 return -EFAULT;
4467                                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, &rms_high, 4) != 0)
4468                                                 return -EFAULT;
4469                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4470                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4471                                         rms_high += (rms_low >> 24);
4472                                         rms_low <<= 8;
4473                                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, &rms_low, 4) != 0)
4474                                                 return -EFAULT;
4475                                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, &rms_high, 4) != 0)
4476                                                 return -EFAULT;
4477                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4478                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4479                                         rms_high += (rms_low >> 24);
4480                                         rms_low <<= 8;
4481                                         if (copy_to_user((void __user *)peak_rms->output_rms+i*8, &rms_low, 4) != 0)
4482                                                 return -EFAULT;
4483                                         if (copy_to_user((void __user *)peak_rms->output_rms+i*8+4, &rms_high, 4) != 0)
4484                                                 return -EFAULT;
4485                                 }
4486                         }
4487                         return 0;
4488                 }
4489                 if (hdsp->io_type == H9632) {
4490                         int j;
4491                         hdsp_9632_meters_t *m;
4492                         int doublespeed = 0;
4493                         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4494                                 doublespeed = 1;
4495                         m = (hdsp_9632_meters_t *)(hdsp->iobase+HDSP_9632_metersBase);
4496                         peak_rms = (hdsp_peak_rms_t __user *)arg;
4497                         for (i = 0, j = 0; i < 16; ++i, ++j) {
4498                                 if (copy_to_user((void __user *)peak_rms->input_peaks+i*4, &(m->input_peak[j]), 4) != 0)
4499                                         return -EFAULT;
4500                                 if (copy_to_user((void __user *)peak_rms->playback_peaks+i*4, &(m->playback_peak[j]), 4) != 0)
4501                                         return -EFAULT;
4502                                 if (copy_to_user((void __user *)peak_rms->output_peaks+i*4, &(m->output_peak[j]), 4) != 0)
4503                                         return -EFAULT;
4504                                 if (copy_to_user((void __user *)peak_rms->input_rms+i*8, &(m->input_rms_low[j]), 4) != 0)
4505                                         return -EFAULT;
4506                                 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, &(m->playback_rms_low[j]), 4) != 0)
4507                                         return -EFAULT;
4508                                 if (copy_to_user((void __user *)peak_rms->output_rms+i*8, &(m->output_rms_low[j]), 4) != 0)
4509                                         return -EFAULT;
4510                                 if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, &(m->input_rms_high[j]), 4) != 0)
4511                                         return -EFAULT;
4512                                 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, &(m->playback_rms_high[j]), 4) != 0)
4513                                         return -EFAULT;
4514                                 if (copy_to_user((void __user *)peak_rms->output_rms+i*8+4, &(m->output_rms_high[j]), 4) != 0)
4515                                         return -EFAULT;
4516                                 if (doublespeed && i == 3) i += 4;
4517                         }
4518                         return 0;
4519                 }
4520                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4521                         snd_printk("firmware needs to be uploaded to the card.\n");
4522                         return -EINVAL;
4523                 }
4524                 peak_rms = (hdsp_peak_rms_t __user *)arg;
4525                 for (i = 0; i < 26; ++i) {
4526                     if (copy_to_user((void __user *)peak_rms->playback_peaks+i*4, (void *)hdsp->iobase+HDSP_playbackPeakLevel+i*4, 4) != 0)
4527                             return -EFAULT;
4528                     if (copy_to_user((void __user *)peak_rms->input_peaks+i*4, (void *)hdsp->iobase+HDSP_inputPeakLevel+i*4, 4) != 0)
4529                             return -EFAULT;
4530                 }
4531                 for (i = 0; i < 26; ++i) {
4532                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8, 4) != 0)
4533                                 return -EFAULT;
4534                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8+4, 4) != 0)
4535                                 return -EFAULT;
4536                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8, 4) != 0)
4537                                 return -EFAULT;
4538                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8+4, 4) != 0)
4539                                 return -EFAULT;
4540                 }
4541                 for (i = 0; i < 28; ++i) {
4542                     if (copy_to_user((void __user *)peak_rms->output_peaks+i*4, (void *)hdsp->iobase+HDSP_outputPeakLevel+i*4, 4) != 0)
4543                             return -EFAULT;
4544                 }
4545                 break;
4546         }
4547         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4548                 hdsp_config_info_t info;
4549                 unsigned long flags;
4550                 int i;
4551
4552                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4553                         snd_printk("Firmware needs to be uploaded to the card.\n");
4554                         return -EINVAL;
4555                 }
4556                 spin_lock_irqsave(&hdsp->lock, flags);
4557                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4558                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4559                 if (hdsp->io_type != H9632) {
4560                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4561                 }
4562                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4563                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4564                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4565                 }
4566                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4567                 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4568                 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4569                 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4570                 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4571                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4572                 info.system_sample_rate = hdsp->system_sample_rate;
4573                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4574                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4575                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4576                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4577                 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4578                 info.passthru = (unsigned char)hdsp->passthru;
4579                 if (hdsp->io_type == H9632) {
4580                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4581                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4582                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4583                         info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4584
4585                 }
4586                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4587                         info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4588                 }
4589                 spin_unlock_irqrestore(&hdsp->lock, flags);
4590                 if (copy_to_user(argp, &info, sizeof(info)))
4591                         return -EFAULT;
4592                 break;
4593         }
4594         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4595                 hdsp_9632_aeb_t h9632_aeb;
4596
4597                 if (hdsp->io_type != H9632) return -EINVAL;
4598                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4599                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4600                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4601                         return -EFAULT;
4602                 break;
4603         }
4604         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4605                 hdsp_version_t hdsp_version;
4606                 int err;
4607
4608                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4609                 if (hdsp->io_type == Undefined) {
4610                         if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4611                                 return err;
4612                         }
4613                 }
4614                 hdsp_version.io_type = hdsp->io_type;
4615                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4616                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4617                         return -EFAULT;
4618                 }
4619                 break;
4620         }
4621         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4622                 hdsp_firmware_t __user *firmware;
4623                 unsigned long __user *firmware_data;
4624                 int err;
4625
4626                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4627                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4628                 if (hdsp->io_type == Undefined) return -EINVAL;
4629
4630                 snd_printk("initializing firmware upload\n");
4631                 firmware = (hdsp_firmware_t __user *)argp;
4632
4633                 if (get_user(firmware_data, &firmware->firmware_data)) {
4634                         return -EFAULT;
4635                 }
4636
4637                 if (hdsp_check_for_iobox (hdsp)) {
4638                         return -EIO;
4639                 }
4640
4641                 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(unsigned long)*24413) != 0) {
4642                         return -EFAULT;
4643                 }
4644
4645                 hdsp->state |= HDSP_FirmwareCached;
4646
4647                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4648                         return err;
4649                 }
4650
4651                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4652                         snd_hdsp_initialize_channels(hdsp);
4653
4654                         snd_hdsp_initialize_midi_flush(hdsp);
4655
4656                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4657                                 snd_printk("error creating alsa devices\n");
4658                             return err;
4659                         }
4660                 }
4661                 break;
4662         }
4663         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4664                 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4665                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4666                         return -EFAULT;
4667                 break;
4668         }
4669         default:
4670                 return -EINVAL;
4671         }
4672         return 0;
4673 }
4674
4675 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4676         .open =         snd_hdsp_playback_open,
4677         .close =        snd_hdsp_playback_release,
4678         .ioctl =        snd_hdsp_ioctl,
4679         .hw_params =    snd_hdsp_hw_params,
4680         .prepare =      snd_hdsp_prepare,
4681         .trigger =      snd_hdsp_trigger,
4682         .pointer =      snd_hdsp_hw_pointer,
4683         .copy =         snd_hdsp_playback_copy,
4684         .silence =      snd_hdsp_hw_silence,
4685 };
4686
4687 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4688         .open =         snd_hdsp_capture_open,
4689         .close =        snd_hdsp_capture_release,
4690         .ioctl =        snd_hdsp_ioctl,
4691         .hw_params =    snd_hdsp_hw_params,
4692         .prepare =      snd_hdsp_prepare,
4693         .trigger =      snd_hdsp_trigger,
4694         .pointer =      snd_hdsp_hw_pointer,
4695         .copy =         snd_hdsp_capture_copy,
4696 };
4697
4698 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4699                                            hdsp_t *hdsp)
4700 {
4701         snd_hwdep_t *hw;
4702         int err;
4703
4704         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4705                 return err;
4706
4707         hdsp->hwdep = hw;
4708         hw->private_data = hdsp;
4709         strcpy(hw->name, "HDSP hwdep interface");
4710
4711         hw->ops.open = snd_hdsp_hwdep_dummy_op;
4712         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4713         hw->ops.release = snd_hdsp_hwdep_dummy_op;
4714
4715         return 0;
4716 }
4717
4718 static int __devinit snd_hdsp_create_pcm(snd_card_t *card,
4719                                          hdsp_t *hdsp)
4720 {
4721         snd_pcm_t *pcm;
4722         int err;
4723
4724         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4725                 return err;
4726
4727         hdsp->pcm = pcm;
4728         pcm->private_data = hdsp;
4729         strcpy(pcm->name, hdsp->card_name);
4730
4731         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4732         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4733
4734         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4735
4736         return 0;
4737 }
4738
4739 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4740 {
4741         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4742         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4743 }
4744
4745 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4746 {
4747         int i;
4748
4749         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4750                 return -EIO;
4751         }
4752
4753         for (i = 0; i < hdsp->max_channels; ++i) {
4754                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4755                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4756         }
4757
4758         return 0;
4759 }
4760
4761 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4762 {
4763         int status, aebi_channels, aebo_channels;
4764
4765         switch (hdsp->io_type) {
4766         case Digiface:
4767                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4768                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4769                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4770                 break;
4771
4772         case H9652:
4773                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4774                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4775                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4776                 break;
4777
4778         case H9632:
4779                 status = hdsp_read(hdsp, HDSP_statusRegister);
4780                 /* HDSP_AEBx bits are low when AEB are connected */
4781                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4782                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4783                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4784                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4785                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4786                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4787                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4788                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4789                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4790                 break;
4791
4792         case Multiface:
4793                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4794                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4795                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4796                 break;
4797
4798         default:
4799                 /* should never get here */
4800                 break;
4801         }
4802 }
4803
4804 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4805 {
4806         snd_hdsp_flush_midi_input (hdsp, 0);
4807         snd_hdsp_flush_midi_input (hdsp, 1);
4808 }
4809
4810 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4811 {
4812         int err;
4813
4814         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4815                 snd_printk("Error creating pcm interface\n");
4816                 return err;
4817         }
4818
4819
4820         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4821                 snd_printk("Error creating first midi interface\n");
4822                 return err;
4823         }
4824
4825
4826         if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4827                 snd_printk("Error creating second midi interface\n");
4828                 return err;
4829         }
4830
4831         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4832                 snd_printk("Error creating ctl interface\n");
4833                 return err;
4834         }
4835
4836         snd_hdsp_proc_init(hdsp);
4837
4838         hdsp->system_sample_rate = -1;
4839         hdsp->playback_pid = -1;
4840         hdsp->capture_pid = -1;
4841         hdsp->capture_substream = NULL;
4842         hdsp->playback_substream = NULL;
4843
4844         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4845                 snd_printk("Error setting default values\n");
4846                 return err;
4847         }
4848
4849         if (!(hdsp->state & HDSP_InitializationComplete)) {
4850                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4851                         hdsp->port, hdsp->irq);
4852
4853                 if ((err = snd_card_register(card)) < 0) {
4854                         snd_printk("error registering card\n");
4855                         return err;
4856                 }
4857                 hdsp->state |= HDSP_InitializationComplete;
4858         }
4859
4860         return 0;
4861 }
4862
4863 static int __devinit snd_hdsp_create(snd_card_t *card,
4864                                      hdsp_t *hdsp,
4865                                      int precise_ptr)
4866 {
4867         struct pci_dev *pci = hdsp->pci;
4868         int err;
4869         int is_9652 = 0;
4870         int is_9632 = 0;
4871
4872         hdsp->irq = -1;
4873         hdsp->state = 0;
4874         hdsp->midi[0].rmidi = NULL;
4875         hdsp->midi[1].rmidi = NULL;
4876         hdsp->midi[0].input = NULL;
4877         hdsp->midi[1].input = NULL;
4878         hdsp->midi[0].output = NULL;
4879         hdsp->midi[1].output = NULL;
4880         spin_lock_init(&hdsp->midi[0].lock);
4881         spin_lock_init(&hdsp->midi[1].lock);
4882         hdsp->iobase = 0;
4883         hdsp->control_register = 0;
4884         hdsp->control2_register = 0;
4885         hdsp->io_type = Undefined;
4886         hdsp->max_channels = 26;
4887
4888         hdsp->card = card;
4889
4890         spin_lock_init(&hdsp->lock);
4891
4892         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4893
4894         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4895
4896         /* From Martin Bjoernsen :
4897             "It is important that the card's latency timer register in
4898             the PCI configuration space is set to a value much larger
4899             than 0 by the computer's BIOS or the driver.
4900             The windows driver always sets this 8 bit register [...]
4901             to its maximum 255 to avoid problems with some computers."
4902         */
4903         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4904
4905         strcpy(card->driver, "H-DSP");
4906         strcpy(card->mixername, "Xilinx FPGA");
4907
4908         switch (hdsp->firmware_rev & 0xff) {
4909         case 0xa:
4910         case 0xb:
4911         case 0x32:
4912                 hdsp->card_name = "RME Hammerfall DSP";
4913                 break;
4914
4915         case 0x64:
4916         case 0x65:
4917         case 0x68:
4918                 hdsp->card_name = "RME HDSP 9652";
4919                 is_9652 = 1;
4920                 break;
4921         case 0x96:
4922         case 0x97:
4923                 hdsp->card_name = "RME HDSP 9632";
4924                 hdsp->max_channels = 16;
4925                 is_9632 = 1;
4926                 break;
4927         default:
4928                 return -ENODEV;
4929         }
4930
4931         if ((err = pci_enable_device(pci)) < 0) {
4932                 return err;
4933         }
4934
4935         pci_set_master(hdsp->pci);
4936
4937         if ((err = pci_request_regions(pci, "hdsp")) < 0)
4938                 return err;
4939         hdsp->port = pci_resource_start(pci, 0);
4940         if ((hdsp->iobase = (unsigned long) ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == 0) {
4941                 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
4942                 return -EBUSY;
4943         }
4944
4945         if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
4946                 snd_printk("unable to use IRQ %d\n", pci->irq);
4947                 return -EBUSY;
4948         }
4949
4950         hdsp->irq = pci->irq;
4951         hdsp->precise_ptr = precise_ptr;
4952
4953         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
4954                 return err;
4955         }
4956
4957         if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) {
4958                 /* no iobox connected, we defer initialization */
4959                 snd_printk("card initialization pending : waiting for firmware\n");
4960                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
4961                         return err;
4962                 }
4963                 return 0;
4964         }
4965
4966         if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
4967                 return err;
4968         }
4969
4970         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
4971                 snd_printk("card initialization pending : waiting for firmware\n");
4972                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
4973                         return err;
4974                 }
4975                 return 0;
4976         }
4977
4978         snd_printk("Firmware already loaded, initializing card.\n");
4979
4980         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
4981                 hdsp->io_type = Multiface;
4982         } else {
4983                 hdsp->io_type = Digiface;
4984         }
4985
4986         if (is_9652) {
4987                 hdsp->io_type = H9652;
4988         }
4989
4990         if (is_9632) {
4991                 hdsp->io_type = H9632;
4992         }
4993
4994         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
4995                 return err;
4996         }
4997
4998         snd_hdsp_initialize_channels(hdsp);
4999         snd_hdsp_initialize_midi_flush(hdsp);
5000
5001         hdsp->state |= HDSP_FirmwareLoaded;
5002
5003         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5004                 return err;
5005         }
5006
5007         return 0;
5008 }
5009
5010 static int snd_hdsp_free(hdsp_t *hdsp)
5011 {
5012         if (hdsp->port) {
5013                 /* stop the audio, and cancel all interrupts */
5014                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5015                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5016         }
5017
5018         if (hdsp->irq >= 0)
5019                 free_irq(hdsp->irq, (void *)hdsp);
5020
5021         snd_hdsp_free_buffers(hdsp);
5022
5023         if (hdsp->iobase)
5024                 iounmap((void *) hdsp->iobase);
5025
5026         if (hdsp->port)
5027                 pci_release_regions(hdsp->pci);
5028
5029         return 0;
5030 }
5031
5032 static void snd_hdsp_card_free(snd_card_t *card)
5033 {
5034         hdsp_t *hdsp = (hdsp_t *) card->private_data;
5035
5036         if (hdsp)
5037                 snd_hdsp_free(hdsp);
5038 }
5039
5040 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5041                                     const struct pci_device_id *pci_id)
5042 {
5043         static int dev;
5044         hdsp_t *hdsp;
5045         snd_card_t *card;
5046         int err;
5047
5048         if (dev >= SNDRV_CARDS)
5049                 return -ENODEV;
5050         if (!enable[dev]) {
5051                 dev++;
5052                 return -ENOENT;
5053         }
5054
5055         if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5056                 return -ENOMEM;
5057
5058         hdsp = (hdsp_t *) card->private_data;
5059         card->private_free = snd_hdsp_card_free;
5060         hdsp->dev = dev;
5061         hdsp->pci = pci;
5062         snd_card_set_dev(card, &pci->dev);
5063
5064         if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
5065                 snd_card_free(card);
5066                 return err;
5067         }
5068
5069         strcpy(card->shortname, "Hammerfall DSP");
5070         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5071                 hdsp->port, hdsp->irq);
5072
5073         if ((err = snd_card_register(card)) < 0) {
5074                 snd_card_free(card);
5075                 return err;
5076         }
5077         pci_set_drvdata(pci, card);
5078         dev++;
5079         return 0;
5080 }
5081
5082 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5083 {
5084         snd_card_free(pci_get_drvdata(pci));
5085         pci_set_drvdata(pci, NULL);
5086 }
5087
5088 static struct pci_driver driver = {
5089         .name =     "RME Hammerfall DSP",
5090         .id_table = snd_hdsp_ids,
5091         .probe =    snd_hdsp_probe,
5092         .remove = __devexit_p(snd_hdsp_remove),
5093 };
5094
5095 static int __init alsa_card_hdsp_init(void)
5096 {
5097         return pci_module_init(&driver);
5098 }
5099
5100 static void __exit alsa_card_hdsp_exit(void)
5101 {
5102         pci_unregister_driver(&driver);
5103 }
5104
5105 module_init(alsa_card_hdsp_init)
5106 module_exit(alsa_card_hdsp_exit)