sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <sound/driver.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <sound/core.h>
  33 #include <sound/control.h>
  34 #include <sound/pcm.h>
  35 #include <sound/info.h>
  36 #include <sound/asoundef.h>
  37 #include <sound/rawmidi.h>
  38 #include <sound/hwdep.h>
  39 #include <sound/initval.h>
  40 #include <sound/hdsp.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/current.h>
  44 #include <asm/io.h>
  45
  46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  49 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
  50 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
  51 static int boot_devs;
  52
  53 module_param_array(index, int, boot_devs, 0444);
  54 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  55 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  56 module_param_array(id, charp, boot_devs, 0444);
  57 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  58 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  59 module_param_array(enable, bool, boot_devs, 0444);
  60 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  61 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  62 module_param_array(precise_ptr, bool, boot_devs, 0444);
  63 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
  64 MODULE_PARM_SYNTAX(precise_ptr, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
  65 module_param_array(line_outs_monitor, bool, boot_devs, 0444);
  66 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
  67 MODULE_PARM_SYNTAX(line_outs_monitor, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
  68 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  69 MODULE_DESCRIPTION("RME Hammerfall DSP");
  70 MODULE_LICENSE("GPL");
  71 MODULE_CLASSES("{sound}");
  72 MODULE_DEVICES("{{RME Hammerfall-DSP},"
  73                 "{RME HDSP-9652},"
  74                 "{RME HDSP-9632}}");
  75
  76 #define HDSP_MAX_CHANNELS        26
  77 #define HDSP_MAX_DS_CHANNELS     14
  78 #define HDSP_MAX_QS_CHANNELS     8
  79 #define DIGIFACE_SS_CHANNELS     26
  80 #define DIGIFACE_DS_CHANNELS     14
  81 #define MULTIFACE_SS_CHANNELS    18
  82 #define MULTIFACE_DS_CHANNELS    14
  83 #define H9652_SS_CHANNELS        26
  84 #define H9652_DS_CHANNELS        14
  85 /* This does not include possible Analog Extension Boards
  86    AEBs are detected at card initialization
  87 */
  88 #define H9632_SS_CHANNELS        12
  89 #define H9632_DS_CHANNELS        8
  90 #define H9632_QS_CHANNELS        4
  91
  92 /* Write registers. These are defined as byte-offsets from the iobase value.
  93  */
  94 #define HDSP_resetPointer               0
  95 #define HDSP_outputBufferAddress        32
  96 #define HDSP_inputBufferAddress         36
  97 #define HDSP_controlRegister            64
  98 #define HDSP_interruptConfirmation      96
  99 #define HDSP_outputEnable               128
 100 #define HDSP_control2Reg                256
 101 #define HDSP_midiDataOut0               352
 102 #define HDSP_midiDataOut1               356
 103 #define HDSP_fifoData                   368
 104 #define HDSP_inputEnable                384
 105
 106 /* Read registers. These are defined as byte-offsets from the iobase value
 107  */
 108
 109 #define HDSP_statusRegister    0
 110 #define HDSP_timecode        128
 111 #define HDSP_status2Register 192
 112 #define HDSP_midiDataOut0    352
 113 #define HDSP_midiDataOut1    356
 114 #define HDSP_midiDataIn0     360
 115 #define HDSP_midiDataIn1     364
 116 #define HDSP_midiStatusOut0  384
 117 #define HDSP_midiStatusOut1  388
 118 #define HDSP_midiStatusIn0   392
 119 #define HDSP_midiStatusIn1   396
 120 #define HDSP_fifoStatus      400
 121
 122 /* the meters are regular i/o-mapped registers, but offset
 123    considerably from the rest. the peak registers are reset
 124    when read; the least-significant 4 bits are full-scale counters;
 125    the actual peak value is in the most-significant 24 bits.
 126 */
 127
 128 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 129 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 130 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 131 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 132 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 133
 134
 135 /* This is for H9652 cards
 136    Peak values are read downward from the base
 137    Rms values are read upward
 138    There are rms values for the outputs too
 139    26*3 values are read in ss mode
 140    14*3 in ds mode, with no gap between values
 141 */
 142 #define HDSP_9652_peakBase      7164
 143 #define HDSP_9652_rmsBase       4096
 144
 145 /* c.f. the hdsp_9632_meters_t struct */
 146 #define HDSP_9632_metersBase    4096
 147
 148 #define HDSP_IO_EXTENT     7168
 149
 150 /* control2 register bits */
 151
 152 #define HDSP_TMS                0x01
 153 #define HDSP_TCK                0x02
 154 #define HDSP_TDI                0x04
 155 #define HDSP_JTAG               0x08
 156 #define HDSP_PWDN               0x10
 157 #define HDSP_PROGRAM            0x020
 158 #define HDSP_CONFIG_MODE_0      0x040
 159 #define HDSP_CONFIG_MODE_1      0x080
 160 #define HDSP_VERSION_BIT        0x100
 161 #define HDSP_BIGENDIAN_MODE     0x200
 162 #define HDSP_RD_MULTIPLE        0x400
 163 #define HDSP_9652_ENABLE_MIXER  0x800
 164 #define HDSP_TDO                0x10000000
 165
 166 #define HDSP_S_PROGRAM          (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 167 #define HDSP_S_LOAD             (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 168
 169 /* Control Register bits */
 170
 171 #define HDSP_Start                (1<<0)  /* start engine */
 172 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 173 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 174 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 175 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 176 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 177 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 178 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 179 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 180 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 181 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 182 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 183 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 184 #define HDSP_SyncRef2             (1<<13)
 185 #define HDSP_SPDIFInputSelect0    (1<<14)
 186 #define HDSP_SPDIFInputSelect1    (1<<15)
 187 #define HDSP_SyncRef0             (1<<16)
 188 #define HDSP_SyncRef1             (1<<17)
 189 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 190 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 191 #define HDSP_Midi0InterruptEnable (1<<22)
 192 #define HDSP_Midi1InterruptEnable (1<<23)
 193 #define HDSP_LineOut              (1<<24)
 194 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 195 #define HDSP_ADGain1              (1<<26)
 196 #define HDSP_DAGain0              (1<<27)
 197 #define HDSP_DAGain1              (1<<28)
 198 #define HDSP_PhoneGain0           (1<<29)
 199 #define HDSP_PhoneGain1           (1<<30)
 200 #define HDSP_QuadSpeed            (1<<31)
 201
 202 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 203 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 204 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 205 #define HDSP_ADGainLowGain     0
 206
 207 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 208 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 209 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 210 #define HDSP_DAGainMinus10dBV    0
 211
 212 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 213 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 214 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 215 #define HDSP_PhoneGainMinus12dB  0
 216
 217 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 218 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 219
 220 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 221 #define HDSP_SPDIFInputADAT1    0
 222 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 223 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 224 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 225
 226 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 227 #define HDSP_SyncRef_ADAT1       0
 228 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 229 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 230 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 231 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 232 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 233
 234 /* Sample Clock Sources */
 235
 236 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 237 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 238 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 239 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 240 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 241 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 242 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 243 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 244 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 245 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 246
 247 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 248
 249 #define HDSP_SYNC_FROM_WORD      0
 250 #define HDSP_SYNC_FROM_SPDIF     1
 251 #define HDSP_SYNC_FROM_ADAT1     2
 252 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 253 #define HDSP_SYNC_FROM_ADAT2     4
 254 #define HDSP_SYNC_FROM_ADAT3     5
 255
 256 /* SyncCheck status */
 257
 258 #define HDSP_SYNC_CHECK_NO_LOCK 0
 259 #define HDSP_SYNC_CHECK_LOCK    1
 260 #define HDSP_SYNC_CHECK_SYNC    2
 261
 262 /* AutoSync references - used by "autosync_ref" control switch */
 263
 264 #define HDSP_AUTOSYNC_FROM_WORD      0
 265 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 266 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 267 #define HDSP_AUTOSYNC_FROM_NONE      3
 268 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 269 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 270 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 271
 272 /* Possible sources of S/PDIF input */
 273
 274 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 275 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 276 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 277 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 278
 279 #define HDSP_Frequency32KHz    HDSP_Frequency0
 280 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 281 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 282 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 283 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 284 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 285 /* For H9632 cards */
 286 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 287 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 288 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 289
 290 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 291 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 292
 293 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 294 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 295
 296 /* Status Register bits */
 297
 298 #define HDSP_audioIRQPending    (1<<0)
 299 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 300 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 301 #define HDSP_Lock1              (1<<2)
 302 #define HDSP_Lock0              (1<<3)
 303 #define HDSP_SPDIFSync          (1<<4)
 304 #define HDSP_TimecodeLock       (1<<5)
 305 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 306 #define HDSP_Sync2              (1<<16)
 307 #define HDSP_Sync1              (1<<17)
 308 #define HDSP_Sync0              (1<<18)
 309 #define HDSP_DoubleSpeedStatus  (1<<19)
 310 #define HDSP_ConfigError        (1<<20)
 311 #define HDSP_DllError           (1<<21)
 312 #define HDSP_spdifFrequency0    (1<<22)
 313 #define HDSP_spdifFrequency1    (1<<23)
 314 #define HDSP_spdifFrequency2    (1<<24)
 315 #define HDSP_SPDIFErrorFlag     (1<<25)
 316 #define HDSP_BufferID           (1<<26)
 317 #define HDSP_TimecodeSync       (1<<27)
 318 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 319 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 320 #define HDSP_midi0IRQPending    (1<<30)
 321 #define HDSP_midi1IRQPending    (1<<31)
 322
 323 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 324
 325 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 326 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 327 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 328
 329 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 330 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 331 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 332
 333 /* This is for H9632 cards */
 334 #define HDSP_spdifFrequency128KHz   HDSP_spdifFrequencyMask
 335 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 336 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 337
 338 /* Status2 Register bits */
 339
 340 #define HDSP_version0     (1<<0)
 341 #define HDSP_version1     (1<<1)
 342 #define HDSP_version2     (1<<2)
 343 #define HDSP_wc_lock      (1<<3)
 344 #define HDSP_wc_sync      (1<<4)
 345 #define HDSP_inp_freq0    (1<<5)
 346 #define HDSP_inp_freq1    (1<<6)
 347 #define HDSP_inp_freq2    (1<<7)
 348 #define HDSP_SelSyncRef0  (1<<8)
 349 #define HDSP_SelSyncRef1  (1<<9)
 350 #define HDSP_SelSyncRef2  (1<<10)
 351
 352 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 353
 354 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 355 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 356 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 357 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 358 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 359 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 360 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 361 /* FIXME : more values for 9632 cards ? */
 362
 363 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 364 #define HDSP_SelSyncRef_ADAT1      0
 365 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 366 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 367 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 368 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 369 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 370
 371 /* Card state flags */
 372
 373 #define HDSP_InitializationComplete  (1<<0)
 374 #define HDSP_FirmwareLoaded          (1<<1)
 375 #define HDSP_FirmwareCached          (1<<2)
 376
 377 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 378
 379 #define HDSP_LONG_WAIT   5000
 380 #define HDSP_SHORT_WAIT  30
 381
 382 #define UNITY_GAIN                       32768
 383 #define MINUS_INFINITY_GAIN              0
 384
 385 #ifndef PCI_VENDOR_ID_XILINX
 386 #define PCI_VENDOR_ID_XILINX            0x10ee
 387 #endif
 388 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
 389 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
 390 #endif
 391
 392 /* the size of a substream (1 mono data stream) */
 393
 394 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 395 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 396
 397 /* the size of the area we need to allocate for DMA transfers. the
 398    size is the same regardless of the number of channels - the
 399    Multiface still uses the same memory area.
 400
 401    Note that we allocate 1 more channel than is apparently needed
 402    because the h/w seems to write 1 byte beyond the end of the last
 403    page. Sigh.
 404 */
 405
 406 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 407 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 408
 409 typedef struct _hdsp             hdsp_t;
 410 typedef struct _hdsp_midi        hdsp_midi_t;
 411 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
 412
 413 struct _hdsp_9632_meters {
 414     u32 input_peak[16];
 415     u32 playback_peak[16];
 416     u32 output_peak[16];
 417     u32 xxx_peak[16];
 418     u32 padding[64];
 419     u32 input_rms_low[16];
 420     u32 playback_rms_low[16];
 421     u32 output_rms_low[16];
 422     u32 xxx_rms_low[16];
 423     u32 input_rms_high[16];
 424     u32 playback_rms_high[16];
 425     u32 output_rms_high[16];
 426     u32 xxx_rms_high[16];
 427 };
 428
 429 struct _hdsp_midi {
 430     hdsp_t                  *hdsp;
 431     int                      id;
 432     snd_rawmidi_t           *rmidi;
 433     snd_rawmidi_substream_t *input;
 434     snd_rawmidi_substream_t *output;
 435     char                     istimer; /* timer in use */
 436     struct timer_list        timer;
 437     spinlock_t               lock;
 438     int                      pending;
 439 };
 440
 441 struct _hdsp {
 442         spinlock_t            lock;
 443         snd_pcm_substream_t  *capture_substream;
 444         snd_pcm_substream_t  *playback_substream;
 445         hdsp_midi_t           midi[2];
 446         struct tasklet_struct midi_tasklet;
 447         int                   precise_ptr;
 448         u32                   control_register;      /* cached value */
 449         u32                   control2_register;     /* cached value */
 450         u32                   creg_spdif;
 451         u32                   creg_spdif_stream;
 452         char                 *card_name;             /* digiface/multiface */
 453         HDSP_IO_Type          io_type;               /* ditto, but for code use */
 454         unsigned short        firmware_rev;
 455         unsigned short        state;                 /* stores state bits */
 456         u32                   firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
 457         size_t                period_bytes;          /* guess what this is */
 458         unsigned char         max_channels;
 459         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 460         unsigned char         ds_in_channels;
 461         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 462         unsigned char         qs_out_channels;
 463         unsigned char         ds_out_channels;
 464         unsigned char         ss_out_channels;
 465         void                 *capture_buffer_unaligned;  /* original buffer addresses */
 466         void                 *playback_buffer_unaligned; /* original buffer addresses */
 467         unsigned char        *capture_buffer;       /* suitably aligned address */
 468         unsigned char        *playback_buffer;      /* suitably aligned address */
 469         dma_addr_t            capture_buffer_addr;
 470         dma_addr_t            playback_buffer_addr;
 471         pid_t                 capture_pid;
 472         pid_t                 playback_pid;
 473         int                   running;
 474         int                   passthru;              /* non-zero if doing pass-thru */
 475         int                   system_sample_rate;
 476         char                 *channel_map;
 477         int                   dev;
 478         int                   irq;
 479         unsigned long         port;
 480         struct resource      *res_port;
 481         unsigned long         iobase;
 482         snd_card_t           *card;
 483         snd_pcm_t            *pcm;
 484         snd_hwdep_t          *hwdep;
 485         struct pci_dev       *pci;
 486         snd_kcontrol_t       *spdif_ctl;
 487         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 488 };
 489
 490 /* These tables map the ALSA channels 1..N to the channels that we
 491    need to use in order to find the relevant channel buffer. RME
 492    refer to this kind of mapping as between "the ADAT channel and
 493    the DMA channel." We index it using the logical audio channel,
 494    and the value is the DMA channel (i.e. channel buffer number)
 495    where the data for that channel can be read/written from/to.
 496 */
 497
 498 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 499         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 500         18, 19, 20, 21, 22, 23, 24, 25
 501 };
 502
 503 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 504         /* Analog */
 505         0, 1, 2, 3, 4, 5, 6, 7,
 506         /* ADAT 2 */
 507         16, 17, 18, 19, 20, 21, 22, 23,
 508         /* SPDIF */
 509         24, 25,
 510         -1, -1, -1, -1, -1, -1, -1, -1
 511 };
 512
 513 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 514         /* ADAT channels are remapped */
 515         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 516         /* channels 12 and 13 are S/PDIF */
 517         24, 25,
 518         /* others don't exist */
 519         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 520 };
 521
 522 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 523         /* ADAT channels */
 524         0, 1, 2, 3, 4, 5, 6, 7,
 525         /* SPDIF */
 526         8, 9,
 527         /* Analog */
 528         10, 11,
 529         /* AO4S-192 and AI4S-192 extension boards */
 530         12, 13, 14, 15,
 531         /* others don't exist */
 532         -1, -1, -1, -1, -1, -1, -1, -1,
 533         -1, -1
 534 };
 535
 536 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 537         /* ADAT */
 538         1, 3, 5, 7,
 539         /* SPDIF */
 540         8, 9,
 541         /* Analog */
 542         10, 11,
 543         /* AO4S-192 and AI4S-192 extension boards */
 544         12, 13, 14, 15,
 545         /* others don't exist */
 546         -1, -1, -1, -1, -1, -1, -1, -1,
 547         -1, -1, -1, -1, -1, -1
 548 };
 549
 550 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 551         /* ADAT is disabled in this mode */
 552         /* SPDIF */
 553         8, 9,
 554         /* Analog */
 555         10, 11,
 556         /* AO4S-192 and AI4S-192 extension boards */
 557         12, 13, 14, 15,
 558         /* others don't exist */
 559         -1, -1, -1, -1, -1, -1, -1, -1,
 560         -1, -1, -1, -1, -1, -1, -1, -1,
 561         -1, -1
 562 };
 563
 564 #define HDSP_PREALLOCATE_MEMORY /* via module snd-hdsp_mem */
 565
 566 #ifdef HDSP_PREALLOCATE_MEMORY
 567 static void *snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size, dma_addr_t *addrp, int capture)
 568 {
 569         struct snd_dma_device pdev;
 570         struct snd_dma_buffer dmbuf;
 571
 572         memset(&pdev, 0, sizeof(pdev));
 573         pdev.type = SNDRV_DMA_TYPE_DEV;
 574         pdev.dev = snd_dma_pci_data(pci);
 575         pdev.id = capture;
 576         dmbuf.bytes = 0;
 577         if (! snd_dma_get_reserved(&pdev, &dmbuf)) {
 578                 if (snd_dma_alloc_pages(&pdev, size, &dmbuf) < 0)
 579                         return NULL;
 580                 snd_dma_set_reserved(&pdev, &dmbuf);
 581         }
 582         *addrp = dmbuf.addr;
 583         return dmbuf.area;
 584 }
 585
 586 static void snd_hammerfall_free_buffer(struct pci_dev *pci, size_t size, void *ptr, dma_addr_t addr, int capture)
 587 {
 588         struct snd_dma_device pdev;
 589
 590         memset(&pdev, 0, sizeof(pdev));
 591         pdev.type = SNDRV_DMA_TYPE_DEV;
 592         pdev.dev = snd_dma_pci_data(pci);
 593         pdev.id = capture;
 594         snd_dma_free_reserved(&pdev);
 595 }
 596
 597 #else
 598 static void *snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size, dma_addr_t *addrp, int capture)
 599 {
 600         return snd_malloc_pci_pages(pci, size, addrp);
 601 }
 602
 603 static void snd_hammerfall_free_buffer(struct pci_dev *pci, size_t size, void *ptr, dma_addr_t addr, int capture)
 604 {
 605         snd_free_pci_pages(pci, size, ptr, addr);
 606 }
 607 #endif
 608
 609 static struct pci_device_id snd_hdsp_ids[] = {
 610         {
 611                 .vendor = PCI_VENDOR_ID_XILINX,
 612                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 613                 .subvendor = PCI_ANY_ID,
 614                 .subdevice = PCI_ANY_ID,
 615         }, /* RME Hammerfall-DSP */
 616         { 0, },
 617 };
 618
 619 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 620
 621 /* prototypes */
 622 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
 623 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
 624 static inline int snd_hdsp_enable_io (hdsp_t *hdsp);
 625 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
 626 static inline void snd_hdsp_initialize_channels (hdsp_t *hdsp);
 627 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
 628 static int hdsp_autosync_ref(hdsp_t *hdsp);
 629 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
 630 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
 631
 632 static inline int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
 633 {
 634         switch (hdsp->firmware_rev) {
 635         case 0xa:
 636                 return (64 * out) + (32 + (in));
 637         case 0x96:
 638         case 0x97:
 639                 return (32 * out) + (16 + (in));
 640         default:
 641                 return (52 * out) + (26 + (in));
 642         }
 643 }
 644
 645 static inline int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
 646 {
 647         switch (hdsp->firmware_rev) {
 648         case 0xa:
 649                 return (64 * out) + in;
 650         case 0x96:
 651         case 0x97:
 652                 return (32 * out) + in;
 653         default:
 654                 return (52 * out) + in;
 655         }
 656 }
 657
 658 static inline void hdsp_write(hdsp_t *hdsp, int reg, int val)
 659 {
 660         writel(val, hdsp->iobase + reg);
 661 }
 662
 663 static inline unsigned int hdsp_read(hdsp_t *hdsp, int reg)
 664 {
 665         return readl (hdsp->iobase + reg);
 666 }
 667
 668 static inline int hdsp_check_for_iobox (hdsp_t *hdsp)
 669 {
 670
 671         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 672         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
 673                 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
 674                 hdsp->state &= ~HDSP_FirmwareLoaded;
 675                 return -EIO;
 676         }
 677         return 0;
 678
 679 }
 680
 681 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
 682
 683         int i;
 684         unsigned long flags;
 685
 686         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 687
 688                 snd_printk ("loading firmware\n");
 689
 690                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 691                 hdsp_write (hdsp, HDSP_fifoData, 0);
 692
 693                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 694                         snd_printk ("timeout waiting for download preparation\n");
 695                         return -EIO;
 696                 }
 697
 698                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 699
 700                 for (i = 0; i < 24413; ++i) {
 701                         hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
 702                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 703                                 snd_printk ("timeout during firmware loading\n");
 704                                 return -EIO;
 705                         }
 706                 }
 707
 708                 if ((1000 / HZ) < 3000) {
 709                         set_current_state(TASK_UNINTERRUPTIBLE);
 710                         schedule_timeout((3000 * HZ + 999) / 1000);
 711                 } else {
 712                         mdelay(3000);
 713                 }
 714
 715                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 716                         snd_printk ("timeout at end of firmware loading\n");
 717                         return -EIO;
 718                 }
 719
 720 #ifdef SNDRV_BIG_ENDIAN
 721                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 722 #else
 723                 hdsp->control2_register = 0;
 724 #endif
 725                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 726                 snd_printk ("finished firmware loading\n");
 727
 728         }
 729         if (hdsp->state & HDSP_InitializationComplete) {
 730                 snd_printk("firmware loaded from cache, restoring defaults\n");
 731                 spin_lock_irqsave(&hdsp->lock, flags);
 732                 snd_hdsp_set_defaults(hdsp);
 733                 spin_unlock_irqrestore(&hdsp->lock, flags);
 734         }
 735
 736         hdsp->state |= HDSP_FirmwareLoaded;
 737
 738         return 0;
 739 }
 740
 741 static inline int hdsp_get_iobox_version (hdsp_t *hdsp)
 742 {
 743         int err;
 744
 745         if (hdsp_check_for_iobox (hdsp)) {
 746                 return -EIO;
 747         }
 748
 749         if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
 750                 return err;
 751         }
 752
 753         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 754
 755                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
 756                 hdsp_write (hdsp, HDSP_fifoData, 0);
 757                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 758                         return -EIO;
 759                 }
 760
 761                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 762                 hdsp_write (hdsp, HDSP_fifoData, 0);
 763
 764                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
 765                         hdsp->io_type = Multiface;
 766                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
 767                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 768                         hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
 769                 } else {
 770                         hdsp->io_type = Digiface;
 771                 }
 772         } else {
 773                 /* firmware was already loaded, get iobox type */
 774                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
 775                         hdsp->io_type = Multiface;
 776                 } else {
 777                         hdsp->io_type = Digiface;
 778                 }
 779         }
 780         return 0;
 781 }
 782
 783
 784 static inline int hdsp_check_for_firmware (hdsp_t *hdsp)
 785 {
 786         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 787         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 788                 snd_printk("firmware not present.\n");
 789                 hdsp->state &= ~HDSP_FirmwareLoaded;
 790                 return -EIO;
 791         }
 792         return 0;
 793 }
 794
 795
 796 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
 797 {
 798         int i;
 799
 800         /* the fifoStatus registers reports on how many words
 801            are available in the command FIFO.
 802         */
 803
 804         for (i = 0; i < timeout; i++) {
 805
 806                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 807                         return 0;
 808
 809                 /* not very friendly, but we only do this during a firmware
 810                    load and changing the mixer, so we just put up with it.
 811                 */
 812
 813                 udelay (100);
 814         }
 815
 816         snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
 817                     count, timeout);
 818         return -1;
 819 }
 820
 821 static inline int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
 822 {
 823         if (addr >= HDSP_MATRIX_MIXER_SIZE) {
 824                 return 0;
 825         }
 826         return hdsp->mixer_matrix[addr];
 827 }
 828
 829 static inline int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
 830 {
 831         unsigned int ad;
 832
 833         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 834                 return -1;
 835
 836         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 837
 838                 /* from martin björnsen:
 839
 840                    "You can only write dwords to the
 841                    mixer memory which contain two
 842                    mixer values in the low and high
 843                    word. So if you want to change
 844                    value 0 you have to read value 1
 845                    from the cache and write both to
 846                    the first dword in the mixer
 847                    memory."
 848                 */
 849
 850                 if (hdsp->io_type == H9632 && addr >= 512) {
 851                         return 0;
 852                 }
 853
 854                 if (hdsp->io_type == H9652 && addr >= 1352) {
 855                         return 0;
 856                 }
 857
 858                 hdsp->mixer_matrix[addr] = data;
 859
 860
 861                 /* `addr' addresses a 16-bit wide address, but
 862                    the address space accessed via hdsp_write
 863                    uses byte offsets. put another way, addr
 864                    varies from 0 to 1351, but to access the
 865                    corresponding memory location, we need
 866                    to access 0 to 2703 ...
 867                 */
 868                 ad = addr/2;
 869
 870                 hdsp_write (hdsp, 4096 + (ad*4),
 871                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 872                             hdsp->mixer_matrix[addr&0x7fe]);
 873
 874                 return 0;
 875
 876         } else {
 877
 878                 ad = (addr << 16) + data;
 879
 880                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
 881                         return -1;
 882                 }
 883
 884                 hdsp_write (hdsp, HDSP_fifoData, ad);
 885                 hdsp->mixer_matrix[addr] = data;
 886
 887         }
 888
 889         return 0;
 890 }
 891
 892 static inline int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
 893 {
 894         unsigned long flags;
 895         int ret = 1;
 896
 897         spin_lock_irqsave(&hdsp->lock, flags);
 898         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 899             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
 900                 ret = 0;
 901         }
 902         spin_unlock_irqrestore(&hdsp->lock, flags);
 903         return ret;
 904 }
 905
 906 static inline int hdsp_external_sample_rate (hdsp_t *hdsp)
 907 {
 908         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 909         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 910
 911         switch (rate_bits) {
 912         case HDSP_systemFrequency32:   return 32000;
 913         case HDSP_systemFrequency44_1: return 44100;
 914         case HDSP_systemFrequency48:   return 48000;
 915         case HDSP_systemFrequency64:   return 64000;
 916         case HDSP_systemFrequency88_2: return 88200;
 917         case HDSP_systemFrequency96:   return 96000;
 918         default:
 919                 return 0;
 920         }
 921 }
 922
 923 static inline int hdsp_spdif_sample_rate(hdsp_t *hdsp)
 924 {
 925         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 926         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 927
 928         if (status & HDSP_SPDIFErrorFlag) {
 929                 return 0;
 930         }
 931
 932         switch (rate_bits) {
 933         case HDSP_spdifFrequency32KHz: return 32000;
 934         case HDSP_spdifFrequency44_1KHz: return 44100;
 935         case HDSP_spdifFrequency48KHz: return 48000;
 936         case HDSP_spdifFrequency64KHz: return 64000;
 937         case HDSP_spdifFrequency88_2KHz: return 88200;
 938         case HDSP_spdifFrequency96KHz: return 96000;
 939         case HDSP_spdifFrequency128KHz:
 940                 if (hdsp->io_type == H9632) return 128000;
 941                 break;
 942         case HDSP_spdifFrequency176_4KHz:
 943                 if (hdsp->io_type == H9632) return 176400;
 944                 break;
 945         case HDSP_spdifFrequency192KHz:
 946                 if (hdsp->io_type == H9632) return 192000;
 947                 break;
 948         default:
 949                 break;
 950         }
 951         snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
 952         return 0;
 953 }
 954
 955 static inline void hdsp_compute_period_size(hdsp_t *hdsp)
 956 {
 957         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
 958 }
 959
 960 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
 961 {
 962         int position;
 963
 964         position = hdsp_read(hdsp, HDSP_statusRegister);
 965
 966         if (!hdsp->precise_ptr) {
 967                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
 968         }
 969
 970         position &= HDSP_BufferPositionMask;
 971         position /= 4;
 972         position -= 32;
 973         position &= (HDSP_CHANNEL_BUFFER_SAMPLES-1);
 974         return position;
 975 }
 976
 977 static inline void hdsp_reset_hw_pointer(hdsp_t *hdsp)
 978 {
 979         hdsp_write (hdsp, HDSP_resetPointer, 0);
 980 }
 981
 982 static inline void hdsp_start_audio(hdsp_t *s)
 983 {
 984         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
 985         hdsp_write(s, HDSP_controlRegister, s->control_register);
 986 }
 987
 988 static inline void hdsp_stop_audio(hdsp_t *s)
 989 {
 990         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
 991         hdsp_write(s, HDSP_controlRegister, s->control_register);
 992 }
 993
 994 static inline void hdsp_silence_playback(hdsp_t *hdsp)
 995 {
 996         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
 997 }
 998
 999 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
1000 {
1001         int n;
1002
1003         spin_lock_irq(&s->lock);
1004
1005         frames >>= 7;
1006         n = 0;
1007         while (frames) {
1008                 n++;
1009                 frames >>= 1;
1010         }
1011
1012         s->control_register &= ~HDSP_LatencyMask;
1013         s->control_register |= hdsp_encode_latency(n);
1014
1015         hdsp_write(s, HDSP_controlRegister, s->control_register);
1016
1017         hdsp_compute_period_size(s);
1018
1019         spin_unlock_irq(&s->lock);
1020
1021         return 0;
1022 }
1023
1024 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
1025 {
1026         int reject_if_open = 0;
1027         int current_rate;
1028         int rate_bits;
1029
1030         /* ASSUMPTION: hdsp->lock is either held, or
1031            there is no need for it (e.g. during module
1032            initialization).
1033         */
1034
1035         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1036                 if (called_internally) {
1037                         /* request from ctl or card initialization */
1038                         snd_printk("device is not running as a clock master: cannot set sample rate.\n");
1039                         return -1;
1040                 } else {
1041                         /* hw_param request while in AutoSync mode */
1042                         int external_freq = hdsp_external_sample_rate(hdsp);
1043                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1044
1045                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1046                                 snd_printk("Detected ADAT in double speed mode\n");
1047                         } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1048                                 snd_printk("Detected ADAT in quad speed mode\n");
1049                         } else if (rate != external_freq) {
1050                                 snd_printk("No AutoSync source for requested rate\n");
1051                                 return -1;
1052                         }
1053                 }
1054         }
1055
1056         current_rate = hdsp->system_sample_rate;
1057
1058         /* Changing from a "single speed" to a "double speed" rate is
1059            not allowed if any substreams are open. This is because
1060            such a change causes a shift in the location of
1061            the DMA buffers and a reduction in the number of available
1062            buffers.
1063
1064            Note that a similar but essentially insoluble problem
1065            exists for externally-driven rate changes. All we can do
1066            is to flag rate changes in the read/write routines.  */
1067
1068         if (rate > 96000 && hdsp->io_type != H9632) {
1069                 return -EINVAL;
1070         }
1071
1072         switch (rate) {
1073         case 32000:
1074                 if (current_rate > 48000) {
1075                         reject_if_open = 1;
1076                 }
1077                 rate_bits = HDSP_Frequency32KHz;
1078                 break;
1079         case 44100:
1080                 if (current_rate > 48000) {
1081                         reject_if_open = 1;
1082                 }
1083                 rate_bits = HDSP_Frequency44_1KHz;
1084                 break;
1085         case 48000:
1086                 if (current_rate > 48000) {
1087                         reject_if_open = 1;
1088                 }
1089                 rate_bits = HDSP_Frequency48KHz;
1090                 break;
1091         case 64000:
1092                 if (current_rate <= 48000 || current_rate > 96000) {
1093                         reject_if_open = 1;
1094                 }
1095                 rate_bits = HDSP_Frequency64KHz;
1096                 break;
1097         case 88200:
1098                 if (current_rate <= 48000 || current_rate > 96000) {
1099                         reject_if_open = 1;
1100                 }
1101                 rate_bits = HDSP_Frequency88_2KHz;
1102                 break;
1103         case 96000:
1104                 if (current_rate <= 48000 || current_rate > 96000) {
1105                         reject_if_open = 1;
1106                 }
1107                 rate_bits = HDSP_Frequency96KHz;
1108                 break;
1109         case 128000:
1110                 if (current_rate < 128000) {
1111                         reject_if_open = 1;
1112                 }
1113                 rate_bits = HDSP_Frequency128KHz;
1114                 break;
1115         case 176400:
1116                 if (current_rate < 128000) {
1117                         reject_if_open = 1;
1118                 }
1119                 rate_bits = HDSP_Frequency176_4KHz;
1120                 break;
1121         case 192000:
1122                 if (current_rate < 128000) {
1123                         reject_if_open = 1;
1124                 }
1125                 rate_bits = HDSP_Frequency192KHz;
1126                 break;
1127         default:
1128                 return -EINVAL;
1129         }
1130
1131         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1132                 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1133                             hdsp->capture_pid,
1134                             hdsp->playback_pid);
1135                 return -EBUSY;
1136         }
1137
1138         hdsp->control_register &= ~HDSP_FrequencyMask;
1139         hdsp->control_register |= rate_bits;
1140         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1141
1142         if (rate >= 128000) {
1143                 hdsp->channel_map = channel_map_H9632_qs;
1144         } else if (rate > 48000) {
1145                 if (hdsp->io_type == H9632) {
1146                         hdsp->channel_map = channel_map_H9632_ds;
1147                 } else {
1148                         hdsp->channel_map = channel_map_ds;
1149                 }
1150         } else {
1151                 switch (hdsp->io_type) {
1152                 case Multiface:
1153                         hdsp->channel_map = channel_map_mf_ss;
1154                         break;
1155                 case Digiface:
1156                 case H9652:
1157                         hdsp->channel_map = channel_map_df_ss;
1158                         break;
1159                 case H9632:
1160                         hdsp->channel_map = channel_map_H9632_ss;
1161                         break;
1162                 default:
1163                         /* should never happen */
1164                         break;
1165                 }
1166         }
1167
1168         hdsp->system_sample_rate = rate;
1169
1170         return 0;
1171 }
1172
1173 static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
1174 {
1175
1176         hdsp->passthru = 0;
1177
1178         if (channel < 0) {
1179
1180                 int i;
1181
1182                 /* set thru for all channels */
1183
1184                 if (enable) {
1185                         for (i = 0; i < hdsp->max_channels; i++) {
1186                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN);
1187                         }
1188                 } else {
1189                         for (i = 0; i < hdsp->max_channels; i++) {
1190                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN);
1191                         }
1192                 }
1193
1194         } else {
1195                 int mapped_channel;
1196
1197                 snd_assert(channel < hdsp->max_channels, return);
1198
1199                 mapped_channel = hdsp->channel_map[channel];
1200
1201                 snd_assert(mapped_channel > -1, return);
1202
1203                 if (enable) {
1204                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN);
1205                 } else {
1206                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN);
1207                 }
1208         }
1209 }
1210
1211 static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
1212 {
1213         if (onoff) {
1214                 hdsp_set_thru(hdsp, -1, 1);
1215                 hdsp_reset_hw_pointer(hdsp);
1216                 hdsp_silence_playback(hdsp);
1217
1218                 /* we don't want interrupts, so do a
1219                    custom version of hdsp_start_audio().
1220                 */
1221
1222                 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
1223
1224                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1225                 hdsp->passthru = 1;
1226         } else {
1227                 hdsp_set_thru(hdsp, -1, 0);
1228                 hdsp_stop_audio(hdsp);
1229                 hdsp->passthru = 0;
1230         }
1231
1232         return 0;
1233 }
1234
1235 /*----------------------------------------------------------------------------
1236    MIDI
1237   ----------------------------------------------------------------------------*/
1238
1239 static inline unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1240 {
1241         /* the hardware already does the relevant bit-mask with 0xff */
1242         if (id) {
1243                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1244         } else {
1245                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1246         }
1247 }
1248
1249 static inline void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1250 {
1251         /* the hardware already does the relevant bit-mask with 0xff */
1252         if (id) {
1253                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1254         } else {
1255                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1256         }
1257 }
1258
1259 static inline int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1260 {
1261         if (id) {
1262                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1263         } else {
1264                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1265         }
1266 }
1267
1268 static inline int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1269 {
1270         int fifo_bytes_used;
1271
1272         if (id) {
1273                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1274         } else {
1275                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1276         }
1277
1278         if (fifo_bytes_used < 128) {
1279                 return  128 - fifo_bytes_used;
1280         } else {
1281                 return 0;
1282         }
1283 }
1284
1285 static inline void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1286 {
1287         while (snd_hdsp_midi_input_available (hdsp, id)) {
1288                 snd_hdsp_midi_read_byte (hdsp, id);
1289         }
1290 }
1291
1292 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1293 {
1294         unsigned long flags;
1295         int n_pending;
1296         int to_write;
1297         int i;
1298         unsigned char buf[128];
1299
1300         /* Output is not interrupt driven */
1301
1302         spin_lock_irqsave (&hmidi->lock, flags);
1303         if (hmidi->output) {
1304                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1305                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1306                                 if (n_pending > (int)sizeof (buf))
1307                                         n_pending = sizeof (buf);
1308
1309                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1310                                         for (i = 0; i < to_write; ++i)
1311                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1312                                 }
1313                         }
1314                 }
1315         }
1316         spin_unlock_irqrestore (&hmidi->lock, flags);
1317         return 0;
1318 }
1319
1320 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1321 {
1322         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1323         unsigned long flags;
1324         int n_pending;
1325         int i;
1326
1327         spin_lock_irqsave (&hmidi->lock, flags);
1328         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1329                 if (hmidi->input) {
1330                         if (n_pending > (int)sizeof (buf)) {
1331                                 n_pending = sizeof (buf);
1332                         }
1333                         for (i = 0; i < n_pending; ++i) {
1334                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1335                         }
1336                         if (n_pending) {
1337                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1338                         }
1339                 } else {
1340                         /* flush the MIDI input FIFO */
1341                         while (--n_pending) {
1342                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1343                         }
1344                 }
1345         }
1346         hmidi->pending = 0;
1347         if (hmidi->id) {
1348                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1349         } else {
1350                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1351         }
1352         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1353         spin_unlock_irqrestore (&hmidi->lock, flags);
1354         return snd_hdsp_midi_output_write (hmidi);
1355 }
1356
1357 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1358 {
1359         hdsp_t *hdsp;
1360         hdsp_midi_t *hmidi;
1361         unsigned long flags;
1362         u32 ie;
1363
1364         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1365         hdsp = hmidi->hdsp;
1366         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1367         spin_lock_irqsave (&hdsp->lock, flags);
1368         if (up) {
1369                 if (!(hdsp->control_register & ie)) {
1370                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1371                         hdsp->control_register |= ie;
1372                 }
1373         } else {
1374                 hdsp->control_register &= ~ie;
1375         }
1376
1377         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1378         spin_unlock_irqrestore (&hdsp->lock, flags);
1379 }
1380
1381 static void snd_hdsp_midi_output_timer(unsigned long data)
1382 {
1383         hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1384         unsigned long flags;
1385
1386         snd_hdsp_midi_output_write(hmidi);
1387         spin_lock_irqsave (&hmidi->lock, flags);
1388
1389         /* this does not bump hmidi->istimer, because the
1390            kernel automatically removed the timer when it
1391            expired, and we are now adding it back, thus
1392            leaving istimer wherever it was set before.
1393         */
1394
1395         if (hmidi->istimer) {
1396                 hmidi->timer.expires = 1 + jiffies;
1397                 add_timer(&hmidi->timer);
1398         }
1399
1400         spin_unlock_irqrestore (&hmidi->lock, flags);
1401 }
1402
1403 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1404 {
1405         hdsp_midi_t *hmidi;
1406         unsigned long flags;
1407
1408         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1409         spin_lock_irqsave (&hmidi->lock, flags);
1410         if (up) {
1411                 if (!hmidi->istimer) {
1412                         init_timer(&hmidi->timer);
1413                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1414                         hmidi->timer.data = (unsigned long) hmidi;
1415                         hmidi->timer.expires = 1 + jiffies;
1416                         add_timer(&hmidi->timer);
1417                         hmidi->istimer++;
1418                 }
1419         } else {
1420                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1421                         del_timer (&hmidi->timer);
1422                 }
1423         }
1424         spin_unlock_irqrestore (&hmidi->lock, flags);
1425         if (up)
1426                 snd_hdsp_midi_output_write(hmidi);
1427 }
1428
1429 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1430 {
1431         hdsp_midi_t *hmidi;
1432         unsigned long flags;
1433
1434         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1435         spin_lock_irqsave (&hmidi->lock, flags);
1436         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1437         hmidi->input = substream;
1438         spin_unlock_irqrestore (&hmidi->lock, flags);
1439
1440         return 0;
1441 }
1442
1443 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1444 {
1445         hdsp_midi_t *hmidi;
1446         unsigned long flags;
1447
1448         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1449         spin_lock_irqsave (&hmidi->lock, flags);
1450         hmidi->output = substream;
1451         spin_unlock_irqrestore (&hmidi->lock, flags);
1452
1453         return 0;
1454 }
1455
1456 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1457 {
1458         hdsp_midi_t *hmidi;
1459         unsigned long flags;
1460
1461         snd_hdsp_midi_input_trigger (substream, 0);
1462
1463         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1464         spin_lock_irqsave (&hmidi->lock, flags);
1465         hmidi->input = NULL;
1466         spin_unlock_irqrestore (&hmidi->lock, flags);
1467
1468         return 0;
1469 }
1470
1471 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1472 {
1473         hdsp_midi_t *hmidi;
1474         unsigned long flags;
1475
1476         snd_hdsp_midi_output_trigger (substream, 0);
1477
1478         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1479         spin_lock_irqsave (&hmidi->lock, flags);
1480         hmidi->output = NULL;
1481         spin_unlock_irqrestore (&hmidi->lock, flags);
1482
1483         return 0;
1484 }
1485
1486 snd_rawmidi_ops_t snd_hdsp_midi_output =
1487 {
1488         .open =         snd_hdsp_midi_output_open,
1489         .close =        snd_hdsp_midi_output_close,
1490         .trigger =      snd_hdsp_midi_output_trigger,
1491 };
1492
1493 snd_rawmidi_ops_t snd_hdsp_midi_input =
1494 {
1495         .open =         snd_hdsp_midi_input_open,
1496         .close =        snd_hdsp_midi_input_close,
1497         .trigger =      snd_hdsp_midi_input_trigger,
1498 };
1499
1500 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1501 {
1502         char buf[32];
1503
1504         hdsp->midi[id].id = id;
1505         hdsp->midi[id].rmidi = NULL;
1506         hdsp->midi[id].input = NULL;
1507         hdsp->midi[id].output = NULL;
1508         hdsp->midi[id].hdsp = hdsp;
1509         hdsp->midi[id].istimer = 0;
1510         hdsp->midi[id].pending = 0;
1511         spin_lock_init (&hdsp->midi[id].lock);
1512
1513         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1514         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1515                 return -1;
1516         }
1517
1518         sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1519         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1520
1521         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1522         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1523
1524         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1525                 SNDRV_RAWMIDI_INFO_INPUT |
1526                 SNDRV_RAWMIDI_INFO_DUPLEX;
1527
1528         return 0;
1529 }
1530
1531 /*-----------------------------------------------------------------------------
1532   Control Interface
1533   ----------------------------------------------------------------------------*/
1534
1535 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1536 {
1537         u32 val = 0;
1538         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1539         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1540         if (val & HDSP_SPDIFProfessional)
1541                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1542         else
1543                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1544         return val;
1545 }
1546
1547 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1548 {
1549         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1550                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1551         if (val & HDSP_SPDIFProfessional)
1552                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1553         else
1554                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1555 }
1556
1557 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1558 {
1559         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1560         uinfo->count = 1;
1561         return 0;
1562 }
1563
1564 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1565 {
1566         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1567
1568         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1569         return 0;
1570 }
1571
1572 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1573 {
1574         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1575         unsigned long flags;
1576         int change;
1577         u32 val;
1578
1579         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1580         spin_lock_irqsave(&hdsp->lock, flags);
1581         change = val != hdsp->creg_spdif;
1582         hdsp->creg_spdif = val;
1583         spin_unlock_irqrestore(&hdsp->lock, flags);
1584         return change;
1585 }
1586
1587 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1588 {
1589         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1590         uinfo->count = 1;
1591         return 0;
1592 }
1593
1594 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1595 {
1596         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1597
1598         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1599         return 0;
1600 }
1601
1602 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1603 {
1604         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1605         unsigned long flags;
1606         int change;
1607         u32 val;
1608
1609         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1610         spin_lock_irqsave(&hdsp->lock, flags);
1611         change = val != hdsp->creg_spdif_stream;
1612         hdsp->creg_spdif_stream = val;
1613         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1614         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1615         spin_unlock_irqrestore(&hdsp->lock, flags);
1616         return change;
1617 }
1618
1619 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1620 {
1621         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1622         uinfo->count = 1;
1623         return 0;
1624 }
1625
1626 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1627 {
1628         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1629         return 0;
1630 }
1631
1632 #define HDSP_SPDIF_IN(xname, xindex) \
1633 { .iface = SNDRV_CTL_ELEM_IFACE_PCM,  \
1634   .name = xname, \
1635   .index = xindex, \
1636   .info = snd_hdsp_info_spdif_in, \
1637   .get = snd_hdsp_get_spdif_in, \
1638   .put = snd_hdsp_put_spdif_in }
1639
1640 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1641 {
1642         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1643 }
1644
1645 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1646 {
1647         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1648         hdsp->control_register |= hdsp_encode_spdif_in(in);
1649         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1650         return 0;
1651 }
1652
1653 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1654 {
1655         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1656         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1657
1658         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1659         uinfo->count = 1;
1660         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1661         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1662                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1663         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1664         return 0;
1665 }
1666
1667 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1668 {
1669         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1670
1671         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1672         return 0;
1673 }
1674
1675 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1676 {
1677         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1678         unsigned long flags;
1679         int change;
1680         unsigned int val;
1681
1682         if (!snd_hdsp_use_is_exclusive(hdsp))
1683                 return -EBUSY;
1684         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1685         spin_lock_irqsave(&hdsp->lock, flags);
1686         change = val != hdsp_spdif_in(hdsp);
1687         if (change)
1688                 hdsp_set_spdif_input(hdsp, val);
1689         spin_unlock_irqrestore(&hdsp->lock, flags);
1690         return change;
1691 }
1692
1693 #define HDSP_SPDIF_OUT(xname, xindex) \
1694 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1695   .info = snd_hdsp_info_spdif_bits, \
1696   .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1697
1698 static int hdsp_spdif_out(hdsp_t *hdsp)
1699 {
1700         return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1701 }
1702
1703 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1704 {
1705         if (out) {
1706                 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1707         } else {
1708                 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1709         }
1710         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1711         return 0;
1712 }
1713
1714 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1715 {
1716         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1717         uinfo->count = 1;
1718         uinfo->value.integer.min = 0;
1719         uinfo->value.integer.max = 1;
1720         return 0;
1721 }
1722
1723 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1724 {
1725         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1726
1727         ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1728         return 0;
1729 }
1730
1731 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1732 {
1733         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1734         unsigned long flags;
1735         int change;
1736         unsigned int val;
1737
1738         if (!snd_hdsp_use_is_exclusive(hdsp))
1739                 return -EBUSY;
1740         val = ucontrol->value.integer.value[0] & 1;
1741         spin_lock_irqsave(&hdsp->lock, flags);
1742         change = (int)val != hdsp_spdif_out(hdsp);
1743         hdsp_set_spdif_output(hdsp, val);
1744         spin_unlock_irqrestore(&hdsp->lock, flags);
1745         return change;
1746 }
1747
1748 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1749 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1750   .info = snd_hdsp_info_spdif_bits, \
1751   .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1752
1753 static int hdsp_spdif_professional(hdsp_t *hdsp)
1754 {
1755         return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1756 }
1757
1758 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1759 {
1760         if (val) {
1761                 hdsp->control_register |= HDSP_SPDIFProfessional;
1762         } else {
1763                 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1764         }
1765         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1766         return 0;
1767 }
1768
1769 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1770 {
1771         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1772
1773         ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1774         return 0;
1775 }
1776
1777 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1778 {
1779         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1780         unsigned long flags;
1781         int change;
1782         unsigned int val;
1783
1784         if (!snd_hdsp_use_is_exclusive(hdsp))
1785                 return -EBUSY;
1786         val = ucontrol->value.integer.value[0] & 1;
1787         spin_lock_irqsave(&hdsp->lock, flags);
1788         change = (int)val != hdsp_spdif_professional(hdsp);
1789         hdsp_set_spdif_professional(hdsp, val);
1790         spin_unlock_irqrestore(&hdsp->lock, flags);
1791         return change;
1792 }
1793
1794 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1795 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1796   .info = snd_hdsp_info_spdif_bits, \
1797   .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1798
1799 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1800 {
1801         return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1802 }
1803
1804 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1805 {
1806         if (val) {
1807                 hdsp->control_register |= HDSP_SPDIFEmphasis;
1808         } else {
1809                 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1810         }
1811         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1812         return 0;
1813 }
1814
1815 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1816 {
1817         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1818
1819         ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1820         return 0;
1821 }
1822
1823 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1824 {
1825         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1826         unsigned long flags;
1827         int change;
1828         unsigned int val;
1829
1830         if (!snd_hdsp_use_is_exclusive(hdsp))
1831                 return -EBUSY;
1832         val = ucontrol->value.integer.value[0] & 1;
1833         spin_lock_irqsave(&hdsp->lock, flags);
1834         change = (int)val != hdsp_spdif_emphasis(hdsp);
1835         hdsp_set_spdif_emphasis(hdsp, val);
1836         spin_unlock_irqrestore(&hdsp->lock, flags);
1837         return change;
1838 }
1839
1840 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1841 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1842   .info = snd_hdsp_info_spdif_bits, \
1843   .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1844
1845 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1846 {
1847         return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1848 }
1849
1850 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1851 {
1852         if (val) {
1853                 hdsp->control_register |= HDSP_SPDIFNonAudio;
1854         } else {
1855                 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1856         }
1857         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1858         return 0;
1859 }
1860
1861 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1862 {
1863         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1864
1865         ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1866         return 0;
1867 }
1868
1869 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1870 {
1871         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1872         unsigned long flags;
1873         int change;
1874         unsigned int val;
1875
1876         if (!snd_hdsp_use_is_exclusive(hdsp))
1877                 return -EBUSY;
1878         val = ucontrol->value.integer.value[0] & 1;
1879         spin_lock_irqsave(&hdsp->lock, flags);
1880         change = (int)val != hdsp_spdif_nonaudio(hdsp);
1881         hdsp_set_spdif_nonaudio(hdsp, val);
1882         spin_unlock_irqrestore(&hdsp->lock, flags);
1883         return change;
1884 }
1885
1886 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1887 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1888   .name = xname, \
1889   .index = xindex, \
1890   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1891   .info = snd_hdsp_info_spdif_sample_rate, \
1892   .get = snd_hdsp_get_spdif_sample_rate \
1893 }
1894
1895 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1896 {
1897         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1898         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1899
1900         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1901         uinfo->count = 1;
1902         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1903         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1904                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1905         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1906         return 0;
1907 }
1908
1909 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1910 {
1911         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1912
1913         switch (hdsp_spdif_sample_rate(hdsp)) {
1914         case 32000:
1915                 ucontrol->value.enumerated.item[0] = 0;
1916                 break;
1917         case 44100:
1918                 ucontrol->value.enumerated.item[0] = 1;
1919                 break;
1920         case 48000:
1921                 ucontrol->value.enumerated.item[0] = 2;
1922                 break;
1923         case 64000:
1924                 ucontrol->value.enumerated.item[0] = 3;
1925                 break;
1926         case 88200:
1927                 ucontrol->value.enumerated.item[0] = 4;
1928                 break;
1929         case 96000:
1930                 ucontrol->value.enumerated.item[0] = 5;
1931                 break;
1932         case 128000:
1933                 ucontrol->value.enumerated.item[0] = 7;
1934                 break;
1935         case 176400:
1936                 ucontrol->value.enumerated.item[0] = 8;
1937                 break;
1938         case 192000:
1939                 ucontrol->value.enumerated.item[0] = 9;
1940                 break;
1941         default:
1942                 ucontrol->value.enumerated.item[0] = 6;
1943         }
1944         return 0;
1945 }
1946
1947 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1948 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1949   .name = xname, \
1950   .index = xindex, \
1951   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1952   .info = snd_hdsp_info_system_sample_rate, \
1953   .get = snd_hdsp_get_system_sample_rate \
1954 }
1955
1956 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1957 {
1958         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1959         uinfo->count = 1;
1960         return 0;
1961 }
1962
1963 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1964 {
1965         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1966
1967         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1968         return 0;
1969 }
1970
1971 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1972 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1973   .name = xname, \
1974   .index = xindex, \
1975   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1976   .info = snd_hdsp_info_autosync_sample_rate, \
1977   .get = snd_hdsp_get_autosync_sample_rate \
1978 }
1979
1980 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1981 {
1982         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1983         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1984         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1985         uinfo->count = 1;
1986         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1987         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1988                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1989         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1990         return 0;
1991 }
1992
1993 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1994 {
1995         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1996
1997         switch (hdsp_external_sample_rate(hdsp)) {
1998         case 32000:
1999                 ucontrol->value.enumerated.item[0] = 0;
2000                 break;
2001         case 44100:
2002                 ucontrol->value.enumerated.item[0] = 1;
2003                 break;
2004         case 48000:
2005                 ucontrol->value.enumerated.item[0] = 2;
2006                 break;
2007         case 64000:
2008                 ucontrol->value.enumerated.item[0] = 3;
2009                 break;
2010         case 88200:
2011                 ucontrol->value.enumerated.item[0] = 4;
2012                 break;
2013         case 96000:
2014                 ucontrol->value.enumerated.item[0] = 5;
2015                 break;
2016         case 128000:
2017                 ucontrol->value.enumerated.item[0] = 7;
2018                 break;
2019         case 176400:
2020                 ucontrol->value.enumerated.item[0] = 8;
2021                 break;
2022         case 192000:
2023                 ucontrol->value.enumerated.item[0] = 9;
2024                 break;
2025         default:
2026                 ucontrol->value.enumerated.item[0] = 6;
2027         }
2028         return 0;
2029 }
2030
2031 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
2032 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2033   .name = xname, \
2034   .index = xindex, \
2035   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2036   .info = snd_hdsp_info_system_clock_mode, \
2037   .get = snd_hdsp_get_system_clock_mode \
2038 }
2039
2040 static int hdsp_system_clock_mode(hdsp_t *hdsp)
2041 {
2042         if (hdsp->control_register & HDSP_ClockModeMaster) {
2043                 return 0;
2044         } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
2045                         return 0;
2046         }
2047         return 1;
2048 }
2049
2050 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2051 {
2052         static char *texts[] = {"Master", "Slave" };
2053
2054         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2055         uinfo->count = 1;
2056         uinfo->value.enumerated.items = 2;
2057         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2058                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2059         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2060         return 0;
2061 }
2062
2063 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2064 {
2065         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2066
2067         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2068         return 0;
2069 }
2070
2071 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2072 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
2073   .name = xname, \
2074   .index = xindex, \
2075   .info = snd_hdsp_info_clock_source, \
2076   .get = snd_hdsp_get_clock_source, \
2077   .put = snd_hdsp_put_clock_source \
2078 }
2079
2080 static int hdsp_clock_source(hdsp_t *hdsp)
2081 {
2082         if (hdsp->control_register & HDSP_ClockModeMaster) {
2083                 switch (hdsp->system_sample_rate) {
2084                 case 32000:
2085                         return 1;
2086                 case 44100:
2087                         return 2;
2088                 case 48000:
2089                         return 3;
2090                 case 64000:
2091                         return 4;
2092                 case 88200:
2093                         return 5;
2094                 case 96000:
2095                         return 6;
2096                 case 128000:
2097                         return 7;
2098                 case 176400:
2099                         return 8;
2100                 case 192000:
2101                         return 9;
2102                 default:
2103                         return 3;
2104                 }
2105         } else {
2106                 return 0;
2107         }
2108 }
2109
2110 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2111 {
2112         int rate;
2113         switch (mode) {
2114         case HDSP_CLOCK_SOURCE_AUTOSYNC:
2115                 if (hdsp_external_sample_rate(hdsp) != 0) {
2116                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2117                         hdsp->control_register &= ~HDSP_ClockModeMaster;
2118                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2119                         return 0;
2120                     }
2121                 }
2122                 return -1;
2123         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2124                 rate = 32000;
2125                 break;
2126         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2127                 rate = 44100;
2128                 break;
2129         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2130                 rate = 48000;
2131                 break;
2132         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2133                 rate = 64000;
2134                 break;
2135         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2136                 rate = 88200;
2137                 break;
2138         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2139                 rate = 96000;
2140                 break;
2141         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2142                 rate = 128000;
2143                 break;
2144         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2145                 rate = 176400;
2146                 break;
2147         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2148                 rate = 192000;
2149                 break;
2150         default:
2151                 rate = 48000;
2152         }
2153         hdsp->control_register |= HDSP_ClockModeMaster;
2154         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2155         hdsp_set_rate(hdsp, rate, 1);
2156         return 0;
2157 }
2158
2159 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2160 {
2161         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2162         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2163
2164         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2165         uinfo->count = 1;
2166         if (hdsp->io_type == H9632)
2167             uinfo->value.enumerated.items = 10;
2168         else
2169             uinfo->value.enumerated.items = 7;
2170         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2171                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2172         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2173         return 0;
2174 }
2175
2176 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2177 {
2178         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2179
2180         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2181         return 0;
2182 }
2183
2184 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2185 {
2186         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2187         unsigned long flags;
2188         int change;
2189         int val;
2190
2191         if (!snd_hdsp_use_is_exclusive(hdsp))
2192                 return -EBUSY;
2193         val = ucontrol->value.enumerated.item[0];
2194         if (val < 0) val = 0;
2195         if (hdsp->io_type == H9632) {
2196             if (val > 9) val = 9;
2197         } else {
2198             if (val > 6) val = 6;
2199         }
2200         spin_lock_irqsave(&hdsp->lock, flags);
2201         if (val != hdsp_clock_source(hdsp)) {
2202                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2203         } else {
2204                 change = 0;
2205         }
2206         spin_unlock_irqrestore(&hdsp->lock, flags);
2207         return change;
2208 }
2209
2210 #define HDSP_DA_GAIN(xname, xindex) \
2211 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2212   .name = xname, \
2213   .index = xindex, \
2214   .info = snd_hdsp_info_da_gain, \
2215   .get = snd_hdsp_get_da_gain, \
2216   .put = snd_hdsp_put_da_gain \
2217 }
2218
2219 static int hdsp_da_gain(hdsp_t *hdsp)
2220 {
2221         switch (hdsp->control_register & HDSP_DAGainMask) {
2222         case HDSP_DAGainHighGain:
2223                 return 0;
2224         case HDSP_DAGainPlus4dBu:
2225                 return 1;
2226         case HDSP_DAGainMinus10dBV:
2227                 return 2;
2228         default:
2229                 return 1;
2230         }
2231 }
2232
2233 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2234 {
2235         hdsp->control_register &= ~HDSP_DAGainMask;
2236         switch (mode) {
2237         case 0:
2238                 hdsp->control_register |= HDSP_DAGainHighGain;
2239                 break;
2240         case 1:
2241                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2242                 break;
2243         case 2:
2244                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2245                 break;
2246         default:
2247                 return -1;
2248
2249         }
2250         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2251         return 0;
2252 }
2253
2254 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2255 {
2256         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2257
2258         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2259         uinfo->count = 1;
2260         uinfo->value.enumerated.items = 3;
2261         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2262                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2263         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2264         return 0;
2265 }
2266
2267 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2268 {
2269         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2270
2271         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2272         return 0;
2273 }
2274
2275 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2276 {
2277         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2278         unsigned long flags;
2279         int change;
2280         int val;
2281
2282         if (!snd_hdsp_use_is_exclusive(hdsp))
2283                 return -EBUSY;
2284         val = ucontrol->value.enumerated.item[0];
2285         if (val < 0) val = 0;
2286         if (val > 2) val = 2;
2287         spin_lock_irqsave(&hdsp->lock, flags);
2288         if (val != hdsp_da_gain(hdsp)) {
2289                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2290         } else {
2291                 change = 0;
2292         }
2293         spin_unlock_irqrestore(&hdsp->lock, flags);
2294         return change;
2295 }
2296
2297 #define HDSP_AD_GAIN(xname, xindex) \
2298 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2299   .name = xname, \
2300   .index = xindex, \
2301   .info = snd_hdsp_info_ad_gain, \
2302   .get = snd_hdsp_get_ad_gain, \
2303   .put = snd_hdsp_put_ad_gain \
2304 }
2305
2306 static int hdsp_ad_gain(hdsp_t *hdsp)
2307 {
2308         switch (hdsp->control_register & HDSP_ADGainMask) {
2309         case HDSP_ADGainMinus10dBV:
2310                 return 0;
2311         case HDSP_ADGainPlus4dBu:
2312                 return 1;
2313         case HDSP_ADGainLowGain:
2314                 return 2;
2315         default:
2316                 return 1;
2317         }
2318 }
2319
2320 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2321 {
2322         hdsp->control_register &= ~HDSP_ADGainMask;
2323         switch (mode) {
2324         case 0:
2325                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2326                 break;
2327         case 1:
2328                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2329                 break;
2330         case 2:
2331                 hdsp->control_register |= HDSP_ADGainLowGain;
2332                 break;
2333         default:
2334                 return -1;
2335
2336         }
2337         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2338         return 0;
2339 }
2340
2341 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2342 {
2343         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2344
2345         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2346         uinfo->count = 1;
2347         uinfo->value.enumerated.items = 3;
2348         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2349                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2350         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2351         return 0;
2352 }
2353
2354 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2355 {
2356         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2357
2358         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2359         return 0;
2360 }
2361
2362 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2363 {
2364         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2365         unsigned long flags;
2366         int change;
2367         int val;
2368
2369         if (!snd_hdsp_use_is_exclusive(hdsp))
2370                 return -EBUSY;
2371         val = ucontrol->value.enumerated.item[0];
2372         if (val < 0) val = 0;
2373         if (val > 2) val = 2;
2374         spin_lock_irqsave(&hdsp->lock, flags);
2375         if (val != hdsp_ad_gain(hdsp)) {
2376                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2377         } else {
2378                 change = 0;
2379         }
2380         spin_unlock_irqrestore(&hdsp->lock, flags);
2381         return change;
2382 }
2383
2384 #define HDSP_PHONE_GAIN(xname, xindex) \
2385 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2386   .name = xname, \
2387   .index = xindex, \
2388   .info = snd_hdsp_info_phone_gain, \
2389   .get = snd_hdsp_get_phone_gain, \
2390   .put = snd_hdsp_put_phone_gain \
2391 }
2392
2393 static int hdsp_phone_gain(hdsp_t *hdsp)
2394 {
2395         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2396         case HDSP_PhoneGain0dB:
2397                 return 0;
2398         case HDSP_PhoneGainMinus6dB:
2399                 return 1;
2400         case HDSP_PhoneGainMinus12dB:
2401                 return 2;
2402         default:
2403                 return 0;
2404         }
2405 }
2406
2407 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2408 {
2409         hdsp->control_register &= ~HDSP_PhoneGainMask;
2410         switch (mode) {
2411         case 0:
2412                 hdsp->control_register |= HDSP_PhoneGain0dB;
2413                 break;
2414         case 1:
2415                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2416                 break;
2417         case 2:
2418                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2419                 break;
2420         default:
2421                 return -1;
2422
2423         }
2424         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2425         return 0;
2426 }
2427
2428 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2429 {
2430         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2431
2432         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2433         uinfo->count = 1;
2434         uinfo->value.enumerated.items = 3;
2435         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2436                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2437         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2438         return 0;
2439 }
2440
2441 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2442 {
2443         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2444
2445         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2446         return 0;
2447 }
2448
2449 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2450 {
2451         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2452         unsigned long flags;
2453         int change;
2454         int val;
2455
2456         if (!snd_hdsp_use_is_exclusive(hdsp))
2457                 return -EBUSY;
2458         val = ucontrol->value.enumerated.item[0];
2459         if (val < 0) val = 0;
2460         if (val > 2) val = 2;
2461         spin_lock_irqsave(&hdsp->lock, flags);
2462         if (val != hdsp_phone_gain(hdsp)) {
2463                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2464         } else {
2465                 change = 0;
2466         }
2467         spin_unlock_irqrestore(&hdsp->lock, flags);
2468         return change;
2469 }
2470
2471 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2472 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2473   .name = xname, \
2474   .index = xindex, \
2475   .info = snd_hdsp_info_xlr_breakout_cable, \
2476   .get = snd_hdsp_get_xlr_breakout_cable, \
2477   .put = snd_hdsp_put_xlr_breakout_cable \
2478 }
2479
2480 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2481 {
2482         if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2483                 return 1;
2484         }
2485         return 0;
2486 }
2487
2488 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2489 {
2490         if (mode) {
2491                 hdsp->control_register |= HDSP_XLRBreakoutCable;
2492         } else {
2493                 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2494         }
2495         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2496         return 0;
2497 }
2498
2499 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2500 {
2501         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2502         uinfo->count = 1;
2503         uinfo->value.integer.min = 0;
2504         uinfo->value.integer.max = 1;
2505         return 0;
2506 }
2507
2508 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2509 {
2510         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2511
2512         ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2513         return 0;
2514 }
2515
2516 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2517 {
2518         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2519         unsigned long flags;
2520         int change;
2521         int val;
2522
2523         if (!snd_hdsp_use_is_exclusive(hdsp))
2524                 return -EBUSY;
2525         val = ucontrol->value.integer.value[0] & 1;
2526         spin_lock_irqsave(&hdsp->lock, flags);
2527         change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2528         hdsp_set_xlr_breakout_cable(hdsp, val);
2529         spin_unlock_irqrestore(&hdsp->lock, flags);
2530         return change;
2531 }
2532
2533 /* (De)activates old RME Analog Extension Board
2534    These are connected to the internal ADAT connector
2535    Switching this on desactivates external ADAT
2536 */
2537 #define HDSP_AEB(xname, xindex) \
2538 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2539   .name = xname, \
2540   .index = xindex, \
2541   .info = snd_hdsp_info_aeb, \
2542   .get = snd_hdsp_get_aeb, \
2543   .put = snd_hdsp_put_aeb \
2544 }
2545
2546 static int hdsp_aeb(hdsp_t *hdsp)
2547 {
2548         if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2549                 return 1;
2550         }
2551         return 0;
2552 }
2553
2554 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2555 {
2556         if (mode) {
2557                 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2558         } else {
2559                 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2560         }
2561         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2562         return 0;
2563 }
2564
2565 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2566 {
2567         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2568         uinfo->count = 1;
2569         uinfo->value.integer.min = 0;
2570         uinfo->value.integer.max = 1;
2571         return 0;
2572 }
2573
2574 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2575 {
2576         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2577
2578         ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2579         return 0;
2580 }
2581
2582 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2583 {
2584         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2585         unsigned long flags;
2586         int change;
2587         int val;
2588
2589         if (!snd_hdsp_use_is_exclusive(hdsp))
2590                 return -EBUSY;
2591         val = ucontrol->value.integer.value[0] & 1;
2592         spin_lock_irqsave(&hdsp->lock, flags);
2593         change = (int)val != hdsp_aeb(hdsp);
2594         hdsp_set_aeb(hdsp, val);
2595         spin_unlock_irqrestore(&hdsp->lock, flags);
2596         return change;
2597 }
2598
2599 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2600 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2601   .name = xname, \
2602   .index = xindex, \
2603   .info = snd_hdsp_info_pref_sync_ref, \
2604   .get = snd_hdsp_get_pref_sync_ref, \
2605   .put = snd_hdsp_put_pref_sync_ref \
2606 }
2607
2608 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2609 {
2610         /* Notice that this looks at the requested sync source,
2611            not the one actually in use.
2612         */
2613
2614         switch (hdsp->control_register & HDSP_SyncRefMask) {
2615         case HDSP_SyncRef_ADAT1:
2616                 return HDSP_SYNC_FROM_ADAT1;
2617         case HDSP_SyncRef_ADAT2:
2618                 return HDSP_SYNC_FROM_ADAT2;
2619         case HDSP_SyncRef_ADAT3:
2620                 return HDSP_SYNC_FROM_ADAT3;
2621         case HDSP_SyncRef_SPDIF:
2622                 return HDSP_SYNC_FROM_SPDIF;
2623         case HDSP_SyncRef_WORD:
2624                 return HDSP_SYNC_FROM_WORD;
2625         case HDSP_SyncRef_ADAT_SYNC:
2626                 return HDSP_SYNC_FROM_ADAT_SYNC;
2627         default:
2628                 return HDSP_SYNC_FROM_WORD;
2629         }
2630         return 0;
2631 }
2632
2633 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2634 {
2635         hdsp->control_register &= ~HDSP_SyncRefMask;
2636         switch (pref) {
2637         case HDSP_SYNC_FROM_ADAT1:
2638                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2639                 break;
2640         case HDSP_SYNC_FROM_ADAT2:
2641                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2642                 break;
2643         case HDSP_SYNC_FROM_ADAT3:
2644                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2645                 break;
2646         case HDSP_SYNC_FROM_SPDIF:
2647                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2648                 break;
2649         case HDSP_SYNC_FROM_WORD:
2650                 hdsp->control_register |= HDSP_SyncRef_WORD;
2651                 break;
2652         case HDSP_SYNC_FROM_ADAT_SYNC:
2653                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2654                 break;
2655         default:
2656                 return -1;
2657         }
2658         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2659         return 0;
2660 }
2661
2662 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2663 {
2664         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2665         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2666
2667         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2668         uinfo->count = 1;
2669
2670         switch (hdsp->io_type) {
2671         case Digiface:
2672         case H9652:
2673                 uinfo->value.enumerated.items = 6;
2674                 break;
2675         case Multiface:
2676                 uinfo->value.enumerated.items = 4;
2677                 break;
2678         case H9632:
2679                 uinfo->value.enumerated.items = 3;
2680                 break;
2681         default:
2682                 uinfo->value.enumerated.items = 0;
2683                 break;
2684         }
2685
2686         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2687                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2688         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2689         return 0;
2690 }
2691
2692 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2693 {
2694         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2695
2696         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2697         return 0;
2698 }
2699
2700 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2701 {
2702         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2703         unsigned long flags;
2704         int change, max;
2705         unsigned int val;
2706
2707         if (!snd_hdsp_use_is_exclusive(hdsp))
2708                 return -EBUSY;
2709
2710         switch (hdsp->io_type) {
2711         case Digiface:
2712         case H9652:
2713                 max = 6;
2714                 break;
2715         case Multiface:
2716                 max = 4;
2717                 break;
2718         case H9632:
2719                 max = 3;
2720                 break;
2721         default:
2722                 return -EIO;
2723         }
2724
2725         val = ucontrol->value.enumerated.item[0] % max;
2726         spin_lock_irqsave(&hdsp->lock, flags);
2727         change = (int)val != hdsp_pref_sync_ref(hdsp);
2728         hdsp_set_pref_sync_ref(hdsp, val);
2729         spin_unlock_irqrestore(&hdsp->lock, flags);
2730         return change;
2731 }
2732
2733 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2734 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2735   .name = xname, \
2736   .index = xindex, \
2737   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2738   .info = snd_hdsp_info_autosync_ref, \
2739   .get = snd_hdsp_get_autosync_ref, \
2740 }
2741
2742 static int hdsp_autosync_ref(hdsp_t *hdsp)
2743 {
2744         /* This looks at the autosync selected sync reference */
2745         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2746
2747         switch (status2 & HDSP_SelSyncRefMask) {
2748         case HDSP_SelSyncRef_WORD:
2749                 return HDSP_AUTOSYNC_FROM_WORD;
2750         case HDSP_SelSyncRef_ADAT_SYNC:
2751                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2752         case HDSP_SelSyncRef_SPDIF:
2753                 return HDSP_AUTOSYNC_FROM_SPDIF;
2754         case HDSP_SelSyncRefMask:
2755                 return HDSP_AUTOSYNC_FROM_NONE;
2756         case HDSP_SelSyncRef_ADAT1:
2757                 return HDSP_AUTOSYNC_FROM_ADAT1;
2758         case HDSP_SelSyncRef_ADAT2:
2759                 return HDSP_AUTOSYNC_FROM_ADAT2;
2760         case HDSP_SelSyncRef_ADAT3:
2761                 return HDSP_AUTOSYNC_FROM_ADAT3;
2762         default:
2763                 return HDSP_AUTOSYNC_FROM_WORD;
2764         }
2765         return 0;
2766 }
2767
2768 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2769 {
2770         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2771
2772         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2773         uinfo->count = 1;
2774         uinfo->value.enumerated.items = 7;
2775         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2776                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2777         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2778         return 0;
2779 }
2780
2781 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2782 {
2783         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2784
2785         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2786         return 0;
2787 }
2788
2789 #define HDSP_PASSTHRU(xname, xindex) \
2790 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2791   .name = xname, \
2792   .index = xindex, \
2793   .info = snd_hdsp_info_passthru, \
2794   .put = snd_hdsp_put_passthru, \
2795   .get = snd_hdsp_get_passthru \
2796 }
2797
2798 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
2799 {
2800         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2801         uinfo->count = 1;
2802         uinfo->value.integer.min = 0;
2803         uinfo->value.integer.max = 1;
2804         return 0;
2805 }
2806
2807 static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2808 {
2809         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2810         unsigned long flags;
2811
2812         spin_lock_irqsave(&hdsp->lock, flags);
2813         ucontrol->value.integer.value[0] = hdsp->passthru;
2814         spin_unlock_irqrestore(&hdsp->lock, flags);
2815         return 0;
2816 }
2817
2818 static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2819 {
2820         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2821         unsigned long flags;
2822         int change;
2823         unsigned int val;
2824         int err = 0;
2825
2826         if (!snd_hdsp_use_is_exclusive(hdsp))
2827                 return -EBUSY;
2828
2829         val = ucontrol->value.integer.value[0] & 1;
2830         spin_lock_irqsave(&hdsp->lock, flags);
2831         change = (ucontrol->value.integer.value[0] != hdsp->passthru);
2832         if (change)
2833                 err = hdsp_set_passthru(hdsp, val);
2834         spin_unlock_irqrestore(&hdsp->lock, flags);
2835         return err ? err : change;
2836 }
2837
2838 #define HDSP_LINE_OUT(xname, xindex) \
2839 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2840   .name = xname, \
2841   .index = xindex, \
2842   .info = snd_hdsp_info_line_out, \
2843   .get = snd_hdsp_get_line_out, \
2844   .put = snd_hdsp_put_line_out \
2845 }
2846
2847 static int hdsp_line_out(hdsp_t *hdsp)
2848 {
2849         return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2850 }
2851
2852 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2853 {
2854         if (out) {
2855                 hdsp->control_register |= HDSP_LineOut;
2856         } else {
2857                 hdsp->control_register &= ~HDSP_LineOut;
2858         }
2859         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2860         return 0;
2861 }
2862
2863 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2864 {
2865         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2866         uinfo->count = 1;
2867         uinfo->value.integer.min = 0;
2868         uinfo->value.integer.max = 1;
2869         return 0;
2870 }
2871
2872 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2873 {
2874         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2875         unsigned long flags;
2876
2877         spin_lock_irqsave(&hdsp->lock, flags);
2878         ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2879         spin_unlock_irqrestore(&hdsp->lock, flags);
2880         return 0;
2881 }
2882
2883 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2884 {
2885         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2886         unsigned long flags;
2887         int change;
2888         unsigned int val;
2889
2890         if (!snd_hdsp_use_is_exclusive(hdsp))
2891                 return -EBUSY;
2892         val = ucontrol->value.integer.value[0] & 1;
2893         spin_lock_irqsave(&hdsp->lock, flags);
2894         change = (int)val != hdsp_line_out(hdsp);
2895         hdsp_set_line_output(hdsp, val);
2896         spin_unlock_irqrestore(&hdsp->lock, flags);
2897         return change;
2898 }
2899
2900 #define HDSP_MIXER(xname, xindex) \
2901 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2902   .name = xname, \
2903   .index = xindex, \
2904   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2905                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2906   .info = snd_hdsp_info_mixer, \
2907   .get = snd_hdsp_get_mixer, \
2908   .put = snd_hdsp_put_mixer \
2909 }
2910
2911 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2912 {
2913         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2914         uinfo->count = 3;
2915         uinfo->value.integer.min = 0;
2916         uinfo->value.integer.max = 65536;
2917         uinfo->value.integer.step = 1;
2918         return 0;
2919 }
2920
2921 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2922 {
2923         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2924         unsigned long flags;
2925         int source;
2926         int destination;
2927         int addr;
2928
2929         source = ucontrol->value.integer.value[0];
2930         destination = ucontrol->value.integer.value[1];
2931
2932         if (source >= hdsp->max_channels) {
2933                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2934         } else {
2935                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2936         }
2937
2938         spin_lock_irqsave(&hdsp->lock, flags);
2939         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2940         spin_unlock_irqrestore(&hdsp->lock, flags);
2941         return 0;
2942 }
2943
2944 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2945 {
2946         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2947         unsigned long flags;
2948         int change;
2949         int source;
2950         int destination;
2951         int gain;
2952         int addr;
2953
2954         if (!snd_hdsp_use_is_exclusive(hdsp))
2955                 return -EBUSY;
2956
2957         source = ucontrol->value.integer.value[0];
2958         destination = ucontrol->value.integer.value[1];
2959
2960         if (source >= hdsp->max_channels) {
2961                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2962         } else {
2963                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2964         }
2965
2966         gain = ucontrol->value.integer.value[2];
2967
2968         spin_lock_irqsave(&hdsp->lock, flags);
2969         change = gain != hdsp_read_gain(hdsp, addr);
2970         if (change)
2971                 hdsp_write_gain(hdsp, addr, gain);
2972         spin_unlock_irqrestore(&hdsp->lock, flags);
2973         return change;
2974 }
2975
2976 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2977 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2978   .name = xname, \
2979   .index = xindex, \
2980   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2981   .info = snd_hdsp_info_sync_check, \
2982   .get = snd_hdsp_get_wc_sync_check \
2983 }
2984
2985 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2986 {
2987         static char *texts[] = {"No Lock", "Lock", "Sync" };
2988         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2989         uinfo->count = 1;
2990         uinfo->value.enumerated.items = 3;
2991         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2992                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2993         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2994         return 0;
2995 }
2996
2997 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2998 {
2999         int status2 = hdsp_read(hdsp, HDSP_status2Register);
3000         if (status2 & HDSP_wc_lock) {
3001                 if (status2 & HDSP_wc_sync) {
3002                         return 2;
3003                 } else {
3004                          return 1;
3005                 }
3006         } else {
3007                 return 0;
3008         }
3009         return 0;
3010 }
3011
3012 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3013 {
3014         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3015
3016         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
3017         return 0;
3018 }
3019
3020 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
3021 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3022   .name = xname, \
3023   .index = xindex, \
3024   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3025   .info = snd_hdsp_info_sync_check, \
3026   .get = snd_hdsp_get_spdif_sync_check \
3027 }
3028
3029 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
3030 {
3031         int status = hdsp_read(hdsp, HDSP_statusRegister);
3032         if (status & HDSP_SPDIFErrorFlag) {
3033                 return 0;
3034         } else {
3035                 if (status & HDSP_SPDIFSync) {
3036                         return 2;
3037                 } else {
3038                         return 1;
3039                 }
3040         }
3041         return 0;
3042 }
3043
3044 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3045 {
3046         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3047
3048         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3049         return 0;
3050 }
3051
3052 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3053 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3054   .name = xname, \
3055   .index = xindex, \
3056   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3057   .info = snd_hdsp_info_sync_check, \
3058   .get = snd_hdsp_get_adatsync_sync_check \
3059 }
3060
3061 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3062 {
3063         int status = hdsp_read(hdsp, HDSP_statusRegister);
3064         if (status & HDSP_TimecodeLock) {
3065                 if (status & HDSP_TimecodeSync) {
3066                         return 2;
3067                 } else {
3068                         return 1;
3069                 }
3070         } else {
3071                 return 0;
3072         }
3073 }
3074
3075 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3076 {
3077         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3078
3079         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3080         return 0;
3081 }
3082
3083 #define HDSP_ADAT_SYNC_CHECK \
3084 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3085   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3086   .info = snd_hdsp_info_sync_check, \
3087   .get = snd_hdsp_get_adat_sync_check \
3088 }
3089
3090 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3091 {
3092         int status = hdsp_read(hdsp, HDSP_statusRegister);
3093
3094         if (status & (HDSP_Lock0>>idx)) {
3095                 if (status & (HDSP_Sync0>>idx)) {
3096                         return 2;
3097                 } else {
3098                         return 1;
3099                 }
3100         } else {
3101                 return 0;
3102         }
3103 }
3104
3105 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3106 {
3107         int offset;
3108         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3109
3110         offset = ucontrol->id.index - 1;
3111         snd_assert(offset >= 0);
3112
3113         switch (hdsp->io_type) {
3114         case Digiface:
3115         case H9652:
3116                 if (offset >= 3)
3117                         return -EINVAL;
3118                 break;
3119         case Multiface:
3120         case H9632:
3121                 if (offset >= 1)
3122                         return -EINVAL;
3123                 break;
3124         default:
3125                 return -EIO;
3126         }
3127
3128         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3129         return 0;
3130 }
3131
3132 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3133 HDSP_DA_GAIN("DA Gain", 0),
3134 HDSP_AD_GAIN("AD Gain", 0),
3135 HDSP_PHONE_GAIN("Phones Gain", 0),
3136 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3137 };
3138
3139 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3140 {
3141         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3142         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3143         .info =         snd_hdsp_control_spdif_info,
3144         .get =          snd_hdsp_control_spdif_get,
3145         .put =          snd_hdsp_control_spdif_put,
3146 },
3147 {
3148         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3149         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3150         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3151         .info =         snd_hdsp_control_spdif_stream_info,
3152         .get =          snd_hdsp_control_spdif_stream_get,
3153         .put =          snd_hdsp_control_spdif_stream_put,
3154 },
3155 {
3156         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3157         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3158         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3159         .info =         snd_hdsp_control_spdif_mask_info,
3160         .get =          snd_hdsp_control_spdif_mask_get,
3161         .private_value = IEC958_AES0_NONAUDIO |
3162                          IEC958_AES0_PROFESSIONAL |
3163                          IEC958_AES0_CON_EMPHASIS,
3164 },
3165 {
3166         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3167         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3168         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3169         .info =         snd_hdsp_control_spdif_mask_info,
3170         .get =          snd_hdsp_control_spdif_mask_get,
3171         .private_value = IEC958_AES0_NONAUDIO |
3172                          IEC958_AES0_PROFESSIONAL |
3173                          IEC958_AES0_PRO_EMPHASIS,
3174 },
3175 HDSP_MIXER("Mixer", 0),
3176 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3177 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3178 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3179 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3180 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3181 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3182 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3183 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3184 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3185 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3186 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3187 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3188 /* 'External Rate' complies with the alsa control naming scheme */
3189 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3190 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3191 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3192 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3193 HDSP_PASSTHRU("Passthru", 0),
3194 HDSP_LINE_OUT("Line Out", 0),
3195 };
3196
3197 #define HDSP_CONTROLS (sizeof(snd_hdsp_controls)/sizeof(snd_kcontrol_new_t))
3198
3199 #define HDSP_9632_CONTROLS (sizeof(snd_hdsp_9632_controls)/sizeof(snd_kcontrol_new_t))
3200
3201 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3202 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3203
3204 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3205 {
3206         unsigned int idx;
3207         int err;
3208         snd_kcontrol_t *kctl;
3209
3210         for (idx = 0; idx < HDSP_CONTROLS; idx++) {
3211                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3212                         return err;
3213                 }
3214                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3215                         hdsp->spdif_ctl = kctl;
3216         }
3217
3218         /* ADAT SyncCheck status */
3219         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3220         snd_hdsp_adat_sync_check.index = 1;
3221         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3222                 return err;
3223         }
3224         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3225                 for (idx = 1; idx < 3; ++idx) {
3226                         snd_hdsp_adat_sync_check.index = idx+1;
3227                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3228                                 return err;
3229                         }
3230                 }
3231         }
3232
3233         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3234         if (hdsp->io_type == H9632) {
3235                 for (idx = 0; idx < HDSP_9632_CONTROLS; idx++) {
3236                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3237                                 return err;
3238                         }
3239                 }
3240         }
3241
3242         /* AEB control for H96xx card */
3243         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3244                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3245                                 return err;
3246                 }
3247         }
3248
3249         return 0;
3250 }
3251
3252 /*------------------------------------------------------------
3253    /proc interface
3254  ------------------------------------------------------------*/
3255
3256 static void
3257 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3258 {
3259         hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3260         unsigned int status;
3261         unsigned int status2;
3262         char *pref_sync_ref;
3263         char *autosync_ref;
3264         char *system_clock_mode;
3265         char *clock_source;
3266         int x;
3267
3268         if (hdsp_check_for_iobox (hdsp)) {
3269                 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3270                 return;
3271         }
3272
3273         if (hdsp_check_for_firmware(hdsp)) {
3274                 if (hdsp->state & HDSP_FirmwareCached) {
3275                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3276                                 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3277                                 return;
3278                         }
3279                 } else {
3280                         snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3281                         return;
3282                 }
3283         }
3284
3285         status = hdsp_read(hdsp, HDSP_statusRegister);
3286         status2 = hdsp_read(hdsp, HDSP_status2Register);
3287
3288         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3289         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3290                     hdsp->capture_buffer, hdsp->playback_buffer);
3291         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3292                     hdsp->irq, hdsp->port, hdsp->iobase);
3293         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3294         snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3295         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3296         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3297         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3298
3299         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3300         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3301         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3302         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3303
3304         snd_iprintf(buffer, "\n");
3305
3306         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3307
3308         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3309         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3310         snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
3311         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3312
3313         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3314
3315         snd_iprintf(buffer, "\n");
3316
3317
3318         switch (hdsp_clock_source(hdsp)) {
3319         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3320                 clock_source = "AutoSync";
3321                 break;
3322         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3323                 clock_source = "Internal 32 kHz";
3324                 break;
3325         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3326                 clock_source = "Internal 44.1 kHz";
3327                 break;
3328         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3329                 clock_source = "Internal 48 kHz";
3330                 break;
3331         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3332                 clock_source = "Internal 64 kHz";
3333                 break;
3334         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3335                 clock_source = "Internal 88.2 kHz";
3336                 break;
3337         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3338                 clock_source = "Internal 96 kHz";
3339                 break;
3340         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3341                 clock_source = "Internal 128 kHz";
3342                 break;
3343         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3344                 clock_source = "Internal 176.4 kHz";
3345                 break;
3346                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3347                 clock_source = "Internal 192 kHz";
3348                 break;
3349         default:
3350                 clock_source = "Error";
3351         }
3352         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3353
3354         if (hdsp_system_clock_mode(hdsp)) {
3355                 system_clock_mode = "Slave";
3356         } else {
3357                 system_clock_mode = "Master";
3358         }
3359
3360         switch (hdsp_pref_sync_ref (hdsp)) {
3361         case HDSP_SYNC_FROM_WORD:
3362                 pref_sync_ref = "Word Clock";
3363                 break;
3364         case HDSP_SYNC_FROM_ADAT_SYNC:
3365                 pref_sync_ref = "ADAT Sync";
3366                 break;
3367         case HDSP_SYNC_FROM_SPDIF:
3368                 pref_sync_ref = "SPDIF";
3369                 break;
3370         case HDSP_SYNC_FROM_ADAT1:
3371                 pref_sync_ref = "ADAT1";
3372                 break;
3373         case HDSP_SYNC_FROM_ADAT2:
3374                 pref_sync_ref = "ADAT2";
3375                 break;
3376         case HDSP_SYNC_FROM_ADAT3:
3377                 pref_sync_ref = "ADAT3";
3378                 break;
3379         default:
3380                 pref_sync_ref = "Word Clock";
3381                 break;
3382         }
3383         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3384
3385         switch (hdsp_autosync_ref (hdsp)) {
3386         case HDSP_AUTOSYNC_FROM_WORD:
3387                 autosync_ref = "Word Clock";
3388                 break;
3389         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3390                 autosync_ref = "ADAT Sync";
3391                 break;
3392         case HDSP_AUTOSYNC_FROM_SPDIF:
3393                 autosync_ref = "SPDIF";
3394                 break;
3395         case HDSP_AUTOSYNC_FROM_NONE:
3396                 autosync_ref = "None";
3397                 break;
3398         case HDSP_AUTOSYNC_FROM_ADAT1:
3399                 autosync_ref = "ADAT1";
3400                 break;
3401         case HDSP_AUTOSYNC_FROM_ADAT2:
3402                 autosync_ref = "ADAT2";
3403                 break;
3404         case HDSP_AUTOSYNC_FROM_ADAT3:
3405                 autosync_ref = "ADAT3";
3406                 break;
3407         default:
3408                 autosync_ref = "---";
3409                 break;
3410         }
3411         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3412
3413         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3414
3415         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3416
3417         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3418
3419         snd_iprintf(buffer, "\n");
3420
3421         switch (hdsp_spdif_in(hdsp)) {
3422         case HDSP_SPDIFIN_OPTICAL:
3423                 snd_iprintf(buffer, "IEC958 input: Optical\n");
3424                 break;
3425         case HDSP_SPDIFIN_COAXIAL:
3426                 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3427                 break;
3428         case HDSP_SPDIFIN_INTERNAL:
3429                 snd_iprintf(buffer, "IEC958 input: Internal\n");
3430                 break;
3431         case HDSP_SPDIFIN_AES:
3432                 snd_iprintf(buffer, "IEC958 input: AES\n");
3433                 break;
3434         default:
3435                 snd_iprintf(buffer, "IEC958 input: ???\n");
3436                 break;
3437         }
3438
3439         if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3440                 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3441         } else {
3442                 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3443         }
3444
3445         if (hdsp->control_register & HDSP_SPDIFProfessional) {
3446                 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3447         } else {
3448                 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3449         }
3450
3451         if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3452                 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3453         } else {
3454                 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3455         }
3456
3457         if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3458                 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3459         } else {
3460                 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3461         }
3462         if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3463                 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3464         } else {
3465                 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3466         }
3467
3468         snd_iprintf(buffer, "\n");
3469
3470         /* Sync Check */
3471         x = status & HDSP_Sync0;
3472         if (status & HDSP_Lock0) {
3473                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3474         } else {
3475                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3476         }
3477
3478         switch (hdsp->io_type) {
3479         case Digiface:
3480         case H9652:
3481                 x = status & HDSP_Sync1;
3482                 if (status & HDSP_Lock1) {
3483                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3484                 } else {
3485                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3486                 }
3487                 x = status & HDSP_Sync2;
3488                 if (status & HDSP_Lock2) {
3489                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3490                 } else {
3491                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3492                 }
3493         default:
3494                 /* relax */
3495                 break;
3496         }
3497
3498         x = status & HDSP_SPDIFSync;
3499         if (status & HDSP_SPDIFErrorFlag) {
3500                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3501         } else {
3502                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3503         }
3504
3505         x = status2 & HDSP_wc_sync;
3506         if (status2 & HDSP_wc_lock) {
3507                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3508         } else {
3509                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3510         }
3511
3512         x = status & HDSP_TimecodeSync;
3513         if (status & HDSP_TimecodeLock) {
3514                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3515         } else {
3516                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3517         }
3518
3519         snd_iprintf(buffer, "\n");
3520
3521         /* Informations about H9632 specific controls */
3522         if (hdsp->io_type == H9632) {
3523                 char *tmp;
3524
3525                 switch (hdsp_ad_gain(hdsp)) {
3526                 case 0:
3527                         tmp = "-10 dBV";
3528                         break;
3529                 case 1:
3530                         tmp = "+4 dBu";
3531                         break;
3532                 default:
3533                         tmp = "Lo Gain";
3534                         break;
3535                 }
3536                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3537
3538                 switch (hdsp_da_gain(hdsp)) {
3539                 case 0:
3540                         tmp = "Hi Gain";
3541                         break;
3542                 case 1:
3543                         tmp = "+4 dBu";
3544                         break;
3545                 default:
3546                         tmp = "-10 dBV";
3547                         break;
3548                 }
3549                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3550
3551                 switch (hdsp_phone_gain(hdsp)) {
3552                 case 0:
3553                         tmp = "0 dB";
3554                         break;
3555                 case 1:
3556                         tmp = "-6 dB";
3557                         break;
3558                 default:
3559                         tmp = "-12 dB";
3560                         break;
3561                 }
3562                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3563
3564                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3565
3566                 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3567                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3568                 } else {
3569                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3570                 }
3571                 snd_iprintf(buffer, "\n");
3572         }
3573
3574 }
3575
3576 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3577 {
3578         snd_info_entry_t *entry;
3579
3580         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3581                 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3582 }
3583
3584 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3585 {
3586         if (hdsp->capture_buffer_unaligned) {
3587                 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES,
3588                                            hdsp->capture_buffer_unaligned,
3589                                            hdsp->capture_buffer_addr, 1);
3590         }
3591
3592         if (hdsp->playback_buffer_unaligned) {
3593                 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES,
3594                                            hdsp->playback_buffer_unaligned,
3595                                            hdsp->playback_buffer_addr, 0);
3596         }
3597 }
3598
3599 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3600 {
3601         void *pb, *cb;
3602         dma_addr_t pb_addr, cb_addr;
3603         unsigned long pb_bus, cb_bus;
3604
3605         cb = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, &cb_addr, 1);
3606         pb = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, &pb_addr, 0);
3607
3608         if (cb == 0 || pb == 0) {
3609                 if (cb) {
3610                         snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, cb, cb_addr, 1);
3611                 }
3612                 if (pb) {
3613                         snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, pb, pb_addr, 0);
3614                 }
3615
3616                 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3617                 return -ENOMEM;
3618         }
3619
3620         /* save raw addresses for use when freeing memory later */
3621
3622         hdsp->capture_buffer_unaligned = cb;
3623         hdsp->playback_buffer_unaligned = pb;
3624         hdsp->capture_buffer_addr = cb_addr;
3625         hdsp->playback_buffer_addr = pb_addr;
3626
3627         /* Align to bus-space 64K boundary */
3628
3629         cb_bus = (cb_addr + 0xFFFF) & ~0xFFFFl;
3630         pb_bus = (pb_addr + 0xFFFF) & ~0xFFFFl;
3631
3632         /* Tell the card where it is */
3633
3634         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3635         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3636
3637         hdsp->capture_buffer = cb + (cb_bus - cb_addr);
3638         hdsp->playback_buffer = pb + (pb_bus - pb_addr);
3639
3640         return 0;
3641 }
3642
3643 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3644 {
3645         unsigned int i;
3646
3647         /* ASSUMPTION: hdsp->lock is either held, or
3648            there is no need to hold it (e.g. during module
3649            initalization).
3650          */
3651
3652         /* set defaults:
3653
3654            SPDIF Input via Coax
3655            Master clock mode
3656            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3657                             which implies 2 4096 sample, 32Kbyte periods).
3658            Enable line out.
3659          */
3660
3661         hdsp->control_register = HDSP_ClockModeMaster |
3662                                  HDSP_SPDIFInputCoaxial |
3663                                  hdsp_encode_latency(7) |
3664                                  HDSP_LineOut;
3665
3666
3667         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3668
3669 #ifdef SNDRV_BIG_ENDIAN
3670         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3671 #else
3672         hdsp->control2_register = 0;
3673 #endif
3674         if (hdsp->io_type == H9652) {
3675                 snd_hdsp_9652_enable_mixer (hdsp);
3676         } else {
3677             hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3678         }
3679
3680         hdsp_reset_hw_pointer(hdsp);
3681         hdsp_compute_period_size(hdsp);
3682
3683         /* silence everything */
3684
3685         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3686                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3687         }
3688
3689         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3690                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3691                         return -EIO;
3692                 }
3693         }
3694
3695         if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) {
3696
3697                 int lineouts_base;
3698
3699                 snd_printk ("sending all inputs and playback streams to line outs.\n");
3700
3701                 /* route all inputs to the line outs for easy monitoring. send
3702                    odd numbered channels to right, even to left.
3703                 */
3704                 if (hdsp->io_type == H9632) {
3705                         /* this is the phones/analog output */
3706                         lineouts_base = 10;
3707                 } else {
3708                         lineouts_base = 26;
3709                 }
3710
3711                 for (i = 0; i < hdsp->max_channels; i++) {
3712                         if (i & 1) {
3713                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) ||
3714                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) {
3715                                     return -EIO;
3716                                 }
3717                         } else {
3718                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) ||
3719                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) {
3720
3721                                     return -EIO;
3722                                 }
3723                         }
3724                 }
3725         }
3726
3727         hdsp->passthru = 0;
3728
3729         /* H9632 specific defaults */
3730         if (hdsp->io_type == H9632) {
3731                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3732                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3733         }
3734
3735         /* set a default rate so that the channel map is set up.
3736          */
3737
3738         hdsp_set_rate(hdsp, 48000, 1);
3739
3740         return 0;
3741 }
3742
3743 void hdsp_midi_tasklet(unsigned long arg)
3744 {
3745         hdsp_t *hdsp = (hdsp_t *)arg;
3746
3747         if (hdsp->midi[0].pending) {
3748                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3749         }
3750         if (hdsp->midi[1].pending) {
3751                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3752         }
3753 }
3754
3755 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3756 {
3757         hdsp_t *hdsp = (hdsp_t *) dev_id;
3758         unsigned int status;
3759         int audio;
3760         int midi0;
3761         int midi1;
3762         unsigned int midi0status;
3763         unsigned int midi1status;
3764         int schedule = 0;
3765
3766         status = hdsp_read(hdsp, HDSP_statusRegister);
3767
3768         audio = status & HDSP_audioIRQPending;
3769         midi0 = status & HDSP_midi0IRQPending;
3770         midi1 = status & HDSP_midi1IRQPending;
3771
3772         if (!audio && !midi0 && !midi1) {
3773                 return IRQ_NONE;
3774         }
3775
3776         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3777
3778         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3779         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3780
3781         if (audio) {
3782                 if (hdsp->capture_substream) {
3783                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3784                 }
3785
3786                 if (hdsp->playback_substream) {
3787                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3788                 }
3789         }
3790
3791         if (midi0 && midi0status) {
3792                 /* we disable interrupts for this input until processing is done */
3793                 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3794                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3795                 hdsp->midi[0].pending = 1;
3796                 schedule = 1;
3797         }
3798         if (midi1 && midi1status) {
3799                 /* we disable interrupts for this input until processing is done */
3800                 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3801                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3802                 hdsp->midi[1].pending = 1;
3803                 schedule = 1;
3804         }
3805         if (schedule)
3806             tasklet_hi_schedule(&hdsp->midi_tasklet);
3807         return IRQ_HANDLED;
3808 }
3809
3810 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3811 {
3812         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3813         return hdsp_hw_pointer(hdsp);
3814 }
3815
3816 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3817                                              int stream,
3818                                              int channel)
3819
3820 {
3821         int mapped_channel;
3822
3823         snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3824
3825         if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3826                 return NULL;
3827         }
3828
3829         if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3830                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3831         } else {
3832                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3833         }
3834 }
3835
3836 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3837                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3838 {
3839         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3840         char *channel_buf;
3841
3842         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3843
3844         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3845         snd_assert(channel_buf != NULL, return -EIO);
3846         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3847                 return -EFAULT;
3848         return count;
3849 }
3850
3851 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3852                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3853 {
3854         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3855         char *channel_buf;
3856
3857         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3858
3859         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3860         snd_assert(channel_buf != NULL, return -EIO);
3861         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3862                 return -EFAULT;
3863         return count;
3864 }
3865
3866 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3867                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3868 {
3869         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3870         char *channel_buf;
3871
3872         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3873         snd_assert(channel_buf != NULL, return -EIO);
3874         memset(channel_buf + pos * 4, 0, count * 4);
3875         return count;
3876 }
3877
3878 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3879 {
3880         snd_pcm_runtime_t *runtime = substream->runtime;
3881         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3882         snd_pcm_substream_t *other;
3883         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3884                 other = hdsp->capture_substream;
3885         else
3886                 other = hdsp->playback_substream;
3887         if (hdsp->running)
3888                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3889         else
3890                 runtime->status->hw_ptr = 0;
3891         if (other) {
3892                 struct list_head *pos;
3893                 snd_pcm_substream_t *s;
3894                 snd_pcm_runtime_t *oruntime = other->runtime;
3895                 snd_pcm_group_for_each(pos, substream) {
3896                         s = snd_pcm_group_substream_entry(pos);
3897                         if (s == other) {
3898                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3899                                 break;
3900                         }
3901                 }
3902         }
3903         return 0;
3904 }
3905
3906 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3907                                  snd_pcm_hw_params_t *params)
3908 {
3909         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3910         int err;
3911         pid_t this_pid;
3912         pid_t other_pid;
3913
3914         if (hdsp_check_for_iobox (hdsp)) {
3915                 return -EIO;
3916         }
3917
3918         if (hdsp_check_for_firmware(hdsp)) {
3919                 if (hdsp->state & HDSP_FirmwareCached) {
3920                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3921                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3922                         }
3923                 } else {
3924                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3925                 }
3926                 return -EIO;
3927         }
3928
3929         spin_lock_irq(&hdsp->lock);
3930
3931         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3932                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3933                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3934                 this_pid = hdsp->playback_pid;
3935                 other_pid = hdsp->capture_pid;
3936         } else {
3937                 this_pid = hdsp->capture_pid;
3938                 other_pid = hdsp->playback_pid;
3939         }
3940
3941         if ((other_pid > 0) && (this_pid != other_pid)) {
3942
3943                 /* The other stream is open, and not by the same
3944                    task as this one. Make sure that the parameters
3945                    that matter are the same.
3946                  */
3947
3948                 if (params_rate(params) != hdsp->system_sample_rate) {
3949                         spin_unlock_irq(&hdsp->lock);
3950                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3951                         return -EBUSY;
3952                 }
3953
3954                 if (params_period_size(params) != hdsp->period_bytes / 4) {
3955                         spin_unlock_irq(&hdsp->lock);
3956                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3957                         return -EBUSY;
3958                 }
3959
3960                 /* We're fine. */
3961
3962                 spin_unlock_irq(&hdsp->lock);
3963                 return 0;
3964
3965         } else {
3966                 spin_unlock_irq(&hdsp->lock);
3967         }
3968
3969         /* how to make sure that the rate matches an externally-set one ?
3970          */
3971
3972         spin_lock_irq(&hdsp->lock);
3973         if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3974                 spin_unlock_irq(&hdsp->lock);
3975                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3976                 return err;
3977         } else {
3978                 spin_unlock_irq(&hdsp->lock);
3979         }
3980
3981         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3982                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3983                 return err;
3984         }
3985
3986         return 0;
3987 }
3988
3989 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3990                                     snd_pcm_channel_info_t *info)
3991 {
3992         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3993         int mapped_channel;
3994
3995         snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3996
3997         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3998                 return -EINVAL;
3999         }
4000
4001         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4002         info->first = 0;
4003         info->step = 32;
4004         return 0;
4005 }
4006
4007 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
4008                              unsigned int cmd, void *arg)
4009 {
4010         switch (cmd) {
4011         case SNDRV_PCM_IOCTL1_RESET:
4012         {
4013                 return snd_hdsp_reset(substream);
4014         }
4015         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4016         {
4017                 snd_pcm_channel_info_t *info = arg;
4018                 return snd_hdsp_channel_info(substream, info);
4019         }
4020         default:
4021                 break;
4022         }
4023
4024         return snd_pcm_lib_ioctl(substream, cmd, arg);
4025 }
4026
4027 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
4028 {
4029         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4030         snd_pcm_substream_t *other;
4031         int running;
4032
4033         if (hdsp_check_for_iobox (hdsp)) {
4034                 return -EIO;
4035         }
4036
4037         if (hdsp_check_for_firmware(hdsp)) {
4038                 if (hdsp->state & HDSP_FirmwareCached) {
4039                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4040                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4041                         }
4042                 } else {
4043                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4044                 }
4045                 return -EIO;
4046         }
4047
4048         spin_lock(&hdsp->lock);
4049         running = hdsp->running;
4050         switch (cmd) {
4051         case SNDRV_PCM_TRIGGER_START:
4052                 running |= 1 << substream->stream;
4053                 break;
4054         case SNDRV_PCM_TRIGGER_STOP:
4055                 running &= ~(1 << substream->stream);
4056                 break;
4057         default:
4058                 snd_BUG();
4059                 spin_unlock(&hdsp->lock);
4060                 return -EINVAL;
4061         }
4062         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4063                 other = hdsp->capture_substream;
4064         else
4065                 other = hdsp->playback_substream;
4066
4067         if (other) {
4068                 struct list_head *pos;
4069                 snd_pcm_substream_t *s;
4070                 snd_pcm_group_for_each(pos, substream) {
4071                         s = snd_pcm_group_substream_entry(pos);
4072                         if (s == other) {
4073                                 snd_pcm_trigger_done(s, substream);
4074                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4075                                         running |= 1 << s->stream;
4076                                 else
4077                                         running &= ~(1 << s->stream);
4078                                 goto _ok;
4079                         }
4080                 }
4081                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4082                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4083                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4084                                 hdsp_silence_playback(hdsp);
4085                 } else {
4086                         if (running &&
4087                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4088                                 hdsp_silence_playback(hdsp);
4089                 }
4090         } else {
4091                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4092                                 hdsp_silence_playback(hdsp);
4093         }
4094  _ok:
4095         snd_pcm_trigger_done(substream, substream);
4096         if (!hdsp->running && running)
4097                 hdsp_start_audio(hdsp);
4098         else if (hdsp->running && !running)
4099                 hdsp_stop_audio(hdsp);
4100         hdsp->running = running;
4101         spin_unlock(&hdsp->lock);
4102
4103         return 0;
4104 }
4105
4106 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4107 {
4108         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4109         int result = 0;
4110
4111         if (hdsp_check_for_iobox (hdsp)) {
4112                 return -EIO;
4113         }
4114
4115         if (hdsp_check_for_firmware(hdsp)) {
4116                 if (hdsp->state & HDSP_FirmwareCached) {
4117                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4118                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4119                         }
4120                 } else {
4121                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4122                 }
4123                 return -EIO;
4124         }
4125
4126         spin_lock(&hdsp->lock);
4127         if (!hdsp->running)
4128                 hdsp_reset_hw_pointer(hdsp);
4129         spin_unlock(&hdsp->lock);
4130         return result;
4131 }
4132
4133 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4134 {
4135         .info =                 (SNDRV_PCM_INFO_MMAP |
4136                                  SNDRV_PCM_INFO_MMAP_VALID |
4137                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4138                                  SNDRV_PCM_INFO_SYNC_START |
4139                                  SNDRV_PCM_INFO_DOUBLE),
4140         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4141         .rates =                (SNDRV_PCM_RATE_32000 |
4142                                  SNDRV_PCM_RATE_44100 |
4143                                  SNDRV_PCM_RATE_48000 |
4144                                  SNDRV_PCM_RATE_64000 |
4145                                  SNDRV_PCM_RATE_88200 |
4146                                  SNDRV_PCM_RATE_96000),
4147         .rate_min =             32000,
4148         .rate_max =             96000,
4149         .channels_min =         14,
4150         .channels_max =         HDSP_MAX_CHANNELS,
4151         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4152         .period_bytes_min =     (64 * 4) * 10,
4153         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4154         .periods_min =          2,
4155         .periods_max =          2,
4156         .fifo_size =            0
4157 };
4158
4159 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4160 {
4161         .info =                 (SNDRV_PCM_INFO_MMAP |
4162                                  SNDRV_PCM_INFO_MMAP_VALID |
4163                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4164                                  SNDRV_PCM_INFO_SYNC_START),
4165         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4166         .rates =                (SNDRV_PCM_RATE_32000 |
4167                                  SNDRV_PCM_RATE_44100 |
4168                                  SNDRV_PCM_RATE_48000 |
4169                                  SNDRV_PCM_RATE_64000 |
4170                                  SNDRV_PCM_RATE_88200 |
4171                                  SNDRV_PCM_RATE_96000),
4172         .rate_min =             32000,
4173         .rate_max =             96000,
4174         .channels_min =         14,
4175         .channels_max =         HDSP_MAX_CHANNELS,
4176         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4177         .period_bytes_min =     (64 * 4) * 10,
4178         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4179         .periods_min =          2,
4180         .periods_max =          2,
4181         .fifo_size =            0
4182 };
4183
4184 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4185
4186 #define HDSP_PERIOD_SIZES sizeof(hdsp_period_sizes) / sizeof(hdsp_period_sizes[0])
4187
4188 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4189         .count = HDSP_PERIOD_SIZES,
4190         .list = hdsp_period_sizes,
4191         .mask = 0
4192 };
4193
4194 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4195
4196 #define HDSP_9632_SAMPLE_RATES sizeof(hdsp_9632_sample_rates) / sizeof(hdsp_9632_sample_rates[0])
4197
4198 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4199         .count = HDSP_9632_SAMPLE_RATES,
4200         .list = hdsp_9632_sample_rates,
4201         .mask = 0
4202 };
4203
4204 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4205                                         snd_pcm_hw_rule_t *rule)
4206 {
4207         hdsp_t *hdsp = rule->private;
4208         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4209         if (hdsp->io_type == H9632) {
4210                 unsigned int list[3];
4211                 list[0] = hdsp->qs_in_channels;
4212                 list[1] = hdsp->ds_in_channels;
4213                 list[2] = hdsp->ss_in_channels;
4214                 return snd_interval_list(c, 3, list, 0);
4215         } else {
4216                 unsigned int list[2];
4217                 list[0] = hdsp->ds_in_channels;
4218                 list[1] = hdsp->ss_in_channels;
4219                 return snd_interval_list(c, 2, list, 0);
4220         }
4221 }
4222
4223 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4224                                         snd_pcm_hw_rule_t *rule)
4225 {
4226         unsigned int list[3];
4227         hdsp_t *hdsp = rule->private;
4228         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4229         if (hdsp->io_type == H9632) {
4230                 list[0] = hdsp->qs_out_channels;
4231                 list[1] = hdsp->ds_out_channels;
4232                 list[2] = hdsp->ss_out_channels;
4233                 return snd_interval_list(c, 3, list, 0);
4234         } else {
4235                 list[0] = hdsp->ds_out_channels;
4236                 list[1] = hdsp->ss_out_channels;
4237         }
4238         return snd_interval_list(c, 2, list, 0);
4239 }
4240
4241 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4242                                              snd_pcm_hw_rule_t *rule)
4243 {
4244         hdsp_t *hdsp = rule->private;
4245         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4246         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4247         if (r->min > 96000 && hdsp->io_type == H9632) {
4248                 snd_interval_t t = {
4249                         .min = hdsp->qs_in_channels,
4250                         .max = hdsp->qs_in_channels,
4251                         .integer = 1,
4252                 };
4253                 return snd_interval_refine(c, &t);
4254         } else if (r->min > 48000 && r->max <= 96000) {
4255                 snd_interval_t t = {
4256                         .min = hdsp->ds_in_channels,
4257                         .max = hdsp->ds_in_channels,
4258                         .integer = 1,
4259                 };
4260                 return snd_interval_refine(c, &t);
4261         } else if (r->max < 64000) {
4262                 snd_interval_t t = {
4263                         .min = hdsp->ss_in_channels,
4264                         .max = hdsp->ss_in_channels,
4265                         .integer = 1,
4266                 };
4267                 return snd_interval_refine(c, &t);
4268         }
4269         return 0;
4270 }
4271
4272 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4273                                              snd_pcm_hw_rule_t *rule)
4274 {
4275         hdsp_t *hdsp = rule->private;
4276         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4277         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4278         if (r->min > 96000 && hdsp->io_type == H9632) {
4279                 snd_interval_t t = {
4280                         .min = hdsp->qs_out_channels,
4281                         .max = hdsp->qs_out_channels,
4282                         .integer = 1,
4283                 };
4284                 return snd_interval_refine(c, &t);
4285         } else if (r->min > 48000 && r->max <= 96000) {
4286                 snd_interval_t t = {
4287                         .min = hdsp->ds_out_channels,
4288                         .max = hdsp->ds_out_channels,
4289                         .integer = 1,
4290                 };
4291                 return snd_interval_refine(c, &t);
4292         } else if (r->max < 64000) {
4293                 snd_interval_t t = {
4294                         .min = hdsp->ss_out_channels,
4295                         .max = hdsp->ss_out_channels,
4296                         .integer = 1,
4297                 };
4298                 return snd_interval_refine(c, &t);
4299         }
4300         return 0;
4301 }
4302
4303 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4304                                              snd_pcm_hw_rule_t *rule)
4305 {
4306         hdsp_t *hdsp = rule->private;
4307         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4309         if (c->min >= hdsp->ss_out_channels) {
4310                 snd_interval_t t = {
4311                         .min = 32000,
4312                         .max = 48000,
4313                         .integer = 1,
4314                 };
4315                 return snd_interval_refine(r, &t);
4316         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4317                 snd_interval_t t = {
4318                         .min = 128000,
4319                         .max = 192000,
4320                         .integer = 1,
4321                 };
4322                 return snd_interval_refine(r, &t);
4323         } else if (c->max <= hdsp->ds_out_channels) {
4324                 snd_interval_t t = {
4325                         .min = 64000,
4326                         .max = 96000,
4327                         .integer = 1,
4328                 };
4329                 return snd_interval_refine(r, &t);
4330         }
4331         return 0;
4332 }
4333
4334 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4335                                              snd_pcm_hw_rule_t *rule)
4336 {
4337         hdsp_t *hdsp = rule->private;
4338         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4339         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4340         if (c->min >= hdsp->ss_in_channels) {
4341                 snd_interval_t t = {
4342                         .min = 32000,
4343                         .max = 48000,
4344                         .integer = 1,
4345                 };
4346                 return snd_interval_refine(r, &t);
4347         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4348                 snd_interval_t t = {
4349                         .min = 128000,
4350                         .max = 192000,
4351                         .integer = 1,
4352                 };
4353                 return snd_interval_refine(r, &t);
4354         } else if (c->max <= hdsp->ds_in_channels) {
4355                 snd_interval_t t = {
4356                         .min = 64000,
4357                         .max = 96000,
4358                         .integer = 1,
4359                 };
4360                 return snd_interval_refine(r, &t);
4361         }
4362         return 0;
4363 }
4364
4365 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4366 {
4367         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4368         unsigned long flags;
4369         snd_pcm_runtime_t *runtime = substream->runtime;
4370
4371         if (hdsp_check_for_iobox (hdsp)) {
4372                 return -EIO;
4373         }
4374
4375         if (hdsp_check_for_firmware(hdsp)) {
4376                 if (hdsp->state & HDSP_FirmwareCached) {
4377                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4378                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4379                         }
4380                 } else {
4381                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4382                 }
4383                 return -EIO;
4384         }
4385
4386         spin_lock_irqsave(&hdsp->lock, flags);
4387
4388         snd_pcm_set_sync(substream);
4389
4390         runtime->hw = snd_hdsp_playback_subinfo;
4391         runtime->dma_area = hdsp->playback_buffer;
4392         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4393
4394         if (hdsp->capture_substream == NULL) {
4395                 hdsp_stop_audio(hdsp);
4396                 hdsp_set_thru(hdsp, -1, 0);
4397         }
4398
4399         hdsp->playback_pid = current->pid;
4400         hdsp->playback_substream = substream;
4401
4402         spin_unlock_irqrestore(&hdsp->lock, flags);
4403
4404         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4405         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4406         if (hdsp->io_type == H9632) {
4407                 runtime->hw.channels_min = hdsp->qs_out_channels;
4408                 runtime->hw.channels_max = hdsp->ss_out_channels;
4409                 runtime->hw.rate_max = 192000;
4410                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4411                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4412         }
4413
4414         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4415                              snd_hdsp_hw_rule_out_channels, hdsp,
4416                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4417         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4418                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4419                              SNDRV_PCM_HW_PARAM_RATE, -1);
4420         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4421                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4422                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4423
4424         hdsp->creg_spdif_stream = hdsp->creg_spdif;
4425         hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4426         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4427                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4428         return 0;
4429 }
4430
4431 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4432 {
4433         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4434         unsigned long flags;
4435
4436         spin_lock_irqsave(&hdsp->lock, flags);
4437
4438         hdsp->playback_pid = -1;
4439         hdsp->playback_substream = NULL;
4440
4441         spin_unlock_irqrestore(&hdsp->lock, flags);
4442
4443         hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4444         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4445                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4446         return 0;
4447 }
4448
4449
4450 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4451 {
4452         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4453         unsigned long flags;
4454         snd_pcm_runtime_t *runtime = substream->runtime;
4455
4456         if (hdsp_check_for_iobox (hdsp)) {
4457                 return -EIO;
4458         }
4459
4460         if (hdsp_check_for_firmware(hdsp)) {
4461                 if (hdsp->state & HDSP_FirmwareCached) {
4462                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4463                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4464                         }
4465                 } else {
4466                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4467                 }
4468                 return -EIO;
4469         }
4470
4471         spin_lock_irqsave(&hdsp->lock, flags);
4472
4473         snd_pcm_set_sync(substream);
4474
4475         runtime->hw = snd_hdsp_capture_subinfo;
4476         runtime->dma_area = hdsp->capture_buffer;
4477         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4478
4479         if (hdsp->playback_substream == NULL) {
4480                 hdsp_stop_audio(hdsp);
4481                 hdsp_set_thru(hdsp, -1, 0);
4482         }
4483
4484         hdsp->capture_pid = current->pid;
4485         hdsp->capture_substream = substream;
4486
4487         spin_unlock_irqrestore(&hdsp->lock, flags);
4488
4489         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4490         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4491         if (hdsp->io_type == H9632) {
4492                 runtime->hw.channels_min = hdsp->qs_in_channels;
4493                 runtime->hw.channels_max = hdsp->ss_in_channels;
4494                 runtime->hw.rate_max = 192000;
4495                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4496                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4497         }
4498         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4499                              snd_hdsp_hw_rule_in_channels, hdsp,
4500                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4501         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4502                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4503                              SNDRV_PCM_HW_PARAM_RATE, -1);
4504         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4505                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4506                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4507         return 0;
4508 }
4509
4510 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4511 {
4512         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4513         unsigned long flags;
4514
4515         spin_lock_irqsave(&hdsp->lock, flags);
4516
4517         hdsp->capture_pid = -1;
4518         hdsp->capture_substream = NULL;
4519
4520         spin_unlock_irqrestore(&hdsp->lock, flags);
4521         return 0;
4522 }
4523
4524 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4525 {
4526         /* we have nothing to initialize but the call is required */
4527         return 0;
4528 }
4529
4530
4531 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4532 {
4533         hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4534         void __user *argp = (void __user *)arg;
4535
4536         switch (cmd) {
4537         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4538                 hdsp_peak_rms_t __user *peak_rms;
4539                 int i;
4540
4541                 if (hdsp->io_type == H9652) {
4542                         unsigned long rms_low, rms_high;
4543                         int doublespeed = 0;
4544                         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4545                                 doublespeed = 1;
4546                         peak_rms = (hdsp_peak_rms_t __user *)arg;
4547                         for (i = 0; i < 26; ++i) {
4548                                 if (!(doublespeed && (i & 4))) {
4549                                         if (copy_to_user_fromio((void __user *)peak_rms->input_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-i*4, 4) != 0)
4550                                                 return -EFAULT;
4551                                         if (copy_to_user_fromio((void __user *)peak_rms->playback_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4552                                                 return -EFAULT;
4553                                         if (copy_to_user_fromio((void __user *)peak_rms->output_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-2*(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4554                                                 return -EFAULT;
4555                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8) & 0xFFFFFF00;
4556                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8+4) & 0xFFFFFF00;
4557                                         rms_high += (rms_low >> 24);
4558                                         rms_low <<= 8;
4559                                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8, &rms_low, 4) != 0)
4560                                                 return -EFAULT;
4561                                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, &rms_high, 4) != 0)
4562                                                 return -EFAULT;
4563                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4564                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4565                                         rms_high += (rms_low >> 24);
4566                                         rms_low <<= 8;
4567                                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, &rms_low, 4) != 0)
4568                                                 return -EFAULT;
4569                                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, &rms_high, 4) != 0)
4570                                                 return -EFAULT;
4571                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4572                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4573                                         rms_high += (rms_low >> 24);
4574                                         rms_low <<= 8;
4575                                         if (copy_to_user((void __user *)peak_rms->output_rms+i*8, &rms_low, 4) != 0)
4576                                                 return -EFAULT;
4577                                         if (copy_to_user((void __user *)peak_rms->output_rms+i*8+4, &rms_high, 4) != 0)
4578                                                 return -EFAULT;
4579                                 }
4580                         }
4581                         return 0;
4582                 }
4583                 if (hdsp->io_type == H9632) {
4584                         int j;
4585                         hdsp_9632_meters_t *m;
4586                         int doublespeed = 0;
4587                         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4588                                 doublespeed = 1;
4589                         m = (hdsp_9632_meters_t *)(hdsp->iobase+HDSP_9632_metersBase);
4590                         peak_rms = (hdsp_peak_rms_t __user *)arg;
4591                         for (i = 0, j = 0; i < 16; ++i, ++j) {
4592                                 if (copy_to_user((void __user *)peak_rms->input_peaks+i*4, &(m->input_peak[j]), 4) != 0)
4593                                         return -EFAULT;
4594                                 if (copy_to_user((void __user *)peak_rms->playback_peaks+i*4, &(m->playback_peak[j]), 4) != 0)
4595                                         return -EFAULT;
4596                                 if (copy_to_user((void __user *)peak_rms->output_peaks+i*4, &(m->output_peak[j]), 4) != 0)
4597                                         return -EFAULT;
4598                                 if (copy_to_user((void __user *)peak_rms->input_rms+i*8, &(m->input_rms_low[j]), 4) != 0)
4599                                         return -EFAULT;
4600                                 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, &(m->playback_rms_low[j]), 4) != 0)
4601                                         return -EFAULT;
4602                                 if (copy_to_user((void __user *)peak_rms->output_rms+i*8, &(m->output_rms_low[j]), 4) != 0)
4603                                         return -EFAULT;
4604                                 if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, &(m->input_rms_high[j]), 4) != 0)
4605                                         return -EFAULT;
4606                                 if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, &(m->playback_rms_high[j]), 4) != 0)
4607                                         return -EFAULT;
4608                                 if (copy_to_user((void __user *)peak_rms->output_rms+i*8+4, &(m->output_rms_high[j]), 4) != 0)
4609                                         return -EFAULT;
4610                                 if (doublespeed && i == 3) i += 4;
4611                         }
4612                         return 0;
4613                 }
4614                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4615                         snd_printk("firmware needs to be uploaded to the card.\n");
4616                         return -EINVAL;
4617                 }
4618                 peak_rms = (hdsp_peak_rms_t __user *)arg;
4619                 for (i = 0; i < 26; ++i) {
4620                     if (copy_to_user((void __user *)peak_rms->playback_peaks+i*4, (void *)hdsp->iobase+HDSP_playbackPeakLevel+i*4, 4) != 0)
4621                             return -EFAULT;
4622                     if (copy_to_user((void __user *)peak_rms->input_peaks+i*4, (void *)hdsp->iobase+HDSP_inputPeakLevel+i*4, 4) != 0)
4623                             return -EFAULT;
4624                 }
4625                 for (i = 0; i < 26; ++i) {
4626                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8+4, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8, 4) != 0)
4627                                 return -EFAULT;
4628                         if (copy_to_user((void __user *)peak_rms->playback_rms+i*8, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8+4, 4) != 0)
4629                                 return -EFAULT;
4630                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8+4, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8, 4) != 0)
4631                                 return -EFAULT;
4632                         if (copy_to_user((void __user *)peak_rms->input_rms+i*8, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8+4, 4) != 0)
4633                                 return -EFAULT;
4634                 }
4635                 for (i = 0; i < 28; ++i) {
4636                     if (copy_to_user((void __user *)peak_rms->output_peaks+i*4, (void *)hdsp->iobase+HDSP_outputPeakLevel+i*4, 4) != 0)
4637                             return -EFAULT;
4638                 }
4639                 break;
4640         }
4641         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4642                 hdsp_config_info_t info;
4643                 unsigned long flags;
4644                 int i;
4645
4646                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4647                         snd_printk("Firmware needs to be uploaded to the card.\n");
4648                         return -EINVAL;
4649                 }
4650                 spin_lock_irqsave(&hdsp->lock, flags);
4651                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4652                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4653                 if (hdsp->io_type != H9632) {
4654                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4655                 }
4656                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4657                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4658                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4659                 }
4660                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4661                 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4662                 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4663                 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4664                 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4665                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4666                 info.system_sample_rate = hdsp->system_sample_rate;
4667                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4668                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4669                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4670                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4671                 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4672                 info.passthru = (unsigned char)hdsp->passthru;
4673                 if (hdsp->io_type == H9632) {
4674                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4675                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4676                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4677                         info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4678
4679                 }
4680                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4681                         info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4682                 }
4683                 spin_unlock_irqrestore(&hdsp->lock, flags);
4684                 if (copy_to_user(argp, &info, sizeof(info)))
4685                         return -EFAULT;
4686                 break;
4687         }
4688         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4689                 hdsp_9632_aeb_t h9632_aeb;
4690
4691                 if (hdsp->io_type != H9632) return -EINVAL;
4692                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4693                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4694                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4695                         return -EFAULT;
4696                 break;
4697         }
4698         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4699                 hdsp_version_t hdsp_version;
4700                 int err;
4701
4702                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4703                 if (hdsp->io_type == Undefined) {
4704                         if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4705                                 return err;
4706                         }
4707                 }
4708                 hdsp_version.io_type = hdsp->io_type;
4709                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4710                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4711                         return -EFAULT;
4712                 }
4713                 break;
4714         }
4715         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4716                 hdsp_firmware_t __user *firmware;
4717                 unsigned long __user *firmware_data;
4718                 int err;
4719
4720                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4721                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4722                 if (hdsp->io_type == Undefined) return -EINVAL;
4723
4724                 snd_printk("initializing firmware upload\n");
4725                 firmware = (hdsp_firmware_t __user *)argp;
4726
4727                 if (get_user(firmware_data, &firmware->firmware_data)) {
4728                         return -EFAULT;
4729                 }
4730
4731                 if (hdsp_check_for_iobox (hdsp)) {
4732                         return -EIO;
4733                 }
4734
4735                 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(unsigned long)*24413) != 0) {
4736                         return -EFAULT;
4737                 }
4738
4739                 hdsp->state |= HDSP_FirmwareCached;
4740
4741                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4742                         return err;
4743                 }
4744
4745                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4746                         snd_hdsp_initialize_channels(hdsp);
4747
4748                         snd_hdsp_initialize_midi_flush(hdsp);
4749
4750                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4751                                 snd_printk("error creating alsa devices\n");
4752                             return err;
4753                         }
4754                 }
4755                 break;
4756         }
4757         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4758                 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4759                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4760                         return -EFAULT;
4761                 break;
4762         }
4763         default:
4764                 return -EINVAL;
4765         }
4766         return 0;
4767 }
4768
4769 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4770         .open =         snd_hdsp_playback_open,
4771         .close =        snd_hdsp_playback_release,
4772         .ioctl =        snd_hdsp_ioctl,
4773         .hw_params =    snd_hdsp_hw_params,
4774         .prepare =      snd_hdsp_prepare,
4775         .trigger =      snd_hdsp_trigger,
4776         .pointer =      snd_hdsp_hw_pointer,
4777         .copy =         snd_hdsp_playback_copy,
4778         .silence =      snd_hdsp_hw_silence,
4779 };
4780
4781 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4782         .open =         snd_hdsp_capture_open,
4783         .close =        snd_hdsp_capture_release,
4784         .ioctl =        snd_hdsp_ioctl,
4785         .hw_params =    snd_hdsp_hw_params,
4786         .prepare =      snd_hdsp_prepare,
4787         .trigger =      snd_hdsp_trigger,
4788         .pointer =      snd_hdsp_hw_pointer,
4789         .copy =         snd_hdsp_capture_copy,
4790 };
4791
4792 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4793                                            hdsp_t *hdsp)
4794 {
4795         snd_hwdep_t *hw;
4796         int err;
4797
4798         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4799                 return err;
4800
4801         hdsp->hwdep = hw;
4802         hw->private_data = hdsp;
4803         strcpy(hw->name, "HDSP hwdep interface");
4804
4805         hw->ops.open = snd_hdsp_hwdep_dummy_op;
4806         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4807         hw->ops.release = snd_hdsp_hwdep_dummy_op;
4808
4809         return 0;
4810 }
4811
4812 static int __devinit snd_hdsp_create_pcm(snd_card_t *card,
4813                                          hdsp_t *hdsp)
4814 {
4815         snd_pcm_t *pcm;
4816         int err;
4817
4818         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4819                 return err;
4820
4821         hdsp->pcm = pcm;
4822         pcm->private_data = hdsp;
4823         strcpy(pcm->name, hdsp->card_name);
4824
4825         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4826         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4827
4828         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4829
4830         return 0;
4831 }
4832
4833 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4834 {
4835         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4836         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4837 }
4838
4839 static inline void snd_hdsp_9652_disable_mixer (hdsp_t *hdsp)
4840 {
4841         hdsp->control2_register &= ~HDSP_9652_ENABLE_MIXER;
4842         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4843 }
4844
4845 static inline int snd_hdsp_enable_io (hdsp_t *hdsp)
4846 {
4847         int i;
4848
4849         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4850                 return -EIO;
4851         }
4852
4853         for (i = 0; i < hdsp->max_channels; ++i) {
4854                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4855                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4856         }
4857
4858         return 0;
4859 }
4860
4861 static inline void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4862 {
4863         int status, aebi_channels, aebo_channels;
4864
4865         switch (hdsp->io_type) {
4866         case Digiface:
4867                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4868                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4869                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4870                 break;
4871
4872         case H9652:
4873                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4874                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4875                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4876                 break;
4877
4878         case H9632:
4879                 status = hdsp_read(hdsp, HDSP_statusRegister);
4880                 /* HDSP_AEBx bits are low when AEB are connected */
4881                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4882                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4883                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4884                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4885                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4886                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4887                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4888                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4889                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4890                 break;
4891
4892         case Multiface:
4893                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4894                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4895                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4896                 break;
4897
4898         default:
4899                 /* should never get here */
4900                 break;
4901         }
4902 }
4903
4904 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4905 {
4906         snd_hdsp_flush_midi_input (hdsp, 0);
4907         snd_hdsp_flush_midi_input (hdsp, 1);
4908 }
4909
4910 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4911 {
4912         int err;
4913
4914         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4915                 snd_printk("Error creating pcm interface\n");
4916                 return err;
4917         }
4918
4919
4920         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4921                 snd_printk("Error creating first midi interface\n");
4922                 return err;
4923         }
4924
4925
4926         if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4927                 snd_printk("Error creating second midi interface\n");
4928                 return err;
4929         }
4930
4931         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4932                 snd_printk("Error creating ctl interface\n");
4933                 return err;
4934         }
4935
4936         snd_hdsp_proc_init(hdsp);
4937
4938         hdsp->system_sample_rate = -1;
4939         hdsp->playback_pid = -1;
4940         hdsp->capture_pid = -1;
4941         hdsp->capture_substream = NULL;
4942         hdsp->playback_substream = NULL;
4943
4944         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4945                 snd_printk("Error setting default values\n");
4946                 return err;
4947         }
4948
4949         if (!(hdsp->state & HDSP_InitializationComplete)) {
4950                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4951                         hdsp->port, hdsp->irq);
4952
4953                 if ((err = snd_card_register(card)) < 0) {
4954                         snd_printk("error registering card\n");
4955                         return err;
4956                 }
4957                 hdsp->state |= HDSP_InitializationComplete;
4958         }
4959
4960         return 0;
4961 }
4962
4963 static int __devinit snd_hdsp_create(snd_card_t *card,
4964                                      hdsp_t *hdsp,
4965                                      int precise_ptr)
4966 {
4967         struct pci_dev *pci = hdsp->pci;
4968         int err;
4969         int is_9652 = 0;
4970         int is_9632 = 0;
4971
4972         hdsp->irq = -1;
4973         hdsp->state = 0;
4974         hdsp->midi[0].rmidi = 0;
4975         hdsp->midi[1].rmidi = 0;
4976         hdsp->midi[0].input = 0;
4977         hdsp->midi[1].input = 0;
4978         hdsp->midi[0].output = 0;
4979         hdsp->midi[1].output = 0;
4980         spin_lock_init(&hdsp->midi[0].lock);
4981         spin_lock_init(&hdsp->midi[1].lock);
4982         hdsp->iobase = 0;
4983         hdsp->res_port = 0;
4984         hdsp->control_register = 0;
4985         hdsp->control2_register = 0;
4986         hdsp->io_type = Undefined;
4987         hdsp->max_channels = 26;
4988
4989         hdsp->card = card;
4990
4991         spin_lock_init(&hdsp->lock);
4992
4993         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4994
4995         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4996
4997         /* From Martin Bjoernsen :
4998             "It is important that the card's latency timer register in
4999             the PCI configuration space is set to a value much larger
5000             than 0 by the computer's BIOS or the driver.
5001             The windows driver always sets this 8 bit register [...]
5002             to its maximum 255 to avoid problems with some computers."
5003         */
5004         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5005
5006         strcpy(card->driver, "H-DSP");
5007         strcpy(card->mixername, "Xilinx FPGA");
5008
5009         switch (hdsp->firmware_rev & 0xff) {
5010         case 0xa:
5011         case 0xb:
5012         case 0x32:
5013                 hdsp->card_name = "RME Hammerfall DSP";
5014                 break;
5015
5016         case 0x64:
5017         case 0x65:
5018         case 0x68:
5019                 hdsp->card_name = "RME HDSP 9652";
5020                 is_9652 = 1;
5021                 break;
5022         case 0x96:
5023         case 0x97:
5024                 hdsp->card_name = "RME HDSP 9632";
5025                 hdsp->max_channels = 16;
5026                 is_9632 = 1;
5027                 break;
5028         default:
5029                 return -ENODEV;
5030         }
5031
5032         if ((err = pci_enable_device(pci)) < 0) {
5033                 return err;
5034         }
5035
5036         pci_set_master(hdsp->pci);
5037
5038         hdsp->port = pci_resource_start(pci, 0);
5039
5040         if ((hdsp->res_port = request_mem_region(hdsp->port, HDSP_IO_EXTENT, "hdsp")) == NULL) {
5041                 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5042                 return -EBUSY;
5043         }
5044
5045         if ((hdsp->iobase = (unsigned long) ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == 0) {
5046                 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5047                 return -EBUSY;
5048         }
5049
5050         if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5051                 snd_printk("unable to use IRQ %d\n", pci->irq);
5052                 return -EBUSY;
5053         }
5054
5055         hdsp->irq = pci->irq;
5056         hdsp->precise_ptr = precise_ptr;
5057
5058         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5059                 return err;
5060         }
5061
5062         if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) {
5063                 /* no iobox connected, we defer initialization */
5064                 snd_printk("card initialization pending : waiting for firmware\n");
5065                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5066                         return err;
5067                 }
5068                 return 0;
5069         }
5070
5071         if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5072                 return err;
5073         }
5074
5075         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5076                 snd_printk("card initialization pending : waiting for firmware\n");
5077                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5078                         return err;
5079                 }
5080                 return 0;
5081         }
5082
5083         snd_printk("Firmware already loaded, initializing card.\n");
5084
5085         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5086                 hdsp->io_type = Multiface;
5087         } else {
5088                 hdsp->io_type = Digiface;
5089         }
5090
5091         if (is_9652) {
5092                 hdsp->io_type = H9652;
5093         }
5094
5095         if (is_9632) {
5096                 hdsp->io_type = H9632;
5097         }
5098
5099         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5100                 return err;
5101         }
5102
5103         snd_hdsp_initialize_channels(hdsp);
5104         snd_hdsp_initialize_midi_flush(hdsp);
5105
5106         hdsp->state |= HDSP_FirmwareLoaded;
5107
5108         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5109                 return err;
5110         }
5111
5112         return 0;
5113 }
5114
5115 static int snd_hdsp_free(hdsp_t *hdsp)
5116 {
5117         if (hdsp->res_port) {
5118                 /* stop the audio, and cancel all interrupts */
5119                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5120                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5121         }
5122
5123         if (hdsp->irq >= 0)
5124                 free_irq(hdsp->irq, (void *)hdsp);
5125
5126         snd_hdsp_free_buffers(hdsp);
5127
5128         if (hdsp->iobase)
5129                 iounmap((void *) hdsp->iobase);
5130
5131         if (hdsp->res_port) {
5132                 release_resource(hdsp->res_port);
5133                 kfree_nocheck(hdsp->res_port);
5134         }
5135
5136         return 0;
5137 }
5138
5139 static void snd_hdsp_card_free(snd_card_t *card)
5140 {
5141         hdsp_t *hdsp = (hdsp_t *) card->private_data;
5142
5143         if (hdsp)
5144                 snd_hdsp_free(hdsp);
5145 }
5146
5147 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5148                                     const struct pci_device_id *pci_id)
5149 {
5150         static int dev;
5151         hdsp_t *hdsp;
5152         snd_card_t *card;
5153         int err;
5154
5155         if (dev >= SNDRV_CARDS)
5156                 return -ENODEV;
5157         if (!enable[dev]) {
5158                 dev++;
5159                 return -ENOENT;
5160         }
5161
5162         if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5163                 return -ENOMEM;
5164
5165         hdsp = (hdsp_t *) card->private_data;
5166         card->private_free = snd_hdsp_card_free;
5167         hdsp->dev = dev;
5168         hdsp->pci = pci;
5169         snd_card_set_dev(card, &pci->dev);
5170
5171         if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
5172                 snd_card_free(card);
5173                 return err;
5174         }
5175
5176         strcpy(card->shortname, "Hammerfall DSP");
5177         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5178                 hdsp->port, hdsp->irq);
5179
5180         if ((err = snd_card_register(card)) < 0) {
5181                 snd_card_free(card);
5182                 return err;
5183         }
5184         pci_set_drvdata(pci, card);
5185         dev++;
5186         return 0;
5187 }
5188
5189 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5190 {
5191         snd_card_free(pci_get_drvdata(pci));
5192         pci_set_drvdata(pci, NULL);
5193 }
5194
5195 static struct pci_driver driver = {
5196         .name =     "RME Hammerfall DSP",
5197         .id_table = snd_hdsp_ids,
5198         .probe =    snd_hdsp_probe,
5199         .remove = __devexit_p(snd_hdsp_remove),
5200 };
5201
5202 static int __init alsa_card_hdsp_init(void)
5203 {
5204         return pci_module_init(&driver);
5205 }
5206
5207 static void __exit alsa_card_hdsp_exit(void)
5208 {
5209         pci_unregister_driver(&driver);
5210 }
5211
5212 module_init(alsa_card_hdsp_init)
5213 module_exit(alsa_card_hdsp_exit)