sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <sound/driver.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30
  31 #include <sound/core.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/info.h>
  35 #include <sound/asoundef.h>
  36 #include <sound/rawmidi.h>
  37 #include <sound/hwdep.h>
  38 #define SNDRV_GET_ID
  39 #include <sound/initval.h>
  40 #include <sound/hdsp.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/current.h>
  44 #include <asm/io.h>
  45
  46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  49 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
  50 static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
  51
  52 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  54 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  55 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
  56 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  57 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  58 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  59 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  60 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  61 MODULE_PARM(precise_ptr, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  62 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
  63 MODULE_PARM_SYNTAX(precise_ptr, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
  64 MODULE_PARM(line_outs_monitor,"1-" __MODULE_STRING(SNDRV_CARDS) "i");
  65 MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
  66 MODULE_PARM_SYNTAX(line_outs_monitor, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
  67 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  68 MODULE_DESCRIPTION("RME Hammerfall DSP");
  69 MODULE_LICENSE("GPL");
  70 MODULE_CLASSES("{sound}");
  71 MODULE_DEVICES("{{RME Hammerfall-DSP},"
  72                 "{RME HDSP-9652},"
  73                 "{RME HDSP-9632}}");
  74
  75 #define HDSP_MAX_CHANNELS        26
  76 #define HDSP_MAX_DS_CHANNELS     14
  77 #define HDSP_MAX_QS_CHANNELS     8
  78 #define DIGIFACE_SS_CHANNELS     26
  79 #define DIGIFACE_DS_CHANNELS     14
  80 #define MULTIFACE_SS_CHANNELS    18
  81 #define MULTIFACE_DS_CHANNELS    14
  82 #define H9652_SS_CHANNELS        26
  83 #define H9652_DS_CHANNELS        14
  84 /* This does not include possible Analog Extension Boards
  85    AEBs are detected at card initialization
  86 */
  87 #define H9632_SS_CHANNELS        12
  88 #define H9632_DS_CHANNELS        8
  89 #define H9632_QS_CHANNELS        4
  90
  91 /* Write registers. These are defined as byte-offsets from the iobase value.
  92  */
  93 #define HDSP_resetPointer               0
  94 #define HDSP_outputBufferAddress        32
  95 #define HDSP_inputBufferAddress         36
  96 #define HDSP_controlRegister            64
  97 #define HDSP_interruptConfirmation      96
  98 #define HDSP_outputEnable               128
  99 #define HDSP_control2Reg                256
 100 #define HDSP_midiDataOut0               352
 101 #define HDSP_midiDataOut1               356
 102 #define HDSP_fifoData                   368
 103 #define HDSP_inputEnable                384
 104
 105 /* Read registers. These are defined as byte-offsets from the iobase value
 106  */
 107
 108 #define HDSP_statusRegister    0
 109 #define HDSP_timecode        128
 110 #define HDSP_status2Register 192
 111 #define HDSP_midiDataOut0    352
 112 #define HDSP_midiDataOut1    356
 113 #define HDSP_midiDataIn0     360
 114 #define HDSP_midiDataIn1     364
 115 #define HDSP_midiStatusOut0  384
 116 #define HDSP_midiStatusOut1  388
 117 #define HDSP_midiStatusIn0   392
 118 #define HDSP_midiStatusIn1   396
 119 #define HDSP_fifoStatus      400
 120
 121 /* the meters are regular i/o-mapped registers, but offset
 122    considerably from the rest. the peak registers are reset
 123    when read; the least-significant 4 bits are full-scale counters;
 124    the actual peak value is in the most-significant 24 bits.
 125 */
 126
 127 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 128 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 129 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 130 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 131 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 132
 133
 134 /* This is for H9652 cards
 135    Peak values are read downward from the base
 136    Rms values are read upward
 137    There are rms values for the outputs too
 138    26*3 values are read in ss mode
 139    14*3 in ds mode, with no gap between values
 140 */
 141 #define HDSP_9652_peakBase      7164
 142 #define HDSP_9652_rmsBase       4096
 143
 144 /* c.f. the hdsp_9632_meters_t struct */
 145 #define HDSP_9632_metersBase    4096
 146
 147 #define HDSP_IO_EXTENT     7168
 148
 149 /* control2 register bits */
 150
 151 #define HDSP_TMS                0x01
 152 #define HDSP_TCK                0x02
 153 #define HDSP_TDI                0x04
 154 #define HDSP_JTAG               0x08
 155 #define HDSP_PWDN               0x10
 156 #define HDSP_PROGRAM            0x020
 157 #define HDSP_CONFIG_MODE_0      0x040
 158 #define HDSP_CONFIG_MODE_1      0x080
 159 #define HDSP_VERSION_BIT        0x100
 160 #define HDSP_BIGENDIAN_MODE     0x200
 161 #define HDSP_RD_MULTIPLE        0x400
 162 #define HDSP_9652_ENABLE_MIXER  0x800
 163 #define HDSP_TDO                0x10000000
 164
 165 #define HDSP_S_PROGRAM          (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 166 #define HDSP_S_LOAD             (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 167
 168 /* Control Register bits */
 169
 170 #define HDSP_Start                (1<<0)  /* start engine */
 171 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 172 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 173 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 174 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 175 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 176 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 177 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 178 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 179 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 180 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 181 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 182 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 183 #define HDSP_SyncRef2             (1<<13)
 184 #define HDSP_SPDIFInputSelect0    (1<<14)
 185 #define HDSP_SPDIFInputSelect1    (1<<15)
 186 #define HDSP_SyncRef0             (1<<16)
 187 #define HDSP_SyncRef1             (1<<17)
 188 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 189 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 190 #define HDSP_Midi0InterruptEnable (1<<22)
 191 #define HDSP_Midi1InterruptEnable (1<<23)
 192 #define HDSP_LineOut              (1<<24)
 193 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 194 #define HDSP_ADGain1              (1<<26)
 195 #define HDSP_DAGain0              (1<<27)
 196 #define HDSP_DAGain1              (1<<28)
 197 #define HDSP_PhoneGain0           (1<<29)
 198 #define HDSP_PhoneGain1           (1<<30)
 199 #define HDSP_QuadSpeed            (1<<31)
 200
 201 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 202 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 203 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 204 #define HDSP_ADGainLowGain     0
 205
 206 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 207 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 208 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 209 #define HDSP_DAGainMinus10dBV    0
 210
 211 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 212 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 213 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 214 #define HDSP_PhoneGainMinus12dB  0
 215
 216 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 217 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 218
 219 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 220 #define HDSP_SPDIFInputADAT1    0
 221 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 222 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 223 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 224
 225 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 226 #define HDSP_SyncRef_ADAT1       0
 227 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 228 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 229 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 230 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 231 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 232
 233 /* Sample Clock Sources */
 234
 235 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 236 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 237 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 238 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 239 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 240 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 241 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 242 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 243 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 244 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 245
 246 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 247
 248 #define HDSP_SYNC_FROM_WORD      0
 249 #define HDSP_SYNC_FROM_SPDIF     1
 250 #define HDSP_SYNC_FROM_ADAT1     2
 251 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 252 #define HDSP_SYNC_FROM_ADAT2     4
 253 #define HDSP_SYNC_FROM_ADAT3     5
 254
 255 /* SyncCheck status */
 256
 257 #define HDSP_SYNC_CHECK_NO_LOCK 0
 258 #define HDSP_SYNC_CHECK_LOCK    1
 259 #define HDSP_SYNC_CHECK_SYNC    2
 260
 261 /* AutoSync references - used by "autosync_ref" control switch */
 262
 263 #define HDSP_AUTOSYNC_FROM_WORD      0
 264 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 265 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 266 #define HDSP_AUTOSYNC_FROM_NONE      3
 267 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 268 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 269 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 270
 271 /* Possible sources of S/PDIF input */
 272
 273 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 274 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 275 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 276 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 277
 278 #define HDSP_Frequency32KHz    HDSP_Frequency0
 279 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 280 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 281 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 282 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 283 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 284 /* For H9632 cards */
 285 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 286 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 287 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 288
 289 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 290 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 291
 292 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 293 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 294
 295 /* Status Register bits */
 296
 297 #define HDSP_audioIRQPending    (1<<0)
 298 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 299 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 300 #define HDSP_Lock1              (1<<2)
 301 #define HDSP_Lock0              (1<<3)
 302 #define HDSP_SPDIFSync          (1<<4)
 303 #define HDSP_TimecodeLock       (1<<5)
 304 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 305 #define HDSP_Sync2              (1<<16)
 306 #define HDSP_Sync1              (1<<17)
 307 #define HDSP_Sync0              (1<<18)
 308 #define HDSP_DoubleSpeedStatus  (1<<19)
 309 #define HDSP_ConfigError        (1<<20)
 310 #define HDSP_DllError           (1<<21)
 311 #define HDSP_spdifFrequency0    (1<<22)
 312 #define HDSP_spdifFrequency1    (1<<23)
 313 #define HDSP_spdifFrequency2    (1<<24)
 314 #define HDSP_SPDIFErrorFlag     (1<<25)
 315 #define HDSP_BufferID           (1<<26)
 316 #define HDSP_TimecodeSync       (1<<27)
 317 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 318 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 319 #define HDSP_midi0IRQPending    (1<<30)
 320 #define HDSP_midi1IRQPending    (1<<31)
 321
 322 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 323
 324 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 325 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 326 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 327
 328 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 329 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 330 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 331
 332 /* This is for H9632 cards */
 333 #define HDSP_spdifFrequency128KHz   HDSP_spdifFrequencyMask
 334 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 335 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 336
 337 /* Status2 Register bits */
 338
 339 #define HDSP_version0     (1<<0)
 340 #define HDSP_version1     (1<<1)
 341 #define HDSP_version2     (1<<2)
 342 #define HDSP_wc_lock      (1<<3)
 343 #define HDSP_wc_sync      (1<<4)
 344 #define HDSP_inp_freq0    (1<<5)
 345 #define HDSP_inp_freq1    (1<<6)
 346 #define HDSP_inp_freq2    (1<<7)
 347 #define HDSP_SelSyncRef0  (1<<8)
 348 #define HDSP_SelSyncRef1  (1<<9)
 349 #define HDSP_SelSyncRef2  (1<<10)
 350
 351 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 352
 353 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 354 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 355 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 356 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 357 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 358 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 359 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 360 /* FIXME : more values for 9632 cards ? */
 361
 362 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 363 #define HDSP_SelSyncRef_ADAT1      0
 364 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 365 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 366 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 367 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 368 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 369
 370 /* Card state flags */
 371
 372 #define HDSP_InitializationComplete  (1<<0)
 373 #define HDSP_FirmwareLoaded          (1<<1)
 374 #define HDSP_FirmwareCached          (1<<2)
 375
 376 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 377
 378 #define HDSP_LONG_WAIT   5000
 379 #define HDSP_SHORT_WAIT  30
 380
 381 #define UNITY_GAIN                       32768
 382 #define MINUS_INFINITY_GAIN              0
 383
 384 #ifndef PCI_VENDOR_ID_XILINX
 385 #define PCI_VENDOR_ID_XILINX            0x10ee
 386 #endif
 387 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
 388 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
 389 #endif
 390
 391 /* the size of a substream (1 mono data stream) */
 392
 393 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 394 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 395
 396 /* the size of the area we need to allocate for DMA transfers. the
 397    size is the same regardless of the number of channels - the
 398    Multiface still uses the same memory area.
 399
 400    Note that we allocate 1 more channel than is apparently needed
 401    because the h/w seems to write 1 byte beyond the end of the last
 402    page. Sigh.
 403 */
 404
 405 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 406 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 407
 408 typedef struct _hdsp             hdsp_t;
 409 typedef struct _hdsp_midi        hdsp_midi_t;
 410 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
 411
 412 struct _hdsp_9632_meters {
 413     u32 input_peak[16];
 414     u32 playback_peak[16];
 415     u32 output_peak[16];
 416     u32 xxx_peak[16];
 417     u32 padding[64];
 418     u32 input_rms_low[16];
 419     u32 playback_rms_low[16];
 420     u32 output_rms_low[16];
 421     u32 xxx_rms_low[16];
 422     u32 input_rms_high[16];
 423     u32 playback_rms_high[16];
 424     u32 output_rms_high[16];
 425     u32 xxx_rms_high[16];
 426 };
 427
 428 struct _hdsp_midi {
 429     hdsp_t                  *hdsp;
 430     int                      id;
 431     snd_rawmidi_t           *rmidi;
 432     snd_rawmidi_substream_t *input;
 433     snd_rawmidi_substream_t *output;
 434     char                     istimer; /* timer in use */
 435     struct timer_list        timer;
 436     spinlock_t               lock;
 437     int                      pending;
 438 };
 439
 440 struct _hdsp {
 441         spinlock_t            lock;
 442         snd_pcm_substream_t  *capture_substream;
 443         snd_pcm_substream_t  *playback_substream;
 444         hdsp_midi_t           midi[2];
 445         struct tasklet_struct midi_tasklet;
 446         int                   precise_ptr;
 447         u32                   control_register;      /* cached value */
 448         u32                   control2_register;     /* cached value */
 449         u32                   creg_spdif;
 450         u32                   creg_spdif_stream;
 451         char                 *card_name;             /* digiface/multiface */
 452         HDSP_IO_Type          io_type;               /* ditto, but for code use */
 453         unsigned short        firmware_rev;
 454         unsigned short        state;                 /* stores state bits */
 455         u32                   firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
 456         size_t                period_bytes;          /* guess what this is */
 457         unsigned char         max_channels;
 458         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 459         unsigned char         ds_in_channels;
 460         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 461         unsigned char         qs_out_channels;
 462         unsigned char         ds_out_channels;
 463         unsigned char         ss_out_channels;
 464         void                 *capture_buffer_unaligned;  /* original buffer addresses */
 465         void                 *playback_buffer_unaligned; /* original buffer addresses */
 466         unsigned char        *capture_buffer;       /* suitably aligned address */
 467         unsigned char        *playback_buffer;      /* suitably aligned address */
 468         dma_addr_t            capture_buffer_addr;
 469         dma_addr_t            playback_buffer_addr;
 470         pid_t                 capture_pid;
 471         pid_t                 playback_pid;
 472         int                   running;
 473         int                   passthru;              /* non-zero if doing pass-thru */
 474         int                   system_sample_rate;
 475         char                 *channel_map;
 476         int                   dev;
 477         int                   irq;
 478         unsigned long         port;
 479         struct resource      *res_port;
 480         unsigned long         iobase;
 481         snd_card_t           *card;
 482         snd_pcm_t            *pcm;
 483         snd_hwdep_t          *hwdep;
 484         struct pci_dev       *pci;
 485         snd_kcontrol_t       *spdif_ctl;
 486         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 487 };
 488
 489 /* These tables map the ALSA channels 1..N to the channels that we
 490    need to use in order to find the relevant channel buffer. RME
 491    refer to this kind of mapping as between "the ADAT channel and
 492    the DMA channel." We index it using the logical audio channel,
 493    and the value is the DMA channel (i.e. channel buffer number)
 494    where the data for that channel can be read/written from/to.
 495 */
 496
 497 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 498         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 499         18, 19, 20, 21, 22, 23, 24, 25
 500 };
 501
 502 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 503         /* Analog */
 504         0, 1, 2, 3, 4, 5, 6, 7,
 505         /* ADAT 2 */
 506         16, 17, 18, 19, 20, 21, 22, 23,
 507         /* SPDIF */
 508         24, 25,
 509         -1, -1, -1, -1, -1, -1, -1, -1
 510 };
 511
 512 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 513         /* ADAT channels are remapped */
 514         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 515         /* channels 12 and 13 are S/PDIF */
 516         24, 25,
 517         /* others don't exist */
 518         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 519 };
 520
 521 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 522         /* ADAT channels */
 523         0, 1, 2, 3, 4, 5, 6, 7,
 524         /* SPDIF */
 525         8, 9,
 526         /* Analog */
 527         10, 11,
 528         /* AO4S-192 and AI4S-192 extension boards */
 529         12, 13, 14, 15,
 530         /* others don't exist */
 531         -1, -1, -1, -1, -1, -1, -1, -1,
 532         -1, -1
 533 };
 534
 535 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 536         /* ADAT */
 537         1, 3, 5, 7,
 538         /* SPDIF */
 539         8, 9,
 540         /* Analog */
 541         10, 11,
 542         /* AO4S-192 and AI4S-192 extension boards */
 543         12, 13, 14, 15,
 544         /* others don't exist */
 545         -1, -1, -1, -1, -1, -1, -1, -1,
 546         -1, -1, -1, -1, -1, -1
 547 };
 548
 549 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 550         /* ADAT is disabled in this mode */
 551         /* SPDIF */
 552         8, 9,
 553         /* Analog */
 554         10, 11,
 555         /* AO4S-192 and AI4S-192 extension boards */
 556         12, 13, 14, 15,
 557         /* others don't exist */
 558         -1, -1, -1, -1, -1, -1, -1, -1,
 559         -1, -1, -1, -1, -1, -1, -1, -1,
 560         -1, -1
 561 };
 562
 563 #define HDSP_PREALLOCATE_MEMORY /* via module snd-hdsp_mem */
 564
 565 #ifdef HDSP_PREALLOCATE_MEMORY
 566 static void *snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size, dma_addr_t *addrp, int capture)
 567 {
 568         struct snd_dma_device pdev;
 569         struct snd_dma_buffer dmbuf;
 570
 571         memset(&pdev, 0, sizeof(pdev));
 572         pdev.type = SNDRV_DMA_TYPE_DEV;
 573         pdev.dev = snd_dma_pci_data(pci);
 574         pdev.id = capture;
 575         dmbuf.bytes = 0;
 576         if (! snd_dma_get_reserved(&pdev, &dmbuf)) {
 577                 if (snd_dma_alloc_pages(&pdev, size, &dmbuf) < 0)
 578                         return NULL;
 579                 snd_dma_set_reserved(&pdev, &dmbuf);
 580         }
 581         *addrp = dmbuf.addr;
 582         return dmbuf.area;
 583 }
 584
 585 static void snd_hammerfall_free_buffer(struct pci_dev *pci, size_t size, void *ptr, dma_addr_t addr, int capture)
 586 {
 587         struct snd_dma_device pdev;
 588
 589         memset(&pdev, 0, sizeof(pdev));
 590         pdev.type = SNDRV_DMA_TYPE_DEV;
 591         pdev.dev = snd_dma_pci_data(pci);
 592         pdev.id = capture;
 593         snd_dma_free_reserved(&pdev);
 594 }
 595
 596 #else
 597 static void *snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size, dma_addr_t *addrp, int capture)
 598 {
 599         return snd_malloc_pci_pages(pci, size, addrp);
 600 }
 601
 602 static void snd_hammerfall_free_buffer(struct pci_dev *pci, size_t size, void *ptr, dma_addr_t addr, int capture)
 603 {
 604         snd_free_pci_pages(pci, size, ptr, addr);
 605 }
 606 #endif
 607
 608 static struct pci_device_id snd_hdsp_ids[] = {
 609         {
 610                 .vendor = PCI_VENDOR_ID_XILINX,
 611                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 612                 .subvendor = PCI_ANY_ID,
 613                 .subdevice = PCI_ANY_ID,
 614         }, /* RME Hammerfall-DSP */
 615         { 0, },
 616 };
 617
 618 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 619
 620 /* prototypes */
 621 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
 622 static int __devinit snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
 623 static inline int snd_hdsp_enable_io (hdsp_t *hdsp);
 624 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
 625 static inline void snd_hdsp_initialize_channels (hdsp_t *hdsp);
 626 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
 627 static int hdsp_autosync_ref(hdsp_t *hdsp);
 628 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
 629 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
 630
 631 static inline int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
 632 {
 633         switch (hdsp->firmware_rev) {
 634         case 0xa:
 635                 return (64 * out) + (32 + (in));
 636         case 0x96:
 637                 return (32 * out) + (16 + (in));
 638         default:
 639                 return (52 * out) + (26 + (in));
 640         }
 641 }
 642
 643 static inline int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
 644 {
 645         switch (hdsp->firmware_rev) {
 646         case 0xa:
 647                 return (64 * out) + in;
 648         case 0x96:
 649                 return (32 * out) + in;
 650         default:
 651                 return (52 * out) + in;
 652         }
 653 }
 654
 655 static inline void hdsp_write(hdsp_t *hdsp, int reg, int val)
 656 {
 657         writel(val, hdsp->iobase + reg);
 658 }
 659
 660 static inline unsigned int hdsp_read(hdsp_t *hdsp, int reg)
 661 {
 662         return readl (hdsp->iobase + reg);
 663 }
 664
 665 static inline int hdsp_check_for_iobox (hdsp_t *hdsp)
 666 {
 667
 668         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 669         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
 670                 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
 671                 hdsp->state &= ~HDSP_FirmwareLoaded;
 672                 return -EIO;
 673         }
 674         return 0;
 675
 676 }
 677
 678 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
 679
 680         int i;
 681         unsigned long flags;
 682
 683         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 684
 685                 snd_printk ("loading firmware\n");
 686
 687                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 688                 hdsp_write (hdsp, HDSP_fifoData, 0);
 689
 690                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 691                         snd_printk ("timeout waiting for download preparation\n");
 692                         return -EIO;
 693                 }
 694
 695                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 696
 697                 for (i = 0; i < 24413; ++i) {
 698                         hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
 699                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 700                                 snd_printk ("timeout during firmware loading\n");
 701                                 return -EIO;
 702                         }
 703                 }
 704
 705                 if ((1000 / HZ) < 3000) {
 706                         set_current_state(TASK_UNINTERRUPTIBLE);
 707                         schedule_timeout((3000 * HZ + 999) / 1000);
 708                 } else {
 709                         mdelay(3000);
 710                 }
 711
 712                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 713                         snd_printk ("timeout at end of firmware loading\n");
 714                         return -EIO;
 715                 }
 716
 717 #ifdef SNDRV_BIG_ENDIAN
 718                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 719 #else
 720                 hdsp->control2_register = 0;
 721 #endif
 722                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 723                 snd_printk ("finished firmware loading\n");
 724
 725         }
 726         if (hdsp->state & HDSP_InitializationComplete) {
 727                 snd_printk("firmware loaded from cache, restoring defaults\n");
 728                 spin_lock_irqsave(&hdsp->lock, flags);
 729                 snd_hdsp_set_defaults(hdsp);
 730                 spin_unlock_irqrestore(&hdsp->lock, flags);
 731         }
 732
 733         hdsp->state |= HDSP_FirmwareLoaded;
 734
 735         return 0;
 736 }
 737
 738 static inline int hdsp_get_iobox_version (hdsp_t *hdsp)
 739 {
 740         int err;
 741
 742         if (hdsp_check_for_iobox (hdsp)) {
 743                 return -EIO;
 744         }
 745
 746         if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
 747                 return err;
 748         }
 749
 750         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 751
 752                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
 753                 hdsp_write (hdsp, HDSP_fifoData, 0);
 754                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 755                         return -EIO;
 756                 }
 757
 758                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 759                 hdsp_write (hdsp, HDSP_fifoData, 0);
 760
 761                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
 762                         hdsp->io_type = Multiface;
 763                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
 764                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 765                         hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
 766                 } else {
 767                         hdsp->io_type = Digiface;
 768                 }
 769         } else {
 770                 /* firmware was already loaded, get iobox type */
 771                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
 772                         hdsp->io_type = Multiface;
 773                 } else {
 774                         hdsp->io_type = Digiface;
 775                 }
 776         }
 777         return 0;
 778 }
 779
 780
 781 static inline int hdsp_check_for_firmware (hdsp_t *hdsp)
 782 {
 783         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 784         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 785                 snd_printk("firmware not present.\n");
 786                 hdsp->state &= ~HDSP_FirmwareLoaded;
 787                 return -EIO;
 788         }
 789         return 0;
 790 }
 791
 792
 793 static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
 794 {
 795         int i;
 796
 797         /* the fifoStatus registers reports on how many words
 798            are available in the command FIFO.
 799         */
 800
 801         for (i = 0; i < timeout; i++) {
 802
 803                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 804                         return 0;
 805
 806                 /* not very friendly, but we only do this during a firmware
 807                    load and changing the mixer, so we just put up with it.
 808                 */
 809
 810                 udelay (100);
 811         }
 812
 813         snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
 814                     count, timeout);
 815         return -1;
 816 }
 817
 818 static inline int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
 819 {
 820         if (addr >= HDSP_MATRIX_MIXER_SIZE) {
 821                 return 0;
 822         }
 823         return hdsp->mixer_matrix[addr];
 824 }
 825
 826 static inline int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
 827 {
 828         unsigned int ad;
 829
 830         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 831                 return -1;
 832
 833         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 834
 835                 /* from martin björnsen:
 836
 837                    "You can only write dwords to the
 838                    mixer memory which contain two
 839                    mixer values in the low and high
 840                    word. So if you want to change
 841                    value 0 you have to read value 1
 842                    from the cache and write both to
 843                    the first dword in the mixer
 844                    memory."
 845                 */
 846
 847                 if (hdsp->io_type == H9632 && addr >= 512) {
 848                         return 0;
 849                 }
 850
 851                 if (hdsp->io_type == H9652 && addr >= 1352) {
 852                         return 0;
 853                 }
 854
 855                 hdsp->mixer_matrix[addr] = data;
 856
 857
 858                 /* `addr' addresses a 16-bit wide address, but
 859                    the address space accessed via hdsp_write
 860                    uses byte offsets. put another way, addr
 861                    varies from 0 to 1351, but to access the
 862                    corresponding memory location, we need
 863                    to access 0 to 2703 ...
 864                 */
 865                 ad = addr/2;
 866
 867                 hdsp_write (hdsp, 4096 + (ad*4),
 868                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 869                             hdsp->mixer_matrix[addr&0x7fe]);
 870
 871                 return 0;
 872
 873         } else {
 874
 875                 ad = (addr << 16) + data;
 876
 877                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
 878                         return -1;
 879                 }
 880
 881                 hdsp_write (hdsp, HDSP_fifoData, ad);
 882                 hdsp->mixer_matrix[addr] = data;
 883
 884         }
 885
 886         return 0;
 887 }
 888
 889 static inline int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
 890 {
 891         unsigned long flags;
 892         int ret = 1;
 893
 894         spin_lock_irqsave(&hdsp->lock, flags);
 895         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 896             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
 897                 ret = 0;
 898         }
 899         spin_unlock_irqrestore(&hdsp->lock, flags);
 900         return ret;
 901 }
 902
 903 static inline int hdsp_external_sample_rate (hdsp_t *hdsp)
 904 {
 905         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 906         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 907
 908         switch (rate_bits) {
 909         case HDSP_systemFrequency32:   return 32000;
 910         case HDSP_systemFrequency44_1: return 44100;
 911         case HDSP_systemFrequency48:   return 48000;
 912         case HDSP_systemFrequency64:   return 64000;
 913         case HDSP_systemFrequency88_2: return 88200;
 914         case HDSP_systemFrequency96:   return 96000;
 915         default:
 916                 return 0;
 917         }
 918 }
 919
 920 static inline int hdsp_spdif_sample_rate(hdsp_t *hdsp)
 921 {
 922         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 923         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 924
 925         if (status & HDSP_SPDIFErrorFlag) {
 926                 return 0;
 927         }
 928
 929         switch (rate_bits) {
 930         case HDSP_spdifFrequency32KHz: return 32000;
 931         case HDSP_spdifFrequency44_1KHz: return 44100;
 932         case HDSP_spdifFrequency48KHz: return 48000;
 933         case HDSP_spdifFrequency64KHz: return 64000;
 934         case HDSP_spdifFrequency88_2KHz: return 88200;
 935         case HDSP_spdifFrequency96KHz: return 96000;
 936         case HDSP_spdifFrequency128KHz:
 937                 if (hdsp->io_type == H9632) return 128000;
 938                 break;
 939         case HDSP_spdifFrequency176_4KHz:
 940                 if (hdsp->io_type == H9632) return 176400;
 941                 break;
 942         case HDSP_spdifFrequency192KHz:
 943                 if (hdsp->io_type == H9632) return 192000;
 944                 break;
 945         default:
 946                 break;
 947         }
 948         snd_printk ("unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
 949         return 0;
 950 }
 951
 952 static inline void hdsp_compute_period_size(hdsp_t *hdsp)
 953 {
 954         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
 955 }
 956
 957 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
 958 {
 959         int position;
 960
 961         position = hdsp_read(hdsp, HDSP_statusRegister);
 962
 963         if (!hdsp->precise_ptr) {
 964                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
 965         }
 966
 967         position &= HDSP_BufferPositionMask;
 968         position /= 4;
 969         position -= 32;
 970         position &= (HDSP_CHANNEL_BUFFER_SAMPLES-1);
 971         return position;
 972 }
 973
 974 static inline void hdsp_reset_hw_pointer(hdsp_t *hdsp)
 975 {
 976         hdsp_write (hdsp, HDSP_resetPointer, 0);
 977 }
 978
 979 static inline void hdsp_start_audio(hdsp_t *s)
 980 {
 981         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
 982         hdsp_write(s, HDSP_controlRegister, s->control_register);
 983 }
 984
 985 static inline void hdsp_stop_audio(hdsp_t *s)
 986 {
 987         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
 988         hdsp_write(s, HDSP_controlRegister, s->control_register);
 989 }
 990
 991 static inline void hdsp_silence_playback(hdsp_t *hdsp)
 992 {
 993         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
 994 }
 995
 996 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
 997 {
 998         int n;
 999
1000         spin_lock_irq(&s->lock);
1001
1002         frames >>= 7;
1003         n = 0;
1004         while (frames) {
1005                 n++;
1006                 frames >>= 1;
1007         }
1008
1009         s->control_register &= ~HDSP_LatencyMask;
1010         s->control_register |= hdsp_encode_latency(n);
1011
1012         hdsp_write(s, HDSP_controlRegister, s->control_register);
1013
1014         hdsp_compute_period_size(s);
1015
1016         spin_unlock_irq(&s->lock);
1017
1018         return 0;
1019 }
1020
1021 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
1022 {
1023         int reject_if_open = 0;
1024         int current_rate;
1025         int rate_bits;
1026
1027         /* ASSUMPTION: hdsp->lock is either held, or
1028            there is no need for it (e.g. during module
1029            initialization).
1030         */
1031
1032         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1033                 if (called_internally) {
1034                         /* request from ctl or card initialization */
1035                         snd_printk("device is not running as a clock master: cannot set sample rate.\n");
1036                         return -1;
1037                 } else {
1038                         /* hw_param request while in AutoSync mode */
1039                         int external_freq = hdsp_external_sample_rate(hdsp);
1040                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1041
1042                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1043                                 snd_printk("Detected ADAT in double speed mode\n");
1044                         } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1045                                 snd_printk("Detected ADAT in quad speed mode\n");
1046                         } else if (rate != external_freq) {
1047                                 snd_printk("No AutoSync source for requested rate\n");
1048                                 return -1;
1049                         }
1050                 }
1051         }
1052
1053         current_rate = hdsp->system_sample_rate;
1054
1055         /* Changing from a "single speed" to a "double speed" rate is
1056            not allowed if any substreams are open. This is because
1057            such a change causes a shift in the location of
1058            the DMA buffers and a reduction in the number of available
1059            buffers.
1060
1061            Note that a similar but essentially insoluble problem
1062            exists for externally-driven rate changes. All we can do
1063            is to flag rate changes in the read/write routines.  */
1064
1065         if (rate > 96000 && hdsp->io_type != H9632) {
1066                 return -EINVAL;
1067         }
1068
1069         switch (rate) {
1070         case 32000:
1071                 if (current_rate > 48000) {
1072                         reject_if_open = 1;
1073                 }
1074                 rate_bits = HDSP_Frequency32KHz;
1075                 break;
1076         case 44100:
1077                 if (current_rate > 48000) {
1078                         reject_if_open = 1;
1079                 }
1080                 rate_bits = HDSP_Frequency44_1KHz;
1081                 break;
1082         case 48000:
1083                 if (current_rate > 48000) {
1084                         reject_if_open = 1;
1085                 }
1086                 rate_bits = HDSP_Frequency48KHz;
1087                 break;
1088         case 64000:
1089                 if (current_rate <= 48000 || current_rate > 96000) {
1090                         reject_if_open = 1;
1091                 }
1092                 rate_bits = HDSP_Frequency64KHz;
1093                 break;
1094         case 88200:
1095                 if (current_rate <= 48000 || current_rate > 96000) {
1096                         reject_if_open = 1;
1097                 }
1098                 rate_bits = HDSP_Frequency88_2KHz;
1099                 break;
1100         case 96000:
1101                 if (current_rate <= 48000 || current_rate > 96000) {
1102                         reject_if_open = 1;
1103                 }
1104                 rate_bits = HDSP_Frequency96KHz;
1105                 break;
1106         case 128000:
1107                 if (current_rate < 128000) {
1108                         reject_if_open = 1;
1109                 }
1110                 rate_bits = HDSP_Frequency128KHz;
1111                 break;
1112         case 176400:
1113                 if (current_rate < 128000) {
1114                         reject_if_open = 1;
1115                 }
1116                 rate_bits = HDSP_Frequency176_4KHz;
1117                 break;
1118         case 192000:
1119                 if (current_rate < 128000) {
1120                         reject_if_open = 1;
1121                 }
1122                 rate_bits = HDSP_Frequency192KHz;
1123                 break;
1124         default:
1125                 return -EINVAL;
1126         }
1127
1128         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1129                 snd_printk ("cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1130                             hdsp->capture_pid,
1131                             hdsp->playback_pid);
1132                 return -EBUSY;
1133         }
1134
1135         hdsp->control_register &= ~HDSP_FrequencyMask;
1136         hdsp->control_register |= rate_bits;
1137         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1138
1139         if (rate >= 128000) {
1140                 hdsp->channel_map = channel_map_H9632_qs;
1141         } else if (rate > 48000) {
1142                 if (hdsp->io_type == H9632) {
1143                         hdsp->channel_map = channel_map_H9632_ds;
1144                 } else {
1145                         hdsp->channel_map = channel_map_ds;
1146                 }
1147         } else {
1148                 switch (hdsp->io_type) {
1149                 case Multiface:
1150                         hdsp->channel_map = channel_map_mf_ss;
1151                         break;
1152                 case Digiface:
1153                 case H9652:
1154                         hdsp->channel_map = channel_map_df_ss;
1155                         break;
1156                 case H9632:
1157                         hdsp->channel_map = channel_map_H9632_ss;
1158                         break;
1159                 default:
1160                         /* should never happen */
1161                         break;
1162                 }
1163         }
1164
1165         hdsp->system_sample_rate = rate;
1166
1167         return 0;
1168 }
1169
1170 static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
1171 {
1172
1173         hdsp->passthru = 0;
1174
1175         if (channel < 0) {
1176
1177                 int i;
1178
1179                 /* set thru for all channels */
1180
1181                 if (enable) {
1182                         for (i = 0; i < hdsp->max_channels; i++) {
1183                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), UNITY_GAIN);
1184                         }
1185                 } else {
1186                         for (i = 0; i < hdsp->max_channels; i++) {
1187                                 hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,i,i), MINUS_INFINITY_GAIN);
1188                         }
1189                 }
1190
1191         } else {
1192                 int mapped_channel;
1193
1194                 snd_assert(channel < hdsp->max_channels, return);
1195
1196                 mapped_channel = hdsp->channel_map[channel];
1197
1198                 snd_assert(mapped_channel > -1, return);
1199
1200                 if (enable) {
1201                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), UNITY_GAIN);
1202                 } else {
1203                         hdsp_write_gain (hdsp, hdsp_input_to_output_key(hdsp,mapped_channel,mapped_channel), MINUS_INFINITY_GAIN);
1204                 }
1205         }
1206 }
1207
1208 static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
1209 {
1210         if (onoff) {
1211                 hdsp_set_thru(hdsp, -1, 1);
1212                 hdsp_reset_hw_pointer(hdsp);
1213                 hdsp_silence_playback(hdsp);
1214
1215                 /* we don't want interrupts, so do a
1216                    custom version of hdsp_start_audio().
1217                 */
1218
1219                 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
1220
1221                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1222                 hdsp->passthru = 1;
1223         } else {
1224                 hdsp_set_thru(hdsp, -1, 0);
1225                 hdsp_stop_audio(hdsp);
1226                 hdsp->passthru = 0;
1227         }
1228
1229         return 0;
1230 }
1231
1232 /*----------------------------------------------------------------------------
1233    MIDI
1234   ----------------------------------------------------------------------------*/
1235
1236 static inline unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1237 {
1238         /* the hardware already does the relevant bit-mask with 0xff */
1239         if (id) {
1240                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1241         } else {
1242                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1243         }
1244 }
1245
1246 static inline void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1247 {
1248         /* the hardware already does the relevant bit-mask with 0xff */
1249         if (id) {
1250                 return hdsp_write(hdsp, HDSP_midiDataOut1, val);
1251         } else {
1252                 return hdsp_write(hdsp, HDSP_midiDataOut0, val);
1253         }
1254 }
1255
1256 static inline int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1257 {
1258         if (id) {
1259                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1260         } else {
1261                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1262         }
1263 }
1264
1265 static inline int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1266 {
1267         int fifo_bytes_used;
1268
1269         if (id) {
1270                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1271         } else {
1272                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1273         }
1274
1275         if (fifo_bytes_used < 128) {
1276                 return  128 - fifo_bytes_used;
1277         } else {
1278                 return 0;
1279         }
1280 }
1281
1282 static inline void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1283 {
1284         while (snd_hdsp_midi_input_available (hdsp, id)) {
1285                 snd_hdsp_midi_read_byte (hdsp, id);
1286         }
1287 }
1288
1289 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1290 {
1291         unsigned long flags;
1292         int n_pending;
1293         int to_write;
1294         int i;
1295         unsigned char buf[128];
1296
1297         /* Output is not interrupt driven */
1298
1299         spin_lock_irqsave (&hmidi->lock, flags);
1300         if (hmidi->output) {
1301                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1302                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1303                                 if (n_pending > (int)sizeof (buf))
1304                                         n_pending = sizeof (buf);
1305
1306                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1307                                         for (i = 0; i < to_write; ++i)
1308                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1309                                 }
1310                         }
1311                 }
1312         }
1313         spin_unlock_irqrestore (&hmidi->lock, flags);
1314         return 0;
1315 }
1316
1317 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1318 {
1319         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1320         unsigned long flags;
1321         int n_pending;
1322         int i;
1323
1324         spin_lock_irqsave (&hmidi->lock, flags);
1325         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1326                 if (hmidi->input) {
1327                         if (n_pending > (int)sizeof (buf)) {
1328                                 n_pending = sizeof (buf);
1329                         }
1330                         for (i = 0; i < n_pending; ++i) {
1331                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1332                         }
1333                         if (n_pending) {
1334                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1335                         }
1336                 } else {
1337                         /* flush the MIDI input FIFO */
1338                         while (--n_pending) {
1339                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1340                         }
1341                 }
1342         }
1343         hmidi->pending = 0;
1344         if (hmidi->id) {
1345                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1346         } else {
1347                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1348         }
1349         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1350         spin_unlock_irqrestore (&hmidi->lock, flags);
1351         return snd_hdsp_midi_output_write (hmidi);
1352 }
1353
1354 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1355 {
1356         hdsp_t *hdsp;
1357         hdsp_midi_t *hmidi;
1358         unsigned long flags;
1359         u32 ie;
1360
1361         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1362         hdsp = hmidi->hdsp;
1363         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1364         spin_lock_irqsave (&hdsp->lock, flags);
1365         if (up) {
1366                 if (!(hdsp->control_register & ie)) {
1367                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1368                         hdsp->control_register |= ie;
1369                 }
1370         } else {
1371                 hdsp->control_register &= ~ie;
1372         }
1373
1374         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1375         spin_unlock_irqrestore (&hdsp->lock, flags);
1376 }
1377
1378 static void snd_hdsp_midi_output_timer(unsigned long data)
1379 {
1380         hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1381         unsigned long flags;
1382
1383         snd_hdsp_midi_output_write(hmidi);
1384         spin_lock_irqsave (&hmidi->lock, flags);
1385
1386         /* this does not bump hmidi->istimer, because the
1387            kernel automatically removed the timer when it
1388            expired, and we are now adding it back, thus
1389            leaving istimer wherever it was set before.
1390         */
1391
1392         if (hmidi->istimer) {
1393                 hmidi->timer.expires = 1 + jiffies;
1394                 add_timer(&hmidi->timer);
1395         }
1396
1397         spin_unlock_irqrestore (&hmidi->lock, flags);
1398 }
1399
1400 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1401 {
1402         hdsp_midi_t *hmidi;
1403         unsigned long flags;
1404
1405         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1406         spin_lock_irqsave (&hmidi->lock, flags);
1407         if (up) {
1408                 if (!hmidi->istimer) {
1409                         init_timer(&hmidi->timer);
1410                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1411                         hmidi->timer.data = (unsigned long) hmidi;
1412                         hmidi->timer.expires = 1 + jiffies;
1413                         add_timer(&hmidi->timer);
1414                         hmidi->istimer++;
1415                 }
1416         } else {
1417                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1418                         del_timer (&hmidi->timer);
1419                 }
1420         }
1421         spin_unlock_irqrestore (&hmidi->lock, flags);
1422         if (up)
1423                 snd_hdsp_midi_output_write(hmidi);
1424 }
1425
1426 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1427 {
1428         hdsp_midi_t *hmidi;
1429         unsigned long flags;
1430
1431         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1432         spin_lock_irqsave (&hmidi->lock, flags);
1433         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1434         hmidi->input = substream;
1435         spin_unlock_irqrestore (&hmidi->lock, flags);
1436
1437         return 0;
1438 }
1439
1440 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1441 {
1442         hdsp_midi_t *hmidi;
1443         unsigned long flags;
1444
1445         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1446         spin_lock_irqsave (&hmidi->lock, flags);
1447         hmidi->output = substream;
1448         spin_unlock_irqrestore (&hmidi->lock, flags);
1449
1450         return 0;
1451 }
1452
1453 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1454 {
1455         hdsp_midi_t *hmidi;
1456         unsigned long flags;
1457
1458         snd_hdsp_midi_input_trigger (substream, 0);
1459
1460         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1461         spin_lock_irqsave (&hmidi->lock, flags);
1462         hmidi->input = NULL;
1463         spin_unlock_irqrestore (&hmidi->lock, flags);
1464
1465         return 0;
1466 }
1467
1468 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1469 {
1470         hdsp_midi_t *hmidi;
1471         unsigned long flags;
1472
1473         snd_hdsp_midi_output_trigger (substream, 0);
1474
1475         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1476         spin_lock_irqsave (&hmidi->lock, flags);
1477         hmidi->output = NULL;
1478         spin_unlock_irqrestore (&hmidi->lock, flags);
1479
1480         return 0;
1481 }
1482
1483 snd_rawmidi_ops_t snd_hdsp_midi_output =
1484 {
1485         .open =         snd_hdsp_midi_output_open,
1486         .close =        snd_hdsp_midi_output_close,
1487         .trigger =      snd_hdsp_midi_output_trigger,
1488 };
1489
1490 snd_rawmidi_ops_t snd_hdsp_midi_input =
1491 {
1492         .open =         snd_hdsp_midi_input_open,
1493         .close =        snd_hdsp_midi_input_close,
1494         .trigger =      snd_hdsp_midi_input_trigger,
1495 };
1496
1497 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1498 {
1499         char buf[32];
1500
1501         hdsp->midi[id].id = id;
1502         hdsp->midi[id].rmidi = NULL;
1503         hdsp->midi[id].input = NULL;
1504         hdsp->midi[id].output = NULL;
1505         hdsp->midi[id].hdsp = hdsp;
1506         hdsp->midi[id].istimer = 0;
1507         hdsp->midi[id].pending = 0;
1508         spin_lock_init (&hdsp->midi[id].lock);
1509
1510         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1511         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1512                 return -1;
1513         }
1514
1515         sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1516         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1517
1518         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1519         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1520
1521         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1522                 SNDRV_RAWMIDI_INFO_INPUT |
1523                 SNDRV_RAWMIDI_INFO_DUPLEX;
1524
1525         return 0;
1526 }
1527
1528 /*-----------------------------------------------------------------------------
1529   Control Interface
1530   ----------------------------------------------------------------------------*/
1531
1532 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1533 {
1534         u32 val = 0;
1535         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1536         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1537         if (val & HDSP_SPDIFProfessional)
1538                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1539         else
1540                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1541         return val;
1542 }
1543
1544 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1545 {
1546         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1547                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1548         if (val & HDSP_SPDIFProfessional)
1549                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1550         else
1551                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1552 }
1553
1554 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1555 {
1556         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1557         uinfo->count = 1;
1558         return 0;
1559 }
1560
1561 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1562 {
1563         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1564
1565         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1566         return 0;
1567 }
1568
1569 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1570 {
1571         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1572         unsigned long flags;
1573         int change;
1574         u32 val;
1575
1576         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1577         spin_lock_irqsave(&hdsp->lock, flags);
1578         change = val != hdsp->creg_spdif;
1579         hdsp->creg_spdif = val;
1580         spin_unlock_irqrestore(&hdsp->lock, flags);
1581         return change;
1582 }
1583
1584 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1585 {
1586         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1587         uinfo->count = 1;
1588         return 0;
1589 }
1590
1591 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1592 {
1593         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1594
1595         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1596         return 0;
1597 }
1598
1599 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1600 {
1601         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1602         unsigned long flags;
1603         int change;
1604         u32 val;
1605
1606         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1607         spin_lock_irqsave(&hdsp->lock, flags);
1608         change = val != hdsp->creg_spdif_stream;
1609         hdsp->creg_spdif_stream = val;
1610         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1611         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1612         spin_unlock_irqrestore(&hdsp->lock, flags);
1613         return change;
1614 }
1615
1616 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1617 {
1618         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1619         uinfo->count = 1;
1620         return 0;
1621 }
1622
1623 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1624 {
1625         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1626         return 0;
1627 }
1628
1629 #define HDSP_SPDIF_IN(xname, xindex) \
1630 { .iface = SNDRV_CTL_ELEM_IFACE_PCM,  \
1631   .name = xname, \
1632   .index = xindex, \
1633   .info = snd_hdsp_info_spdif_in, \
1634   .get = snd_hdsp_get_spdif_in, \
1635   .put = snd_hdsp_put_spdif_in }
1636
1637 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1638 {
1639         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1640 }
1641
1642 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1643 {
1644         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1645         hdsp->control_register |= hdsp_encode_spdif_in(in);
1646         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1647         return 0;
1648 }
1649
1650 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1651 {
1652         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1653         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1654
1655         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1656         uinfo->count = 1;
1657         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1658         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1659                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1660         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1661         return 0;
1662 }
1663
1664 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1665 {
1666         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1667
1668         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1669         return 0;
1670 }
1671
1672 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1673 {
1674         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1675         unsigned long flags;
1676         int change;
1677         unsigned int val;
1678
1679         if (!snd_hdsp_use_is_exclusive(hdsp))
1680                 return -EBUSY;
1681         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1682         spin_lock_irqsave(&hdsp->lock, flags);
1683         change = val != hdsp_spdif_in(hdsp);
1684         if (change)
1685                 hdsp_set_spdif_input(hdsp, val);
1686         spin_unlock_irqrestore(&hdsp->lock, flags);
1687         return change;
1688 }
1689
1690 #define HDSP_SPDIF_OUT(xname, xindex) \
1691 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1692   .info = snd_hdsp_info_spdif_bits, \
1693   .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1694
1695 static int hdsp_spdif_out(hdsp_t *hdsp)
1696 {
1697         return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1698 }
1699
1700 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1701 {
1702         if (out) {
1703                 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1704         } else {
1705                 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1706         }
1707         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1708         return 0;
1709 }
1710
1711 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1712 {
1713         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1714         uinfo->count = 1;
1715         uinfo->value.integer.min = 0;
1716         uinfo->value.integer.max = 1;
1717         return 0;
1718 }
1719
1720 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1721 {
1722         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1723
1724         ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1725         return 0;
1726 }
1727
1728 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1729 {
1730         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1731         unsigned long flags;
1732         int change;
1733         unsigned int val;
1734
1735         if (!snd_hdsp_use_is_exclusive(hdsp))
1736                 return -EBUSY;
1737         val = ucontrol->value.integer.value[0] & 1;
1738         spin_lock_irqsave(&hdsp->lock, flags);
1739         change = (int)val != hdsp_spdif_out(hdsp);
1740         hdsp_set_spdif_output(hdsp, val);
1741         spin_unlock_irqrestore(&hdsp->lock, flags);
1742         return change;
1743 }
1744
1745 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1746 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1747   .info = snd_hdsp_info_spdif_bits, \
1748   .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1749
1750 static int hdsp_spdif_professional(hdsp_t *hdsp)
1751 {
1752         return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1753 }
1754
1755 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1756 {
1757         if (val) {
1758                 hdsp->control_register |= HDSP_SPDIFProfessional;
1759         } else {
1760                 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1761         }
1762         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1763         return 0;
1764 }
1765
1766 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1767 {
1768         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1769
1770         ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1771         return 0;
1772 }
1773
1774 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1775 {
1776         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1777         unsigned long flags;
1778         int change;
1779         unsigned int val;
1780
1781         if (!snd_hdsp_use_is_exclusive(hdsp))
1782                 return -EBUSY;
1783         val = ucontrol->value.integer.value[0] & 1;
1784         spin_lock_irqsave(&hdsp->lock, flags);
1785         change = (int)val != hdsp_spdif_professional(hdsp);
1786         hdsp_set_spdif_professional(hdsp, val);
1787         spin_unlock_irqrestore(&hdsp->lock, flags);
1788         return change;
1789 }
1790
1791 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1792 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1793   .info = snd_hdsp_info_spdif_bits, \
1794   .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1795
1796 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1797 {
1798         return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1799 }
1800
1801 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1802 {
1803         if (val) {
1804                 hdsp->control_register |= HDSP_SPDIFEmphasis;
1805         } else {
1806                 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1807         }
1808         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1809         return 0;
1810 }
1811
1812 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1813 {
1814         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1815
1816         ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1817         return 0;
1818 }
1819
1820 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1821 {
1822         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1823         unsigned long flags;
1824         int change;
1825         unsigned int val;
1826
1827         if (!snd_hdsp_use_is_exclusive(hdsp))
1828                 return -EBUSY;
1829         val = ucontrol->value.integer.value[0] & 1;
1830         spin_lock_irqsave(&hdsp->lock, flags);
1831         change = (int)val != hdsp_spdif_emphasis(hdsp);
1832         hdsp_set_spdif_emphasis(hdsp, val);
1833         spin_unlock_irqrestore(&hdsp->lock, flags);
1834         return change;
1835 }
1836
1837 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1838 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1839   .info = snd_hdsp_info_spdif_bits, \
1840   .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1841
1842 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1843 {
1844         return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1845 }
1846
1847 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1848 {
1849         if (val) {
1850                 hdsp->control_register |= HDSP_SPDIFNonAudio;
1851         } else {
1852                 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1853         }
1854         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1855         return 0;
1856 }
1857
1858 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1859 {
1860         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1861
1862         ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1863         return 0;
1864 }
1865
1866 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1867 {
1868         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1869         unsigned long flags;
1870         int change;
1871         unsigned int val;
1872
1873         if (!snd_hdsp_use_is_exclusive(hdsp))
1874                 return -EBUSY;
1875         val = ucontrol->value.integer.value[0] & 1;
1876         spin_lock_irqsave(&hdsp->lock, flags);
1877         change = (int)val != hdsp_spdif_nonaudio(hdsp);
1878         hdsp_set_spdif_nonaudio(hdsp, val);
1879         spin_unlock_irqrestore(&hdsp->lock, flags);
1880         return change;
1881 }
1882
1883 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1884 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1885   .name = xname, \
1886   .index = xindex, \
1887   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1888   .info = snd_hdsp_info_spdif_sample_rate, \
1889   .get = snd_hdsp_get_spdif_sample_rate \
1890 }
1891
1892 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1893 {
1894         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1895         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1896
1897         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1898         uinfo->count = 1;
1899         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1900         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1901                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1902         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1903         return 0;
1904 }
1905
1906 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1907 {
1908         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1909
1910         switch (hdsp_spdif_sample_rate(hdsp)) {
1911         case 32000:
1912                 ucontrol->value.enumerated.item[0] = 0;
1913                 break;
1914         case 44100:
1915                 ucontrol->value.enumerated.item[0] = 1;
1916                 break;
1917         case 48000:
1918                 ucontrol->value.enumerated.item[0] = 2;
1919                 break;
1920         case 64000:
1921                 ucontrol->value.enumerated.item[0] = 3;
1922                 break;
1923         case 88200:
1924                 ucontrol->value.enumerated.item[0] = 4;
1925                 break;
1926         case 96000:
1927                 ucontrol->value.enumerated.item[0] = 5;
1928                 break;
1929         case 128000:
1930                 ucontrol->value.enumerated.item[0] = 7;
1931                 break;
1932         case 176400:
1933                 ucontrol->value.enumerated.item[0] = 8;
1934                 break;
1935         case 192000:
1936                 ucontrol->value.enumerated.item[0] = 9;
1937                 break;
1938         default:
1939                 ucontrol->value.enumerated.item[0] = 6;
1940         }
1941         return 0;
1942 }
1943
1944 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1945 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1946   .name = xname, \
1947   .index = xindex, \
1948   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1949   .info = snd_hdsp_info_system_sample_rate, \
1950   .get = snd_hdsp_get_system_sample_rate \
1951 }
1952
1953 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1954 {
1955         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1956         uinfo->count = 1;
1957         return 0;
1958 }
1959
1960 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1961 {
1962         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1963
1964         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1965         return 0;
1966 }
1967
1968 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1969 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1970   .name = xname, \
1971   .index = xindex, \
1972   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1973   .info = snd_hdsp_info_autosync_sample_rate, \
1974   .get = snd_hdsp_get_autosync_sample_rate \
1975 }
1976
1977 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1978 {
1979         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1980         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1981         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1982         uinfo->count = 1;
1983         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1984         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1985                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1986         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1987         return 0;
1988 }
1989
1990 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1991 {
1992         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1993
1994         switch (hdsp_external_sample_rate(hdsp)) {
1995         case 32000:
1996                 ucontrol->value.enumerated.item[0] = 0;
1997                 break;
1998         case 44100:
1999                 ucontrol->value.enumerated.item[0] = 1;
2000                 break;
2001         case 48000:
2002                 ucontrol->value.enumerated.item[0] = 2;
2003                 break;
2004         case 64000:
2005                 ucontrol->value.enumerated.item[0] = 3;
2006                 break;
2007         case 88200:
2008                 ucontrol->value.enumerated.item[0] = 4;
2009                 break;
2010         case 96000:
2011                 ucontrol->value.enumerated.item[0] = 5;
2012                 break;
2013         case 128000:
2014                 ucontrol->value.enumerated.item[0] = 7;
2015                 break;
2016         case 176400:
2017                 ucontrol->value.enumerated.item[0] = 8;
2018                 break;
2019         case 192000:
2020                 ucontrol->value.enumerated.item[0] = 9;
2021                 break;
2022         default:
2023                 ucontrol->value.enumerated.item[0] = 6;
2024         }
2025         return 0;
2026 }
2027
2028 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
2029 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2030   .name = xname, \
2031   .index = xindex, \
2032   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2033   .info = snd_hdsp_info_system_clock_mode, \
2034   .get = snd_hdsp_get_system_clock_mode \
2035 }
2036
2037 static int hdsp_system_clock_mode(hdsp_t *hdsp)
2038 {
2039         if (hdsp->control_register & HDSP_ClockModeMaster) {
2040                 return 0;
2041         } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
2042                         return 0;
2043         }
2044         return 1;
2045 }
2046
2047 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2048 {
2049         static char *texts[] = {"Master", "Slave" };
2050
2051         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2052         uinfo->count = 1;
2053         uinfo->value.enumerated.items = 2;
2054         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2055                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2056         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2057         return 0;
2058 }
2059
2060 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2061 {
2062         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2063
2064         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2065         return 0;
2066 }
2067
2068 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2069 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
2070   .name = xname, \
2071   .index = xindex, \
2072   .info = snd_hdsp_info_clock_source, \
2073   .get = snd_hdsp_get_clock_source, \
2074   .put = snd_hdsp_put_clock_source \
2075 }
2076
2077 static int hdsp_clock_source(hdsp_t *hdsp)
2078 {
2079         if (hdsp->control_register & HDSP_ClockModeMaster) {
2080                 switch (hdsp->system_sample_rate) {
2081                 case 32000:
2082                         return 1;
2083                 case 44100:
2084                         return 2;
2085                 case 48000:
2086                         return 3;
2087                 case 64000:
2088                         return 4;
2089                 case 88200:
2090                         return 5;
2091                 case 96000:
2092                         return 6;
2093                 case 128000:
2094                         return 7;
2095                 case 176400:
2096                         return 8;
2097                 case 192000:
2098                         return 9;
2099                 default:
2100                         return 3;
2101                 }
2102         } else {
2103                 return 0;
2104         }
2105 }
2106
2107 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2108 {
2109         int rate;
2110         switch (mode) {
2111         case HDSP_CLOCK_SOURCE_AUTOSYNC:
2112                 if (hdsp_external_sample_rate(hdsp) != 0) {
2113                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2114                         hdsp->control_register &= ~HDSP_ClockModeMaster;
2115                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2116                         return 0;
2117                     }
2118                 }
2119                 return -1;
2120         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2121                 rate = 32000;
2122                 break;
2123         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2124                 rate = 44100;
2125                 break;
2126         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2127                 rate = 48000;
2128                 break;
2129         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2130                 rate = 64000;
2131                 break;
2132         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2133                 rate = 88200;
2134                 break;
2135         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2136                 rate = 96000;
2137                 break;
2138         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2139                 rate = 128000;
2140                 break;
2141         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2142                 rate = 176400;
2143                 break;
2144         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2145                 rate = 192000;
2146                 break;
2147         default:
2148                 rate = 48000;
2149         }
2150         hdsp->control_register |= HDSP_ClockModeMaster;
2151         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2152         hdsp_set_rate(hdsp, rate, 1);
2153         return 0;
2154 }
2155
2156 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2157 {
2158         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2159         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2160
2161         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2162         uinfo->count = 1;
2163         if (hdsp->io_type == H9632)
2164             uinfo->value.enumerated.items = 10;
2165         else
2166             uinfo->value.enumerated.items = 7;
2167         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2168                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2169         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2170         return 0;
2171 }
2172
2173 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2174 {
2175         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2176
2177         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2178         return 0;
2179 }
2180
2181 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2182 {
2183         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2184         unsigned long flags;
2185         int change;
2186         int val;
2187
2188         if (!snd_hdsp_use_is_exclusive(hdsp))
2189                 return -EBUSY;
2190         val = ucontrol->value.enumerated.item[0];
2191         if (val < 0) val = 0;
2192         if (hdsp->io_type == H9632) {
2193             if (val > 9) val = 9;
2194         } else {
2195             if (val > 6) val = 6;
2196         }
2197         spin_lock_irqsave(&hdsp->lock, flags);
2198         if (val != hdsp_clock_source(hdsp)) {
2199                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2200         } else {
2201                 change = 0;
2202         }
2203         spin_unlock_irqrestore(&hdsp->lock, flags);
2204         return change;
2205 }
2206
2207 #define HDSP_DA_GAIN(xname, xindex) \
2208 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2209   .name = xname, \
2210   .index = xindex, \
2211   .info = snd_hdsp_info_da_gain, \
2212   .get = snd_hdsp_get_da_gain, \
2213   .put = snd_hdsp_put_da_gain \
2214 }
2215
2216 static int hdsp_da_gain(hdsp_t *hdsp)
2217 {
2218         switch (hdsp->control_register & HDSP_DAGainMask) {
2219         case HDSP_DAGainHighGain:
2220                 return 0;
2221         case HDSP_DAGainPlus4dBu:
2222                 return 1;
2223         case HDSP_DAGainMinus10dBV:
2224                 return 2;
2225         default:
2226                 return 1;
2227         }
2228 }
2229
2230 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2231 {
2232         hdsp->control_register &= ~HDSP_DAGainMask;
2233         switch (mode) {
2234         case 0:
2235                 hdsp->control_register |= HDSP_DAGainHighGain;
2236                 break;
2237         case 1:
2238                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2239                 break;
2240         case 2:
2241                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2242                 break;
2243         default:
2244                 return -1;
2245
2246         }
2247         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2248         return 0;
2249 }
2250
2251 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2252 {
2253         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2254
2255         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2256         uinfo->count = 1;
2257         uinfo->value.enumerated.items = 3;
2258         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2259                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2260         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2261         return 0;
2262 }
2263
2264 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2265 {
2266         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2267
2268         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2269         return 0;
2270 }
2271
2272 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2273 {
2274         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2275         unsigned long flags;
2276         int change;
2277         int val;
2278
2279         if (!snd_hdsp_use_is_exclusive(hdsp))
2280                 return -EBUSY;
2281         val = ucontrol->value.enumerated.item[0];
2282         if (val < 0) val = 0;
2283         if (val > 2) val = 2;
2284         spin_lock_irqsave(&hdsp->lock, flags);
2285         if (val != hdsp_da_gain(hdsp)) {
2286                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2287         } else {
2288                 change = 0;
2289         }
2290         spin_unlock_irqrestore(&hdsp->lock, flags);
2291         return change;
2292 }
2293
2294 #define HDSP_AD_GAIN(xname, xindex) \
2295 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2296   .name = xname, \
2297   .index = xindex, \
2298   .info = snd_hdsp_info_ad_gain, \
2299   .get = snd_hdsp_get_ad_gain, \
2300   .put = snd_hdsp_put_ad_gain \
2301 }
2302
2303 static int hdsp_ad_gain(hdsp_t *hdsp)
2304 {
2305         switch (hdsp->control_register & HDSP_ADGainMask) {
2306         case HDSP_ADGainMinus10dBV:
2307                 return 0;
2308         case HDSP_ADGainPlus4dBu:
2309                 return 1;
2310         case HDSP_ADGainLowGain:
2311                 return 2;
2312         default:
2313                 return 1;
2314         }
2315 }
2316
2317 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2318 {
2319         hdsp->control_register &= ~HDSP_ADGainMask;
2320         switch (mode) {
2321         case 0:
2322                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2323                 break;
2324         case 1:
2325                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2326                 break;
2327         case 2:
2328                 hdsp->control_register |= HDSP_ADGainLowGain;
2329                 break;
2330         default:
2331                 return -1;
2332
2333         }
2334         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2335         return 0;
2336 }
2337
2338 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2339 {
2340         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2341
2342         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2343         uinfo->count = 1;
2344         uinfo->value.enumerated.items = 3;
2345         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2346                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2347         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2348         return 0;
2349 }
2350
2351 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2352 {
2353         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2354
2355         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2356         return 0;
2357 }
2358
2359 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2360 {
2361         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2362         unsigned long flags;
2363         int change;
2364         int val;
2365
2366         if (!snd_hdsp_use_is_exclusive(hdsp))
2367                 return -EBUSY;
2368         val = ucontrol->value.enumerated.item[0];
2369         if (val < 0) val = 0;
2370         if (val > 2) val = 2;
2371         spin_lock_irqsave(&hdsp->lock, flags);
2372         if (val != hdsp_ad_gain(hdsp)) {
2373                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2374         } else {
2375                 change = 0;
2376         }
2377         spin_unlock_irqrestore(&hdsp->lock, flags);
2378         return change;
2379 }
2380
2381 #define HDSP_PHONE_GAIN(xname, xindex) \
2382 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2383   .name = xname, \
2384   .index = xindex, \
2385   .info = snd_hdsp_info_phone_gain, \
2386   .get = snd_hdsp_get_phone_gain, \
2387   .put = snd_hdsp_put_phone_gain \
2388 }
2389
2390 static int hdsp_phone_gain(hdsp_t *hdsp)
2391 {
2392         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2393         case HDSP_PhoneGain0dB:
2394                 return 0;
2395         case HDSP_PhoneGainMinus6dB:
2396                 return 1;
2397         case HDSP_PhoneGainMinus12dB:
2398                 return 2;
2399         default:
2400                 return 0;
2401         }
2402 }
2403
2404 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2405 {
2406         hdsp->control_register &= ~HDSP_PhoneGainMask;
2407         switch (mode) {
2408         case 0:
2409                 hdsp->control_register |= HDSP_PhoneGain0dB;
2410                 break;
2411         case 1:
2412                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2413                 break;
2414         case 2:
2415                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2416                 break;
2417         default:
2418                 return -1;
2419
2420         }
2421         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2422         return 0;
2423 }
2424
2425 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2426 {
2427         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2428
2429         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2430         uinfo->count = 1;
2431         uinfo->value.enumerated.items = 3;
2432         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2433                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2434         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2435         return 0;
2436 }
2437
2438 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2439 {
2440         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2441
2442         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2443         return 0;
2444 }
2445
2446 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2447 {
2448         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2449         unsigned long flags;
2450         int change;
2451         int val;
2452
2453         if (!snd_hdsp_use_is_exclusive(hdsp))
2454                 return -EBUSY;
2455         val = ucontrol->value.enumerated.item[0];
2456         if (val < 0) val = 0;
2457         if (val > 2) val = 2;
2458         spin_lock_irqsave(&hdsp->lock, flags);
2459         if (val != hdsp_phone_gain(hdsp)) {
2460                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2461         } else {
2462                 change = 0;
2463         }
2464         spin_unlock_irqrestore(&hdsp->lock, flags);
2465         return change;
2466 }
2467
2468 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2469 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2470   .name = xname, \
2471   .index = xindex, \
2472   .info = snd_hdsp_info_xlr_breakout_cable, \
2473   .get = snd_hdsp_get_xlr_breakout_cable, \
2474   .put = snd_hdsp_put_xlr_breakout_cable \
2475 }
2476
2477 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2478 {
2479         if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2480                 return 1;
2481         }
2482         return 0;
2483 }
2484
2485 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2486 {
2487         if (mode) {
2488                 hdsp->control_register |= HDSP_XLRBreakoutCable;
2489         } else {
2490                 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2491         }
2492         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2493         return 0;
2494 }
2495
2496 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2497 {
2498         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2499         uinfo->count = 1;
2500         uinfo->value.integer.min = 0;
2501         uinfo->value.integer.max = 1;
2502         return 0;
2503 }
2504
2505 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2506 {
2507         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2508
2509         ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2510         return 0;
2511 }
2512
2513 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2514 {
2515         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2516         unsigned long flags;
2517         int change;
2518         int val;
2519
2520         if (!snd_hdsp_use_is_exclusive(hdsp))
2521                 return -EBUSY;
2522         val = ucontrol->value.integer.value[0] & 1;
2523         spin_lock_irqsave(&hdsp->lock, flags);
2524         change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2525         hdsp_set_xlr_breakout_cable(hdsp, val);
2526         spin_unlock_irqrestore(&hdsp->lock, flags);
2527         return change;
2528 }
2529
2530 /* (De)activates old RME Analog Extension Board
2531    These are connected to the internal ADAT connector
2532    Switching this on desactivates external ADAT
2533 */
2534 #define HDSP_AEB(xname, xindex) \
2535 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2536   .name = xname, \
2537   .index = xindex, \
2538   .info = snd_hdsp_info_aeb, \
2539   .get = snd_hdsp_get_aeb, \
2540   .put = snd_hdsp_put_aeb \
2541 }
2542
2543 static int hdsp_aeb(hdsp_t *hdsp)
2544 {
2545         if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2546                 return 1;
2547         }
2548         return 0;
2549 }
2550
2551 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2552 {
2553         if (mode) {
2554                 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2555         } else {
2556                 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2557         }
2558         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2559         return 0;
2560 }
2561
2562 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2563 {
2564         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2565         uinfo->count = 1;
2566         uinfo->value.integer.min = 0;
2567         uinfo->value.integer.max = 1;
2568         return 0;
2569 }
2570
2571 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2572 {
2573         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2574
2575         ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2576         return 0;
2577 }
2578
2579 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2580 {
2581         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2582         unsigned long flags;
2583         int change;
2584         int val;
2585
2586         if (!snd_hdsp_use_is_exclusive(hdsp))
2587                 return -EBUSY;
2588         val = ucontrol->value.integer.value[0] & 1;
2589         spin_lock_irqsave(&hdsp->lock, flags);
2590         change = (int)val != hdsp_aeb(hdsp);
2591         hdsp_set_aeb(hdsp, val);
2592         spin_unlock_irqrestore(&hdsp->lock, flags);
2593         return change;
2594 }
2595
2596 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2597 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2598   .name = xname, \
2599   .index = xindex, \
2600   .info = snd_hdsp_info_pref_sync_ref, \
2601   .get = snd_hdsp_get_pref_sync_ref, \
2602   .put = snd_hdsp_put_pref_sync_ref \
2603 }
2604
2605 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2606 {
2607         /* Notice that this looks at the requested sync source,
2608            not the one actually in use.
2609         */
2610
2611         switch (hdsp->control_register & HDSP_SyncRefMask) {
2612         case HDSP_SyncRef_ADAT1:
2613                 return HDSP_SYNC_FROM_ADAT1;
2614         case HDSP_SyncRef_ADAT2:
2615                 return HDSP_SYNC_FROM_ADAT2;
2616         case HDSP_SyncRef_ADAT3:
2617                 return HDSP_SYNC_FROM_ADAT3;
2618         case HDSP_SyncRef_SPDIF:
2619                 return HDSP_SYNC_FROM_SPDIF;
2620         case HDSP_SyncRef_WORD:
2621                 return HDSP_SYNC_FROM_WORD;
2622         case HDSP_SyncRef_ADAT_SYNC:
2623                 return HDSP_SYNC_FROM_ADAT_SYNC;
2624         default:
2625                 return HDSP_SYNC_FROM_WORD;
2626         }
2627         return 0;
2628 }
2629
2630 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2631 {
2632         hdsp->control_register &= ~HDSP_SyncRefMask;
2633         switch (pref) {
2634         case HDSP_SYNC_FROM_ADAT1:
2635                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2636                 break;
2637         case HDSP_SYNC_FROM_ADAT2:
2638                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2639                 break;
2640         case HDSP_SYNC_FROM_ADAT3:
2641                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2642                 break;
2643         case HDSP_SYNC_FROM_SPDIF:
2644                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2645                 break;
2646         case HDSP_SYNC_FROM_WORD:
2647                 hdsp->control_register |= HDSP_SyncRef_WORD;
2648                 break;
2649         case HDSP_SYNC_FROM_ADAT_SYNC:
2650                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2651                 break;
2652         default:
2653                 return -1;
2654         }
2655         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2656         return 0;
2657 }
2658
2659 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2660 {
2661         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2662         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2663
2664         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2665         uinfo->count = 1;
2666
2667         switch (hdsp->io_type) {
2668         case Digiface:
2669         case H9652:
2670                 uinfo->value.enumerated.items = 6;
2671                 break;
2672         case Multiface:
2673                 uinfo->value.enumerated.items = 4;
2674                 break;
2675         case H9632:
2676                 uinfo->value.enumerated.items = 3;
2677                 break;
2678         default:
2679                 uinfo->value.enumerated.items = 0;
2680                 break;
2681         }
2682
2683         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2684                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2685         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2686         return 0;
2687 }
2688
2689 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2690 {
2691         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2692
2693         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2694         return 0;
2695 }
2696
2697 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2698 {
2699         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2700         unsigned long flags;
2701         int change, max;
2702         unsigned int val;
2703
2704         if (!snd_hdsp_use_is_exclusive(hdsp))
2705                 return -EBUSY;
2706
2707         switch (hdsp->io_type) {
2708         case Digiface:
2709         case H9652:
2710                 max = 6;
2711                 break;
2712         case Multiface:
2713                 max = 4;
2714                 break;
2715         case H9632:
2716                 max = 3;
2717                 break;
2718         default:
2719                 return -EIO;
2720         }
2721
2722         val = ucontrol->value.enumerated.item[0] % max;
2723         spin_lock_irqsave(&hdsp->lock, flags);
2724         change = (int)val != hdsp_pref_sync_ref(hdsp);
2725         hdsp_set_pref_sync_ref(hdsp, val);
2726         spin_unlock_irqrestore(&hdsp->lock, flags);
2727         return change;
2728 }
2729
2730 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2731 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2732   .name = xname, \
2733   .index = xindex, \
2734   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2735   .info = snd_hdsp_info_autosync_ref, \
2736   .get = snd_hdsp_get_autosync_ref, \
2737 }
2738
2739 static int hdsp_autosync_ref(hdsp_t *hdsp)
2740 {
2741         /* This looks at the autosync selected sync reference */
2742         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2743
2744         switch (status2 & HDSP_SelSyncRefMask) {
2745         case HDSP_SelSyncRef_WORD:
2746                 return HDSP_AUTOSYNC_FROM_WORD;
2747         case HDSP_SelSyncRef_ADAT_SYNC:
2748                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2749         case HDSP_SelSyncRef_SPDIF:
2750                 return HDSP_AUTOSYNC_FROM_SPDIF;
2751         case HDSP_SelSyncRefMask:
2752                 return HDSP_AUTOSYNC_FROM_NONE;
2753         case HDSP_SelSyncRef_ADAT1:
2754                 return HDSP_AUTOSYNC_FROM_ADAT1;
2755         case HDSP_SelSyncRef_ADAT2:
2756                 return HDSP_AUTOSYNC_FROM_ADAT2;
2757         case HDSP_SelSyncRef_ADAT3:
2758                 return HDSP_AUTOSYNC_FROM_ADAT3;
2759         default:
2760                 return HDSP_AUTOSYNC_FROM_WORD;
2761         }
2762         return 0;
2763 }
2764
2765 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2766 {
2767         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2768
2769         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2770         uinfo->count = 1;
2771         uinfo->value.enumerated.items = 7;
2772         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2773                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2774         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2775         return 0;
2776 }
2777
2778 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2779 {
2780         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2781
2782         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2783         return 0;
2784 }
2785
2786 #define HDSP_PASSTHRU(xname, xindex) \
2787 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2788   .name = xname, \
2789   .index = xindex, \
2790   .info = snd_hdsp_info_passthru, \
2791   .put = snd_hdsp_put_passthru, \
2792   .get = snd_hdsp_get_passthru \
2793 }
2794
2795 static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
2796 {
2797         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2798         uinfo->count = 1;
2799         uinfo->value.integer.min = 0;
2800         uinfo->value.integer.max = 1;
2801         return 0;
2802 }
2803
2804 static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2805 {
2806         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2807         unsigned long flags;
2808
2809         spin_lock_irqsave(&hdsp->lock, flags);
2810         ucontrol->value.integer.value[0] = hdsp->passthru;
2811         spin_unlock_irqrestore(&hdsp->lock, flags);
2812         return 0;
2813 }
2814
2815 static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2816 {
2817         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2818         unsigned long flags;
2819         int change;
2820         unsigned int val;
2821         int err = 0;
2822
2823         if (!snd_hdsp_use_is_exclusive(hdsp))
2824                 return -EBUSY;
2825
2826         val = ucontrol->value.integer.value[0] & 1;
2827         spin_lock_irqsave(&hdsp->lock, flags);
2828         change = (ucontrol->value.integer.value[0] != hdsp->passthru);
2829         if (change)
2830                 err = hdsp_set_passthru(hdsp, val);
2831         spin_unlock_irqrestore(&hdsp->lock, flags);
2832         return err ? err : change;
2833 }
2834
2835 #define HDSP_LINE_OUT(xname, xindex) \
2836 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2837   .name = xname, \
2838   .index = xindex, \
2839   .info = snd_hdsp_info_line_out, \
2840   .get = snd_hdsp_get_line_out, \
2841   .put = snd_hdsp_put_line_out \
2842 }
2843
2844 static int hdsp_line_out(hdsp_t *hdsp)
2845 {
2846         return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2847 }
2848
2849 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2850 {
2851         if (out) {
2852                 hdsp->control_register |= HDSP_LineOut;
2853         } else {
2854                 hdsp->control_register &= ~HDSP_LineOut;
2855         }
2856         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2857         return 0;
2858 }
2859
2860 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2861 {
2862         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2863         uinfo->count = 1;
2864         uinfo->value.integer.min = 0;
2865         uinfo->value.integer.max = 1;
2866         return 0;
2867 }
2868
2869 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2870 {
2871         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2872         unsigned long flags;
2873
2874         spin_lock_irqsave(&hdsp->lock, flags);
2875         ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2876         spin_unlock_irqrestore(&hdsp->lock, flags);
2877         return 0;
2878 }
2879
2880 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2881 {
2882         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2883         unsigned long flags;
2884         int change;
2885         unsigned int val;
2886
2887         if (!snd_hdsp_use_is_exclusive(hdsp))
2888                 return -EBUSY;
2889         val = ucontrol->value.integer.value[0] & 1;
2890         spin_lock_irqsave(&hdsp->lock, flags);
2891         change = (int)val != hdsp_line_out(hdsp);
2892         hdsp_set_line_output(hdsp, val);
2893         spin_unlock_irqrestore(&hdsp->lock, flags);
2894         return change;
2895 }
2896
2897 #define HDSP_MIXER(xname, xindex) \
2898 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2899   .name = xname, \
2900   .index = xindex, \
2901   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2902                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2903   .info = snd_hdsp_info_mixer, \
2904   .get = snd_hdsp_get_mixer, \
2905   .put = snd_hdsp_put_mixer \
2906 }
2907
2908 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2909 {
2910         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2911         uinfo->count = 3;
2912         uinfo->value.integer.min = 0;
2913         uinfo->value.integer.max = 65536;
2914         uinfo->value.integer.step = 1;
2915         return 0;
2916 }
2917
2918 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2919 {
2920         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2921         unsigned long flags;
2922         int source;
2923         int destination;
2924         int addr;
2925
2926         source = ucontrol->value.integer.value[0];
2927         destination = ucontrol->value.integer.value[1];
2928
2929         if (source >= hdsp->max_channels) {
2930                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2931         } else {
2932                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2933         }
2934
2935         spin_lock_irqsave(&hdsp->lock, flags);
2936         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2937         spin_unlock_irqrestore(&hdsp->lock, flags);
2938         return 0;
2939 }
2940
2941 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2942 {
2943         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
2944         unsigned long flags;
2945         int change;
2946         int source;
2947         int destination;
2948         int gain;
2949         int addr;
2950
2951         if (!snd_hdsp_use_is_exclusive(hdsp))
2952                 return -EBUSY;
2953
2954         source = ucontrol->value.integer.value[0];
2955         destination = ucontrol->value.integer.value[1];
2956
2957         if (source >= hdsp->max_channels) {
2958                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2959         } else {
2960                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2961         }
2962
2963         gain = ucontrol->value.integer.value[2];
2964
2965         spin_lock_irqsave(&hdsp->lock, flags);
2966         change = gain != hdsp_read_gain(hdsp, addr);
2967         if (change)
2968                 hdsp_write_gain(hdsp, addr, gain);
2969         spin_unlock_irqrestore(&hdsp->lock, flags);
2970         return change;
2971 }
2972
2973 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2974 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2975   .name = xname, \
2976   .index = xindex, \
2977   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2978   .info = snd_hdsp_info_sync_check, \
2979   .get = snd_hdsp_get_wc_sync_check \
2980 }
2981
2982 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2983 {
2984         static char *texts[] = {"No Lock", "Lock", "Sync" };
2985         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2986         uinfo->count = 1;
2987         uinfo->value.enumerated.items = 3;
2988         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2989                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2990         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2991         return 0;
2992 }
2993
2994 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2995 {
2996         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2997         if (status2 & HDSP_wc_lock) {
2998                 if (status2 & HDSP_wc_sync) {
2999                         return 2;
3000                 } else {
3001                          return 1;
3002                 }
3003         } else {
3004                 return 0;
3005         }
3006         return 0;
3007 }
3008
3009 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3010 {
3011         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3012
3013         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
3014         return 0;
3015 }
3016
3017 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
3018 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3019   .name = xname, \
3020   .index = xindex, \
3021   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3022   .info = snd_hdsp_info_sync_check, \
3023   .get = snd_hdsp_get_spdif_sync_check \
3024 }
3025
3026 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
3027 {
3028         int status = hdsp_read(hdsp, HDSP_statusRegister);
3029         if (status & HDSP_SPDIFErrorFlag) {
3030                 return 0;
3031         } else {
3032                 if (status & HDSP_SPDIFSync) {
3033                         return 2;
3034                 } else {
3035                         return 1;
3036                 }
3037         }
3038         return 0;
3039 }
3040
3041 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3042 {
3043         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3044
3045         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3046         return 0;
3047 }
3048
3049 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3050 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3051   .name = xname, \
3052   .index = xindex, \
3053   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3054   .info = snd_hdsp_info_sync_check, \
3055   .get = snd_hdsp_get_adatsync_sync_check \
3056 }
3057
3058 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3059 {
3060         int status = hdsp_read(hdsp, HDSP_statusRegister);
3061         if (status & HDSP_TimecodeLock) {
3062                 if (status & HDSP_TimecodeSync) {
3063                         return 2;
3064                 } else {
3065                         return 1;
3066                 }
3067         } else {
3068                 return 0;
3069         }
3070 }
3071
3072 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3073 {
3074         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3075
3076         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3077         return 0;
3078 }
3079
3080 #define HDSP_ADAT_SYNC_CHECK \
3081 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3082   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3083   .info = snd_hdsp_info_sync_check, \
3084   .get = snd_hdsp_get_adat_sync_check \
3085 }
3086
3087 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3088 {
3089         int status = hdsp_read(hdsp, HDSP_statusRegister);
3090
3091         if (status & (HDSP_Lock0>>idx)) {
3092                 if (status & (HDSP_Sync0>>idx)) {
3093                         return 2;
3094                 } else {
3095                         return 1;
3096                 }
3097         } else {
3098                 return 0;
3099         }
3100 }
3101
3102 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3103 {
3104         int offset;
3105         hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
3106
3107         offset = ucontrol->id.index - 1;
3108         snd_assert(offset >= 0);
3109
3110         switch (hdsp->io_type) {
3111         case Digiface:
3112         case H9652:
3113                 if (offset >= 3)
3114                         return -EINVAL;
3115                 break;
3116         case Multiface:
3117         case H9632:
3118                 if (offset >= 1)
3119                         return -EINVAL;
3120                 break;
3121         default:
3122                 return -EIO;
3123         }
3124
3125         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3126         return 0;
3127 }
3128
3129 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3130 HDSP_DA_GAIN("DA Gain", 0),
3131 HDSP_AD_GAIN("AD Gain", 0),
3132 HDSP_PHONE_GAIN("Phones Gain", 0),
3133 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3134 };
3135
3136 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3137 {
3138         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3139         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3140         .info =         snd_hdsp_control_spdif_info,
3141         .get =          snd_hdsp_control_spdif_get,
3142         .put =          snd_hdsp_control_spdif_put,
3143 },
3144 {
3145         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3146         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3147         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3148         .info =         snd_hdsp_control_spdif_stream_info,
3149         .get =          snd_hdsp_control_spdif_stream_get,
3150         .put =          snd_hdsp_control_spdif_stream_put,
3151 },
3152 {
3153         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3154         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3155         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3156         .info =         snd_hdsp_control_spdif_mask_info,
3157         .get =          snd_hdsp_control_spdif_mask_get,
3158         .private_value = IEC958_AES0_NONAUDIO |
3159                          IEC958_AES0_PROFESSIONAL |
3160                          IEC958_AES0_CON_EMPHASIS,
3161 },
3162 {
3163         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3164         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3165         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3166         .info =         snd_hdsp_control_spdif_mask_info,
3167         .get =          snd_hdsp_control_spdif_mask_get,
3168         .private_value = IEC958_AES0_NONAUDIO |
3169                          IEC958_AES0_PROFESSIONAL |
3170                          IEC958_AES0_PRO_EMPHASIS,
3171 },
3172 HDSP_MIXER("Mixer", 0),
3173 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3174 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3175 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3176 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3177 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3178 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3179 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3180 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3181 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3182 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3183 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3184 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3185 /* 'External Rate' complies with the alsa control naming scheme */
3186 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3187 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3188 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3189 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3190 HDSP_PASSTHRU("Passthru", 0),
3191 HDSP_LINE_OUT("Line Out", 0),
3192 };
3193
3194 #define HDSP_CONTROLS (sizeof(snd_hdsp_controls)/sizeof(snd_kcontrol_new_t))
3195
3196 #define HDSP_9632_CONTROLS (sizeof(snd_hdsp_9632_controls)/sizeof(snd_kcontrol_new_t))
3197
3198 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3199 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3200
3201 int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3202 {
3203         unsigned int idx;
3204         int err;
3205         snd_kcontrol_t *kctl;
3206
3207         for (idx = 0; idx < HDSP_CONTROLS; idx++) {
3208                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3209                         return err;
3210                 }
3211                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3212                         hdsp->spdif_ctl = kctl;
3213         }
3214
3215         /* ADAT SyncCheck status */
3216         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3217         snd_hdsp_adat_sync_check.index = 1;
3218         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3219                 return err;
3220         }
3221         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3222                 for (idx = 1; idx < 3; ++idx) {
3223                         snd_hdsp_adat_sync_check.index = idx+1;
3224                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3225                                 return err;
3226                         }
3227                 }
3228         }
3229
3230         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3231         if (hdsp->io_type == H9632) {
3232                 for (idx = 0; idx < HDSP_9632_CONTROLS; idx++) {
3233                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3234                                 return err;
3235                         }
3236                 }
3237         }
3238
3239         /* AEB control for H96xx card */
3240         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3241                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3242                                 return err;
3243                 }
3244         }
3245
3246         return 0;
3247 }
3248
3249 /*------------------------------------------------------------
3250    /proc interface
3251  ------------------------------------------------------------*/
3252
3253 static void
3254 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3255 {
3256         hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3257         unsigned int status;
3258         unsigned int status2;
3259         char *pref_sync_ref;
3260         char *autosync_ref;
3261         char *system_clock_mode;
3262         char *clock_source;
3263         int x;
3264
3265         if (hdsp_check_for_iobox (hdsp)) {
3266                 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3267                 return;
3268         }
3269
3270         if (hdsp_check_for_firmware(hdsp)) {
3271                 if (hdsp->state & HDSP_FirmwareCached) {
3272                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3273                                 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3274                                 return;
3275                         }
3276                 } else {
3277                         snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3278                         return;
3279                 }
3280         }
3281
3282         status = hdsp_read(hdsp, HDSP_statusRegister);
3283         status2 = hdsp_read(hdsp, HDSP_status2Register);
3284
3285         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3286         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3287                     hdsp->capture_buffer, hdsp->playback_buffer);
3288         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3289                     hdsp->irq, hdsp->port, hdsp->iobase);
3290         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3291         snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3292         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3293         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3294         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3295
3296         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3297         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3298         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3299         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3300
3301         snd_iprintf(buffer, "\n");
3302
3303         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3304
3305         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3306         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3307         snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
3308         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3309
3310         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3311
3312         snd_iprintf(buffer, "\n");
3313
3314
3315         switch (hdsp_clock_source(hdsp)) {
3316         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3317                 clock_source = "AutoSync";
3318                 break;
3319         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3320                 clock_source = "Internal 32 kHz";
3321                 break;
3322         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3323                 clock_source = "Internal 44.1 kHz";
3324                 break;
3325         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3326                 clock_source = "Internal 48 kHz";
3327                 break;
3328         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3329                 clock_source = "Internal 64 kHz";
3330                 break;
3331         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3332                 clock_source = "Internal 88.2 kHz";
3333                 break;
3334         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3335                 clock_source = "Internal 96 kHz";
3336                 break;
3337         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3338                 clock_source = "Internal 128 kHz";
3339                 break;
3340         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3341                 clock_source = "Internal 176.4 kHz";
3342                 break;
3343                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3344                 clock_source = "Internal 192 kHz";
3345                 break;
3346         default:
3347                 clock_source = "Error";
3348         }
3349         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3350
3351         if (hdsp_system_clock_mode(hdsp)) {
3352                 system_clock_mode = "Slave";
3353         } else {
3354                 system_clock_mode = "Master";
3355         }
3356
3357         switch (hdsp_pref_sync_ref (hdsp)) {
3358         case HDSP_SYNC_FROM_WORD:
3359                 pref_sync_ref = "Word Clock";
3360                 break;
3361         case HDSP_SYNC_FROM_ADAT_SYNC:
3362                 pref_sync_ref = "ADAT Sync";
3363                 break;
3364         case HDSP_SYNC_FROM_SPDIF:
3365                 pref_sync_ref = "SPDIF";
3366                 break;
3367         case HDSP_SYNC_FROM_ADAT1:
3368                 pref_sync_ref = "ADAT1";
3369                 break;
3370         case HDSP_SYNC_FROM_ADAT2:
3371                 pref_sync_ref = "ADAT2";
3372                 break;
3373         case HDSP_SYNC_FROM_ADAT3:
3374                 pref_sync_ref = "ADAT3";
3375                 break;
3376         default:
3377                 pref_sync_ref = "Word Clock";
3378                 break;
3379         }
3380         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3381
3382         switch (hdsp_autosync_ref (hdsp)) {
3383         case HDSP_AUTOSYNC_FROM_WORD:
3384                 autosync_ref = "Word Clock";
3385                 break;
3386         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3387                 autosync_ref = "ADAT Sync";
3388                 break;
3389         case HDSP_AUTOSYNC_FROM_SPDIF:
3390                 autosync_ref = "SPDIF";
3391                 break;
3392         case HDSP_AUTOSYNC_FROM_NONE:
3393                 autosync_ref = "None";
3394                 break;
3395         case HDSP_AUTOSYNC_FROM_ADAT1:
3396                 autosync_ref = "ADAT1";
3397                 break;
3398         case HDSP_AUTOSYNC_FROM_ADAT2:
3399                 autosync_ref = "ADAT2";
3400                 break;
3401         case HDSP_AUTOSYNC_FROM_ADAT3:
3402                 autosync_ref = "ADAT3";
3403                 break;
3404         default:
3405                 autosync_ref = "---";
3406                 break;
3407         }
3408         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3409
3410         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3411
3412         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3413
3414         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3415
3416         snd_iprintf(buffer, "\n");
3417
3418         switch (hdsp_spdif_in(hdsp)) {
3419         case HDSP_SPDIFIN_OPTICAL:
3420                 snd_iprintf(buffer, "IEC958 input: Optical\n");
3421                 break;
3422         case HDSP_SPDIFIN_COAXIAL:
3423                 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3424                 break;
3425         case HDSP_SPDIFIN_INTERNAL:
3426                 snd_iprintf(buffer, "IEC958 input: Internal\n");
3427                 break;
3428         case HDSP_SPDIFIN_AES:
3429                 snd_iprintf(buffer, "IEC958 input: AES\n");
3430                 break;
3431         default:
3432                 snd_iprintf(buffer, "IEC958 input: ???\n");
3433                 break;
3434         }
3435
3436         if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3437                 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3438         } else {
3439                 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3440         }
3441
3442         if (hdsp->control_register & HDSP_SPDIFProfessional) {
3443                 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3444         } else {
3445                 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3446         }
3447
3448         if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3449                 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3450         } else {
3451                 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3452         }
3453
3454         if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3455                 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3456         } else {
3457                 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3458         }
3459         if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3460                 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3461         } else {
3462                 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3463         }
3464
3465         snd_iprintf(buffer, "\n");
3466
3467         /* Sync Check */
3468         x = status & HDSP_Sync0;
3469         if (status & HDSP_Lock0) {
3470                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3471         } else {
3472                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3473         }
3474
3475         switch (hdsp->io_type) {
3476         case Digiface:
3477         case H9652:
3478                 x = status & HDSP_Sync1;
3479                 if (status & HDSP_Lock1) {
3480                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3481                 } else {
3482                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3483                 }
3484                 x = status & HDSP_Sync2;
3485                 if (status & HDSP_Lock2) {
3486                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3487                 } else {
3488                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3489                 }
3490         default:
3491                 /* relax */
3492                 break;
3493         }
3494
3495         x = status & HDSP_SPDIFSync;
3496         if (status & HDSP_SPDIFErrorFlag) {
3497                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3498         } else {
3499                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3500         }
3501
3502         x = status2 & HDSP_wc_sync;
3503         if (status2 & HDSP_wc_lock) {
3504                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3505         } else {
3506                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3507         }
3508
3509         x = status & HDSP_TimecodeSync;
3510         if (status & HDSP_TimecodeLock) {
3511                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3512         } else {
3513                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3514         }
3515
3516         snd_iprintf(buffer, "\n");
3517
3518         /* Informations about H9632 specific controls */
3519         if (hdsp->io_type == H9632) {
3520                 char *tmp;
3521
3522                 switch (hdsp_ad_gain(hdsp)) {
3523                 case 0:
3524                         tmp = "-10 dBV";
3525                         break;
3526                 case 1:
3527                         tmp = "+4 dBu";
3528                         break;
3529                 default:
3530                         tmp = "Lo Gain";
3531                         break;
3532                 }
3533                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3534
3535                 switch (hdsp_da_gain(hdsp)) {
3536                 case 0:
3537                         tmp = "Hi Gain";
3538                         break;
3539                 case 1:
3540                         tmp = "+4 dBu";
3541                         break;
3542                 default:
3543                         tmp = "-10 dBV";
3544                         break;
3545                 }
3546                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3547
3548                 switch (hdsp_phone_gain(hdsp)) {
3549                 case 0:
3550                         tmp = "0 dB";
3551                         break;
3552                 case 1:
3553                         tmp = "-6 dB";
3554                         break;
3555                 default:
3556                         tmp = "-12 dB";
3557                         break;
3558                 }
3559                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3560
3561                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3562
3563                 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3564                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3565                 } else {
3566                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3567                 }
3568                 snd_iprintf(buffer, "\n");
3569         }
3570
3571 }
3572
3573 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3574 {
3575         snd_info_entry_t *entry;
3576
3577         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3578                 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3579 }
3580
3581 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3582 {
3583         if (hdsp->capture_buffer_unaligned) {
3584                 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES,
3585                                            hdsp->capture_buffer_unaligned,
3586                                            hdsp->capture_buffer_addr, 1);
3587         }
3588
3589         if (hdsp->playback_buffer_unaligned) {
3590                 snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES,
3591                                            hdsp->playback_buffer_unaligned,
3592                                            hdsp->playback_buffer_addr, 0);
3593         }
3594 }
3595
3596 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3597 {
3598         void *pb, *cb;
3599         dma_addr_t pb_addr, cb_addr;
3600         unsigned long pb_bus, cb_bus;
3601
3602         cb = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, &cb_addr, 1);
3603         pb = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, &pb_addr, 0);
3604
3605         if (cb == 0 || pb == 0) {
3606                 if (cb) {
3607                         snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, cb, cb_addr, 1);
3608                 }
3609                 if (pb) {
3610                         snd_hammerfall_free_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES, pb, pb_addr, 0);
3611                 }
3612
3613                 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3614                 return -ENOMEM;
3615         }
3616
3617         /* save raw addresses for use when freeing memory later */
3618
3619         hdsp->capture_buffer_unaligned = cb;
3620         hdsp->playback_buffer_unaligned = pb;
3621         hdsp->capture_buffer_addr = cb_addr;
3622         hdsp->playback_buffer_addr = pb_addr;
3623
3624         /* Align to bus-space 64K boundary */
3625
3626         cb_bus = (cb_addr + 0xFFFF) & ~0xFFFFl;
3627         pb_bus = (pb_addr + 0xFFFF) & ~0xFFFFl;
3628
3629         /* Tell the card where it is */
3630
3631         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3632         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3633
3634         hdsp->capture_buffer = cb + (cb_bus - cb_addr);
3635         hdsp->playback_buffer = pb + (pb_bus - pb_addr);
3636
3637         return 0;
3638 }
3639
3640 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3641 {
3642         unsigned int i;
3643
3644         /* ASSUMPTION: hdsp->lock is either held, or
3645            there is no need to hold it (e.g. during module
3646            initalization).
3647          */
3648
3649         /* set defaults:
3650
3651            SPDIF Input via Coax
3652            Master clock mode
3653            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3654                             which implies 2 4096 sample, 32Kbyte periods).
3655            Enable line out.
3656          */
3657
3658         hdsp->control_register = HDSP_ClockModeMaster |
3659                                  HDSP_SPDIFInputCoaxial |
3660                                  hdsp_encode_latency(7) |
3661                                  HDSP_LineOut;
3662
3663
3664         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3665
3666 #ifdef SNDRV_BIG_ENDIAN
3667         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3668 #else
3669         hdsp->control2_register = 0;
3670 #endif
3671         if (hdsp->io_type == H9652) {
3672                 snd_hdsp_9652_enable_mixer (hdsp);
3673         } else {
3674             hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3675         }
3676
3677         hdsp_reset_hw_pointer(hdsp);
3678         hdsp_compute_period_size(hdsp);
3679
3680         /* silence everything */
3681
3682         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3683                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3684         }
3685
3686         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3687                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3688                         return -EIO;
3689                 }
3690         }
3691
3692         if ((hdsp->io_type != H9652) && line_outs_monitor[hdsp->dev]) {
3693
3694                 int lineouts_base;
3695
3696                 snd_printk ("sending all inputs and playback streams to line outs.\n");
3697
3698                 /* route all inputs to the line outs for easy monitoring. send
3699                    odd numbered channels to right, even to left.
3700                 */
3701                 if (hdsp->io_type == H9632) {
3702                         /* this is the phones/analog output */
3703                         lineouts_base = 10;
3704                 } else {
3705                         lineouts_base = 26;
3706                 }
3707
3708                 for (i = 0; i < hdsp->max_channels; i++) {
3709                         if (i & 1) {
3710                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN) ||
3711                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base), UNITY_GAIN)) {
3712                                     return -EIO;
3713                                 }
3714                         } else {
3715                                 if (hdsp_write_gain (hdsp, hdsp_input_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN) ||
3716                                     hdsp_write_gain (hdsp, hdsp_playback_to_output_key (hdsp, i, lineouts_base+1), UNITY_GAIN)) {
3717
3718                                     return -EIO;
3719                                 }
3720                         }
3721                 }
3722         }
3723
3724         hdsp->passthru = 0;
3725
3726         /* H9632 specific defaults */
3727         if (hdsp->io_type == H9632) {
3728                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3729                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3730         }
3731
3732         /* set a default rate so that the channel map is set up.
3733          */
3734
3735         hdsp_set_rate(hdsp, 48000, 1);
3736
3737         return 0;
3738 }
3739
3740 void hdsp_midi_tasklet(unsigned long arg)
3741 {
3742         hdsp_t *hdsp = (hdsp_t *)arg;
3743
3744         if (hdsp->midi[0].pending) {
3745                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3746         }
3747         if (hdsp->midi[1].pending) {
3748                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3749         }
3750 }
3751
3752 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3753 {
3754         hdsp_t *hdsp = (hdsp_t *) dev_id;
3755         unsigned int status;
3756         int audio;
3757         int midi0;
3758         int midi1;
3759         unsigned int midi0status;
3760         unsigned int midi1status;
3761         int schedule = 0;
3762
3763         status = hdsp_read(hdsp, HDSP_statusRegister);
3764
3765         audio = status & HDSP_audioIRQPending;
3766         midi0 = status & HDSP_midi0IRQPending;
3767         midi1 = status & HDSP_midi1IRQPending;
3768
3769         if (!audio && !midi0 && !midi1) {
3770                 return IRQ_NONE;
3771         }
3772
3773         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3774
3775         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3776         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3777
3778         if (audio) {
3779                 if (hdsp->capture_substream) {
3780                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3781                 }
3782
3783                 if (hdsp->playback_substream) {
3784                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3785                 }
3786         }
3787
3788         if (midi0 && midi0status) {
3789                 /* we disable interrupts for this input until processing is done */
3790                 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3791                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3792                 hdsp->midi[0].pending = 1;
3793                 schedule = 1;
3794         }
3795         if (midi1 && midi1status) {
3796                 /* we disable interrupts for this input until processing is done */
3797                 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3798                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3799                 hdsp->midi[1].pending = 1;
3800                 schedule = 1;
3801         }
3802         if (schedule)
3803             tasklet_hi_schedule(&hdsp->midi_tasklet);
3804         return IRQ_HANDLED;
3805 }
3806
3807 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3808 {
3809         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3810         return hdsp_hw_pointer(hdsp);
3811 }
3812
3813 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3814                                              int stream,
3815                                              int channel)
3816
3817 {
3818         int mapped_channel;
3819
3820         snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3821
3822         if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3823                 return NULL;
3824         }
3825
3826         if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3827                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3828         } else {
3829                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3830         }
3831 }
3832
3833 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3834                                   snd_pcm_uframes_t pos, void *src, snd_pcm_uframes_t count)
3835 {
3836         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3837         char *channel_buf;
3838
3839         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3840
3841         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3842         snd_assert(channel_buf != NULL, return -EIO);
3843         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3844                 return -EFAULT;
3845         return count;
3846 }
3847
3848 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3849                                  snd_pcm_uframes_t pos, void *dst, snd_pcm_uframes_t count)
3850 {
3851         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3852         char *channel_buf;
3853
3854         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3855
3856         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3857         snd_assert(channel_buf != NULL, return -EIO);
3858         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3859                 return -EFAULT;
3860         return count;
3861 }
3862
3863 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3864                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3865 {
3866         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3867         char *channel_buf;
3868
3869         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3870         snd_assert(channel_buf != NULL, return -EIO);
3871         memset(channel_buf + pos * 4, 0, count * 4);
3872         return count;
3873 }
3874
3875 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3876 {
3877         snd_pcm_runtime_t *runtime = substream->runtime;
3878         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3879         snd_pcm_substream_t *other;
3880         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3881                 other = hdsp->capture_substream;
3882         else
3883                 other = hdsp->playback_substream;
3884         if (hdsp->running)
3885                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3886         else
3887                 runtime->status->hw_ptr = 0;
3888         if (other) {
3889                 struct list_head *pos;
3890                 snd_pcm_substream_t *s;
3891                 snd_pcm_runtime_t *oruntime = other->runtime;
3892                 snd_pcm_group_for_each(pos, substream) {
3893                         s = snd_pcm_group_substream_entry(pos);
3894                         if (s == other) {
3895                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3896                                 break;
3897                         }
3898                 }
3899         }
3900         return 0;
3901 }
3902
3903 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3904                                  snd_pcm_hw_params_t *params)
3905 {
3906         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3907         int err;
3908         pid_t this_pid;
3909         pid_t other_pid;
3910
3911         if (hdsp_check_for_iobox (hdsp)) {
3912                 return -EIO;
3913         }
3914
3915         if (hdsp_check_for_firmware(hdsp)) {
3916                 if (hdsp->state & HDSP_FirmwareCached) {
3917                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3918                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
3919                         }
3920                 } else {
3921                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
3922                 }
3923                 return -EIO;
3924         }
3925
3926         spin_lock_irq(&hdsp->lock);
3927
3928         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3929                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3930                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3931                 this_pid = hdsp->playback_pid;
3932                 other_pid = hdsp->capture_pid;
3933         } else {
3934                 this_pid = hdsp->capture_pid;
3935                 other_pid = hdsp->playback_pid;
3936         }
3937
3938         if ((other_pid > 0) && (this_pid != other_pid)) {
3939
3940                 /* The other stream is open, and not by the same
3941                    task as this one. Make sure that the parameters
3942                    that matter are the same.
3943                  */
3944
3945                 if (params_rate(params) != hdsp->system_sample_rate) {
3946                         spin_unlock_irq(&hdsp->lock);
3947                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3948                         return -EBUSY;
3949                 }
3950
3951                 if (params_period_size(params) != hdsp->period_bytes / 4) {
3952                         spin_unlock_irq(&hdsp->lock);
3953                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3954                         return -EBUSY;
3955                 }
3956
3957                 /* We're fine. */
3958
3959                 spin_unlock_irq(&hdsp->lock);
3960                 return 0;
3961
3962         } else {
3963                 spin_unlock_irq(&hdsp->lock);
3964         }
3965
3966         /* how to make sure that the rate matches an externally-set one ?
3967          */
3968
3969         spin_lock_irq(&hdsp->lock);
3970         if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3971                 spin_unlock_irq(&hdsp->lock);
3972                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3973                 return err;
3974         } else {
3975                 spin_unlock_irq(&hdsp->lock);
3976         }
3977
3978         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3979                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3980                 return err;
3981         }
3982
3983         return 0;
3984 }
3985
3986 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3987                                     snd_pcm_channel_info_t *info)
3988 {
3989         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
3990         int mapped_channel;
3991
3992         snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3993
3994         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3995                 return -EINVAL;
3996         }
3997
3998         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3999         info->first = 0;
4000         info->step = 32;
4001         return 0;
4002 }
4003
4004 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
4005                              unsigned int cmd, void *arg)
4006 {
4007         switch (cmd) {
4008         case SNDRV_PCM_IOCTL1_RESET:
4009         {
4010                 return snd_hdsp_reset(substream);
4011         }
4012         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4013         {
4014                 snd_pcm_channel_info_t *info = arg;
4015                 return snd_hdsp_channel_info(substream, info);
4016         }
4017         default:
4018                 break;
4019         }
4020
4021         return snd_pcm_lib_ioctl(substream, cmd, arg);
4022 }
4023
4024 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
4025 {
4026         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4027         snd_pcm_substream_t *other;
4028         int running;
4029
4030         if (hdsp_check_for_iobox (hdsp)) {
4031                 return -EIO;
4032         }
4033
4034         if (hdsp_check_for_firmware(hdsp)) {
4035                 if (hdsp->state & HDSP_FirmwareCached) {
4036                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4037                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4038                         }
4039                 } else {
4040                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4041                 }
4042                 return -EIO;
4043         }
4044
4045         spin_lock(&hdsp->lock);
4046         running = hdsp->running;
4047         switch (cmd) {
4048         case SNDRV_PCM_TRIGGER_START:
4049                 running |= 1 << substream->stream;
4050                 break;
4051         case SNDRV_PCM_TRIGGER_STOP:
4052                 running &= ~(1 << substream->stream);
4053                 break;
4054         default:
4055                 snd_BUG();
4056                 spin_unlock(&hdsp->lock);
4057                 return -EINVAL;
4058         }
4059         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4060                 other = hdsp->capture_substream;
4061         else
4062                 other = hdsp->playback_substream;
4063
4064         if (other) {
4065                 struct list_head *pos;
4066                 snd_pcm_substream_t *s;
4067                 snd_pcm_group_for_each(pos, substream) {
4068                         s = snd_pcm_group_substream_entry(pos);
4069                         if (s == other) {
4070                                 snd_pcm_trigger_done(s, substream);
4071                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4072                                         running |= 1 << s->stream;
4073                                 else
4074                                         running &= ~(1 << s->stream);
4075                                 goto _ok;
4076                         }
4077                 }
4078                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4079                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4080                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4081                                 hdsp_silence_playback(hdsp);
4082                 } else {
4083                         if (running &&
4084                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4085                                 hdsp_silence_playback(hdsp);
4086                 }
4087         } else {
4088                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4089                                 hdsp_silence_playback(hdsp);
4090         }
4091  _ok:
4092         snd_pcm_trigger_done(substream, substream);
4093         if (!hdsp->running && running)
4094                 hdsp_start_audio(hdsp);
4095         else if (hdsp->running && !running)
4096                 hdsp_stop_audio(hdsp);
4097         hdsp->running = running;
4098         spin_unlock(&hdsp->lock);
4099
4100         return 0;
4101 }
4102
4103 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4104 {
4105         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4106         int result = 0;
4107
4108         if (hdsp_check_for_iobox (hdsp)) {
4109                 return -EIO;
4110         }
4111
4112         if (hdsp_check_for_firmware(hdsp)) {
4113                 if (hdsp->state & HDSP_FirmwareCached) {
4114                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4115                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4116                         }
4117                 } else {
4118                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4119                 }
4120                 return -EIO;
4121         }
4122
4123         spin_lock_irq(&hdsp->lock);
4124         if (!hdsp->running)
4125                 hdsp_reset_hw_pointer(hdsp);
4126         spin_unlock_irq(&hdsp->lock);
4127         return result;
4128 }
4129
4130 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4131 {
4132         .info =                 (SNDRV_PCM_INFO_MMAP |
4133                                  SNDRV_PCM_INFO_MMAP_VALID |
4134                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4135                                  SNDRV_PCM_INFO_SYNC_START |
4136                                  SNDRV_PCM_INFO_DOUBLE),
4137         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4138         .rates =                (SNDRV_PCM_RATE_32000 |
4139                                  SNDRV_PCM_RATE_44100 |
4140                                  SNDRV_PCM_RATE_48000 |
4141                                  SNDRV_PCM_RATE_64000 |
4142                                  SNDRV_PCM_RATE_88200 |
4143                                  SNDRV_PCM_RATE_96000),
4144         .rate_min =             32000,
4145         .rate_max =             96000,
4146         .channels_min =         14,
4147         .channels_max =         HDSP_MAX_CHANNELS,
4148         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4149         .period_bytes_min =     (64 * 4) * 10,
4150         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4151         .periods_min =          2,
4152         .periods_max =          2,
4153         .fifo_size =            0
4154 };
4155
4156 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4157 {
4158         .info =                 (SNDRV_PCM_INFO_MMAP |
4159                                  SNDRV_PCM_INFO_MMAP_VALID |
4160                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4161                                  SNDRV_PCM_INFO_SYNC_START),
4162         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4163         .rates =                (SNDRV_PCM_RATE_32000 |
4164                                  SNDRV_PCM_RATE_44100 |
4165                                  SNDRV_PCM_RATE_48000 |
4166                                  SNDRV_PCM_RATE_64000 |
4167                                  SNDRV_PCM_RATE_88200 |
4168                                  SNDRV_PCM_RATE_96000),
4169         .rate_min =             32000,
4170         .rate_max =             96000,
4171         .channels_min =         14,
4172         .channels_max =         HDSP_MAX_CHANNELS,
4173         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4174         .period_bytes_min =     (64 * 4) * 10,
4175         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4176         .periods_min =          2,
4177         .periods_max =          2,
4178         .fifo_size =            0
4179 };
4180
4181 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4182
4183 #define HDSP_PERIOD_SIZES sizeof(hdsp_period_sizes) / sizeof(hdsp_period_sizes[0])
4184
4185 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4186         .count = HDSP_PERIOD_SIZES,
4187         .list = hdsp_period_sizes,
4188         .mask = 0
4189 };
4190
4191 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4192
4193 #define HDSP_9632_SAMPLE_RATES sizeof(hdsp_9632_sample_rates) / sizeof(hdsp_9632_sample_rates[0])
4194
4195 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4196         .count = HDSP_9632_SAMPLE_RATES,
4197         .list = hdsp_9632_sample_rates,
4198         .mask = 0
4199 };
4200
4201 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4202                                         snd_pcm_hw_rule_t *rule)
4203 {
4204         hdsp_t *hdsp = rule->private;
4205         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4206         if (hdsp->io_type == H9632) {
4207                 unsigned int list[3];
4208                 list[0] = hdsp->qs_in_channels;
4209                 list[1] = hdsp->ds_in_channels;
4210                 list[2] = hdsp->ss_in_channels;
4211                 return snd_interval_list(c, 3, list, 0);
4212         } else {
4213                 unsigned int list[2];
4214                 list[0] = hdsp->ds_in_channels;
4215                 list[1] = hdsp->ss_in_channels;
4216                 return snd_interval_list(c, 2, list, 0);
4217         }
4218 }
4219
4220 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4221                                         snd_pcm_hw_rule_t *rule)
4222 {
4223         unsigned int list[3];
4224         hdsp_t *hdsp = rule->private;
4225         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4226         if (hdsp->io_type == H9632) {
4227                 list[0] = hdsp->qs_out_channels;
4228                 list[1] = hdsp->ds_out_channels;
4229                 list[2] = hdsp->ss_out_channels;
4230                 return snd_interval_list(c, 3, list, 0);
4231         } else {
4232                 list[0] = hdsp->ds_out_channels;
4233                 list[1] = hdsp->ss_out_channels;
4234         }
4235         return snd_interval_list(c, 2, list, 0);
4236 }
4237
4238 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4239                                              snd_pcm_hw_rule_t *rule)
4240 {
4241         hdsp_t *hdsp = rule->private;
4242         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4243         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4244         if (r->min > 96000 && hdsp->io_type == H9632) {
4245                 snd_interval_t t = {
4246                         .min = hdsp->qs_in_channels,
4247                         .max = hdsp->qs_in_channels,
4248                         .integer = 1,
4249                 };
4250                 return snd_interval_refine(c, &t);
4251         } else if (r->min > 48000 && r->max <= 96000) {
4252                 snd_interval_t t = {
4253                         .min = hdsp->ds_in_channels,
4254                         .max = hdsp->ds_in_channels,
4255                         .integer = 1,
4256                 };
4257                 return snd_interval_refine(c, &t);
4258         } else if (r->max < 64000) {
4259                 snd_interval_t t = {
4260                         .min = hdsp->ss_in_channels,
4261                         .max = hdsp->ss_in_channels,
4262                         .integer = 1,
4263                 };
4264                 return snd_interval_refine(c, &t);
4265         }
4266         return 0;
4267 }
4268
4269 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4270                                              snd_pcm_hw_rule_t *rule)
4271 {
4272         hdsp_t *hdsp = rule->private;
4273         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4274         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4275         if (r->min > 96000 && hdsp->io_type == H9632) {
4276                 snd_interval_t t = {
4277                         .min = hdsp->qs_out_channels,
4278                         .max = hdsp->qs_out_channels,
4279                         .integer = 1,
4280                 };
4281                 return snd_interval_refine(c, &t);
4282         } else if (r->min > 48000 && r->max <= 96000) {
4283                 snd_interval_t t = {
4284                         .min = hdsp->ds_out_channels,
4285                         .max = hdsp->ds_out_channels,
4286                         .integer = 1,
4287                 };
4288                 return snd_interval_refine(c, &t);
4289         } else if (r->max < 64000) {
4290                 snd_interval_t t = {
4291                         .min = hdsp->ss_out_channels,
4292                         .max = hdsp->ss_out_channels,
4293                         .integer = 1,
4294                 };
4295                 return snd_interval_refine(c, &t);
4296         }
4297         return 0;
4298 }
4299
4300 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4301                                              snd_pcm_hw_rule_t *rule)
4302 {
4303         hdsp_t *hdsp = rule->private;
4304         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4305         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4306         if (c->min >= hdsp->ss_out_channels) {
4307                 snd_interval_t t = {
4308                         .min = 32000,
4309                         .max = 48000,
4310                         .integer = 1,
4311                 };
4312                 return snd_interval_refine(r, &t);
4313         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4314                 snd_interval_t t = {
4315                         .min = 128000,
4316                         .max = 192000,
4317                         .integer = 1,
4318                 };
4319                 return snd_interval_refine(r, &t);
4320         } else if (c->max <= hdsp->ds_out_channels) {
4321                 snd_interval_t t = {
4322                         .min = 64000,
4323                         .max = 96000,
4324                         .integer = 1,
4325                 };
4326                 return snd_interval_refine(r, &t);
4327         }
4328         return 0;
4329 }
4330
4331 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4332                                              snd_pcm_hw_rule_t *rule)
4333 {
4334         hdsp_t *hdsp = rule->private;
4335         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4336         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4337         if (c->min >= hdsp->ss_in_channels) {
4338                 snd_interval_t t = {
4339                         .min = 32000,
4340                         .max = 48000,
4341                         .integer = 1,
4342                 };
4343                 return snd_interval_refine(r, &t);
4344         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4345                 snd_interval_t t = {
4346                         .min = 128000,
4347                         .max = 192000,
4348                         .integer = 1,
4349                 };
4350                 return snd_interval_refine(r, &t);
4351         } else if (c->max <= hdsp->ds_in_channels) {
4352                 snd_interval_t t = {
4353                         .min = 64000,
4354                         .max = 96000,
4355                         .integer = 1,
4356                 };
4357                 return snd_interval_refine(r, &t);
4358         }
4359         return 0;
4360 }
4361
4362 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4363 {
4364         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4365         unsigned long flags;
4366         snd_pcm_runtime_t *runtime = substream->runtime;
4367
4368         if (hdsp_check_for_iobox (hdsp)) {
4369                 return -EIO;
4370         }
4371
4372         if (hdsp_check_for_firmware(hdsp)) {
4373                 if (hdsp->state & HDSP_FirmwareCached) {
4374                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4375                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4376                         }
4377                 } else {
4378                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4379                 }
4380                 return -EIO;
4381         }
4382
4383         spin_lock_irqsave(&hdsp->lock, flags);
4384
4385         snd_pcm_set_sync(substream);
4386
4387         runtime->hw = snd_hdsp_playback_subinfo;
4388         runtime->dma_area = hdsp->playback_buffer;
4389         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4390
4391         if (hdsp->capture_substream == NULL) {
4392                 hdsp_stop_audio(hdsp);
4393                 hdsp_set_thru(hdsp, -1, 0);
4394         }
4395
4396         hdsp->playback_pid = current->pid;
4397         hdsp->playback_substream = substream;
4398
4399         spin_unlock_irqrestore(&hdsp->lock, flags);
4400
4401         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4402         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4403         if (hdsp->io_type == H9632) {
4404                 runtime->hw.channels_min = hdsp->qs_out_channels;
4405                 runtime->hw.channels_max = hdsp->ss_out_channels;
4406                 runtime->hw.rate_max = 192000;
4407                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4408                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4409         }
4410
4411         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4412                              snd_hdsp_hw_rule_out_channels, hdsp,
4413                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4414         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4415                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4416                              SNDRV_PCM_HW_PARAM_RATE, -1);
4417         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4418                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4419                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4420
4421         hdsp->creg_spdif_stream = hdsp->creg_spdif;
4422         hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4423         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4424                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4425         return 0;
4426 }
4427
4428 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4429 {
4430         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4431         unsigned long flags;
4432
4433         spin_lock_irqsave(&hdsp->lock, flags);
4434
4435         hdsp->playback_pid = -1;
4436         hdsp->playback_substream = NULL;
4437
4438         spin_unlock_irqrestore(&hdsp->lock, flags);
4439
4440         hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4441         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4442                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4443         return 0;
4444 }
4445
4446
4447 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4448 {
4449         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4450         unsigned long flags;
4451         snd_pcm_runtime_t *runtime = substream->runtime;
4452
4453         if (hdsp_check_for_iobox (hdsp)) {
4454                 return -EIO;
4455         }
4456
4457         if (hdsp_check_for_firmware(hdsp)) {
4458                 if (hdsp->state & HDSP_FirmwareCached) {
4459                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4460                                 snd_printk("Firmware loading from cache failed, please upload manually.\n");
4461                         }
4462                 } else {
4463                         snd_printk("No firmware loaded nor cached, please upload firmware.\n");
4464                 }
4465                 return -EIO;
4466         }
4467
4468         spin_lock_irqsave(&hdsp->lock, flags);
4469
4470         snd_pcm_set_sync(substream);
4471
4472         runtime->hw = snd_hdsp_capture_subinfo;
4473         runtime->dma_area = hdsp->capture_buffer;
4474         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4475
4476         if (hdsp->playback_substream == NULL) {
4477                 hdsp_stop_audio(hdsp);
4478                 hdsp_set_thru(hdsp, -1, 0);
4479         }
4480
4481         hdsp->capture_pid = current->pid;
4482         hdsp->capture_substream = substream;
4483
4484         spin_unlock_irqrestore(&hdsp->lock, flags);
4485
4486         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4487         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4488         if (hdsp->io_type == H9632) {
4489                 runtime->hw.channels_min = hdsp->qs_in_channels;
4490                 runtime->hw.channels_max = hdsp->ss_in_channels;
4491                 runtime->hw.rate_max = 192000;
4492                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4493                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4494         }
4495         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4496                              snd_hdsp_hw_rule_in_channels, hdsp,
4497                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4498         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4499                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4500                              SNDRV_PCM_HW_PARAM_RATE, -1);
4501         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4502                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4503                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4504         return 0;
4505 }
4506
4507 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4508 {
4509         hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
4510         unsigned long flags;
4511
4512         spin_lock_irqsave(&hdsp->lock, flags);
4513
4514         hdsp->capture_pid = -1;
4515         hdsp->capture_substream = NULL;
4516
4517         spin_unlock_irqrestore(&hdsp->lock, flags);
4518         return 0;
4519 }
4520
4521 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4522 {
4523         /* we have nothing to initialize but the call is required */
4524         return 0;
4525 }
4526
4527
4528 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4529 {
4530         hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4531
4532         switch (cmd) {
4533         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4534                 hdsp_peak_rms_t *peak_rms;
4535                 int i;
4536
4537                 if (hdsp->io_type == H9652) {
4538                         unsigned long rms_low, rms_high;
4539                         int doublespeed = 0;
4540                         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4541                                 doublespeed = 1;
4542                         peak_rms = (hdsp_peak_rms_t *)arg;
4543                         for (i = 0; i < 26; ++i) {
4544                                 if (!(doublespeed && (i & 4))) {
4545                                         if (copy_to_user_fromio((void *)peak_rms->input_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-i*4, 4) != 0)
4546                                                 return -EFAULT;
4547                                         if (copy_to_user_fromio((void *)peak_rms->playback_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4548                                                 return -EFAULT;
4549                                         if (copy_to_user_fromio((void *)peak_rms->output_peaks+i*4, hdsp->iobase+HDSP_9652_peakBase-2*(doublespeed ? 14 : 26)*4-i*4, 4) != 0)
4550                                                 return -EFAULT;
4551                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8) & 0xFFFFFF00;
4552                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+i*8+4) & 0xFFFFFF00;
4553                                         rms_high += (rms_low >> 24);
4554                                         rms_low <<= 8;
4555                                         if (copy_to_user((void *)peak_rms->input_rms+i*8, &rms_low, 4) != 0)
4556                                                 return -EFAULT;
4557                                         if (copy_to_user((void *)peak_rms->input_rms+i*8+4, &rms_high, 4) != 0)
4558                                                 return -EFAULT;
4559                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4560                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4561                                         rms_high += (rms_low >> 24);
4562                                         rms_low <<= 8;
4563                                         if (copy_to_user((void *)peak_rms->playback_rms+i*8, &rms_low, 4) != 0)
4564                                                 return -EFAULT;
4565                                         if (copy_to_user((void *)peak_rms->playback_rms+i*8+4, &rms_high, 4) != 0)
4566                                                 return -EFAULT;
4567                                         rms_low = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8) & 0xFFFFFF00;
4568                                         rms_high = *(u32 *)(hdsp->iobase+HDSP_9652_rmsBase+2*(doublespeed ? 14 : 26)*8+i*8+4) & 0xFFFFFF00;
4569                                         rms_high += (rms_low >> 24);
4570                                         rms_low <<= 8;
4571                                         if (copy_to_user((void *)peak_rms->output_rms+i*8, &rms_low, 4) != 0)
4572                                                 return -EFAULT;
4573                                         if (copy_to_user((void *)peak_rms->output_rms+i*8+4, &rms_high, 4) != 0)
4574                                                 return -EFAULT;
4575                                 }
4576                         }
4577                         return 0;
4578                 }
4579                 if (hdsp->io_type == H9632) {
4580                         int j;
4581                         hdsp_9632_meters_t *m;
4582                         int doublespeed = 0;
4583                         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4584                                 doublespeed = 1;
4585                         m = (hdsp_9632_meters_t *)(hdsp->iobase+HDSP_9632_metersBase);
4586                         peak_rms = (hdsp_peak_rms_t *)arg;
4587                         for (i = 0, j = 0; i < 16; ++i, ++j) {
4588                                 if (copy_to_user((void *)peak_rms->input_peaks+i*4, &(m->input_peak[j]), 4) != 0)
4589                                         return -EFAULT;
4590                                 if (copy_to_user((void *)peak_rms->playback_peaks+i*4, &(m->playback_peak[j]), 4) != 0)
4591                                         return -EFAULT;
4592                                 if (copy_to_user((void *)peak_rms->output_peaks+i*4, &(m->output_peak[j]), 4) != 0)
4593                                         return -EFAULT;
4594                                 if (copy_to_user((void *)peak_rms->input_rms+i*8, &(m->input_rms_low[j]), 4) != 0)
4595                                         return -EFAULT;
4596                                 if (copy_to_user((void *)peak_rms->playback_rms+i*8, &(m->playback_rms_low[j]), 4) != 0)
4597                                         return -EFAULT;
4598                                 if (copy_to_user((void *)peak_rms->output_rms+i*8, &(m->output_rms_low[j]), 4) != 0)
4599                                         return -EFAULT;
4600                                 if (copy_to_user((void *)peak_rms->input_rms+i*8+4, &(m->input_rms_high[j]), 4) != 0)
4601                                         return -EFAULT;
4602                                 if (copy_to_user((void *)peak_rms->playback_rms+i*8+4, &(m->playback_rms_high[j]), 4) != 0)
4603                                         return -EFAULT;
4604                                 if (copy_to_user((void *)peak_rms->output_rms+i*8+4, &(m->output_rms_high[j]), 4) != 0)
4605                                         return -EFAULT;
4606                                 if (doublespeed && i == 3) i += 4;
4607                         }
4608                         return 0;
4609                 }
4610                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4611                         snd_printk("firmware needs to be uploaded to the card.\n");
4612                         return -EINVAL;
4613                 }
4614                 peak_rms = (hdsp_peak_rms_t *)arg;
4615                 for (i = 0; i < 26; ++i) {
4616                     if (copy_to_user((void *)peak_rms->playback_peaks+i*4, (void *)hdsp->iobase+HDSP_playbackPeakLevel+i*4, 4) != 0)
4617                             return -EFAULT;
4618                     if (copy_to_user((void *)peak_rms->input_peaks+i*4, (void *)hdsp->iobase+HDSP_inputPeakLevel+i*4, 4) != 0)
4619                             return -EFAULT;
4620                 }
4621                 for (i = 0; i < 26; ++i) {
4622                         if (copy_to_user((void *)peak_rms->playback_rms+i*8+4, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8, 4) != 0)
4623                                 return -EFAULT;
4624                         if (copy_to_user((void *)peak_rms->playback_rms+i*8, (void *)hdsp->iobase+HDSP_playbackRmsLevel+i*8+4, 4) != 0)
4625                                 return -EFAULT;
4626                         if (copy_to_user((void *)peak_rms->input_rms+i*8+4, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8, 4) != 0)
4627                                 return -EFAULT;
4628                         if (copy_to_user((void *)peak_rms->input_rms+i*8, (void *)hdsp->iobase+HDSP_inputRmsLevel+i*8+4, 4) != 0)
4629                                 return -EFAULT;
4630                 }
4631                 for (i = 0; i < 28; ++i) {
4632                     if (copy_to_user((void *)peak_rms->output_peaks+i*4, (void *)hdsp->iobase+HDSP_outputPeakLevel+i*4, 4) != 0)
4633                             return -EFAULT;
4634                 }
4635                 break;
4636         }
4637         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4638                 hdsp_config_info_t info;
4639                 unsigned long flags;
4640                 int i;
4641
4642                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4643                         snd_printk("Firmware needs to be uploaded to the card.\n");
4644                         return -EINVAL;
4645                 }
4646                 spin_lock_irqsave(&hdsp->lock, flags);
4647                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4648                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4649                 if (hdsp->io_type != H9632) {
4650                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4651                 }
4652                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4653                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4654                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4655                 }
4656                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4657                 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4658                 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4659                 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4660                 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4661                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4662                 info.system_sample_rate = hdsp->system_sample_rate;
4663                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4664                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4665                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4666                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4667                 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4668                 info.passthru = (unsigned char)hdsp->passthru;
4669                 if (hdsp->io_type == H9632) {
4670                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4671                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4672                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4673                         info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4674
4675                 }
4676                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4677                         info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4678                 }
4679                 spin_unlock_irqrestore(&hdsp->lock, flags);
4680                 if (copy_to_user((void *)arg, &info, sizeof(info)))
4681                         return -EFAULT;
4682                 break;
4683         }
4684         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4685                 hdsp_9632_aeb_t h9632_aeb;
4686
4687                 if (hdsp->io_type != H9632) return -EINVAL;
4688                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4689                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4690                 if (copy_to_user((void *)arg, &h9632_aeb, sizeof(h9632_aeb)))
4691                         return -EFAULT;
4692                 break;
4693         }
4694         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4695                 hdsp_version_t hdsp_version;
4696                 int err;
4697
4698                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4699                 if (hdsp->io_type == Undefined) {
4700                         if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4701                                 return err;
4702                         }
4703                 }
4704                 hdsp_version.io_type = hdsp->io_type;
4705                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4706                 if ((err = copy_to_user((void *)arg, &hdsp_version, sizeof(hdsp_version)))) {
4707                         return -EFAULT;
4708                 }
4709                 break;
4710         }
4711         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4712                 hdsp_firmware_t *firmware;
4713                 unsigned long *firmware_data;
4714                 int err;
4715
4716                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4717                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4718                 if (hdsp->io_type == Undefined) return -EINVAL;
4719
4720                 snd_printk("initializing firmware upload\n");
4721                 firmware = (hdsp_firmware_t *)arg;
4722
4723                 if (get_user(firmware_data, &firmware->firmware_data)) {
4724                         return -EFAULT;
4725                 }
4726
4727                 if (hdsp_check_for_iobox (hdsp)) {
4728                         return -EIO;
4729                 }
4730
4731                 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(unsigned long)*24413) != 0) {
4732                         return -EFAULT;
4733                 }
4734
4735                 hdsp->state |= HDSP_FirmwareCached;
4736
4737                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4738                         return err;
4739                 }
4740
4741                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4742                         snd_hdsp_initialize_channels(hdsp);
4743
4744                         snd_hdsp_initialize_midi_flush(hdsp);
4745
4746                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4747                                 snd_printk("error creating alsa devices\n");
4748                             return err;
4749                         }
4750                 }
4751                 break;
4752         }
4753         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4754                 hdsp_mixer_t *mixer;
4755
4756                 mixer = (hdsp_mixer_t *)arg;
4757                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4758                         return -EFAULT;
4759                 break;
4760         }
4761         default:
4762                 return -EINVAL;
4763         }
4764         return 0;
4765 }
4766
4767 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4768         .open =         snd_hdsp_playback_open,
4769         .close =        snd_hdsp_playback_release,
4770         .ioctl =        snd_hdsp_ioctl,
4771         .hw_params =    snd_hdsp_hw_params,
4772         .prepare =      snd_hdsp_prepare,
4773         .trigger =      snd_hdsp_trigger,
4774         .pointer =      snd_hdsp_hw_pointer,
4775         .copy =         snd_hdsp_playback_copy,
4776         .silence =      snd_hdsp_hw_silence,
4777 };
4778
4779 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4780         .open =         snd_hdsp_capture_open,
4781         .close =        snd_hdsp_capture_release,
4782         .ioctl =        snd_hdsp_ioctl,
4783         .hw_params =    snd_hdsp_hw_params,
4784         .prepare =      snd_hdsp_prepare,
4785         .trigger =      snd_hdsp_trigger,
4786         .pointer =      snd_hdsp_hw_pointer,
4787         .copy =         snd_hdsp_capture_copy,
4788 };
4789
4790 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4791                                            hdsp_t *hdsp)
4792 {
4793         snd_hwdep_t *hw;
4794         int err;
4795
4796         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4797                 return err;
4798
4799         hdsp->hwdep = hw;
4800         hw->private_data = hdsp;
4801         strcpy(hw->name, "HDSP hwdep interface");
4802
4803         hw->ops.open = snd_hdsp_hwdep_dummy_op;
4804         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4805         hw->ops.release = snd_hdsp_hwdep_dummy_op;
4806
4807         return 0;
4808 }
4809
4810 static int __devinit snd_hdsp_create_pcm(snd_card_t *card,
4811                                          hdsp_t *hdsp)
4812 {
4813         snd_pcm_t *pcm;
4814         int err;
4815
4816         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4817                 return err;
4818
4819         hdsp->pcm = pcm;
4820         pcm->private_data = hdsp;
4821         strcpy(pcm->name, hdsp->card_name);
4822
4823         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4824         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4825
4826         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4827
4828         return 0;
4829 }
4830
4831 static inline void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4832 {
4833         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4834         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4835 }
4836
4837 static inline void snd_hdsp_9652_disable_mixer (hdsp_t *hdsp)
4838 {
4839         hdsp->control2_register &= ~HDSP_9652_ENABLE_MIXER;
4840         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4841 }
4842
4843 static inline int snd_hdsp_enable_io (hdsp_t *hdsp)
4844 {
4845         int i;
4846
4847         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4848                 return -EIO;
4849         }
4850
4851         for (i = 0; i < hdsp->max_channels; ++i) {
4852                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4853                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4854         }
4855
4856         return 0;
4857 }
4858
4859 static inline void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4860 {
4861         int status, aebi_channels, aebo_channels;
4862
4863         switch (hdsp->io_type) {
4864         case Digiface:
4865                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4866                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4867                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4868                 break;
4869
4870         case H9652:
4871                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4872                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4873                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4874                 break;
4875
4876         case H9632:
4877                 status = hdsp_read(hdsp, HDSP_statusRegister);
4878                 /* HDSP_AEBx bits are low when AEB are connected */
4879                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4880                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4881                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4882                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4883                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4884                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4885                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4886                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4887                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4888                 break;
4889
4890         case Multiface:
4891                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4892                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4893                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4894                 break;
4895
4896         default:
4897                 /* should never get here */
4898                 break;
4899         }
4900 }
4901
4902 static inline void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4903 {
4904         snd_hdsp_flush_midi_input (hdsp, 0);
4905         snd_hdsp_flush_midi_input (hdsp, 1);
4906 }
4907
4908 static int __devinit snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4909 {
4910         int err;
4911
4912         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4913                 snd_printk("Error creating pcm interface\n");
4914                 return err;
4915         }
4916
4917
4918         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4919                 snd_printk("Error creating first midi interface\n");
4920                 return err;
4921         }
4922
4923
4924         if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4925                 snd_printk("Error creating second midi interface\n");
4926                 return err;
4927         }
4928
4929         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4930                 snd_printk("Error creating ctl interface\n");
4931                 return err;
4932         }
4933
4934         snd_hdsp_proc_init(hdsp);
4935
4936         hdsp->system_sample_rate = -1;
4937         hdsp->playback_pid = -1;
4938         hdsp->capture_pid = -1;
4939         hdsp->capture_substream = NULL;
4940         hdsp->playback_substream = NULL;
4941
4942         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4943                 snd_printk("Error setting default values\n");
4944                 return err;
4945         }
4946
4947         if (!(hdsp->state & HDSP_InitializationComplete)) {
4948                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4949                         hdsp->port, hdsp->irq);
4950
4951                 if ((err = snd_card_register(card)) < 0) {
4952                         snd_printk("error registering card\n");
4953                         return err;
4954                 }
4955                 hdsp->state |= HDSP_InitializationComplete;
4956         }
4957
4958         return 0;
4959 }
4960
4961 static int __devinit snd_hdsp_create(snd_card_t *card,
4962                                      hdsp_t *hdsp,
4963                                      int precise_ptr)
4964 {
4965         struct pci_dev *pci = hdsp->pci;
4966         int err;
4967         int is_9652 = 0;
4968         int is_9632 = 0;
4969
4970         hdsp->irq = -1;
4971         hdsp->state = 0;
4972         hdsp->midi[0].rmidi = 0;
4973         hdsp->midi[1].rmidi = 0;
4974         hdsp->midi[0].input = 0;
4975         hdsp->midi[1].input = 0;
4976         hdsp->midi[0].output = 0;
4977         hdsp->midi[1].output = 0;
4978         spin_lock_init(&hdsp->midi[0].lock);
4979         spin_lock_init(&hdsp->midi[1].lock);
4980         hdsp->iobase = 0;
4981         hdsp->res_port = 0;
4982         hdsp->control_register = 0;
4983         hdsp->control2_register = 0;
4984         hdsp->io_type = Undefined;
4985         hdsp->max_channels = 26;
4986
4987         hdsp->card = card;
4988
4989         spin_lock_init(&hdsp->lock);
4990
4991         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4992
4993         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4994
4995         /* From Martin Bjoernsen :
4996             "It is important that the card's latency timer register in
4997             the PCI configuration space is set to a value much larger
4998             than 0 by the computer's BIOS or the driver.
4999             The windows driver always sets this 8 bit register [...]
5000             to its maximum 255 to avoid problems with some computers."
5001         */
5002         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5003
5004         strcpy(card->driver, "H-DSP");
5005         strcpy(card->mixername, "Xilinx FPGA");
5006
5007         switch (hdsp->firmware_rev & 0xff) {
5008         case 0xa:
5009         case 0xb:
5010         case 0x32:
5011                 hdsp->card_name = "RME Hammerfall DSP";
5012                 break;
5013
5014         case 0x64:
5015         case 0x65:
5016         case 0x68:
5017                 hdsp->card_name = "RME HDSP 9652";
5018                 is_9652 = 1;
5019                 break;
5020         case 0x96:
5021                 hdsp->card_name = "RME HDSP 9632";
5022                 hdsp->max_channels = 16;
5023                 is_9632 = 1;
5024                 break;
5025         default:
5026                 return -ENODEV;
5027         }
5028
5029         if ((err = pci_enable_device(pci)) < 0) {
5030                 return err;
5031         }
5032
5033         pci_set_master(hdsp->pci);
5034
5035         hdsp->port = pci_resource_start(pci, 0);
5036
5037         if ((hdsp->res_port = request_mem_region(hdsp->port, HDSP_IO_EXTENT, "hdsp")) == NULL) {
5038                 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5039                 return -EBUSY;
5040         }
5041
5042         if ((hdsp->iobase = (unsigned long) ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == 0) {
5043                 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5044                 return -EBUSY;
5045         }
5046
5047         if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5048                 snd_printk("unable to use IRQ %d\n", pci->irq);
5049                 return -EBUSY;
5050         }
5051
5052         hdsp->irq = pci->irq;
5053         hdsp->precise_ptr = precise_ptr;
5054
5055         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5056                 return err;
5057         }
5058
5059         if (!is_9652 && !is_9632 && hdsp_check_for_iobox (hdsp)) {
5060                 /* no iobox connected, we defer initialization */
5061                 snd_printk("card initialization pending : waiting for firmware\n");
5062                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5063                         return err;
5064                 }
5065                 return 0;
5066         }
5067
5068         if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5069                 return err;
5070         }
5071
5072         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5073                 snd_printk("card initialization pending : waiting for firmware\n");
5074                 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5075                         return err;
5076                 }
5077                 return 0;
5078         }
5079
5080         snd_printk("Firmware already loaded, initializing card.\n");
5081
5082         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5083                 hdsp->io_type = Multiface;
5084         } else {
5085                 hdsp->io_type = Digiface;
5086         }
5087
5088         if (is_9652) {
5089                 hdsp->io_type = H9652;
5090         }
5091
5092         if (is_9632) {
5093                 hdsp->io_type = H9632;
5094         }
5095
5096         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5097                 return err;
5098         }
5099
5100         snd_hdsp_initialize_channels(hdsp);
5101         snd_hdsp_initialize_midi_flush(hdsp);
5102
5103         hdsp->state |= HDSP_FirmwareLoaded;
5104
5105         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5106                 return err;
5107         }
5108
5109         return 0;
5110 }
5111
5112 static int snd_hdsp_free(hdsp_t *hdsp)
5113 {
5114         if (hdsp->res_port) {
5115                 /* stop the audio, and cancel all interrupts */
5116                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5117                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5118         }
5119
5120         if (hdsp->irq >= 0)
5121                 free_irq(hdsp->irq, (void *)hdsp);
5122
5123         snd_hdsp_free_buffers(hdsp);
5124
5125         if (hdsp->iobase)
5126                 iounmap((void *) hdsp->iobase);
5127
5128         if (hdsp->res_port) {
5129                 release_resource(hdsp->res_port);
5130                 kfree_nocheck(hdsp->res_port);
5131         }
5132
5133         return 0;
5134 }
5135
5136 static void snd_hdsp_card_free(snd_card_t *card)
5137 {
5138         hdsp_t *hdsp = (hdsp_t *) card->private_data;
5139
5140         if (hdsp)
5141                 snd_hdsp_free(hdsp);
5142 }
5143
5144 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5145                                     const struct pci_device_id *pci_id)
5146 {
5147         static int dev;
5148         hdsp_t *hdsp;
5149         snd_card_t *card;
5150         int err;
5151
5152         if (dev >= SNDRV_CARDS)
5153                 return -ENODEV;
5154         if (!enable[dev]) {
5155                 dev++;
5156                 return -ENOENT;
5157         }
5158
5159         if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5160                 return -ENOMEM;
5161
5162         hdsp = (hdsp_t *) card->private_data;
5163         card->private_free = snd_hdsp_card_free;
5164         hdsp->dev = dev;
5165         hdsp->pci = pci;
5166         snd_card_set_dev(card, &pci->dev);
5167
5168         if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
5169                 snd_card_free(card);
5170                 return err;
5171         }
5172
5173         strcpy(card->shortname, "Hammerfall DSP");
5174         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5175                 hdsp->port, hdsp->irq);
5176
5177         if ((err = snd_card_register(card)) < 0) {
5178                 snd_card_free(card);
5179                 return err;
5180         }
5181         pci_set_drvdata(pci, card);
5182         dev++;
5183         return 0;
5184 }
5185
5186 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5187 {
5188         snd_card_free(pci_get_drvdata(pci));
5189         pci_set_drvdata(pci, NULL);
5190 }
5191
5192 static struct pci_driver driver = {
5193         .name =     "RME Hammerfall DSP",
5194         .id_table = snd_hdsp_ids,
5195         .probe =    snd_hdsp_probe,
5196         .remove = __devexit_p(snd_hdsp_remove),
5197 };
5198
5199 static int __init alsa_card_hdsp_init(void)
5200 {
5201         if (pci_module_init(&driver) < 0) {
5202 #ifdef MODULE
5203                 printk(KERN_ERR "RME Hammerfall-DSP: no cards found\n");
5204 #endif
5205                 return -ENODEV;
5206         }
5207
5208         return 0;
5209 }
5210
5211 static void __exit alsa_card_hdsp_exit(void)
5212 {
5213         pci_unregister_driver(&driver);
5214 }
5215
5216 module_init(alsa_card_hdsp_init)
5217 module_exit(alsa_card_hdsp_exit)
5218
5219 #ifndef MODULE
5220
5221 /* format is: snd-hdsp=enable,index,id */
5222
5223 static int __init alsa_card_hdsp_setup(char *str)
5224 {
5225         static unsigned __initdata nr_dev = 0;
5226
5227         if (nr_dev >= SNDRV_CARDS)
5228                 return 0;
5229         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
5230                get_option(&str,&index[nr_dev]) == 2 &&
5231                get_id(&str,&id[nr_dev]) == 2);
5232         nr_dev++;
5233         return 1;
5234 }
5235
5236 __setup("snd-hdsp=", alsa_card_hdsp_setup);
5237
5238 #endif /* ifndef MODULE */