sound/sparc/amd7930.c

   1 /*
   2  * Driver for AMD7930 sound chips found on Sparcs.
   3  * Copyright (C) 2002 David S. Miller <davem@redhat.com>
   4  *
   5  * Based entirely upon drivers/sbus/audio/amd7930.c which is:
   6  * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
   7  *
   8  * --- Notes from Thomas's original driver ---
   9  * This is the lowlevel driver for the AMD7930 audio chip found on all
  10  * sun4c machines and some sun4m machines.
  11  *
  12  * The amd7930 is actually an ISDN chip which has a very simple
  13  * integrated audio encoder/decoder. When Sun decided on what chip to
  14  * use for audio, they had the brilliant idea of using the amd7930 and
  15  * only connecting the audio encoder/decoder pins.
  16  *
  17  * Thanks to the AMD engineer who was able to get us the AMD79C30
  18  * databook which has all the programming information and gain tables.
  19  *
  20  * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
  21  * SparcStation 1+.  The chip provides microphone and speaker interfaces
  22  * which provide mono-channel audio at 8K samples per second via either
  23  * 8-bit A-law or 8-bit mu-law encoding.  Also, the chip features an
  24  * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
  25  * which performs basic D channel LAPD processing and provides raw
  26  * B channel data.  The digital audio channel, the two ISDN B channels,
  27  * and two 64 Kbps channels to the microprocessor are all interconnected
  28  * via a multiplexer.
  29  * --- End of notes from Thoamas's original driver ---
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/slab.h>
  35 #include <linux/init.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/moduleparam.h>
  38
  39 #include <sound/driver.h>
  40 #include <sound/core.h>
  41 #include <sound/pcm.h>
  42 #include <sound/info.h>
  43 #include <sound/control.h>
  44 #include <sound/initval.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/sbus.h>
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  51 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  52 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  53 static int boot_devs;
  54
  55 module_param_array(index, int, boot_devs, 0444);
  56 MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
  57 module_param_array(id, charp, boot_devs, 0444);
  58 MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
  59 module_param_array(enable, bool, boot_devs, 0444);
  60 MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
  61 MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
  62 MODULE_DESCRIPTION("Sun AMD7930");
  63 MODULE_LICENSE("GPL");
  64 MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
  65
  66 /* Device register layout.  */
  67
  68 /* Register interface presented to the CPU by the amd7930. */
  69 #define AMD7930_CR      0x00UL          /* Command Register (W) */
  70 #define AMD7930_IR      AMD7930_CR      /* Interrupt Register (R) */
  71 #define AMD7930_DR      0x01UL          /* Data Register (R/W) */
  72 #define AMD7930_DSR1    0x02UL          /* D-channel Status Register 1 (R) */
  73 #define AMD7930_DER     0x03UL          /* D-channel Error Register (R) */
  74 #define AMD7930_DCTB    0x04UL          /* D-channel Transmit Buffer (W) */
  75 #define AMD7930_DCRB    AMD7930_DCTB    /* D-channel Receive Buffer (R) */
  76 #define AMD7930_BBTB    0x05UL          /* Bb-channel Transmit Buffer (W) */
  77 #define AMD7930_BBRB    AMD7930_BBTB    /* Bb-channel Receive Buffer (R) */
  78 #define AMD7930_BCTB    0x06UL          /* Bc-channel Transmit Buffer (W) */
  79 #define AMD7930_BCRB    AMD7930_BCTB    /* Bc-channel Receive Buffer (R) */
  80 #define AMD7930_DSR2    0x07UL          /* D-channel Status Register 2 (R) */
  81
  82 /* Indirect registers in the Main Audio Processor. */
  83 struct amd7930_map {
  84         __u16   x[8];
  85         __u16   r[8];
  86         __u16   gx;
  87         __u16   gr;
  88         __u16   ger;
  89         __u16   stgr;
  90         __u16   ftgr;
  91         __u16   atgr;
  92         __u8    mmr1;
  93         __u8    mmr2;
  94 };
  95
  96 /* After an amd7930 interrupt, reading the Interrupt Register (ir)
  97  * clears the interrupt and returns a bitmask indicating which
  98  * interrupt source(s) require service.
  99  */
 100
 101 #define AMR_IR_DTTHRSH                  0x01 /* D-channel xmit threshold */
 102 #define AMR_IR_DRTHRSH                  0x02 /* D-channel recv threshold */
 103 #define AMR_IR_DSRI                     0x04 /* D-channel packet status */
 104 #define AMR_IR_DERI                     0x08 /* D-channel error */
 105 #define AMR_IR_BBUF                     0x10 /* B-channel data xfer */
 106 #define AMR_IR_LSRI                     0x20 /* LIU status */
 107 #define AMR_IR_DSR2I                    0x40 /* D-channel buffer status */
 108 #define AMR_IR_MLTFRMI                  0x80 /* multiframe or PP */
 109
 110 /* The amd7930 has "indirect registers" which are accessed by writing
 111  * the register number into the Command Register and then reading or
 112  * writing values from the Data Register as appropriate. We define the
 113  * AMR_* macros to be the indirect register numbers and AM_* macros to
 114  * be bits in whatever register is referred to.
 115  */
 116
 117 /* Initialization */
 118 #define AMR_INIT                        0x21
 119 #define         AM_INIT_ACTIVE                  0x01
 120 #define         AM_INIT_DATAONLY                0x02
 121 #define         AM_INIT_POWERDOWN               0x03
 122 #define         AM_INIT_DISABLE_INTS            0x04
 123 #define AMR_INIT2                       0x20
 124 #define         AM_INIT2_ENABLE_POWERDOWN       0x20
 125 #define         AM_INIT2_ENABLE_MULTIFRAME      0x10
 126
 127 /* Line Interface Unit */
 128 #define AMR_LIU_LSR                     0xA1
 129 #define         AM_LIU_LSR_STATE                0x07
 130 #define         AM_LIU_LSR_F3                   0x08
 131 #define         AM_LIU_LSR_F7                   0x10
 132 #define         AM_LIU_LSR_F8                   0x20
 133 #define         AM_LIU_LSR_HSW                  0x40
 134 #define         AM_LIU_LSR_HSW_CHG              0x80
 135 #define AMR_LIU_LPR                     0xA2
 136 #define AMR_LIU_LMR1                    0xA3
 137 #define         AM_LIU_LMR1_B1_ENABL            0x01
 138 #define         AM_LIU_LMR1_B2_ENABL            0x02
 139 #define         AM_LIU_LMR1_F_DISABL            0x04
 140 #define         AM_LIU_LMR1_FA_DISABL           0x08
 141 #define         AM_LIU_LMR1_REQ_ACTIV           0x10
 142 #define         AM_LIU_LMR1_F8_F3               0x20
 143 #define         AM_LIU_LMR1_LIU_ENABL           0x40
 144 #define AMR_LIU_LMR2                    0xA4
 145 #define         AM_LIU_LMR2_DECHO               0x01
 146 #define         AM_LIU_LMR2_DLOOP               0x02
 147 #define         AM_LIU_LMR2_DBACKOFF            0x04
 148 #define         AM_LIU_LMR2_EN_F3_INT           0x08
 149 #define         AM_LIU_LMR2_EN_F8_INT           0x10
 150 #define         AM_LIU_LMR2_EN_HSW_INT          0x20
 151 #define         AM_LIU_LMR2_EN_F7_INT           0x40
 152 #define AMR_LIU_2_4                     0xA5
 153 #define AMR_LIU_MF                      0xA6
 154 #define AMR_LIU_MFSB                    0xA7
 155 #define AMR_LIU_MFQB                    0xA8
 156
 157 /* Multiplexor */
 158 #define AMR_MUX_MCR1                    0x41
 159 #define AMR_MUX_MCR2                    0x42
 160 #define AMR_MUX_MCR3                    0x43
 161 #define         AM_MUX_CHANNEL_B1               0x01
 162 #define         AM_MUX_CHANNEL_B2               0x02
 163 #define         AM_MUX_CHANNEL_Ba               0x03
 164 #define         AM_MUX_CHANNEL_Bb               0x04
 165 #define         AM_MUX_CHANNEL_Bc               0x05
 166 #define         AM_MUX_CHANNEL_Bd               0x06
 167 #define         AM_MUX_CHANNEL_Be               0x07
 168 #define         AM_MUX_CHANNEL_Bf               0x08
 169 #define AMR_MUX_MCR4                    0x44
 170 #define         AM_MUX_MCR4_ENABLE_INTS         0x08
 171 #define         AM_MUX_MCR4_REVERSE_Bb          0x10
 172 #define         AM_MUX_MCR4_REVERSE_Bc          0x20
 173 #define AMR_MUX_1_4                     0x45
 174
 175 /* Main Audio Processor */
 176 #define AMR_MAP_X                       0x61
 177 #define AMR_MAP_R                       0x62
 178 #define AMR_MAP_GX                      0x63
 179 #define AMR_MAP_GR                      0x64
 180 #define AMR_MAP_GER                     0x65
 181 #define AMR_MAP_STGR                    0x66
 182 #define AMR_MAP_FTGR_1_2                0x67
 183 #define AMR_MAP_ATGR_1_2                0x68
 184 #define AMR_MAP_MMR1                    0x69
 185 #define         AM_MAP_MMR1_ALAW                0x01
 186 #define         AM_MAP_MMR1_GX                  0x02
 187 #define         AM_MAP_MMR1_GR                  0x04
 188 #define         AM_MAP_MMR1_GER                 0x08
 189 #define         AM_MAP_MMR1_X                   0x10
 190 #define         AM_MAP_MMR1_R                   0x20
 191 #define         AM_MAP_MMR1_STG                 0x40
 192 #define         AM_MAP_MMR1_LOOPBACK            0x80
 193 #define AMR_MAP_MMR2                    0x6A
 194 #define         AM_MAP_MMR2_AINB                0x01
 195 #define         AM_MAP_MMR2_LS                  0x02
 196 #define         AM_MAP_MMR2_ENABLE_DTMF         0x04
 197 #define         AM_MAP_MMR2_ENABLE_TONEGEN      0x08
 198 #define         AM_MAP_MMR2_ENABLE_TONERING     0x10
 199 #define         AM_MAP_MMR2_DISABLE_HIGHPASS    0x20
 200 #define         AM_MAP_MMR2_DISABLE_AUTOZERO    0x40
 201 #define AMR_MAP_1_10                    0x6B
 202 #define AMR_MAP_MMR3                    0x6C
 203 #define AMR_MAP_STRA                    0x6D
 204 #define AMR_MAP_STRF                    0x6E
 205 #define AMR_MAP_PEAKX                   0x70
 206 #define AMR_MAP_PEAKR                   0x71
 207 #define AMR_MAP_15_16                   0x72
 208
 209 /* Data Link Controller */
 210 #define AMR_DLC_FRAR_1_2_3              0x81
 211 #define AMR_DLC_SRAR_1_2_3              0x82
 212 #define AMR_DLC_TAR                     0x83
 213 #define AMR_DLC_DRLR                    0x84
 214 #define AMR_DLC_DTCR                    0x85
 215 #define AMR_DLC_DMR1                    0x86
 216 #define         AMR_DLC_DMR1_DTTHRSH_INT        0x01
 217 #define         AMR_DLC_DMR1_DRTHRSH_INT        0x02
 218 #define         AMR_DLC_DMR1_TAR_ENABL          0x04
 219 #define         AMR_DLC_DMR1_EORP_INT           0x08
 220 #define         AMR_DLC_DMR1_EN_ADDR1           0x10
 221 #define         AMR_DLC_DMR1_EN_ADDR2           0x20
 222 #define         AMR_DLC_DMR1_EN_ADDR3           0x40
 223 #define         AMR_DLC_DMR1_EN_ADDR4           0x80
 224 #define         AMR_DLC_DMR1_EN_ADDRS           0xf0
 225 #define AMR_DLC_DMR2                    0x87
 226 #define         AMR_DLC_DMR2_RABRT_INT          0x01
 227 #define         AMR_DLC_DMR2_RESID_INT          0x02
 228 #define         AMR_DLC_DMR2_COLL_INT           0x04
 229 #define         AMR_DLC_DMR2_FCS_INT            0x08
 230 #define         AMR_DLC_DMR2_OVFL_INT           0x10
 231 #define         AMR_DLC_DMR2_UNFL_INT           0x20
 232 #define         AMR_DLC_DMR2_OVRN_INT           0x40
 233 #define         AMR_DLC_DMR2_UNRN_INT           0x80
 234 #define AMR_DLC_1_7                     0x88
 235 #define AMR_DLC_DRCR                    0x89
 236 #define AMR_DLC_RNGR1                   0x8A
 237 #define AMR_DLC_RNGR2                   0x8B
 238 #define AMR_DLC_FRAR4                   0x8C
 239 #define AMR_DLC_SRAR4                   0x8D
 240 #define AMR_DLC_DMR3                    0x8E
 241 #define         AMR_DLC_DMR3_VA_INT             0x01
 242 #define         AMR_DLC_DMR3_EOTP_INT           0x02
 243 #define         AMR_DLC_DMR3_LBRP_INT           0x04
 244 #define         AMR_DLC_DMR3_RBA_INT            0x08
 245 #define         AMR_DLC_DMR3_LBT_INT            0x10
 246 #define         AMR_DLC_DMR3_TBE_INT            0x20
 247 #define         AMR_DLC_DMR3_RPLOST_INT         0x40
 248 #define         AMR_DLC_DMR3_KEEP_FCS           0x80
 249 #define AMR_DLC_DMR4                    0x8F
 250 #define         AMR_DLC_DMR4_RCV_1              0x00
 251 #define         AMR_DLC_DMR4_RCV_2              0x01
 252 #define         AMR_DLC_DMR4_RCV_4              0x02
 253 #define         AMR_DLC_DMR4_RCV_8              0x03
 254 #define         AMR_DLC_DMR4_RCV_16             0x01
 255 #define         AMR_DLC_DMR4_RCV_24             0x02
 256 #define         AMR_DLC_DMR4_RCV_30             0x03
 257 #define         AMR_DLC_DMR4_XMT_1              0x00
 258 #define         AMR_DLC_DMR4_XMT_2              0x04
 259 #define         AMR_DLC_DMR4_XMT_4              0x08
 260 #define         AMR_DLC_DMR4_XMT_8              0x0c
 261 #define         AMR_DLC_DMR4_XMT_10             0x08
 262 #define         AMR_DLC_DMR4_XMT_14             0x0c
 263 #define         AMR_DLC_DMR4_IDLE_MARK          0x00
 264 #define         AMR_DLC_DMR4_IDLE_FLAG          0x10
 265 #define         AMR_DLC_DMR4_ADDR_BOTH          0x00
 266 #define         AMR_DLC_DMR4_ADDR_1ST           0x20
 267 #define         AMR_DLC_DMR4_ADDR_2ND           0xa0
 268 #define         AMR_DLC_DMR4_CR_ENABLE          0x40
 269 #define AMR_DLC_12_15                   0x90
 270 #define AMR_DLC_ASR                     0x91
 271 #define AMR_DLC_EFCR                    0x92
 272 #define         AMR_DLC_EFCR_EXTEND_FIFO        0x01
 273 #define         AMR_DLC_EFCR_SEC_PKT_INT        0x02
 274
 275 #define AMR_DSR1_VADDR                  0x01
 276 #define AMR_DSR1_EORP                   0x02
 277 #define AMR_DSR1_PKT_IP                 0x04
 278 #define AMR_DSR1_DECHO_ON               0x08
 279 #define AMR_DSR1_DLOOP_ON               0x10
 280 #define AMR_DSR1_DBACK_OFF              0x20
 281 #define AMR_DSR1_EOTP                   0x40
 282 #define AMR_DSR1_CXMT_ABRT              0x80
 283
 284 #define AMR_DSR2_LBRP                   0x01
 285 #define AMR_DSR2_RBA                    0x02
 286 #define AMR_DSR2_RPLOST                 0x04
 287 #define AMR_DSR2_LAST_BYTE              0x08
 288 #define AMR_DSR2_TBE                    0x10
 289 #define AMR_DSR2_MARK_IDLE              0x20
 290 #define AMR_DSR2_FLAG_IDLE              0x40
 291 #define AMR_DSR2_SECOND_PKT             0x80
 292
 293 #define AMR_DER_RABRT                   0x01
 294 #define AMR_DER_RFRAME                  0x02
 295 #define AMR_DER_COLLISION               0x04
 296 #define AMR_DER_FCS                     0x08
 297 #define AMR_DER_OVFL                    0x10
 298 #define AMR_DER_UNFL                    0x20
 299 #define AMR_DER_OVRN                    0x40
 300 #define AMR_DER_UNRN                    0x80
 301
 302 /* Peripheral Port */
 303 #define AMR_PP_PPCR1                    0xC0
 304 #define AMR_PP_PPSR                     0xC1
 305 #define AMR_PP_PPIER                    0xC2
 306 #define AMR_PP_MTDR                     0xC3
 307 #define AMR_PP_MRDR                     0xC3
 308 #define AMR_PP_CITDR0                   0xC4
 309 #define AMR_PP_CIRDR0                   0xC4
 310 #define AMR_PP_CITDR1                   0xC5
 311 #define AMR_PP_CIRDR1                   0xC5
 312 #define AMR_PP_PPCR2                    0xC8
 313 #define AMR_PP_PPCR3                    0xC9
 314
 315 typedef struct snd_amd7930 {
 316         spinlock_t              lock;
 317         void __iomem            *regs;
 318         u32                     flags;
 319 #define AMD7930_FLAG_PLAYBACK   0x00000001
 320 #define AMD7930_FLAG_CAPTURE    0x00000002
 321
 322         struct amd7930_map      map;
 323
 324         snd_card_t              *card;
 325         snd_pcm_t               *pcm;
 326         snd_pcm_substream_t     *playback_substream;
 327         snd_pcm_substream_t     *capture_substream;
 328
 329         /* Playback/Capture buffer state. */
 330         unsigned char           *p_orig, *p_cur;
 331         int                     p_left;
 332         unsigned char           *c_orig, *c_cur;
 333         int                     c_left;
 334
 335         int                     rgain;
 336         int                     pgain;
 337         int                     mgain;
 338
 339         struct sbus_dev         *sdev;
 340         unsigned int            irq;
 341         unsigned int            regs_size;
 342         struct snd_amd7930      *next;
 343 } amd7930_t;
 344
 345 static amd7930_t *amd7930_list;
 346
 347 /* Idle the AMD7930 chip.  The amd->lock is not held.  */
 348 static __inline__ void amd7930_idle(amd7930_t *amd)
 349 {
 350         unsigned long flags;
 351
 352         spin_lock_irqsave(&amd->lock, flags);
 353         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
 354         sbus_writeb(0, amd->regs + AMD7930_DR);
 355         spin_unlock_irqrestore(&amd->lock, flags);
 356 }
 357
 358 /* Enable chip interrupts.  The amd->lock is not held.  */
 359 static __inline__ void amd7930_enable_ints(amd7930_t *amd)
 360 {
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&amd->lock, flags);
 364         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
 365         sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
 366         spin_unlock_irqrestore(&amd->lock, flags);
 367 }
 368
 369 /* Disable chip interrupts.  The amd->lock is not held.  */
 370 static __inline__ void amd7930_disable_ints(amd7930_t *amd)
 371 {
 372         unsigned long flags;
 373
 374         spin_lock_irqsave(&amd->lock, flags);
 375         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
 376         sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
 377         spin_unlock_irqrestore(&amd->lock, flags);
 378 }
 379
 380 /* Commit amd7930_map settings to the hardware.
 381  * The amd->lock is held and local interrupts are disabled.
 382  */
 383 static void __amd7930_write_map(amd7930_t *amd)
 384 {
 385         struct amd7930_map *map = &amd->map;
 386
 387         sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
 388         sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
 389         sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
 390
 391         sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
 392         sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
 393         sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
 394
 395         sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
 396         sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
 397         sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
 398
 399         sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
 400         sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
 401         sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
 402
 403         sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
 404         sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
 405
 406         sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
 407         sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
 408 }
 409
 410 /* gx, gr & stg gains.  this table must contain 256 elements with
 411  * the 0th being "infinity" (the magic value 9008).  The remaining
 412  * elements match sun's gain curve (but with higher resolution):
 413  * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
 414  */
 415 static __const__ __u16 gx_coeff[256] = {
 416         0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
 417         0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
 418         0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
 419         0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
 420         0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
 421         0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
 422         0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
 423         0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
 424         0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
 425         0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
 426         0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
 427         0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
 428         0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
 429         0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
 430         0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
 431         0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
 432         0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
 433         0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
 434         0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
 435         0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
 436         0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
 437         0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
 438         0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
 439         0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
 440         0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
 441         0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
 442         0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
 443         0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
 444         0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
 445         0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
 446         0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
 447         0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
 448 };
 449
 450 static __const__ __u16 ger_coeff[] = {
 451         0x431f, /* 5. dB */
 452         0x331f, /* 5.5 dB */
 453         0x40dd, /* 6. dB */
 454         0x11dd, /* 6.5 dB */
 455         0x440f, /* 7. dB */
 456         0x411f, /* 7.5 dB */
 457         0x311f, /* 8. dB */
 458         0x5520, /* 8.5 dB */
 459         0x10dd, /* 9. dB */
 460         0x4211, /* 9.5 dB */
 461         0x410f, /* 10. dB */
 462         0x111f, /* 10.5 dB */
 463         0x600b, /* 11. dB */
 464         0x00dd, /* 11.5 dB */
 465         0x4210, /* 12. dB */
 466         0x110f, /* 13. dB */
 467         0x7200, /* 14. dB */
 468         0x2110, /* 15. dB */
 469         0x2200, /* 15.9 dB */
 470         0x000b, /* 16.9 dB */
 471         0x000f  /* 18. dB */
 472 };
 473
 474 /* Update amd7930_map settings and program them into the hardware.
 475  * The amd->lock is held and local interrupts are disabled.
 476  */
 477 static void __amd7930_update_map(amd7930_t *amd)
 478 {
 479         struct amd7930_map *map = &amd->map;
 480         int level;
 481
 482         map->gx = gx_coeff[amd->rgain];
 483         map->stgr = gx_coeff[amd->mgain];
 484         level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
 485         if (level >= 256) {
 486                 map->ger = ger_coeff[level - 256];
 487                 map->gr = gx_coeff[255];
 488         } else {
 489                 map->ger = ger_coeff[0];
 490                 map->gr = gx_coeff[level];
 491         }
 492         __amd7930_write_map(amd);
 493 }
 494
 495 static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 496 {
 497         amd7930_t *amd = dev_id;
 498         unsigned int elapsed;
 499         u8 ir;
 500
 501         spin_lock(&amd->lock);
 502
 503         elapsed = 0;
 504
 505         ir = sbus_readb(amd->regs + AMD7930_IR);
 506         if (ir & AMR_IR_BBUF) {
 507                 u8 byte;
 508
 509                 if (amd->flags & AMD7930_FLAG_PLAYBACK) {
 510                         if (amd->p_left > 0) {
 511                                 byte = *(amd->p_cur++);
 512                                 amd->p_left--;
 513                                 sbus_writeb(byte, amd->regs + AMD7930_BBTB);
 514                                 if (amd->p_left == 0)
 515                                         elapsed |= AMD7930_FLAG_PLAYBACK;
 516                         } else
 517                                 sbus_writeb(0, amd->regs + AMD7930_BBTB);
 518                 } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
 519                         byte = sbus_readb(amd->regs + AMD7930_BBRB);
 520                         if (amd->c_left > 0) {
 521                                 *(amd->c_cur++) = byte;
 522                                 amd->c_left--;
 523                                 if (amd->c_left == 0)
 524                                         elapsed |= AMD7930_FLAG_CAPTURE;
 525                         }
 526                 }
 527         }
 528         spin_unlock(&amd->lock);
 529
 530         if (elapsed & AMD7930_FLAG_PLAYBACK)
 531                 snd_pcm_period_elapsed(amd->playback_substream);
 532         else
 533                 snd_pcm_period_elapsed(amd->capture_substream);
 534
 535         return IRQ_HANDLED;
 536 }
 537
 538 static int snd_amd7930_trigger(amd7930_t *amd, unsigned int flag, int cmd)
 539 {
 540         unsigned long flags;
 541         int result = 0;
 542
 543         spin_lock_irqsave(&amd->lock, flags);
 544         if (cmd == SNDRV_PCM_TRIGGER_START) {
 545                 if (!(amd->flags & flag)) {
 546                         amd->flags |= flag;
 547
 548                         /* Enable B channel interrupts.  */
 549                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
 550                         sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
 551                 }
 552         } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 553                 if (amd->flags & flag) {
 554                         amd->flags &= ~flag;
 555
 556                         /* Disable B channel interrupts.  */
 557                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
 558                         sbus_writeb(0, amd->regs + AMD7930_DR);
 559                 }
 560         } else {
 561                 result = -EINVAL;
 562         }
 563         spin_unlock_irqrestore(&amd->lock, flags);
 564
 565         return result;
 566 }
 567
 568 static int snd_amd7930_playback_trigger(snd_pcm_substream_t * substream,
 569                                         int cmd)
 570 {
 571         amd7930_t *amd = snd_pcm_substream_chip(substream);
 572         return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
 573 }
 574
 575 static int snd_amd7930_capture_trigger(snd_pcm_substream_t * substream,
 576                                        int cmd)
 577 {
 578         amd7930_t *amd = snd_pcm_substream_chip(substream);
 579         return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
 580 }
 581
 582 static int snd_amd7930_playback_prepare(snd_pcm_substream_t * substream)
 583 {
 584         amd7930_t *amd = snd_pcm_substream_chip(substream);
 585         snd_pcm_runtime_t *runtime = substream->runtime;
 586         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
 587         unsigned long flags;
 588         u8 new_mmr1;
 589
 590         spin_lock_irqsave(&amd->lock, flags);
 591
 592         amd->flags |= AMD7930_FLAG_PLAYBACK;
 593
 594         /* Setup the pseudo-dma transfer pointers.  */
 595         amd->p_orig = amd->p_cur = runtime->dma_area;
 596         amd->p_left = size;
 597
 598         /* Put the chip into the correct encoding format.  */
 599         new_mmr1 = amd->map.mmr1;
 600         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
 601                 new_mmr1 |= AM_MAP_MMR1_ALAW;
 602         else
 603                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
 604         if (new_mmr1 != amd->map.mmr1) {
 605                 amd->map.mmr1 = new_mmr1;
 606                 __amd7930_update_map(amd);
 607         }
 608
 609         spin_unlock_irqrestore(&amd->lock, flags);
 610
 611         return 0;
 612 }
 613
 614 static int snd_amd7930_capture_prepare(snd_pcm_substream_t * substream)
 615 {
 616         amd7930_t *amd = snd_pcm_substream_chip(substream);
 617         snd_pcm_runtime_t *runtime = substream->runtime;
 618         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
 619         unsigned long flags;
 620         u8 new_mmr1;
 621
 622         spin_lock_irqsave(&amd->lock, flags);
 623
 624         amd->flags |= AMD7930_FLAG_CAPTURE;
 625
 626         /* Setup the pseudo-dma transfer pointers.  */
 627         amd->c_orig = amd->c_cur = runtime->dma_area;
 628         amd->c_left = size;
 629
 630         /* Put the chip into the correct encoding format.  */
 631         new_mmr1 = amd->map.mmr1;
 632         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
 633                 new_mmr1 |= AM_MAP_MMR1_ALAW;
 634         else
 635                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
 636         if (new_mmr1 != amd->map.mmr1) {
 637                 amd->map.mmr1 = new_mmr1;
 638                 __amd7930_update_map(amd);
 639         }
 640
 641         spin_unlock_irqrestore(&amd->lock, flags);
 642
 643         return 0;
 644 }
 645
 646 static snd_pcm_uframes_t snd_amd7930_playback_pointer(snd_pcm_substream_t * substream)
 647 {
 648         amd7930_t *amd = snd_pcm_substream_chip(substream);
 649         size_t ptr;
 650
 651         if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
 652                 return 0;
 653         ptr = amd->p_cur - amd->p_orig;
 654         return bytes_to_frames(substream->runtime, ptr);
 655 }
 656
 657 static snd_pcm_uframes_t snd_amd7930_capture_pointer(snd_pcm_substream_t * substream)
 658 {
 659         amd7930_t *amd = snd_pcm_substream_chip(substream);
 660         size_t ptr;
 661
 662         if (!(amd->flags & AMD7930_FLAG_CAPTURE))
 663                 return 0;
 664
 665         ptr = amd->c_cur - amd->c_orig;
 666         return bytes_to_frames(substream->runtime, ptr);
 667 }
 668
 669 /* Playback and capture have identical properties.  */
 670 static snd_pcm_hardware_t snd_amd7930_pcm_hw =
 671 {
 672         .info                   = (SNDRV_PCM_INFO_MMAP |
 673                                    SNDRV_PCM_INFO_MMAP_VALID |
 674                                    SNDRV_PCM_INFO_INTERLEAVED |
 675                                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
 676                                    SNDRV_PCM_INFO_HALF_DUPLEX),
 677         .formats                = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
 678         .rates                  = SNDRV_PCM_RATE_8000,
 679         .rate_min               = 8000,
 680         .rate_max               = 8000,
 681         .channels_min           = 1,
 682         .channels_max           = 1,
 683         .buffer_bytes_max       = (64*1024),
 684         .period_bytes_min       = 1,
 685         .period_bytes_max       = (64*1024),
 686         .periods_min            = 1,
 687         .periods_max            = 1024,
 688 };
 689
 690 static int snd_amd7930_playback_open(snd_pcm_substream_t * substream)
 691 {
 692         amd7930_t *amd = snd_pcm_substream_chip(substream);
 693         snd_pcm_runtime_t *runtime = substream->runtime;
 694
 695         amd->playback_substream = substream;
 696         runtime->hw = snd_amd7930_pcm_hw;
 697         return 0;
 698 }
 699
 700 static int snd_amd7930_capture_open(snd_pcm_substream_t * substream)
 701 {
 702         amd7930_t *amd = snd_pcm_substream_chip(substream);
 703         snd_pcm_runtime_t *runtime = substream->runtime;
 704
 705         amd->capture_substream = substream;
 706         runtime->hw = snd_amd7930_pcm_hw;
 707         return 0;
 708 }
 709
 710 static int snd_amd7930_playback_close(snd_pcm_substream_t * substream)
 711 {
 712         amd7930_t *amd = snd_pcm_substream_chip(substream);
 713
 714         amd->playback_substream = NULL;
 715         return 0;
 716 }
 717
 718 static int snd_amd7930_capture_close(snd_pcm_substream_t * substream)
 719 {
 720         amd7930_t *amd = snd_pcm_substream_chip(substream);
 721
 722         amd->capture_substream = NULL;
 723         return 0;
 724 }
 725
 726 static int snd_amd7930_hw_params(snd_pcm_substream_t * substream,
 727                                     snd_pcm_hw_params_t * hw_params)
 728 {
 729         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 730 }
 731
 732 static int snd_amd7930_hw_free(snd_pcm_substream_t * substream)
 733 {
 734         return snd_pcm_lib_free_pages(substream);
 735 }
 736
 737 static snd_pcm_ops_t snd_amd7930_playback_ops = {
 738         .open           =       snd_amd7930_playback_open,
 739         .close          =       snd_amd7930_playback_close,
 740         .ioctl          =       snd_pcm_lib_ioctl,
 741         .hw_params      =       snd_amd7930_hw_params,
 742         .hw_free        =       snd_amd7930_hw_free,
 743         .prepare        =       snd_amd7930_playback_prepare,
 744         .trigger        =       snd_amd7930_playback_trigger,
 745         .pointer        =       snd_amd7930_playback_pointer,
 746 };
 747
 748 static snd_pcm_ops_t snd_amd7930_capture_ops = {
 749         .open           =       snd_amd7930_capture_open,
 750         .close          =       snd_amd7930_capture_close,
 751         .ioctl          =       snd_pcm_lib_ioctl,
 752         .hw_params      =       snd_amd7930_hw_params,
 753         .hw_free        =       snd_amd7930_hw_free,
 754         .prepare        =       snd_amd7930_capture_prepare,
 755         .trigger        =       snd_amd7930_capture_trigger,
 756         .pointer        =       snd_amd7930_capture_pointer,
 757 };
 758
 759 static void snd_amd7930_pcm_free(snd_pcm_t *pcm)
 760 {
 761         amd7930_t *amd = pcm->private_data;
 762
 763         amd->pcm = NULL;
 764         snd_pcm_lib_preallocate_free_for_all(pcm);
 765 }
 766
 767 static int __init snd_amd7930_pcm(amd7930_t *amd)
 768 {
 769         snd_pcm_t *pcm;
 770         int err;
 771
 772         if ((err = snd_pcm_new(amd->card,
 773                                /* ID */             "sun_amd7930",
 774                                /* device */         0,
 775                                /* playback count */ 1,
 776                                /* capture count */  1, &pcm)) < 0)
 777                 return err;
 778         snd_assert(pcm != NULL, return -EINVAL);
 779
 780         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
 781         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
 782
 783         pcm->private_data = amd;
 784         pcm->private_free = snd_amd7930_pcm_free;
 785         pcm->info_flags = 0;
 786         strcpy(pcm->name, amd->card->shortname);
 787         amd->pcm = pcm;
 788
 789         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
 790                                               snd_dma_continuous_data(GFP_KERNEL),
 791                                               64*1024, 64*1024);
 792
 793         return 0;
 794 }
 795
 796 #define VOLUME_MONITOR  0
 797 #define VOLUME_CAPTURE  1
 798 #define VOLUME_PLAYBACK 2
 799
 800 static int snd_amd7930_info_volume(snd_kcontrol_t *kctl, snd_ctl_elem_info_t *uinfo)
 801 {
 802         int type = kctl->private_value;
 803
 804         snd_assert(type == VOLUME_MONITOR ||
 805                    type == VOLUME_CAPTURE ||
 806                    type == VOLUME_PLAYBACK, return -EINVAL);
 807         (void) type;
 808
 809         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 810         uinfo->count = 1;
 811         uinfo->value.integer.min = 0;
 812         uinfo->value.integer.max = 255;
 813
 814         return 0;
 815 }
 816
 817 static int snd_amd7930_get_volume(snd_kcontrol_t *kctl, snd_ctl_elem_value_t *ucontrol)
 818 {
 819         amd7930_t *amd = snd_kcontrol_chip(kctl);
 820         int type = kctl->private_value;
 821         int *swval;
 822
 823         snd_assert(type == VOLUME_MONITOR ||
 824                    type == VOLUME_CAPTURE ||
 825                    type == VOLUME_PLAYBACK, return -EINVAL);
 826
 827         switch (type) {
 828         case VOLUME_MONITOR:
 829                 swval = &amd->mgain;
 830                 break;
 831         case VOLUME_CAPTURE:
 832                 swval = &amd->rgain;
 833                 break;
 834         case VOLUME_PLAYBACK:
 835         default:
 836                 swval = &amd->pgain;
 837                 break;
 838         };
 839
 840         ucontrol->value.integer.value[0] = *swval;
 841
 842         return 0;
 843 }
 844
 845 static int snd_amd7930_put_volume(snd_kcontrol_t *kctl, snd_ctl_elem_value_t *ucontrol)
 846 {
 847         amd7930_t *amd = snd_kcontrol_chip(kctl);
 848         unsigned long flags;
 849         int type = kctl->private_value;
 850         int *swval, change;
 851
 852         snd_assert(type == VOLUME_MONITOR ||
 853                    type == VOLUME_CAPTURE ||
 854                    type == VOLUME_PLAYBACK, return -EINVAL);
 855
 856         switch (type) {
 857         case VOLUME_MONITOR:
 858                 swval = &amd->mgain;
 859                 break;
 860         case VOLUME_CAPTURE:
 861                 swval = &amd->rgain;
 862                 break;
 863         case VOLUME_PLAYBACK:
 864         default:
 865                 swval = &amd->pgain;
 866                 break;
 867         };
 868
 869         spin_lock_irqsave(&amd->lock, flags);
 870
 871         if (*swval != ucontrol->value.integer.value[0]) {
 872                 *swval = ucontrol->value.integer.value[0];
 873                 __amd7930_update_map(amd);
 874                 change = 1;
 875         } else
 876                 change = 0;
 877
 878         spin_unlock_irqrestore(&amd->lock, flags);
 879
 880         return change;
 881 }
 882
 883 static snd_kcontrol_new_t amd7930_controls[] __initdata = {
 884         {
 885                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
 886                 .name           =       "Monitor Volume",
 887                 .index          =       0,
 888                 .info           =       snd_amd7930_info_volume,
 889                 .get            =       snd_amd7930_get_volume,
 890                 .put            =       snd_amd7930_put_volume,
 891                 .private_value  =       VOLUME_MONITOR,
 892         },
 893         {
 894                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
 895                 .name           =       "Capture Volume",
 896                 .index          =       0,
 897                 .info           =       snd_amd7930_info_volume,
 898                 .get            =       snd_amd7930_get_volume,
 899                 .put            =       snd_amd7930_put_volume,
 900                 .private_value  =       VOLUME_CAPTURE,
 901         },
 902         {
 903                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
 904                 .name           =       "Playback Volume",
 905                 .index          =       0,
 906                 .info           =       snd_amd7930_info_volume,
 907                 .get            =       snd_amd7930_get_volume,
 908                 .put            =       snd_amd7930_put_volume,
 909                 .private_value  =       VOLUME_PLAYBACK,
 910         },
 911 };
 912
 913 static int __init snd_amd7930_mixer(amd7930_t *amd)
 914 {
 915         snd_card_t *card;
 916         int idx, err;
 917
 918         snd_assert(amd != NULL && amd->card != NULL, return -EINVAL);
 919
 920         card = amd->card;
 921         strcpy(card->mixername, card->shortname);
 922
 923         for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
 924                 if ((err = snd_ctl_add(card,
 925                                        snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
 926                         return err;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int snd_amd7930_free(amd7930_t *amd)
 933 {
 934         amd7930_idle(amd);
 935
 936         if (amd->irq)
 937                 free_irq(amd->irq, amd);
 938
 939         if (amd->regs)
 940                 sbus_iounmap(amd->regs, amd->regs_size);
 941
 942         kfree(amd);
 943
 944         return 0;
 945 }
 946
 947 static int snd_amd7930_dev_free(snd_device_t *device)
 948 {
 949         amd7930_t *amd = device->device_data;
 950
 951         return snd_amd7930_free(amd);
 952 }
 953
 954 static snd_device_ops_t snd_amd7930_dev_ops = {
 955         .dev_free       =       snd_amd7930_dev_free,
 956 };
 957
 958 static int __init snd_amd7930_create(snd_card_t *card,
 959                                      struct sbus_dev *sdev,
 960                                      struct resource *rp,
 961                                      unsigned int reg_size,
 962                                      struct linux_prom_irqs *irq_prop,
 963                                      int dev,
 964                                      amd7930_t **ramd)
 965 {
 966         unsigned long flags;
 967         amd7930_t *amd;
 968         int err;
 969
 970         *ramd = NULL;
 971         amd = kcalloc(1, sizeof(*amd), GFP_KERNEL);
 972         if (amd == NULL)
 973                 return -ENOMEM;
 974
 975         spin_lock_init(&amd->lock);
 976         amd->card = card;
 977         amd->sdev = sdev;
 978         amd->regs_size = reg_size;
 979
 980         amd->regs = sbus_ioremap(rp, 0, amd->regs_size, "amd7930");
 981         if (!amd->regs) {
 982                 snd_printk("amd7930-%d: Unable to map chip registers.\n", dev);
 983                 return -EIO;
 984         }
 985
 986         amd7930_idle(amd);
 987
 988         if (request_irq(irq_prop->pri, snd_amd7930_interrupt,
 989                         SA_INTERRUPT | SA_SHIRQ, "amd7930", amd)) {
 990                 snd_printk("amd7930-%d: Unable to grab IRQ %s\n",
 991                            dev,
 992                            __irq_itoa(irq_prop->pri));
 993                 snd_amd7930_free(amd);
 994                 return -EBUSY;
 995         }
 996         amd->irq = irq_prop->pri;
 997
 998         amd7930_enable_ints(amd);
 999
1000         spin_lock_irqsave(&amd->lock, flags);
1001
1002         amd->rgain = 128;
1003         amd->pgain = 200;
1004         amd->mgain = 0;
1005
1006         memset(&amd->map, 0, sizeof(amd->map));
1007         amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
1008                          AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
1009         amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
1010
1011         __amd7930_update_map(amd);
1012
1013         /* Always MUX audio (Ba) to channel Bb. */
1014         sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
1015         sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
1016                     amd->regs + AMD7930_DR);
1017
1018         spin_unlock_irqrestore(&amd->lock, flags);
1019
1020         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
1021                                   amd, &snd_amd7930_dev_ops)) < 0) {
1022                 snd_amd7930_free(amd);
1023                 return err;
1024         }
1025
1026         *ramd = amd;
1027         return 0;
1028 }
1029
1030 static int __init amd7930_attach(int prom_node, struct sbus_dev *sdev)
1031 {
1032         static int dev;
1033         struct linux_prom_registers reg_prop;
1034         struct linux_prom_irqs irq_prop;
1035         struct resource res, *rp;
1036         snd_card_t *card;
1037         amd7930_t *amd;
1038         int err;
1039
1040         if (dev >= SNDRV_CARDS)
1041                 return -ENODEV;
1042         if (!enable[dev]) {
1043                 dev++;
1044                 return -ENOENT;
1045         }
1046
1047         err = prom_getproperty(prom_node, "intr",
1048                                (char *) &irq_prop, sizeof(irq_prop));
1049         if (err < 0) {
1050                 snd_printk("amd7930-%d: Firmware node lacks IRQ property.\n", dev);
1051                 return -ENODEV;
1052         }
1053
1054         err = prom_getproperty(prom_node, "reg",
1055                                (char *) &reg_prop, sizeof(reg_prop));
1056         if (err < 0) {
1057                 snd_printk("amd7930-%d: Firmware node lacks register property.\n", dev);
1058                 return -ENODEV;
1059         }
1060
1061         if (sdev) {
1062                 rp = &sdev->resource[0];
1063         } else {
1064                 rp = &res;
1065                 rp->start = reg_prop.phys_addr;
1066                 rp->end = rp->start + reg_prop.reg_size - 1;
1067                 rp->flags = IORESOURCE_IO | (reg_prop.which_io & 0xff);
1068         }
1069
1070         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1071         if (card == NULL)
1072                 return -ENOMEM;
1073
1074         strcpy(card->driver, "AMD7930");
1075         strcpy(card->shortname, "Sun AMD7930");
1076         sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
1077                 card->shortname,
1078                 rp->flags & 0xffL,
1079                 rp->start,
1080                 __irq_itoa(irq_prop.pri));
1081
1082         if ((err = snd_amd7930_create(card, sdev, rp, reg_prop.reg_size,
1083                                           &irq_prop, dev, &amd)) < 0)
1084                 goto out_err;
1085
1086         if ((err = snd_amd7930_pcm(amd)) < 0)
1087                 goto out_err;
1088
1089         if ((err = snd_amd7930_mixer(amd)) < 0)
1090                 goto out_err;
1091
1092         if ((err = snd_card_register(card)) < 0)
1093                 goto out_err;
1094
1095         amd->next = amd7930_list;
1096         amd7930_list = amd;
1097
1098         dev++;
1099         return 0;
1100
1101 out_err:
1102         snd_card_free(card);
1103         return err;
1104 }
1105
1106 static int __init amd7930_init(void)
1107 {
1108         struct sbus_bus *sbus;
1109         struct sbus_dev *sdev;
1110         int node, found;
1111
1112         found = 0;
1113
1114         /* Try to find the sun4c "audio" node first. */
1115         node = prom_getchild(prom_root_node);
1116         node = prom_searchsiblings(node, "audio");
1117         if (node && amd7930_attach(node, NULL) == 0)
1118                 found++;
1119
1120         /* Probe each SBUS for amd7930 chips. */
1121         for_all_sbusdev(sdev, sbus) {
1122                 if (!strcmp(sdev->prom_name, "audio")) {
1123                         if (amd7930_attach(sdev->prom_node, sdev) == 0)
1124                                 found++;
1125                 }
1126         }
1127
1128         return (found > 0) ? 0 : -EIO;
1129 }
1130
1131 static void __exit amd7930_exit(void)
1132 {
1133         amd7930_t *p = amd7930_list;
1134
1135         while (p != NULL) {
1136                 amd7930_t *next = p->next;
1137
1138                 snd_card_free(p->card);
1139
1140                 p = next;
1141         }
1142
1143         amd7930_list = NULL;
1144 }
1145
1146 module_init(amd7930_init);
1147 module_exit(amd7930_exit);