--- /dev/null
+
+ Linux kernel management style
+
+This is a short document describing the preferred (or made up, depending
+on who you ask) management style for the linux kernel. It's meant to
+mirror the CodingStyle document to some degree, and mainly written to
+avoid answering (*) the same (or similar) questions over and over again.
+
+Management style is very personal and much harder to quantify than
+simple coding style rules, so this document may or may not have anything
+to do with reality. It started as a lark, but that doesn't mean that it
+might not actually be true. You'll have to decide for yourself.
+
+Btw, when talking about "kernel manager", it's all about the technical
+lead persons, not the people who do traditional management inside
+companies. If you sign purchase orders or you have any clue about the
+budget of your group, you're almost certainly not a kernel manager.
+These suggestions may or may not apply to you.
+
+First off, I'd suggest buying "Seven Habits of Highly Successful
+People", and NOT read it. Burn it, it's a great symbolic gesture.
+
+(*) This document does so not so much by answering the question, but by
+making it painfully obvious to the questioner that we don't have a clue
+to what the answer is.
+
+Anyway, here goes:
+
+
+ Chapter 1: Decisions
+
+Everybody thinks managers make decisions, and that decision-making is
+important. The bigger and more painful the decision, the bigger the
+manager must be to make it. That's very deep and obvious, but it's not
+actually true.
+
+The name of the game is to _avoid_ having to make a decision. In
+particular, if somebody tells you "choose (a) or (b), we really need you
+to decide on this", you're in trouble as a manager. The people you
+manage had better know the details better than you, so if they come to
+you for a technical decision, you're screwed. You're clearly not
+competent to make that decision for them.
+
+(Corollary:if the people you manage don't know the details better than
+you, you're also screwed, although for a totally different reason.
+Namely that you are in the wrong job, and that _they_ should be managing
+your brilliance instead).
+
+So the name of the game is to _avoid_ decisions, at least the big and
+painful ones. Making small and non-consequential decisions is fine, and
+makes you look like you know what you're doing, so what a kernel manager
+needs to do is to turn the big and painful ones into small things where
+nobody really cares.
+
+It helps to realize that the key difference between a big decision and a
+small one is whether you can fix your decision afterwards. Any decision
+can be made small by just always making sure that if you were wrong (and
+you _will_ be wrong), you can always undo the damage later by
+backtracking. Suddenly, you get to be doubly managerial for making
+_two_ inconsequential decisions - the wrong one _and_ the right one.
+
+And people will even see that as true leadership (*cough* bullshit
+*cough*).
+
+Thus the key to avoiding big decisions becomes to just avoiding to do
+things that can't be undone. Don't get ushered into a corner from which
+you cannot escape. A cornered rat may be dangerous - a cornered manager
+is just pitiful.
+
+It turns out that since nobody would be stupid enough to ever really let
+a kernel manager have huge fiscal responsibility _anyway_, it's usually
+fairly easy to backtrack. Since you're not going to be able to waste
+huge amounts of money that you might not be able to repay, the only
+thing you can backtrack on is a technical decision, and there
+back-tracking is very easy: just tell everybody that you were an
+incompetent nincompoop, say you're sorry, and undo all the worthless
+work you had people work on for the last year. Suddenly the decision
+you made a year ago wasn't a big decision after all, since it could be
+easily undone.
+
+It turns out that some people have trouble with this approach, for two
+reasons:
+ - admitting you were an idiot is harder than it looks. We all like to
+ maintain appearances, and coming out in public to say that you were
+ wrong is sometimes very hard indeed.
+ - having somebody tell you that what you worked on for the last year
+ wasn't worthwhile after all can be hard on the poor lowly engineers
+ too, and while the actual _work_ was easy enough to undo by just
+ deleting it, you may have irrevocably lost the trust of that
+ engineer. And remember: "irrevocable" was what we tried to avoid in
+ the first place, and your decision ended up being a big one after
+ all.
+
+Happily, both of these reasons can be mitigated effectively by just
+admitting up-front that you don't have a friggin' clue, and telling
+people ahead of the fact that your decision is purely preliminary, and
+might be the wrong thing. You should always reserve the right to change
+your mind, and make people very _aware_ of that. And it's much easier
+to admit that you are stupid when you haven't _yet_ done the really
+stupid thing.
+
+Then, when it really does turn out to be stupid, people just roll their
+eyes and say "Oops, he did it again".
+
+This preemptive admission of incompetence might also make the people who
+actually do the work also think twice about whether it's worth doing or
+not. After all, if _they_ aren't certain whether it's a good idea, you
+sure as hell shouldn't encourage them by promising them that what they
+work on will be included. Make them at least think twice before they
+embark on a big endeavor.
+
+Remember: they'd better know more about the details than you do, and
+they usually already think they have the answer to everything. The best
+thing you can do as a manager is not to instill confidence, but rather a
+healthy dose of critical thinking on what they do.
+
+Btw, another way to avoid a decision is to plaintively just whine "can't
+we just do both?" and look pitiful. Trust me, it works. If it's not
+clear which approach is better, they'll eventually figure it out. The
+answer may end up being that both teams get so frustrated by the
+situation that they just give up.
+
+That may sound like a failure, but it's usually a sign that there was
+something wrong with both projects, and the reason the people involved
+couldn't decide was that they were both wrong. You end up coming up
+smelling like roses, and you avoided yet another decision that you could
+have screwed up on.
+
+
+ Chapter 2: People
+
+Most people are idiots, and being a manager means you'll have to deal
+with it, and perhaps more importantly, that _they_ have to deal with
+_you_.
+
+It turns out that while it's easy to undo technical mistakes, it's not
+as easy to undo personality disorders. You just have to live with
+theirs - and yours.
+
+However, in order to prepare yourself as a kernel manager, it's best to
+remember not to burn any bridges, bomb any innocent villagers, or
+alienate too many kernel developers. It turns out that alienating people
+is fairly easy, and un-alienating them is hard. Thus "alienating"
+immediately falls under the heading of "not reversible", and becomes a
+no-no according to Chapter 1.
+
+There's just a few simple rules here:
+ (1) don't call people d*ckheads (at least not in public)
+ (2) learn how to apologize when you forgot rule (1)
+
+The problem with #1 is that it's very easy to do, since you can say
+"you're a d*ckhead" in millions of different ways (*), sometimes without
+even realizing it, and almost always with a white-hot conviction that
+you are right.
+
+And the more convinced you are that you are right (and let's face it,
+you can call just about _anybody_ a d*ckhead, and you often _will_ be
+right), the harder it ends up being to apologize afterwards.
+
+To solve this problem, you really only have two options:
+ - get really good at apologies
+ - spread the "love" out so evenly that nobody really ends up feeling
+ like they get unfairly targeted. Make it inventive enough, and they
+ might even be amused.
+
+The option of being unfailingly polite really doesn't exist. Nobody will
+trust somebody who is so clearly hiding his true character.
+
+(*) Paul Simon sang "Fifty Ways to Lose Your Lover", because quite
+frankly, "A Million Ways to Tell a Developer He Is a D*ckhead" doesn't
+scan nearly as well. But I'm sure he thought about it.
+
+
+ Chapter 3: People II - the Good Kind
+
+While it turns out that most people are idiots, the corollary to that is
+sadly that you are one too, and that while we can all bask in the secure
+knowledge that we're better than the average person (let's face it,
+nobody ever believes that they're average or below-average), we should
+also admit that we're not the sharpest knife around, and there will be
+other people that are less of an idiot that you are.
+
+Some people react badly to smart people. Others take advantage of them.
+
+Make sure that you, as a kernel maintainer, are in the second group.
+Suck up to them, because they are the people who will make your job
+easier. In particular, they'll be able to make your decisions for you,
+which is what the game is all about.
+
+So when you find somebody smarter than you are, just coast along. Your
+management responsibilities largely become ones of saying "Sounds like a
+good idea - go wild", or "That sounds good, but what about xxx?". The
+second version in particular is a great way to either learn something
+new about "xxx" or seem _extra_ managerial by pointing out something the
+smarter person hadn't thought about. In either case, you win.
+
+One thing to look out for is to realize that greatness in one area does
+not necessarily translate to other areas. So you might prod people in
+specific directions, but let's face it, they might be good at what they
+do, and suck at everything else. The good news is that people tend to
+naturally gravitate back to what they are good at, so it's not like you
+are doing something irreversible when you _do_ prod them in some
+direction, just don't push too hard.
+
+
+ Chapter 4: Placing blame
+
+Things will go wrong, and people want somebody to blame. Tag, you're it.
+
+It's not actually that hard to accept the blame, especially if people
+kind of realize that it wasn't _all_ your fault. Which brings us to the
+best way of taking the blame: do it for another guy. You'll feel good
+for taking the fall, he'll feel good about not getting blamed, and the
+guy who lost his whole 36GB porn-collection because of your incompetence
+will grudgingly admit that you at least didn't try to weasel out of it.
+
+Then make the developer who really screwed up (if you can find him) know
+_in_private_ that he screwed up. Not just so he can avoid it in the
+future, but so that he knows he owes you one. And, perhaps even more
+importantly, he's also likely the person who can fix it. Because, let's
+face it, it sure ain't you.
+
+Taking the blame is also why you get to be manager in the first place.
+It's part of what makes people trust you, and allow you the potential
+glory, because you're the one who gets to say "I screwed up". And if
+you've followed the previous rules, you'll be pretty good at saying that
+by now.
+
+
+ Chapter 5: Things to avoid
+
+There's one thing people hate even more than being called "d*ckhead",
+and that is being called a "d*ckhead" in a sanctimonious voice. The
+first you can apologize for, the second one you won't really get the
+chance. They likely will no longer be listening even if you otherwise
+do a good job.
+
+We all think we're better than anybody else, which means that when
+somebody else puts on airs, it _really_ rubs us the wrong way. You may
+be morally and intellectually superior to everybody around you, but
+don't try to make it too obvious unless you really _intend_ to irritate
+somebody (*).
+
+Similarly, don't be too polite or subtle about things. Politeness easily
+ends up going overboard and hiding the problem, and as they say, "On the
+internet, nobody can hear you being subtle". Use a big blunt object to
+hammer the point in, because you can't really depend on people getting
+your point otherwise.
+
+Some humor can help pad both the bluntness and the moralizing. Going
+overboard to the point of being ridiculous can drive a point home
+without making it painful to the recipient, who just thinks you're being
+silly. It can thus help get through the personal mental block we all
+have about criticism.
+
+(*) Hint: internet newsgroups that are not directly related to your work
+are great ways to take out your frustrations at other people. Write
+insulting posts with a sneer just to get into a good flame every once in
+a while, and you'll feel cleansed. Just don't crap too close to home.
+
+
+ Chapter 6: Why me?
+
+Since your main responsibility seems to be to take the blame for other
+peoples mistakes, and make it painfully obvious to everybody else that
+you're incompetent, the obvious question becomes one of why do it in the
+first place?
+
+First off, while you may or may not get screaming teenage girls (or
+boys, let's not be judgmental or sexist here) knocking on your dressing
+room door, you _will_ get an immense feeling of personal accomplishment
+for being "in charge". Never mind the fact that you're really leading
+by trying to keep up with everybody else and running after them as fast
+as you can. Everybody will still think you're the person in charge.
+
+It's a great job if you can hack it.
--- /dev/null
+Read the F-ing Papers!
+
+
+This document describes RCU-related publications, and is followed by
+the corresponding bibtex entries.
+
+The first thing resembling RCU was published in 1980, when Kung and Lehman
+[Kung80] recommended use of a garbage collector to defer destruction
+of nodes in a parallel binary search tree in order to simplify its
+implementation. This works well in environments that have garbage
+collectors, but current production garbage collectors incur significant
+read-side overhead.
+
+In 1982, Manber and Ladner [Manber82,Manber84] recommended deferring
+destruction until all threads running at that time have terminated, again
+for a parallel binary search tree. This approach works well in systems
+with short-lived threads, such as the K42 research operating system.
+However, Linux has long-lived tasks, so more is needed.
+
+In 1986, Hennessy, Osisek, and Seigh [Hennessy89] introduced passive
+serialization, which is an RCU-like mechanism that relies on the presence
+of "quiescent states" in the VM/XA hypervisor that are guaranteed not
+to be referencing the data structure. However, this mechanism was not
+optimized for modern computer systems, which is not surprising given
+that these overheads were not so expensive in the mid-80s. Nonetheless,
+passive serialization appears to be the first deferred-destruction
+mechanism to be used in production. Furthermore, the relevant patent has
+lapsed, so this approach may be used in non-GPL software, if desired.
+(In contrast, use of RCU is permitted only in software licensed under
+GPL. Sorry!!!)
+
+In 1990, Pugh [Pugh90] noted that explicitly tracking which threads
+were reading a given data structure permitted deferred free to operate
+in the presence of non-terminating threads. However, this explicit
+tracking imposes significant read-side overhead, which is undesirable
+in read-mostly situations. This algorithm does take pains to avoid
+write-side contention and parallelize the other write-side overheads by
+providing a fine-grained locking design, however, it would be interesting
+to see how much of the performance advantage reported in 1990 remains
+in 2004.
+
+At about this same time, Adams [Adams91] described ``chaotic relaxation'',
+where the normal barriers between successive iterations of convergent
+numerical algorithms are relaxed, so that iteration $n$ might use
+data from iteration $n-1$ or even $n-2$. This introduces error,
+which typically slows convergence and thus increases the number of
+iterations required. However, this increase is sometimes more than made
+up for by a reduction in the number of expensive barrier operations,
+which are otherwise required to synchronize the threads at the end
+of each iteration. Unfortunately, chaotic relaxation requires highly
+structured data, such as the matrices used in scientific programs, and
+is thus inapplicable to most data structures in operating-system kernels.
+
+In 1993, Jacobson [Jacobson93] verbally described what is perhaps the
+simplest deferred-free technique: simply waiting a fixed amount of time
+before freeing blocks awaiting deferred free. Jacobson did not describe
+any write-side changes he might have made in this work using SGI's Irix
+kernel. Aju John published a similar technique in 1995 [AjuJohn95].
+This works well if there is a well-defined upper bound on the length of
+time that reading threads can hold references, as there might well be in
+hard real-time systems. However, if this time is exceeded, perhaps due
+to preemption, excessive interrupts, or larger-than-anticipated load,
+memory corruption can ensue, with no reasonable means of diagnosis.
+Jacobson's technique is therefore inappropriate for use in production
+operating-system kernels, except when such kernels can provide hard
+real-time response guarantees for all operations.
+
+Also in 1995, Pu et al. [Pu95a] applied a technique similar to that of Pugh's
+read-side-tracking to permit replugging of algorithms within a commercial
+Unix operating system. However, this replugging permitted only a single
+reader at a time. The following year, this same group of researchers
+extended their technique to allow for multiple readers [Cowan96a].
+Their approach requires memory barriers (and thus pipeline stalls),
+but reduces memory latency, contention, and locking overheads.
+
+1995 also saw the first publication of DYNIX/ptx's RCU mechanism
+[Slingwine95], which was optimized for modern CPU architectures,
+and was successfully applied to a number of situations within the
+DYNIX/ptx kernel. The corresponding conference paper appeared in 1998
+[McKenney98].
+
+In 1999, the Tornado and K42 groups described their "generations"
+mechanism, which quite similar to RCU [Gamsa99]. These operating systems
+made pervasive use of RCU in place of "existence locks", which greatly
+simplifies locking hierarchies.
+
+2001 saw the first RCU presentation involving Linux [McKenney01a]
+at OLS. The resulting abundance of RCU patches was presented the
+following year [McKenney02a], and use of RCU in dcache was first
+described that same year [Linder02a].
+
+Also in 2002, Michael [Michael02b,Michael02a] presented techniques
+that defer the destruction of data structures to simplify non-blocking
+synchronization (wait-free synchronization, lock-free synchronization,
+and obstruction-free synchronization are all examples of non-blocking
+synchronization). In particular, this technique eliminates locking,
+reduces contention, reduces memory latency for readers, and parallelizes
+pipeline stalls and memory latency for writers. However, these
+techniques still impose significant read-side overhead in the form of
+memory barriers. Researchers at Sun worked along similar lines in the
+same timeframe [HerlihyLM02,HerlihyLMS03].
+
+In 2003, the K42 group described how RCU could be used to create
+hot-pluggable implementations of operating-system functions. Later that
+year saw a paper describing an RCU implementation of System V IPC
+[Arcangeli03], and an introduction to RCU in Linux Journal [McKenney03a].
+
+2004 has seen a Linux-Journal article on use of RCU in dcache
+[McKenney04a], a performance comparison of locking to RCU on several
+different CPUs [McKenney04b], a dissertation describing use of RCU in a
+number of operating-system kernels [PaulEdwardMcKenneyPhD], and a paper
+describing how to make RCU safe for soft-realtime applications [Sarma04c].
+
+
+Bibtex Entries
+
+@article{Kung80
+,author="H. T. Kung and Q. Lehman"
+,title="Concurrent Maintenance of Binary Search Trees"
+,Year="1980"
+,Month="September"
+,journal="ACM Transactions on Database Systems"
+,volume="5"
+,number="3"
+,pages="354-382"
+}
+
+@techreport{Manber82
+,author="Udi Manber and Richard E. Ladner"
+,title="Concurrency Control in a Dynamic Search Structure"
+,institution="Department of Computer Science, University of Washington"
+,address="Seattle, Washington"
+,year="1982"
+,number="82-01-01"
+,month="January"
+,pages="28"
+}
+
+@article{Manber84
+,author="Udi Manber and Richard E. Ladner"
+,title="Concurrency Control in a Dynamic Search Structure"
+,Year="1984"
+,Month="September"
+,journal="ACM Transactions on Database Systems"
+,volume="9"
+,number="3"
+,pages="439-455"
+}
+
+@techreport{Hennessy89
+,author="James P. Hennessy and Damian L. Osisek and Joseph W. {Seigh II}"
+,title="Passive Serialization in a Multitasking Environment"
+,institution="US Patent and Trademark Office"
+,address="Washington, DC"
+,year="1989"
+,number="US Patent 4,809,168 (lapsed)"
+,month="February"
+,pages="11"
+}
+
+@techreport{Pugh90
+,author="William Pugh"
+,title="Concurrent Maintenance of Skip Lists"
+,institution="Institute of Advanced Computer Science Studies, Department of Computer Science, University of Maryland"
+,address="College Park, Maryland"
+,year="1990"
+,number="CS-TR-2222.1"
+,month="June"
+}
+
+@Book{Adams91
+,Author="Gregory R. Adams"
+,title="Concurrent Programming, Principles, and Practices"
+,Publisher="Benjamin Cummins"
+,Year="1991"
+}
+
+@unpublished{Jacobson93
+,author="Van Jacobson"
+,title="Avoid Read-Side Locking Via Delayed Free"
+,year="1993"
+,month="September"
+,note="Verbal discussion"
+}
+
+@Conference{AjuJohn95
+,Author="Aju John"
+,Title="Dynamic vnodes -- Design and Implementation"
+,Booktitle="{USENIX Winter 1995}"
+,Publisher="USENIX Association"
+,Month="January"
+,Year="1995"
+,pages="11-23"
+,Address="New Orleans, LA"
+}
+
+@techreport{Slingwine95
+,author="John D. Slingwine and Paul E. McKenney"
+,title="Apparatus and Method for Achieving Reduced Overhead Mutual
+Exclusion and Maintaining Coherency in a Multiprocessor System
+Utilizing Execution History and Thread Monitoring"
+,institution="US Patent and Trademark Office"
+,address="Washington, DC"
+,year="1995"
+,number="US Patent 5,442,758 (contributed under GPL)"
+,month="August"
+}
+
+@techreport{Slingwine97
+,author="John D. Slingwine and Paul E. McKenney"
+,title="Method for maintaining data coherency using thread
+activity summaries in a multicomputer system"
+,institution="US Patent and Trademark Office"
+,address="Washington, DC"
+,year="1997"
+,number="US Patent 5,608,893 (contributed under GPL)"
+,month="March"
+}
+
+@techreport{Slingwine98
+,author="John D. Slingwine and Paul E. McKenney"
+,title="Apparatus and method for achieving reduced overhead
+mutual exclusion and maintaining coherency in a multiprocessor
+system utilizing execution history and thread monitoring"
+,institution="US Patent and Trademark Office"
+,address="Washington, DC"
+,year="1998"
+,number="US Patent 5,727,209 (contributed under GPL)"
+,month="March"
+}
+
+@Conference{McKenney98
+,Author="Paul E. McKenney and John D. Slingwine"
+,Title="Read-Copy Update: Using Execution History to Solve Concurrency
+Problems"
+,Booktitle="{Parallel and Distributed Computing and Systems}"
+,Month="October"
+,Year="1998"
+,pages="509-518"
+,Address="Las Vegas, NV"
+}
+
+@Conference{Gamsa99
+,Author="Ben Gamsa and Orran Krieger and Jonathan Appavoo and Michael Stumm"
+,Title="Tornado: Maximizing Locality and Concurrency in a Shared Memory
+Multiprocessor Operating System"
+,Booktitle="{Proceedings of the 3\textsuperscript{rd} Symposium on
+Operating System Design and Implementation}"
+,Month="February"
+,Year="1999"
+,pages="87-100"
+,Address="New Orleans, LA"
+}
+
+@techreport{Slingwine01
+,author="John D. Slingwine and Paul E. McKenney"
+,title="Apparatus and method for achieving reduced overhead
+mutual exclusion and maintaining coherency in a multiprocessor
+system utilizing execution history and thread monitoring"
+,institution="US Patent and Trademark Office"
+,address="Washington, DC"
+,year="2001"
+,number="US Patent 5,219,690 (contributed under GPL)"
+,month="April"
+}
+
+@Conference{McKenney01a
+,Author="Paul E. McKenney and Jonathan Appavoo and Andi Kleen and
+Orran Krieger and Rusty Russell and Dipankar Sarma and Maneesh Soni"
+,Title="Read-Copy Update"
+,Booktitle="{Ottawa Linux Symposium}"
+,Month="July"
+,Year="2001"
+,note="Available:
+\url{http://www.linuxsymposium.org/2001/abstracts/readcopy.php}
+\url{http://www.rdrop.com/users/paulmck/rclock/rclock_OLS.2001.05.01c.pdf}
+[Viewed June 23, 2004]"
+annotation="
+Described RCU, and presented some patches implementing and using it in
+the Linux kernel.
+"
+}
+
+@Conference{Linder02a
+,Author="Hanna Linder and Dipankar Sarma and Maneesh Soni"
+,Title="Scalability of the Directory Entry Cache"
+,Booktitle="{Ottawa Linux Symposium}"
+,Month="June"
+,Year="2002"
+,pages="289-300"
+}
+
+@Conference{McKenney02a
+,Author="Paul E. McKenney and Dipankar Sarma and
+Andrea Arcangeli and Andi Kleen and Orran Krieger and Rusty Russell"
+,Title="Read-Copy Update"
+,Booktitle="{Ottawa Linux Symposium}"
+,Month="June"
+,Year="2002"
+,pages="338-367"
+,note="Available:
+\url{http://www.linux.org.uk/~ajh/ols2002_proceedings.pdf.gz}
+[Viewed June 23, 2004]"
+}
+
+@article{Appavoo03a
+,author="J. Appavoo and K. Hui and C. A. N. Soules and R. W. Wisniewski and
+D. M. {Da Silva} and O. Krieger and M. A. Auslander and D. J. Edelsohn and
+B. Gamsa and G. R. Ganger and P. McKenney and M. Ostrowski and
+B. Rosenburg and M. Stumm and J. Xenidis"
+,title="Enabling Autonomic Behavior in Systems Software With Hot Swapping"
+,Year="2003"
+,Month="January"
+,journal="IBM Systems Journal"
+,volume="42"
+,number="1"
+,pages="60-76"
+}
+
+@Conference{Arcangeli03
+,Author="Andrea Arcangeli and Mingming Cao and Paul E. McKenney and
+Dipankar Sarma"
+,Title="Using Read-Copy Update Techniques for {System V IPC} in the
+{Linux} 2.5 Kernel"
+,Booktitle="Proceedings of the 2003 USENIX Annual Technical Conference
+(FREENIX Track)"
+,Publisher="USENIX Association"
+,year="2003"
+,month="June"
+,pages="297-310"
+}
+
+@article{McKenney03a
+,author="Paul E. McKenney"
+,title="Using {RCU} in the {Linux} 2.5 Kernel"
+,Year="2003"
+,Month="October"
+,journal="Linux Journal"
+,volume="1"
+,number="114"
+,pages="18-26"
+}
+
+@article{McKenney04a
+,author="Paul E. McKenney and Dipankar Sarma and Maneesh Soni"
+,title="Scaling dcache with {RCU}"
+,Year="2004"
+,Month="January"
+,journal="Linux Journal"
+,volume="1"
+,number="118"
+,pages="38-46"
+}
+
+@Conference{McKenney04b
+,Author="Paul E. McKenney"
+,Title="{RCU} vs. Locking Performance on Different {CPUs}"
+,Booktitle="{linux.conf.au}"
+,Month="January"
+,Year="2004"
+,Address="Adelaide, Australia"
+,note="Available:
+\url{http://www.linux.org.au/conf/2004/abstracts.html#90}
+\url{http://www.rdrop.com/users/paulmck/rclock/lockperf.2004.01.17a.pdf}
+[Viewed June 23, 2004]"
+}
+
+@phdthesis{PaulEdwardMcKenneyPhD
+,author="Paul E. McKenney"
+,title="Exploiting Deferred Destruction:
+An Analysis of Read-Copy-Update Techniques
+in Operating System Kernels"
+,school="OGI School of Science and Engineering at
+Oregon Health and Sciences University"
+,year="2004"
+}
+
+@Conference{Sarma04c
+,Author="Dipankar Sarma and Paul E. McKenney"
+,Title="Making RCU Safe for Deep Sub-Millisecond Response Realtime Applications"
+,Booktitle="Proceedings of the 2004 USENIX Annual Technical Conference
+(FREENIX Track)"
+,Publisher="USENIX Association"
+,year="2004"
+,month="June"
+,pages="182-191"
+}
--- /dev/null
+RCU on Uniprocessor Systems
+
+
+A common misconception is that, on UP systems, the call_rcu() primitive
+may immediately invoke its function, and that the synchronize_kernel
+primitive may return immediately. The basis of this misconception
+is that since there is only one CPU, it should not be necessary to
+wait for anything else to get done, since there are no other CPUs for
+anything else to be happening on. Although this approach will sort of
+work a surprising amount of the time, it is a very bad idea in general.
+This document presents two examples that demonstrate exactly how bad an
+idea this is.
+
+
+Example 1: softirq Suicide
+
+Suppose that an RCU-based algorithm scans a linked list containing
+elements A, B, and C in process context, and can delete elements from
+this same list in softirq context. Suppose that the process-context scan
+is referencing element B when it is interrupted by softirq processing,
+which deletes element B, and then invokes call_rcu() to free element B
+after a grace period.
+
+Now, if call_rcu() were to directly invoke its arguments, then upon return
+from softirq, the list scan would find itself referencing a newly freed
+element B. This situation can greatly decrease the life expectancy of
+your kernel.
+
+
+Example 2: Function-Call Fatality
+
+Of course, one could avert the suicide described in the preceding example
+by having call_rcu() directly invoke its arguments only if it was called
+from process context. However, this can fail in a similar manner.
+
+Suppose that an RCU-based algorithm again scans a linked list containing
+elements A, B, and C in process contexts, but that it invokes a function
+on each element as it is scanned. Suppose further that this function
+deletes element B from the list, then passes it to call_rcu() for deferred
+freeing. This may be a bit unconventional, but it is perfectly legal
+RCU usage, since call_rcu() must wait for a grace period to elapse.
+Therefore, in this case, allowing call_rcu() to immediately invoke
+its arguments would cause it to fail to make the fundamental guarantee
+underlying RCU, namely that call_rcu() defers invoking its arguments until
+all RCU read-side critical sections currently executing have completed.
+
+Quick Quiz: why is it -not- legal to invoke synchronize_kernel() in
+this case?
+
+
+Summary
+
+Permitting call_rcu() to immediately invoke its arguments or permitting
+synchronize_kernel() to immediately return breaks RCU, even on a UP system.
+So do not do it! Even on a UP system, the RCU infrastructure -must-
+respect grace periods.
+
+
+Answer to Quick Quiz
+
+The calling function is scanning an RCU-protected linked list, and
+is therefore within an RCU read-side critical section. Therefore,
+the called function has been invoked within an RCU read-side critical
+section, and is not permitted to block.
--- /dev/null
+Using RCU to Protect Read-Mostly Arrays
+
+
+Although RCU is more commonly used to protect linked lists, it can
+also be used to protect arrays. Three situations are as follows:
+
+1. Hash Tables
+
+2. Static Arrays
+
+3. Resizeable Arrays
+
+Each of these situations are discussed below.
+
+
+Situation 1: Hash Tables
+
+Hash tables are often implemented as an array, where each array entry
+has a linked-list hash chain. Each hash chain can be protected by RCU
+as described in the listRCU.txt document. This approach also applies
+to other array-of-list situations, such as radix trees.
+
+
+Situation 2: Static Arrays
+
+Static arrays, where the data (rather than a pointer to the data) is
+located in each array element, and where the array is never resized,
+have not been used with RCU. Rik van Riel recommends using seqlock in
+this situation, which would also have minimal read-side overhead as long
+as updates are rare.
+
+Quick Quiz: Why is it so important that updates be rare when
+ using seqlock?
+
+
+Situation 3: Resizeable Arrays
+
+Use of RCU for resizeable arrays is demonstrated by the grow_ary()
+function used by the System V IPC code. The array is used to map from
+semaphore, message-queue, and shared-memory IDs to the data structure
+that represents the corresponding IPC construct. The grow_ary()
+function does not acquire any locks; instead its caller must hold the
+ids->sem semaphore.
+
+The grow_ary() function, shown below, does some limit checks, allocates a
+new ipc_id_ary, copies the old to the new portion of the new, initializes
+the remainder of the new, updates the ids->entries pointer to point to
+the new array, and invokes ipc_rcu_putref() to free up the old array.
+Note that rcu_assign_pointer() is used to update the ids->entries pointer,
+which includes any memory barriers required on whatever architecture
+you are running on.
+
+ static int grow_ary(struct ipc_ids* ids, int newsize)
+ {
+ struct ipc_id_ary* new;
+ struct ipc_id_ary* old;
+ int i;
+ int size = ids->entries->size;
+
+ if(newsize > IPCMNI)
+ newsize = IPCMNI;
+ if(newsize <= size)
+ return newsize;
+
+ new = ipc_rcu_alloc(sizeof(struct kern_ipc_perm *)*newsize +
+ sizeof(struct ipc_id_ary));
+ if(new == NULL)
+ return size;
+ new->size = newsize;
+ memcpy(new->p, ids->entries->p,
+ sizeof(struct kern_ipc_perm *)*size +
+ sizeof(struct ipc_id_ary));
+ for(i=size;i<newsize;i++) {
+ new->p[i] = NULL;
+ }
+ old = ids->entries;
+
+ /*
+ * Use rcu_assign_pointer() to make sure the memcpyed
+ * contents of the new array are visible before the new
+ * array becomes visible.
+ */
+ rcu_assign_pointer(ids->entries, new);
+
+ ipc_rcu_putref(old);
+ return newsize;
+ }
+
+The ipc_rcu_putref() function decrements the array's reference count
+and then, if the reference count has dropped to zero, uses call_rcu()
+to free the array after a grace period has elapsed.
+
+The array is traversed by the ipc_lock() function. This function
+indexes into the array under the protection of rcu_read_lock(),
+using rcu_dereference() to pick up the pointer to the array so
+that it may later safely be dereferenced -- memory barriers are
+required on the Alpha CPU. Since the size of the array is stored
+with the array itself, there can be no array-size mismatches, so
+a simple check suffices. The pointer to the structure corresponding
+to the desired IPC object is placed in "out", with NULL indicating
+a non-existent entry. After acquiring "out->lock", the "out->deleted"
+flag indicates whether the IPC object is in the process of being
+deleted, and, if not, the pointer is returned.
+
+ struct kern_ipc_perm* ipc_lock(struct ipc_ids* ids, int id)
+ {
+ struct kern_ipc_perm* out;
+ int lid = id % SEQ_MULTIPLIER;
+ struct ipc_id_ary* entries;
+
+ rcu_read_lock();
+ entries = rcu_dereference(ids->entries);
+ if(lid >= entries->size) {
+ rcu_read_unlock();
+ return NULL;
+ }
+ out = entries->p[lid];
+ if(out == NULL) {
+ rcu_read_unlock();
+ return NULL;
+ }
+ spin_lock(&out->lock);
+
+ /* ipc_rmid() may have already freed the ID while ipc_lock
+ * was spinning: here verify that the structure is still valid
+ */
+ if (out->deleted) {
+ spin_unlock(&out->lock);
+ rcu_read_unlock();
+ return NULL;
+ }
+ return out;
+ }
+
+
+Answer to Quick Quiz:
+
+ The reason that it is important that updates be rare when
+ using seqlock is that frequent updates can livelock readers.
+ One way to avoid this problem is to assign a seqlock for
+ each array entry rather than to the entire array.
--- /dev/null
+Review Checklist for RCU Patches
+
+
+This document contains a checklist for producing and reviewing patches
+that make use of RCU. Violating any of the rules listed below will
+result in the same sorts of problems that leaving out a locking primitive
+would cause. This list is based on experiences reviewing such patches
+over a rather long period of time, but improvements are always welcome!
+
+0. Is RCU being applied to a read-mostly situation? If the data
+ structure is updated more than about 10% of the time, then
+ you should strongly consider some other approach, unless
+ detailed performance measurements show that RCU is nonetheless
+ the right tool for the job.
+
+ The other exception would be where performance is not an issue,
+ and RCU provides a simpler implementation. An example of this
+ situation is the dynamic NMI code in the Linux 2.6 kernel,
+ at least on architectures where NMIs are rare.
+
+1. Does the update code have proper mutual exclusion?
+
+ RCU does allow -readers- to run (almost) naked, but -writers- must
+ still use some sort of mutual exclusion, such as:
+
+ a. locking,
+ b. atomic operations, or
+ c. restricting updates to a single task.
+
+ If you choose #b, be prepared to describe how you have handled
+ memory barriers on weakly ordered machines (pretty much all of
+ them -- even x86 allows reads to be reordered), and be prepared
+ to explain why this added complexity is worthwhile. If you
+ choose #c, be prepared to explain how this single task does not
+ become a major bottleneck on big multiprocessor machines.
+
+2. Do the RCU read-side critical sections make proper use of
+ rcu_read_lock() and friends? These primitives are needed
+ to suppress preemption (or bottom halves, in the case of
+ rcu_read_lock_bh()) in the read-side critical sections,
+ and are also an excellent aid to readability.
+
+3. Does the update code tolerate concurrent accesses?
+
+ The whole point of RCU is to permit readers to run without
+ any locks or atomic operations. This means that readers will
+ be running while updates are in progress. There are a number
+ of ways to handle this concurrency, depending on the situation:
+
+ a. Make updates appear atomic to readers. For example,
+ pointer updates to properly aligned fields will appear
+ atomic, as will individual atomic primitives. Operations
+ performed under a lock and sequences of multiple atomic
+ primitives will -not- appear to be atomic.
+
+ This is almost always the best approach.
+
+ b. Carefully order the updates and the reads so that
+ readers see valid data at all phases of the update.
+ This is often more difficult than it sounds, especially
+ given modern CPUs' tendency to reorder memory references.
+ One must usually liberally sprinkle memory barriers
+ (smp_wmb(), smp_rmb(), smp_mb()) through the code,
+ making it difficult to understand and to test.
+
+ It is usually better to group the changing data into
+ a separate structure, so that the change may be made
+ to appear atomic by updating a pointer to reference
+ a new structure containing updated values.
+
+4. Weakly ordered CPUs pose special challenges. Almost all CPUs
+ are weakly ordered -- even i386 CPUs allow reads to be reordered.
+ RCU code must take all of the following measures to prevent
+ memory-corruption problems:
+
+ a. Readers must maintain proper ordering of their memory
+ accesses. The rcu_dereference() primitive ensures that
+ the CPU picks up the pointer before it picks up the data
+ that the pointer points to. This really is necessary
+ on Alpha CPUs. If you don't believe me, see:
+
+ http://www.openvms.compaq.com/wizard/wiz_2637.html
+
+ The rcu_dereference() primitive is also an excellent
+ documentation aid, letting the person reading the code
+ know exactly which pointers are protected by RCU.
+
+ The rcu_dereference() primitive is used by the various
+ "_rcu()" list-traversal primitives, such as the
+ list_for_each_entry_rcu().
+
+ b. If the list macros are being used, the list_del_rcu(),
+ list_add_tail_rcu(), and list_del_rcu() primitives must
+ be used in order to prevent weakly ordered machines from
+ misordering structure initialization and pointer planting.
+ Similarly, if the hlist macros are being used, the
+ hlist_del_rcu() and hlist_add_head_rcu() primitives
+ are required.
+
+ c. Updates must ensure that initialization of a given
+ structure happens before pointers to that structure are
+ publicized. Use the rcu_assign_pointer() primitive
+ when publicizing a pointer to a structure that can
+ be traversed by an RCU read-side critical section.
+
+ [The rcu_assign_pointer() primitive is in process.]
+
+5. If call_rcu(), or a related primitive such as call_rcu_bh(),
+ is used, the callback function must be written to be called
+ from softirq context. In particular, it cannot block.
+
+6. Since synchronize_kernel() blocks, it cannot be called from
+ any sort of irq context.
+
+7. If the updater uses call_rcu(), then the corresponding readers
+ must use rcu_read_lock() and rcu_read_unlock(). If the updater
+ uses call_rcu_bh(), then the corresponding readers must use
+ rcu_read_lock_bh() and rcu_read_unlock_bh(). Mixing things up
+ will result in confusion and broken kernels.
+
+ One exception to this rule: rcu_read_lock() and rcu_read_unlock()
+ may be substituted for rcu_read_lock_bh() and rcu_read_unlock_bh()
+ in cases where local bottom halves are already known to be
+ disabled, for example, in irq or softirq context. Commenting
+ such cases is a must, of course! And the jury is still out on
+ whether the increased speed is worth it.
+
+8. Although synchronize_kernel() is a bit slower than is call_rcu(),
+ it usually results in simpler code. So, unless update performance
+ is important or the updaters cannot block, synchronize_kernel()
+ should be used in preference to call_rcu().
+
+9. All RCU list-traversal primitives, which include
+ list_for_each_rcu(), list_for_each_entry_rcu(),
+ list_for_each_continue_rcu(), and list_for_each_safe_rcu(),
+ must be within an RCU read-side critical section. RCU
+ read-side critical sections are delimited by rcu_read_lock()
+ and rcu_read_unlock(), or by similar primitives such as
+ rcu_read_lock_bh() and rcu_read_unlock_bh().
+
+ Use of the _rcu() list-traversal primitives outside of an
+ RCU read-side critical section causes no harm other than
+ a slight performance degradation on Alpha CPUs and some
+ confusion on the part of people trying to read the code.
+
+ Another way of thinking of this is "If you are holding the
+ lock that prevents the data structure from changing, why do
+ you also need RCU-based protection?" That said, there may
+ well be situations where use of the _rcu() list-traversal
+ primitives while the update-side lock is held results in
+ simpler and more maintainable code. The jury is still out
+ on this question.
+
+10. Conversely, if you are in an RCU read-side critical section,
+ you -must- use the "_rcu()" variants of the list macros.
+ Failing to do so will break Alpha and confuse people reading
+ your code.
--- /dev/null
+Using RCU to Protect Read-Mostly Linked Lists
+
+
+One of the best applications of RCU is to protect read-mostly linked lists
+("struct list_head" in list.h). One big advantage of this approach
+is that all of the required memory barriers are included for you in
+the list macros. This document describes several applications of RCU,
+with the best fits first.
+
+
+Example 1: Read-Side Action Taken Outside of Lock, No In-Place Updates
+
+The best applications are cases where, if reader-writer locking were
+used, the read-side lock would be dropped before taking any action
+based on the results of the search. The most celebrated example is
+the routing table. Because the routing table is tracking the state of
+equipment outside of the computer, it will at times contain stale data.
+Therefore, once the route has been computed, there is no need to hold
+the routing table static during transmission of the packet. After all,
+you can hold the routing table static all you want, but that won't keep
+the external Internet from changing, and it is the state of the external
+Internet that really matters. In addition, routing entries are typically
+added or deleted, rather than being modified in place.
+
+A straightforward example of this use of RCU may be found in the
+system-call auditing support. For example, a reader-writer locked
+implementation of audit_filter_task() might be as follows:
+
+ static enum audit_state audit_filter_task(struct task_struct *tsk)
+ {
+ struct audit_entry *e;
+ enum audit_state state;
+
+ read_lock(&auditsc_lock);
+ list_for_each_entry(e, &audit_tsklist, list) {
+ if (audit_filter_rules(tsk, &e->rule, NULL, &state)) {
+ read_unlock(&auditsc_lock);
+ return state;
+ }
+ }
+ read_unlock(&auditsc_lock);
+ return AUDIT_BUILD_CONTEXT;
+ }
+
+Here the list is searched under the lock, but the lock is dropped before
+the corresponding value is returned. By the time that this value is acted
+on, the list may well have been modified. This makes sense, since if
+you are turning auditing off, it is OK to audit a few extra system calls.
+
+This means that RCU can be easily applied to the read side, as follows:
+
+ static enum audit_state audit_filter_task(struct task_struct *tsk)
+ {
+ struct audit_entry *e;
+ enum audit_state state;
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(e, &audit_tsklist, list) {
+ if (audit_filter_rules(tsk, &e->rule, NULL, &state)) {
+ rcu_read_unlock();
+ return state;
+ }
+ }
+ rcu_read_unlock();
+ return AUDIT_BUILD_CONTEXT;
+ }
+
+The read_lock() and read_unlock() calls have become rcu_read_lock()
+and rcu_read_unlock(), respectively, and the list_for_each_entry() has
+become list_for_each_entry_rcu(). The _rcu() list-traversal primitives
+insert the read-side memory barriers that are required on DEC Alpha CPUs.
+
+The changes to the update side are also straightforward. A reader-writer
+lock might be used as follows for deletion and insertion:
+
+ static inline int audit_del_rule(struct audit_rule *rule,
+ struct list_head *list)
+ {
+ struct audit_entry *e;
+
+ write_lock(&auditsc_lock);
+ list_for_each_entry(e, list, list) {
+ if (!audit_compare_rule(rule, &e->rule)) {
+ list_del(&e->list);
+ call_rcu(&e->rcu, audit_free_rule, e);
+ return 0;
+ }
+ }
+ write_unlock(&auditsc_lock);
+ return -EFAULT; /* No matching rule */
+ }
+
+ static inline int audit_add_rule(struct audit_entry *entry,
+ struct list_head *list)
+ {
+ write_lock(&auditsc_lock);
+ if (entry->rule.flags & AUDIT_PREPEND) {
+ entry->rule.flags &= ~AUDIT_PREPEND;
+ list_add(&entry->list, list);
+ } else {
+ list_add_tail(&entry->list, list);
+ }
+ write_unlock(&auditsc_lock);
+ return 0;
+ }
+
+Following are the RCU equivalents for these two functions:
+
+ static inline int audit_del_rule(struct audit_rule *rule,
+ struct list_head *list)
+ {
+ struct audit_entry *e;
+
+ /* Do not use the _rcu iterator here, since this is the only
+ * deletion routine. */
+ list_for_each_entry(e, list, list) {
+ if (!audit_compare_rule(rule, &e->rule)) {
+ list_del_rcu(&e->list);
+ call_rcu(&e->rcu, audit_free_rule, e);
+ return 0;
+ }
+ }
+ return -EFAULT; /* No matching rule */
+ }
+
+ static inline int audit_add_rule(struct audit_entry *entry,
+ struct list_head *list)
+ {
+ if (entry->rule.flags & AUDIT_PREPEND) {
+ entry->rule.flags &= ~AUDIT_PREPEND;
+ list_add_rcu(&entry->list, list);
+ } else {
+ list_add_tail_rcu(&entry->list, list);
+ }
+ return 0;
+ }
+
+Normally, the write_lock() and write_unlock() would be replaced by
+a spin_lock() and a spin_unlock(), but in this case, all callers hold
+audit_netlink_sem, so no additional locking is required. The auditsc_lock
+can therefore be eliminated, since use of RCU eliminates the need for
+writers to exclude readers.
+
+The list_del(), list_add(), and list_add_tail() primitives have been
+replaced by list_del_rcu(), list_add_rcu(), and list_add_tail_rcu().
+The _rcu() list-manipulation primitives add memory barriers that are
+needed on weakly ordered CPUs (most of them!).
+
+So, when readers can tolerate stale data and when entries are either added
+or deleted, without in-place modification, it is very easy to use RCU!
+
+
+Example 2: Handling In-Place Updates
+
+The system-call auditing code does not update auditing rules in place.
+However, if it did, reader-writer-locked code to do so might look as
+follows (presumably, the field_count is only permitted to decrease,
+otherwise, the added fields would need to be filled in):
+
+ static inline int audit_upd_rule(struct audit_rule *rule,
+ struct list_head *list,
+ __u32 newaction,
+ __u32 newfield_count)
+ {
+ struct audit_entry *e;
+ struct audit_newentry *ne;
+
+ write_lock(&auditsc_lock);
+ list_for_each_entry(e, list, list) {
+ if (!audit_compare_rule(rule, &e->rule)) {
+ e->rule.action = newaction;
+ e->rule.file_count = newfield_count;
+ write_unlock(&auditsc_lock);
+ return 0;
+ }
+ }
+ write_unlock(&auditsc_lock);
+ return -EFAULT; /* No matching rule */
+ }
+
+The RCU version creates a copy, updates the copy, then replaces the old
+entry with the newly updated entry. This sequence of actions, allowing
+concurrent reads while doing a copy to perform an update, is what gives
+RCU ("read-copy update") its name. The RCU code is as follows:
+
+ static inline int audit_upd_rule(struct audit_rule *rule,
+ struct list_head *list,
+ __u32 newaction,
+ __u32 newfield_count)
+ {
+ struct audit_entry *e;
+ struct audit_newentry *ne;
+
+ list_for_each_entry(e, list, list) {
+ if (!audit_compare_rule(rule, &e->rule)) {
+ ne = kmalloc(sizeof(*entry), GFP_ATOMIC);
+ if (ne == NULL)
+ return -ENOMEM;
+ audit_copy_rule(&ne->rule, &e->rule);
+ ne->rule.action = newaction;
+ ne->rule.file_count = newfield_count;
+ list_add_rcu(ne, e);
+ list_del(e);
+ call_rcu(&e->rcu, audit_free_rule, e);
+ return 0;
+ }
+ }
+ return -EFAULT; /* No matching rule */
+ }
+
+Again, this assumes that the caller holds audit_netlink_sem. Normally,
+the reader-writer lock would become a spinlock in this sort of code.
+
+
+Example 3: Eliminating Stale Data
+
+The auditing examples above tolerate stale data, as do most algorithms
+that are tracking external state. Because there is a delay from the
+time the external state changes before Linux becomes aware of the change,
+additional RCU-induced staleness is normally not a problem.
+
+However, there are many examples where stale data cannot be tolerated.
+One example in the Linux kernel is the System V IPC (see the ipc_lock()
+function in ipc/util.c). This code checks a "deleted" flag under a
+per-entry spinlock, and, if the "deleted" flag is set, pretends that the
+entry does not exist. For this to be helpful, the search function must
+return holding the per-entry spinlock, as ipc_lock() does in fact do.
+
+Quick Quiz: Why does the search function need to return holding the
+per-entry lock for this deleted-flag technique to be helpful?
+
+If the system-call audit module were to ever need to reject stale data,
+one way to accomplish this would be to add a "deleted" flag and a "lock"
+spinlock to the audit_entry structure, and modify audit_filter_task()
+as follows:
+
+ static enum audit_state audit_filter_task(struct task_struct *tsk)
+ {
+ struct audit_entry *e;
+ enum audit_state state;
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(e, &audit_tsklist, list) {
+ if (audit_filter_rules(tsk, &e->rule, NULL, &state)) {
+ spin_lock(&e->lock);
+ if (e->deleted) {
+ spin_unlock(&e->lock);
+ rcu_read_unlock();
+ return AUDIT_BUILD_CONTEXT;
+ }
+ rcu_read_unlock();
+ return state;
+ }
+ }
+ rcu_read_unlock();
+ return AUDIT_BUILD_CONTEXT;
+ }
+
+Note that this example assumes that entries are only added and deleted.
+Additional mechanism is required to deal correctly with the
+update-in-place performed by audit_upd_rule(). For one thing,
+audit_upd_rule() would need additional memory barriers to ensure
+that the list_add_rcu() was really executed before the list_del_rcu().
+
+The audit_del_rule() function would need to set the "deleted"
+flag under the spinlock as follows:
+
+ static inline int audit_del_rule(struct audit_rule *rule,
+ struct list_head *list)
+ {
+ struct audit_entry *e;
+
+ /* Do not use the _rcu iterator here, since this is the only
+ * deletion routine. */
+ list_for_each_entry(e, list, list) {
+ if (!audit_compare_rule(rule, &e->rule)) {
+ spin_lock(&e->lock);
+ list_del_rcu(&e->list);
+ e->deleted = 1;
+ spin_unlock(&e->lock);
+ call_rcu(&e->rcu, audit_free_rule, e);
+ return 0;
+ }
+ }
+ return -EFAULT; /* No matching rule */
+ }
+
+
+Summary
+
+Read-mostly list-based data structures that can tolerate stale data are
+the most amenable to use of RCU. The simplest case is where entries are
+either added or deleted from the data structure (or atomically modified
+in place), but non-atomic in-place modifications can be handled by making
+a copy, updating the copy, then replacing the original with the copy.
+If stale data cannot be tolerated, then a "deleted" flag may be used
+in conjunction with a per-entry spinlock in order to allow the search
+function to reject newly deleted data.
+
+
+Answer to Quick Quiz
+
+If the search function drops the per-entry lock before returning, then
+the caller will be processing stale data in any case. If it is really
+OK to be processing stale data, then you don't need a "deleted" flag.
+If processing stale data really is a problem, then you need to hold the
+per-entry lock across all of the code that uses the value looked up.
--- /dev/null
+RCU Concepts
+
+
+The basic idea behind RCU (read-copy update) is to split destructive
+operations into two parts, one that prevents anyone from seeing the data
+item being destroyed, and one that actually carries out the destruction.
+A "grace period" must elapse between the two parts, and this grace period
+must be long enough that any readers accessing the item being deleted have
+since dropped their references. For example, an RCU-protected deletion
+from a linked list would first remove the item from the list, wait for
+a grace period to elapse, then free the element. See the listRCU.txt
+file for more information on using RCU with linked lists.
+
+
+Frequently Asked Questions
+
+o Why would anyone want to use RCU?
+
+ The advantage of RCU's two-part approach is that RCU readers need
+ not acquire any locks, perform any atomic instructions, write to
+ shared memory, or (on CPUs other than Alpha) execute any memory
+ barriers. The fact that these operations are quite expensive
+ on modern CPUs is what gives RCU its performance advantages
+ in read-mostly situations. The fact that RCU readers need not
+ acquire locks can also greatly simplify deadlock-avoidance code.
+
+o How can the updater tell when a grace period has completed
+ if the RCU readers give no indication when they are done?
+
+ Just as with spinlocks, RCU readers are not permitted to
+ block, switch to user-mode execution, or enter the idle loop.
+ Therefore, as soon as a CPU is seen passing through any of these
+ three states, we know that that CPU has exited any previous RCU
+ read-side critical sections. So, if we remove an item from a
+ linked list, and then wait until all CPUs have switched context,
+ executed in user mode, or executed in the idle loop, we can
+ safely free up that item.
+
+o If I am running on a uniprocessor kernel, which can only do one
+ thing at a time, why should I wait for a grace period?
+
+ See the UP.txt file in this directory.
+
+o How can I see where RCU is currently used in the Linux kernel?
+
+ Search for "rcu_read_lock", "call_rcu", and "synchronize_kernel".
+
+o What guidelines should I follow when writing code that uses RCU?
+
+ See the checklist.txt file in this directory.
+
+o Why the name "RCU"?
+
+ "RCU" stands for "read-copy update". The file listRCU.txt has
+ more information on where this name came from, search for
+ "read-copy update" to find it.
+
+o I hear that RCU is patented? What is with that?
+
+ Yes, it is. There are several known patents related to RCU,
+ search for the string "Patent" in RTFP.txt to find them.
+ Of these, one was allowed to lapse by the assignee, and the
+ others have been contributed to the Linux kernel under GPL.
+
+o Where can I find more information on RCU?
+
+ See the RTFP.txt file in this directory.
--- /dev/null
+
+-------------------------------------------------------------------------
+Release Notes for Linux on Intel's IXP2000 Network Processor
+
+Maintained by Deepak Saxena <dsaxena@plexity.net>
+-------------------------------------------------------------------------
+
+1. Overview
+
+Intel's IXP2000 family of NPUs (IXP2400, IXP2800, IXP2850) is designed
+for high-performance network applications such high-availability
+telecom systems. In addition to an XScale core, it contains up to 8
+"MicroEngines" that run special code, several high-end networking
+interfaces (UTOPIA, SPI, etc), a PCI host bridge, one serial port,
+flash interface, and some other odds and ends. For more information, see:
+
+http://developer.intel.com/design/network/products/npfamily/ixp2xxx.htm
+
+2. Linux Support
+
+Linux currently supports the following features on the IXP2000 NPUS:
+
+- On-chip serial
+- PCI
+- Flash (MTD/JFFS2)
+- I2C through GPIO
+- Timers (watchdog, OS)
+
+That is about all we can support under Linux ATM b/c the core networking
+components of the chip are accessed via Intel's closed source SDK.
+Please contact Intel directly on issues with using those. There is
+also a mailing list run by some folks at Princeton University that might
+be of helpful: https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
+
+WHATEVER YOU DO, DO NOT POST EMAIL TO THE LINUX-ARM OR LINUX-ARM-KERNEL
+MAILINNG LISTS REGARDING THE INTEL SDK.
+
+3. Supported Platforms
+
+- Intel IXDP2400 Reference Platform
+- Intel IXDP2800 Reference Platform
+- Intel IXDP2401 Reference Platform
+- Intel IXDP2801 Reference Platform
+- RadiSys ENP-2611
+
+4. Usage Notes
+
+- The IXP2000 platforms ususally have rather complex PCI bus topologies
+ with large memory space requirements. In addition, b/c of the way the
+ Intel SDK is designed, devices are enumerated in a vert specific
+ way. B/c of this this, we use "pci=firmware" option in the kernel
+ command line so that we do not re-enumerate the bus.
+
+- IXDP2x01 systems have variable clock tick rates that we cannot determine
+ via HW registers. The "ixdp2x01_clk=XXX" cmd line options allows you
+ to pass the clock rate to the board port.
+
+5. Thanks
+
+The IXP2000 work has been funded by Intel Corp. and MontaVista Software, Inc.
+
+The following people have contributed patches/comments/etc:
+
+Naeem F. Afzal
+Lennert Buytenhek
+Jeffrey Daly
+
+-------------------------------------------------------------------------
+Last Update: 8/09/2004
--- /dev/null
+ Simtec Electronics EB2410ITX (BAST)
+ ===================================
+
+ http://www.simtec.co.uk/products/EB2410ITX/
+
+Introduction
+------------
+
+ The EB2410ITX is a S3C2410 based development board with a variety of
+ peripherals and expansion connectors. This board is also known by
+ the shortened name of Bast.
+
+
+Configuration
+-------------
+
+ To set the default configuration, use `make bast_defconfig` which
+ supports the commonly used features of this board
+
+
+Support
+-------
+
+ Official support information can be found on the Simtec Electronics
+ website, at the product page http://www.simtec.co.uk/products/EB2410ITX/
+ and http://www.simtec.co.uk/products/EB2410ITX/resources.html
+
+
+MTD
+---
+
+ The NAND and NOR onboard are currently supported in the linux-mtd cvs,
+ and are awaiting merge in the mainline. see the linux-mtd project at
+ http://www.linux-mtd.infradead.org/ for more information.
+
+
+IDE
+---
+
+ Both onboard IDE ports are supported, however there is no support for
+ changing speed of devices, PIO Mode 4 capable drives should be used.
+
+
+(c) 2004 Ben Dooks, Simtec Electronics
--- /dev/null
+ S3C2410 GPIO Control
+ ====================
+
+Introduction
+------------
+
+ The s3c2410 kernel provides an interface to configure and
+ manipulate the state of the GPIO pins, and find out other
+ information about them.
+
+ There are a number of conditions attached to the configuration
+ of the s3c2410 GPIO system, please read the Samsung provided
+ data-sheet/users manual to find out the complete list.
+
+
+Headers
+-------
+
+ See include/asm-arm/arch-s3c2410/regs-gpio.h for the list
+ of GPIO pins, and the configuration values for them. This
+ is included by using #include <asm/arch/regs-gpio.h>
+
+ The GPIO management functions are defined in the hardware
+ header include/asm-arm/arch-s3c2410/hardware.h which can be
+ included by #include <asm/arch/hardware.h>
+
+ A useful ammount of documentation can be found in the hardware
+ header on how the GPIO functions (and others) work.
+
+ Whilst a number of these functions do make some checks on what
+ is passed to them, for speed of use, they may not always ensure
+ that the user supplied data to them is correct.
+
+
+PIN Numbers
+-----------
+
+ Each pin has an unique number associated with it in regs-gpio.h,
+ eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell
+ the GPIO functions which pin is to be used.
+
+
+Configuring a pin
+-----------------
+
+ The following function allows the configuration of a given pin to
+ be changed.
+
+ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+
+ Eg:
+
+ s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
+ s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
+
+ which would turn GPA0 into the lowest Address line A0, and set
+ GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line.
+
+
+Reading the current configuration
+---------------------------------
+
+ The current configuration of a pin can be read by using:
+
+ s3c2410_gpio_getcfg(unsigned int pin);
+
+ The return value will be from the same set of values which can be
+ passed to s3c2410_gpio_cfgpin().
+
+
+Configuring a pull-up resistor
+------------------------------
+
+ A large proportion of the GPIO pins on the S3C2410 can have weak
+ pull-up resistors enabled. This can be configured by the following
+ function:
+
+ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+
+ Where the to value is zero to set the pull-up off, and 1 to enable
+ the specified pull-up. Any other values are currently undefined.
+
+
+Getting the state of a PIN
+--------------------------
+
+ The state of a pin can be read by using the function:
+
+ unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+ This will return either zero or non-zero. Do not count on this
+ function returning 1 if the pin is set.
+
+
+Setting the state of a PIN
+--------------------------
+
+ The value an pin is outputing can be modified by using the following:
+
+ void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+
+ Which sets the given pin to the value. Use 0 to write 0, and 1 to
+ set the output to 1.
+
+
+Getting the IRQ number associated with a PIN
+--------------------------------------------
+
+ The following function can map the given pin number to an IRQ
+ number to pass to the IRQ system.
+
+ int s3c2410_gpio_getirq(unsigned int pin);
+
+ Note, not all pins have an IRQ.
+
+
+Authour
+-------
+
+
+Ben Dooks, 03 October 2004
+(c) 2004 Ben Dooks, Simtec Electronics
--- /dev/null
+ S3C24XX ARM Linux Overview
+ ==========================
+
+
+
+Introduction
+------------
+
+ The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
+ by the 's3c2410' architecture of ARM Linux. Currently the S3C2410 is
+ the only supported CPU in this range.
+
+
+Configuration
+-------------
+
+ A generic S3C2410 configuration is provided, and can be used as the
+ default by `make s3c2410_defconfig`. This configuration has support
+ for all the machines, and the commonly used features on them.
+
+ Certain machines may have their own default configurations as well,
+ please check the machine specific documentation.
+
+
+Machines
+--------
+
+ The currently supported machines are as follows:
+
+ Simtec Electronics EB2410ITX (BAST)
+
+ A general purpose development board, see EB2410ITX.txt for further
+ details
+
+ Samsung SMDK2410
+
+ Samsung's own development board, geared for PDA work.
+
+ Thorcom VR1000
+
+ Custom embedded board
+
+ HP IPAQ 1940
+
+ Handheld (IPAQ), available in several varieties
+
+
+NAND
+----
+
+ The current kernels do not have direct support for the NAND
+ controller, the latest linux-mtd CVS has support for this.
+ See http://www.linux-mtd.infradead.org/
+
+
+Serial
+------
+
+ The s3c2410 serial driver provides support for the internal
+ serial ports. These devices appear as /dev/ttySAC0 through 3.
+
+ To create device nodes for these, use the following commands
+
+ mknod ttySAC0 c 204 64
+ mknod ttySAC1 c 204 65
+ mknod ttySAC2 c 204 66
+
+
+GPIO
+----
+
+ The core contains support for manipulating the GPIO, see the
+ documentation in GPIO.txt in the same directory as this file.
+
+
+Clock Management
+----------------
+
+ The core provides the interface defined in the header file
+ include/asm-arm/hardware/clock.h, to allow control over the
+ various clock units
+
+
+Port Contributors
+-----------------
+
+ Ben Dooks
+ Vincent Sanders
+ Herbert Potzl
+ Arnaud Patard
+ Roc Wu
+
+
+Document Author
+---------------
+
+Ben Dooks, (c) 2004 Simtec Electronics
--- /dev/null
+
+ Linux I2O Support (c) Copyright 1999 Red Hat Software
+ and others.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ as published by the Free Software Foundation; either version
+ 2 of the License, or (at your option) any later version.
+
+AUTHORS (so far)
+
+Alan Cox, Building Number Three Ltd.
+ Core code, SCSI and Block OSMs
+
+Steve Ralston, LSI Logic Corp.
+ Debugging SCSI and Block OSM
+
+Deepak Saxena, Intel Corp.
+ Various core/block extensions
+ /proc interface, bug fixes
+ Ioctl interfaces for control
+ Debugging LAN OSM
+
+Philip Rumpf
+ Fixed assorted dumb SMP locking bugs
+
+Juha Sievanen, University of Helsinki Finland
+ LAN OSM code
+ /proc interface to LAN class
+ Bug fixes
+ Core code extensions
+
+Auvo Häkkinen, University of Helsinki Finland
+ LAN OSM code
+ /Proc interface to LAN class
+ Bug fixes
+ Core code extensions
+
+Taneli Vähäkangas, University of Helsinki Finland
+ Fixes to i2o_config
+
+CREDITS
+
+ This work was made possible by
+
+Red Hat Software
+ Funding for the Building #3 part of the project
+
+Symbios Logic (Now LSI)
+ Host adapters, hints, known to work platforms when I hit
+ compatibility problems
+
+BoxHill Corporation
+ Loan of initial FibreChannel disk array used for development work.
+
+European Comission
+ Funding the work done by the University of Helsinki
+
+SysKonnect
+ Loan of FDDI and Gigabit Ethernet cards
+
+ASUSTeK
+ Loan of I2O motherboard
--- /dev/null
+
+Linux I2O User Space Interface
+rev 0.3 - 04/20/99
+
+=============================================================================
+Originally written by Deepak Saxena(deepak@plexity.net)
+Currently maintained by Deepak Saxena(deepak@plexity.net)
+=============================================================================
+
+I. Introduction
+
+The Linux I2O subsystem provides a set of ioctl() commands that can be
+utilized by user space applications to communicate with IOPs and devices
+on individual IOPs. This document defines the specific ioctl() commands
+that are available to the user and provides examples of their uses.
+
+This document assumes the reader is familiar with or has access to the
+I2O specification as no I2O message parameters are outlined. For information
+on the specification, see http://www.i2osig.org
+
+This document and the I2O user space interface are currently maintained
+by Deepak Saxena. Please send all comments, errata, and bug fixes to
+deepak@csociety.purdue.edu
+
+II. IOP Access
+
+Access to the I2O subsystem is provided through the device file named
+/dev/i2o/ctl. This file is a character file with major number 10 and minor
+number 166. It can be created through the following command:
+
+ mknod /dev/i2o/ctl c 10 166
+
+III. Determining the IOP Count
+
+ SYNOPSIS
+
+ ioctl(fd, I2OGETIOPS, int *count);
+
+ u8 count[MAX_I2O_CONTROLLERS];
+
+ DESCRIPTION
+
+ This function returns the system's active IOP table. count should
+ point to a buffer containing MAX_I2O_CONTROLLERS entries. Upon
+ returning, each entry will contain a non-zero value if the given
+ IOP unit is active, and NULL if it is inactive or non-existent.
+
+ RETURN VALUE.
+
+ Returns 0 if no errors occur, and -1 otherwise. If an error occurs,
+ errno is set appropriately:
+
+ EFAULT Invalid user space pointer was passed
+
+IV. Getting Hardware Resource Table
+
+ SYNOPSIS
+
+ ioctl(fd, I2OHRTGET, struct i2o_cmd_hrt *hrt);
+
+ struct i2o_cmd_hrtlct
+ {
+ u32 iop; /* IOP unit number */
+ void *resbuf; /* Buffer for result */
+ u32 *reslen; /* Buffer length in bytes */
+ };
+
+ DESCRIPTION
+
+ This function returns the Hardware Resource Table of the IOP specified
+ by hrt->iop in the buffer pointed to by hrt->resbuf. The actual size of
+ the data is written into *(hrt->reslen).
+
+ RETURNS
+
+ This function returns 0 if no errors occur. If an error occurs, -1
+ is returned and errno is set appropriately:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ENOBUFS Buffer not large enough. If this occurs, the required
+ buffer length is written into *(hrt->reslen)
+
+V. Getting Logical Configuration Table
+
+ SYNOPSIS
+
+ ioctl(fd, I2OLCTGET, struct i2o_cmd_lct *lct);
+
+ struct i2o_cmd_hrtlct
+ {
+ u32 iop; /* IOP unit number */
+ void *resbuf; /* Buffer for result */
+ u32 *reslen; /* Buffer length in bytes */
+ };
+
+ DESCRIPTION
+
+ This function returns the Logical Configuration Table of the IOP specified
+ by lct->iop in the buffer pointed to by lct->resbuf. The actual size of
+ the data is written into *(lct->reslen).
+
+ RETURNS
+
+ This function returns 0 if no errors occur. If an error occurs, -1
+ is returned and errno is set appropriately:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ENOBUFS Buffer not large enough. If this occurs, the required
+ buffer length is written into *(lct->reslen)
+
+VI. Settting Parameters
+
+ SYNOPSIS
+
+ ioctl(fd, I2OPARMSET, struct i2o_parm_setget *ops);
+
+ struct i2o_cmd_psetget
+ {
+ u32 iop; /* IOP unit number */
+ u32 tid; /* Target device TID */
+ void *opbuf; /* Operation List buffer */
+ u32 oplen; /* Operation List buffer length in bytes */
+ void *resbuf; /* Result List buffer */
+ u32 *reslen; /* Result List buffer length in bytes */
+ };
+
+ DESCRIPTION
+
+ This function posts a UtilParamsSet message to the device identified
+ by ops->iop and ops->tid. The operation list for the message is
+ sent through the ops->opbuf buffer, and the result list is written
+ into the buffer pointed to by ops->resbuf. The number of bytes
+ written is placed into *(ops->reslen).
+
+ RETURNS
+
+ The return value is the size in bytes of the data written into
+ ops->resbuf if no errors occur. If an error occurs, -1 is returned
+ and errno is set appropriatly:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ENOBUFS Buffer not large enough. If this occurs, the required
+ buffer length is written into *(ops->reslen)
+ ETIMEDOUT Timeout waiting for reply message
+ ENOMEM Kernel memory allocation error
+
+ A return value of 0 does not mean that the value was actually
+ changed properly on the IOP. The user should check the result
+ list to determine the specific status of the transaction.
+
+VII. Getting Parameters
+
+ SYNOPSIS
+
+ ioctl(fd, I2OPARMGET, struct i2o_parm_setget *ops);
+
+ struct i2o_parm_setget
+ {
+ u32 iop; /* IOP unit number */
+ u32 tid; /* Target device TID */
+ void *opbuf; /* Operation List buffer */
+ u32 oplen; /* Operation List buffer length in bytes */
+ void *resbuf; /* Result List buffer */
+ u32 *reslen; /* Result List buffer length in bytes */
+ };
+
+ DESCRIPTION
+
+ This function posts a UtilParamsGet message to the device identified
+ by ops->iop and ops->tid. The operation list for the message is
+ sent through the ops->opbuf buffer, and the result list is written
+ into the buffer pointed to by ops->resbuf. The actual size of data
+ written is placed into *(ops->reslen).
+
+ RETURNS
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ENOBUFS Buffer not large enough. If this occurs, the required
+ buffer length is written into *(ops->reslen)
+ ETIMEDOUT Timeout waiting for reply message
+ ENOMEM Kernel memory allocation error
+
+ A return value of 0 does not mean that the value was actually
+ properly retreived. The user should check the result list
+ to determine the specific status of the transaction.
+
+VIII. Downloading Software
+
+ SYNOPSIS
+
+ ioctl(fd, I2OSWDL, struct i2o_sw_xfer *sw);
+
+ struct i2o_sw_xfer
+ {
+ u32 iop; /* IOP unit number */
+ u8 flags; /* DownloadFlags field */
+ u8 sw_type; /* Software type */
+ u32 sw_id; /* Software ID */
+ void *buf; /* Pointer to software buffer */
+ u32 *swlen; /* Length of software buffer */
+ u32 *maxfrag; /* Number of fragments */
+ u32 *curfrag; /* Current fragment number */
+ };
+
+ DESCRIPTION
+
+ This function downloads a software fragment pointed by sw->buf
+ to the iop identified by sw->iop. The DownloadFlags, SwID, SwType
+ and SwSize fields of the ExecSwDownload message are filled in with
+ the values of sw->flags, sw->sw_id, sw->sw_type and *(sw->swlen).
+
+ The fragments _must_ be sent in order and be 8K in size. The last
+ fragment _may_ be shorter, however. The kernel will compute its
+ size based on information in the sw->swlen field.
+
+ Please note that SW transfers can take a long time.
+
+ RETURNS
+
+ This function returns 0 no errors occur. If an error occurs, -1
+ is returned and errno is set appropriatly:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ETIMEDOUT Timeout waiting for reply message
+ ENOMEM Kernel memory allocation error
+
+IX. Uploading Software
+
+ SYNOPSIS
+
+ ioctl(fd, I2OSWUL, struct i2o_sw_xfer *sw);
+
+ struct i2o_sw_xfer
+ {
+ u32 iop; /* IOP unit number */
+ u8 flags; /* UploadFlags */
+ u8 sw_type; /* Software type */
+ u32 sw_id; /* Software ID */
+ void *buf; /* Pointer to software buffer */
+ u32 *swlen; /* Length of software buffer */
+ u32 *maxfrag; /* Number of fragments */
+ u32 *curfrag; /* Current fragment number */
+ };
+
+ DESCRIPTION
+
+ This function uploads a software fragment from the IOP identified
+ by sw->iop, sw->sw_type, sw->sw_id and optionally sw->swlen fields.
+ The UploadFlags, SwID, SwType and SwSize fields of the ExecSwUpload
+ message are filled in with the values of sw->flags, sw->sw_id,
+ sw->sw_type and *(sw->swlen).
+
+ The fragments _must_ be requested in order and be 8K in size. The
+ user is responsible for allocating memory pointed by sw->buf. The
+ last fragment _may_ be shorter.
+
+ Please note that SW transfers can take a long time.
+
+ RETURNS
+
+ This function returns 0 if no errors occur. If an error occurs, -1
+ is returned and errno is set appropriatly:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ETIMEDOUT Timeout waiting for reply message
+ ENOMEM Kernel memory allocation error
+
+X. Removing Software
+
+ SYNOPSIS
+
+ ioctl(fd, I2OSWDEL, struct i2o_sw_xfer *sw);
+
+ struct i2o_sw_xfer
+ {
+ u32 iop; /* IOP unit number */
+ u8 flags; /* RemoveFlags */
+ u8 sw_type; /* Software type */
+ u32 sw_id; /* Software ID */
+ void *buf; /* Unused */
+ u32 *swlen; /* Length of the software data */
+ u32 *maxfrag; /* Unused */
+ u32 *curfrag; /* Unused */
+ };
+
+ DESCRIPTION
+
+ This function removes software from the IOP identified by sw->iop.
+ The RemoveFlags, SwID, SwType and SwSize fields of the ExecSwRemove message
+ are filled in with the values of sw->flags, sw->sw_id, sw->sw_type and
+ *(sw->swlen). Give zero in *(sw->len) if the value is unknown. IOP uses
+ *(sw->swlen) value to verify correct identication of the module to remove.
+ The actual size of the module is written into *(sw->swlen).
+
+ RETURNS
+
+ This function returns 0 if no errors occur. If an error occurs, -1
+ is returned and errno is set appropriatly:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ETIMEDOUT Timeout waiting for reply message
+ ENOMEM Kernel memory allocation error
+
+X. Validating Configuration
+
+ SYNOPSIS
+
+ ioctl(fd, I2OVALIDATE, int *iop);
+ u32 iop;
+
+ DESCRIPTION
+
+ This function posts an ExecConfigValidate message to the controller
+ identified by iop. This message indicates that the current
+ configuration is accepted. The iop changes the status of suspect drivers
+ to valid and may delete old drivers from its store.
+
+ RETURNS
+
+ This function returns 0 if no erro occur. If an error occurs, -1 is
+ returned and errno is set appropriatly:
+
+ ETIMEDOUT Timeout waiting for reply message
+ ENXIO Invalid IOP number
+
+XI. Configuration Dialog
+
+ SYNOPSIS
+
+ ioctl(fd, I2OHTML, struct i2o_html *htquery);
+ struct i2o_html
+ {
+ u32 iop; /* IOP unit number */
+ u32 tid; /* Target device ID */
+ u32 page; /* HTML page */
+ void *resbuf; /* Buffer for reply HTML page */
+ u32 *reslen; /* Length in bytes of reply buffer */
+ void *qbuf; /* Pointer to HTTP query string */
+ u32 qlen; /* Length in bytes of query string buffer */
+ };
+
+ DESCRIPTION
+
+ This function posts an UtilConfigDialog message to the device identified
+ by htquery->iop and htquery->tid. The requested HTML page number is
+ provided by the htquery->page field, and the resultant data is stored
+ in the buffer pointed to by htquery->resbuf. If there is an HTTP query
+ string that is to be sent to the device, it should be sent in the buffer
+ pointed to by htquery->qbuf. If there is no query string, this field
+ should be set to NULL. The actual size of the reply received is written
+ into *(htquery->reslen).
+
+ RETURNS
+
+ This function returns 0 if no error occur. If an error occurs, -1
+ is returned and errno is set appropriatly:
+
+ EFAULT Invalid user space pointer was passed
+ ENXIO Invalid IOP number
+ ENOBUFS Buffer not large enough. If this occurs, the required
+ buffer length is written into *(ops->reslen)
+ ETIMEDOUT Timeout waiting for reply message
+ ENOMEM Kernel memory allocation error
+
+XII. Events
+
+ In the process of determining this. Current idea is to have use
+ the select() interface to allow user apps to periodically poll
+ the /dev/i2o/ctl device for events. When select() notifies the user
+ that an event is available, the user would call read() to retrieve
+ a list of all the events that are pending for the specific device.
+
+=============================================================================
+Revision History
+=============================================================================
+
+Rev 0.1 - 04/01/99
+- Initial revision
+
+Rev 0.2 - 04/06/99
+- Changed return values to match UNIX ioctl() standard. Only return values
+ are 0 and -1. All errors are reported through errno.
+- Added summary of proposed possible event interfaces
+
+Rev 0.3 - 04/20/99
+- Changed all ioctls() to use pointers to user data instead of actual data
+- Updated error values to match the code
--- /dev/null
+Generic networking statistics for netlink users
+======================================================================
+
+Statistic counters are grouped into structs:
+
+Struct TLV type Description
+----------------------------------------------------------------------
+gnet_stats_basic TCA_STATS_BASIC Basic statistics
+gnet_stats_rate_est TCA_STATS_RATE_EST Rate estimator
+gnet_stats_queue TCA_STATS_QUEUE Queue statistics
+none TCA_STATS_APP Application specific
+
+
+Collecting:
+-----------
+
+Declare the statistic structs you need:
+struct mystruct {
+ struct gnet_stats_basic bstats;
+ struct gnet_stats_queue qstats;
+ ...
+};
+
+Update statistics:
+mystruct->tstats.packet++;
+mystruct->qstats.backlog += skb->pkt_len;
+
+
+Export to userspace (Dump):
+---------------------------
+
+my_dumping_routine(struct sk_buff *skb, ...)
+{
+ struct gnet_dump dump;
+
+ if (gnet_stats_start_copy(skb, TCA_STATS2, &mystruct->lock, &dump) < 0)
+ goto rtattr_failure;
+
+ if (gnet_stats_copy_basic(&dump, &mystruct->bstats) < 0 ||
+ gnet_stats_copy_queue(&dump, &mystruct->qstats) < 0 ||
+ gnet_stats_copy_app(&dump, &xstats, sizeof(xstats)) < 0)
+ goto rtattr_failure;
+
+ if (gnet_stats_finish_copy(&dump) < 0)
+ goto rtattr_failure;
+ ...
+}
+
+TCA_STATS/TCA_XSTATS backward compatibility:
+--------------------------------------------
+
+Prior users of struct tc_stats and xstats can maintain backward
+compatibility by calling the compat wrappers to keep providing the
+existing TLV types.
+
+my_dumping_routine(struct sk_buff *skb, ...)
+{
+ if (gnet_stats_start_copy_compat(skb, TCA_STATS2, TCA_STATS,
+ TCA_XSTATS, &mystruct->lock, &dump) < 0)
+ goto rtattr_failure;
+ ...
+}
+
+A struct tc_stats will be filled out during gnet_stats_copy_* calls
+and appended to the skb. TCA_XSTATS is provided if gnet_stats_copy_app
+was called.
+
+
+Locking:
+--------
+
+Locks are taken before writing and released once all statistics have
+been written. Locks are always released in case of an error. You
+are responsible for making sure that the lock is initialized.
+
+
+Rate Estimator:
+--------------
+
+0) Prepare an estimator attribute. Most likely this would be in user
+ space. The value of this TLV should contain a tc_estimator structure.
+ As usual, such a TLV nees to be 32 bit aligned and therefore the
+ length needs to be appropriately set etc. The estimator interval
+ and ewma log need to be converted to the appropriate values.
+ tc_estimator.c::tc_setup_estimator() is advisable to be used as the
+ conversion routine. It does a few clever things. It takes a time
+ interval in microsecs, a time constant also in microsecs and a struct
+ tc_estimator to be populated. The returned tc_estimator can be
+ transported to the kernel. Transfer such a structure in a TLV of type
+ TCA_RATE to your code in the kernel.
+
+In the kernel when setting up:
+1) make sure you have basic stats and rate stats setup first.
+2) make sure you have initialized stats lock that is used to setup such
+ stats.
+3) Now initialize a new estimator:
+
+ int ret = gen_new_estimator(my_basicstats,my_rate_est_stats,
+ mystats_lock, attr_with_tcestimator_struct);
+
+ if ret == 0
+ success
+ else
+ failed
+
+From now on, everytime you dump my_rate_est_stats it will contain
+uptodate info.
+
+Once you are done, call gen_kill_estimator(my_basicstats,
+my_rate_est_stats) Make sure that my_basicstats and my_rate_est_stats
+are still valid (i.e still exist) at the time of making this call.
+
+
+Authors:
+--------
+Thomas Graf <tgraf@suug.ch>
+Jamal Hadi Salim <hadi@cyberus.ca>
--- /dev/null
+Version 10 of schedstats includes support for sched_domains, which
+hit the mainline kernel in 2.6.7. Some counters make more sense to be
+per-runqueue; other to be per-domain. Note that domains (and their associated
+information) will only be pertinent and available on machines utilizing
+CONFIG_SMP.
+
+In version 10 of schedstat, there is at least one level of domain
+statistics for each cpu listed, and there may well be more than one
+domain. Domains have no particular names in this implementation, but
+the highest numbered one typically arbitrates balancing across all the
+cpus on the machine, while domain0 is the most tightly focused domain,
+sometimes balancing only between pairs of cpus. At this time, there
+are no architectures which need more than three domain levels. The first
+field in the domain stats is a bit map indicating which cpus are affected
+by that domain.
+
+These fields are counters, and only increment. Programs which make use
+of these will need to start with a baseline observation and then calculate
+the change in the counters at each subsequent observation. A perl script
+which does this for many of the fields is available at
+
+ http://eaglet.rain.com/rick/linux/schedstat/
+
+Note that any such script will necessarily be version-specific, as the main
+reason to change versions is changes in the output format. For those wishing
+to write their own scripts, the fields are described here.
+
+CPU statistics
+--------------
+cpu<N> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
+
+NOTE: In the sched_yield() statistics, the active queue is considered empty
+ if it has only one process in it, since obviously the process calling
+ sched_yield() is that process.
+
+First four fields are sched_yield() statistics:
+ 1) # of times both the active and the expired queue were empty
+ 2) # of times just the active queue was empty
+ 3) # of times just the expired queue was empty
+ 4) # of times sched_yield() was called
+
+Next four are schedule() statistics:
+ 5) # of times the active queue had at least one other process on it
+ 6) # of times we switched to the expired queue and reused it
+ 7) # of times schedule() was called
+ 8) # of times schedule() left the processor idle
+
+Next four are active_load_balance() statistics:
+ 9) # of times active_load_balance() was called
+ 10) # of times active_load_balance() caused this cpu to gain a task
+ 11) # of times active_load_balance() caused this cpu to lose a task
+ 12) # of times active_load_balance() tried to move a task and failed
+
+Next three are try_to_wake_up() statistics:
+ 13) # of times try_to_wake_up() was called
+ 14) # of times try_to_wake_up() successfully moved the awakening task
+ 15) # of times try_to_wake_up() attempted to move the awakening task
+
+Next two are wake_up_new_task() statistics:
+ 16) # of times wake_up_new_task() was called
+ 17) # of times wake_up_new_task() successfully moved the new task
+
+Next one is a sched_migrate_task() statistic:
+ 18) # of times sched_migrate_task() was called
+
+Next one is a sched_balance_exec() statistic:
+ 19) # of times sched_balance_exec() was called
+
+Next three are statistics describing scheduling latency:
+ 20) sum of all time spent running by tasks on this processor (in ms)
+ 21) sum of all time spent waiting to run by tasks on this processor (in ms)
+ 22) # of tasks (not necessarily unique) given to the processor
+
+The last six are statistics dealing with pull_task():
+ 23) # of times pull_task() moved a task to this cpu when newly idle
+ 24) # of times pull_task() stole a task from this cpu when another cpu
+ was newly idle
+ 25) # of times pull_task() moved a task to this cpu when idle
+ 26) # of times pull_task() stole a task from this cpu when another cpu
+ was idle
+ 27) # of times pull_task() moved a task to this cpu when busy
+ 28) # of times pull_task() stole a task from this cpu when another cpu
+ was busy
+
+
+Domain statistics
+-----------------
+One of these is produced per domain for each cpu described. (Note that if
+CONFIG_SMP is not defined, *no* domains are utilized and these lines
+will not appear in the output.)
+
+domain<N> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+
+The first field is a bit mask indicating what cpus this domain operates over.
+
+The next fifteen are a variety of load_balance() statistics:
+
+ 1) # of times in this domain load_balance() was called when the cpu
+ was idle
+ 2) # of times in this domain load_balance() was called when the cpu
+ was busy
+ 3) # of times in this domain load_balance() was called when the cpu
+ was just becoming idle
+ 4) # of times in this domain load_balance() tried to move one or more
+ tasks and failed, when the cpu was idle
+ 5) # of times in this domain load_balance() tried to move one or more
+ tasks and failed, when the cpu was busy
+ 6) # of times in this domain load_balance() tried to move one or more
+ tasks and failed, when the cpu was just becoming idle
+ 7) sum of imbalances discovered (if any) with each call to
+ load_balance() in this domain when the cpu was idle
+ 8) sum of imbalances discovered (if any) with each call to
+ load_balance() in this domain when the cpu was busy
+ 9) sum of imbalances discovered (if any) with each call to
+ load_balance() in this domain when the cpu was just becoming idle
+ 10) # of times in this domain load_balance() was called but did not find
+ a busier queue while the cpu was idle
+ 11) # of times in this domain load_balance() was called but did not find
+ a busier queue while the cpu was busy
+ 12) # of times in this domain load_balance() was called but did not find
+ a busier queue while the cpu was just becoming idle
+ 13) # of times in this domain a busier queue was found while the cpu was
+ idle but no busier group was found
+ 14) # of times in this domain a busier queue was found while the cpu was
+ busy but no busier group was found
+ 15) # of times in this domain a busier queue was found while the cpu was
+ just becoming idle but no busier group was found
+
+Next two are sched_balance_exec() statistics:
+ 17) # of times in this domain sched_balance_exec() successfully pushed
+ a task to a new cpu
+ 18) # of times in this domain sched_balance_exec() tried but failed to
+ push a task to a new cpu
+
+Next two are try_to_wake_up() statistics:
+ 19) # of times in this domain try_to_wake_up() tried to move a task based
+ on affinity and cache warmth
+ 20) # of times in this domain try_to_wake_up() tried to move a task based
+ on load balancing
+
+
+/proc/<pid>/schedstat
+----------------
+schedstats also adds a new /proc/<pid/schedstat file to include some of
+the same information on a per-process level. There are three fields in
+this file correlating to fields 20, 21, and 22 in the CPU fields, but
+they only apply for that process.
+
+A program could be easily written to make use of these extra fields to
+report on how well a particular process or set of processes is faring
+under the scheduler's policies. A simple version of such a program is
+available at
+ http://eaglet.rain.com/rick/linux/schedstat/v10/latency.c
--- /dev/null
+ Notes on Management Module
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Overview:
+--------
+
+Different classes of controllers from LSI Logic, accept and respond to the
+user applications in a similar way. They understand the same firmware control
+commands. Furthermore, the applications also can treat different classes of
+the controllers uniformly. Hence it is logical to have a single module that
+interefaces with the applications on one side and all the low level drivers
+on the other.
+
+The advantages, though obvious, are listed for completeness:
+
+ i. Avoid duplicate code from the low level drivers.
+ ii. Unburden the low level drivers from having to export the
+ character node device and related handling.
+ iii. Implement any policy mechanisms in one place.
+ iv. Applications have to interface with only module instead of
+ multiple low level drivers.
+
+Currently this module (called Common Management Module) is used only to issue
+ioctl commands. But this module is envisioned to handle all user space level
+interactions. So any 'proc', 'sysfs' implementations will be localized in this
+common module.
+
+Credits:
+-------
+
+"Shared code in a third module, a "library module", is an acceptable
+solution. modprobe automatically loads dependent modules, so users
+running "modprobe driver1" or "modprobe driver2" would automatically
+load the shared library module."
+
+ - Jeff Garzik (jgarzik@pobox.com), 02.25.2004 LKML
+
+"As Jeff hinted, if your userspace<->driver API is consistent between
+your new MPT-based RAID controllers and your existing megaraid driver,
+then perhaps you need a single small helper module (lsiioctl or some
+better name), loaded by both mptraid and megaraid automatically, which
+handles registering the /dev/megaraid node dynamically. In this case,
+both mptraid and megaraid would register with lsiioctl for each
+adapter discovered, and lsiioctl would essentially be a switch,
+redirecting userspace tool ioctls to the appropriate driver."
+
+ - Matt Domsch, (Matt_Domsch@dell.com), 02.25.2004 LKML
+
+Design:
+------
+
+The Common Management Module is implemented in megaraid_mm.[ch] files. This
+module acts as a registry for low level hba drivers. The low level drivers
+(currently only megaraid) register each controller with the common module.
+
+The applications interface with the common module via the character device
+node exported by the module.
+
+The lower level drivers now understand only a new improved ioctl packet called
+uioc_t. The management module converts the older ioctl packets from the older
+applications into uioc_t. After driver handles the uioc_t, the common module
+will convert that back into the old format before returning to applications.
+
+As new applications evolve and replace the old ones, the old packet format
+will be retired.
+
+Common module dedicates one uioc_t packet to each controller registered. This
+can easily be more than one. But since megaraid is the only low level driver
+today, and it can handle only one ioctl, there is no reason to have more. But
+as new controller classes get added, this will be tuned appropriately.
--- /dev/null
+Time Interpolators
+------------------
+
+Time interpolators are a base of time calculation between timer ticks and
+allow an accurate determination of time down to the accuracy of the time
+source in nanoseconds.
+
+The architecture specific code typically provides gettimeofday and
+settimeofday under Linux. The time interpolator provides both if an arch
+defines CONFIG_TIME_INTERPOLATION. The arch still must set up timer tick
+operations and call the necessary functions to advance the clock.
+With the time interpolator a standardized interface exists for time
+interpolation between ticks which also allows the determination
+of time in a hardware independent way. The provided logic is highly scalable
+and has been tested in SMP situations of up to 512 CPUs.
+
+If CONFIG_TIME_INTERPOLATION is defined then the architecture specific code
+(or the device drivers - like HPET) must register time interpolators.
+These are typically defined in the following way:
+
+static struct time_interpolator my_interpolator;
+
+void time_init(void)
+{
+ ....
+ /* Initialization of the timer *.
+ my_interpolator.frequency = MY_FREQUENCY;
+ my_interpolator.source = TIME_SOURCE_MMIO32;
+ my_interpolator.address = &my_timer;
+ my_interpolator.shift = 32; /* increase accuracy of scaling */
+ my_interpolator.drift = -1; /* Unknown */
+ my_interpolator.jitter = 0; /* A stable time source */
+ register_time_interpolator(&my_interpolator);
+ ....
+}
+
+For more details see include/linux/timex.h.
+
+Christoph Lameter <christoph@lameter.com>, September 8, 2004
+
--- /dev/null
+
+ The Lockronomicon
+
+Your guide to the ancient and twisted locking policies of the tty layer and
+the warped logic behind them. Beware all ye who read on.
+
+FIXME: still need to work out the full set of BKL assumptions and document
+them so they can eventually be killed off.
+
+
+Line Discipline
+---------------
+
+Line disciplines are registered with tty_register_ldisc() passing the
+discipline number and the ldisc structure. At the point of registration the
+discipline must be ready to use and it is possible it will get used before
+the call returns success. If the call returns an error then it won't get
+called. Do not re-use ldisc numbers as they are part of the userspace ABI
+and writing over an existing ldisc will cause demons to eat your computer.
+After the return the ldisc data has been copied so you may free your own
+copy of the structure. You must not re-register over the top of the line
+discipline even with the same data or your computer again will be eaten by
+demons.
+
+In order to remove a line discipline call tty_register_ldisc passing NULL.
+In ancient times this always worked. In modern times the function will
+return -EBUSY if the ldisc is currently in use. Since the ldisc referencing
+code manages the module counts this should not usually be a concern.
+
+Heed this warning: the reference count field of the registered copies of the
+tty_ldisc structure in the ldisc table counts the number of lines using this
+discipline. The reference count of the tty_ldisc structure within a tty
+counts the number of active users of the ldisc at this instant. In effect it
+counts the number of threads of execution within an ldisc method (plus those
+about to enter and exit although this detail matters not).
+
+Line Discipline Methods
+-----------------------
+
+TTY side interfaces:
+
+close() - This is called on a terminal when the line
+ discipline is being unplugged. At the point of
+ execution no further users will enter the
+ ldisc code for this tty. Can sleep.
+
+open() - Called when the line discipline is attached to
+ the terminal. No other call into the line
+ discipline for this tty will occur until it
+ completes successfully. Can sleep.
+
+write() - A process is writing data from user space
+ through the line discipline. Multiple write calls
+ are serialized by the tty layer for the ldisc. May
+ sleep.
+
+flush_buffer() - May be called at any point between open and close.
+
+chars_in_buffer() - Report the number of bytes in the buffer.
+
+set_termios() - Called on termios structure changes. The caller
+ passes the old termios data and the current data
+ is in the tty. Called under the termios semaphore so
+ allowed to sleep. Serialized against itself only.
+
+read() - Move data from the line discipline to the user.
+ Multiple read calls may occur in parallel and the
+ ldisc must deal with serialization issues. May
+ sleep.
+
+poll() - Check the status for the poll/select calls. Multiple
+ poll calls may occur in parallel. May sleep.
+
+ioctl() - Called when an ioctl is handed to the tty layer
+ that might be for the ldisc. Multiple ioctl calls
+ may occur in parallel. May sleep.
+
+Driver Side Interfaces:
+
+receive_buf() - Hand buffers of bytes from the driver to the ldisc
+ for processing. Semantics currently rather
+ mysterious 8(
+
+receive_room() - Can be called by the driver layer at any time when
+ the ldisc is opened. The ldisc must be able to
+ handle the reported amount of data at that instant.
+ Synchronization between active receive_buf and
+ receive_room calls is down to the driver not the
+ ldisc. Must not sleep.
+
+write_wakeup() - May be called at any point between open and close.
+ The TTY_DO_WRITE_WAKEUP flag indicates if a call
+ is needed but always races versus calls. Thus the
+ ldisc must be careful about setting order and to
+ handle unexpected calls. Must not sleep.
+
+
+Locking
+
+Callers to the line discipline functions from the tty layer are required to
+take line discipline locks. The same is true of calls from the driver side
+but not yet enforced.
+
+Three calls are now provided
+
+ ldisc = tty_ldisc_ref(tty);
+
+takes a handle to the line discipline in the tty and returns it. If no ldisc
+is currently attached or the ldisc is being closed and re-opened at this
+point then NULL is returned. While this handle is held the ldisc will not
+change or go away.
+
+ tty_ldisc_deref(ldisc)
+
+Returns the ldisc reference and allows the ldisc to be closed. Returning the
+reference takes away your right to call the ldisc functions until you take
+a new reference.
+
+ ldisc = tty_ldisc_ref_wait(tty);
+
+Performs the same function as tty_ldisc_ref except that it will wait for an
+ldisc change to complete and then return a reference to the new ldisc.
+
+While these functions are slightly slower than the old code they should have
+minimal impact as most receive logic uses the flip buffers and they only
+need to take a reference when they push bits up through the driver.
+
+A caution: The ldisc->open(), ldisc->close() and driver->set_ldisc
+functions are called with the ldisc unavailable. Thus tty_ldisc_ref will
+fail in this situation if used within these functions. Ldisc and driver
+code calling its own functions must be careful in this case.
+
+
+Driver Interface
+----------------
+
+open() - Called when a device is opened. May sleep
+
+close() - Called when a device is closed. At the point of
+ return from this call the driver must make no
+ further ldisc calls of any kind. May sleep
+
+write() - Called to write bytes to the device. May not
+ sleep. May occur in parallel in special cases.
+ Because this includes panic paths drivers generally
+ shouldn't try and do clever locking here.
+
+put_char() - Stuff a single character onto the queue. The
+ driver is guaranteed following up calls to
+ flush_chars.
+
+flush_chars() - Ask the kernel to write put_char queue
+
+write_room() - Return the number of characters tht can be stuffed
+ into the port buffers without overflow (or less).
+ The ldisc is responsible for being intelligent
+ about multi-threading of write_room/write calls
+
+ioctl() - Called when an ioctl may be for the driver
+
+set_termios() - Called on termios change, serialized against
+ itself by a semaphore. May sleep.
+
+set_ldisc() - Notifier for discipline change. At the point this
+ is done the discipline is not yet usable. Can now
+ sleep (I think)
+
+throttle() - Called by the ldisc to ask the driver to do flow
+ control. Serialization including with unthrottle
+ is the job of the ldisc layer.
+
+unthrottle() - Called by the ldisc to ask the driver to stop flow
+ control.
+
+stop() - Ldisc notifier to the driver to stop output. As with
+ throttle the serializations with start() are down
+ to the ldisc layer.
+
+start() - Ldisc notifier to the driver to start output.
+
+hangup() - Ask the tty driver to cause a hangup initiated
+ from the host side. [Can sleep ??]
+
+break_ctl() - Send RS232 break. Can sleep. Can get called in
+ parallel, driver must serialize (for now), and
+ with write calls.
+
+wait_until_sent() - Wait for characters to exit the hardware queue
+ of the driver. Can sleep
+
+send_xchar() - Send XON/XOFF and if possible jump the queue with
+ it in order to get fast flow control responses.
+ Cannot sleep ??
+
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config EARLY_PRINTK
+ bool
+ depends on ALPHA_GENERIC || ALPHA_SRM
+ default y
+
+config DEBUG_RWLOCK
+ bool "Read-write spinlock debugging"
+ depends on DEBUG_KERNEL
+ help
+ If you say Y here then read-write lock processing will count how many
+ times it has tried to get the lock and issue an error message after
+ too many attempts. If you suspect a rwlock problem or a kernel
+ hacker asks for this option then say Y. Otherwise say N.
+
+config DEBUG_SEMAPHORE
+ bool "Semaphore debugging"
+ depends on DEBUG_KERNEL
+ help
+ If you say Y here then semaphore processing will issue lots of
+ verbose debugging messages. If you suspect a semaphore problem or a
+ kernel hacker asks for this option then say Y. Otherwise say N.
+
+config ALPHA_LEGACY_START_ADDRESS
+ bool "Legacy kernel start address"
+ depends on ALPHA_GENERIC
+ default n
+ ---help---
+ The 2.4 kernel changed the kernel start address from 0x310000
+ to 0x810000 to make room for the Wildfire's larger SRM console.
+ Recent consoles on Titan and Marvel machines also require the
+ extra room.
+
+ If you're using aboot 0.7 or later, the bootloader will examine the
+ ELF headers to determine where to transfer control. Unfortunately,
+ most older bootloaders -- APB or MILO -- hardcoded the kernel start
+ address rather than examining the ELF headers, and the result is a
+ hard lockup.
+
+ Say Y if you have a broken bootloader. Say N if you do not, or if
+ you wish to run on Wildfire, Titan, or Marvel.
+
+config ALPHA_LEGACY_START_ADDRESS
+ bool
+ depends on !ALPHA_GENERIC && !ALPHA_TITAN && !ALPHA_MARVEL && !ALPHA_WILDFIRE
+ default y
+
+config MATHEMU
+ tristate "Kernel FP software completion" if DEBUG_KERNEL && !SMP
+ default y if !DEBUG_KERNEL || SMP
+ help
+ This option is required for IEEE compliant floating point arithmetic
+ on the Alpha. The only time you would ever not say Y is to say M in
+ order to debug the code. Say Y unless you know what you are doing.
+
+endmenu
--- /dev/null
+/*
+ * Alpha IO and memory functions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/io.h>
+
+/* Out-of-line versions of the i/o routines that redirect into the
+ platform-specific version. Note that "platform-specific" may mean
+ "generic", which bumps through the machine vector. */
+
+unsigned int
+ioread8(void __iomem *addr)
+{
+ unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr);
+ mb();
+ return ret;
+}
+
+unsigned int ioread16(void __iomem *addr)
+{
+ unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr);
+ mb();
+ return ret;
+}
+
+unsigned int ioread32(void __iomem *addr)
+{
+ unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr);
+ mb();
+ return ret;
+}
+
+void iowrite8(u8 b, void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr);
+ mb();
+}
+
+void iowrite16(u16 b, void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr);
+ mb();
+}
+
+void iowrite32(u32 b, void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
+ mb();
+}
+
+EXPORT_SYMBOL(ioread8);
+EXPORT_SYMBOL(ioread16);
+EXPORT_SYMBOL(ioread32);
+EXPORT_SYMBOL(iowrite8);
+EXPORT_SYMBOL(iowrite16);
+EXPORT_SYMBOL(iowrite32);
+
+u8 inb(unsigned long port)
+{
+ return ioread8(ioport_map(port, 1));
+}
+
+u16 inw(unsigned long port)
+{
+ return ioread16(ioport_map(port, 2));
+}
+
+u32 inl(unsigned long port)
+{
+ return ioread32(ioport_map(port, 4));
+}
+
+void outb(u8 b, unsigned long port)
+{
+ iowrite8(b, ioport_map(port, 1));
+}
+
+void outw(u16 b, unsigned long port)
+{
+ iowrite16(b, ioport_map(port, 2));
+}
+
+void outl(u32 b, unsigned long port)
+{
+ iowrite32(b, ioport_map(port, 4));
+}
+
+EXPORT_SYMBOL(inb);
+EXPORT_SYMBOL(inw);
+EXPORT_SYMBOL(inl);
+EXPORT_SYMBOL(outb);
+EXPORT_SYMBOL(outw);
+EXPORT_SYMBOL(outl);
+
+u8 __raw_readb(const volatile void __iomem *addr)
+{
+ return IO_CONCAT(__IO_PREFIX,readb)(addr);
+}
+
+u16 __raw_readw(const volatile void __iomem *addr)
+{
+ return IO_CONCAT(__IO_PREFIX,readw)(addr);
+}
+
+u32 __raw_readl(const volatile void __iomem *addr)
+{
+ return IO_CONCAT(__IO_PREFIX,readl)(addr);
+}
+
+u64 __raw_readq(const volatile void __iomem *addr)
+{
+ return IO_CONCAT(__IO_PREFIX,readq)(addr);
+}
+
+void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,writeb)(b, addr);
+}
+
+void __raw_writew(u16 b, volatile void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,writew)(b, addr);
+}
+
+void __raw_writel(u32 b, volatile void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,writel)(b, addr);
+}
+
+void __raw_writeq(u64 b, volatile void __iomem *addr)
+{
+ IO_CONCAT(__IO_PREFIX,writeq)(b, addr);
+}
+
+EXPORT_SYMBOL(__raw_readb);
+EXPORT_SYMBOL(__raw_readw);
+EXPORT_SYMBOL(__raw_readl);
+EXPORT_SYMBOL(__raw_readq);
+EXPORT_SYMBOL(__raw_writeb);
+EXPORT_SYMBOL(__raw_writew);
+EXPORT_SYMBOL(__raw_writel);
+EXPORT_SYMBOL(__raw_writeq);
+
+u8 readb(const volatile void __iomem *addr)
+{
+ u8 ret = __raw_readb(addr);
+ mb();
+ return ret;
+}
+
+u16 readw(const volatile void __iomem *addr)
+{
+ u16 ret = __raw_readw(addr);
+ mb();
+ return ret;
+}
+
+u32 readl(const volatile void __iomem *addr)
+{
+ u32 ret = __raw_readl(addr);
+ mb();
+ return ret;
+}
+
+u64 readq(const volatile void __iomem *addr)
+{
+ u64 ret = __raw_readq(addr);
+ mb();
+ return ret;
+}
+
+void writeb(u8 b, volatile void __iomem *addr)
+{
+ __raw_writeb(b, addr);
+ mb();
+}
+
+void writew(u16 b, volatile void __iomem *addr)
+{
+ __raw_writew(b, addr);
+ mb();
+}
+
+void writel(u32 b, volatile void __iomem *addr)
+{
+ __raw_writel(b, addr);
+ mb();
+}
+
+void writeq(u64 b, volatile void __iomem *addr)
+{
+ __raw_writeq(b, addr);
+ mb();
+}
+
+EXPORT_SYMBOL(readb);
+EXPORT_SYMBOL(readw);
+EXPORT_SYMBOL(readl);
+EXPORT_SYMBOL(readq);
+EXPORT_SYMBOL(writeb);
+EXPORT_SYMBOL(writew);
+EXPORT_SYMBOL(writel);
+EXPORT_SYMBOL(writeq);
+
+
+/*
+ * Read COUNT 8-bit bytes from port PORT into memory starting at SRC.
+ */
+void ioread8_rep(void __iomem *port, void *dst, unsigned long count)
+{
+ while ((unsigned long)dst & 0x3) {
+ if (!count)
+ return;
+ count--;
+ *(unsigned char *)dst = ioread8(port);
+ dst += 1;
+ }
+
+ while (count >= 4) {
+ unsigned int w;
+ count -= 4;
+ w = ioread8(port);
+ w |= ioread8(port) << 8;
+ w |= ioread8(port) << 16;
+ w |= ioread8(port) << 24;
+ *(unsigned int *)dst = w;
+ dst += 4;
+ }
+
+ while (count) {
+ --count;
+ *(unsigned char *)dst = ioread8(port);
+ dst += 1;
+ }
+}
+
+void insb(unsigned long port, void *dst, unsigned long count)
+{
+ ioread8_rep(ioport_map(port, 1), dst, count);
+}
+
+EXPORT_SYMBOL(ioread8_rep);
+EXPORT_SYMBOL(insb);
+
+/*
+ * Read COUNT 16-bit words from port PORT into memory starting at
+ * SRC. SRC must be at least short aligned. This is used by the
+ * IDE driver to read disk sectors. Performance is important, but
+ * the interfaces seems to be slow: just using the inlined version
+ * of the inw() breaks things.
+ */
+void ioread16_rep(void __iomem *port, void *dst, unsigned long count)
+{
+ if (unlikely((unsigned long)dst & 0x3)) {
+ if (!count)
+ return;
+ BUG_ON((unsigned long)dst & 0x1);
+ count--;
+ *(unsigned short *)dst = ioread16(port);
+ dst += 2;
+ }
+
+ while (count >= 2) {
+ unsigned int w;
+ count -= 2;
+ w = ioread16(port);
+ w |= ioread16(port) << 16;
+ *(unsigned int *)dst = w;
+ dst += 4;
+ }
+
+ if (count) {
+ *(unsigned short*)dst = ioread16(port);
+ }
+}
+
+void insw(unsigned long port, void *dst, unsigned long count)
+{
+ ioread16_rep(ioport_map(port, 2), dst, count);
+}
+
+EXPORT_SYMBOL(ioread16_rep);
+EXPORT_SYMBOL(insw);
+
+
+/*
+ * Read COUNT 32-bit words from port PORT into memory starting at
+ * SRC. Now works with any alignment in SRC. Performance is important,
+ * but the interfaces seems to be slow: just using the inlined version
+ * of the inl() breaks things.
+ */
+void ioread32_rep(void __iomem *port, void *dst, unsigned long count)
+{
+ if (unlikely((unsigned long)dst & 0x3)) {
+ while (count--) {
+ struct S { int x __attribute__((packed)); };
+ ((struct S *)dst)->x = ioread32(port);
+ dst += 4;
+ }
+ } else {
+ /* Buffer 32-bit aligned. */
+ while (count--) {
+ *(unsigned int *)dst = ioread32(port);
+ dst += 4;
+ }
+ }
+}
+
+void insl(unsigned long port, void *dst, unsigned long count)
+{
+ ioread32_rep(ioport_map(port, 4), dst, count);
+}
+
+EXPORT_SYMBOL(ioread32_rep);
+EXPORT_SYMBOL(insl);
+
+
+/*
+ * Like insb but in the opposite direction.
+ * Don't worry as much about doing aligned memory transfers:
+ * doing byte reads the "slow" way isn't nearly as slow as
+ * doing byte writes the slow way (no r-m-w cycle).
+ */
+void iowrite8_rep(void __iomem *port, const void *xsrc, unsigned long count)
+{
+ const unsigned char *src = xsrc;
+ while (count--)
+ iowrite8(*src++, port);
+}
+
+void outsb(unsigned long port, const void *src, unsigned long count)
+{
+ iowrite8_rep(ioport_map(port, 1), src, count);
+}
+
+EXPORT_SYMBOL(iowrite8_rep);
+EXPORT_SYMBOL(outsb);
+
+
+/*
+ * Like insw but in the opposite direction. This is used by the IDE
+ * driver to write disk sectors. Performance is important, but the
+ * interfaces seems to be slow: just using the inlined version of the
+ * outw() breaks things.
+ */
+void iowrite16_rep(void __iomem *port, const void *src, unsigned long count)
+{
+ if (unlikely((unsigned long)src & 0x3)) {
+ if (!count)
+ return;
+ BUG_ON((unsigned long)src & 0x1);
+ iowrite16(*(unsigned short *)src, port);
+ src += 2;
+ --count;
+ }
+
+ while (count >= 2) {
+ unsigned int w;
+ count -= 2;
+ w = *(unsigned int *)src;
+ src += 4;
+ iowrite16(w >> 0, port);
+ iowrite16(w >> 16, port);
+ }
+
+ if (count) {
+ iowrite16(*(unsigned short *)src, port);
+ }
+}
+
+void outsw(unsigned long port, const void *src, unsigned long count)
+{
+ iowrite16_rep(ioport_map(port, 2), src, count);
+}
+
+EXPORT_SYMBOL(iowrite16_rep);
+EXPORT_SYMBOL(outsw);
+
+
+/*
+ * Like insl but in the opposite direction. This is used by the IDE
+ * driver to write disk sectors. Works with any alignment in SRC.
+ * Performance is important, but the interfaces seems to be slow:
+ * just using the inlined version of the outl() breaks things.
+ */
+void iowrite32_rep(void __iomem *port, const void *src, unsigned long count)
+{
+ if (unlikely((unsigned long)src & 0x3)) {
+ while (count--) {
+ struct S { int x __attribute__((packed)); };
+ iowrite32(((struct S *)src)->x, port);
+ src += 4;
+ }
+ } else {
+ /* Buffer 32-bit aligned. */
+ while (count--) {
+ iowrite32(*(unsigned int *)src, port);
+ src += 4;
+ }
+ }
+}
+
+void outsl(unsigned long port, const void *src, unsigned long count)
+{
+ iowrite32_rep(ioport_map(port, 4), src, count);
+}
+
+EXPORT_SYMBOL(iowrite32_rep);
+EXPORT_SYMBOL(outsl);
+
+
+/*
+ * Copy data from IO memory space to "real" memory space.
+ * This needs to be optimized.
+ */
+void memcpy_fromio(void *to, const volatile void __iomem *from, long count)
+{
+ /* Optimize co-aligned transfers. Everything else gets handled
+ a byte at a time. */
+
+ if (count >= 8 && ((u64)to & 7) == ((u64)from & 7)) {
+ count -= 8;
+ do {
+ *(u64 *)to = __raw_readq(from);
+ count -= 8;
+ to += 8;
+ from += 8;
+ } while (count >= 0);
+ count += 8;
+ }
+
+ if (count >= 4 && ((u64)to & 3) == ((u64)from & 3)) {
+ count -= 4;
+ do {
+ *(u32 *)to = __raw_readl(from);
+ count -= 4;
+ to += 4;
+ from += 4;
+ } while (count >= 0);
+ count += 4;
+ }
+
+ if (count >= 2 && ((u64)to & 1) == ((u64)from & 1)) {
+ count -= 2;
+ do {
+ *(u16 *)to = __raw_readw(from);
+ count -= 2;
+ to += 2;
+ from += 2;
+ } while (count >= 0);
+ count += 2;
+ }
+
+ while (count > 0) {
+ *(u8 *) to = __raw_readb(from);
+ count--;
+ to++;
+ from++;
+ }
+ mb();
+}
+
+EXPORT_SYMBOL(memcpy_fromio);
+
+
+/*
+ * Copy data from "real" memory space to IO memory space.
+ * This needs to be optimized.
+ */
+void memcpy_toio(volatile void __iomem *to, const void *from, long count)
+{
+ /* Optimize co-aligned transfers. Everything else gets handled
+ a byte at a time. */
+ /* FIXME -- align FROM. */
+
+ if (count >= 8 && ((u64)to & 7) == ((u64)from & 7)) {
+ count -= 8;
+ do {
+ __raw_writeq(*(const u64 *)from, to);
+ count -= 8;
+ to += 8;
+ from += 8;
+ } while (count >= 0);
+ count += 8;
+ }
+
+ if (count >= 4 && ((u64)to & 3) == ((u64)from & 3)) {
+ count -= 4;
+ do {
+ __raw_writel(*(const u32 *)from, to);
+ count -= 4;
+ to += 4;
+ from += 4;
+ } while (count >= 0);
+ count += 4;
+ }
+
+ if (count >= 2 && ((u64)to & 1) == ((u64)from & 1)) {
+ count -= 2;
+ do {
+ __raw_writew(*(const u16 *)from, to);
+ count -= 2;
+ to += 2;
+ from += 2;
+ } while (count >= 0);
+ count += 2;
+ }
+
+ while (count > 0) {
+ __raw_writeb(*(const u8 *) from, to);
+ count--;
+ to++;
+ from++;
+ }
+ mb();
+}
+
+EXPORT_SYMBOL(memcpy_toio);
+
+
+/*
+ * "memset" on IO memory space.
+ */
+void _memset_c_io(volatile void __iomem *to, unsigned long c, long count)
+{
+ /* Handle any initial odd byte */
+ if (count > 0 && ((u64)to & 1)) {
+ __raw_writeb(c, to);
+ to++;
+ count--;
+ }
+
+ /* Handle any initial odd halfword */
+ if (count >= 2 && ((u64)to & 2)) {
+ __raw_writew(c, to);
+ to += 2;
+ count -= 2;
+ }
+
+ /* Handle any initial odd word */
+ if (count >= 4 && ((u64)to & 4)) {
+ __raw_writel(c, to);
+ to += 4;
+ count -= 4;
+ }
+
+ /* Handle all full-sized quadwords: we're aligned
+ (or have a small count) */
+ count -= 8;
+ if (count >= 0) {
+ do {
+ __raw_writeq(c, to);
+ to += 8;
+ count -= 8;
+ } while (count >= 0);
+ }
+ count += 8;
+
+ /* The tail is word-aligned if we still have count >= 4 */
+ if (count >= 4) {
+ __raw_writel(c, to);
+ to += 4;
+ count -= 4;
+ }
+
+ /* The tail is half-word aligned if we have count >= 2 */
+ if (count >= 2) {
+ __raw_writew(c, to);
+ to += 2;
+ count -= 2;
+ }
+
+ /* And finally, one last byte.. */
+ if (count) {
+ __raw_writeb(c, to);
+ }
+ mb();
+}
+
+EXPORT_SYMBOL(_memset_c_io);
+
+/* A version of memcpy used by the vga console routines to move data around
+ arbitrarily between screen and main memory. */
+
+void
+scr_memcpyw(u16 *d, const u16 *s, unsigned int count)
+{
+ const u16 __iomem *ios = (const u16 __iomem *) s;
+ u16 __iomem *iod = (u16 __iomem *) d;
+ int s_isio = __is_ioaddr(s);
+ int d_isio = __is_ioaddr(d);
+
+ if (s_isio) {
+ if (d_isio) {
+ /* FIXME: Should handle unaligned ops and
+ operation widening. */
+
+ count /= 2;
+ while (count--) {
+ u16 tmp = __raw_readw(ios++);
+ __raw_writew(tmp, iod++);
+ }
+ }
+ else
+ memcpy_fromio(d, ios, count);
+ } else {
+ if (d_isio)
+ memcpy_toio(iod, s, count);
+ else
+ memcpy(d, s, count);
+ }
+}
+
+EXPORT_SYMBOL(scr_memcpyw);
+
+void __iomem *ioport_map(unsigned long port, unsigned int size)
+{
+ return IO_CONCAT(__IO_PREFIX,ioportmap) (port);
+}
+
+void ioport_unmap(void __iomem *addr)
+{
+}
+
+EXPORT_SYMBOL(ioport_map);
+EXPORT_SYMBOL(ioport_unmap);
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+# RMK wants arm kernels compiled with frame pointers so hardwire this to y.
+# If you know what you are doing and are willing to live without stack
+# traces, you can get a slightly smaller kernel by setting this option to
+# n, but then RMK will have to kill you ;).
+config FRAME_POINTER
+ bool
+ default y
+ help
+ If you say N here, the resulting kernel will be slightly smaller and
+ faster. However, when a problem occurs with the kernel, the
+ information that is reported is severely limited. Most people
+ should say Y here.
+
+config DEBUG_USER
+ bool "Verbose user fault messages"
+ help
+ When a user program crashes due to an exception, the kernel can
+ print a brief message explaining what the problem was. This is
+ sometimes helpful for debugging but serves no purpose on a
+ production system. Most people should say N here.
+
+ In addition, you need to pass user_debug=N on the kernel command
+ line to enable this feature. N consists of the sum of:
+
+ 1 - undefined instruction events
+ 2 - system calls
+ 4 - invalid data aborts
+ 8 - SIGSEGV faults
+ 16 - SIGBUS faults
+
+config DEBUG_WAITQ
+ bool "Wait queue debugging"
+ depends on DEBUG_KERNEL
+
+config DEBUG_ERRORS
+ bool "Verbose kernel error messages"
+ depends on DEBUG_KERNEL
+ help
+ This option controls verbose debugging information which can be
+ printed when the kernel detects an internal error. This debugging
+ information is useful to kernel hackers when tracking down problems,
+ but mostly meaningless to other people. It's safe to say Y unless
+ you are concerned with the code size or don't want to see these
+ messages.
+
+config DEBUG_INFO
+ bool "Include GDB debugging information in kernel binary"
+ help
+ Say Y here to include source-level debugging information in the
+ `vmlinux' binary image. This is handy if you want to use gdb or
+ addr2line to debug the kernel. It has no impact on the in-memory
+ footprint of the running kernel but it can increase the amount of
+ time and disk space needed for compilation of the kernel. If in
+ doubt say N.
+
+# These options are only for real kernel hackers who want to get their hands dirty.
+config DEBUG_LL
+ bool "Kernel low-level debugging functions"
+ depends on DEBUG_KERNEL
+ help
+ Say Y here to include definitions of printascii, printchar, printhex
+ in the kernel. This is helpful if you are debugging code that
+ executes before the console is initialized.
+
+config DEBUG_ICEDCC
+ bool "Kernel low-level debugging via EmbeddedICE DCC channel"
+ depends on DEBUG_LL
+ help
+ Say Y here if you want the debug print routines to direct their
+ output to the EmbeddedICE macrocell's DCC channel using
+ co-processor 14. This is known to work on the ARM9 style ICE
+ channel.
+
+ It does include a timeout to ensure that the system does not
+ totally freeze when there is nothing connected to read.
+
+config DEBUG_DC21285_PORT
+ bool "Kernel low-level debugging messages via footbridge serial port"
+ depends on DEBUG_LL && FOOTBRIDGE
+ help
+ Say Y here if you want the debug print routines to direct their
+ output to the serial port in the DC21285 (Footbridge). Saying N
+ will cause the debug messages to appear on the first 16550
+ serial port.
+
+config DEBUG_CLPS711X_UART2
+ bool "Kernel low-level debugging messages via UART2"
+ depends on DEBUG_LL && ARCH_CLPS711X
+ help
+ Say Y here if you want the debug print routines to direct their
+ output to the second serial port on these devices. Saying N will
+ cause the debug messages to appear on the first serial port.
+
+config DEBUG_S3C2410_PORT
+ depends on DEBUG_LL && ARCH_S3C2410
+ bool "Kernel low-level debugging messages via S3C2410 UART"
+ help
+ Say Y here if you want debug print routines to go to one of the
+ S3C2410 internal UARTs. The chosen UART must have been configured
+ before it is used.
+
+config DEBUG_S3C2410_UART
+ depends on DEBUG_LL && ARCH_S3C2410
+ int "S3C2410 UART to use for low-level debug"
+ default "0"
+ help
+ Choice for UART for kernel low-level using S3C2410 UARTS,
+ should be between zero and two. The port must have been
+ initalised by the boot-loader before use.
+
+endmenu
--- /dev/null
+/*
+ * linux/arch/arm/boot/compressed/big-endian.S
+ *
+ * Switch CPU into big endian mode.
+ * Author: Nicolas Pitre
+ */
+
+ .section ".start", #alloc, #execinstr
+
+ mrc p15, 0, r0, c1, c0, 0 @ read control reg
+ orr r0, r0, #(1 << 7) @ enable big endian mode
+ mcr p15, 0, r0, c1, c0, 0 @ write control reg
+
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+CONFIG_ARCH_IXP2000=y
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+
+#
+# Intel IXP2400/2800 Implementation Options
+#
+
+#
+# IXP2400/2800 Platforms
+#
+CONFIG_ARCH_ENP2611=y
+# CONFIG_ARCH_IXDP2400 is not set
+# CONFIG_ARCH_IXDP2800 is not set
+# CONFIG_ARCH_IXDP2401 is not set
+# CONFIG_ARCH_IXDP2801 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_IXP2000=y
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_EEPRO100_PIO is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+CONFIG_WAN=y
+# CONFIG_LANMEDIA is not set
+# CONFIG_SYNCLINK_SYNCPPP is not set
+CONFIG_HDLC=y
+CONFIG_HDLC_RAW=y
+# CONFIG_HDLC_RAW_ETH is not set
+CONFIG_HDLC_CISCO=y
+CONFIG_HDLC_FR=y
+CONFIG_HDLC_PPP=y
+
+#
+# X.25/LAPB support is disabled
+#
+# CONFIG_PCI200SYN is not set
+# CONFIG_WANXL is not set
+# CONFIG_PC300 is not set
+# CONFIG_FARSYNC is not set
+CONFIG_DLCI=y
+CONFIG_DLCI_COUNT=24
+CONFIG_DLCI_MAX=8
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_IXP2000_WATCHDOG=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_IXP2000 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_BDI2000_XSCALE is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+CONFIG_ARCH_IOP3XX=y
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+
+#
+# IOP3xx Implementation Options
+#
+
+#
+# IOP3xx Platform Types
+#
+# CONFIG_ARCH_IQ80321 is not set
+CONFIG_ARCH_IQ31244=y
+# CONFIG_ARCH_IQ80331 is not set
+CONFIG_ARCH_EP80219=y
+CONFIG_ARCH_IOP321=y
+# CONFIG_ARCH_IOP331 is not set
+
+#
+# IOP3xx Chipset Features
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_PCI_LEGACY_PROC is not set
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200 mem=128M@0xa0000000"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+# CONFIG_MD_LINEAR is not set
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID5=y
+# CONFIG_MD_RAID6 is not set
+# CONFIG_MD_MULTIPATH is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+CONFIG_E100_NAPI=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA6322 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+CONFIG_I2C_IOP3XX=y
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_SECURITY=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V4 is not set
+# CONFIG_NFSD_TCP is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_KERNEL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.9-rc1
+# Thu Sep 2 11:04:11 2004
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+# CONFIG_ARCH_IMX is not set
+CONFIG_ARCH_H720X=y
+
+#
+# h720x Implementations
+#
+CONFIG_ARCH_H7201=y
+# CONFIG_ARCH_H7202 is not set
+CONFIG_CPU_H7201=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM720T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_LV4T=y
+CONFIG_CPU_CACHE_V4=y
+CONFIG_CPU_COPY_V4WT=y
+CONFIG_CPU_TLB_V4WT=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+
+#
+# General setup
+#
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE=""
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_H720X is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+# CONFIG_NET is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+# CONFIG_SND is not set
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_INFO is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.9-rc1
+# Thu Sep 30 10:30:42 2004
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+# CONFIG_ARCH_IMX is not set
+CONFIG_ARCH_H720X=y
+
+#
+# h720x Implementations
+#
+# CONFIG_ARCH_H7201 is not set
+CONFIG_ARCH_H7202=y
+# CONFIG_ARCH_FU7202 is not set
+CONFIG_CPU_H7202=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM720T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_LV4T=y
+CONFIG_CPU_CACHE_V4=y
+CONFIG_CPU_COPY_V4WT=y
+CONFIG_CPU_TLB_V4WT=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+
+#
+# General setup
+#
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,19200"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+CONFIG_MTD_H720X=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_SMC91X is not set
+# CONFIG_CS89x0 is not set
+CONFIG_CIRRUS=y
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+CONFIG_SERIO_H7202=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+# CONFIG_ROOT_NFS is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+
+#
+# Logo configuration
+#
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_SA1100 is not set
+CONFIG_USB_GADGET_H7202=y
+CONFIG_USB_H7202=m
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_FILE_STORAGE_TEST=y
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_MULTISER=m
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+CONFIG_ARCH_IOP3XX=y
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+
+#
+# IOP3xx Implementation Options
+#
+
+#
+# IOP3xx Platform Types
+#
+# CONFIG_ARCH_IQ80321 is not set
+CONFIG_ARCH_IQ31244=y
+# CONFIG_ARCH_IQ80331 is not set
+# CONFIG_ARCH_EP80219 is not set
+CONFIG_ARCH_IOP321=y
+# CONFIG_ARCH_IOP331 is not set
+
+#
+# IOP3xx Chipset Features
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_PCI_LEGACY_PROC is not set
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200 mem=256M@0xa0000000"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+# CONFIG_MD_LINEAR is not set
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID5=y
+# CONFIG_MD_RAID6 is not set
+# CONFIG_MD_MULTIPATH is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+# CONFIG_NET_ETHERNET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+CONFIG_E1000_NAPI=y
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA6322 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+CONFIG_I2C_IOP3XX=y
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_SECURITY=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V4 is not set
+# CONFIG_NFSD_TCP is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_KERNEL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+CONFIG_ARCH_IOP3XX=y
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+
+#
+# IOP3xx Implementation Options
+#
+
+#
+# IOP3xx Platform Types
+#
+# CONFIG_ARCH_IQ80321 is not set
+# CONFIG_ARCH_IQ31244 is not set
+CONFIG_ARCH_IQ80331=y
+# CONFIG_ARCH_EP80219 is not set
+CONFIG_ARCH_IOP331=y
+
+#
+# IOP3xx Chipset Features
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_PCI_LEGACY_PROC is not set
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200 mem=128M@0x00000000"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_LINEAR=y
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID5=y
+# CONFIG_MD_RAID6 is not set
+# CONFIG_MD_MULTIPATH is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+# CONFIG_NET_ETHERNET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+CONFIG_E1000_NAPI=y
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA6322 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_SECURITY=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V4 is not set
+# CONFIG_NFSD_TCP is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+CONFIG_ARCH_IXP2000=y
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+
+#
+# Intel IXP2400/2800 Implementation Options
+#
+
+#
+# IXP2400/2800 Platforms
+#
+# CONFIG_ARCH_ENP2611 is not set
+CONFIG_ARCH_IXDP2400=y
+# CONFIG_ARCH_IXDP2800 is not set
+CONFIG_ARCH_IXDP2X00=y
+# CONFIG_ARCH_IXDP2401 is not set
+# CONFIG_ARCH_IXDP2801 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_IXP2000=y
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_EEPRO100_PIO is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+CONFIG_WAN=y
+# CONFIG_LANMEDIA is not set
+# CONFIG_SYNCLINK_SYNCPPP is not set
+CONFIG_HDLC=y
+CONFIG_HDLC_RAW=y
+# CONFIG_HDLC_RAW_ETH is not set
+CONFIG_HDLC_CISCO=y
+CONFIG_HDLC_FR=y
+CONFIG_HDLC_PPP=y
+
+#
+# X.25/LAPB support is disabled
+#
+# CONFIG_PCI200SYN is not set
+# CONFIG_WANXL is not set
+# CONFIG_PC300 is not set
+# CONFIG_FARSYNC is not set
+CONFIG_DLCI=y
+CONFIG_DLCI_COUNT=24
+CONFIG_DLCI_MAX=8
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_IXP2000_WATCHDOG=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_IXP2000 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_BDI2000_XSCALE is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+CONFIG_ARCH_IXP2000=y
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+
+#
+# Intel IXP2400/2800 Implementation Options
+#
+
+#
+# IXP2400/2800 Platforms
+#
+# CONFIG_ARCH_ENP2611 is not set
+# CONFIG_ARCH_IXDP2400 is not set
+# CONFIG_ARCH_IXDP2800 is not set
+CONFIG_ARCH_IXDP2401=y
+# CONFIG_ARCH_IXDP2801 is not set
+CONFIG_ARCH_IXDP2X01=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_IXP2000=y
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+CONFIG_CS89x0=y
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_EEPRO100_PIO is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+CONFIG_WAN=y
+# CONFIG_LANMEDIA is not set
+# CONFIG_SYNCLINK_SYNCPPP is not set
+CONFIG_HDLC=y
+CONFIG_HDLC_RAW=y
+# CONFIG_HDLC_RAW_ETH is not set
+CONFIG_HDLC_CISCO=y
+CONFIG_HDLC_FR=y
+CONFIG_HDLC_PPP=y
+
+#
+# X.25/LAPB support is disabled
+#
+# CONFIG_PCI200SYN is not set
+# CONFIG_WANXL is not set
+# CONFIG_PC300 is not set
+# CONFIG_FARSYNC is not set
+CONFIG_DLCI=y
+CONFIG_DLCI_COUNT=24
+CONFIG_DLCI_MAX=8
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_IXP2000_WATCHDOG=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_IXP2000 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_BDI2000_XSCALE is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+CONFIG_ARCH_IXP2000=y
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+
+#
+# Intel IXP2400/2800 Implementation Options
+#
+
+#
+# IXP2400/2800 Platforms
+#
+# CONFIG_ARCH_ENP2611 is not set
+# CONFIG_ARCH_IXDP2400 is not set
+CONFIG_ARCH_IXDP2800=y
+CONFIG_ARCH_IXDP2X00=y
+# CONFIG_ARCH_IXDP2401 is not set
+# CONFIG_ARCH_IXDP2801 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,9600 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_IXP2000=y
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_EEPRO100_PIO is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+CONFIG_WAN=y
+# CONFIG_LANMEDIA is not set
+# CONFIG_SYNCLINK_SYNCPPP is not set
+CONFIG_HDLC=y
+CONFIG_HDLC_RAW=y
+# CONFIG_HDLC_RAW_ETH is not set
+CONFIG_HDLC_CISCO=y
+CONFIG_HDLC_FR=y
+CONFIG_HDLC_PPP=y
+
+#
+# X.25/LAPB support is disabled
+#
+# CONFIG_PCI200SYN is not set
+# CONFIG_WANXL is not set
+# CONFIG_PC300 is not set
+# CONFIG_FARSYNC is not set
+CONFIG_DLCI=y
+CONFIG_DLCI_COUNT=24
+CONFIG_DLCI_MAX=8
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_IXP2000_WATCHDOG=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_IXP2000 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_BDI2000_XSCALE is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+CONFIG_ARCH_IXP2000=y
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+
+#
+# Intel IXP2400/2800 Implementation Options
+#
+
+#
+# IXP2400/2800 Platforms
+#
+# CONFIG_ARCH_ENP2611 is not set
+# CONFIG_ARCH_IXDP2400 is not set
+# CONFIG_ARCH_IXDP2800 is not set
+# CONFIG_ARCH_IXDP2401 is not set
+CONFIG_ARCH_IXDP2801=y
+CONFIG_ARCH_IXDP2X01=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_XSCALE_PMU=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp mem=64M@0x0 pci=firmware ixdp2x01_clock=50000000"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_IXP2000=y
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_PCI is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+CONFIG_CS89x0=y
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_EEPRO100_PIO is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+CONFIG_WAN=y
+# CONFIG_LANMEDIA is not set
+# CONFIG_SYNCLINK_SYNCPPP is not set
+CONFIG_HDLC=y
+CONFIG_HDLC_RAW=y
+# CONFIG_HDLC_RAW_ETH is not set
+CONFIG_HDLC_CISCO=y
+CONFIG_HDLC_FR=y
+CONFIG_HDLC_PPP=y
+
+#
+# X.25/LAPB support is disabled
+#
+# CONFIG_PCI200SYN is not set
+# CONFIG_WANXL is not set
+# CONFIG_PC300 is not set
+# CONFIG_FARSYNC is not set
+CONFIG_DLCI=y
+CONFIG_DLCI_COUNT=24
+CONFIG_DLCI_MAX=8
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_IXP2000_WATCHDOG=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_IXP2000 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_BDI2000_XSCALE is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_STANDALONE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_IOSCHED_NOOP is not set
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
+CONFIG_ARCH_IMX=y
+
+#
+# IMX Implementations
+#
+CONFIG_ARCH_MX1ADS=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# General setup
+#
+CONFIG_ISA=y
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_CPU_FREQ is not set
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+CONFIG_FPE_FASTFPE=y
+# CONFIG_VFP is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_PM is not set
+CONFIG_PREEMPT=y
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttySMX0,57600n8 ip=bootp root=/dev/nfs"
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_MX1ADS=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_SMC91X is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Userland interfaces
+#
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=m
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Library routines
+#
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+/*
+ * linux/arch/arm/kernel/iwmmxt.S
+ *
+ * XScale iWMMXt (Concan) context switching and handling
+ *
+ * Initial code:
+ * Copyright (c) 2003, Intel Corporation
+ *
+ * Full lazy switching support, optimizations and more, by Nicolas Pitre
+* Copyright (c) 2003-2004, MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+#include <asm/thread_info.h>
+#include <asm/constants.h>
+
+#define MMX_WR0 (0x00)
+#define MMX_WR1 (0x08)
+#define MMX_WR2 (0x10)
+#define MMX_WR3 (0x18)
+#define MMX_WR4 (0x20)
+#define MMX_WR5 (0x28)
+#define MMX_WR6 (0x30)
+#define MMX_WR7 (0x38)
+#define MMX_WR8 (0x40)
+#define MMX_WR9 (0x48)
+#define MMX_WR10 (0x50)
+#define MMX_WR11 (0x58)
+#define MMX_WR12 (0x60)
+#define MMX_WR13 (0x68)
+#define MMX_WR14 (0x70)
+#define MMX_WR15 (0x78)
+#define MMX_WCSSF (0x80)
+#define MMX_WCASF (0x84)
+#define MMX_WCGR0 (0x88)
+#define MMX_WCGR1 (0x8C)
+#define MMX_WCGR2 (0x90)
+#define MMX_WCGR3 (0x94)
+
+#define MMX_SIZE (0x98)
+
+ .text
+
+/*
+ * Lazy switching of Concan coprocessor context
+ *
+ * r10 = struct thread_info pointer
+ * r9 = ret_from_exception
+ * lr = undefined instr exit
+ *
+ * called from prefetch exception handler with interrupts disabled
+ */
+
+ENTRY(iwmmxt_task_enable)
+
+ mrc p15, 0, r2, c15, c1, 0
+ tst r2, #0x3 @ CP0 and CP1 accessible?
+ movne pc, lr @ if so no business here
+ orr r2, r2, #0x3 @ enable access to CP0 and CP1
+ mcr p15, 0, r2, c15, c1, 0
+
+ ldr r3, =concan_owner
+ add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
+ ldr r2, [sp, #60] @ current task pc value
+ ldr r1, [r3] @ get current Concan owner
+ str r0, [r3] @ this task now owns Concan regs
+ sub r2, r2, #4 @ adjust pc back
+ str r2, [sp, #60]
+
+ mrc p15, 0, r2, c2, c0, 0
+ mov r2, r2 @ cpwait
+
+ teq r1, #0 @ test for last ownership
+ mov lr, r9 @ normal exit from exception
+ beq concan_load @ no owner, skip save
+
+concan_save:
+
+ tmrc r2, wCon
+
+ @ CUP? wCx
+ tst r2, #0x1
+ beq 1f
+
+concan_dump:
+
+ wstrw wCSSF, [r1, #MMX_WCSSF]
+ wstrw wCASF, [r1, #MMX_WCASF]
+ wstrw wCGR0, [r1, #MMX_WCGR0]
+ wstrw wCGR1, [r1, #MMX_WCGR1]
+ wstrw wCGR2, [r1, #MMX_WCGR2]
+ wstrw wCGR3, [r1, #MMX_WCGR3]
+
+1: @ MUP? wRn
+ tst r2, #0x2
+ beq 2f
+
+ wstrd wR0, [r1, #MMX_WR0]
+ wstrd wR1, [r1, #MMX_WR1]
+ wstrd wR2, [r1, #MMX_WR2]
+ wstrd wR3, [r1, #MMX_WR3]
+ wstrd wR4, [r1, #MMX_WR4]
+ wstrd wR5, [r1, #MMX_WR5]
+ wstrd wR6, [r1, #MMX_WR6]
+ wstrd wR7, [r1, #MMX_WR7]
+ wstrd wR8, [r1, #MMX_WR8]
+ wstrd wR9, [r1, #MMX_WR9]
+ wstrd wR10, [r1, #MMX_WR10]
+ wstrd wR11, [r1, #MMX_WR11]
+ wstrd wR12, [r1, #MMX_WR12]
+ wstrd wR13, [r1, #MMX_WR13]
+ wstrd wR14, [r1, #MMX_WR14]
+ wstrd wR15, [r1, #MMX_WR15]
+
+2: teq r0, #0 @ anything to load?
+ moveq pc, lr
+
+concan_load:
+
+ @ Load wRn
+ wldrd wR0, [r0, #MMX_WR0]
+ wldrd wR1, [r0, #MMX_WR1]
+ wldrd wR2, [r0, #MMX_WR2]
+ wldrd wR3, [r0, #MMX_WR3]
+ wldrd wR4, [r0, #MMX_WR4]
+ wldrd wR5, [r0, #MMX_WR5]
+ wldrd wR6, [r0, #MMX_WR6]
+ wldrd wR7, [r0, #MMX_WR7]
+ wldrd wR8, [r0, #MMX_WR8]
+ wldrd wR9, [r0, #MMX_WR9]
+ wldrd wR10, [r0, #MMX_WR10]
+ wldrd wR11, [r0, #MMX_WR11]
+ wldrd wR12, [r0, #MMX_WR12]
+ wldrd wR13, [r0, #MMX_WR13]
+ wldrd wR14, [r0, #MMX_WR14]
+ wldrd wR15, [r0, #MMX_WR15]
+
+ @ Load wCx
+ wldrw wCSSF, [r0, #MMX_WCSSF]
+ wldrw wCASF, [r0, #MMX_WCASF]
+ wldrw wCGR0, [r0, #MMX_WCGR0]
+ wldrw wCGR1, [r0, #MMX_WCGR1]
+ wldrw wCGR2, [r0, #MMX_WCGR2]
+ wldrw wCGR3, [r0, #MMX_WCGR3]
+
+ @ clear CUP/MUP (only if r1 != 0)
+ teq r1, #0
+ mov r2, #0
+ moveq pc, lr
+ tmcr wCon, r2
+ mov pc, lr
+
+/*
+ * Back up Concan regs to save area and disable access to them
+ * (mainly for gdb or sleep mode usage)
+ *
+ * r0 = struct thread_info pointer of target task or NULL for any
+ */
+
+ENTRY(iwmmxt_task_disable)
+
+ stmfd sp!, {r4, lr}
+
+ mrs ip, cpsr
+ orr r2, ip, #PSR_I_BIT @ disable interrupts
+ msr cpsr_c, r2
+
+ ldr r3, =concan_owner
+ add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
+ ldr r1, [r3] @ get current Concan owner
+ teq r1, #0 @ any current owner?
+ beq 1f @ no: quit
+ teq r0, #0 @ any owner?
+ teqne r1, r2 @ or specified one?
+ bne 1f @ no: quit
+
+ mrc p15, 0, r4, c15, c1, 0
+ orr r4, r4, #0x3 @ enable access to CP0 and CP1
+ mcr p15, 0, r4, c15, c1, 0
+ mov r0, #0 @ nothing to load
+ str r0, [r3] @ no more current owner
+ mrc p15, 0, r2, c2, c0, 0
+ mov r2, r2 @ cpwait
+ bl concan_save
+
+ bic r4, r4, #0x3 @ disable access to CP0 and CP1
+ mcr p15, 0, r4, c15, c1, 0
+ mrc p15, 0, r2, c2, c0, 0
+ mov r2, r2 @ cpwait
+
+1: msr cpsr_c, ip @ restore interrupt mode
+ ldmfd sp!, {r4, pc}
+
+/*
+ * Copy Concan state to given memory address
+ *
+ * r0 = struct thread_info pointer of target task
+ * r1 = memory address where to store Concan state
+ *
+ * this is called mainly in the creation of signal stack frames
+ */
+
+ENTRY(iwmmxt_task_copy)
+
+ mrs ip, cpsr
+ orr r2, ip, #PSR_I_BIT @ disable interrupts
+ msr cpsr_c, r2
+
+ ldr r3, =concan_owner
+ add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
+ ldr r3, [r3] @ get current Concan owner
+ teq r2, r3 @ does this task own it...
+ beq 1f
+
+ @ current Concan values are in the task save area
+ msr cpsr_c, ip @ restore interrupt mode
+ mov r0, r1
+ mov r1, r2
+ mov r2, #MMX_SIZE
+ b memcpy
+
+1: @ this task owns Concan regs -- grab a copy from there
+ mov r0, #0 @ nothing to load
+ mov r2, #3 @ save all regs
+ mov r3, lr @ preserve return address
+ bl concan_dump
+ msr cpsr_c, ip @ restore interrupt mode
+ mov pc, r3
+
+/*
+ * Restore Concan state from given memory address
+ *
+ * r0 = struct thread_info pointer of target task
+ * r1 = memory address where to get Concan state from
+ *
+ * this is used to restore Concan state when unwinding a signal stack frame
+ */
+
+ENTRY(iwmmxt_task_restore)
+
+ mrs ip, cpsr
+ orr r2, ip, #PSR_I_BIT @ disable interrupts
+ msr cpsr_c, r2
+
+ ldr r3, =concan_owner
+ add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
+ ldr r3, [r3] @ get current Concan owner
+ bic r2, r2, #0x7 @ 64-bit alignment
+ teq r2, r3 @ does this task own it...
+ beq 1f
+
+ @ this task doesn't own Concan regs -- use its save area
+ msr cpsr_c, ip @ restore interrupt mode
+ mov r0, r2
+ mov r2, #MMX_SIZE
+ b memcpy
+
+1: @ this task owns Concan regs -- load them directly
+ mov r0, r1
+ mov r1, #0 @ don't clear CUP/MUP
+ mov r3, lr @ preserve return address
+ bl concan_load
+ msr cpsr_c, ip @ restore interrupt mode
+ mov pc, r3
+
+/*
+ * Concan handling on task switch
+ *
+ * r0 = previous task_struct pointer (must be preserved)
+ * r1 = previous thread_info pointer
+ * r2 = next thread_info.cpu_domain pointer (must be preserved)
+ *
+ * Called only from __switch_to with task preemption disabled.
+ * No need to care about preserving r4 and above.
+ */
+ENTRY(iwmmxt_task_switch)
+
+ mrc p15, 0, r4, c15, c1, 0
+ tst r4, #0x3 @ CP0 and CP1 accessible?
+ bne 1f @ yes: block them for next task
+
+ ldr r5, =concan_owner
+ add r6, r2, #(TI_IWMMXT_STATE - TI_CPU_DOMAIN) @ get next task Concan save area
+ ldr r5, [r5] @ get current Concan owner
+ teq r5, r6 @ next task owns it?
+ movne pc, lr @ no: leave Concan disabled
+
+1: eor r4, r4, #3 @ flip Concan access
+ mcr p15, 0, r4, c15, c1, 0
+
+ mrc p15, 0, r4, c2, c0, 0
+ sub pc, lr, r4, lsr #32 @ cpwait and return
+
+/*
+ * Remove Concan ownership of given task
+ *
+ * r0 = struct thread_info pointer
+ */
+ENTRY(iwmmxt_task_release)
+
+ mrs r2, cpsr
+ orr ip, r2, #PSR_I_BIT @ disable interrupts
+ msr cpsr_c, ip
+ ldr r3, =concan_owner
+ add r0, r0, #TI_IWMMXT_STATE @ get task Concan save area
+ ldr r1, [r3] @ get current Concan owner
+ eors r0, r0, r1 @ if equal...
+ streq r0, [r3] @ then clear ownership
+ msr cpsr_c, r2 @ restore interrupts
+ mov pc, lr
+
+ .data
+concan_owner:
+ .word 0
+
--- /dev/null
+menu "h720x Implementations"
+
+config ARCH_H7201
+ bool "gms30c7201"
+ depends on ARCH_H720X
+ select CPU_H7201
+ help
+ Say Y here if you are using the Hynix GMS30C7201 Reference Board
+
+config ARCH_H7202
+ bool "hms30c7202"
+ select CPU_H7202
+ depends on ARCH_H720X
+ help
+ Say Y here if you are using the Hynix HMS30C7202 Reference Board
+
+endmenu
+
+config CPU_H7201
+ bool
+ help
+ Select code specific to h7201 variants
+
+config CPU_H7202
+ bool
+ help
+ Select code specific to h7202 variants
--- /dev/null
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := common.o
+obj-m :=
+obj-n :=
+obj- :=
+
+# Specific board support
+
+obj-$(CONFIG_ARCH_H7201) += h7201-eval.o
+obj-$(CONFIG_ARCH_H7202) += h7202-eval.o
+obj-$(CONFIG_CPU_H7201) += cpu-h7201.o
+obj-$(CONFIG_CPU_H7202) += cpu-h7202.o
--- /dev/null
+/*
+ * linux/arch/arm/mach-h720x/common.c
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * common stuff for Hynix h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/mman.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <asm/arch/irqs.h>
+
+#include <asm/mach/dma.h>
+
+#if 0
+#define IRQDBG(args...) printk(args)
+#else
+#define IRQDBG(args...) do {} while(0)
+#endif
+
+void __init arch_dma_init(dma_t *dma)
+{
+}
+
+/*
+ * Return usecs since last timer reload
+ * (timercount * (usecs perjiffie)) / (ticks per jiffie)
+ */
+unsigned long h720x_gettimeoffset(void)
+{
+ return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
+}
+
+/*
+ * mask Global irq's
+ */
+static void mask_global_irq (unsigned int irq )
+{
+ CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
+}
+
+/*
+ * unmask Global irq's
+ */
+static void unmask_global_irq (unsigned int irq )
+{
+ CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
+}
+
+
+/*
+ * ack GPIO irq's
+ * Ack only for edge triggered int's valid
+ */
+static void inline ack_gpio_irq(u32 irq)
+{
+ u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
+ u32 bit = IRQ_TO_BIT(irq);
+ if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
+ CPU_REG (reg_base, GPIO_CLR) = bit;
+}
+
+/*
+ * mask GPIO irq's
+ */
+static void inline mask_gpio_irq(u32 irq)
+{
+ u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
+ u32 bit = IRQ_TO_BIT(irq);
+ CPU_REG (reg_base, GPIO_MASK) &= ~bit;
+}
+
+/*
+ * unmask GPIO irq's
+ */
+static void inline unmask_gpio_irq(u32 irq)
+{
+ u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
+ u32 bit = IRQ_TO_BIT(irq);
+ CPU_REG (reg_base, GPIO_MASK) |= bit;
+}
+
+static void
+h720x_gpio_handler(unsigned int mask, unsigned int irq,
+ struct irqdesc *desc, struct pt_regs *regs)
+{
+ IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
+ desc = irq_desc + irq;
+ while (mask) {
+ if (mask & 1) {
+ IRQDBG("handling irq %d\n", irq);
+ desc->handle(irq, desc, regs);
+ }
+ irq++;
+ desc++;
+ mask >>= 1;
+ }
+}
+
+static void
+h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
+ irq = IRQ_CHAINED_GPIOA(0);
+ IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ h720x_gpio_handler(mask, irq, desc, regs);
+}
+
+static void
+h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+ mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
+ irq = IRQ_CHAINED_GPIOB(0);
+ IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ h720x_gpio_handler(mask, irq, desc, regs);
+}
+
+static void
+h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
+ irq = IRQ_CHAINED_GPIOC(0);
+ IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ h720x_gpio_handler(mask, irq, desc, regs);
+}
+
+static void
+h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
+ irq = IRQ_CHAINED_GPIOD(0);
+ IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ h720x_gpio_handler(mask, irq, desc, regs);
+}
+
+#ifdef CONFIG_CPU_H7202
+static void
+h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
+ irq = IRQ_CHAINED_GPIOE(0);
+ IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ h720x_gpio_handler(mask, irq, desc, regs);
+}
+#endif
+
+static struct irqchip h720x_global_chip = {
+ .ack = mask_global_irq,
+ .mask = mask_global_irq,
+ .unmask = unmask_global_irq,
+};
+
+static struct irqchip h720x_gpio_chip = {
+ .ack = ack_gpio_irq,
+ .mask = mask_gpio_irq,
+ .unmask = unmask_gpio_irq,
+};
+
+/*
+ * Initialize IRQ's, mask all, enable multiplexed irq's
+ */
+void __init h720x_init_irq (void)
+{
+ int irq;
+
+ /* Mask global irq's */
+ CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
+
+ /* Mask all multiplexed irq's */
+ CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
+ CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
+ CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
+ CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
+
+ /* Initialize global IRQ's, fast path */
+ for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
+ set_irq_chip(irq, &h720x_global_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ }
+
+ /* Initialize multiplexed IRQ's, slow path */
+ for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
+ set_irq_chip(irq, &h720x_gpio_chip);
+ set_irq_handler(irq, do_edge_IRQ);
+ set_irq_flags(irq, IRQF_VALID );
+ }
+ set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
+ set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
+ set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
+ set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
+
+#ifdef CONFIG_CPU_H7202
+ for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
+ set_irq_chip(irq, &h720x_gpio_chip);
+ set_irq_handler(irq, do_edge_IRQ);
+ set_irq_flags(irq, IRQF_VALID );
+ }
+ set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
+#endif
+
+ /* Enable multiplexed irq's */
+ CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
+}
+
+static struct map_desc h720x_io_desc[] __initdata = {
+ { IO_VIRT, IO_PHYS, IO_SIZE, MT_DEVICE },
+};
+
+/* Initialize io tables */
+void __init h720x_map_io(void)
+{
+ iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-h720x/cpu-h7201.c
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * processor specific stuff for the Hynix h7201
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <asm/types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/arch/irqs.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+extern unsigned long h720x_gettimeoffset(void);
+extern void __init h720x_init_irq (void);
+
+/*
+ * Timer interrupt handler
+ */
+static irqreturn_t
+h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
+ timer_tick(regs);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction h7201_timer_irq = {
+ .name = "h7201 Timer Tick",
+ .flags = SA_INTERRUPT,
+ .handler = h7201_timer_interrupt
+};
+
+/*
+ * Setup TIMER0 as system timer
+ */
+void __init h7201_init_time(void)
+{
+ gettimeoffset = h720x_gettimeoffset;
+
+ CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
+ CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
+ CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
+ CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
+
+ setup_irq(IRQ_TIMER0, &h7201_timer_irq);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-h720x/cpu-h7202.c
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * processor specific stuff for the Hynix h7201
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <asm/types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/arch/irqs.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <linux/device.h>
+
+static struct resource h7202ps2_resources[] = {
+ [0] = {
+ .start = 0x8002c000,
+ .end = 0x8002c040,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_PS2,
+ .end = IRQ_PS2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device h7202ps2_device = {
+ .name = "h7202ps2",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(h7202ps2_resources),
+ .resource = h7202ps2_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &h7202ps2_device,
+};
+
+extern unsigned long h720x_gettimeoffset(void);
+extern void __init h720x_init_irq (void);
+
+/* Although we have two interrupt lines for the timers, we only have one
+ * status register which clears all pending timer interrupts on reading. So
+ * we have to handle all timer interrupts in one place.
+ */
+static void
+h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
+
+ if ( mask & TSTAT_T0INT ) {
+ timer_tick(regs);
+ if( mask == TSTAT_T0INT )
+ return;
+ }
+
+ mask >>= 1;
+ irq = IRQ_TIMER1;
+ desc = irq_desc + irq;
+ while (mask) {
+ if (mask & 1)
+ desc->handle(irq, desc, regs);
+ irq++;
+ desc++;
+ mask >>= 1;
+ }
+}
+
+/*
+ * Timer interrupt handler
+ */
+static irqreturn_t
+h7202_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ h7202_timerx_demux_handler(0, NULL, regs);
+ return IRQ_HANDLED;
+}
+
+/*
+ * mask multiplexed timer irq's
+ */
+static void inline mask_timerx_irq (u32 irq)
+{
+ unsigned int bit;
+ bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
+ CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
+}
+
+/*
+ * unmask multiplexed timer irq's
+ */
+static void inline unmask_timerx_irq (u32 irq)
+{
+ unsigned int bit;
+ bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
+ CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
+}
+
+static struct irqchip h7202_timerx_chip = {
+ .ack = mask_timerx_irq,
+ .mask = mask_timerx_irq,
+ .unmask = unmask_timerx_irq,
+};
+
+static struct irqaction h7202_timer_irq = {
+ .name = "h7202 Timer Tick",
+ .flags = SA_INTERRUPT,
+ .handler = h7202_timer_interrupt
+};
+
+/*
+ * Setup TIMER0 as system timer
+ */
+void __init h7202_init_time(void)
+{
+ gettimeoffset = h720x_gettimeoffset;
+
+ CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
+ CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
+ CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
+ CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
+
+ setup_irq(IRQ_TIMER0, &h7202_timer_irq);
+}
+
+void __init h7202_init_irq (void)
+{
+ int irq;
+
+ CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
+
+ for (irq = IRQ_TIMER1;
+ irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
+ mask_timerx_irq(irq);
+ set_irq_chip(irq, &h7202_timerx_chip);
+ set_irq_handler(irq, do_edge_IRQ);
+ set_irq_flags(irq, IRQF_VALID );
+ }
+ set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
+
+ h720x_init_irq();
+}
+
+void __init init_hw_h7202(void)
+{
+ /* Enable clocks */
+ CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
+
+ (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-h720x/h7201-eval.c
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Architecture specific stuff for Hynix GMS30C7201 development board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/device.h>
+
+#include <asm/setup.h>
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware.h>
+
+extern void h720x_init_irq (void);
+extern void h7201_init_time(void);
+extern void __init h720x_map_io(void);
+
+MACHINE_START(H7201, "Hynix GMS30C7201")
+ MAINTAINER("Robert Schwebel, Pengutronix")
+ BOOT_MEM(0x40000000, 0x80000000, 0xf0000000)
+ BOOT_PARAMS(0xc0001000)
+ MAPIO(h720x_map_io)
+ INITIRQ(h720x_init_irq)
+ INITTIME(h7201_init_time)
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-h720x/h7202-eval.c
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Architecture specific stuff for Hynix HMS30C7202 development board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/device.h>
+
+#include <asm/setup.h>
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware.h>
+
+extern void __init init_hw_h7202(void);
+extern void __init h7202_init_irq (void);
+extern void __init h7202_init_time(void);
+extern void __init h720x_map_io(void);
+
+static struct resource cirrus_resources[] = {
+ [0] = {
+ .start = ETH0_PHYS + 0x300,
+ .end = ETH0_PHYS + 0x300 + 0x10,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CHAINED_GPIOB(8),
+ .end = IRQ_CHAINED_GPIOB(8),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device cirrus_device = {
+ .name = "cirrus-cs89x0",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(cirrus_resources),
+ .resource = cirrus_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &cirrus_device,
+};
+
+/*
+ * Hardware init. This is called early in initcalls
+ * Place pin inits here. So you avoid adding ugly
+ * #ifdef stuff to common drivers.
+ * Use this only, if your bootloader is not able
+ * to initialize the pins proper.
+ */
+static void __init init_eval_h7202(void)
+{
+ init_hw_h7202();
+ (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ /* Enable interrupt on portb bit 8 (ethernet) */
+ CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
+ CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
+}
+
+MACHINE_START(H7202, "Hynix HMS30C7202")
+ MAINTAINER("Robert Schwebel, Pengutronix")
+ BOOT_MEM(0x40000000, 0x80000000, 0xf0000000)
+ BOOT_PARAMS(0x40000100)
+ MAPIO(h720x_map_io)
+ INITIRQ(h7202_init_irq)
+ INITTIME(h7202_init_time)
+ INIT_MACHINE(init_eval_h7202)
+MACHINE_END
--- /dev/null
+menu "IMX Implementations"
+ depends on ARCH_IMX
+
+config ARCH_MX1ADS
+ bool "mx1ads"
+ depends on ARCH_IMX
+ help
+ Say Y here if you are using the Motorola MX1ADS board
+
+endmenu
--- /dev/null
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+# Object file lists.
+
+obj-y += irq.o time.o dma.o generic.o
+
+# Specific board support
+obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
+
+# Support for blinky lights
+led-y := leds.o
+
+obj-$(CONFIG_LEDS) += $(led-y)
+led-$(CONFIG_ARCH_MX1ADS) += leds-mx1ads.o
--- /dev/null
+/*
+ * linux/arch/arm/mach-imx/dma.c
+ *
+ * imx DMA registration and IRQ dispatching
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
+ * initial version heavily inspired by
+ * linux/arch/arm/mach-pxa/dma.c
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/dma.h>
+
+static struct dma_channel {
+ char *name;
+ void (*irq_handler) (int, void *, struct pt_regs *);
+ void (*err_handler) (int, void *, struct pt_regs *);
+ void *data;
+} dma_channels[11];
+
+/* set err_handler to NULL to have the standard info-only error handler */
+int
+imx_request_dma(char *name, imx_dma_prio prio,
+ void (*irq_handler) (int, void *, struct pt_regs *),
+ void (*err_handler) (int, void *, struct pt_regs *), void *data)
+{
+ unsigned long flags;
+ int i, found = 0;
+
+ /* basic sanity checks */
+ if (!name || !irq_handler)
+ return -EINVAL;
+
+ local_irq_save(flags);
+
+ /* try grabbing a DMA channel with the requested priority */
+ for (i = prio; i < prio + (prio == DMA_PRIO_LOW) ? 8 : 4; i++) {
+ if (!dma_channels[i].name) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found) {
+ /* requested prio group is full, try hier priorities */
+ for (i = prio - 1; i >= 0; i--) {
+ if (!dma_channels[i].name) {
+ found = 1;
+ break;
+ }
+ }
+ }
+
+ if (found) {
+ DIMR &= ~(1 << i);
+ dma_channels[i].name = name;
+ dma_channels[i].irq_handler = irq_handler;
+ dma_channels[i].err_handler = err_handler;
+ dma_channels[i].data = data;
+ } else {
+ printk(KERN_WARNING "No more available DMA channels for %s\n",
+ name);
+ i = -ENODEV;
+ }
+
+ local_irq_restore(flags);
+ return i;
+}
+
+void
+imx_free_dma(int dma_ch)
+{
+ unsigned long flags;
+
+ if (!dma_channels[dma_ch].name) {
+ printk(KERN_CRIT
+ "%s: trying to free channel %d which is already freed\n",
+ __FUNCTION__, dma_ch);
+ return;
+ }
+
+ local_irq_save(flags);
+ DIMR &= ~(1 << dma_ch);
+ dma_channels[dma_ch].name = NULL;
+ local_irq_restore(flags);
+}
+
+static irqreturn_t
+dma_err_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+ int i;
+ struct dma_channel *channel;
+ unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
+
+ for (i = 0; i < 11; i++) {
+ channel = &dma_channels[i];
+
+ if ( (err_mask & 1<<i) && channel->name && channel->err_handler) {
+ channel->err_handler(i, channel->data, regs);
+ continue;
+ }
+
+ if (DBTOSR & (1 << i)) {
+ printk(KERN_WARNING
+ "Burst timeout on channel %d (%s)\n",
+ i, channel->name);
+ DBTOSR |= (1 << i);
+ }
+ if (DRTOSR & (1 << i)) {
+ printk(KERN_WARNING
+ "Request timeout on channel %d (%s)\n",
+ i, channel->name);
+ DRTOSR |= (1 << i);
+ }
+ if (DSESR & (1 << i)) {
+ printk(KERN_WARNING
+ "Transfer timeout on channel %d (%s)\n",
+ i, channel->name);
+ DSESR |= (1 << i);
+ }
+ if (DBOSR & (1 << i)) {
+ printk(KERN_WARNING
+ "Buffer overflow timeout on channel %d (%s)\n",
+ i, channel->name);
+ DBOSR |= (1 << i);
+ }
+ DISR |= (1 << i);
+ }
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+ int i, disr = DISR;
+
+ for (i = 0; i < 11; i++) {
+ if (disr & (1 << i)) {
+ struct dma_channel *channel = &dma_channels[i];
+ if (channel->name && channel->irq_handler) {
+ channel->irq_handler(i, channel->data, regs);
+ } else {
+ /*
+ * IRQ for an unregistered DMA channel:
+ * let's clear the interrupts and disable it.
+ */
+ printk(KERN_WARNING
+ "spurious IRQ for DMA channel %d\n", i);
+ DISR |= (1 << i);
+ }
+ }
+ }
+ return IRQ_HANDLED;
+}
+
+static int __init
+imx_dma_init(void)
+{
+ int ret;
+
+ /* reset DMA module */
+ DCR = DCR_DRST;
+
+ ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
+ if (ret) {
+ printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
+ return ret;
+ }
+
+ ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
+ if (ret) {
+ printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n");
+ free_irq(DMA_INT, NULL);
+ }
+
+ /* enable DMA module */
+ DCR = DCR_DEN;
+
+ /* clear all interrupts */
+ DISR = 0x3ff;
+
+ /* enable interrupts */
+ DIMR = 0;
+
+ return ret;
+}
+
+arch_initcall(imx_dma_init);
+
+EXPORT_SYMBOL(imx_request_dma);
+EXPORT_SYMBOL(imx_free_dma);
--- /dev/null
+/*
+ * arch/arm/mach-imx/generic.c
+ *
+ * author: Sascha Hauer
+ * Created: april 20th, 2004
+ * Copyright: Synertronixx GmbH
+ *
+ * Common code for i.MX machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/hardware.h>
+
+#include <asm/mach/map.h>
+
+void imx_gpio_mode(int gpio_mode)
+{
+ unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+ unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
+ unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
+ unsigned int tmp;
+
+ /* Pullup enable */
+ if(gpio_mode & GPIO_PUEN)
+ PUEN(port) |= (1<<pin);
+ else
+ PUEN(port) &= ~(1<<pin);
+
+ /* Data direction */
+ if(gpio_mode & GPIO_OUT)
+ DDIR(port) |= 1<<pin;
+ else
+ DDIR(port) &= ~(1<<pin);
+
+ /* Primary / alternate function */
+ if(gpio_mode & GPIO_AF)
+ GPR(port) |= (1<<pin);
+ else
+ GPR(port) &= ~(1<<pin);
+
+ /* use as gpio? */
+ if( ocr == 3 )
+ GIUS(port) |= (1<<pin);
+ else
+ GIUS(port) &= ~(1<<pin);
+
+ /* Output / input configuration */
+ /* FIXME: I'm not very sure about OCR and ICONF, someone
+ * should have a look over it
+ */
+ if(pin<16) {
+ tmp = OCR1(port);
+ tmp &= ~( 3<<(pin*2));
+ tmp |= (ocr << (pin*2));
+ OCR1(port) = tmp;
+
+ if( gpio_mode & GPIO_AOUT )
+ ICONFA1(port) &= ~( 3<<(pin*2));
+ if( gpio_mode & GPIO_BOUT )
+ ICONFB1(port) &= ~( 3<<(pin*2));
+ } else {
+ tmp = OCR2(port);
+ tmp &= ~( 3<<((pin-16)*2));
+ tmp |= (ocr << ((pin-16)*2));
+ OCR2(port) = tmp;
+
+ if( gpio_mode & GPIO_AOUT )
+ ICONFA2(port) &= ~( 3<<((pin-16)*2));
+ if( gpio_mode & GPIO_BOUT )
+ ICONFB2(port) &= ~( 3<<((pin-16)*2));
+ }
+}
+
+EXPORT_SYMBOL(imx_gpio_mode);
+
+/*
+ * get the system pll clock in Hz
+ *
+ * mfi + mfn / (mfd +1)
+ * f = 2 * f_ref * --------------------
+ * pd + 1
+ */
+static unsigned int imx_decode_pll(unsigned int pll)
+{
+ u32 mfi = (pll >> 10) & 0xf;
+ u32 mfn = pll & 0x3f;
+ u32 mfd = (pll >> 16) & 0x3f;
+ u32 pd = (pll >> 26) & 0xf;
+ u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ return (2 * (f_ref>>10) * ( (mfi<<10) + (mfn<<10) / (mfd+1) )) / (pd+1);
+}
+
+unsigned int imx_get_system_clk(void)
+{
+ return imx_decode_pll(SPCTL0);
+}
+EXPORT_SYMBOL(imx_get_system_clk);
+
+unsigned int imx_get_mcu_clk(void)
+{
+ return imx_decode_pll(MPCTL0);
+}
+EXPORT_SYMBOL(imx_get_mcu_clk);
+
+/*
+ * get peripheral clock 1 ( UART[12], Timer[12], PWM )
+ */
+unsigned int imx_get_perclk1(void)
+{
+ return imx_get_system_clk() / (((PCDR) & 0xf)+1);
+}
+EXPORT_SYMBOL(imx_get_perclk1);
+
+/*
+ * get peripheral clock 2 ( LCD, SD, SPI[12] )
+ */
+unsigned int imx_get_perclk2(void)
+{
+ return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
+}
+EXPORT_SYMBOL(imx_get_perclk2);
+
+/*
+ * get peripheral clock 3 ( SSI )
+ */
+unsigned int imx_get_perclk3(void)
+{
+ return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
+}
+EXPORT_SYMBOL(imx_get_perclk3);
+
+/*
+ * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
+ */
+unsigned int imx_get_hclk(void)
+{
+ return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
+}
+EXPORT_SYMBOL(imx_get_hclk);
+
+static struct resource imx_mmc_resources[] = {
+ [0] = {
+ .start = 0x00214000,
+ .end = 0x002140FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = (SDHC_INT),
+ .end = (SDHC_INT),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device imx_mmc_device = {
+ .name = "imx-mmc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(imx_mmc_resources),
+ .resource = imx_mmc_resources,
+};
+
+static struct resource imx_uart1_resources[] = {
+ [0] = {
+ .start = 0x00206000,
+ .end = 0x002060FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = (UART1_MINT_RX),
+ .end = (UART1_MINT_RX),
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = (UART1_MINT_TX),
+ .end = (UART1_MINT_TX),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device imx_uart1_device = {
+ .name = "imx-uart",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(imx_uart1_resources),
+ .resource = imx_uart1_resources,
+};
+
+static struct resource imx_uart2_resources[] = {
+ [0] = {
+ .start = 0x00207000,
+ .end = 0x002070FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = (UART2_MINT_RX),
+ .end = (UART2_MINT_RX),
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = (UART2_MINT_TX),
+ .end = (UART2_MINT_TX),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device imx_uart2_device = {
+ .name = "imx-uart",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(imx_uart2_resources),
+ .resource = imx_uart2_resources,
+};
+
+static struct resource imxfb_resources[] = {
+ [0] = {
+ .start = 0x00205000,
+ .end = 0x002050FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LCDC_INT,
+ .end = LCDC_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device imxfb_device = {
+ .name = "imx-fb",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(imxfb_resources),
+ .resource = imxfb_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &imx_mmc_device,
+ &imxfb_device,
+ &imx_uart1_device,
+ &imx_uart2_device,
+};
+
+static struct map_desc imx_io_desc[] __initdata = {
+ /* virtual physical length type */
+ {IMX_IO_BASE, IMX_IO_PHYS, IMX_IO_SIZE, MT_DEVICE},
+};
+
+void __init
+imx_map_io(void)
+{
+ iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
+}
+
+static int __init imx_init(void)
+{
+ return platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+subsys_initcall(imx_init);
--- /dev/null
+/*
+ * linux/arch/arm/mach-imx/generic.h
+ *
+ * Author: Sascha Hauer <sascha@saschahauer.de>
+ * Copyright: Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extern void __init imx_map_io(void);
+extern void __init imx_init_irq(void);
+extern void __init imx_init_time(void);
--- /dev/null
+/*
+ * linux/arch/arm/mach-imx/irq.c
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
+ * Copied from the motorola bsp package and added gpio demux
+ * interrupt handler
+ */
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/irq.h>
+
+/*
+ *
+ * We simply use the ENABLE DISABLE registers inside of the IMX
+ * to turn on/off specific interrupts. FIXME- We should
+ * also add support for the accelerated interrupt controller
+ * by putting offets to irq jump code in the appropriate
+ * places.
+ *
+ */
+
+#define INTENNUM_OFF 0x8
+#define INTDISNUM_OFF 0xC
+
+#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
+#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
+#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
+
+#if 0
+#define DEBUG_IRQ(fmt...) printk(fmt)
+#else
+#define DEBUG_IRQ(fmt...) do { } while (0)
+#endif
+
+static void
+imx_mask_irq(unsigned int irq)
+{
+ __raw_writel(irq, IMX_AITC_INTDISNUM);
+}
+
+static void
+imx_unmask_irq(unsigned int irq)
+{
+ __raw_writel(irq, IMX_AITC_INTENNUM);
+}
+
+static int
+imx_gpio_irq_type(unsigned int _irq, unsigned int type)
+{
+ unsigned int irq_type = 0, irq, reg, bit;
+
+ irq = _irq - IRQ_GPIOA(0);
+ reg = irq >> 5;
+ bit = 1 << (irq % 32);
+
+ if (type == IRQT_PROBE) {
+ /* Don't mess with enabled GPIOs using preconfigured edges or
+ GPIOs set to alternate function during probe */
+ /* TODO: support probe */
+// if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
+// GPIO_bit(gpio))
+// return 0;
+// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
+// return 0;
+// type = __IRQT_RISEDGE | __IRQT_FALEDGE;
+ }
+
+ GIUS(reg) |= bit;
+ DDIR(reg) &= ~(bit);
+
+ DEBUG_IRQ("setting type of irq %d to ", _irq);
+
+ if (type & __IRQT_RISEDGE) {
+ DEBUG_IRQ("rising edges\n");
+ irq_type = 0x0;
+ }
+ if (type & __IRQT_FALEDGE) {
+ DEBUG_IRQ("falling edges\n");
+ irq_type = 0x1;
+ }
+ if (type & __IRQT_LOWLVL) {
+ DEBUG_IRQ("low level\n");
+ irq_type = 0x3;
+ }
+ if (type & __IRQT_HIGHLVL) {
+ DEBUG_IRQ("high level\n");
+ irq_type = 0x2;
+ }
+
+ if (irq % 32 < 16) {
+ ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
+ (irq_type << ((irq % 16) * 2));
+ } else {
+ ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
+ (irq_type << ((irq % 16) * 2));
+ }
+
+ return 0;
+
+}
+
+static void
+imx_gpio_ack_irq(unsigned int irq)
+{
+ DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
+ ISR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
+}
+
+static void
+imx_gpio_mask_irq(unsigned int irq)
+{
+ DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
+ IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
+}
+
+static void
+imx_gpio_unmask_irq(unsigned int irq)
+{
+ DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
+ IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
+}
+
+static void
+imx_gpio_handler(unsigned int mask, unsigned int irq,
+ struct irqdesc *desc, struct pt_regs *regs)
+{
+ desc = irq_desc + irq;
+ while (mask) {
+ if (mask & 1) {
+ DEBUG_IRQ("handling irq %d\n", irq);
+ desc->handle(irq, desc, regs);
+ }
+ irq++;
+ desc++;
+ mask >>= 1;
+ }
+}
+
+static void
+imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = ISR(0);
+ irq = IRQ_GPIOA(0);
+ imx_gpio_handler(mask, irq, desc, regs);
+}
+
+static void
+imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = ISR(1);
+ irq = IRQ_GPIOB(0);
+ imx_gpio_handler(mask, irq, desc, regs);
+}
+
+static void
+imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = ISR(2);
+ irq = IRQ_GPIOC(0);
+ imx_gpio_handler(mask, irq, desc, regs);
+}
+
+static void
+imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
+ struct pt_regs *regs)
+{
+ unsigned int mask, irq;
+
+ mask = ISR(3);
+ irq = IRQ_GPIOD(0);
+ imx_gpio_handler(mask, irq, desc, regs);
+}
+
+static struct irqchip imx_internal_chip = {
+ .ack = imx_mask_irq,
+ .mask = imx_mask_irq,
+ .unmask = imx_unmask_irq,
+};
+
+static struct irqchip imx_gpio_chip = {
+ .ack = imx_gpio_ack_irq,
+ .mask = imx_gpio_mask_irq,
+ .unmask = imx_gpio_unmask_irq,
+ .type = imx_gpio_irq_type,
+};
+
+void __init
+imx_init_irq(void)
+{
+ unsigned int irq;
+
+ DEBUG_IRQ("Initializing imx interrupts\n");
+
+ /* Mask all interrupts initially */
+ IMR(0) = 0;
+ IMR(1) = 0;
+ IMR(2) = 0;
+ IMR(3) = 0;
+
+ for (irq = 0; irq < IMX_IRQS; irq++) {
+ set_irq_chip(irq, &imx_internal_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
+ set_irq_chip(irq, &imx_gpio_chip);
+ set_irq_handler(irq, do_edge_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
+ set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
+ set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
+ set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
+
+ /* Disable all interrupts initially. */
+ /* In IMX this is done in the bootloader. */
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-imx/leds-mx1ads.c
+ *
+ * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ * Original (leds-footbridge.c) by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include "leds.h"
+
+/*
+ * The MX1ADS Board has only one usable LED,
+ * so select only the timer led or the
+ * cpu usage led
+ */
+void
+mx1ads_leds_event(led_event_t ledevt)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ switch (ledevt) {
+#ifdef CONFIG_LEDS_CPU
+ case led_idle_start:
+ DR(0) &= ~(1<<2);
+ break;
+
+ case led_idle_end:
+ DR(0) |= 1<<2;
+ break;
+#endif
+
+#ifdef CONFIG_LEDS_TIMER
+ case led_timer:
+ DR(0) ^= 1<<2;
+#endif
+ default:
+ break;
+ }
+ local_irq_restore(flags);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-imx/leds.h
+ *
+ * Copyright (C) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include "leds.h"
+
+static int __init
+leds_init(void)
+{
+ if (machine_is_mx1ads()) {
+ leds_event = mx1ads_leds_event;
+ }
+
+ return 0;
+}
+
+__initcall(leds_init);
--- /dev/null
+/*
+ * include/asm-arm/arch-imx/leds.h
+ *
+ * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ * blinky lights for IMX-based systems
+ *
+ */
+extern void mx1ads_leds_event(led_event_t evt);
--- /dev/null
+/*
+ * arch/arm/mach-imx/mx1ads.c
+ *
+ * Initially based on:
+ * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
+ * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <linux/interrupt.h>
+#include "generic.h"
+#include <asm/serial.h>
+
+static struct resource mx1ads_resources[] = {
+ [0] = {
+ .start = IMX_CS4_VIRT,
+ .end = IMX_CS4_VIRT + 16,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 13,
+ .end = 13,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device mx1ads_device = {
+ .name = "mx1ads",
+ .num_resources = ARRAY_SIZE(mx1ads_resources),
+ .resource = mx1ads_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &mx1ads_device,
+};
+
+static void __init
+mx1ads_init(void)
+{
+#ifdef CONFIG_LEDS
+ imx_gpio_mode(GPIO_PORTA | GPIO_OUT | GPIO_GPIO | 2);
+#endif
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static struct map_desc mx1ads_io_desc[] __initdata = {
+ /* virtual physical length type */
+ {IMX_CS0_VIRT, IMX_CS0_PHYS, IMX_CS0_SIZE, MT_DEVICE},
+ {IMX_CS1_VIRT, IMX_CS1_PHYS, IMX_CS1_SIZE, MT_DEVICE},
+ {IMX_CS2_VIRT, IMX_CS2_PHYS, IMX_CS2_SIZE, MT_DEVICE},
+ {IMX_CS3_VIRT, IMX_CS3_PHYS, IMX_CS3_SIZE, MT_DEVICE},
+ {IMX_CS4_VIRT, IMX_CS4_PHYS, IMX_CS4_SIZE, MT_DEVICE},
+ {IMX_CS5_VIRT, IMX_CS5_PHYS, IMX_CS5_SIZE, MT_DEVICE},
+};
+
+static void __init
+mx1ads_map_io(void)
+{
+ imx_map_io();
+ iotable_init(mx1ads_io_desc, ARRAY_SIZE(mx1ads_io_desc));
+}
+
+MACHINE_START(MX1ADS, "Motorola MX1ADS")
+ MAINTAINER("Sascha Hauer, Pengutronix")
+ BOOT_MEM(0x08000000, 0x00200000, 0xe0200000)
+ BOOT_PARAMS(0x08000100)
+ MAPIO(mx1ads_map_io)
+ INITIRQ(imx_init_irq)
+ INITTIME(imx_init_time)
+ INIT_MACHINE(mx1ads_init)
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-imx/time.c
+ *
+ * Copyright (C) 2000-2001 Deep Blue Solutions
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/leds.h>
+#include <asm/irq.h>
+#include <asm/mach/time.h>
+
+/* Use timer 1 as system timer */
+#define TIMER_BASE IMX_TIM1_BASE
+
+/*
+ * Returns number of us since last clock interrupt. Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ */
+static unsigned long
+imx_gettimeoffset(void)
+{
+ unsigned long ticks;
+
+ /*
+ * Get the current number of ticks. Note that there is a race
+ * condition between us reading the timer and checking for
+ * an interrupt. We get around this by ensuring that the
+ * counter has not reloaded between our two reads.
+ */
+ ticks = IMX_TCN(TIMER_BASE);
+
+ /*
+ * Interrupt pending? If so, we've reloaded once already.
+ */
+ if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP)
+ ticks += LATCH;
+
+ /*
+ * Convert the ticks to usecs
+ */
+ return (1000000 / CLK32) * ticks;
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+imx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ /* clear the interrupt */
+ if (IMX_TSTAT(TIMER_BASE))
+ IMX_TSTAT(TIMER_BASE) = 0;
+
+ timer_tick(regs);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction imx_timer_irq = {
+ .name = "i.MX Timer Tick",
+ .flags = SA_INTERRUPT,
+ .handler = imx_timer_interrupt
+};
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init
+imx_init_time(void)
+{
+ /*
+ * Initialise to a known state (all timers off, and timing reset)
+ */
+ IMX_TCTL(TIMER_BASE) = 0;
+ IMX_TPRER(TIMER_BASE) = 0;
+ IMX_TCMP(TIMER_BASE) = LATCH - 1;
+ IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN;
+
+ /*
+ * Make irqs happen for the system timer
+ */
+ setup_irq(TIM1_INT, &imx_timer_irq);
+ gettimeoffset = imx_gettimeoffset;
+}
--- /dev/null
+/*
+ * arch/arm/mach-iop3xx/common.c
+ *
+ * Common routines shared across all IOP3xx implementations
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright 2003 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/hardware.h>
+
+/*
+ * Shared variables
+ */
+unsigned long iop3xx_pcibios_min_io = 0;
+unsigned long iop3xx_pcibios_min_mem = 0;
+
+#ifdef CONFIG_ARCH_EP80219
+#include <linux/kernel.h>
+/*
+ * Default power-off for EP80219
+ */
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+
+static inline void ep80219_send_to_pic(__u8 c) {
+}
+
+void ep80219_power_off(void)
+{
+ /*
+ * This function will send a SHUTDOWN_COMPLETE message to the PIC controller
+ * over I2C. We are not using the i2c subsystem since we are going to power
+ * off and it may be removed
+ */
+
+ /* Send the Address byte w/ the start condition */
+ *IOP321_IDBR1 = 0x60;
+ *IOP321_ICR1 = 0xE9;
+ mdelay(1);
+
+ /* Send the START_MSG byte w/ no start or stop condition */
+ *IOP321_IDBR1 = 0x0F;
+ *IOP321_ICR1 = 0xE8;
+ mdelay(1);
+
+ /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */
+ *IOP321_IDBR1 = 0x03;
+ *IOP321_ICR1 = 0xE8;
+ mdelay(1);
+
+ /* Send an ignored byte w/ stop condition */
+ *IOP321_IDBR1 = 0x00;
+ *IOP321_ICR1 = 0xEA;
+
+ while (1) ;
+}
+
+#include <linux/init.h>
+#include <linux/pm.h>
+
+static int __init ep80219_init(void)
+{
+ pm_power_off = ep80219_power_off;
+ return 0;
+}
+arch_initcall(ep80219_init);
+#endif
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/mm.c
+ *
+ * Low level memory initialization for IOP321 based systems
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * Standard IO mapping for all IOP321 based systems
+ */
+static struct map_desc iop321_std_desc[] __initdata = {
+ /* virtual physical length type */
+
+ /* mem mapped registers */
+ { IOP321_VIRT_MEM_BASE, IOP321_PHY_MEM_BASE, 0x00002000, MT_DEVICE },
+
+ /* PCI IO space */
+ { 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
+};
+
+void __init iop321_map_io(void)
+{
+ iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc));
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/iop321-setup.c
+ *
+ * Author: Nicolas Pitre <nico@cam.org>
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+
+#include <asm/setup.h>
+#include <asm/system.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#ifdef CONFIG_ARCH_IQ80321
+extern void iq80321_map_io(void);
+extern void iop321_init_irq(void);
+extern void iop321_init_time(void);
+#endif
+
+#ifdef CONFIG_ARCH_IQ31244
+extern void iq31244_map_io(void);
+extern void iop321_init_irq(void);
+extern void iop321_init_time(void);
+#endif
+
+static void __init
+fixup_iop321(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+}
+
+#if defined(CONFIG_ARCH_IQ80321)
+MACHINE_START(IQ80321, "Intel IQ80321")
+ MAINTAINER("Intel Corporation")
+ BOOT_MEM(PHYS_OFFSET, IQ80321_UART, 0xfe800000)
+ FIXUP(fixup_iop321)
+ MAPIO(iq80321_map_io)
+ INITIRQ(iop321_init_irq)
+ INITTIME(iop321_init_time)
+ BOOT_PARAMS(0xa0000100)
+MACHINE_END
+#elif defined(CONFIG_ARCH_IQ31244)
+ MACHINE_START(IQ31244, "Intel IQ31244")
+ MAINTAINER("Intel Corp.")
+ BOOT_MEM(PHYS_OFFSET, IQ31244_UART, IQ31244_UART)
+ MAPIO(iq31244_map_io)
+ INITIRQ(iop321_init_irq)
+ INITTIME(iop321_init_time)
+ BOOT_PARAMS(0xa0000100)
+MACHINE_END
+#else
+#error No machine descriptor defined for this IOP3XX implementation
+#endif
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/iop331-irq.c
+ *
+ * Generic IOP331 IRQ handling functionality
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ * Copyright (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+
+#include <asm/mach-types.h>
+
+static u32 iop331_mask0 = 0;
+static u32 iop331_mask1 = 0;
+
+static inline void intctl_write0(u32 val)
+{
+ // INTCTL0
+ asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
+}
+
+static inline void intctl_write1(u32 val)
+{
+ // INTCTL1
+ asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
+}
+
+static inline void intstr_write0(u32 val)
+{
+ // INTSTR0
+ asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
+}
+
+static inline void intstr_write1(u32 val)
+{
+ // INTSTR1
+ asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
+}
+
+static void
+iop331_irq_mask1 (unsigned int irq)
+{
+ iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS));
+ intctl_write0(iop331_mask0);
+}
+
+static void
+iop331_irq_mask2 (unsigned int irq)
+{
+ iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32));
+ intctl_write1(iop331_mask1);
+}
+
+static void
+iop331_irq_unmask1(unsigned int irq)
+{
+ iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS));
+ intctl_write0(iop331_mask0);
+}
+
+static void
+iop331_irq_unmask2(unsigned int irq)
+{
+ iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32));
+ intctl_write1(iop331_mask1);
+}
+
+struct irqchip iop331_irqchip1 = {
+ .ack = iop331_irq_mask1,
+ .mask = iop331_irq_mask1,
+ .unmask = iop331_irq_unmask1,
+};
+
+struct irqchip iop331_irqchip2 = {
+ .ack = iop331_irq_mask2,
+ .mask = iop331_irq_mask2,
+ .unmask = iop331_irq_unmask2,
+};
+
+void __init iop331_init_irq(void)
+{
+ unsigned int i, tmp;
+
+ /* Enable access to coprocessor 6 for dealing with IRQs.
+ * From RMK:
+ * Basically, the Intel documentation here is poor. It appears that
+ * you need to set the bit to be able to access the coprocessor from
+ * SVC mode. Whether that allows access from user space or not is
+ * unclear.
+ */
+ asm volatile (
+ "mrc p15, 0, %0, c15, c1, 0\n\t"
+ "orr %0, %0, %1\n\t"
+ "mcr p15, 0, %0, c15, c1, 0\n\t"
+ /* The action is delayed, so we have to do this: */
+ "mrc p15, 0, %0, c15, c1, 0\n\t"
+ "mov %0, %0\n\t"
+ "sub pc, pc, #4"
+ : "=r" (tmp) : "i" (1 << 6) );
+
+ intctl_write0(0); // disable all interrupts
+ intctl_write1(0);
+ intstr_write0(0); // treat all as IRQ
+ intstr_write1(0);
+ if(machine_is_iq80331()) // all interrupts are inputs to chip
+ *IOP331_PCIIRSR = 0x0f;
+
+ for(i = IOP331_IRQ_OFS; i < NR_IOP331_IRQS; i++)
+ {
+ set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
+ set_irq_handler(i, do_level_IRQ);
+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+ }
+}
+
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/mm.c
+ *
+ * Low level memory initialization for IOP331 based systems
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ * Copyright (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * Standard IO mapping for all IOP331 based systems
+ */
+static struct map_desc iop331_std_desc[] __initdata = {
+ /* virtual physical length type */
+
+ /* mem mapped registers */
+ { IOP331_VIRT_MEM_BASE, IOP331_PHYS_MEM_BASE, 0x00002000, MT_DEVICE },
+
+ /* PCI IO space */
+ { 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
+};
+
+void __init iop331_map_io(void)
+{
+ iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc));
+}
--- /dev/null
+/*
+ * arch/arm/mach-iop3xx/iop331-pci.c
+ *
+ * PCI support for the Intel IOP331 chipset
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach/pci.h>
+
+#include <asm/arch/iop331.h>
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) do { } while (0)
+#endif
+
+/*
+ * This routine builds either a type0 or type1 configuration command. If the
+ * bus is on the 80331 then a type0 made, else a type1 is created.
+ */
+static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where)
+{
+ struct pci_sys_data *sys = bus->sysdata;
+ u32 addr;
+
+ if (sys->busnr == bus->number)
+ addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
+ else
+ addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
+
+ addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
+
+ return addr;
+}
+
+/*
+ * This routine checks the status of the last configuration cycle. If an error
+ * was detected it returns a 1, else it returns a 0. The errors being checked
+ * are parity, master abort, target abort (master and target). These types of
+ * errors occure during a config cycle where there is no device, like during
+ * the discovery stage.
+ */
+static int iop331_pci_status(void)
+{
+ unsigned int status;
+ int ret = 0;
+
+ /*
+ * Check the status registers.
+ */
+ status = *IOP331_ATUSR;
+ if (status & 0xf900)
+ {
+ DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
+ *IOP331_ATUSR = status & 0xf900;
+ ret = 1;
+ }
+ status = *IOP331_ATUISR;
+ if (status & 0x679f)
+ {
+ DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
+ *IOP331_ATUISR = status & 0x679f;
+ ret = 1;
+ }
+ return ret;
+}
+
+/*
+ * Simply write the address register and read the configuration
+ * data. Note that the 4 nop's ensure that we are able to handle
+ * a delayed abort (in theory.)
+ */
+static inline u32 iop331_read(unsigned long addr)
+{
+ u32 val;
+
+ __asm__ __volatile__(
+ "str %1, [%2]\n\t"
+ "ldr %0, [%3]\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ : "=r" (val)
+ : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
+
+ return val;
+}
+
+/*
+ * The read routines must check the error status of the last configuration
+ * cycle. If there was an error, the routine returns all hex f's.
+ */
+static int
+iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 *value)
+{
+ unsigned long addr = iop331_cfg_address(bus, devfn, where);
+ u32 val = iop331_read(addr) >> ((where & 3) * 8);
+
+ if( iop331_pci_status() )
+ val = 0xffffffff;
+
+ *value = val;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 value)
+{
+ unsigned long addr = iop331_cfg_address(bus, devfn, where);
+ u32 val;
+
+ if (size != 4) {
+ val = iop331_read(addr);
+ if (!iop331_pci_status() == 0)
+ return PCIBIOS_SUCCESSFUL;
+
+ where = (where & 3) * 8;
+
+ if (size == 1)
+ val &= ~(0xff << where);
+ else
+ val &= ~(0xffff << where);
+
+ *IOP331_OCCDR = val | value << where;
+ } else {
+ asm volatile(
+ "str %1, [%2]\n\t"
+ "str %0, [%3]\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ :
+ : "r" (value), "r" (addr),
+ "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops iop331_ops = {
+ .read = iop331_read_config,
+ .write = iop331_write_config,
+};
+
+/*
+ * When a PCI device does not exist during config cycles, the XScale gets a
+ * bus error instead of returning 0xffffffff. This handler simply returns.
+ */
+int
+iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+ DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
+ addr, fsr, regs->ARM_pc, regs->ARM_lr);
+
+ /*
+ * If it was an imprecise abort, then we need to correct the
+ * return address to be _after_ the instruction.
+ */
+ if (fsr & (1 << 10))
+ regs->ARM_pc += 4;
+
+ return 0;
+}
+
+/*
+ * Scan an IOP331 PCI bus. sys->bus defines which bus we scan.
+ */
+struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys)
+{
+ return pci_scan_bus(sys->busnr, &iop331_ops, sys);
+}
+
+void iop331_init(void)
+{
+ DBG("PCI: Intel 80331 PCI init code.\n");
+ DBG("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
+ DBG("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
+ *IOP331_OMWTVR0,
+ *IOP331_OIOWTVR);
+ DBG("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
+ DBG("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
+ DBG("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
+ DBG("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
+ DBG("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
+
+ /* redboot changed, reset IABAR0 to something sane */
+ /* fixes master aborts in plugged in cards */
+ /* will clean up later and work nicely with redboot */
+ *IOP331_IABAR0 = 0x00000004;
+ hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");
+}
+
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/iop331-setup.c
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2004 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/setup.h>
+#include <asm/system.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#define IOP331_UART_XTAL 33334000
+
+/*
+ * Standard IO mapping for all IOP331 based systems
+ */
+static struct map_desc iop331_std_desc[] __initdata = {
+ /* virtual physical length type */
+
+ /* mem mapped registers */
+ { IOP331_VIRT_MEM_BASE, IOP331_PHYS_MEM_BASE, 0x00002000, MT_DEVICE },
+
+ /* PCI IO space */
+ { 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
+};
+
+static struct uart_port iop331_serial_ports[] = {
+ {
+ .membase = (char*)(IQ80331_UART0_VIRT),
+ .mapbase = (IQ80331_UART0_PHYS),
+ .irq = IRQ_IOP331_UART0,
+ .flags = UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IOP331_UART_XTAL,
+ .line = 0,
+ .type = PORT_XSCALE,
+ .fifosize = 32
+ } , {
+ .membase = (char*)(IQ80331_UART1_VIRT),
+ .mapbase = (IQ80331_UART1_PHYS),
+ .irq = IRQ_IOP331_UART1,
+ .flags = UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IOP331_UART_XTAL,
+ .line = 1,
+ .type = PORT_XSCALE,
+ .fifosize = 32
+ }
+};
+
+void __init iop331_map_io(void)
+{
+ iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc));
+ early_serial_setup(&iop331_serial_ports[0]);
+ early_serial_setup(&iop331_serial_ports[1]);
+}
+
+#ifdef CONFIG_ARCH_IQ80331
+extern void iop331_init_irq(void);
+extern void iop331_init_time(void);
+extern void iq80331_map_io(void);
+#endif
+
+#if defined(CONFIG_ARCH_IQ80331)
+MACHINE_START(IQ80331, "Intel IQ80331")
+ MAINTAINER("Intel Corp.")
+ BOOT_MEM(PHYS_OFFSET, 0xfefff000, 0xfffff000) // virtual, physical
+ //BOOT_MEM(PHYS_OFFSET, IQ80331_UART0_VIRT, IQ80331_UART0_PHYS)
+ MAPIO(iq80331_map_io)
+ INITIRQ(iop331_init_irq)
+ INITTIME(iop331_init_time)
+ BOOT_PARAMS(0x0100)
+MACHINE_END
+#else
+#error No machine descriptor defined for this IOP3XX implementation
+#endif
+
+
--- /dev/null
+/*
+ * arch/arm/mach-iop3xx/iop331-time.c
+ *
+ * Timer code for IOP331 based systems
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ *
+ * Copyright 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/init.h>
+#include <linux/timex.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/mach-types.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+#undef IOP331_TIME_SYNC
+
+static unsigned long iop331_latch;
+
+static inline unsigned long get_elapsed(void)
+{
+ return iop331_latch - *IOP331_TU_TCR0;
+}
+
+static unsigned long iop331_gettimeoffset(void)
+{
+ unsigned long elapsed, usec;
+ u32 tisr1, tisr2;
+
+ /*
+ * If an interrupt was pending before we read the timer,
+ * we've already wrapped. Factor this into the time.
+ * If an interrupt was pending after we read the timer,
+ * it may have wrapped between checking the interrupt
+ * status and reading the timer. Re-read the timer to
+ * be sure its value is after the wrap.
+ */
+
+ asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1));
+ elapsed = get_elapsed();
+ asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2));
+
+ if(tisr1 & 1)
+ elapsed += iop331_latch;
+ else if (tisr2 & 1)
+ elapsed = iop331_latch + get_elapsed();
+
+ /*
+ * Now convert them to usec.
+ */
+ usec = (unsigned long)(elapsed * (tick_nsec / 1000)) / iop331_latch;
+
+ return usec;
+}
+
+static irqreturn_t
+iop331_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ u32 tisr;
+#ifdef IOP331_TIME_SYNC
+ u32 passed;
+#define TM_THRESH (iop331_latch*2)
+#endif
+
+ asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr));
+
+ tisr |= 1;
+
+ asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr));
+
+#ifdef IOP331_TIME_SYNC
+ passed = 0xffffffff - *IOP331_TU_TCR1;
+
+ do
+ {
+ do_timer(regs);
+ if(passed < TM_THRESH)
+ break;
+ if(passed > iop331_latch)
+ passed -= iop331_latch;
+ else
+ passed = 0;
+ } while(1);
+
+ asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (0xffffffff));
+#else
+ do_timer(regs);
+#endif
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction iop331_timer_irq = {
+ .name = "IOP331 Timer Tick",
+ .handler = iop331_timer_interrupt,
+ .flags = SA_INTERRUPT
+};
+
+extern int setup_arm_irq(int, struct irqaction*);
+
+void __init iop331_init_time(void)
+{
+ u32 timer_ctl;
+
+ iop331_latch = (CLOCK_TICK_RATE + HZ / 2) / HZ;
+ gettimeoffset = iop331_gettimeoffset;
+ setup_irq(IRQ_IOP331_TIMER0, &iop331_timer_irq);
+
+ timer_ctl = IOP331_TMR_EN | IOP331_TMR_PRIVILEGED | IOP331_TMR_RELOAD |
+ IOP331_TMR_RATIO_1_1;
+
+ asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (iop331_latch));
+
+ asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
+
+#ifdef IOP331_TIME_SYNC
+ /* Setup second timer */
+ /* setup counter */
+ timer_ctl = IOP331_TMR_EN | IOP331_TMR_PRIVILEGED |
+ IOP331_TMR_RATIO_1_1;
+ asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (0xffffffff));
+ /* setup control */
+ asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
+#endif
+}
+
+
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/mm.c
+ *
+ * Low level memory initialization for iq80321 platform
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * IQ80321 specific IO mappings
+ *
+ * We use RedBoot's setup for the onboard devices.
+ */
+static struct map_desc iq31244_io_desc[] __initdata = {
+ /* virtual physical length type */
+
+ /* on-board devices */
+ { IQ31244_UART, IQ31244_UART, 0x00100000, MT_DEVICE }
+};
+
+void __init iq31244_map_io(void)
+{
+ iop321_map_io();
+
+ iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
+}
--- /dev/null
+/*
+ * arch/arm/mach-iop3xx/iq80321-pci.c
+ *
+ * PCI support for the Intel IQ80321 reference board
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+/*
+ * The following macro is used to lookup irqs in a standard table
+ * format for those systems that do not already have PCI
+ * interrupts properly routed. We assume 1 <= pin <= 4
+ */
+#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
+({ int _ctl_ = -1; \
+ unsigned int _idsel = idsel - minid; \
+ if (_idsel <= maxid) \
+ _ctl_ = pci_irq_table[_idsel][pin-1]; \
+ _ctl_; })
+
+#define INTA IRQ_IQ31244_INTA
+#define INTB IRQ_IQ31244_INTB
+#define INTC IRQ_IQ31244_INTC
+#define INTD IRQ_IQ31244_INTD
+
+#define INTE IRQ_IQ31244_I82546
+
+static inline int __init
+iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+ static int pci_irq_table[][4] = {
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+#ifdef CONFIG_ARCH_EP80219
+ {INTB, INTB, INTB, INTB}, /* CFlash */
+ {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */
+ {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
+ {INTC, INTC, INTC, INTC}, /* SATA */
+#else
+ {INTB, INTB, INTB, INTB}, /* CFlash */
+ {INTC, INTC, INTC, INTC}, /* SATA */
+ {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
+ {INTE, INTE, INTE, INTE}, /* 82546 GigE */
+#endif // CONFIG_ARCH_EP80219
+ };
+
+ BUG_ON(pin < 1 || pin > 4);
+
+ return PCI_IRQ_TABLE_LOOKUP(0, 7);
+}
+
+static int iq31244_setup(int nr, struct pci_sys_data *sys)
+{
+ struct resource *res;
+
+ if(nr != 0)
+ return 0;
+
+ res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ if (!res)
+ panic("PCI: unable to alloc resources");
+
+ memset(res, 0, sizeof(struct resource) * 2);
+
+ res[0].start = IQ31244_PCI_IO_BASE + 0x6e000000;
+ res[0].end = IQ31244_PCI_IO_BASE + IQ31244_PCI_IO_SIZE - 1 + IQ31244_PCI_IO_OFFSET;
+ res[0].name = "IQ31244 PCI I/O Space";
+ res[0].flags = IORESOURCE_IO;
+
+ res[1].start = IQ31244_PCI_MEM_BASE;
+ res[1].end = IQ31244_PCI_MEM_BASE + IQ31244_PCI_MEM_SIZE;
+ res[1].name = "IQ31244 PCI Memory Space";
+ res[1].flags = IORESOURCE_MEM;
+
+ request_resource(&ioport_resource, &res[0]);
+ request_resource(&iomem_resource, &res[1]);
+
+ sys->resource[0] = &res[0];
+ sys->resource[1] = &res[1];
+ sys->resource[2] = NULL;
+ sys->io_offset = IQ31244_PCI_IO_OFFSET;
+ sys->mem_offset = IQ80321_PCI_MEM_BASE -
+ (*IOP321_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
+
+ iop3xx_pcibios_min_io = IQ31244_PCI_IO_BASE;
+ iop3xx_pcibios_min_mem = IQ31244_PCI_MEM_BASE;
+
+ return 1;
+}
+
+static void iq31244_preinit(void)
+{
+ iop321_init();
+ /* setting up the second translation window */
+ *IOP321_OMWTVR1 = IQ31244_PCI_MEM_BASE + 0x04000000;
+ *IOP321_OUMWTVR1 = 0x0;
+}
+
+static struct hw_pci iq31244_pci __initdata = {
+ .swizzle = pci_std_swizzle,
+ .nr_controllers = 1,
+ .setup = iq31244_setup,
+ .scan = iop321_scan_bus,
+ .preinit = iq31244_preinit,
+ .map_irq = iq31244_map_irq
+};
+
+static int __init iq31244_pci_init(void)
+{
+ if (machine_is_iq31244())
+ pci_common_init(&iq31244_pci);
+ return 0;
+}
+
+subsys_initcall(iq31244_pci_init);
+
+
+
+
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/mm.c
+ *
+ * Low level memory initialization for iq80321 platform
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * IQ80321 specific IO mappings
+ *
+ * We use RedBoot's setup for the onboard devices.
+ */
+static struct map_desc iq80321_io_desc[] __initdata = {
+ /* virtual physical length type */
+
+ /* on-board devices */
+ { IQ80321_UART, IQ80321_UART, 0x00100000, MT_DEVICE }
+};
+
+void __init iq80321_map_io(void)
+{
+ iop321_map_io();
+
+ iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-iop3xx/mm.c
+ *
+ * Low level memory initialization for iq80331 platform
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ * Copyright (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * IQ80331 specific IO mappings
+ *
+ * We use RedBoot's setup for the onboard devices.
+ */
+
+void __init iq80331_map_io(void)
+{
+ iop331_map_io();
+}
--- /dev/null
+/*
+ * arch/arm/mach-iop3xx/iq80331-pci.c
+ *
+ * PCI support for the Intel IQ80331 reference board
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ * Copyright (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+/*
+ * The following macro is used to lookup irqs in a standard table
+ * format for those systems that do not already have PCI
+ * interrupts properly routed. We assume 1 <= pin <= 4
+ */
+#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
+({ int _ctl_ = -1; \
+ unsigned int _idsel = idsel - minid; \
+ if (_idsel <= maxid) \
+ _ctl_ = pci_irq_table[_idsel][pin-1]; \
+ _ctl_; })
+
+#define INTA IRQ_IQ80331_INTA
+#define INTB IRQ_IQ80331_INTB
+#define INTC IRQ_IQ80331_INTC
+#define INTD IRQ_IQ80331_INTD
+
+//#define INTE IRQ_IQ80331_I82544
+
+static inline int __init
+iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+ static int pci_irq_table[][4] = {
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {INTB, INTC, INTD, INTA}, /* PCI-X Slot */
+ {INTC, INTC, INTC, INTC}, /* GigE */
+ };
+
+ BUG_ON(pin < 1 || pin > 4);
+
+ return PCI_IRQ_TABLE_LOOKUP(1, 7);
+}
+
+static int iq80331_setup(int nr, struct pci_sys_data *sys)
+{
+ struct resource *res;
+
+ if(nr != 0)
+ return 0;
+
+ res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ if (!res)
+ panic("PCI: unable to alloc resources");
+
+ memset(res, 0, sizeof(struct resource) * 2);
+
+ res[0].start = IQ80331_PCI_IO_BASE + 0x6e000000;
+ res[0].end = IQ80331_PCI_IO_BASE + IQ80331_PCI_IO_SIZE - 1 + IQ80331_PCI_IO_OFFSET;
+ res[0].name = "IQ80331 PCI I/O Space";
+ res[0].flags = IORESOURCE_IO;
+
+ res[1].start = IQ80331_PCI_MEM_BASE;
+ res[1].end = IQ80331_PCI_MEM_BASE + IQ80331_PCI_MEM_SIZE;
+ res[1].name = "IQ80331 PCI Memory Space";
+ res[1].flags = IORESOURCE_MEM;
+
+ request_resource(&ioport_resource, &res[0]);
+ request_resource(&iomem_resource, &res[1]);
+
+ /*
+ * Since the IQ80331 is a slave card on a PCI backplane,
+ * it uses BAR1 to reserve a portion of PCI memory space for
+ * use with the private devices on the secondary bus
+ * (GigE and PCI-X slot). We read BAR1 and configure
+ * our outbound translation windows to target that
+ * address range and assign all devices in that
+ * address range. W/O this, certain BIOSes will fail
+ * to boot as the IQ80331 claims addresses that are
+ * in use by other devices.
+ *
+ * Note that the same cannot be done with I/O space,
+ * so hopefully the host will stick to the lower 64K for
+ * PCI I/O and leave us alone.
+ */
+ sys->mem_offset = IQ80331_PCI_MEM_BASE -
+ (*IOP331_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
+
+ sys->resource[0] = &res[0];
+ sys->resource[1] = &res[1];
+ sys->resource[2] = NULL;
+ sys->io_offset = IQ80331_PCI_IO_OFFSET;
+
+ iop3xx_pcibios_min_io = IQ80331_PCI_IO_BASE;
+ iop3xx_pcibios_min_mem = IQ80331_PCI_MEM_BASE;
+
+ return 1;
+}
+
+static void iq80331_preinit(void)
+{
+ iop331_init();
+}
+
+static struct hw_pci iq80331_pci __initdata = {
+ .swizzle = pci_std_swizzle,
+ .nr_controllers = 1,
+ .setup = iq80331_setup,
+ .scan = iop331_scan_bus,
+ .preinit = iq80331_preinit,
+ .map_irq = iq80331_map_irq
+};
+
+static int __init iq80331_pci_init(void)
+{
+ if (machine_is_iq80331())
+ pci_common_init(&iq80331_pci);
+ return 0;
+}
+
+subsys_initcall(iq80331_pci_init);
+
+
+
+
--- /dev/null
+
+if ARCH_IXP2000
+
+config ARCH_SUPPORTS_BIG_ENDIAN
+ bool
+ default y
+
+menu "Intel IXP2400/2800 Implementation Options"
+
+comment "IXP2400/2800 Platforms"
+
+config ARCH_ENP2611
+ bool "Support Radisys ENP-2611"
+ help
+ Say 'Y' here if you want your kernel to support the Radisys
+ ENP2611 PCI network processing card. For more information on
+ this card, see Documentation/arm/ENP2611.
+
+config ARCH_IXDP2400
+ bool "Support Intel IXDP2400"
+ help
+ Say 'Y' here if you want your kernel to support the Intel
+ IXDP2400 reference platform. For more information on
+ this platform, see Documentation/arm/IXP2000.
+
+config ARCH_IXDP2800
+ bool "Support Intel IXDP2800"
+ help
+ Say 'Y' here if you want your kernel to support the Intel
+ IXDP2800 reference platform. For more information on
+ this platform, see Documentation/arm/IXP2000.
+
+config ARCH_IXDP2X00
+ bool
+ depends on ARCH_IXDP2400 || ARCH_IXDP2800
+ default y
+
+config ARCH_IXDP2401
+ bool "Support Intel IXDP2401"
+ help
+ Say 'Y' here if you want your kernel to support the Intel
+ IXDP2401 reference platform. For more information on
+ this platform, see Documentation/arm/IXP2000.
+
+config ARCH_IXDP2801
+ bool "Support Intel IXDP2801"
+ help
+ Say 'Y' here if you want your kernel to support the Intel
+ IXDP2801 reference platform. For more information on
+ this platform, see Documentation/arm/IXP2000.
+
+config ARCH_IXDP2X01
+ bool
+ depends on ARCH_IXDP2401 || ARCH_IXDP2801
+ default y
+
+endmenu
+
+endif
--- /dev/null
+#
+# Makefile for the linux kernel.
+#
+obj-y := core.o pci.o
+obj-m :=
+obj-n :=
+obj- :=
+
+obj-$(CONFIG_ARCH_ENP2611) += enp2611.o
+obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o
+obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o
+obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o
+obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/common.c
+ *
+ * Common routines used by all IXP2400/2800 based platforms.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (C) MontaVista Software, Inc.
+ *
+ * Based on work Copyright (C) 2002-2003 Intel Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/serial_core.h>
+#include <linux/mm.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+
+static spinlock_t ixp2000_slowport_lock = SPIN_LOCK_UNLOCKED;
+static unsigned long ixp2000_slowport_irq_flags;
+
+/*************************************************************************
+ * Slowport access routines
+ *************************************************************************/
+void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
+{
+
+ spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
+
+ old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
+ old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
+ old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
+ old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
+ old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
+
+ ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
+ ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
+ ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
+ ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
+ ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
+}
+
+void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
+{
+ ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
+ ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
+ ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
+ ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
+ ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
+
+ spin_unlock_irqrestore(&ixp2000_slowport_lock,
+ ixp2000_slowport_irq_flags);
+}
+
+/*************************************************************************
+ * Chip specific mappings shared by all IXP2000 systems
+ *************************************************************************/
+static struct map_desc ixp2000_small_io_desc[] __initdata = {
+ {
+ .virtual = IXP2000_GLOBAL_REG_VIRT_BASE,
+ .physical = IXP2000_GLOBAL_REG_PHYS_BASE,
+ .length = IXP2000_GLOBAL_REG_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_GPIO_VIRT_BASE,
+ .physical = IXP2000_GPIO_PHYS_BASE,
+ .length = IXP2000_GPIO_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_TIMER_VIRT_BASE,
+ .physical = IXP2000_TIMER_PHYS_BASE,
+ .length = IXP2000_TIMER_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_UART_VIRT_BASE,
+ .physical = IXP2000_UART_PHYS_BASE,
+ .length = IXP2000_UART_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_SLOWPORT_CSR_VIRT_BASE,
+ .physical = IXP2000_SLOWPORT_CSR_PHYS_BASE,
+ .length = IXP2000_SLOWPORT_CSR_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_INTCTL_VIRT_BASE,
+ .physical = IXP2000_INTCTL_PHYS_BASE,
+ .length = IXP2000_INTCTL_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_PCI_CREG_VIRT_BASE,
+ .physical = IXP2000_PCI_CREG_PHYS_BASE,
+ .length = IXP2000_PCI_CREG_SIZE,
+ .type = MT_DEVICE
+ }
+};
+
+static struct map_desc ixp2000_large_io_desc[] __initdata = {
+ {
+ .virtual = IXP2000_PCI_CSR_VIRT_BASE,
+ .physical = IXP2000_PCI_CSR_PHYS_BASE,
+ .length = IXP2000_PCI_CSR_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_PCI_IO_VIRT_BASE,
+ .physical = IXP2000_PCI_IO_PHYS_BASE,
+ .length = IXP2000_PCI_IO_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
+ .physical = IXP2000_PCI_CFG0_PHYS_BASE,
+ .length = IXP2000_PCI_CFG0_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
+ .physical = IXP2000_PCI_CFG1_PHYS_BASE,
+ .length = IXP2000_PCI_CFG1_SIZE,
+ .type = MT_DEVICE
+ }
+};
+
+static struct uart_port ixp2000_serial_port = {
+ .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
+ .mapbase = IXP2000_UART_PHYS_BASE + 3,
+ .irq = IRQ_IXP2000_UART,
+ .flags = UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = 50000000,
+ .line = 0,
+ .type = PORT_XSCALE,
+ .fifosize = 16
+};
+
+void __init ixp2000_map_io(void)
+{
+ iotable_init(ixp2000_small_io_desc, ARRAY_SIZE(ixp2000_small_io_desc));
+ iotable_init(ixp2000_large_io_desc, ARRAY_SIZE(ixp2000_large_io_desc));
+ early_serial_setup(&ixp2000_serial_port);
+}
+
+/*************************************************************************
+ * Timer-tick functions for IXP2000
+ *************************************************************************/
+static unsigned ticks_per_jiffy;
+static unsigned ticks_per_usec;
+
+static unsigned long ixp2000_gettimeoffset (void)
+{
+ unsigned long elapsed;
+
+ /* Get ticks since last perfect jiffy */
+ elapsed = ticks_per_jiffy - *IXP2000_T1_CSR;
+
+ return elapsed / ticks_per_usec;
+}
+
+static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ /* clear timer 1 */
+ ixp2000_reg_write(IXP2000_T1_CLR, 1);
+
+ timer_tick(regs);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction ixp2000_timer_irq = {
+ .name = "IXP2000 Timer Tick",
+ .flags = SA_INTERRUPT,
+ .handler = ixp2000_timer_interrupt
+};
+
+void __init ixp2000_init_time(unsigned long tick_rate)
+{
+ gettimeoffset = ixp2000_gettimeoffset;
+
+ ixp2000_reg_write(IXP2000_T1_CLR, 0);
+ ixp2000_reg_write(IXP2000_T2_CLR, 0);
+
+ ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
+ ticks_per_usec = tick_rate / 1000000;
+
+ ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy);
+ ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
+
+ /* register for interrupt */
+ setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
+}
+
+/*************************************************************************
+ * GPIO helpers
+ *************************************************************************/
+static unsigned long GPIO_IRQ_rising_edge;
+static unsigned long GPIO_IRQ_falling_edge;
+static unsigned long GPIO_IRQ_level_low;
+static unsigned long GPIO_IRQ_level_high;
+
+void gpio_line_config(int line, int style)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ if(style == GPIO_OUT) {
+ /* if it's an output, it ain't an interrupt anymore */
+ ixp2000_reg_write(IXP2000_GPIO_PDSR, (1 << line));
+ GPIO_IRQ_falling_edge &= ~(1 << line);
+ GPIO_IRQ_rising_edge &= ~(1 << line);
+ GPIO_IRQ_level_low &= ~(1 << line);
+ GPIO_IRQ_level_high &= ~(1 << line);
+ ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
+ ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
+ ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
+ ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
+ irq_desc[line+IRQ_IXP2000_GPIO0].valid = 0;
+ } else if(style == GPIO_IN) {
+ ixp2000_reg_write(IXP2000_GPIO_PDCR, (1 << line));
+ }
+
+ local_irq_restore(flags);
+}
+
+
+/*************************************************************************
+ * IRQ handling IXP2000
+ *************************************************************************/
+static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+ int i;
+ unsigned long status = *IXP2000_GPIO_INST;
+
+ for (i = 0; i <= 7; i++) {
+ if (status & (1<<i)) {
+ desc = irq_desc + i + IRQ_IXP2000_GPIO0;
+ desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
+ }
+ }
+}
+
+static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
+ ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
+}
+
+static void ixp2000_GPIO_irq_mask(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
+}
+
+static void ixp2000_GPIO_irq_unmask(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
+}
+
+static struct irqchip ixp2000_GPIO_irq_chip = {
+ .ack = ixp2000_GPIO_irq_mask_ack,
+ .mask = ixp2000_GPIO_irq_mask,
+ .unmask = ixp2000_GPIO_irq_unmask
+};
+
+static void ixp2000_pci_irq_mask(unsigned int irq)
+{
+ unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
+ if (irq == IRQ_IXP2000_PCIA)
+ ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
+ else if (irq == IRQ_IXP2000_PCIB)
+ ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
+}
+
+static void ixp2000_pci_irq_unmask(unsigned int irq)
+{
+ unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
+ if (irq == IRQ_IXP2000_PCIA)
+ ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
+ else if (irq == IRQ_IXP2000_PCIB)
+ ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
+}
+
+static struct irqchip ixp2000_pci_irq_chip = {
+ .ack = ixp2000_pci_irq_mask,
+ .mask = ixp2000_pci_irq_mask,
+ .unmask = ixp2000_pci_irq_unmask
+};
+
+/*
+ * Error interrupts. These are used extensively by the microengine drivers
+ */
+static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+ int i;
+ unsigned long status = *IXP2000_IRQ_ERR_STATUS;
+
+
+ for (i = 0; i <= 12; i++) {
+ if (status & (1 << i)) {
+ desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
+ desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
+ }
+ }
+}
+
+static void ixp2000_err_irq_mask(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
+ (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
+}
+
+static void ixp2000_err_irq_unmask(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
+ (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
+}
+
+static struct irqchip ixp2000_err_irq_chip = {
+ .ack = ixp2000_err_irq_mask,
+ .mask = ixp2000_err_irq_mask,
+ .unmask = ixp2000_err_irq_unmask
+};
+
+static void ixp2000_irq_mask(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
+}
+
+static void ixp2000_irq_unmask(unsigned int irq)
+{
+ ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
+}
+
+static struct irqchip ixp2000_irq_chip = {
+ .ack = ixp2000_irq_mask,
+ .mask = ixp2000_irq_mask,
+ .unmask = ixp2000_irq_unmask
+};
+
+void __init ixp2000_init_irq(void)
+{
+ int irq;
+
+ /*
+ * Mask all sources
+ */
+ ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
+ ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
+
+ /* clear all GPIO edge/level detects */
+ ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
+ ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
+ ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
+ ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
+ ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
+
+ /* clear PCI interrupt sources */
+ ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
+
+ /*
+ * Certain bits in the IRQ status register of the
+ * IXP2000 are reserved. Instead of trying to map
+ * things non 1:1 from bit position to IRQ number,
+ * we mark the reserved IRQs as invalid. This makes
+ * our mask/unmask code much simpler.
+ */
+ for (irq = IRQ_IXP2000_SWI; irq <= IRQ_IXP2000_THDB3; irq++) {
+ if((1 << irq) & IXP2000_VALID_IRQ_MASK) {
+ set_irq_chip(irq, &ixp2000_irq_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ } else set_irq_flags(irq, 0);
+ }
+
+ /*
+ * GPIO IRQs are invalid until someone sets the interrupt mode
+ * by calling gpio_line_set();
+ */
+ for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
+ set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, 0);
+ }
+ set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
+
+ /*
+ * Enable PCI irq
+ */
+ *(IXP2000_IRQ_ENABLE_SET) = (1 << IRQ_IXP2000_PCI);
+ for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
+ set_irq_chip(irq, &ixp2000_pci_irq_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
+ set_irq_chip(irq, &ixp2000_err_irq_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+ set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
+}
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/enp2611.c
+ *
+ * Radisys ENP-2611 support.
+ *
+ * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
+ * original version carries the following notices:
+ *
+ * Original Author: Andrzej Mialwoski <andrzej.mialwoski@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002-2003 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+/*************************************************************************
+ * ENP-2611 timer tick configuration
+ *************************************************************************/
+static void __init enp2611_init_time(void)
+{
+ ixp2000_init_time(50 * 1000 * 1000);
+}
+
+
+/*************************************************************************
+ * ENP-2611 PCI
+ *************************************************************************/
+static int enp2611_pci_setup(int nr, struct pci_sys_data *sys)
+{
+ sys->mem_offset = 0xe0000000;
+ ixp2000_pci_setup(nr, sys);
+ return 1;
+}
+
+static void __init enp2611_pci_preinit(void)
+{
+ ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
+ ixp2000_pci_preinit();
+}
+
+static inline int enp2611_pci_valid_device(struct pci_bus *bus,
+ unsigned int devfn)
+{
+ /* The 82559 ethernet controller appears at both PCI:1:0:0 and
+ * PCI:1:2:0, so let's pretend the second one isn't there.
+ */
+ if (bus->number == 0x01 && devfn == 0x10)
+ return 0;
+
+ return 1;
+}
+
+static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *value)
+{
+ if (enp2611_pci_valid_device(bus, devfn))
+ return ixp2000_pci_read_config(bus, devfn, where, size, value);
+
+ return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 value)
+{
+ if (enp2611_pci_valid_device(bus, devfn))
+ return ixp2000_pci_write_config(bus, devfn, where, size, value);
+
+ return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static struct pci_ops enp2611_pci_ops = {
+ .read = enp2611_pci_read_config,
+ .write = enp2611_pci_write_config
+};
+
+static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
+ struct pci_sys_data *sys)
+{
+ return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys);
+}
+
+static int __init enp2611_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq;
+
+ if (dev->bus->number == 0x00 && PCI_SLOT(dev->devfn) == 0x01) {
+ /* 21555 non-transparent bridge. */
+ irq = IRQ_IXP2000_PCIB;
+ } else if (dev->bus->number == 0x01 && PCI_SLOT(dev->devfn) == 0x00) {
+ /* 82559 ethernet. */
+ irq = IRQ_IXP2000_PCIA;
+ } else {
+ printk(KERN_INFO "enp2611_pci_map_irq for unknown device\n");
+ irq = IRQ_IXP2000_PCI;
+ }
+
+ printk(KERN_INFO "Assigned IRQ %d to PCI:%d:%d:%d\n", irq,
+ dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
+
+ return irq;
+}
+
+struct hw_pci enp2611_pci __initdata = {
+ .nr_controllers = 1,
+ .setup = enp2611_pci_setup,
+ .preinit = enp2611_pci_preinit,
+ .scan = enp2611_pci_scan_bus,
+ .map_irq = enp2611_pci_map_irq,
+};
+
+int __init enp2611_pci_init(void)
+{
+ pci_common_init(&enp2611_pci);
+ return 0;
+}
+
+subsys_initcall(enp2611_pci_init);
+
+
+/*************************************************************************
+ * ENP-2611 Machine Intialization
+ *************************************************************************/
+static struct flash_platform_data enp2611_flash_platform_data = {
+ .map_name = "cfi_probe",
+ .width = 1,
+};
+
+static struct ixp2000_flash_data enp2611_flash_data = {
+ .platform_data = &enp2611_flash_platform_data,
+ .nr_banks = 1
+};
+
+static struct resource enp2611_flash_resource = {
+ .start = 0xc4000000,
+ .end = 0xc4000000 + 0x00ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device enp2611_flash = {
+ .name = "IXP2000-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &enp2611_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &enp2611_flash_resource,
+};
+
+static struct platform_device *enp2611_devices[] __initdata = {
+ &enp2611_flash
+};
+
+static void __init enp2611_init_machine(void)
+{
+ platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices));
+}
+
+
+#ifdef CONFIG_ARCH_ENP2611
+MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
+ MAINTAINER("Lennert Buytenhek <buytenh@wantstofly.org>")
+ BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
+ BOOT_PARAMS(0x00000100)
+ MAPIO(ixp2000_map_io)
+ INITIRQ(ixp2000_init_irq)
+ INITTIME(enp2611_init_time)
+ INIT_MACHINE(enp2611_init_machine)
+MACHINE_END
+#endif
+
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/ixdp2400.c
+ *
+ * IXDP2400 platform support
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/arch.h>
+
+/*************************************************************************
+ * IXDP2400 timer tick
+ *************************************************************************/
+static void __init ixdp2400_init_time(void)
+{
+ int numerator, denominator;
+ int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8};
+
+ numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2;
+ denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)];
+
+ ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2);
+}
+
+/*************************************************************************
+ * IXDP2400 PCI
+ *************************************************************************/
+void __init ixdp2400_pci_preinit(void)
+{
+ ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
+ ixp2000_pci_preinit();
+}
+
+int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys)
+{
+ sys->mem_offset = 0xe0000000;
+
+ ixp2000_pci_setup(nr, sys);
+
+ return 1;
+}
+
+static int __init ixdp2400_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (ixdp2x00_master_npu()) {
+
+ /*
+ * Root bus devices. Slave NPU is only one with interrupt.
+ * Everything else, we just return -1 b/c nothing else
+ * on the root bus has interrupts.
+ */
+ if(!dev->bus->self) {
+ if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
+ return IRQ_IXDP2400_INGRESS_NPU;
+
+ return -1;
+ }
+
+ /*
+ * Bridge behind the PMC slot.
+ * NOTE: Only INTA from the PMC slot is routed. VERY BAD.
+ */
+ if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
+ dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
+ !dev->bus->parent->self->bus->parent)
+ return IRQ_IXDP2400_PMC;
+
+ /*
+ * Device behind the first bridge
+ */
+ if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
+ switch(dev->devfn) {
+ case IXDP2400_MASTER_ENET_DEVFN:
+ return IRQ_IXDP2400_ENET;
+
+ case IXDP2400_MEDIA_DEVFN:
+ return IRQ_IXDP2400_MEDIA_PCI;
+
+ case IXDP2400_SWITCH_FABRIC_DEVFN:
+ return IRQ_IXDP2400_SF_PCI;
+
+ case IXDP2X00_PMC_DEVFN:
+ return IRQ_IXDP2400_PMC;
+ }
+ }
+
+ return -1;
+ } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
+}
+
+
+static void ixdp2400_pci_postinit(void)
+{
+ struct pci_dev *dev;
+
+ if (ixdp2x00_master_npu()) {
+ dev = pci_find_slot(1, IXDP2400_SLAVE_ENET_DEVFN);
+ pci_remove_bus_device(dev);
+ } else {
+ dev = pci_find_slot(1, IXDP2400_MASTER_ENET_DEVFN);
+ pci_remove_bus_device(dev);
+
+ ixdp2x00_slave_pci_postinit();
+ }
+}
+
+static struct hw_pci ixdp2400_pci __initdata = {
+ .nr_controllers = 1,
+ .setup = ixdp2400_pci_setup,
+ .preinit = ixdp2400_pci_preinit,
+ .postinit = ixdp2400_pci_postinit,
+ .scan = ixp2000_pci_scan_bus,
+ .map_irq = ixdp2400_pci_map_irq,
+};
+
+int __init ixdp2400_pci_init(void)
+{
+ if (machine_is_ixdp2400())
+ pci_common_init(&ixdp2400_pci);
+
+ return 0;
+}
+
+subsys_initcall(ixdp2400_pci_init);
+
+void ixdp2400_init_irq(void)
+{
+ ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS);
+}
+
+MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
+ MAINTAINER("MontaVista Software, Inc.")
+ BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
+ BOOT_PARAMS(0x00000100)
+ MAPIO(ixdp2x00_map_io)
+ INITIRQ(ixdp2400_init_irq)
+ INITTIME(ixdp2400_init_time)
+ INIT_MACHINE(ixdp2x00_init_machine)
+MACHINE_END
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/ixdp2800.c
+ *
+ * IXDP2800 platform support
+ *
+ * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/arch.h>
+
+
+void ixdp2400_init_irq(void)
+{
+ ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2400_NR_IRQS);
+}
+
+/*************************************************************************
+ * IXDP2800 timer tick
+ *************************************************************************/
+
+static void __init ixdp2800_init_time(void)
+{
+ ixp2000_init_time(50000000);
+}
+
+/*************************************************************************
+ * IXDP2800 PCI
+ *************************************************************************/
+void __init ixdp2800_pci_preinit(void)
+{
+ printk("ixdp2x00_pci_preinit called\n");
+
+ *IXP2000_PCI_ADDR_EXT = 0x0000e000;
+
+ *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
+ *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
+
+ ixp2000_pci_preinit();
+}
+
+int ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
+{
+ sys->mem_offset = 0x00000000;
+
+ ixp2000_pci_setup(nr, sys);
+
+ return 1;
+}
+
+static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (ixdp2x00_master_npu()) {
+
+ /*
+ * Root bus devices. Slave NPU is only one with interrupt.
+ * Everything else, we just return -1 which is invalid.
+ */
+ if(!dev->bus->self) {
+ if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
+ return IRQ_IXDP2800_INGRESS_NPU;
+
+ return -1;
+ }
+
+ /*
+ * Bridge behind the PMC slot.
+ */
+ if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
+ dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
+ !dev->bus->parent->self->bus->parent)
+ return IRQ_IXDP2800_PMC;
+
+ /*
+ * Device behind the first bridge
+ */
+ if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
+ switch(PCI_SLOT(dev->devfn)) {
+ case IXDP2X00_PMC_DEVFN:
+ return IRQ_IXDP2800_PMC;
+
+ case IXDP2800_MASTER_ENET_DEVFN:
+ return IRQ_IXDP2800_EGRESS_ENET;
+
+ case IXDP2800_SWITCH_FABRIC_DEVFN:
+ return IRQ_IXDP2800_FABRIC;
+ }
+ }
+
+ return -1;
+ } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
+}
+
+static void ixdp2800_pci_postinit(void)
+{
+ struct pci_dev *dev;
+
+ if (ixdp2x00_master_npu()) {
+ dev = pci_find_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
+ pci_remove_bus_device(dev);
+ } else {
+ dev = pci_find_slot(1, IXDP2800_MASTER_ENET_DEVFN);
+ pci_remove_bus_device(dev);
+
+ ixdp2x00_slave_pci_postinit();
+ }
+}
+
+struct hw_pci ixdp2800_pci __initdata = {
+ .nr_controllers = 1,
+ .setup = ixdp2800_pci_setup,
+ .preinit = ixdp2800_pci_preinit,
+ .postinit = ixdp2800_pci_postinit,
+ .scan = ixp2000_pci_scan_bus,
+ .map_irq = ixdp2800_pci_map_irq,
+};
+
+int __init ixdp2800_pci_init(void)
+{
+ if (machine_is_ixdp2800())
+ pci_common_init(&ixdp2800_pci);
+
+ return 0;
+}
+
+subsys_initcall(ixdp2800_pci_init);
+
+void ixdp2800_init_irq(void)
+{
+ ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
+}
+
+MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
+ MAINTAINER("MontaVista Software, Inc.")
+ BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
+ BOOT_PARAMS(0x00000100)
+ MAPIO(ixdp2x00_map_io)
+ INITIRQ(ixdp2800_init_irq)
+ INITTIME(ixdp2800_init_time)
+ INIT_MACHINE(ixdp2x00_init_machine)
+MACHINE_END
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/ixdp2x00.c
+ *
+ * Code common to IXDP2400 and IXDP2800 platforms.
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/arch.h>
+
+/*************************************************************************
+ * IXDP2x00 IRQ Initialization
+ *************************************************************************/
+static volatile unsigned long *board_irq_mask;
+static volatile unsigned long *board_irq_stat;
+static unsigned long board_irq_count;
+
+#ifdef CONFIG_ARCH_IXDP2400
+/*
+ * Slowport configuration for accessing CPLD registers on IXDP2x00
+ */
+static struct slowport_cfg slowport_cpld_cfg = {
+ .CCR = SLOWPORT_CCR_DIV_2,
+ .WTC = 0x00000070,
+ .RTC = 0x00000070,
+ .PCR = SLOWPORT_MODE_FLASH,
+ .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8
+};
+#endif
+
+static void ixdp2x00_irq_mask(unsigned int irq)
+{
+ unsigned long dummy;
+ static struct slowport_cfg old_cfg;
+
+ /*
+ * This is ugly in common code but really don't know
+ * of a better way to handle it. :(
+ */
+#ifdef CONFIG_ARCH_IXDP2400
+ if (machine_is_ixdp2400())
+ ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
+#endif
+
+ dummy = *board_irq_mask;
+ dummy |= IXP2000_BOARD_IRQ_MASK(irq);
+ ixp2000_reg_write(board_irq_mask, dummy);
+
+#ifdef CONFIG_ARCH_IXDP2400
+ if (machine_is_ixdp2400())
+ ixp2000_release_slowport(&old_cfg);
+#endif
+}
+
+static void ixdp2x00_irq_unmask(unsigned int irq)
+{
+ unsigned long dummy;
+ static struct slowport_cfg old_cfg;
+
+#ifdef CONFGI_ARCH_IXDP2400
+ if (machine_is_ixdp2400())
+ ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
+#endif
+
+ dummy = *board_irq_mask;
+ dummy &= ~IXP2000_BOARD_IRQ_MASK(irq);
+ ixp2000_reg_write(board_irq_mask, dummy);
+
+ if (machine_is_ixdp2400())
+ ixp2000_release_slowport(&old_cfg);
+}
+
+static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+ volatile u32 ex_interrupt = 0;
+ static struct slowport_cfg old_cfg;
+ int i;
+
+ desc->chip->mask(irq);
+
+#ifdef CONFIG_ARCH_IXDP2400
+ if (machine_is_ixdp2400())
+ ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
+#endif
+ ex_interrupt = *board_irq_stat & 0xff;
+ if (machine_is_ixdp2400())
+ ixp2000_release_slowport(&old_cfg);
+
+ if(!ex_interrupt) {
+ printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n");
+ return;
+ }
+
+ for(i = 0; i < board_irq_count; i++) {
+ if(ex_interrupt & (1 << i)) {
+ struct irqdesc *cpld_desc;
+ int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
+ cpld_desc = irq_desc + cpld_irq;
+ cpld_desc->handle(cpld_irq, cpld_desc, regs);
+ }
+ }
+
+ desc->chip->unmask(irq);
+}
+
+static struct irqchip ixdp2x00_cpld_irq_chip = {
+ .ack = ixdp2x00_irq_mask,
+ .mask = ixdp2x00_irq_mask,
+ .unmask = ixdp2x00_irq_unmask
+};
+
+void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_irqs)
+{
+ unsigned int irq;
+
+ ixp2000_init_irq();
+
+ if (!ixdp2x00_master_npu())
+ return;
+
+ board_irq_stat = stat_reg;
+ board_irq_mask = mask_reg;
+ board_irq_count = nr_irqs;
+
+ *board_irq_mask = 0xffffffff;
+
+ for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
+ set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ /* Hook into PCI interrupt */
+ set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x00_irq_handler);
+}
+
+/*************************************************************************
+ * IXDP2x00 memory map
+ *************************************************************************/
+static struct map_desc ixdp2x00_io_desc __initdata = {
+ .virtual = IXDP2X00_VIRT_CPLD_BASE,
+ .physical = IXDP2X00_PHYS_CPLD_BASE,
+ .length = IXDP2X00_CPLD_SIZE,
+ .type = MT_DEVICE
+};
+
+void __init ixdp2x00_map_io(void)
+{
+ ixp2000_map_io();
+
+ iotable_init(&ixdp2x00_io_desc, 1);
+}
+
+/*************************************************************************
+ * IXDP2x00-common PCI init
+ *
+ * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board
+ * contains two NPUs (ingress and egress) connected over PCI, both running
+ * instances of the kernel. So far so good. Peers on the PCI bus running
+ * Linux is a common design in telecom systems. The problem is that instead
+ * of all the devices being controlled by a single host, different
+ * devices are controlles by different NPUs on the same bus, leading to
+ * multiple hosts on the bus.i The exact bus layout looks like:
+ *
+ * Bus 0
+ * Master NPU <-------------------+-------------------> Slave NPU
+ * |
+ * |
+ * P2P
+ * |
+ *
+ * Bus 1 |
+ * <--+------+---------+---------+------+-->
+ * | | | | |
+ * | | | | |
+ * ... Dev PMC Media Eth0 Eth1 ...
+ *
+ * The master controlls all but Eth1, which is controlled by the
+ * slave. What this measn is that the both the master and the slave
+ * have to scan the bus, but only one of them can enumerate the bus.
+ * In addition, after the bus is scaned, each kernel must remove
+ * the device(s) it does not control from the PCI dev list otherwise
+ * a driver on each NPU will try to manage it and we will have horrible
+ * conflicts. Oh..and the slave NPU needs to see the master NPU
+ * for Intel's drivers to work properly. Closed source drivers...
+ *
+ * The way we deal with this is fairly simple but ugly:
+ *
+ * 1) Let master scan and enumerate the bus completely.
+ * 2) Master deletes Eth1 from device list.
+ * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave)
+ * from device list.
+ * 4) Find HW designers and LART them.
+ *
+ * The boards also do not do normal PCI IRQ routing, or any sort of
+ * sensical swizzling, so we just need to check where on the bus a
+ * device sits and figure out to which CPLD pin the interrupt is routed.
+ * See ixdp2[48]00.c files.
+ *
+ *************************************************************************/
+void ixdp2x00_slave_pci_postinit(void)
+{
+ struct pci_dev *dev;
+
+ /*
+ * Remove PMC device is there is one
+ */
+ if((dev = pci_find_slot(1, IXDP2X00_PMC_DEVFN)))
+ pci_remove_bus_device(dev);
+
+ dev = pci_find_slot(0, IXDP2X00_21555_DEVFN);
+ pci_remove_bus_device(dev);
+}
+
+/**************************************************************************
+ * IXDP2x00 Machine Setup
+ *************************************************************************/
+static struct flash_platform_data ixdp2x00_platform_data = {
+ .map_name = "cfi_probe",
+ .width = 1,
+};
+
+static struct ixp2000_flash_data ixdp2x00_flash_data = {
+ .platform_data = &ixdp2x00_platform_data,
+ .nr_banks = 1
+};
+
+static struct resource ixdp2x00_flash_resource = {
+ .start = 0xc4000000,
+ .end = 0xc4000000 + 0x00ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ixdp2x00_flash = {
+ .name = "IXP2000-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &ixdp2x00_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &ixdp2x00_flash_resource,
+};
+
+static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = {
+ .sda_pin = IXDP2X00_GPIO_SDA,
+ .scl_pin = IXDP2X00_GPIO_SCL,
+};
+
+static struct platform_device ixdp2x00_i2c_controller = {
+ .name = "IXP2000-I2C",
+ .id = 0,
+ .dev = {
+ .platform_data = &ixdp2x00_i2c_gpio_pins,
+ },
+ .num_resources = 0
+};
+
+static struct platform_device *ixdp2x00_devices[] __initdata = {
+ &ixdp2x00_flash,
+ &ixdp2x00_i2c_controller
+};
+
+void __init ixdp2x00_init_machine(void)
+{
+ gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1);
+ gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
+
+ platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));
+}
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/ixdp2x01.c
+ *
+ * Code common to Intel IXDP2401 and IXDP2801 platforms
+ *
+ * Original Author: Andrzej Mialwoski <andrzej.mialwoski@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002-2003 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+/*************************************************************************
+ * IXDP2x01 IRQ Handling
+ *************************************************************************/
+static void ixdp2x01_irq_mask(unsigned int irq)
+{
+ *IXDP2X01_INT_MASK_SET_REG = IXP2000_BOARD_IRQ_MASK(irq);
+}
+
+static void ixdp2x01_irq_unmask(unsigned int irq)
+{
+ *IXDP2X01_INT_MASK_CLR_REG = IXP2000_BOARD_IRQ_MASK(irq);
+}
+
+static u32 valid_irq_mask;
+
+static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+ u32 ex_interrupt;
+ int i;
+
+ desc->chip->mask(irq);
+
+ ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
+
+ if (!ex_interrupt) {
+ printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
+ return;
+ }
+
+ for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
+ if (ex_interrupt & (1 << i)) {
+ struct irqdesc *cpld_desc;
+ int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
+ cpld_desc = irq_desc + cpld_irq;
+ cpld_desc->handle(cpld_irq, cpld_desc, regs);
+ }
+ }
+
+ desc->chip->unmask(irq);
+}
+
+static struct irqchip ixdp2x01_irq_chip = {
+ .mask = ixdp2x01_irq_mask,
+ .ack = ixdp2x01_irq_mask,
+ .unmask = ixdp2x01_irq_unmask
+};
+
+/*
+ * We only do anything if we are the master NPU on the board.
+ * The slave NPU only has the ethernet chip going directly to
+ * the PCIB interrupt input.
+ */
+void __init ixdp2x01_init_irq(void)
+{
+ int irq = 0;
+
+ /* initialize chip specific interrupts */
+ ixp2000_init_irq();
+
+ if (machine_is_ixdp2401())
+ valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
+ else
+ valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
+
+ /* Mask all interrupts from CPLD, disable simulation */
+ *IXDP2X01_INT_MASK_SET_REG = 0xffffffff;
+ *IXDP2X01_INT_SIM_REG = 0;
+
+ for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
+ if (irq & valid_irq_mask) {
+ set_irq_chip(irq, &ixdp2x01_irq_chip);
+ set_irq_handler(irq, do_level_IRQ);
+ set_irq_flags(irq, IRQF_VALID);
+ } else {
+ set_irq_flags(irq, 0);
+ }
+ }
+
+ /* Hook into PCI interrupts */
+ set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler);
+}
+
+
+/*************************************************************************
+ * IXDP2x01 memory map and serial ports
+ *************************************************************************/
+static struct map_desc ixdp2x01_io_desc __initdata = {
+ .virtual = IXDP2X01_VIRT_CPLD_BASE,
+ .physical = IXDP2X01_PHYS_CPLD_BASE,
+ .length = IXDP2X01_CPLD_REGION_SIZE,
+ .type = MT_DEVICE
+};
+
+static struct uart_port ixdp2x01_serial_ports[2] = {
+ {
+ .membase = (char *)(IXDP2X01_UART1_VIRT_BASE),
+ .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
+ .irq = IRQ_IXDP2X01_UART1,
+ .flags = UPF_SKIP_TEST,
+ .iotype = UPIO_MEM32,
+ .regshift = 2,
+ .uartclk = IXDP2X01_UART_CLK,
+ .line = 1,
+ .type = PORT_16550A,
+ .fifosize = 16
+ }, {
+ .membase = (char *)(IXDP2X01_UART2_VIRT_BASE),
+ .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
+ .irq = IRQ_IXDP2X01_UART2,
+ .flags = UPF_SKIP_TEST,
+ .iotype = UPIO_MEM32,
+ .regshift = 2,
+ .uartclk = IXDP2X01_UART_CLK,
+ .line = 2,
+ .type = PORT_16550A,
+ .fifosize = 16
+ },
+};
+
+static void __init ixdp2x01_map_io(void)
+{
+ ixp2000_map_io();
+
+ iotable_init(&ixdp2x01_io_desc, 1);
+
+ early_serial_setup(&ixdp2x01_serial_ports[0]);
+ early_serial_setup(&ixdp2x01_serial_ports[1]);
+}
+
+
+/*************************************************************************
+ * IXDP2x01 timer tick configuration
+ *************************************************************************/
+static unsigned int ixdp2x01_clock;
+
+static int __init ixdp2x01_clock_setup(char *str)
+{
+ ixdp2x01_clock = simple_strtoul(str, NULL, 10);
+
+ return 1;
+}
+
+__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
+
+static void __init ixdp2x01_init_time(void)
+{
+ if (!ixdp2x01_clock)
+ ixdp2x01_clock = 50000000;
+
+ ixp2000_init_time(ixdp2x01_clock);
+}
+
+/*************************************************************************
+ * IXDP2x01 PCI
+ *************************************************************************/
+void __init ixdp2x01_pci_preinit(void)
+{
+ ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
+ ixp2000_pci_preinit();
+}
+
+#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
+
+static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ u8 bus = dev->bus->number;
+ u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
+ struct pci_bus *tmp_bus = dev->bus;
+
+ /* Primary bus, no interrupts here */
+ if (bus == 0) {
+ return -1;
+ }
+
+ /* Lookup first leaf in bus tree */
+ while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
+ tmp_bus = tmp_bus->parent;
+ }
+
+ /* Select between known bridges */
+ switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
+ /* Device is located after first MB bridge */
+ case 0x0008:
+ if (tmp_bus == dev->bus) {
+ /* Device is located directy after first MB bridge */
+ switch (devpin) {
+ case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
+ if (machine_is_ixdp2401())
+ return IRQ_IXDP2401_INTA_82546;
+ return -1;
+ case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
+ if (machine_is_ixdp2401())
+ return IRQ_IXDP2401_INTB_82546;
+ return -1;
+ case DEVPIN(0, 1): /* PMC INTA# */
+ return IRQ_IXDP2X01_SPCI_PMC_INTA;
+ case DEVPIN(0, 2): /* PMC INTB# */
+ return IRQ_IXDP2X01_SPCI_PMC_INTB;
+ case DEVPIN(0, 3): /* PMC INTC# */
+ return IRQ_IXDP2X01_SPCI_PMC_INTC;
+ case DEVPIN(0, 4): /* PMC INTD# */
+ return IRQ_IXDP2X01_SPCI_PMC_INTD;
+ }
+ }
+ break;
+ case 0x0010:
+ if (tmp_bus == dev->bus) {
+ /* Device is located directy after second MB bridge */
+ /* Secondary bus of second bridge */
+ switch (devpin) {
+ case DEVPIN(0, 1): /* DB#0 */
+ return IRQ_IXDP2X01_SPCI_DB_0;
+ case DEVPIN(1, 1): /* DB#1 */
+ return IRQ_IXDP2X01_SPCI_DB_1;
+ }
+ } else {
+ /* Device is located indirectly after second MB bridge */
+ /* Not supported now */
+ }
+ break;
+ }
+
+ return -1;
+}
+
+
+static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
+{
+ sys->mem_offset = 0xe0000000;
+
+ if (machine_is_ixdp2801())
+ sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
+
+ return ixp2000_pci_setup(nr, sys);
+}
+
+struct hw_pci ixdp2x01_pci __initdata = {
+ .nr_controllers = 1,
+ .setup = ixdp2x01_pci_setup,
+ .preinit = ixdp2x01_pci_preinit,
+ .scan = ixp2000_pci_scan_bus,
+ .map_irq = ixdp2x01_pci_map_irq,
+};
+
+int __init ixdp2x01_pci_init(void)
+{
+
+ pci_common_init(&ixdp2x01_pci);
+ return 0;
+}
+
+subsys_initcall(ixdp2x01_pci_init);
+
+/*************************************************************************
+ * IXDP2x01 Machine Intialization
+ *************************************************************************/
+static struct flash_platform_data ixdp2x01_flash_platform_data = {
+ .map_name = "cfi_probe",
+ .width = 1,
+};
+
+static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
+{
+ *IXDP2X01_CPLD_FLASH_REG =
+ ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN);
+ return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
+}
+
+static struct ixp2000_flash_data ixdp2x01_flash_data = {
+ .platform_data = &ixdp2x01_flash_platform_data,
+ .bank_setup = ixdp2x01_flash_bank_setup
+};
+
+static struct resource ixdp2x01_flash_resource = {
+ .start = 0xc4000000,
+ .end = 0xc4000000 + 0x01ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ixdp2x01_flash = {
+ .name = "IXP2000-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &ixdp2x01_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &ixdp2x01_flash_resource,
+};
+
+static struct platform_device *ixdp2x01_devices[] __initdata = {
+ &ixdp2x01_flash
+};
+
+static void __init ixdp2x01_init_machine(void)
+{
+ *IXDP2X01_CPLD_FLASH_REG =
+ (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN);
+
+ ixdp2x01_flash_data.nr_banks =
+ ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
+
+ platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
+}
+
+
+#ifdef CONFIG_ARCH_IXDP2401
+MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
+ MAINTAINER("MontaVista Software, Inc.")
+ BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
+ BOOT_PARAMS(0x00000100)
+ MAPIO(ixdp2x01_map_io)
+ INITIRQ(ixdp2x01_init_irq)
+ INITTIME(ixdp2x01_init_time)
+ INIT_MACHINE(ixdp2x01_init_machine)
+MACHINE_END
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2801
+MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
+ MAINTAINER("MontaVista Software, Inc.")
+ BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
+ BOOT_PARAMS(0x00000100)
+ MAPIO(ixdp2x01_map_io)
+ INITIRQ(ixdp2x01_init_irq)
+ INITTIME(ixdp2x01_init_time)
+ INIT_MACHINE(ixdp2x01_init_machine)
+MACHINE_END
+#endif
+
+
--- /dev/null
+/*
+ * arch/arm/mach-ixp2000/pci.c
+ *
+ * PCI routines for IXDP2400/IXDP2800 boards
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintained by: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+
+#include <asm/mach/pci.h>
+
+static int pci_master_aborts = 0;
+
+static int clear_master_aborts(void);
+
+static u32 *
+ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
+{
+ u32 *paddress;
+
+ if (PCI_SLOT(devfn) > 7)
+ return 0;
+
+ /* Must be dword aligned */
+ where &= ~3;
+
+ /*
+ * For top bus, generate type 0, else type 1
+ */
+ if (!bus_nr) {
+ /* only bits[23:16] are used for IDSEL */
+ paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE
+ | (1 << (PCI_SLOT(devfn) + 16))
+ | (PCI_FUNC(devfn) << 8) | where);
+ } else {
+ paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE
+ | (bus_nr << 16)
+ | (PCI_SLOT(devfn) << 11)
+ | (PCI_FUNC(devfn) << 8) | where);
+ }
+
+ return paddress;
+}
+
+/*
+ * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
+ * 0 and 3 are not valid indexes...
+ */
+static u32 bytemask[] = {
+ /*0*/ 0,
+ /*1*/ 0xff,
+ /*2*/ 0xffff,
+ /*3*/ 0,
+ /*4*/ 0xffffffff,
+};
+
+
+int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 *value)
+{
+ u32 n;
+ u32 *addr;
+
+ n = where % 4;
+
+ addr = ixp2000_pci_config_addr(bus->number, devfn, where);
+ if (!addr)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ pci_master_aborts = 0;
+ *value = (*addr >> (8*n)) & bytemask[size];
+ if (pci_master_aborts) {
+ pci_master_aborts = 0;
+ *value = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * We don't do error checks by callling clear_master_aborts() b/c the
+ * assumption is that the caller did a read first to make sure a device
+ * exists.
+ */
+int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 value)
+{
+ u32 mask;
+ u32 *addr;
+ u32 temp;
+
+ mask = ~(bytemask[size] << ((where % 0x4) * 8));
+ addr = ixp2000_pci_config_addr(bus->number, devfn, where);
+ if (!addr)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ temp = (u32) (value) << ((where % 0x4) * 8);
+ *addr = (*addr & mask) | temp;
+
+ clear_master_aborts();
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static struct pci_ops ixp2000_pci_ops = {
+ .read = ixp2000_pci_read_config,
+ .write = ixp2000_pci_write_config
+};
+
+struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
+{
+ return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata);
+}
+
+
+int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+
+ volatile u32 temp;
+
+ pci_master_aborts = 1;
+
+ cli();
+ temp = *(IXP2000_PCI_CONTROL);
+ if (temp & ((1 << 8) | (1 << 5))) {
+ *(IXP2000_PCI_CONTROL) = temp;
+ }
+
+ temp = *(IXP2000_PCI_CMDSTAT);
+ if (temp & (1 << 29)) {
+ while (temp & (1 << 29)) {
+ *(IXP2000_PCI_CMDSTAT) = temp;
+ temp = *(IXP2000_PCI_CMDSTAT);
+ }
+ }
+ sti();
+
+ /*
+ * If it was an imprecise abort, then we need to correct the
+ * return address to be _after_ the instruction.
+ */
+ if (fsr & (1 << 10))
+ regs->ARM_pc += 4;
+
+ return 0;
+}
+
+int
+clear_master_aborts(void)
+{
+ volatile u32 temp;
+
+ cli();
+ temp = *(IXP2000_PCI_CONTROL);
+ if (temp & ((1 << 8) | (1 << 5))) {
+ *(IXP2000_PCI_CONTROL) = temp;
+ }
+
+ temp = *(IXP2000_PCI_CMDSTAT);
+ if (temp & (1 << 29)) {
+ while (temp & (1 << 29)) {
+ *(IXP2000_PCI_CMDSTAT) = temp;
+ temp = *(IXP2000_PCI_CMDSTAT);
+ }
+ }
+ sti();
+
+ return 0;
+}
+
+void __init
+ixp2000_pci_preinit(void)
+{
+ hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS,
+ "PCI config cycle to non-existent device");
+}
+
+
+/*
+ * IXP2000 systems often have large resource requirements, so we just
+ * use our own resource space.
+ */
+static struct resource ixp2000_pci_mem_space = {
+ .start = 0x00000000,
+ .end = 0xffffffff,
+ .flags = IORESOURCE_MEM,
+ .name = "PCI Mem Space"
+};
+
+static struct resource ixp2000_pci_io_space = {
+ .start = 0x00000000,
+ .end = 0xffffffff,
+ .flags = IORESOURCE_IO,
+ .name = "PCI I/O Space"
+};
+
+int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
+{
+ if (nr >= 1)
+ return 0;
+
+ sys->resource[0] = &ixp2000_pci_io_space;
+ sys->resource[1] = &ixp2000_pci_mem_space;
+ sys->resource[2] = NULL;
+
+ return 1;
+}
+
--- /dev/null
+/*
+ * linux/arch/arm/mach-omap/board-h2.c
+ *
+ * Board specific inits for OMAP-1610 H2
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * H2 specific changes and cleanup
+ * Copyright (C) 2004 Nokia Corporation by Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/clocks.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/usb.h>
+
+#include "common.h"
+
+extern void __init omap_init_time(void);
+
+static struct map_desc h2_io_desc[] __initdata = {
+{ OMAP1610_ETHR_BASE, OMAP1610_ETHR_START, OMAP1610_ETHR_SIZE,MT_DEVICE },
+{ OMAP1610_NOR_FLASH_BASE, OMAP1610_NOR_FLASH_START, OMAP1610_NOR_FLASH_SIZE,
+ MT_DEVICE },
+};
+
+static struct resource h2_smc91x_resources[] = {
+ [0] = {
+ .start = OMAP1610_ETHR_START, /* Physical */
+ .end = OMAP1610_ETHR_START + SZ_4K,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0, /* Really GPIO 0 */
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device h2_smc91x_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(h2_smc91x_resources),
+ .resource = h2_smc91x_resources,
+};
+
+static struct platform_device *h2_devices[] __initdata = {
+ &h2_smc91x_device,
+};
+
+void h2_init_irq(void)
+{
+ omap_init_irq();
+}
+
+static struct omap_usb_config h2_usb_config __initdata = {
+ /* usb1 has a Mini-AB port and external isp1301 transceiver */
+ .otg = 2,
+
+#ifdef CONFIG_USB_GADGET_OMAP
+ .hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled
+ // .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback)
+#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+ /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
+ .hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled
+#endif
+
+ .pins[1] = 3,
+};
+
+static struct omap_board_config_kernel h2_config[] = {
+ { OMAP_TAG_USB, &h2_usb_config },
+};
+
+static void __init h2_init(void)
+{
+ platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
+ omap_board_config = h2_config;
+ omap_board_config_size = ARRAY_SIZE(h2_config);
+}
+
+static void __init h2_map_io(void)
+{
+ omap_map_io();
+ iotable_init(h2_io_desc, ARRAY_SIZE(h2_io_desc));
+}
+
+MACHINE_START(OMAP_H2, "TI-H2")
+ MAINTAINER("Imre Deak <imre.deak@nokia.com>")
+ BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
+ BOOT_PARAMS(0x10000100)
+ MAPIO(h2_map_io)
+ INITIRQ(h2_init_irq)
+ INIT_MACHINE(h2_init)
+ INITTIME(omap_init_time)
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-omap/board-h3.c
+ *
+ * This file contains OMAP1710 H3 specific code.
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "common.h"
+
+extern void __init omap_init_time(void);
+
+void h3_init_irq(void)
+{
+ omap_init_irq();
+}
+
+static struct resource smc91x_resources[] = {
+ [0] = {
+ .start = OMAP1710_ETHR_START, /* Physical */
+ .end = OMAP1710_ETHR_START + OMAP1710_ETHR_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device smc91x_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smc91x_resources),
+ .resource = smc91x_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &smc91x_device,
+};
+
+static void __init h3_init(void)
+{
+ (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static struct map_desc h3_io_desc[] __initdata = {
+{ OMAP1710_ETHR_BASE, OMAP1710_ETHR_START, OMAP1710_ETHR_SIZE, MT_DEVICE },
+{ OMAP_NOR_FLASH_BASE, OMAP_NOR_FLASH_START, OMAP_NOR_FLASH_SIZE, MT_DEVICE },
+};
+
+static void __init h3_map_io(void)
+{
+ omap_map_io();
+ iotable_init(h3_io_desc, ARRAY_SIZE(h3_io_desc));
+}
+
+MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
+ MAINTAINER("Texas Instruments, Inc.")
+ BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
+ BOOT_PARAMS(0x10000100)
+ MAPIO(h3_map_io)
+ INITIRQ(h3_init_irq)
+ INIT_MACHINE(h3_init)
+ INITTIME(omap_init_time)
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-omap/leds-h2p2-debug.c
+ *
+ * Copyright 2003 by Texas Instruments Incorporated
+ *
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/version.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include <asm/arch/fpga.h>
+
+#include "leds.h"
+
+void h2p2_dbg_leds_event(led_event_t evt)
+{
+ unsigned long flags;
+ static unsigned long hw_led_state = 0;
+
+ local_irq_save(flags);
+
+ switch (evt) {
+ case led_start:
+ hw_led_state |= H2P2_DBG_FPGA_LED_STARTSTOP;
+ break;
+
+ case led_stop:
+ hw_led_state &= ~H2P2_DBG_FPGA_LED_STARTSTOP;
+ break;
+
+ case led_claim:
+ hw_led_state |= H2P2_DBG_FPGA_LED_CLAIMRELEASE;
+ break;
+
+ case led_release:
+ hw_led_state &= ~H2P2_DBG_FPGA_LED_CLAIMRELEASE;
+ break;
+
+#ifdef CONFIG_LEDS_TIMER
+ case led_timer:
+ /*
+ * Toggle Timer LED
+ */
+ if (hw_led_state & H2P2_DBG_FPGA_LED_TIMER)
+ hw_led_state &= ~H2P2_DBG_FPGA_LED_TIMER;
+ else
+ hw_led_state |= H2P2_DBG_FPGA_LED_TIMER;
+ break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+ case led_idle_start:
+ hw_led_state |= H2P2_DBG_FPGA_LED_IDLE;
+ break;
+
+ case led_idle_end:
+ hw_led_state &= ~H2P2_DBG_FPGA_LED_IDLE;
+ break;
+#endif
+
+ case led_halted:
+ if (hw_led_state & H2P2_DBG_FPGA_LED_HALTED)
+ hw_led_state &= ~H2P2_DBG_FPGA_LED_HALTED;
+ else
+ hw_led_state |= H2P2_DBG_FPGA_LED_HALTED;
+ break;
+
+ case led_green_on:
+ break;
+
+ case led_green_off:
+ break;
+
+ case led_amber_on:
+ break;
+
+ case led_amber_off:
+ break;
+
+ case led_red_on:
+ break;
+
+ case led_red_off:
+ break;
+
+ default:
+ break;
+ }
+
+
+ /*
+ * Actually burn the LEDs
+ */
+ __raw_writew(~hw_led_state & 0xffff, H2P2_DBG_FPGA_LEDS);
+
+ local_irq_restore(flags);
+}
--- /dev/null
+/*
+ * linux/arch/arm/omap/mcbsp.c
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/wait.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/mcbsp.h>
+
+#ifdef CONFIG_MCBSP_DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...) do { } while (0)
+#endif
+
+struct omap_mcbsp {
+ u32 io_base;
+ u8 id;
+ u8 free;
+ omap_mcbsp_word_length rx_word_length;
+ omap_mcbsp_word_length tx_word_length;
+
+ /* IRQ based TX/RX */
+ int rx_irq;
+ int tx_irq;
+
+ /* DMA stuff */
+ u8 dma_rx_sync;
+ short dma_rx_lch;
+ u8 dma_tx_sync;
+ short dma_tx_lch;
+
+ /* Completion queues */
+ struct completion tx_irq_completion;
+ struct completion rx_irq_completion;
+ struct completion tx_dma_completion;
+ struct completion rx_dma_completion;
+
+ spinlock_t lock;
+};
+
+static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
+
+
+static void omap_mcbsp_dump_reg(u8 id)
+{
+ DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
+ DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
+ DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
+ DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
+ DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
+ DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
+ DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
+ DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
+ DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
+ DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
+ DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
+ DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
+ DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
+ DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
+ DBG("***********************\n");
+}
+
+
+static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
+
+ DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
+
+ complete(&mcbsp_tx->tx_irq_completion);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
+
+ DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
+
+ complete(&mcbsp_rx->rx_irq_completion);
+ return IRQ_HANDLED;
+}
+
+
+static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
+{
+ struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
+
+ DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
+
+ /* We can free the channels */
+ omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
+ mcbsp_dma_tx->dma_tx_lch = -1;
+
+ complete(&mcbsp_dma_tx->tx_dma_completion);
+}
+
+static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
+{
+ struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
+
+ DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
+
+ /* We can free the channels */
+ omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
+ mcbsp_dma_rx->dma_rx_lch = -1;
+
+ complete(&mcbsp_dma_rx->rx_dma_completion);
+}
+
+
+/*
+ * omap_mcbsp_config simply write a config to the
+ * appropriate McBSP.
+ * You either call this function or set the McBSP registers
+ * by yourself before calling omap_mcbsp_start().
+ */
+
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
+{
+ u32 io_base = mcbsp[id].io_base;
+
+ DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id+1, io_base);
+
+ /* We write the given config */
+ OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
+ OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
+ OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
+ OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
+ OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
+ OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
+ OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
+ OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
+ OMAP_MCBSP_WRITE(io_base, SRGR2, config->mcr2);
+ OMAP_MCBSP_WRITE(io_base, SRGR1, config->mcr1);
+ OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
+}
+
+
+
+static int omap_mcbsp_check(unsigned int id)
+{
+ if (cpu_is_omap730()) {
+ if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
+ return -1;
+ }
+ return 0;
+ }
+
+ if (cpu_is_omap1510() || cpu_is_omap1610() || cpu_is_omap1710()) {
+ if (id > OMAP_MAX_MCBSP_COUNT) {
+ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
+ return -1;
+ }
+ return 0;
+ }
+
+ return -1;
+}
+
+#define DSP_RSTCT2 0xe1008014
+
+static void omap_mcbsp_dsp_request(void)
+{
+ if (cpu_is_omap1510() || cpu_is_omap1610() || cpu_is_omap1710()) {
+ omap_writew((omap_readw(ARM_RSTCT1) | (1 << 1) | (1 << 2)),
+ ARM_RSTCT1);
+ omap_writew((omap_readw(ARM_CKCTL) | 1 << EN_DSPCK),
+ ARM_CKCTL);
+ omap_writew((omap_readw(ARM_IDLECT2) | (1 << EN_APICK)),
+ ARM_IDLECT2);
+
+ /* enable 12MHz clock to mcbsp 1 & 3 */
+ __raw_writew(__raw_readw(DSP_IDLECT2) | (1 << EN_XORPCK),
+ DSP_IDLECT2);
+ __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
+ DSP_RSTCT2);
+ }
+}
+
+static void omap_mcbsp_dsp_free(void)
+{
+ /* Useless for now */
+}
+
+
+int omap_mcbsp_request(unsigned int id)
+{
+ int err;
+
+ if (omap_mcbsp_check(id) < 0)
+ return -EINVAL;
+
+ /*
+ * On 1510, 1610 and 1710, McBSP1 and McBSP3
+ * are DSP public peripherals.
+ */
+ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+ omap_mcbsp_dsp_request();
+
+ spin_lock(&mcbsp[id].lock);
+ if (!mcbsp[id].free) {
+ printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
+ spin_unlock(&mcbsp[id].lock);
+ return -1;
+ }
+
+ mcbsp[id].free = 0;
+ spin_unlock(&mcbsp[id].lock);
+
+ /* We need to get IRQs here */
+ err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
+ "McBSP",
+ (void *) (&mcbsp[id]));
+ if (err != 0) {
+ printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
+ mcbsp[id].tx_irq, mcbsp[id].id);
+ return err;
+ }
+
+ init_completion(&(mcbsp[id].tx_irq_completion));
+
+
+ err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
+ "McBSP",
+ (void *) (&mcbsp[id]));
+ if (err != 0) {
+ printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
+ mcbsp[id].rx_irq, mcbsp[id].id);
+ free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
+ return err;
+ }
+
+ init_completion(&(mcbsp[id].rx_irq_completion));
+ return 0;
+
+}
+
+void omap_mcbsp_free(unsigned int id)
+{
+ if (omap_mcbsp_check(id) < 0)
+ return;
+
+ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+ omap_mcbsp_dsp_free();
+
+ spin_lock(&mcbsp[id].lock);
+ if (mcbsp[id].free) {
+ printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
+ spin_unlock(&mcbsp[id].lock);
+ return;
+ }
+
+ mcbsp[id].free = 1;
+ spin_unlock(&mcbsp[id].lock);
+
+ /* Free IRQs */
+ free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
+ free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
+}
+
+/*
+ * Here we start the McBSP, by enabling the sample
+ * generator, both transmitter and receivers,
+ * and the frame sync.
+ */
+void omap_mcbsp_start(unsigned int id)
+{
+ u32 io_base;
+ u16 w;
+
+ if (omap_mcbsp_check(id) < 0)
+ return;
+
+ io_base = mcbsp[id].io_base;
+
+ mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
+ mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
+
+ /* Start the sample generator */
+ w = OMAP_MCBSP_READ(io_base, SPCR2);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+
+ /* Enable transmitter and receiver */
+ w = OMAP_MCBSP_READ(io_base, SPCR2);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
+
+ w = OMAP_MCBSP_READ(io_base, SPCR1);
+ OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
+
+ udelay(100);
+
+ /* Start frame sync */
+ w = OMAP_MCBSP_READ(io_base, SPCR2);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+
+ /* Dump McBSP Regs */
+ omap_mcbsp_dump_reg(id);
+
+}
+
+void omap_mcbsp_stop(unsigned int id)
+{
+ u32 io_base;
+ u16 w;
+
+ if (omap_mcbsp_check(id) < 0)
+ return;
+
+ io_base = mcbsp[id].io_base;
+
+ /* Reset transmitter */
+ w = OMAP_MCBSP_READ(io_base, SPCR2);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
+
+ /* Reset receiver */
+ w = OMAP_MCBSP_READ(io_base, SPCR1);
+ OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
+
+ /* Reset the sample rate generator */
+ w = OMAP_MCBSP_READ(io_base, SPCR2);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+}
+
+
+/*
+ * IRQ based word transmission.
+ */
+void omap_mcbsp_xmit_word(unsigned int id, u32 word)
+{
+ u32 io_base;
+ omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
+
+ if (omap_mcbsp_check(id) < 0)
+ return;
+
+ io_base = mcbsp[id].io_base;
+
+ wait_for_completion(&(mcbsp[id].tx_irq_completion));
+
+ if (word_length > OMAP_MCBSP_WORD_16)
+ OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
+ OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
+}
+
+u32 omap_mcbsp_recv_word(unsigned int id)
+{
+ u32 io_base;
+ u16 word_lsb, word_msb = 0;
+ omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
+
+ if (omap_mcbsp_check(id) < 0)
+ return -EINVAL;
+
+ io_base = mcbsp[id].io_base;
+
+ wait_for_completion(&(mcbsp[id].rx_irq_completion));
+
+ if (word_length > OMAP_MCBSP_WORD_16)
+ word_msb = OMAP_MCBSP_READ(io_base, DRR2);
+ word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+
+ return (word_lsb | (word_msb << 16));
+}
+
+
+/*
+ * Simple DMA based buffer rx/tx routines.
+ * Nothing fancy, just a single buffer tx/rx through DMA.
+ * The DMA resources are released once the transfer is done.
+ * For anything fancier, you should use your own customized DMA
+ * routines and callbacks.
+ */
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
+{
+ int dma_tx_ch;
+
+ if (omap_mcbsp_check(id) < 0)
+ return -EINVAL;
+
+ if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
+ &mcbsp[id],
+ &dma_tx_ch)) {
+ printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
+ return -EAGAIN;
+ }
+ mcbsp[id].dma_tx_lch = dma_tx_ch;
+
+ DBG("TX DMA on channel %d\n", dma_tx_ch);
+
+ init_completion(&(mcbsp[id].tx_dma_completion));
+
+ omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
+ OMAP_DMA_DATA_TYPE_S16,
+ length >> 1, 1,
+ OMAP_DMA_SYNC_ELEMENT);
+
+ omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
+ OMAP_DMA_PORT_TIPB,
+ OMAP_DMA_AMODE_CONSTANT,
+ mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1);
+
+ omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
+ OMAP_DMA_PORT_EMIFF,
+ OMAP_DMA_AMODE_POST_INC,
+ buffer);
+
+ omap_start_dma(mcbsp[id].dma_tx_lch);
+ wait_for_completion(&(mcbsp[id].tx_dma_completion));
+ return 0;
+}
+
+
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
+{
+ int dma_rx_ch;
+
+ if (omap_mcbsp_check(id) < 0)
+ return -EINVAL;
+
+ if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
+ &mcbsp[id],
+ &dma_rx_ch)) {
+ printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
+ return -EAGAIN;
+ }
+ mcbsp[id].dma_rx_lch = dma_rx_ch;
+
+ DBG("RX DMA on channel %d\n", dma_rx_ch);
+
+ init_completion(&(mcbsp[id].rx_dma_completion));
+
+ omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
+ OMAP_DMA_DATA_TYPE_S16,
+ length >> 1, 1,
+ OMAP_DMA_SYNC_ELEMENT);
+
+ omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
+ OMAP_DMA_PORT_TIPB,
+ OMAP_DMA_AMODE_CONSTANT,
+ mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1);
+
+ omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
+ OMAP_DMA_PORT_EMIFF,
+ OMAP_DMA_AMODE_POST_INC,
+ buffer);
+
+ omap_start_dma(mcbsp[id].dma_rx_lch);
+ wait_for_completion(&(mcbsp[id].rx_dma_completion));
+ return 0;
+}
+
+
+/*
+ * SPI wrapper.
+ * Since SPI setup is much simpler than the generic McBSP one,
+ * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
+ * Once this is done, you can call omap_mcbsp_start().
+ */
+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
+{
+ struct omap_mcbsp_reg_cfg mcbsp_cfg;
+
+ if (omap_mcbsp_check(id) < 0)
+ return;
+
+ memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
+
+ /* SPI has only one frame */
+ mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
+ mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
+
+ /* Clock stop mode */
+ if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
+ mcbsp_cfg.spcr1 |= (1 << 12);
+ else
+ mcbsp_cfg.spcr1 |= (3 << 11);
+
+ /* Set clock parities */
+ if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
+ mcbsp_cfg.pcr0 |= CLKRP;
+ else
+ mcbsp_cfg.pcr0 &= ~CLKRP;
+
+ if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
+ mcbsp_cfg.pcr0 &= ~CLKXP;
+ else
+ mcbsp_cfg.pcr0 |= CLKXP;
+
+ /* Set SCLKME to 0 and CLKSM to 1 */
+ mcbsp_cfg.pcr0 &= ~SCLKME;
+ mcbsp_cfg.srgr2 |= CLKSM;
+
+ /* Set FSXP */
+ if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
+ mcbsp_cfg.pcr0 &= ~FSXP;
+ else
+ mcbsp_cfg.pcr0 |= FSXP;
+
+ if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
+ mcbsp_cfg.pcr0 |= CLKXM;
+ mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
+ mcbsp_cfg.pcr0 |= FSXM;
+ mcbsp_cfg.srgr2 &= ~FSGM;
+ mcbsp_cfg.xcr2 |= XDATDLY(1);
+ mcbsp_cfg.rcr2 |= RDATDLY(1);
+ }
+ else {
+ mcbsp_cfg.pcr0 &= ~CLKXM;
+ mcbsp_cfg.srgr1 |= CLKGDV(1);
+ mcbsp_cfg.pcr0 &= ~FSXM;
+ mcbsp_cfg.xcr2 &= ~XDATDLY(3);
+ mcbsp_cfg.rcr2 &= ~RDATDLY(3);
+ }
+
+ mcbsp_cfg.xcr2 &= ~XPHASE;
+ mcbsp_cfg.rcr2 &= ~RPHASE;
+
+ omap_mcbsp_config(id, &mcbsp_cfg);
+}
+
+
+/*
+ * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
+ * 730 has only 2 McBSP, and both of them are MPU peripherals.
+ */
+struct omap_mcbsp_info {
+ u32 virt_base;
+ u8 dma_rx_sync, dma_tx_sync;
+ u16 rx_irq, tx_irq;
+};
+
+#ifdef CONFIG_ARCH_OMAP730
+static const struct omap_mcbsp_info mcbsp_730[] = {
+ [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+ .rx_irq = INT_730_McBSP1RX,
+ .tx_irq = INT_730_McBSP1TX },
+ [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+ .rx_irq = INT_730_McBSP2RX,
+ .tx_irq = INT_730_McBSP2TX },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+static const struct omap_mcbsp_info mcbsp_1510[] = {
+ [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+ .rx_irq = INT_McBSP1RX,
+ .tx_irq = INT_McBSP1TX },
+ [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+ .rx_irq = INT_1510_SPI_RX,
+ .tx_irq = INT_1510_SPI_TX },
+ [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+ .rx_irq = INT_McBSP3RX,
+ .tx_irq = INT_McBSP3TX },
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710)
+static const struct omap_mcbsp_info mcbsp_1610[] = {
+ [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+ .rx_irq = INT_McBSP1RX,
+ .tx_irq = INT_McBSP1TX },
+ [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
+ .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+ .rx_irq = INT_1610_McBSP2_RX,
+ .tx_irq = INT_1610_McBSP2_TX },
+ [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
+ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+ .rx_irq = INT_McBSP3RX,
+ .tx_irq = INT_McBSP3TX },
+};
+#endif
+
+static int __init omap_mcbsp_init(void)
+{
+ int mcbsp_count = 0, i;
+ static const struct omap_mcbsp_info *mcbsp_info;
+
+ printk("Initializing OMAP McBSP system\n");
+#ifdef CONFIG_ARCH_OMAP730
+ if (cpu_is_omap730()) {
+ mcbsp_info = mcbsp_730;
+ mcbsp_count = ARRAY_SIZE(mcbsp_730);
+ }
+#endif
+#ifdef CONFIG_ARCH_OMAP1510
+ if (cpu_is_omap1510()) {
+ mcbsp_info = mcbsp_1510;
+ mcbsp_count = ARRAY_SIZE(mcbsp_1510);
+ }
+#endif
+#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710)
+ if (cpu_is_omap1610() || cpu_is_omap1710()) {
+ mcbsp_info = mcbsp_1610;
+ mcbsp_count = ARRAY_SIZE(mcbsp_1610);
+ }
+#endif
+ for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
+ if (i >= mcbsp_count) {
+ mcbsp[i].io_base = 0;
+ mcbsp[i].free = 0;
+ continue;
+ }
+ mcbsp[i].id = i + 1;
+ mcbsp[i].free = 1;
+ mcbsp[i].dma_tx_lch = -1;
+ mcbsp[i].dma_rx_lch = -1;
+
+ mcbsp[i].io_base = mcbsp_info[i].virt_base;
+ mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
+ mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
+ mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
+ mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
+ spin_lock_init(&mcbsp[i].lock);
+ }
+
+ return 0;
+}
+
+
+arch_initcall(omap_mcbsp_init);
+
+EXPORT_SYMBOL(omap_mcbsp_config);
+EXPORT_SYMBOL(omap_mcbsp_request);
+EXPORT_SYMBOL(omap_mcbsp_free);
+EXPORT_SYMBOL(omap_mcbsp_start);
+EXPORT_SYMBOL(omap_mcbsp_stop);
+EXPORT_SYMBOL(omap_mcbsp_xmit_word);
+EXPORT_SYMBOL(omap_mcbsp_recv_word);
+EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
+EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
+EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
--- /dev/null
+/*
+ * arch/arm/mach-omap/usb.c -- platform level USB initialization
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/usb_otg.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/board.h>
+
+/* These routines should handle the standard chip-specific modes
+ * for usb0/1/2 ports, covering basic mux and transceiver setup.
+ * Call omap_usb_init() once, from INIT_MACHINE().
+ *
+ * Some board-*.c files will need to set up additional mux options,
+ * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
+ */
+
+/* TESTED ON:
+ * - 1611B H2 (with usb1 mini-AB)
+ * - 1510 Innovator with built-in transceiver (custom cable feeding 5V VBUS)
+ * - 1710 custom development board using alternate pin group
+ */
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ARCH_OMAP_OTG
+
+static struct otg_transceiver *xceiv;
+
+/**
+ * otg_get_transceiver - find the (single) OTG transceiver driver
+ *
+ * Returns the transceiver driver, after getting a refcount to it; or
+ * null if there is no such transceiver. The caller is responsible for
+ * releasing that count.
+ */
+struct otg_transceiver *otg_get_transceiver(void)
+{
+ if (xceiv)
+ get_device(xceiv->dev);
+ return xceiv;
+}
+EXPORT_SYMBOL(otg_get_transceiver);
+
+int otg_set_transceiver(struct otg_transceiver *x)
+{
+ if (xceiv && x)
+ return -EBUSY;
+ xceiv = x;
+ return 0;
+}
+EXPORT_SYMBOL(otg_set_transceiver);
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
+{
+ u32 syscon1 = 0;
+
+ if (nwires == 0) {
+ USB_TRANSCEIVER_CTRL_REG &= ~(1 << 3);
+ return 0;
+ }
+
+ /*
+ * VP and VM are needed for all active usb0 configurations.
+ * USB0_VP and USB0_VM are always set on 1510, there's no muxing
+ * available for them.
+ */
+ if (nwires >= 2 && !cpu_is_omap1510()) {
+ omap_cfg_reg(AA9_USB0_VP);
+ omap_cfg_reg(R9_USB0_VM);
+ }
+
+ /* internal transceiver */
+ if (nwires == 2) {
+ if (cpu_is_omap1510()) {
+ /* This works for OHCI on 1510-Innovator, nothing to mux */
+ return 0;
+ }
+
+#if 0
+ /* NOTE: host OR device mode for now, no OTG */
+ USB_TRANSCEIVER_CTRL_REG &= ~(3 << 4);
+ if (is_device) {
+ omap_cfg_reg(W4_USB_PUEN);
+ omap_cfg_reg(R18_1510_USB_GPIO0);
+ // omap_cfg_reg(USB0_VBUS);
+ // omap_cfg_reg(USB0_PUEN);
+ // USB_TRANSCEIVER_CTRL_REG.CONF_USB0_PORT_R = 7
+ // when USB0_PUEN is needed
+ } else /* host mode needs D+ and D- pulldowns */
+ USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
+ return 3 << 16;
+#else
+ /* FIXME: 1610 needs to return the right value here */
+ printk(KERN_ERR "usb0 internal transceiver, nyet\n");
+ return 0;
+#endif
+ }
+
+ /* alternate pin config, external transceiver */
+ omap_cfg_reg(V6_USB0_TXD);
+ omap_cfg_reg(W9_USB0_TXEN);
+ omap_cfg_reg(W5_USB0_SE0);
+
+#ifdef CONFIG_ARCH_OMAP_USB_SPEED
+ /* FIXME: there's good chance that pin V9 is used for MMC2 port cmddir */
+ omap_cfg_reg(V9_USB0_SPEED);
+ // omap_cfg_reg(V9_USB0_SUSP);
+#endif
+
+ if (nwires != 3)
+ omap_cfg_reg(Y5_USB0_RCV);
+
+ switch (nwires) {
+ case 3:
+ syscon1 = 2;
+ break;
+ case 4:
+ syscon1 = 1;
+ break;
+ case 6:
+ syscon1 = 3;
+ /* REVISIT: Is CONF_USB2_UNI_R only needed when nwires = 6? */
+ USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+ break;
+ default:
+ printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+ 0, nwires);
+ }
+ return syscon1 << 16;
+}
+
+static u32 __init omap_usb1_init(unsigned nwires)
+{
+ u32 syscon1 = 0;
+
+ if (nwires != 6)
+ USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
+ if (nwires == 0)
+ return 0;
+
+ /* external transceiver */
+ omap_cfg_reg(USB1_TXD);
+ omap_cfg_reg(USB1_TXEN);
+ if (cpu_is_omap1510()) {
+ omap_cfg_reg(USB1_SEO);
+ omap_cfg_reg(USB1_SPEED);
+ // SUSP
+ } else if (cpu_is_omap1610() || cpu_is_omap5912() || cpu_is_omap1710()) {
+ omap_cfg_reg(W13_1610_USB1_SE0);
+ omap_cfg_reg(R13_1610_USB1_SPEED);
+ // SUSP
+ } else {
+ pr_debug("usb unrecognized\n");
+ }
+ if (nwires != 3)
+ omap_cfg_reg(USB1_RCV);
+
+ switch (nwires) {
+ case 3:
+ syscon1 = 2;
+ break;
+ case 4:
+ syscon1 = 1;
+ break;
+ case 6:
+ syscon1 = 3;
+ omap_cfg_reg(USB1_VP);
+ omap_cfg_reg(USB1_VM);
+ USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
+ break;
+ default:
+ printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+ 1, nwires);
+ }
+ return syscon1 << 20;
+}
+
+static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+ u32 syscon1 = 0;
+
+ if (alt_pingroup)
+ return 0;
+ if (nwires != 6)
+ USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+ if (nwires == 0)
+ return 0;
+
+ /* external transceiver */
+ if (cpu_is_omap1510()) {
+ omap_cfg_reg(USB2_TXD);
+ omap_cfg_reg(USB2_TXEN);
+ omap_cfg_reg(USB2_SEO);
+ if (nwires != 3)
+ omap_cfg_reg(USB2_RCV);
+ } else if (cpu_is_omap1610() || cpu_is_omap5912() || cpu_is_omap1710()) {
+ omap_cfg_reg(V6_USB2_TXD);
+ omap_cfg_reg(W9_USB2_TXEN);
+ omap_cfg_reg(W5_USB2_SE0);
+ if (nwires != 3)
+ omap_cfg_reg(Y5_USB2_RCV);
+ } else {
+ pr_debug("usb unrecognized\n");
+ }
+ // omap_cfg_reg(USB2_SUSP);
+ // FIXME omap_cfg_reg(USB2_SPEED);
+
+ switch (nwires) {
+ case 3:
+ syscon1 = 2;
+ break;
+ case 4:
+ syscon1 = 1;
+ break;
+ case 6:
+ syscon1 = 3;
+ if (cpu_is_omap1510()) {
+ omap_cfg_reg(USB2_VP);
+ omap_cfg_reg(USB2_VM);
+ } else {
+ omap_cfg_reg(AA9_USB2_VP);
+ omap_cfg_reg(R9_USB2_VM);
+ }
+ USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+ break;
+ default:
+ printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+ 2, nwires);
+ }
+ return syscon1 << 24;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#if defined(CONFIG_USB_GADGET_OMAP) || \
+ defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) || \
+ (defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG))
+static void usb_release(struct device *dev)
+{
+ /* normally not freed */
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_OMAP
+
+static struct resource udc_resources[] = {
+ /* order is significant! */
+ { /* registers */
+ .start = IO_ADDRESS(UDC_BASE),
+ .end = IO_ADDRESS(UDC_BASE + 0xff),
+ .flags = IORESOURCE_MEM,
+ }, { /* general IRQ */
+ .start = IH2_BASE + 20,
+ .flags = IORESOURCE_IRQ,
+ }, { /* PIO IRQ */
+ .start = IH2_BASE + 30,
+ .flags = IORESOURCE_IRQ,
+ }, { /* SOF IRQ */
+ .start = IH2_BASE + 29,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 udc_dmamask = ~(u32)0;
+
+static struct platform_device udc_device = {
+ .name = "omap_udc",
+ .id = -1,
+ .dev = {
+ .release = usb_release,
+ .dma_mask = &udc_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(udc_resources),
+ .resource = udc_resources,
+};
+
+#endif
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct resource ohci_resources[] = {
+ {
+ .start = IO_ADDRESS(OMAP_OHCI_BASE),
+ .end = IO_ADDRESS(OMAP_OHCI_BASE + 4096),
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_USB_HHC_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device ohci_device = {
+ .name = "ohci",
+ .id = -1,
+ .dev = {
+ .release = usb_release,
+ .dma_mask = &ohci_dmamask,
+ .coherent_dma_mask = 0x0fffffff,
+ },
+ .num_resources = ARRAY_SIZE(ohci_resources),
+ .resource = ohci_resources,
+};
+
+#endif
+
+#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
+
+static struct resource otg_resources[] = {
+ /* order is significant! */
+ {
+ .start = IO_ADDRESS(OTG_BASE),
+ .end = IO_ADDRESS(OTG_BASE + 0xff),
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IH2_BASE + 8,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device otg_device = {
+ .name = "omap_otg",
+ .id = -1,
+ .dev = {
+ .release = usb_release,
+ },
+ .num_resources = ARRAY_SIZE(otg_resources),
+ .resource = otg_resources,
+};
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+// FIXME correct answer depends on hmc_mode,
+// as does any nonzero value for config->otg port number
+#define is_usb0_device(config) 0
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ARCH_OMAP_OTG
+
+void __init
+omap_otg_init(struct omap_usb_config *config)
+{
+ u32 syscon = OTG_SYSCON_1_REG & 0xffff;
+ int status;
+ int alt_pingroup = 0;
+
+ /* NOTE: no bus or clock setup (yet?) */
+
+ syscon = OTG_SYSCON_1_REG & 0xffff;
+ if (!(syscon & OTG_RESET_DONE))
+ pr_debug("USB resets not complete?\n");
+
+ // OTG_IRQ_EN_REG = 0;
+
+ /* pin muxing and transceiver pinouts */
+ if (config->pins[0] > 2) /* alt pingroup 2 */
+ alt_pingroup = 1;
+ syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
+ syscon |= omap_usb1_init(config->pins[1]);
+ syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
+ pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
+ OTG_SYSCON_1_REG = syscon;
+
+ syscon = config->hmc_mode;
+ syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
+ if (config->otg || config->register_host)
+ syscon |= UHOST_EN;
+#ifdef CONFIG_USB_OTG
+ if (config->otg)
+ syscon |= OTG_EN;
+#endif
+ pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
+ OTG_SYSCON_2_REG = syscon;
+
+ printk("USB: hmc %d", config->hmc_mode);
+ if (alt_pingroup)
+ printk(", usb2 alt %d wires", config->pins[2]);
+ else if (config->pins[0])
+ printk(", usb0 %d wires%s", config->pins[2],
+ is_usb0_device(config) ? " (dev)" : "");
+ if (config->pins[1])
+ printk(", usb1 %d wires", config->pins[1]);
+ if (!alt_pingroup && config->pins[2])
+ printk(", usb2 %d wires", config->pins[2]);
+ if (config->otg)
+ printk(", Mini-AB on usb%d", config->otg - 1);
+ printk("\n");
+
+ /* don't clock unused USB controllers */
+ syscon = OTG_SYSCON_1_REG;
+ syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
+
+#ifdef CONFIG_USB_GADGET_OMAP
+ if (config->otg || config->register_dev) {
+ syscon &= ~DEV_IDLE_EN;
+ udc_device.dev.platform_data = config;
+ status = platform_device_register(&udc_device);
+ if (status)
+ pr_debug("can't register UDC device, %d\n", status);
+ }
+#endif
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+ if (config->otg || config->register_host) {
+ syscon &= ~HST_IDLE_EN;
+ ohci_device.dev.platform_data = config;
+ status = platform_device_register(&ohci_device);
+ if (status)
+ pr_debug("can't register OHCI device, %d\n", status);
+ }
+#endif
+
+#ifdef CONFIG_USB_OTG
+ if (config->otg) {
+ syscon &= ~OTG_IDLE_EN;
+ if (cpu_is_omap730())
+ otg_resources[1].start = INT_730_USB_OTG;
+ status = platform_device_register(&otg_device);
+ // ...
+ }
+#endif
+ pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
+ OTG_SYSCON_1_REG = syscon;
+
+ status = 0;
+}
+
+#else
+static inline void omap_otg_init(struct omap_usb_config *config) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ARCH_OMAP1510
+
+static void __init omap_1510_usb_init(struct omap_usb_config *config)
+{
+ int status;
+ unsigned int val;
+
+ omap_usb0_init(config->pins[0], is_usb0_device(config));
+ omap_usb1_init(config->pins[1]);
+ omap_usb2_init(config->pins[2], 0);
+
+ val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
+ val |= (config->hmc_mode << 1);
+ omap_writel(val, MOD_CONF_CTRL_0);
+
+ // FIXME this has a UDC controller too
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+ if (config->otg || config->register_host) {
+ ohci_device.dev.platform_data = config;
+ status = platform_device_register(&ohci_device);
+ if (status)
+ pr_debug("can't register OHCI device, %d\n", status);
+ }
+ // FIXME completely untested ...
+#endif
+
+}
+
+#else
+static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+static struct omap_usb_config platform_data;
+
+static int __init
+omap_usb_init(void)
+{
+ const struct omap_usb_config *config;
+
+ config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config);
+ if (config == NULL) {
+ printk(KERN_ERR "USB: No board-specific platform config found\n");
+ return -ENODEV;
+ }
+ platform_data = *config;
+
+ if (cpu_is_omap730()
+ || cpu_is_omap1610()
+ || cpu_is_omap1710()
+ || cpu_is_omap5912())
+ omap_otg_init(&platform_data);
+ else if (cpu_is_omap1510())
+ omap_1510_usb_init(&platform_data);
+ else {
+ printk(KERN_ERR "USB: No init for your chip yet\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+subsys_initcall(omap_usb_init);
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/clock.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 Clock control support
+ *
+ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
+ **
+ ** Copyright (C) 2004 ARM Limited.
+ ** Written by Deep Blue Solutions Limited.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/hardware.h>
+#include <asm/atomic.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/hardware/clock.h>
+#include <asm/arch/regs-clock.h>
+
+#include "clock.h"
+
+
+static LIST_HEAD(clocks);
+static DECLARE_MUTEX(clocks_sem);
+
+
+/* old functions */
+
+void s3c2410_clk_enable(unsigned int clocks, unsigned int enable)
+{
+ unsigned long clkcon;
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ clkcon = __raw_readl(S3C2410_CLKCON);
+ clkcon &= ~clocks;
+
+ if (enable)
+ clkcon |= clocks;
+
+ __raw_writel(clkcon, S3C2410_CLKCON);
+
+ local_irq_restore(flags);
+}
+
+
+/* Clock API calls */
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ struct clk *p;
+ struct clk *clk = ERR_PTR(-ENOENT);
+
+ down(&clocks_sem);
+ list_for_each_entry(p, &clocks, list) {
+ if (strcmp(id, p->name) == 0 &&
+ try_module_get(p->owner)) {
+ clk = p;
+ break;
+ }
+ }
+ up(&clocks_sem);
+
+ return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+ module_put(clk->owner);
+}
+
+int clk_enable(struct clk *clk)
+{
+ if (clk->ctrlbit != 0)
+ s3c2410_clk_enable(clk->ctrlbit, 1);
+
+ return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+ s3c2410_clk_enable(clk->ctrlbit, 0);
+}
+
+
+int clk_use(struct clk *clk)
+{
+ atomic_inc(&clk->used);
+ return 0;
+}
+
+
+void clk_unuse(struct clk *clk)
+{
+ atomic_dec(&clk->used);
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ if (clk->parent != NULL)
+ return clk->parent->rate;
+
+ return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ return rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ return -EINVAL;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ return clk->parent;
+}
+
+EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_use);
+EXPORT_SYMBOL(clk_unuse);
+EXPORT_SYMBOL(clk_get_rate);
+EXPORT_SYMBOL(clk_round_rate);
+EXPORT_SYMBOL(clk_set_rate);
+EXPORT_SYMBOL(clk_get_parent);
+
+/* base clocks */
+
+static struct clk clk_f = {
+ .name = "fclk",
+ .rate = 0,
+ .parent = NULL,
+ .ctrlbit = 0
+};
+
+static struct clk clk_h = {
+ .name = "hclk",
+ .rate = 0,
+ .parent = NULL,
+ .ctrlbit = 0
+};
+
+static struct clk clk_p = {
+ .name = "pclk",
+ .rate = 0,
+ .parent = NULL,
+ .ctrlbit = 0
+};
+
+/* clock definitions */
+
+static struct clk init_clocks[] = {
+ { .name = "nand",
+ .parent = &clk_h,
+ .ctrlbit = S3C2410_CLKCON_NAND
+ },
+ { .name = "lcd",
+ .parent = &clk_h,
+ .ctrlbit = S3C2410_CLKCON_LCDC
+ },
+ { .name = "usb-host",
+ .parent = &clk_h,
+ .ctrlbit = S3C2410_CLKCON_USBH
+ },
+ { .name = "usb-device",
+ .parent = &clk_h,
+ .ctrlbit = S3C2410_CLKCON_USBD
+ },
+ { .name = "timers",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_PWMT
+ },
+ { .name = "sdi",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_SDI
+ },
+ { .name = "uart0",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_UART0
+ },
+ { .name = "uart1",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_UART1
+ },
+ { .name = "uart2",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_UART2
+ },
+ { .name = "gpio",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_GPIO
+ },
+ { .name = "rtc",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_RTC
+ },
+ { .name = "adc",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_ADC
+ },
+ { .name = "i2c",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_IIC
+ },
+ { .name = "iis",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_IIS
+ },
+ { .name = "spi",
+ .parent = &clk_p,
+ .ctrlbit = S3C2410_CLKCON_SPI
+ },
+ { .name = "watchdog",
+ .parent = &clk_p,
+ .ctrlbit = 0
+ }
+};
+
+/* initialise the clock system */
+
+int s3c2410_register_clock(struct clk *clk)
+{
+ clk->owner = THIS_MODULE;
+ atomic_set(&clk->used, 0);
+
+ /* add to the list of available clocks */
+
+ down(&clocks_sem);
+ list_add(&clk->list, &clocks);
+ up(&clocks_sem);
+
+ return 0;
+}
+
+/* initalise all the clocks */
+
+static int __init s3c2410_init_clocks(void)
+{
+ struct clk *clkp = init_clocks;
+ int ptr;
+ int ret;
+
+ printk(KERN_INFO "S3C2410 Clock control, (c) 2004 Simtec Electronics\n");
+
+ /* initialise the main system clocks */
+
+ clk_h.rate = s3c2410_hclk;
+ clk_p.rate = s3c2410_pclk;
+ clk_f.rate = s3c2410_fclk;
+
+ /* set the enabled clocks to a minimal (known) state */
+ __raw_writel(S3C2410_CLKCON_PWMT | S3C2410_CLKCON_UART0 | S3C2410_CLKCON_UART1 | S3C2410_CLKCON_UART2 | S3C2410_CLKCON_GPIO | S3C2410_CLKCON_RTC, S3C2410_CLKCON);
+
+ /* register our clocks */
+
+ if (s3c2410_register_clock(&clk_f) < 0)
+ printk(KERN_ERR "failed to register cpu fclk\n");
+
+ if (s3c2410_register_clock(&clk_h) < 0)
+ printk(KERN_ERR "failed to register cpu hclk\n");
+
+ if (s3c2410_register_clock(&clk_p) < 0)
+ printk(KERN_ERR "failed to register cpu pclk\n");
+
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+ ret = s3c2410_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+
+ return 0;
+}
+
+arch_initcall(s3c2410_init_clocks);
+
--- /dev/null
+/*
+ * linux/arch/arm/mach-s3c2410/clock.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct clk {
+ struct list_head list;
+ struct module *owner;
+ struct clk *parent;
+ const char *name;
+ atomic_t used;
+ unsigned long rate;
+ unsigned long ctrlbit;
+};
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/cpu.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/regs-gpio.h>
+
+#include "cpu.h"
+#include "s3c2410.h"
+#include "s3c2440.h"
+
+struct cpu_table {
+ unsigned long idcode;
+ unsigned long idmask;
+ void (*map_io)(struct map_desc *mach_desc, int size);
+ int (*init)(void);
+ const char *name;
+};
+
+/* table of supported CPUs */
+
+static const char name_s3c2410[] = "S3C2410";
+static const char name_s3c2440[] = "S3C2440";
+static const char name_s3c2410a[] = "S3C2410A";
+static const char name_s3c2440a[] = "S3C2440A";
+
+static struct cpu_table cpu_ids[] __initdata = {
+ {
+ .idcode = 0x32410000,
+ .idmask = 0xffffffff,
+ .map_io = s3c2410_map_io,
+ .init = s3c2410_init,
+ .name = name_s3c2410
+ },
+ {
+ .idcode = 0x3241002,
+ .idmask = 0xffffffff,
+ .map_io = s3c2410_map_io,
+ .init = s3c2410_init,
+ .name = name_s3c2410a
+ },
+ {
+ .idcode = 0x32440000,
+ .idmask = 0xffffffff,
+ .map_io = s3c2440_map_io,
+ .init = s3c2440_init,
+ .name = name_s3c2440
+ },
+ {
+ .idcode = 0x32440001,
+ .idmask = 0xffffffff,
+ .map_io = s3c2440_map_io,
+ .init = s3c2440_init,
+ .name = name_s3c2440a
+ }
+};
+
+/* minimal IO mapping */
+
+static struct map_desc s3c_iodesc[] __initdata = {
+ IODESC_ENT(GPIO),
+ IODESC_ENT(IRQ),
+ IODESC_ENT(MEMCTRL),
+ IODESC_ENT(UART)
+};
+
+
+static struct cpu_table *
+s3c_lookup_cpu(unsigned long idcode)
+{
+ struct cpu_table *tab;
+ int count;
+
+ tab = cpu_ids;
+ for (count = 0; count < ARRAY_SIZE(cpu_ids); count++) {
+ if ((idcode & tab->idmask) == tab->idcode)
+ return tab;
+ }
+
+ return NULL;
+}
+
+static struct cpu_table *cpu;
+
+void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
+{
+ unsigned long idcode;
+
+ /* initialise the io descriptors we need for initialisation */
+ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
+
+ idcode = __raw_readl(S3C2410_GSTATUS1);
+ cpu = s3c_lookup_cpu(idcode);
+
+ if (cpu == NULL) {
+ printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
+ panic("Unknown S3C24XX CPU");
+ }
+
+ if (cpu->map_io == NULL || cpu->init == NULL) {
+ printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
+ panic("Unsupported S3C24XX CPU");
+ }
+
+ printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
+
+ (cpu->map_io)(mach_desc, size);
+}
+
+static int __init s3c_arch_init(void)
+{
+ // do the correct init for cpu
+
+ if (cpu == NULL)
+ panic("s3c_arch_init: NULL cpu\n");
+
+ return (cpu->init)();
+}
+
+arch_initcall(s3c_arch_init);
--- /dev/null
+/* arch/arm/mach-s3c2410/cpu.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for S3C24XX CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 24-Aug-2004 BJD Start of generic S3C24XX support
+*/
+
+#define IODESC_ENT(x) { S3C2410_VA_##x, S3C2410_PA_##x, S3C2410_SZ_##x, MT_DEVICE }
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
+
+#ifdef CONFIG_CPU_S3C2410
+extern int s3c2410_init(void);
+extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
+#else
+#define s3c2410_map_io NULL
+#define s3c2410_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+extern int s3c2440_init(void);
+extern void s3c2440_map_io(struct map_desc *mach_desc, int size);
+#else
+#define s3c2440_map_io NULL
+#define s3c2440_init NULL
+#endif
+
+extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
+
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/devs.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Base S3C2410 platform device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 29-Aug-2004 BJD Added timers 0 through 3
+ * 29-Aug-2004 BJD Changed index of devices we only have one of to -1
+ * 21-Aug-2004 BJD Added IRQ_TICK to RTC resources
+ * 18-Aug-2004 BJD Created initial version
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "devs.h"
+
+/* USB Host Controller */
+
+static struct resource s3c_usb_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_USBHOST,
+ .end = S3C2410_PA_USBHOST + S3C2410_SZ_USBHOST,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBH,
+ .end = IRQ_USBH,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 s3c_device_usb_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_usb = {
+ .name = "s3c2410-ohci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_usb_resource),
+ .resource = s3c_usb_resource,
+ .dev = {
+ .dma_mask = &s3c_device_usb_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
+};
+
+EXPORT_SYMBOL(s3c_device_usb);
+
+/* LCD Controller */
+
+static struct resource s3c_lcd_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_LCD,
+ .end = S3C2410_PA_LCD + S3C2410_SZ_LCD,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_LCD,
+ .end = IRQ_LCD,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_lcd = {
+ .name = "s3c2410-lcd",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_lcd_resource),
+ .resource = s3c_lcd_resource,
+ .dev = {
+ .dma_mask = &s3c_device_lcd_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
+};
+
+EXPORT_SYMBOL(s3c_device_lcd);
+
+/* NAND Controller */
+
+static struct resource s3c_nand_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_NAND,
+ .end = S3C2410_PA_NAND + S3C2410_SZ_NAND,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+struct platform_device s3c_device_nand = {
+ .name = "s3c2410-nand",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_nand_resource),
+ .resource = s3c_nand_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_nand);
+
+/* USB Device (Gadget)*/
+
+static struct resource s3c_usbgadget_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_USBDEV,
+ .end = S3C2410_PA_USBDEV + S3C2410_SZ_USBDEV,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBD,
+ .end = IRQ_USBD,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_usbgadget = {
+ .name = "s3c2410-usbgadget",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
+ .resource = s3c_usbgadget_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_usbgadget);
+
+/* Watchdog */
+
+static struct resource s3c_wdt_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_WATCHDOG,
+ .end = S3C2410_PA_WATCHDOG + S3C2410_SZ_WATCHDOG,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_WDT,
+ .end = IRQ_WDT,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_wdt = {
+ .name = "s3c2410-wdt",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_wdt_resource),
+ .resource = s3c_wdt_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_wdt);
+
+/* I2C */
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_IIC,
+ .end = S3C2410_PA_IIC + S3C2410_SZ_IIC,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC,
+ .end = IRQ_IIC,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_i2c = {
+ .name = "s3c2410-i2c",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_i2c);
+
+/* IIS */
+
+static struct resource s3c_iis_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_IIS,
+ .end = S3C2410_PA_IIS + S3C2410_SZ_IIS,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static u64 s3c_device_iis_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_iis = {
+ .name = "s3c2410-iis",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_iis_resource),
+ .resource = s3c_iis_resource,
+ .dev = {
+ .dma_mask = &s3c_device_iis_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
+};
+
+EXPORT_SYMBOL(s3c_device_iis);
+
+/* RTC */
+
+static struct resource s3c_rtc_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_RTC,
+ .end = S3C2410_PA_RTC + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_RTC,
+ .end = IRQ_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_TICK,
+ .end = IRQ_TICK,
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+struct platform_device s3c_device_rtc = {
+ .name = "s3c2410-rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_rtc_resource),
+ .resource = s3c_rtc_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_rtc);
+
+/* ADC */
+
+static struct resource s3c_adc_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_ADC,
+ .end = S3C2410_PA_ADC + S3C2410_SZ_ADC,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TC,
+ .end = IRQ_ADC,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_adc = {
+ .name = "s3c2410-adc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_adc_resource),
+ .resource = s3c_adc_resource,
+};
+
+/* SDI */
+
+static struct resource s3c_sdi_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_SDI,
+ .end = S3C2410_PA_SDI + S3C2410_SZ_SDI,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SDI,
+ .end = IRQ_SDI,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_sdi = {
+ .name = "s3c2410-sdi",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_sdi_resource),
+ .resource = s3c_sdi_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_sdi);
+
+/* SPI (0) */
+
+static struct resource s3c_spi0_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_SPI,
+ .end = S3C2410_PA_SPI + 0x1f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SPI0,
+ .end = IRQ_SPI0,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_spi0 = {
+ .name = "s3c2410-spi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(s3c_spi0_resource),
+ .resource = s3c_spi0_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_spi0);
+
+/* SPI (1) */
+
+static struct resource s3c_spi1_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_SPI + 0x20,
+ .end = S3C2410_PA_SPI + 0x20 + 0x1f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SPI1,
+ .end = IRQ_SPI1,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_spi1 = {
+ .name = "s3c2410-spi",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_spi1_resource),
+ .resource = s3c_spi1_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_spi1);
+
+/* pwm timer blocks */
+
+static struct resource s3c_timer0_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_TIMER + 0x0C,
+ .end = S3C2410_PA_TIMER + 0x0C + 0xB,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TIMER0,
+ .end = IRQ_TIMER0,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_timer0 = {
+ .name = "s3c2410-timer",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(s3c_timer0_resource),
+ .resource = s3c_timer0_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_timer0);
+
+/* timer 1 */
+
+static struct resource s3c_timer1_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_TIMER + 0x18,
+ .end = S3C2410_PA_TIMER + 0x23,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TIMER1,
+ .end = IRQ_TIMER1,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_timer1 = {
+ .name = "s3c2410-timer",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_timer1_resource),
+ .resource = s3c_timer1_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_timer1);
+
+/* timer 2 */
+
+static struct resource s3c_timer2_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_TIMER + 0x24,
+ .end = S3C2410_PA_TIMER + 0x2F,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TIMER2,
+ .end = IRQ_TIMER2,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_timer2 = {
+ .name = "s3c2410-timer",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(s3c_timer2_resource),
+ .resource = s3c_timer2_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_timer2);
+
+/* timer 3 */
+
+static struct resource s3c_timer3_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_TIMER + 0x30,
+ .end = S3C2410_PA_TIMER + 0x3B,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TIMER3,
+ .end = IRQ_TIMER3,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+struct platform_device s3c_device_timer3 = {
+ .name = "s3c2410-timer",
+ .id = 3,
+ .num_resources = ARRAY_SIZE(s3c_timer3_resource),
+ .resource = s3c_timer3_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_timer3);
--- /dev/null
+/* arch/arm/mach-s3c2410/devs.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for s3c2410 standard platform devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 18-Aug-2004 BJD Created initial version
+ * 27-Aug-2004 BJD Added timers 0 through 3
+*/
+
+extern struct platform_device s3c_device_usb;
+extern struct platform_device s3c_device_lcd;
+extern struct platform_device s3c_device_wdt;
+extern struct platform_device s3c_device_i2c;
+extern struct platform_device s3c_device_iis;
+extern struct platform_device s3c_device_rtc;
+extern struct platform_device s3c_device_adc;
+extern struct platform_device s3c_device_sdi;
+
+extern struct platform_device s3c_device_spi0;
+extern struct platform_device s3c_device_spi1;
+
+extern struct platform_device s3c_device_nand;
+
+extern struct platform_device s3c_device_timer0;
+extern struct platform_device s3c_device_timer1;
+extern struct platform_device s3c_device_timer2;
+extern struct platform_device s3c_device_timer3;
+
+extern struct platform_device s3c_device_usbgadget;
--- /dev/null
+/* linux/arch/arm/mach-bast/dma.c
+ *
+ * (c) 2003,2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 DMA core
+ *
+ * http://www.simtec.co.uk/products/EB2410ITX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ * 08-Aug-2004 BJD Apply rmk's suggestions
+ * 21-Jul-2004 BJD Ported to linux 2.6
+ * 12-Jul-2004 BJD Finished re-write and change of API
+ * 06-Jul-2004 BJD Rewrote dma code to try and cope with various problems
+ * 23-May-2003 BJD Created file
+ * 19-Aug-2003 BJD Cleanup, header fix, added URL
+ *
+ * This file is based on the Sangwook Lee/Samsung patches, re-written due
+ * to various ommisions from the code (such as flexible dma configuration)
+ * for use with the BAST system board.
+ *
+ * The re-write is pretty much complete, and should be good enough for any
+ * possible DMA function
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_S3C2410_DMA_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+
+#include <asm/mach/dma.h>
+#include <asm/arch/map.h>
+
+/* io map for dma */
+static void *dma_base;
+
+/* dma channel state information */
+s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];
+
+/* debugging functions */
+
+#define BUF_MAGIC (0xcafebabe)
+
+#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
+
+#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
+
+#if 1
+#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
+#else
+static inline void
+dma_wrreg(s3c2410_dma_chan_t *chan, int reg, unsigned long val)
+{
+ pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
+ writel(val, dma_regaddr(chan, reg));
+}
+
+#endif
+
+#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
+
+/* captured register state for debug */
+
+struct s3c2410_dma_regstate {
+ unsigned long dcsrc;
+ unsigned long disrc;
+ unsigned long dstat;
+ unsigned long dcon;
+ unsigned long dmsktrig;
+};
+
+#ifdef CONFIG_S3C2410_DMA_DEBUG
+
+/* dmadbg_showregs
+ *
+ * simple debug routine to print the current state of the dma registers
+*/
+
+static void
+dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs)
+{
+ regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
+ regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
+ regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
+ regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
+ regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+}
+
+static void
+dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan,
+ struct s3c2410_dma_regstate *regs)
+{
+ printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
+ chan->number, fname, line,
+ regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
+ regs->dcon);
+}
+
+static void
+dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan)
+{
+ struct s3c2410_dma_regstate state;
+
+ dmadbg_capture(chan, &state);
+
+ printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
+ chan->number, fname, line, chan->load_state,
+ chan->curr, chan->next, chan->end);
+
+ dmadbg_showregs(fname, line, chan, &state);
+}
+
+#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
+#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
+#else
+#define dbg_showregs(chan) do { } while(0)
+#define dbg_showchan(chan) do { } while(0)
+#endif /* CONFIG_S3C2410_DMA_DEBUG */
+
+#define check_channel(chan) \
+ do { if ((chan) >= S3C2410_DMA_CHANNELS) { \
+ printk(KERN_ERR "%s: invalid channel %d\n", __FUNCTION__, (chan)); \
+ return -EINVAL; \
+ } } while(0)
+
+
+/* s3c2410_dma_stats_timeout
+ *
+ * Update DMA stats from timeout info
+*/
+
+static void
+s3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val)
+{
+ if (stats == NULL)
+ return;
+
+ if (val > stats->timeout_longest)
+ stats->timeout_longest = val;
+ if (val < stats->timeout_shortest)
+ stats->timeout_shortest = val;
+
+ stats->timeout_avg += val;
+}
+
+/* s3c2410_dma_waitforload
+ *
+ * wait for the DMA engine to load a buffer, and update the state accordingly
+*/
+
+static int
+s3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line)
+{
+ int timeout = chan->load_timeout;
+ int took;
+
+ if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
+ printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
+ return 0;
+ }
+
+ if (chan->stats != NULL)
+ chan->stats->loads++;
+
+ while (--timeout > 0) {
+ if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
+ took = chan->load_timeout - timeout;
+
+ s3c2410_dma_stats_timeout(chan->stats, took);
+
+ switch (chan->load_state) {
+ case S3C2410_DMALOAD_1LOADED:
+ chan->load_state = S3C2410_DMALOAD_1RUNNING;
+ break;
+
+ default:
+ printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
+ }
+
+ return 1;
+ }
+ }
+
+ if (chan->stats != NULL) {
+ chan->stats->timeout_failed++;
+ }
+
+ return 0;
+}
+
+
+
+/* s3c2410_dma_loadbuffer
+ *
+ * load a buffer, and update the channel state
+*/
+
+static inline int
+s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan,
+ s3c2410_dma_buf_t *buf)
+{
+ unsigned long reload;
+
+ pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
+ buf, (unsigned long)buf->data, buf->size);
+
+ if (buf == NULL) {
+ dmawarn("buffer is NULL\n");
+ return -EINVAL;
+ }
+
+ /* check the state of the channel before we do anything */
+
+ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
+ dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
+ }
+
+ if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
+ dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
+ }
+
+ /* it would seem sensible if we are the last buffer to not bother
+ * with the auto-reload bit, so that the DMA engine will not try
+ * and load another transfer after this one has finished...
+ */
+ if (chan->load_state == S3C2410_DMALOAD_NONE) {
+ pr_debug("load_state is none, checking for noreload (next=%p)\n",
+ buf->next);
+ reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
+ } else {
+ pr_debug("load_state is %d => autoreload\n", chan->load_state);
+ reload = S3C2410_DCON_AUTORELOAD;
+ }
+
+ writel(buf->data, chan->addr_reg);
+
+ dma_wrreg(chan, S3C2410_DMA_DCON,
+ chan->dcon | reload | (buf->size/chan->xfer_unit));
+
+ chan->next = buf->next;
+
+ /* update the state of the channel */
+
+ switch (chan->load_state) {
+ case S3C2410_DMALOAD_NONE:
+ chan->load_state = S3C2410_DMALOAD_1LOADED;
+ break;
+
+ case S3C2410_DMALOAD_1RUNNING:
+ chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
+ break;
+
+ default:
+ dmawarn("dmaload: unknown state %d in loadbuffer\n",
+ chan->load_state);
+ break;
+ }
+
+ return 0;
+}
+
+/* s3c2410_dma_call_op
+ *
+ * small routine to call the op routine with the given op if it has been
+ * registered
+*/
+
+static void
+s3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op)
+{
+ if (chan->op_fn != NULL) {
+ (chan->op_fn)(chan, op);
+ }
+}
+
+/* s3c2410_dma_buffdone
+ *
+ * small wrapper to check if callback routine needs to be called, and
+ * if so, call it
+*/
+
+static inline void
+s3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf,
+ s3c2410_dma_buffresult_t result)
+{
+ pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
+ chan->callback_fn, buf, buf->id, buf->size, result);
+
+ if (chan->callback_fn != NULL) {
+ (chan->callback_fn)(chan, buf->id, buf->size, result);
+ }
+}
+
+/* s3c2410_dma_start
+ *
+ * start a dma channel going
+*/
+
+static int s3c2410_dma_start(s3c2410_dma_chan_t *chan)
+{
+ unsigned long tmp;
+ unsigned long flags;
+
+ pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
+
+ local_irq_save(flags);
+
+ if (chan->state == S3C2410_DMA_RUNNING) {
+ pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
+ local_irq_restore(flags);
+ return 0;
+ }
+
+ chan->state = S3C2410_DMA_RUNNING;
+
+ /* check wether there is anything to load, and if not, see
+ * if we can find anything to load
+ */
+
+ if (chan->load_state == S3C2410_DMALOAD_NONE) {
+ if (chan->next == NULL) {
+ printk(KERN_ERR "dma%d: channel has nothing loaded\n",
+ chan->number);
+ chan->state = S3C2410_DMA_IDLE;
+ local_irq_restore(flags);
+ return -EINVAL;
+ }
+
+ s3c2410_dma_loadbuffer(chan, chan->next);
+ }
+
+ dbg_showchan(chan);
+
+ /* enable the channel */
+
+ if (!chan->irq_enabled) {
+ enable_irq(chan->irq);
+ chan->irq_enabled = 1;
+ }
+
+ /* start the channel going */
+
+ tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+ tmp &= ~S3C2410_DMASKTRIG_STOP;
+ tmp |= S3C2410_DMASKTRIG_ON;
+ dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
+
+ pr_debug("wrote %08lx to DMASKTRIG\n", tmp);
+
+#if 0
+ /* the dma buffer loads should take care of clearing the AUTO
+ * reloading feature */
+ tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
+ tmp &= ~S3C2410_DCON_NORELOAD;
+ dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
+#endif
+
+ s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
+
+ dbg_showchan(chan);
+
+ local_irq_restore(flags);
+ return 0;
+}
+
+/* s3c2410_dma_canload
+ *
+ * work out if we can queue another buffer into the DMA engine
+*/
+
+static int
+s3c2410_dma_canload(s3c2410_dma_chan_t *chan)
+{
+ if (chan->load_state == S3C2410_DMALOAD_NONE ||
+ chan->load_state == S3C2410_DMALOAD_1RUNNING)
+ return 1;
+
+ return 0;
+}
+
+
+/* s3c2410_dma_enqueue
+ *
+ * queue an given buffer for dma transfer.
+ *
+ * id the device driver's id information for this buffer
+ * data the physical address of the buffer data
+ * size the size of the buffer in bytes
+ *
+ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
+ * is checked, and if set, the channel is started. If this flag isn't set,
+ * then an error will be returned.
+ *
+ * It is possible to queue more than one DMA buffer onto a channel at
+ * once, and the code will deal with the re-loading of the next buffer
+ * when necessary.
+*/
+
+int s3c2410_dma_enqueue(unsigned int channel, void *id,
+ dma_addr_t data, int size)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+ s3c2410_dma_buf_t *buf;
+ unsigned long flags;
+
+ check_channel(channel);
+
+ pr_debug("%s: id=%p, data=%08x, size=%d\n",
+ __FUNCTION__, id, (unsigned int)data, size);
+
+ buf = (s3c2410_dma_buf_t *)kmalloc(sizeof(*buf), GFP_ATOMIC);
+ if (buf == NULL) {
+ pr_debug("%s: out of memory (%d alloc)\n",
+ __FUNCTION__, sizeof(*buf));
+ return -ENOMEM;
+ }
+
+ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
+
+ //dbg_showchan(chan);
+
+ buf->next = NULL;
+ buf->data = buf->ptr = data;
+ buf->size = size;
+ buf->id = id;
+ buf->magic = BUF_MAGIC;
+
+ local_irq_save(flags);
+
+ if (chan->curr == NULL) {
+ /* we've got nothing loaded... */
+ pr_debug("%s: buffer %p queued onto empty channel\n",
+ __FUNCTION__, buf);
+
+ chan->curr = buf;
+ chan->end = buf;
+ chan->next = NULL;
+ } else {
+ pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
+ chan->number, __FUNCTION__, buf);
+
+ if (chan->end == NULL)
+ pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
+ chan->number, __FUNCTION__, chan);
+
+ chan->end->next = buf;
+ chan->end = buf;
+ }
+
+ /* if necessary, update the next buffer field */
+ if (chan->next == NULL)
+ chan->next = buf;
+
+ /* check to see if we can load a buffer */
+ if (chan->state == S3C2410_DMA_RUNNING) {
+ if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
+ if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+ printk(KERN_ERR "dma%d: loadbuffer:"
+ "timeout loading buffer\n",
+ chan->number);
+ dbg_showchan(chan);
+ local_irq_restore(flags);
+ return -EINVAL;
+ }
+ }
+
+ while (s3c2410_dma_canload(chan) && chan->next != NULL) {
+ s3c2410_dma_loadbuffer(chan, chan->next);
+ }
+ } else if (chan->state == S3C2410_DMA_IDLE) {
+ if (chan->flags & S3C2410_DMAF_AUTOSTART) {
+ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
+ } else {
+ printk(KERN_DEBUG "dma%d: cannot load onto stopped channel'n", chan->number);
+ local_irq_restore(flags);
+ return -EINVAL;
+ }
+ }
+
+ local_irq_restore(flags);
+ return 0;
+}
+
+static inline void
+s3c2410_dma_freebuf(s3c2410_dma_buf_t *buf)
+{
+ int magicok = (buf->magic == BUF_MAGIC);
+
+ buf->magic = -1;
+
+ if (magicok) {
+ kfree(buf);
+ } else {
+ printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
+ }
+}
+
+/* s3c2410_dma_lastxfer
+ *
+ * called when the system is out of buffers, to ensure that the channel
+ * is prepared for shutdown.
+*/
+
+static inline void
+s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan)
+{
+ pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
+ chan->number, chan->load_state);
+
+ switch (chan->load_state) {
+ case S3C2410_DMALOAD_NONE:
+ break;
+
+ case S3C2410_DMALOAD_1LOADED:
+ if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+ /* flag error? */
+ printk(KERN_ERR "dma%d: timeout waiting for load\n",
+ chan->number);
+ return;
+ }
+ break;
+
+ default:
+ pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",
+ chan->number, chan->load_state);
+ return;
+
+ }
+
+ /* hopefully this'll shut the damned thing up after the transfer... */
+ dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
+}
+
+
+#define dmadbg2(x...)
+
+static irqreturn_t
+s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
+{
+ s3c2410_dma_chan_t *chan = (s3c2410_dma_chan_t *)devpw;
+ s3c2410_dma_buf_t *buf;
+
+ buf = chan->curr;
+
+ dbg_showchan(chan);
+
+ /* modify the channel state */
+
+ switch (chan->load_state) {
+ case S3C2410_DMALOAD_1RUNNING:
+ /* TODO - if we are running only one buffer, we probably
+ * want to reload here, and then worry about the buffer
+ * callback */
+
+ chan->load_state = S3C2410_DMALOAD_NONE;
+ break;
+
+ case S3C2410_DMALOAD_1LOADED:
+ /* iirc, we should go back to NONE loaded here, we
+ * had a buffer, and it was never verified as being
+ * loaded.
+ */
+
+ chan->load_state = S3C2410_DMALOAD_NONE;
+ break;
+
+ case S3C2410_DMALOAD_1LOADED_1RUNNING:
+ /* we'll worry about checking to see if another buffer is
+ * ready after we've called back the owner. This should
+ * ensure we do not wait around too long for the DMA
+ * engine to start the next transfer
+ */
+
+ chan->load_state = S3C2410_DMALOAD_1LOADED;
+ break;
+
+ case S3C2410_DMALOAD_NONE:
+ printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
+ chan->number);
+ break;
+
+ default:
+ printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
+ chan->number, chan->load_state);
+ break;
+ }
+
+ if (buf != NULL) {
+ /* update the chain to make sure that if we load any more
+ * buffers when we call the callback function, things should
+ * work properly */
+
+ chan->curr = buf->next;
+ buf->next = NULL;
+
+ if (buf->magic != BUF_MAGIC) {
+ printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
+ chan->number, __FUNCTION__, buf);
+ return IRQ_HANDLED;
+ }
+
+ s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
+
+ /* free resouces */
+ s3c2410_dma_freebuf(buf);
+ } else {
+ }
+
+ if (chan->next != NULL) {
+ unsigned long flags;
+
+ switch (chan->load_state) {
+ case S3C2410_DMALOAD_1RUNNING:
+ /* don't need to do anything for this state */
+ break;
+
+ case S3C2410_DMALOAD_NONE:
+ /* can load buffer immediately */
+ break;
+
+ case S3C2410_DMALOAD_1LOADED:
+ if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
+ /* flag error? */
+ printk(KERN_ERR "dma%d: timeout waiting for load\n",
+ chan->number);
+ return IRQ_HANDLED;
+ }
+
+ break;
+
+ default:
+ printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
+ chan->number, chan->load_state);
+ return IRQ_HANDLED;
+ }
+
+ local_irq_save(flags);
+ s3c2410_dma_loadbuffer(chan, chan->next);
+ local_irq_restore(flags);
+ } else {
+ s3c2410_dma_lastxfer(chan);
+
+ /* see if we can stop this channel.. */
+ if (chan->load_state == S3C2410_DMALOAD_NONE) {
+ pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
+ chan->number, jiffies);
+ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+
+
+/* s3c2410_request_dma
+ *
+ * get control of an dma channel
+*/
+
+int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client,
+ void *dev)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+ unsigned long flags;
+ int err;
+
+ pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
+ channel, client->name, dev);
+
+ check_channel(channel);
+
+ local_irq_save(flags);
+
+ dbg_showchan(chan);
+
+ if (chan->in_use) {
+ if (client != chan->client) {
+ printk(KERN_ERR "dma%d: already in use\n", channel);
+ local_irq_restore(flags);
+ return -EBUSY;
+ } else {
+ printk(KERN_ERR "dma%d: client already has channel\n", channel);
+ }
+ }
+
+ chan->client = client;
+ chan->in_use = 1;
+
+ if (!chan->irq_claimed) {
+ pr_debug("dma%d: %s : requesting irq %d\n",
+ channel, __FUNCTION__, chan->irq);
+
+ err = request_irq(chan->irq, s3c2410_dma_irq, SA_INTERRUPT,
+ client->name, (void *)chan);
+
+ if (err) {
+ chan->in_use = 0;
+ local_irq_restore(flags);
+
+ printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
+ client->name, chan->irq, chan->number);
+ return err;
+ }
+
+ chan->irq_claimed = 1;
+ chan->irq_enabled = 1;
+ }
+
+ local_irq_restore(flags);
+
+ /* need to setup */
+
+ pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
+
+ return 0;
+}
+
+/* s3c2410_dma_free
+ *
+ * release the given channel back to the system, will stop and flush
+ * any outstanding transfers, and ensure the channel is ready for the
+ * next claimant.
+ *
+ * Note, although a warning is currently printed if the freeing client
+ * info is not the same as the registrant's client info, the free is still
+ * allowed to go through.
+*/
+
+int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+ unsigned long flags;
+
+ check_channel(channel);
+
+ local_irq_save(flags);
+
+
+ if (chan->client != client) {
+ printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
+ channel, chan->client, client);
+ }
+
+ /* sort out stopping and freeing the channel */
+
+ if (chan->state != S3C2410_DMA_IDLE) {
+ pr_debug("%s: need to stop dma channel %p\n",
+ __FUNCTION__, chan);
+
+ /* possibly flush the channel */
+ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
+ }
+
+ chan->client = NULL;
+ chan->in_use = 0;
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan)
+{
+ unsigned long tmp;
+ unsigned long flags;
+
+ pr_debug("%s:\n", __FUNCTION__);
+
+ dbg_showchan(chan);
+
+ local_irq_save(flags);
+
+ s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
+
+ tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
+ tmp |= S3C2410_DMASKTRIG_STOP;
+ dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
+
+#if 0
+ /* should also clear interrupts, according to WinCE BSP */
+ tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
+ tmp |= S3C2410_DCON_NORELOAD;
+ dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
+#endif
+
+ chan->state = S3C2410_DMA_IDLE;
+ chan->load_state = S3C2410_DMALOAD_NONE;
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+/* s3c2410_dma_flush
+ *
+ * stop the channel, and remove all current and pending transfers
+*/
+
+static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan)
+{
+ s3c2410_dma_buf_t *buf, *next;
+ unsigned long flags;
+
+ pr_debug("%s:\n", __FUNCTION__);
+
+ local_irq_save(flags);
+
+ if (chan->state != S3C2410_DMA_IDLE) {
+ pr_debug("%s: stopping channel...\n", __FUNCTION__ );
+ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
+ }
+
+ buf = chan->curr;
+ if (buf == NULL)
+ buf = chan->next;
+
+ chan->curr = chan->next = chan->end = NULL;
+
+ if (buf != NULL) {
+ for ( ; buf != NULL; buf = next) {
+ next = buf->next;
+
+ pr_debug("%s: free buffer %p, next %p\n",
+ __FUNCTION__, buf, buf->next);
+
+ s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
+ s3c2410_dma_freebuf(buf);
+ }
+ }
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+
+int
+s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+
+ check_channel(channel);
+
+ switch (op) {
+ case S3C2410_DMAOP_START:
+ return s3c2410_dma_start(chan);
+
+ case S3C2410_DMAOP_STOP:
+ return s3c2410_dma_dostop(chan);
+
+ case S3C2410_DMAOP_PAUSE:
+ return -ENOENT;
+
+ case S3C2410_DMAOP_RESUME:
+ return -ENOENT;
+
+ case S3C2410_DMAOP_FLUSH:
+ return s3c2410_dma_flush(chan);
+
+ case S3C2410_DMAOP_TIMEOUT:
+ return 0;
+
+ }
+
+ return -ENOENT; /* unknown, don't bother */
+}
+
+
+/* DMA configuration for each channel
+ *
+ * DISRCC -> source of the DMA (AHB,APB)
+ * DISRC -> source address of the DMA
+ * DIDSTC -> destination of the DMA (AHB,APD)
+ * DIDST -> destination address of the DMA
+*/
+
+/* s3c2410_dma_config
+ *
+ * xfersize: size of unit in bytes (1,2,4)
+ * dcon: base value of the DCONx register
+*/
+
+int s3c2410_dma_config(dmach_t channel,
+ int xferunit,
+ int dcon)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+
+ pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
+ __FUNCTION__, channel, xferunit, dcon);
+
+ check_channel(channel);
+
+ switch (xferunit) {
+ case 1:
+ dcon |= S3C2410_DCON_BYTE;
+ break;
+
+ case 2:
+ dcon |= S3C2410_DCON_HALFWORD;
+ break;
+
+ case 4:
+ dcon |= S3C2410_DCON_WORD;
+ break;
+
+ default:
+ pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
+ return -EINVAL;
+ }
+
+ dcon |= S3C2410_DCON_HWTRIG;
+ dcon |= S3C2410_DCON_INTREQ;
+
+ pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
+
+ chan->dcon = dcon;
+ chan->xfer_unit = xferunit;
+
+ return 0;
+}
+
+
+int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+
+ check_channel(channel);
+
+ pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
+
+ chan->flags = flags;
+
+ return 0;
+}
+
+/* do we need to protect the settings of the fields from
+ * irq?
+*/
+
+int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+
+ check_channel(channel);
+
+ pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
+
+ chan->op_fn = rtn;
+
+ return 0;
+}
+
+int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+
+ check_channel(channel);
+
+ pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
+
+ chan->callback_fn = rtn;
+
+ return 0;
+}
+
+/* s3c2410_dma_devconfig
+ *
+ * configure the dma source/destination hardware type and address
+ *
+ * source: S3C2410_DMASRC_HW: source is hardware
+ * S3C2410_DMASRC_MEM: source is memory
+ *
+ * hwcfg: the value for xxxSTCn register,
+ * bit 0: 0=increment pointer, 1=leave pointer
+ * bit 1: 0=soucre is AHB, 1=soucre is APB
+ *
+ * devaddr: physical address of the source
+*/
+
+int s3c2410_dma_devconfig(int channel,
+ s3c2410_dmasrc_t source,
+ int hwcfg,
+ unsigned long devaddr)
+{
+ s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
+
+ check_channel(channel);
+
+ pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
+ __FUNCTION__, (int)source, hwcfg, devaddr);
+
+ chan->source = source;
+ chan->dev_addr = devaddr;
+
+ switch (source) {
+ case S3C2410_DMASRC_HW:
+ /* source is hardware */
+ pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
+ __FUNCTION__, devaddr, hwcfg);
+ dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
+ dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
+ dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
+
+ chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
+ return 0;
+
+ case S3C2410_DMASRC_MEM:
+ /* source is memory */
+ pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
+ __FUNCTION__, devaddr, hwcfg);
+ dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
+ dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
+ dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
+
+ chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
+ return 0;
+ }
+
+ printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
+ return -EINVAL;
+}
+
+/* initialisation code */
+
+static int __init s3c2410_init_dma(void)
+{
+ int channel;
+ s3c2410_dma_chan_t *cp;
+
+ printk("S3C2410 DMA Driver, (c) 2003-2004 Simtec Electronics\n");
+
+ dma_base = ioremap(S3C2410_PA_DMA, 0x200);
+ if (dma_base == NULL) {
+ printk(KERN_ERR "dma failed to remap register block\n");
+ return -ENOMEM;
+ }
+
+ for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) {
+ cp = &s3c2410_chans[channel];
+
+ memset(cp, 0, sizeof(s3c2410_dma_chan_t));
+
+ /* dma channel irqs are in order.. */
+ cp->number = channel;
+ cp->irq = channel + IRQ_DMA0;
+ cp->regs = (unsigned long)dma_base + (channel*0x40);
+
+ /* point current stats somewhere */
+ cp->stats = &cp->stats_store;
+ cp->stats_store.timeout_shortest = LONG_MAX;
+
+ /* basic channel configuration */
+
+ cp->load_timeout = 1<<18;
+
+ printk("DMA channel %d at %08lx, irq %d\n",
+ cp->number, cp->regs, cp->irq);
+ }
+
+ return 0;
+}
+
+__initcall(s3c2410_init_dma);
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/s3c2440-dsc.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C2440 Drive Strength Control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 29-Aug-2004 BJD Start of drive-strength control
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-dsc.h>
+
+#include "s3c2440.h"
+#include "cpu.h"
+
+int s3c2440_set_dsc(unsigned int pin, unsigned int value)
+{
+ unsigned long base;
+ unsigned long val;
+ unsigned long flags;
+ unsigned long mask;
+
+ base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
+ mask = 3 << S3C2440_DSC_GETSHIFT(pin);
+
+ local_irq_save(flags);
+
+ val = __raw_readl(base);
+ val &= ~mask;
+ val |= value & mask;
+ __raw_writel(val, base);
+
+ local_irq_restore(flags);
+ return 0;
+}
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/s3c2440.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C2440 Mobile CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 24-Aug-2004 BJD Start of s3c2440 support
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-serial.h>
+
+#include "s3c2440.h"
+#include "cpu.h"
+
+int s3c2440_clock_tick_rate = 12*1000*1000; /* current timers at 12MHz */
+
+/* clock info */
+
+unsigned long s3c2440_baseclk = 12*1000*1000; /* assume base is 12MHz */
+unsigned long s3c2440_hdiv;
+
+unsigned long s3c2440_fclk;
+unsigned long s3c2440_hclk;
+unsigned long s3c2440_pclk;
+
+static struct map_desc s3c2440_iodesc[] __initdata = {
+ IODESC_ENT(USBHOST),
+ IODESC_ENT(CLKPWR),
+ IODESC_ENT(LCD),
+ IODESC_ENT(TIMER),
+ IODESC_ENT(ADC),
+};
+
+static struct resource s3c_uart0_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_UART0,
+ .end = S3C2410_PA_UART0 + 0x3fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX0,
+ .end = IRQ_S3CUART_ERR0,
+ .flags = IORESOURCE_IRQ,
+ }
+
+};
+
+static struct resource s3c_uart1_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_UART1,
+ .end = S3C2410_PA_UART1 + 0x3fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX1,
+ .end = IRQ_S3CUART_ERR1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct resource s3c_uart2_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_UART2,
+ .end = S3C2410_PA_UART2 + 0x3fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX2,
+ .end = IRQ_S3CUART_ERR2,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+/* our uart devices */
+
+static struct platform_device s3c_uart0 = {
+ .name = "s3c2440-uart",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(s3c_uart0_resource),
+ .resource = s3c_uart0_resource,
+};
+
+
+static struct platform_device s3c_uart1 = {
+ .name = "s3c2440-uart",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_uart1_resource),
+ .resource = s3c_uart1_resource,
+};
+
+static struct platform_device s3c_uart2 = {
+ .name = "s3c2440-uart",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(s3c_uart2_resource),
+ .resource = s3c_uart2_resource,
+};
+
+static struct platform_device *uart_devices[] __initdata = {
+ &s3c_uart0,
+ &s3c_uart1,
+ &s3c_uart2
+};
+
+void __init s3c2440_map_io(struct map_desc *mach_desc, int size)
+{
+ unsigned long tmp;
+ unsigned long camdiv;
+
+ /* register our io-tables */
+
+ iotable_init(s3c2440_iodesc, ARRAY_SIZE(s3c2440_iodesc));
+ iotable_init(mach_desc, size);
+
+ /* now we've got our machine bits initialised, work out what
+ * clocks we've got */
+
+ s3c2440_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON),
+ s3c2440_baseclk);
+
+ tmp = __raw_readl(S3C2410_CLKDIVN);
+ camdiv = __raw_readl(S3C2440_CAMDIVN);
+
+ /* work out clock scalings */
+
+ switch (tmp & S3C2440_CLKDIVN_HDIVN_MASK) {
+ case S3C2440_CLKDIVN_HDIVN_1:
+ s3c2440_hdiv = 1;
+ break;
+
+ case S3C2440_CLKDIVN_HDIVN_2:
+ s3c2440_hdiv = 1;
+ break;
+
+ case S3C2440_CLKDIVN_HDIVN_4_8:
+ s3c2440_hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
+ break;
+
+ case S3C2440_CLKDIVN_HDIVN_3_6:
+ s3c2440_hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 6 : 3;
+ break;
+ }
+
+ s3c2440_hclk = s3c2440_fclk / s3c2440_hdiv;
+ s3c2440_pclk = s3c2440_hclk / ((tmp & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
+
+ /* print brieft summary of clocks, etc */
+
+ printk("S3C2440: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
+ print_mhz(s3c2440_fclk), print_mhz(s3c2440_hclk),
+ print_mhz(s3c2440_pclk));
+}
+
+
+
+int __init s3c2440_init(void)
+{
+ int ret;
+
+ printk("S3C2440: Initialising architecture\n");
+
+ ret = platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices));
+ if (ret)
+ return ret;
+
+ // todo: board specific inits?
+
+ return ret;
+}
+
--- /dev/null
+/* arch/arm/mach-s3c2410/s3c2440.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for s3c2440 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 24-Aug-2004 BJD Start of S3C2440 CPU support
+*/
+
+extern void s3c2440_init_irq(void);
+
+extern void s3c2440_init_time(void);
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/usb-simtec.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.simtec.co.uk/products/EB2410ITX/
+ *
+ * Simtec BAST and Thorcom VR1000 USB port support functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 14-Sep-2004 BJD Created
+*/
+
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-irq.h>
+#include <asm/arch/usb-control.h>
+#include <asm/arch/regs-gpio.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include "devs.h"
+#include "usb-simtec.h"
+
+/* control power and monitor over-current events on various Simtec
+ * designed boards.
+*/
+
+static void
+usb_simtec_powercontrol(int port, int to)
+{
+ pr_debug("usb_simtec_powercontrol(%d,%d)\n", port, to);
+
+ if (port == 1) {
+ s3c2410_gpio_setpin(S3C2410_GPB4, to ? 0:1);
+ pr_debug("GPBDAT now %08x\n", __raw_readl(S3C2410_GPBDAT));
+ }
+}
+
+static irqreturn_t
+usb_simtec_ocirq(int irq, void *pw, struct pt_regs *regs)
+{
+ struct s3c2410_hcd_info *info = (struct s3c2410_hcd_info *)pw;
+
+ if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) {
+ pr_debug("usb_simtec: over-current irq (oc detected)\n");
+ s3c2410_report_oc(info, 3);
+ } else {
+ pr_debug("usb_simtec: over-current irq (oc cleared)\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
+{
+ int ret;
+
+ if (on) {
+ pr_debug("claiming usb overccurent\n");
+ ret = request_irq(IRQ_USBOC, usb_simtec_ocirq, SA_INTERRUPT,
+ "usb-oc", info);
+ if (ret != 0) {
+ printk(KERN_ERR "failed to request usb oc irq\n");
+ }
+
+ set_irq_type(IRQ_USBOC, IRQT_BOTHEDGE);
+ } else {
+ free_irq(IRQ_USBOC, NULL);
+ }
+}
+
+static struct s3c2410_hcd_info usb_simtec_info = {
+ .port[0] = {
+ .flags = S3C_HCDFLG_USED
+ },
+ .port[1] = {
+ .flags = S3C_HCDFLG_USED
+ },
+
+ .power_control = usb_simtec_powercontrol,
+ .enable_oc = usb_simtec_enableoc,
+};
+
+
+int usb_simtec_init(void)
+{
+ printk("USB Power Control, (c) 2004 Simtec Electronics\n");
+ s3c_device_usb.dev.platform_data = &usb_simtec_info;
+
+ s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP);
+ s3c2410_gpio_setpin(S3C2410_GPB4, 1);
+
+ pr_debug("GPB: CON=%08x, DAT=%08x\n",
+ __raw_readl(S3C2410_GPBCON), __raw_readl(S3C2410_GPBDAT));
+
+ if (0) {
+ s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST,
+ S3C2410_MISCCR_USBDEV);
+ }
+
+ return 0;
+}
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/usb-simtec.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.simtec.co.uk/products/EB2410ITX/
+ *
+ * Simtec BAST and Thorcom VR1000 USB port support functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 20-Aug-2004 BJD Created
+*/
+
+extern int usb_simtec_init(void);
+
--- /dev/null
+/*
+ * linux/arch/arm/mm/flush.c
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+
+#include <asm/cacheflush.h>
+#include <asm/system.h>
+
+static void __flush_dcache_page(struct address_space *mapping, struct page *page)
+{
+ struct mm_struct *mm = current->active_mm;
+ struct vm_area_struct *mpnt;
+ struct prio_tree_iter iter;
+ pgoff_t pgoff;
+
+ /*
+ * Writeback any data associated with the kernel mapping of this
+ * page. This ensures that data in the physical page is mutually
+ * coherent with the kernels mapping.
+ */
+ __cpuc_flush_dcache_page(page_address(page));
+
+ /*
+ * If there's no mapping pointer here, then this page isn't
+ * visible to userspace yet, so there are no cache lines
+ * associated with any other aliases.
+ */
+ if (!mapping)
+ return;
+
+ /*
+ * There are possible user space mappings of this page:
+ * - VIVT cache: we need to also write back and invalidate all user
+ * data in the current VM view associated with this page.
+ * - aliasing VIPT: we only need to find one mapping of this page.
+ */
+ pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
+
+ flush_dcache_mmap_lock(mapping);
+ vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
+ unsigned long offset;
+
+ /*
+ * If this VMA is not in our MM, we can ignore it.
+ */
+ if (mpnt->vm_mm != mm)
+ continue;
+ if (!(mpnt->vm_flags & VM_MAYSHARE))
+ continue;
+ offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
+ flush_cache_page(mpnt, mpnt->vm_start + offset);
+ if (cache_is_vipt())
+ break;
+ }
+ flush_dcache_mmap_unlock(mapping);
+}
+
+/*
+ * Ensure cache coherency between kernel mapping and userspace mapping
+ * of this page.
+ *
+ * We have three cases to consider:
+ * - VIPT non-aliasing cache: fully coherent so nothing required.
+ * - VIVT: fully aliasing, so we need to handle every alias in our
+ * current VM view.
+ * - VIPT aliasing: need to handle one alias in our current VM view.
+ *
+ * If we need to handle aliasing:
+ * If the page only exists in the page cache and there are no user
+ * space mappings, we can be lazy and remember that we may have dirty
+ * kernel cache lines for later. Otherwise, we assume we have
+ * aliasing mappings.
+ */
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+
+ if (cache_is_vipt_nonaliasing())
+ return;
+
+ if (mapping && !mapping_mapped(mapping))
+ set_bit(PG_dcache_dirty, &page->flags);
+ else
+ __flush_dcache_page(mapping, page);
+}
+EXPORT_SYMBOL(flush_dcache_page);
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+# RMK wants arm kernels compiled with frame pointers so hardwire this to y.
+# If you know what you are doing and are willing to live without stack
+# traces, you can get a slightly smaller kernel by setting this option to
+# n, but then RMK will have to kill you ;).
+config FRAME_POINTER
+ bool
+ default y
+ help
+ If you say N here, the resulting kernel will be slightly smaller and
+ faster. However, when a problem occurs with the kernel, the
+ information that is reported is severely limited. Most people
+ should say Y here.
+
+config DEBUG_USER
+ bool "Verbose user fault messages"
+ help
+ When a user program crashes due to an exception, the kernel can
+ print a brief message explaining what the problem was. This is
+ sometimes helpful for debugging but serves no purpose on a
+ production system. Most people should say N here.
+
+config DEBUG_WAITQ
+ bool "Wait queue debugging"
+ depends on DEBUG_KERNEL
+
+config DEBUG_ERRORS
+ bool "Verbose kernel error messages"
+ depends on DEBUG_KERNEL
+ help
+ This option controls verbose debugging information which can be
+ printed when the kernel detects an internal error. This debugging
+ information is useful to kernel hackers when tracking down problems,
+ but mostly meaningless to other people. It's safe to say Y unless
+ you are concerned with the code size or don't want to see these
+ messages.
+
+config DEBUG_INFO
+ bool "Include GDB debugging information in kernel binary"
+ help
+ Say Y here to include source-level debugging information in the
+ `vmlinux' binary image. This is handy if you want to use gdb or
+ addr2line to debug the kernel. It has no impact on the in-memory
+ footprint of the running kernel but it can increase the amount of
+ time and disk space needed for compilation of the kernel. If in
+ doubt say N.
+
+# These options are only for real kernel hackers who want to get their hands dirty.
+config DEBUG_LL
+ bool "Kernel low-level debugging functions"
+ depends on DEBUG_KERNEL
+ help
+ Say Y here to include definitions of printascii, printchar, printhex
+ in the kernel. This is helpful if you are debugging code that
+ executes before the console is initialized.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+#bool 'Debug kmalloc/kfree' CONFIG_DEBUG_MALLOC
+config PROFILE
+ bool "Kernel profiling support"
+
+config PROFILE_SHIFT
+ int "Profile shift count"
+ depends on PROFILE
+ default "2"
+
+config ETRAX_KGDB
+ bool "Use kernel GDB debugger"
+ ---help---
+ The CRIS version of gdb can be used to remotely debug a running
+ Linux kernel via the serial debug port. Provided you have gdb-cris
+ installed, run gdb-cris vmlinux, then type
+
+ (gdb) set remotebaud 115200 <- kgdb uses 115200 as default
+ (gdb) target remote /dev/ttyS0 <- maybe you use another port
+
+ This should connect you to your booted kernel (or boot it now if you
+ didn't before). The kernel halts when it boots, waiting for gdb if
+ this option is turned on!
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config FULLDEBUG
+ bool "Full Symbolic/Source Debugging support"
+ help
+ Enable debugging symbols on kernel build.
+
+config HIGHPROFILE
+ bool "Use fast second timer for profiling"
+ help
+ Use a fast secondary clock to produce profiling information.
+
+config NO_KERNEL_MSG
+ bool "Suppress Kernel BUG Messages"
+ help
+ Do not output any debug BUG messages within the kernel.
+
+config GDB_MAGICPRINT
+ bool "Message Output for GDB MagicPrint service"
+ depends on (H8300H_SIM || H8S_SIM)
+ help
+ kernel messages output useing MagicPrint service from GDB
+
+config SYSCALL_PRINT
+ bool "SystemCall trace print"
+ help
+ outout history of systemcall
+
+config GDB_DEBUG
+ bool "Use gdb stub"
+ depends on (!H8300H_SIM && !H8S_SIM)
+ help
+ gdb stub exception support
+
+config CONFIG_SH_STANDARD_BIOS
+ bool "Use gdb protocol serial console"
+ depends on (!H8300H_SIM && !H8S_SIM)
+ help
+ serial console output using GDB protocol.
+ Require eCos/RedBoot
+
+config DEFAULT_CMDLINE
+ bool "Use buildin commandline"
+ default n
+ help
+ buildin kernel commandline enabled.
+
+config KERNEL_COMMAND
+ string "Buildin commmand string"
+ depends on DEFAULT_CMDLINE
+ help
+ buildin kernel commandline strings.
+
+config BLKDEV_RESERVE
+ bool "BLKDEV Reserved Memory"
+ default n
+ help
+ Reserved BLKDEV area.
+
+config CONFIG_BLKDEV_RESERVE_ADDRESS
+ hex 'start address'
+ depends on BLKDEV_RESERVE
+ help
+ BLKDEV start address.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config EARLY_PRINTK
+ bool "Early printk" if EMBEDDED
+ default y
+ help
+ Write kernel log output directly into the VGA buffer or to a serial
+ port.
+
+ This is useful for kernel debugging when your machine crashes very
+ early before the console code is initialized. For normal operation
+ it is not recommended because it looks ugly and doesn't cooperate
+ with klogd/syslogd or the X server. You should normally N here,
+ unless you want to debug such a crash.
+
+config DEBUG_STACKOVERFLOW
+ bool "Check for stack overflows"
+ depends on DEBUG_KERNEL
+
+config KPROBES
+ bool "Kprobes"
+ depends on DEBUG_KERNEL
+ help
+ Kprobes allows you to trap at almost any kernel address and
+ execute a callback function. register_kprobe() establishes
+ a probepoint and specifies the callback. Kprobes is useful
+ for kernel debugging, non-intrusive instrumentation and testing.
+ If in doubt, say "N".
+
+config DEBUG_STACK_USAGE
+ bool "Stack utilization instrumentation"
+ depends on DEBUG_KERNEL
+ help
+ Enables the display of the minimum amount of free stack which each
+ task has ever had available in the sysrq-T and sysrq-P debug output.
+
+ This option will slow down process creation somewhat.
+
+config DEBUG_PAGEALLOC
+ bool "Page alloc debugging"
+ depends on DEBUG_KERNEL
+ help
+ Unmap pages from the kernel linear mapping after free_pages().
+ This results in a large slowdown, but helps to find certain types
+ of memory corruptions.
+
+config 4KSTACKS
+ bool "Use 4Kb for kernel stacks instead of 8Kb"
+ help
+ If you say Y here the kernel will use a 4Kb stacksize for the
+ kernel stack attached to each process/thread. This facilitates
+ running more threads on a system and also reduces the pressure
+ on the VM subsystem for higher order allocations. This option
+ will also use IRQ stacks to compensate for the reduced stackspace.
+
+config SCHEDSTATS
+ bool "Collect scheduler statistics"
+ depends on DEBUG_KERNEL && PROC_FS
+ help
+ If you say Y here, additional code will be inserted into the
+ scheduler and related routines to collect statistics about
+ scheduler behavior and provide them in /proc/schedstat. These
+ stats may be useful for both tuning and debugging the scheduler
+ If you aren't debugging the scheduler or trying to tune a specific
+ application, you can say N to avoid the very slight overhead
+ this adds.
+
+config X86_FIND_SMP_CONFIG
+ bool
+ depends on X86_LOCAL_APIC || X86_VOYAGER
+ default y
+
+config X86_MPPARSE
+ bool
+ depends on X86_LOCAL_APIC && !X86_VISWS
+ default y
+
+endmenu
--- /dev/null
+/*
+ * Kernel Probes (KProbes)
+ * arch/i386/kernel/kprobes.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ *
+ * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
+ * Probes initial implementation ( includes contributions from
+ * Rusty Russell).
+ * 2004-July Suparna Bhattacharya <suparna@in.ibm.com> added jumper probes
+ * interface to access function arguments.
+ */
+
+#include <linux/config.h>
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+#include <linux/spinlock.h>
+#include <linux/preempt.h>
+#include <asm/kdebug.h>
+
+/* kprobe_status settings */
+#define KPROBE_HIT_ACTIVE 0x00000001
+#define KPROBE_HIT_SS 0x00000002
+
+static struct kprobe *current_kprobe;
+static unsigned long kprobe_status, kprobe_old_eflags, kprobe_saved_eflags;
+static struct pt_regs jprobe_saved_regs;
+static long *jprobe_saved_esp;
+/* copy of the kernel stack at the probe fire time */
+static kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE];
+
+/*
+ * returns non-zero if opcode modifies the interrupt flag.
+ */
+static inline int is_IF_modifier(kprobe_opcode_t opcode)
+{
+ switch (opcode) {
+ case 0xfa: /* cli */
+ case 0xfb: /* sti */
+ case 0xcf: /* iret/iretd */
+ case 0x9d: /* popf/popfd */
+ return 1;
+ }
+ return 0;
+}
+
+void arch_prepare_kprobe(struct kprobe *p)
+{
+ memcpy(p->insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
+}
+
+static inline void disarm_kprobe(struct kprobe *p, struct pt_regs *regs)
+{
+ *p->addr = p->opcode;
+ regs->eip = (unsigned long)p->addr;
+}
+
+static inline void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+ regs->eflags |= TF_MASK;
+ regs->eflags &= ~IF_MASK;
+ regs->eip = (unsigned long)&p->insn;
+}
+
+/*
+ * Interrupts are disabled on entry as trap3 is an interrupt gate and they
+ * remain disabled thorough out this function.
+ */
+static inline int kprobe_handler(struct pt_regs *regs)
+{
+ struct kprobe *p;
+ int ret = 0;
+ u8 *addr = (u8 *) (regs->eip - 1);
+
+ /* We're in an interrupt, but this is clear and BUG()-safe. */
+ preempt_disable();
+
+ /* Check we're not actually recursing */
+ if (kprobe_running()) {
+ /* We *are* holding lock here, so this is safe.
+ Disarm the probe we just hit, and ignore it. */
+ p = get_kprobe(addr);
+ if (p) {
+ disarm_kprobe(p, regs);
+ ret = 1;
+ } else {
+ p = current_kprobe;
+ if (p->break_handler && p->break_handler(p, regs)) {
+ goto ss_probe;
+ }
+ }
+ /* If it's not ours, can't be delete race, (we hold lock). */
+ goto no_kprobe;
+ }
+
+ lock_kprobes();
+ p = get_kprobe(addr);
+ if (!p) {
+ unlock_kprobes();
+ if (*addr != BREAKPOINT_INSTRUCTION) {
+ /*
+ * The breakpoint instruction was removed right
+ * after we hit it. Another cpu has removed
+ * either a probepoint or a debugger breakpoint
+ * at this address. In either case, no further
+ * handling of this interrupt is appropriate.
+ */
+ ret = 1;
+ }
+ /* Not one of ours: let kernel handle it */
+ goto no_kprobe;
+ }
+
+ kprobe_status = KPROBE_HIT_ACTIVE;
+ current_kprobe = p;
+ kprobe_saved_eflags = kprobe_old_eflags
+ = (regs->eflags & (TF_MASK | IF_MASK));
+ if (is_IF_modifier(p->opcode))
+ kprobe_saved_eflags &= ~IF_MASK;
+
+ if (p->pre_handler(p, regs)) {
+ /* handler has already set things up, so skip ss setup */
+ return 1;
+ }
+
+ ss_probe:
+ prepare_singlestep(p, regs);
+ kprobe_status = KPROBE_HIT_SS;
+ return 1;
+
+ no_kprobe:
+ preempt_enable_no_resched();
+ return ret;
+}
+
+/*
+ * Called after single-stepping. p->addr is the address of the
+ * instruction whose first byte has been replaced by the "int 3"
+ * instruction. To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction. The address of this
+ * copy is p->insn.
+ *
+ * This function prepares to return from the post-single-step
+ * interrupt. We have to fix up the stack as follows:
+ *
+ * 0) Except in the case of absolute or indirect jump or call instructions,
+ * the new eip is relative to the copied instruction. We need to make
+ * it relative to the original instruction.
+ *
+ * 1) If the single-stepped instruction was pushfl, then the TF and IF
+ * flags are set in the just-pushed eflags, and may need to be cleared.
+ *
+ * 2) If the single-stepped instruction was a call, the return address
+ * that is atop the stack is the address following the copied instruction.
+ * We need to make it the address following the original instruction.
+ */
+static void resume_execution(struct kprobe *p, struct pt_regs *regs)
+{
+ unsigned long *tos = (unsigned long *)®s->esp;
+ unsigned long next_eip = 0;
+ unsigned long copy_eip = (unsigned long)&p->insn;
+ unsigned long orig_eip = (unsigned long)p->addr;
+
+ switch (p->insn[0]) {
+ case 0x9c: /* pushfl */
+ *tos &= ~(TF_MASK | IF_MASK);
+ *tos |= kprobe_old_eflags;
+ break;
+ case 0xe8: /* call relative - Fix return addr */
+ *tos = orig_eip + (*tos - copy_eip);
+ break;
+ case 0xff:
+ if ((p->insn[1] & 0x30) == 0x10) {
+ /* call absolute, indirect */
+ /* Fix return addr; eip is correct. */
+ next_eip = regs->eip;
+ *tos = orig_eip + (*tos - copy_eip);
+ } else if (((p->insn[1] & 0x31) == 0x20) || /* jmp near, absolute indirect */
+ ((p->insn[1] & 0x31) == 0x21)) { /* jmp far, absolute indirect */
+ /* eip is correct. */
+ next_eip = regs->eip;
+ }
+ break;
+ case 0xea: /* jmp absolute -- eip is correct */
+ next_eip = regs->eip;
+ break;
+ default:
+ break;
+ }
+
+ regs->eflags &= ~TF_MASK;
+ if (next_eip) {
+ regs->eip = next_eip;
+ } else {
+ regs->eip = orig_eip + (regs->eip - copy_eip);
+ }
+}
+
+/*
+ * Interrupts are disabled on entry as trap1 is an interrupt gate and they
+ * remain disabled thoroughout this function. And we hold kprobe lock.
+ */
+static inline int post_kprobe_handler(struct pt_regs *regs)
+{
+ if (!kprobe_running())
+ return 0;
+
+ if (current_kprobe->post_handler)
+ current_kprobe->post_handler(current_kprobe, regs, 0);
+
+ resume_execution(current_kprobe, regs);
+ regs->eflags |= kprobe_saved_eflags;
+
+ unlock_kprobes();
+ preempt_enable_no_resched();
+
+ /*
+ * if somebody else is singlestepping across a probe point, eflags
+ * will have TF set, in which case, continue the remaining processing
+ * of do_debug, as if this is not a probe hit.
+ */
+ if (regs->eflags & TF_MASK)
+ return 0;
+
+ return 1;
+}
+
+/* Interrupts disabled, kprobe_lock held. */
+static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+ if (current_kprobe->fault_handler
+ && current_kprobe->fault_handler(current_kprobe, regs, trapnr))
+ return 1;
+
+ if (kprobe_status & KPROBE_HIT_SS) {
+ resume_execution(current_kprobe, regs);
+ regs->eflags |= kprobe_old_eflags;
+
+ unlock_kprobes();
+ preempt_enable_no_resched();
+ }
+ return 0;
+}
+
+/*
+ * Wrapper routine to for handling exceptions.
+ */
+int kprobe_exceptions_notify(struct notifier_block *self, unsigned long val,
+ void *data)
+{
+ struct die_args *args = (struct die_args *)data;
+ switch (val) {
+ case DIE_INT3:
+ if (kprobe_handler(args->regs))
+ return NOTIFY_STOP;
+ break;
+ case DIE_DEBUG:
+ if (post_kprobe_handler(args->regs))
+ return NOTIFY_STOP;
+ break;
+ case DIE_GPF:
+ if (kprobe_running() &&
+ kprobe_fault_handler(args->regs, args->trapnr))
+ return NOTIFY_STOP;
+ break;
+ case DIE_PAGE_FAULT:
+ if (kprobe_running() &&
+ kprobe_fault_handler(args->regs, args->trapnr))
+ return NOTIFY_STOP;
+ break;
+ default:
+ break;
+ }
+ return NOTIFY_DONE;
+}
+
+int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+ struct jprobe *jp = container_of(p, struct jprobe, kp);
+ unsigned long addr;
+
+ jprobe_saved_regs = *regs;
+ jprobe_saved_esp = ®s->esp;
+ addr = (unsigned long)jprobe_saved_esp;
+
+ /*
+ * TBD: As Linus pointed out, gcc assumes that the callee
+ * owns the argument space and could overwrite it, e.g.
+ * tailcall optimization. So, to be absolutely safe
+ * we also save and restore enough stack bytes to cover
+ * the argument area.
+ */
+ memcpy(jprobes_stack, (kprobe_opcode_t *) addr, MIN_STACK_SIZE(addr));
+ regs->eflags &= ~IF_MASK;
+ regs->eip = (unsigned long)(jp->entry);
+ return 1;
+}
+
+void jprobe_return(void)
+{
+ preempt_enable_no_resched();
+ asm volatile (" xchgl %%ebx,%%esp \n"
+ " int3 \n"::"b"
+ (jprobe_saved_esp):"memory");
+}
+void jprobe_return_end(void)
+{
+};
+
+int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+ u8 *addr = (u8 *) (regs->eip - 1);
+ unsigned long stack_addr = (unsigned long)jprobe_saved_esp;
+ struct jprobe *jp = container_of(p, struct jprobe, kp);
+
+ if ((addr > (u8 *) jprobe_return) && (addr < (u8 *) jprobe_return_end)) {
+ if (®s->esp != jprobe_saved_esp) {
+ struct pt_regs *saved_regs =
+ container_of(jprobe_saved_esp, struct pt_regs, esp);
+ printk("current esp %p does not match saved esp %p\n",
+ ®s->esp, jprobe_saved_esp);
+ printk("Saved registers for jprobe %p\n", jp);
+ show_registers(saved_regs);
+ printk("Current registers\n");
+ show_registers(regs);
+ BUG();
+ }
+ *regs = jprobe_saved_regs;
+ memcpy((kprobe_opcode_t *) stack_addr, jprobes_stack,
+ MIN_STACK_SIZE(stack_addr));
+ return 1;
+ }
+ return 0;
+}
--- /dev/null
+/*
+ * machine_kexec.c - handle transition of Linux booting another kernel
+ * Copyright (C) 2002-2004 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/kexec.h>
+#include <linux/delay.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
+#include <asm/io.h>
+#include <asm/apic.h>
+#include <asm/cpufeature.h>
+
+static inline unsigned long read_cr3(void)
+{
+ unsigned long cr3;
+ asm volatile("movl %%cr3,%0": "=r"(cr3));
+ return cr3;
+}
+
+#define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
+
+#define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define L2_ATTR (_PAGE_PRESENT)
+
+#define LEVEL0_SIZE (1UL << 12UL)
+
+#ifndef CONFIG_X86_PAE
+#define LEVEL1_SIZE (1UL << 22UL)
+static u32 pgtable_level1[1024] PAGE_ALIGNED;
+
+static void identity_map_page(unsigned long address)
+{
+ unsigned long level1_index, level2_index;
+ u32 *pgtable_level2;
+
+ /* Find the current page table */
+ pgtable_level2 = __va(read_cr3());
+
+ /* Find the indexes of the physical address to identity map */
+ level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
+ level2_index = address / LEVEL1_SIZE;
+
+ /* Identity map the page table entry */
+ pgtable_level1[level1_index] = address | L0_ATTR;
+ pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
+
+ /* Flush the tlb so the new mapping takes effect.
+ * Global tlb entries are not flushed but that is not an issue.
+ */
+ load_cr3(pgtable_level2);
+}
+
+#else
+#define LEVEL1_SIZE (1UL << 21UL)
+#define LEVEL2_SIZE (1UL << 30UL)
+static u64 pgtable_level1[512] PAGE_ALIGNED;
+static u64 pgtable_level2[512] PAGE_ALIGNED;
+
+static void identity_map_page(unsigned long address)
+{
+ unsigned long level1_index, level2_index, level3_index;
+ u64 *pgtable_level3;
+
+ /* Find the current page table */
+ pgtable_level3 = __va(read_cr3());
+
+ /* Find the indexes of the physical address to identity map */
+ level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
+ level2_index = (address % LEVEL2_SIZE)/LEVEL1_SIZE;
+ level3_index = address / LEVEL2_SIZE;
+
+ /* Identity map the page table entry */
+ pgtable_level1[level1_index] = address | L0_ATTR;
+ pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
+ set_64bit(&pgtable_level3[level3_index], __pa(pgtable_level2) | L2_ATTR);
+
+ /* Flush the tlb so the new mapping takes effect.
+ * Global tlb entries are not flushed but that is not an issue.
+ */
+ load_cr3(pgtable_level3);
+}
+#endif
+
+
+static void set_idt(void *newidt, __u16 limit)
+{
+ unsigned char curidt[6];
+
+ /* ia32 supports unaliged loads & stores */
+ (*(__u16 *)(curidt)) = limit;
+ (*(__u32 *)(curidt +2)) = (unsigned long)(newidt);
+
+ __asm__ __volatile__ (
+ "lidt %0\n"
+ : "=m" (curidt)
+ );
+};
+
+
+static void set_gdt(void *newgdt, __u16 limit)
+{
+ unsigned char curgdt[6];
+
+ /* ia32 supports unaligned loads & stores */
+ (*(__u16 *)(curgdt)) = limit;
+ (*(__u32 *)(curgdt +2)) = (unsigned long)(newgdt);
+
+ __asm__ __volatile__ (
+ "lgdt %0\n"
+ : "=m" (curgdt)
+ );
+};
+
+static void load_segments(void)
+{
+#define __STR(X) #X
+#define STR(X) __STR(X)
+
+ __asm__ __volatile__ (
+ "\tljmp $"STR(__KERNEL_CS)",$1f\n"
+ "\t1:\n"
+ "\tmovl $"STR(__KERNEL_DS)",%eax\n"
+ "\tmovl %eax,%ds\n"
+ "\tmovl %eax,%es\n"
+ "\tmovl %eax,%fs\n"
+ "\tmovl %eax,%gs\n"
+ "\tmovl %eax,%ss\n"
+ );
+#undef STR
+#undef __STR
+}
+
+typedef asmlinkage void (*relocate_new_kernel_t)(
+ unsigned long indirection_page, unsigned long reboot_code_buffer,
+ unsigned long start_address, unsigned int has_pae);
+
+const extern unsigned char relocate_new_kernel[];
+extern void relocate_new_kernel_end(void);
+const extern unsigned int relocate_new_kernel_size;
+
+/*
+ * Do what every setup is needed on image and the
+ * reboot code buffer to allow us to avoid allocations
+ * later. Currently nothing.
+ */
+int machine_kexec_prepare(struct kimage *image)
+{
+ return 0;
+}
+
+void machine_kexec_cleanup(struct kimage *image)
+{
+}
+
+/*
+ * Do not allocate memory (or fail in any way) in machine_kexec().
+ * We are past the point of no return, committed to rebooting now.
+ */
+void machine_kexec(struct kimage *image)
+{
+ unsigned long indirection_page;
+ unsigned long reboot_code_buffer;
+ relocate_new_kernel_t rnk;
+
+ /* Interrupts aren't acceptable while we reboot */
+ local_irq_disable();
+
+ /* Compute some offsets */
+ reboot_code_buffer = page_to_pfn(image->control_code_page) << PAGE_SHIFT;
+ indirection_page = image->head & PAGE_MASK;
+
+ /* Set up an identity mapping for the reboot_code_buffer */
+ identity_map_page(reboot_code_buffer);
+
+ /* copy it out */
+ memcpy((void *)reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size);
+
+ /* The segment registers are funny things, they are
+ * automatically loaded from a table, in memory wherever you
+ * set them to a specific selector, but this table is never
+ * accessed again you set the segment to a different selector.
+ *
+ * The more common model is are caches where the behide
+ * the scenes work is done, but is also dropped at arbitrary
+ * times.
+ *
+ * I take advantage of this here by force loading the
+ * segments, before I zap the gdt with an invalid value.
+ */
+ load_segments();
+ /* The gdt & idt are now invalid.
+ * If you want to load them you must set up your own idt & gdt.
+ */
+ set_gdt(phys_to_virt(0),0);
+ set_idt(phys_to_virt(0),0);
+
+ /* now call it */
+ rnk = (relocate_new_kernel_t) reboot_code_buffer;
+ (*rnk)(indirection_page, reboot_code_buffer, image->start, cpu_has_pae);
+}
--- /dev/null
+/*
+ * relocate_kernel.S - put the kernel image in place to boot
+ * Copyright (C) 2002-2004 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <linux/linkage.h>
+
+ /*
+ * Must be relocatable PIC code callable as a C function, that once
+ * it starts can not use the previous processes stack.
+ */
+ .globl relocate_new_kernel
+relocate_new_kernel:
+ /* read the arguments and say goodbye to the stack */
+ movl 4(%esp), %ebx /* indirection_page */
+ movl 8(%esp), %ebp /* reboot_code_buffer */
+ movl 12(%esp), %edx /* start address */
+ movl 16(%esp), %ecx /* cpu_has_pae */
+
+ /* zero out flags, and disable interrupts */
+ pushl $0
+ popfl
+
+ /* set a new stack at the bottom of our page... */
+ lea 4096(%ebp), %esp
+
+ /* store the parameters back on the stack */
+ pushl %edx /* store the start address */
+
+ /* Set cr0 to a known state:
+ * 31 0 == Paging disabled
+ * 18 0 == Alignment check disabled
+ * 16 0 == Write protect disabled
+ * 3 0 == No task switch
+ * 2 0 == Don't do FP software emulation.
+ * 0 1 == Proctected mode enabled
+ */
+ movl %cr0, %eax
+ andl $~((1<<31)|(1<<18)|(1<<16)|(1<<3)|(1<<2)), %eax
+ orl $(1<<0), %eax
+ movl %eax, %cr0
+
+ /* clear cr4 if applicable */
+ testl %ecx, %ecx
+ jz 1f
+ /* Set cr4 to a known state:
+ * Setting everything to zero seems safe.
+ */
+ movl %cr4, %eax
+ andl $0, %eax
+ movl %eax, %cr4
+
+ jmp 1f
+1:
+
+ /* Flush the TLB (needed?) */
+ xorl %eax, %eax
+ movl %eax, %cr3
+
+ /* Do the copies */
+ cld
+0: /* top, read another word for the indirection page */
+ movl %ebx, %ecx
+ movl (%ebx), %ecx
+ addl $4, %ebx
+ testl $0x1, %ecx /* is it a destination page */
+ jz 1f
+ movl %ecx, %edi
+ andl $0xfffff000, %edi
+ jmp 0b
+1:
+ testl $0x2, %ecx /* is it an indirection page */
+ jz 1f
+ movl %ecx, %ebx
+ andl $0xfffff000, %ebx
+ jmp 0b
+1:
+ testl $0x4, %ecx /* is it the done indicator */
+ jz 1f
+ jmp 2f
+1:
+ testl $0x8, %ecx /* is it the source indicator */
+ jz 0b /* Ignore it otherwise */
+ movl %ecx, %esi /* For every source page do a copy */
+ andl $0xfffff000, %esi
+
+ movl $1024, %ecx
+ rep ; movsl
+ jmp 0b
+
+2:
+
+ /* To be certain of avoiding problems with self-modifying code
+ * I need to execute a serializing instruction here.
+ * So I flush the TLB, it's handy, and not processor dependent.
+ */
+ xorl %eax, %eax
+ movl %eax, %cr3
+
+ /* set all of the registers to known values */
+ /* leave %esp alone */
+
+ xorl %eax, %eax
+ xorl %ebx, %ebx
+ xorl %ecx, %ecx
+ xorl %edx, %edx
+ xorl %esi, %esi
+ xorl %edi, %edi
+ xorl %ebp, %ebp
+ ret
+relocate_new_kernel_end:
+
+ .globl relocate_new_kernel_size
+relocate_new_kernel_size:
+ .long relocate_new_kernel_end - relocate_new_kernel
--- /dev/null
+/*
+ * Linker script for vsyscall DSO. The vsyscall page is an ELF shared
+ * object prelinked to its virtual address, and with only one read-only
+ * segment (that fits in one page). This script controls its layout.
+ */
+#include <asm/asm_offsets.h>
+
+SECTIONS
+{
+ . = VSYSCALL_BASE + SIZEOF_HEADERS;
+
+ .hash : { *(.hash) } :text
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+
+ /* This linker script is used both with -r and with -shared.
+ For the layouts to match, we need to skip more than enough
+ space for the dynamic symbol table et al. If this amount
+ is insufficient, ld -shared will barf. Just increase it here. */
+ . = VSYSCALL_BASE + 0x400;
+
+ .text : { *(.text) } :text =0x90909090
+
+ .eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
+ .eh_frame : { KEEP (*(.eh_frame)) } :text
+ .dynamic : { *(.dynamic) } :text :dynamic
+ .useless : {
+ *(.got.plt) *(.got)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ } :text
+}
+
+/*
+ * We must supply the ELF program headers explicitly to get just one
+ * PT_LOAD segment, and set the flags explicitly to make segments read-only.
+ */
+PHDRS
+{
+ text PT_LOAD FILEHDR PHDRS FLAGS(5); /* PF_R|PF_X */
+ dynamic PT_DYNAMIC FLAGS(4); /* PF_R */
+ eh_frame_hdr 0x6474e550; /* PT_GNU_EH_FRAME, but ld doesn't match the name */
+}
+
+/*
+ * This controls what symbols we export from the DSO.
+ */
+VERSION
+{
+ LINUX_2.5 {
+ global:
+ __kernel_vsyscall;
+ __kernel_sigreturn;
+ __kernel_rt_sigreturn;
+
+ local: *;
+ };
+}
+
+/* The ELF entry point can be used to set the AT_SYSINFO value. */
+ENTRY(__kernel_vsyscall);
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+choice
+ prompt "Physical memory granularity"
+ default IA64_GRANULE_64MB
+
+config IA64_GRANULE_16MB
+ bool "16MB"
+ help
+ IA-64 identity-mapped regions use a large page size called "granules".
+
+ Select "16MB" for a small granule size.
+ Select "64MB" for a large granule size. This is the current default.
+
+config IA64_GRANULE_64MB
+ bool "64MB"
+ depends on !(IA64_GENERIC || IA64_HP_ZX1 || IA64_SGI_SN2)
+
+endchoice
+
+config IA64_PRINT_HAZARDS
+ bool "Print possible IA-64 dependency violations to console"
+ depends on DEBUG_KERNEL
+ help
+ Selecting this option prints more information for Illegal Dependency
+ Faults, that is, for Read-after-Write (RAW), Write-after-Write (WAW),
+ or Write-after-Read (WAR) violations. This option is ignored if you
+ are compiling for an Itanium A step processor
+ (CONFIG_ITANIUM_ASTEP_SPECIFIC). If you're unsure, select Y.
+
+config DISABLE_VHPT
+ bool "Disable VHPT"
+ depends on DEBUG_KERNEL
+ help
+ The Virtual Hash Page Table (VHPT) enhances virtual address
+ translation performance. Normally you want the VHPT active but you
+ can select this option to disable the VHPT for debugging. If you're
+ unsure, answer N.
+
+config IA64_DEBUG_CMPXCHG
+ bool "Turn on compare-and-exchange bug checking (slow!)"
+ depends on DEBUG_KERNEL
+ help
+ Selecting this option turns on bug checking for the IA-64
+ compare-and-exchange instructions. This is slow! Itaniums
+ from step B3 or later don't have this problem. If you're unsure,
+ select N.
+
+config IA64_DEBUG_IRQ
+ bool "Turn on irq debug checks (slow!)"
+ depends on DEBUG_KERNEL
+ help
+ Selecting this option turns on bug checking for the IA-64 irq_save
+ and restore instructions. It's useful for tracking down spinlock
+ problems, but slow! If you're unsure, select N.
+
+config SYSVIPC_COMPAT
+ bool
+ depends on COMPAT && SYSVIPC
+ default y
+
+endmenu
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.9-rc2
+# Tue Sep 28 13:26:53 2004
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_HOTPLUG=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+
+#
+# Processor type and features
+#
+CONFIG_IA64=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_TIME_INTERPOLATION=y
+CONFIG_EFI=y
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_ZX1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+# CONFIG_ITANIUM_BSTEP_SPECIFIC is not set
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_VIRTUAL_MEM_MAP is not set
+# CONFIG_IA64_CYCLONE is not set
+CONFIG_IOSAPIC=y
+CONFIG_FORCE_MAX_ZONEORDER=18
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_PREEMPT=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_COMPAT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+
+#
+# Firmware Drivers
+#
+CONFIG_EFI_VARS=y
+CONFIG_EFI_PCDP=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+
+#
+# Power management and ACPI
+#
+CONFIG_PM=y
+CONFIG_ACPI=y
+
+#
+# ACPI (Advanced Configuration and Power Interface) Support
+#
+CONFIG_ACPI_BOOT=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_FAN=m
+CONFIG_ACPI_PROCESSOR=m
+CONFIG_ACPI_THERMAL=m
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_BUS=y
+CONFIG_ACPI_POWER=y
+CONFIG_ACPI_PCI=y
+CONFIG_ACPI_SYSTEM=y
+
+#
+# Bus options (PCI, PCMCIA)
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# PCMCIA/CardBus support
+#
+# CONFIG_PCMCIA is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_SIZE=4096
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+CONFIG_BLK_DEV_IDEPCI=y
+CONFIG_IDEPCI_SHARE_IRQ=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=m
+# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_PIIX=m
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI Transport Attributes
+#
+CONFIG_SCSI_SPI_ATTRS=m
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA6322 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID5=m
+CONFIG_MD_RAID6=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_EEPRO100_PIO is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_ACPI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+CONFIG_AGP=m
+CONFIG_AGP_I460=m
+CONFIG_DRM=y
+# CONFIG_DRM_TDFX is not set
+CONFIG_DRM_R128=m
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_SIS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_HPET is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_SEQUENCER_OSS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_OPL3_LIB=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# PCI devices
+#
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CS46XX is not set
+CONFIG_SND_CS4281=m
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VX222 is not set
+
+#
+# ALSA USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_USX2Y is not set
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+
+#
+# USB support
+#
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+CONFIG_USB_UHCI_HCD=m
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BLUETOOTH_TTY=m
+CONFIG_USB_MIDI=m
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_RW_DETECT is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=m
+CONFIG_USB_HIDINPUT=y
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_TIGL is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_XFS_FS=y
+# CONFIG_XFS_RT is not set
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_SECURITY=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_DEVPTS_FS_XATTR=y
+CONFIG_DEVPTS_FS_SECURITY=y
+CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_TCP=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_IA64_GRANULE_16MB is not set
+CONFIG_IA64_GRANULE_64MB=y
+# CONFIG_IA64_PRINT_HAZARDS is not set
+# CONFIG_DISABLE_VHPT is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_SYSVIPC_COMPAT=y
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WHIRLPOOL is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.9-rc2
+# Tue Sep 28 09:03:25 2004
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+CONFIG_MODVERSIONS=y
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+
+#
+# Processor type and features
+#
+CONFIG_IA64=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_TIME_INTERPOLATION=y
+CONFIG_EFI=y
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_ZX1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+# CONFIG_NUMA is not set
+CONFIG_VIRTUAL_MEM_MAP=y
+CONFIG_IA64_CYCLONE=y
+CONFIG_IOSAPIC=y
+CONFIG_FORCE_MAX_ZONEORDER=18
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_PREEMPT is not set
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_COMPAT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+
+#
+# Firmware Drivers
+#
+CONFIG_EFI_VARS=y
+CONFIG_EFI_PCDP=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+
+#
+# Power management and ACPI
+#
+CONFIG_PM=y
+CONFIG_ACPI=y
+
+#
+# ACPI (Advanced Configuration and Power Interface) Support
+#
+CONFIG_ACPI_BOOT=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_FAN=m
+CONFIG_ACPI_PROCESSOR=m
+CONFIG_ACPI_THERMAL=m
+# CONFIG_ACPI_DEBUG is not set
+CONFIG_ACPI_BUS=y
+CONFIG_ACPI_POWER=y
+CONFIG_ACPI_PCI=y
+CONFIG_ACPI_SYSTEM=y
+
+#
+# Bus options (PCI, PCMCIA)
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# PCI Hotplug Support
+#
+CONFIG_HOTPLUG_PCI=m
+# CONFIG_HOTPLUG_PCI_FAKE is not set
+CONFIG_HOTPLUG_PCI_ACPI=m
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+
+#
+# PCMCIA/CardBus support
+#
+# CONFIG_PCMCIA is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_SIZE=4096
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+CONFIG_BLK_DEV_IDESCSI=m
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+CONFIG_BLK_DEV_CMD64X=y
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_PIIX=y
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INIA100 is not set
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_QLA2XXX=y
+CONFIG_SCSI_QLA21XX=m
+CONFIG_SCSI_QLA22XX=m
+CONFIG_SCSI_QLA2300=m
+CONFIG_SCSI_QLA2322=m
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA6322 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+# CONFIG_MD_RAID10 is not set
+CONFIG_MD_RAID5=m
+CONFIG_MD_RAID6=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+
+#
+# Fusion MPT device support
+#
+CONFIG_FUSION=y
+CONFIG_FUSION_MAX_SGE=40
+# CONFIG_FUSION_CTL is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK_DEV=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_RX is not set
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+CONFIG_NET_TULIP=y
+# CONFIG_DE2104X is not set
+CONFIG_TULIP=m
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_MMIO is not set
+# CONFIG_TULIP_NAPI is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_DM9102 is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=m
+# CONFIG_EEPRO100_PIO is not set
+CONFIG_E100=m
+# CONFIG_E100_NAPI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+CONFIG_TIGON3=y
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+CONFIG_NETCONSOLE=y
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+CONFIG_GAMEPORT=m
+CONFIG_SOUND_GAMEPORT=m
+# CONFIG_GAMEPORT_NS558 is not set
+# CONFIG_GAMEPORT_L4 is not set
+# CONFIG_GAMEPORT_EMU10K1 is not set
+# CONFIG_GAMEPORT_VORTEX is not set
+# CONFIG_GAMEPORT_FM801 is not set
+# CONFIG_GAMEPORT_CS461x is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_ACPI=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+CONFIG_AGP=m
+CONFIG_AGP_I460=m
+CONFIG_DRM=y
+CONFIG_DRM_TDFX=m
+CONFIG_DRM_R128=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_MGA=m
+CONFIG_DRM_SIS=m
+CONFIG_RAW_DRIVER=m
+CONFIG_HPET=y
+# CONFIG_HPET_RTC_IRQ is not set
+CONFIG_HPET_MMAP=y
+CONFIG_MAX_RAW_DEVS=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_EHCI_SPLIT_ISO is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_UHCI_HCD=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_RW_DETECT is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT=y
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_TIGL is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_XFS_FS=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_SECURITY is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_DIRECTIO=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_TCP=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMB_NLS_REMOTE="cp437"
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_POSIX is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_INFO is not set
+CONFIG_IA64_GRANULE_16MB=y
+# CONFIG_IA64_GRANULE_64MB is not set
+# CONFIG_IA64_PRINT_HAZARDS is not set
+# CONFIG_DISABLE_VHPT is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_SYSVIPC_COMPAT=y
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WHIRLPOOL is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
--- /dev/null
+/*
+ * File: mca_drv.c
+ * Purpose: Generic MCA handling layer
+ *
+ * Copyright (C) 2004 FUJITSU LIMITED
+ * Copyright (C) Hidetoshi Seto (seto.hidetoshi@jp.fujitsu.com)
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kallsyms.h>
+#include <linux/smp_lock.h>
+#include <linux/bootmem.h>
+#include <linux/acpi.h>
+#include <linux/timer.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/workqueue.h>
+#include <linux/mm.h>
+
+#include <asm/delay.h>
+#include <asm/machvec.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/sal.h>
+#include <asm/mca.h>
+
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+
+#include "mca_drv.h"
+
+/* max size of SAL error record (default) */
+static int sal_rec_max = 10000;
+
+/* from mca.c */
+static ia64_mca_sal_to_os_state_t *sal_to_os_handoff_state;
+static ia64_mca_os_to_sal_state_t *os_to_sal_handoff_state;
+
+/* from mca_drv_asm.S */
+extern void *mca_handler_bhhook(void);
+
+static spinlock_t mca_bh_lock = SPIN_LOCK_UNLOCKED;
+
+typedef enum {
+ MCA_IS_LOCAL = 0,
+ MCA_IS_GLOBAL = 1
+} mca_type_t;
+
+#define MAX_PAGE_ISOLATE 32
+
+static struct page *page_isolate[MAX_PAGE_ISOLATE];
+static int num_page_isolate = 0;
+
+typedef enum {
+ ISOLATE_NG = 0,
+ ISOLATE_OK = 1
+} isolate_status_t;
+
+/*
+ * This pool keeps pointers to the section part of SAL error record
+ */
+static struct {
+ slidx_list_t *buffer; /* section pointer list pool */
+ int cur_idx; /* Current index of section pointer list pool */
+ int max_idx; /* Maximum index of section pointer list pool */
+} slidx_pool;
+
+/**
+ * mca_page_isolate - isolate a poisoned page in order not to use it later
+ * @paddr: poisoned memory location
+ *
+ * Return value:
+ * ISOLATE_OK / ISOLATE_NG
+ */
+
+static isolate_status_t
+mca_page_isolate(unsigned long paddr)
+{
+ int i;
+ struct page *p;
+
+ /* whether physical address is valid or not */
+ if ( !ia64_phys_addr_valid(paddr) )
+ return ISOLATE_NG;
+
+ /* convert physical address to physical page number */
+ p = pfn_to_page(paddr>>PAGE_SHIFT);
+
+ /* check whether a page number have been already registered or not */
+ for( i = 0; i < num_page_isolate; i++ )
+ if( page_isolate[i] == p )
+ return ISOLATE_OK; /* already listed */
+
+ /* limitation check */
+ if( num_page_isolate == MAX_PAGE_ISOLATE )
+ return ISOLATE_NG;
+
+ /* kick pages having attribute 'SLAB' or 'Reserved' */
+ if( PageSlab(p) || PageReserved(p) )
+ return ISOLATE_NG;
+
+ /* add attribute 'Reserved' and register the page */
+ SetPageReserved(p);
+ page_isolate[num_page_isolate++] = p;
+
+ return ISOLATE_OK;
+}
+
+/**
+ * mca_hanlder_bh - Kill the process which occurred memory read error
+ * @paddr: poisoned address received from MCA Handler
+ */
+
+void
+mca_handler_bh(unsigned long paddr)
+{
+ printk(KERN_DEBUG "OS_MCA: process [pid: %d](%s) encounters MCA.\n",
+ current->pid, current->comm);
+
+ spin_lock(&mca_bh_lock);
+ if (mca_page_isolate(paddr) == ISOLATE_OK) {
+ printk(KERN_DEBUG "Page isolation: ( %lx ) success.\n", paddr);
+ } else {
+ printk(KERN_DEBUG "Page isolation: ( %lx ) failure.\n", paddr);
+ }
+ spin_unlock(&mca_bh_lock);
+
+ /* This process is about to be killed itself */
+ force_sig(SIGKILL, current);
+ schedule();
+}
+
+/**
+ * mca_make_peidx - Make index of processor error section
+ * @slpi: pointer to record of processor error section
+ * @peidx: pointer to index of processor error section
+ */
+
+static void
+mca_make_peidx(sal_log_processor_info_t *slpi, peidx_table_t *peidx)
+{
+ /*
+ * calculate the start address of
+ * "struct cpuid_info" and "sal_processor_static_info_t".
+ */
+ u64 total_check_num = slpi->valid.num_cache_check
+ + slpi->valid.num_tlb_check
+ + slpi->valid.num_bus_check
+ + slpi->valid.num_reg_file_check
+ + slpi->valid.num_ms_check;
+ u64 head_size = sizeof(sal_log_mod_error_info_t) * total_check_num
+ + sizeof(sal_log_processor_info_t);
+ u64 mid_size = slpi->valid.cpuid_info * sizeof(struct sal_cpuid_info);
+
+ peidx_head(peidx) = slpi;
+ peidx_mid(peidx) = (struct sal_cpuid_info *)
+ (slpi->valid.cpuid_info ? ((char*)slpi + head_size) : NULL);
+ peidx_bottom(peidx) = (sal_processor_static_info_t *)
+ (slpi->valid.psi_static_struct ?
+ ((char*)slpi + head_size + mid_size) : NULL);
+}
+
+/**
+ * mca_make_slidx - Make index of SAL error record
+ * @buffer: pointer to SAL error record
+ * @slidx: pointer to index of SAL error record
+ *
+ * Return value:
+ * 1 if record has platform error / 0 if not
+ */
+#define LOG_INDEX_ADD_SECT_PTR(sect, ptr) \
+ { slidx_list_t *hl = &slidx_pool.buffer[slidx_pool.cur_idx]; \
+ hl->hdr = ptr; \
+ list_add(&hl->list, &(sect)); \
+ slidx_pool.cur_idx = (slidx_pool.cur_idx + 1)%slidx_pool.max_idx; }
+
+static int
+mca_make_slidx(void *buffer, slidx_table_t *slidx)
+{
+ int platform_err = 0;
+ int record_len = ((sal_log_record_header_t*)buffer)->len;
+ u32 ercd_pos;
+ int sects;
+ sal_log_section_hdr_t *sp;
+
+ /*
+ * Initialize index referring current record
+ */
+ INIT_LIST_HEAD(&(slidx->proc_err));
+ INIT_LIST_HEAD(&(slidx->mem_dev_err));
+ INIT_LIST_HEAD(&(slidx->sel_dev_err));
+ INIT_LIST_HEAD(&(slidx->pci_bus_err));
+ INIT_LIST_HEAD(&(slidx->smbios_dev_err));
+ INIT_LIST_HEAD(&(slidx->pci_comp_err));
+ INIT_LIST_HEAD(&(slidx->plat_specific_err));
+ INIT_LIST_HEAD(&(slidx->host_ctlr_err));
+ INIT_LIST_HEAD(&(slidx->plat_bus_err));
+ INIT_LIST_HEAD(&(slidx->unsupported));
+
+ /*
+ * Extract a Record Header
+ */
+ slidx->header = buffer;
+
+ /*
+ * Extract each section records
+ * (arranged from "int ia64_log_platform_info_print()")
+ */
+ for (ercd_pos = sizeof(sal_log_record_header_t), sects = 0;
+ ercd_pos < record_len; ercd_pos += sp->len, sects++) {
+ sp = (sal_log_section_hdr_t *)((char*)buffer + ercd_pos);
+ if (!efi_guidcmp(sp->guid, SAL_PROC_DEV_ERR_SECT_GUID)) {
+ LOG_INDEX_ADD_SECT_PTR(slidx->proc_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_MEM_DEV_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->mem_dev_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_SEL_DEV_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->sel_dev_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_PCI_BUS_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->pci_bus_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->smbios_dev_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_PCI_COMP_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->pci_comp_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_SPECIFIC_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->plat_specific_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_HOST_CTLR_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->host_ctlr_err, sp);
+ } else if (!efi_guidcmp(sp->guid, SAL_PLAT_BUS_ERR_SECT_GUID)) {
+ platform_err = 1;
+ LOG_INDEX_ADD_SECT_PTR(slidx->plat_bus_err, sp);
+ } else {
+ LOG_INDEX_ADD_SECT_PTR(slidx->unsupported, sp);
+ }
+ }
+ slidx->n_sections = sects;
+
+ return platform_err;
+}
+
+/**
+ * init_record_index_pools - Initialize pool of lists for SAL record index
+ *
+ * Return value:
+ * 0 on Success / -ENOMEM on Failure
+ */
+static int
+init_record_index_pools(void)
+{
+ int i;
+ int rec_max_size; /* Maximum size of SAL error records */
+ int sect_min_size; /* Minimum size of SAL error sections */
+ /* minimum size table of each section */
+ static int sal_log_sect_min_sizes[] = {
+ sizeof(sal_log_processor_info_t) + sizeof(sal_processor_static_info_t),
+ sizeof(sal_log_mem_dev_err_info_t),
+ sizeof(sal_log_sel_dev_err_info_t),
+ sizeof(sal_log_pci_bus_err_info_t),
+ sizeof(sal_log_smbios_dev_err_info_t),
+ sizeof(sal_log_pci_comp_err_info_t),
+ sizeof(sal_log_plat_specific_err_info_t),
+ sizeof(sal_log_host_ctlr_err_info_t),
+ sizeof(sal_log_plat_bus_err_info_t),
+ };
+
+ /*
+ * MCA handler cannot allocate new memory on flight,
+ * so we preallocate enough memory to handle a SAL record.
+ *
+ * Initialize a handling set of slidx_pool:
+ * 1. Pick up the max size of SAL error records
+ * 2. Pick up the min size of SAL error sections
+ * 3. Allocate the pool as enough to 2 SAL records
+ * (now we can estimate the maxinum of section in a record.)
+ */
+
+ /* - 1 - */
+ rec_max_size = sal_rec_max;
+
+ /* - 2 - */
+ sect_min_size = sal_log_sect_min_sizes[0];
+ for (i = 1; i < sizeof sal_log_sect_min_sizes/sizeof(size_t); i++)
+ if (sect_min_size > sal_log_sect_min_sizes[i])
+ sect_min_size = sal_log_sect_min_sizes[i];
+
+ /* - 3 - */
+ slidx_pool.max_idx = (rec_max_size/sect_min_size) * 2 + 1;
+ slidx_pool.buffer = (slidx_list_t *) kmalloc(slidx_pool.max_idx * sizeof(slidx_list_t), GFP_KERNEL);
+
+ return slidx_pool.buffer ? 0 : -ENOMEM;
+}
+
+
+/*****************************************************************************
+ * Recovery functions *
+ *****************************************************************************/
+
+/**
+ * is_mca_global - Check whether this MCA is global or not
+ * @peidx: pointer of index of processor error section
+ * @pbci: pointer to pal_bus_check_info_t
+ *
+ * Return value:
+ * MCA_IS_LOCAL / MCA_IS_GLOBAL
+ */
+
+static mca_type_t
+is_mca_global(peidx_table_t *peidx, pal_bus_check_info_t *pbci)
+{
+ pal_processor_state_info_t *psp = (pal_processor_state_info_t*)peidx_psp(peidx);
+
+ /*
+ * PAL can request a rendezvous, if the MCA has a global scope.
+ * If "rz_always" flag is set, SAL requests MCA rendezvous
+ * in spite of global MCA.
+ * Therefore it is local MCA when rendezvous has not been requested.
+ * Failed to rendezvous, the system must be down.
+ */
+ switch (sal_to_os_handoff_state->imsto_rendez_state) {
+ case -1: /* SAL rendezvous unsuccessful */
+ return MCA_IS_GLOBAL;
+ case 0: /* SAL rendezvous not required */
+ return MCA_IS_LOCAL;
+ case 1: /* SAL rendezvous successful int */
+ case 2: /* SAL rendezvous successful int with init */
+ default:
+ break;
+ }
+
+ /*
+ * If One or more Cache/TLB/Reg_File/Uarch_Check is here,
+ * it would be a local MCA. (i.e. processor internal error)
+ */
+ if (psp->tc || psp->cc || psp->rc || psp->uc)
+ return MCA_IS_LOCAL;
+
+ /*
+ * Bus_Check structure with Bus_Check.ib (internal bus error) flag set
+ * would be a global MCA. (e.g. a system bus address parity error)
+ */
+ if (!pbci || pbci->ib)
+ return MCA_IS_GLOBAL;
+
+ /*
+ * Bus_Check structure with Bus_Check.eb (external bus error) flag set
+ * could be either a local MCA or a global MCA.
+ *
+ * Referring Bus_Check.bsi:
+ * 0: Unknown/unclassified
+ * 1: BERR#
+ * 2: BINIT#
+ * 3: Hard Fail
+ * (FIXME: Are these SGI specific or generic bsi values?)
+ */
+ if (pbci->eb)
+ switch (pbci->bsi) {
+ case 0:
+ /* e.g. a load from poisoned memory */
+ return MCA_IS_LOCAL;
+ case 1:
+ case 2:
+ case 3:
+ return MCA_IS_GLOBAL;
+ }
+
+ return MCA_IS_GLOBAL;
+}
+
+/**
+ * recover_from_read_error - Try to recover the errors which type are "read"s.
+ * @slidx: pointer of index of SAL error record
+ * @peidx: pointer of index of processor error section
+ * @pbci: pointer of pal_bus_check_info
+ *
+ * Return value:
+ * 1 on Success / 0 on Failure
+ */
+
+static int
+recover_from_read_error(slidx_table_t *slidx, peidx_table_t *peidx, pal_bus_check_info_t *pbci)
+{
+ sal_log_mod_error_info_t *smei;
+ pal_min_state_area_t *pmsa;
+ struct ia64_psr *psr1, *psr2;
+ ia64_fptr_t *mca_hdlr_bh = (ia64_fptr_t*)mca_handler_bhhook;
+
+ /* Is target address valid? */
+ if (!pbci->tv)
+ return 0;
+
+ /*
+ * cpu read or memory-mapped io read
+ *
+ * offending process affected process OS MCA do
+ * kernel mode kernel mode down system
+ * kernel mode user mode kill the process
+ * user mode kernel mode down system (*)
+ * user mode user mode kill the process
+ *
+ * (*) You could terminate offending user-mode process
+ * if (pbci->pv && pbci->pl != 0) *and* if you sure
+ * the process not have any locks of kernel.
+ */
+
+ psr1 =(struct ia64_psr *)&(peidx_minstate_area(peidx)->pmsa_ipsr);
+
+ /*
+ * Check the privilege level of interrupted context.
+ * If it is user-mode, then terminate affected process.
+ */
+ if (psr1->cpl != 0) {
+ smei = peidx_bus_check(peidx, 0);
+ if (smei->valid.target_identifier) {
+ /*
+ * setup for resume to bottom half of MCA,
+ * "mca_handler_bhhook"
+ */
+ pmsa = (pal_min_state_area_t *)(sal_to_os_handoff_state->pal_min_state | (6ul<<61));
+ /* pass to bhhook as 1st argument (gr8) */
+ pmsa->pmsa_gr[8-1] = smei->target_identifier;
+ /* set interrupted return address (but no use) */
+ pmsa->pmsa_br0 = pmsa->pmsa_iip;
+ /* change resume address to bottom half */
+ pmsa->pmsa_iip = mca_hdlr_bh->fp;
+ pmsa->pmsa_gr[1-1] = mca_hdlr_bh->gp;
+ /* set cpl with kernel mode */
+ psr2 = (struct ia64_psr *)&pmsa->pmsa_ipsr;
+ psr2->cpl = 0;
+ psr2->ri = 0;
+
+ return 1;
+ }
+
+ }
+
+ return 0;
+}
+
+/**
+ * recover_from_platform_error - Recover from platform error.
+ * @slidx: pointer of index of SAL error record
+ * @peidx: pointer of index of processor error section
+ * @pbci: pointer of pal_bus_check_info
+ *
+ * Return value:
+ * 1 on Success / 0 on Failure
+ */
+
+static int
+recover_from_platform_error(slidx_table_t *slidx, peidx_table_t *peidx, pal_bus_check_info_t *pbci)
+{
+ int status = 0;
+ pal_processor_state_info_t *psp = (pal_processor_state_info_t*)peidx_psp(peidx);
+
+ if (psp->bc && pbci->eb && pbci->bsi == 0) {
+ switch(pbci->type) {
+ case 1: /* partial read */
+ case 3: /* full line(cpu) read */
+ case 9: /* I/O space read */
+ status = recover_from_read_error(slidx, peidx, pbci);
+ break;
+ case 0: /* unknown */
+ case 2: /* partial write */
+ case 4: /* full line write */
+ case 5: /* implicit or explicit write-back operation */
+ case 6: /* snoop probe */
+ case 7: /* incoming or outgoing ptc.g */
+ case 8: /* write coalescing transactions */
+ case 10: /* I/O space write */
+ case 11: /* inter-processor interrupt message(IPI) */
+ case 12: /* interrupt acknowledge or external task priority cycle */
+ default:
+ break;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * recover_from_processor_error
+ * @platform: whether there are some platform error section or not
+ * @slidx: pointer of index of SAL error record
+ * @peidx: pointer of index of processor error section
+ * @pbci: pointer of pal_bus_check_info
+ *
+ * Return value:
+ * 1 on Success / 0 on Failure
+ */
+/*
+ * Later we try to recover when below all conditions are satisfied.
+ * 1. Only one processor error section is exist.
+ * 2. BUS_CHECK is exist and the others are not exist.(Except TLB_CHECK)
+ * 3. The entry of BUS_CHECK_INFO is 1.
+ * 4. "External bus error" flag is set and the others are not set.
+ */
+
+static int
+recover_from_processor_error(int platform, slidx_table_t *slidx, peidx_table_t *peidx, pal_bus_check_info_t *pbci)
+{
+ pal_processor_state_info_t *psp = (pal_processor_state_info_t*)peidx_psp(peidx);
+
+ /*
+ * We cannot recover errors with other than bus_check.
+ */
+ if (psp->cc || psp->rc || psp->uc)
+ return 0;
+
+ /*
+ * If there is no bus error, record is weird but we need not to recover.
+ */
+ if (psp->bc == 0 || pbci == NULL)
+ return 1;
+
+ /*
+ * Sorry, we cannot handle so many.
+ */
+ if (peidx_bus_check_num(peidx) > 1)
+ return 0;
+ /*
+ * Well, here is only one bus error.
+ */
+ if (pbci->ib || pbci->cc)
+ return 0;
+ if (pbci->eb && pbci->bsi > 0)
+ return 0;
+ if (psp->ci == 0)
+ return 0;
+
+ /*
+ * This is a local MCA and estimated as recoverble external bus error.
+ * (e.g. a load from poisoned memory)
+ * This means "there are some platform errors".
+ */
+ if (platform)
+ return recover_from_platform_error(slidx, peidx, pbci);
+ /*
+ * On account of strange SAL error record, we cannot recover.
+ */
+ return 0;
+}
+
+/**
+ * mca_try_to_recover - Try to recover from MCA
+ * @rec: pointer to a SAL error record
+ *
+ * Return value:
+ * 1 on Success / 0 on Failure
+ */
+
+static int
+mca_try_to_recover(void *rec,
+ ia64_mca_sal_to_os_state_t *sal_to_os_state,
+ ia64_mca_os_to_sal_state_t *os_to_sal_state)
+{
+ int platform_err;
+ int n_proc_err;
+ slidx_table_t slidx;
+ peidx_table_t peidx;
+ pal_bus_check_info_t pbci;
+
+ /* handoff state from/to mca.c */
+ sal_to_os_handoff_state = sal_to_os_state;
+ os_to_sal_handoff_state = os_to_sal_state;
+
+ /* Make index of SAL error record */
+ platform_err = mca_make_slidx(rec, &slidx);
+
+ /* Count processor error sections */
+ n_proc_err = slidx_count(&slidx, proc_err);
+
+ /* Now, OS can recover when there is one processor error section */
+ if (n_proc_err > 1)
+ return 0;
+ else if (n_proc_err == 0) {
+ /* Weird SAL record ... We need not to recover */
+
+ return 1;
+ }
+
+ /* Make index of processor error section */
+ mca_make_peidx((sal_log_processor_info_t*)slidx_first_entry(&slidx.proc_err)->hdr, &peidx);
+
+ /* Extract Processor BUS_CHECK[0] */
+ *((u64*)&pbci) = peidx_check_info(&peidx, bus_check, 0);
+
+ /* Check whether MCA is global or not */
+ if (is_mca_global(&peidx, &pbci))
+ return 0;
+
+ /* Try to recover a processor error */
+ return recover_from_processor_error(platform_err, &slidx, &peidx, &pbci);
+}
+
+/*
+ * =============================================================================
+ */
+
+int __init mca_external_handler_init(void)
+{
+ if (init_record_index_pools())
+ return -ENOMEM;
+
+ /* register external mca handlers */
+ if (ia64_reg_MCA_extension(mca_try_to_recover)){
+ printk(KERN_ERR "ia64_reg_MCA_extension failed.\n");
+ kfree(slidx_pool.buffer);
+ return -EFAULT;
+ }
+ return 0;
+}
+
+void __exit mca_external_handler_exit(void)
+{
+ /* unregister external mca handlers */
+ ia64_unreg_MCA_extension();
+ kfree(slidx_pool.buffer);
+}
+
+module_init(mca_external_handler_init);
+module_exit(mca_external_handler_exit);
+
+module_param(sal_rec_max, int, 0644);
+MODULE_PARM_DESC(sal_rec_max, "Max size of SAL error record");
+
+MODULE_DESCRIPTION("ia64 platform dependent mca handler driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * File: mca_drv.h
+ * Purpose: Define helpers for Generic MCA handling
+ *
+ * Copyright (C) 2004 FUJITSU LIMITED
+ * Copyright (C) Hidetoshi Seto (seto.hidetoshi@jp.fujitsu.com)
+ */
+/*
+ * Processor error section:
+ *
+ * +-sal_log_processor_info_t *info-------------+
+ * | sal_log_section_hdr_t header; |
+ * | ... |
+ * | sal_log_mod_error_info_t info[0]; |
+ * +-+----------------+-------------------------+
+ * | CACHE_CHECK | ^ num_cache_check v
+ * +----------------+
+ * | TLB_CHECK | ^ num_tlb_check v
+ * +----------------+
+ * | BUS_CHECK | ^ num_bus_check v
+ * +----------------+
+ * | REG_FILE_CHECK | ^ num_reg_file_check v
+ * +----------------+
+ * | MS_CHECK | ^ num_ms_check v
+ * +-struct cpuid_info *id----------------------+
+ * | regs[5]; |
+ * | reserved; |
+ * +-sal_processor_static_info_t *regs----------+
+ * | valid; |
+ * | ... |
+ * | fr[128]; |
+ * +--------------------------------------------+
+ */
+
+/* peidx: index of processor error section */
+typedef struct peidx_table {
+ sal_log_processor_info_t *info;
+ struct sal_cpuid_info *id;
+ sal_processor_static_info_t *regs;
+} peidx_table_t;
+
+#define peidx_head(p) (((p)->info))
+#define peidx_mid(p) (((p)->id))
+#define peidx_bottom(p) (((p)->regs))
+
+#define peidx_psp(p) (&(peidx_head(p)->proc_state_parameter))
+#define peidx_field_valid(p) (&(peidx_head(p)->valid))
+#define peidx_minstate_area(p) (&(peidx_bottom(p)->min_state_area))
+
+#define peidx_cache_check_num(p) (peidx_head(p)->valid.num_cache_check)
+#define peidx_tlb_check_num(p) (peidx_head(p)->valid.num_tlb_check)
+#define peidx_bus_check_num(p) (peidx_head(p)->valid.num_bus_check)
+#define peidx_reg_file_check_num(p) (peidx_head(p)->valid.num_reg_file_check)
+#define peidx_ms_check_num(p) (peidx_head(p)->valid.num_ms_check)
+
+#define peidx_cache_check_idx(p, n) (n)
+#define peidx_tlb_check_idx(p, n) (peidx_cache_check_idx(p, peidx_cache_check_num(p)) + n)
+#define peidx_bus_check_idx(p, n) (peidx_tlb_check_idx(p, peidx_tlb_check_num(p)) + n)
+#define peidx_reg_file_check_idx(p, n) (peidx_bus_check_idx(p, peidx_bus_check_num(p)) + n)
+#define peidx_ms_check_idx(p, n) (peidx_reg_file_check_idx(p, peidx_reg_file_check_num(p)) + n)
+
+#define peidx_mod_error_info(p, name, n) \
+({ int __idx = peidx_##name##_idx(p, n); \
+ sal_log_mod_error_info_t *__ret = NULL; \
+ if (peidx_##name##_num(p) > n) /*BUG*/ \
+ __ret = &(peidx_head(p)->info[__idx]); \
+ __ret; })
+
+#define peidx_cache_check(p, n) peidx_mod_error_info(p, cache_check, n)
+#define peidx_tlb_check(p, n) peidx_mod_error_info(p, tlb_check, n)
+#define peidx_bus_check(p, n) peidx_mod_error_info(p, bus_check, n)
+#define peidx_reg_file_check(p, n) peidx_mod_error_info(p, reg_file_check, n)
+#define peidx_ms_check(p, n) peidx_mod_error_info(p, ms_check, n)
+
+#define peidx_check_info(proc, name, n) \
+({ \
+ sal_log_mod_error_info_t *__info = peidx_mod_error_info(proc, name, n);\
+ u64 __temp = __info && __info->valid.check_info \
+ ? __info->check_info : 0; \
+ __temp; })
+
+/* slidx: index of SAL log error record */
+
+typedef struct slidx_list {
+ struct list_head list;
+ sal_log_section_hdr_t *hdr;
+} slidx_list_t;
+
+typedef struct slidx_table {
+ sal_log_record_header_t *header;
+ int n_sections; /* # of section headers */
+ struct list_head proc_err;
+ struct list_head mem_dev_err;
+ struct list_head sel_dev_err;
+ struct list_head pci_bus_err;
+ struct list_head smbios_dev_err;
+ struct list_head pci_comp_err;
+ struct list_head plat_specific_err;
+ struct list_head host_ctlr_err;
+ struct list_head plat_bus_err;
+ struct list_head unsupported; /* list of unsupported sections */
+} slidx_table_t;
+
+#define slidx_foreach_entry(pos, head) \
+ list_for_each_entry(pos, head, list)
+#define slidx_first_entry(head) \
+ (((head)->next != (head)) ? list_entry((head)->next, typeof(slidx_list_t), list) : NULL)
+#define slidx_count(slidx, sec) \
+({ int __count = 0; \
+ slidx_list_t *__pos; \
+ slidx_foreach_entry(__pos, &((slidx)->sec)) { __count++; }\
+ __count; })
+
--- /dev/null
+/*
+ * File: mca_drv_asm.S
+ * Purpose: Assembly portion of Generic MCA handling
+ *
+ * Copyright (C) 2004 FUJITSU LIMITED
+ * Copyright (C) Hidetoshi Seto (seto.hidetoshi@jp.fujitsu.com)
+ */
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asmmacro.h>
+#include <asm/processor.h>
+
+GLOBAL_ENTRY(mca_handler_bhhook)
+ invala // clear RSE ?
+ ;; //
+ cover //
+ ;; //
+ clrrrb //
+ ;;
+ alloc r16=ar.pfs,0,2,1,0 // make a new frame
+ ;;
+ mov r13=IA64_KR(CURRENT) // current task pointer
+ ;;
+ adds r12=IA64_TASK_THREAD_KSP_OFFSET,r13
+ ;;
+ ld8 r12=[r12] // stack pointer
+ ;;
+ mov loc0=r16
+ movl loc1=mca_handler_bh // recovery C function
+ ;;
+ mov out0=r8 // poisoned address
+ mov b6=loc1
+ ;;
+ mov loc1=rp
+ ;;
+ br.call.sptk.many rp=b6 // not return ...
+ ;;
+ mov ar.pfs=loc0
+ mov rp=loc1
+ ;;
+ mov r8=r0
+ br.ret.sptk.many rp
+ ;;
+END(mca_handler_bhhook)
--- /dev/null
+/**
+ * @file perfmon.c
+ *
+ * @remark Copyright 2003 OProfile authors
+ * @remark Read the file COPYING
+ *
+ * @author John Levon <levon@movementarian.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/oprofile.h>
+#include <linux/sched.h>
+#include <asm/perfmon.h>
+#include <asm/ptrace.h>
+#include <asm/errno.h>
+
+static int allow_ints;
+
+static int
+perfmon_handler(struct task_struct *task, void *buf, pfm_ovfl_arg_t *arg,
+ struct pt_regs *regs, unsigned long stamp)
+{
+ int cpu = smp_processor_id();
+ unsigned long eip = instruction_pointer(regs);
+ int event = arg->pmd_eventid;
+
+ arg->ovfl_ctrl.bits.reset_ovfl_pmds = 1;
+
+ /* the owner of the oprofile event buffer may have exited
+ * without perfmon being shutdown (e.g. SIGSEGV)
+ */
+ if (allow_ints)
+ oprofile_add_sample(eip, !user_mode(regs), event, cpu);
+ return 0;
+}
+
+
+static int perfmon_start(void)
+{
+ allow_ints = 1;
+ return 0;
+}
+
+
+static void perfmon_stop(void)
+{
+ allow_ints = 0;
+}
+
+
+#define OPROFILE_FMT_UUID { \
+ 0x77, 0x7a, 0x6e, 0x61, 0x20, 0x65, 0x73, 0x69, 0x74, 0x6e, 0x72, 0x20, 0x61, 0x65, 0x0a, 0x6c }
+
+static pfm_buffer_fmt_t oprofile_fmt = {
+ .fmt_name = "oprofile_format",
+ .fmt_uuid = OPROFILE_FMT_UUID,
+ .fmt_handler = perfmon_handler,
+};
+
+
+static char * get_cpu_type(void)
+{
+ __u8 family = local_cpu_data->family;
+
+ switch (family) {
+ case 0x07:
+ return "ia64/itanium";
+ case 0x1f:
+ return "ia64/itanium2";
+ default:
+ return "ia64/ia64";
+ }
+}
+
+
+/* all the ops are handled via userspace for IA64 perfmon */
+static struct oprofile_operations perfmon_ops = {
+ .start = perfmon_start,
+ .stop = perfmon_stop,
+};
+
+static int using_perfmon;
+
+int perfmon_init(struct oprofile_operations ** ops)
+{
+ int ret = pfm_register_buffer_fmt(&oprofile_fmt);
+ if (ret)
+ return -ENODEV;
+
+ perfmon_ops.cpu_type = get_cpu_type();
+ *ops = &perfmon_ops;
+ using_perfmon = 1;
+ printk(KERN_INFO "oprofile: using perfmon.\n");
+ return 0;
+}
+
+
+void perfmon_exit(void)
+{
+ if (!using_perfmon)
+ return;
+
+ pfm_unregister_buffer_fmt(oprofile_fmt.fmt_uuid);
+}
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * SGI Altix topology and hardware performance monitoring API.
+ * Mark Goodwin <markgw@sgi.com>.
+ *
+ * Creates /proc/sgi_sn/sn_topology (read-only) to export
+ * info about Altix nodes, routers, CPUs and NumaLink
+ * interconnection/topology.
+ *
+ * Also creates a dynamic misc device named "sn_hwperf"
+ * that supports an ioctl interface to call down into SAL
+ * to discover hw objects, topology and to read/write
+ * memory mapped registers, e.g. for performance monitoring.
+ * The "sn_hwperf" device is registered only after the procfs
+ * file is first opened, i.e. only if/when it's needed.
+ *
+ * This API is used by SGI Performance Co-Pilot and other
+ * tools, see http://oss.sgi.com/projects/pcp
+ */
+
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/seq_file.h>
+#include <linux/miscdevice.h>
+#include <linux/cpumask.h>
+#include <linux/smp_lock.h>
+#include <asm/processor.h>
+#include <asm/topology.h>
+#include <asm/smp.h>
+#include <asm/semaphore.h>
+#include <asm/segment.h>
+#include <asm/uaccess.h>
+#include <asm-ia64/sal.h>
+#include <asm-ia64/sn/sn_sal.h>
+#include <asm-ia64/sn/sn2/sn_hwperf.h>
+
+static void *sn_hwperf_salheap = NULL;
+static int sn_hwperf_obj_cnt = 0;
+static nasid_t sn_hwperf_master_nasid = INVALID_NASID;
+static int sn_hwperf_init(void);
+static DECLARE_MUTEX(sn_hwperf_init_mutex);
+
+static int sn_hwperf_enum_objects(int *nobj, struct sn_hwperf_object_info **ret)
+{
+ int e;
+ u64 sz;
+ struct sn_hwperf_object_info *objbuf = NULL;
+
+ if ((e = sn_hwperf_init()) < 0) {
+ printk("sn_hwperf_init failed: err %d\n", e);
+ goto out;
+ }
+
+ sz = sn_hwperf_obj_cnt * sizeof(struct sn_hwperf_object_info);
+ if ((objbuf = (struct sn_hwperf_object_info *) vmalloc(sz)) == NULL) {
+ printk("sn_hwperf_enum_objects: vmalloc(%d) failed\n", (int)sz);
+ e = -ENOMEM;
+ goto out;
+ }
+
+ e = ia64_sn_hwperf_op(sn_hwperf_master_nasid, SN_HWPERF_ENUM_OBJECTS,
+ 0, sz, (u64) objbuf, 0, 0, NULL);
+ if (e != SN_HWPERF_OP_OK) {
+ e = -EINVAL;
+ vfree(objbuf);
+ }
+
+out:
+ *nobj = sn_hwperf_obj_cnt;
+ *ret = objbuf;
+ return e;
+}
+
+static int sn_hwperf_geoid_to_cnode(char *location)
+{
+ int cnode;
+ int mod, slot, slab;
+ int cmod, cslot, cslab;
+
+ if (sscanf(location, "%03dc%02d#%d", &mod, &slot, &slab) != 3)
+ return -1;
+ for (cnode = 0; cnode < numnodes; cnode++) {
+ /* XXX: need a better way than this ... */
+ if (sscanf(NODEPDA(cnode)->hwg_node_name,
+ "hw/module/%03dc%02d/slab/%d", &cmod, &cslot, &cslab) == 3) {
+ if (mod == cmod && slot == cslot && slab == cslab)
+ break;
+ }
+ }
+
+ return cnode < numnodes ? cnode : -1;
+}
+
+static int sn_hwperf_obj_to_cnode(struct sn_hwperf_object_info * obj)
+{
+ if (!obj->sn_hwp_this_part)
+ return -1;
+ return sn_hwperf_geoid_to_cnode(obj->location);
+}
+
+static int sn_hwperf_generic_ordinal(struct sn_hwperf_object_info *obj,
+ struct sn_hwperf_object_info *objs)
+{
+ int ordinal;
+ struct sn_hwperf_object_info *p;
+
+ for (ordinal=0, p=objs; p != obj; p++) {
+ if (SN_HWPERF_FOREIGN(p))
+ continue;
+ if (p->location[3] == obj->location[3])
+ ordinal++;
+ }
+
+ return ordinal;
+}
+
+#ifndef MODULE_IOBRICK
+/* this will be available when ioif TIO support is added */
+#define MODULE_IOBRICK (MODULE_OPUSBRICK+1)
+#endif
+
+static const char *sn_hwperf_get_brickname(struct sn_hwperf_object_info *obj,
+ struct sn_hwperf_object_info *objs, int *ordinal)
+{
+ int i;
+ const char *objtype = NULL;
+
+ for (i=0; i < MAX_BRICK_TYPES; i++) {
+ if (brick_types[i] != obj->location[3])
+ continue;
+ switch (i) {
+ case MODULE_CBRICK:
+ objtype = "node";
+ *ordinal = sn_hwperf_obj_to_cnode(obj); /* cnodeid */
+ break;
+
+ case MODULE_RBRICK:
+ objtype = "router";
+ *ordinal = sn_hwperf_generic_ordinal(obj, objs);
+ break;
+
+ case MODULE_IOBRICK:
+ objtype = "ionode";
+ *ordinal = sn_hwperf_generic_ordinal(obj, objs);
+ break;
+ }
+ break;
+ }
+
+ if (i == MAX_BRICK_TYPES) {
+ objtype = "other";
+ *ordinal = sn_hwperf_generic_ordinal(obj, objs);
+ }
+
+ return objtype;
+}
+
+static int sn_topology_show(struct seq_file *s, void *d)
+{
+ int sz;
+ int pt;
+ int e;
+ int i;
+ int j;
+ const char *brickname;
+ int ordinal;
+ cpumask_t cpumask;
+ char slice;
+ struct cpuinfo_ia64 *c;
+ struct sn_hwperf_port_info *ptdata;
+ struct sn_hwperf_object_info *p;
+ struct sn_hwperf_object_info *obj = d; /* this object */
+ struct sn_hwperf_object_info *objs = s->private; /* all objects */
+
+ if (obj == objs) {
+ seq_printf(s, "# sn_topology version 1\n");
+ seq_printf(s, "# objtype ordinal location partition"
+ " [attribute value [, ...]]\n");
+ }
+
+ if (SN_HWPERF_FOREIGN(obj)) {
+ /* private in another partition: not interesting */
+ return 0;
+ }
+
+ for (i = 0; obj->name[i]; i++) {
+ if (obj->name[i] == ' ')
+ obj->name[i] = '_';
+ }
+
+ brickname = sn_hwperf_get_brickname(obj, objs, &ordinal);
+ seq_printf(s, "%s %d %s %s asic %s", brickname, ordinal, obj->location,
+ obj->sn_hwp_this_part ? "local" : "shared", obj->name);
+
+ if (obj->location[3] != 'c')
+ seq_putc(s, '\n');
+ else {
+ seq_printf(s, ", nasid 0x%x", cnodeid_to_nasid(ordinal));
+ for (i=0; i < numnodes; i++) {
+ seq_printf(s, i ? ":%d" : ", dist %d",
+ node_distance(ordinal, i));
+ }
+ seq_putc(s, '\n');
+
+ /*
+ * CPUs on this node
+ */
+ cpumask = node_to_cpumask(ordinal);
+ for_each_online_cpu(i) {
+ if (cpu_isset(i, cpumask)) {
+ slice = 'a' + cpuid_to_slice(i);
+ c = cpu_data(i);
+ seq_printf(s, "cpu %d %s%c local"
+ " freq %luMHz, arch ia64",
+ i, obj->location, slice,
+ c->proc_freq / 1000000);
+ for_each_online_cpu(j) {
+ seq_printf(s, j ? ":%d" : ", dist %d",
+ node_distance(
+ cpuid_to_cnodeid(i),
+ cpuid_to_cnodeid(j)));
+ }
+ seq_putc(s, '\n');
+ }
+ }
+ }
+
+ if (obj->ports) {
+ /*
+ * numalink ports
+ */
+ sz = obj->ports * sizeof(struct sn_hwperf_port_info);
+ if ((ptdata = vmalloc(sz)) == NULL)
+ return -ENOMEM;
+ e = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
+ SN_HWPERF_ENUM_PORTS, obj->id, sz,
+ (u64) ptdata, 0, 0, NULL);
+ if (e != SN_HWPERF_OP_OK)
+ return -EINVAL;
+ for (ordinal=0, p=objs; p != obj; p++) {
+ if (!SN_HWPERF_FOREIGN(p))
+ ordinal += p->ports;
+ }
+ for (pt = 0; pt < obj->ports; pt++) {
+ for (p = objs, i = 0; i < sn_hwperf_obj_cnt; i++, p++) {
+ if (ptdata[pt].conn_id == p->id) {
+ break;
+ }
+ }
+ if (i >= sn_hwperf_obj_cnt)
+ continue;
+ seq_printf(s, "numalink %d %s-%d",
+ ordinal+pt, obj->location, ptdata[pt].port);
+
+ if (obj->sn_hwp_this_part && p->sn_hwp_this_part)
+ /* both ends local to this partition */
+ seq_puts(s, " local");
+ else if (!obj->sn_hwp_this_part && !p->sn_hwp_this_part)
+ /* both ends of the link in foreign partiton */
+ seq_puts(s, " foreign");
+ else
+ /* link straddles a partition */
+ seq_puts(s, " shared");
+
+ /*
+ * Unlikely, but strictly should query the LLP config
+ * registers because an NL4R can be configured to run
+ * NL3 protocol, even when not talking to an NL3 router.
+ * Ditto for node-node.
+ */
+ seq_printf(s, " endpoint %s-%d, protocol %s\n",
+ p->location, ptdata[pt].conn_port,
+ strcmp(obj->name, "NL3Router") == 0 ||
+ strcmp(p->name, "NL3Router") == 0 ?
+ "LLP3" : "LLP4");
+ }
+ vfree(ptdata);
+ }
+
+ return 0;
+}
+
+static void *sn_topology_start(struct seq_file *s, loff_t * pos)
+{
+ struct sn_hwperf_object_info *objs = s->private;
+
+ if (*pos < sn_hwperf_obj_cnt)
+ return (void *)(objs + *pos);
+
+ return NULL;
+}
+
+static void *sn_topology_next(struct seq_file *s, void *v, loff_t * pos)
+{
+ ++*pos;
+ return sn_topology_start(s, pos);
+}
+
+static void sn_topology_stop(struct seq_file *m, void *v)
+{
+ return;
+}
+
+/*
+ * /proc/sgi_sn/sn_topology, read-only using seq_file
+ */
+static struct seq_operations sn_topology_seq_ops = {
+ .start = sn_topology_start,
+ .next = sn_topology_next,
+ .stop = sn_topology_stop,
+ .show = sn_topology_show
+};
+
+struct sn_hwperf_op_info {
+ u64 op;
+ struct sn_hwperf_ioctl_args *a;
+ void *p;
+ int *v0;
+ int ret;
+};
+
+static void sn_hwperf_call_sal(void *info)
+{
+ struct sn_hwperf_op_info *op_info = info;
+ int r;
+
+ r = ia64_sn_hwperf_op(sn_hwperf_master_nasid, op_info->op,
+ op_info->a->arg, op_info->a->sz,
+ (u64) op_info->p, 0, 0, op_info->v0);
+ op_info->ret = r;
+}
+
+static int sn_hwperf_op_cpu(struct sn_hwperf_op_info *op_info)
+{
+ u32 cpu;
+ u32 use_ipi;
+ int r = 0;
+ cpumask_t save_allowed;
+
+ cpu = (op_info->a->arg & SN_HWPERF_ARG_CPU_MASK) >> 32;
+ use_ipi = op_info->a->arg & SN_HWPERF_ARG_USE_IPI_MASK;
+ op_info->a->arg &= SN_HWPERF_ARG_OBJID_MASK;
+
+ if (cpu != SN_HWPERF_ARG_ANY_CPU) {
+ if (cpu >= num_online_cpus() || !cpu_online(cpu)) {
+ r = -EINVAL;
+ goto out;
+ }
+ }
+
+ if (cpu == SN_HWPERF_ARG_ANY_CPU || cpu == get_cpu()) {
+ /* don't care, or already on correct cpu */
+ sn_hwperf_call_sal(op_info);
+ }
+ else {
+ if (use_ipi) {
+ /* use an interprocessor interrupt to call SAL */
+ smp_call_function_single(cpu, sn_hwperf_call_sal,
+ op_info, 1, 1);
+ }
+ else {
+ /* migrate the task before calling SAL */
+ save_allowed = current->cpus_allowed;
+ set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ sn_hwperf_call_sal(op_info);
+ set_cpus_allowed(current, save_allowed);
+ }
+ }
+ r = op_info->ret;
+
+out:
+ return r;
+}
+
+/*
+ * ioctl for "sn_hwperf" misc device
+ */
+static int
+sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, u64 arg)
+{
+ struct sn_hwperf_ioctl_args a;
+ struct cpuinfo_ia64 *cdata;
+ struct sn_hwperf_object_info *objs;
+ struct sn_hwperf_object_info *cpuobj;
+ struct sn_hwperf_op_info op_info;
+ void *p = NULL;
+ int nobj;
+ char slice;
+ int node;
+ int r;
+ int v0;
+ int i;
+ int j;
+
+ unlock_kernel();
+
+ /* only user requests are allowed here */
+ if ((op & SN_HWPERF_OP_MASK) < 10) {
+ r = -EINVAL;
+ goto error;
+ }
+ r = copy_from_user(&a, (const void *)arg,
+ sizeof(struct sn_hwperf_ioctl_args));
+ if (r != 0) {
+ r = -EFAULT;
+ goto error;
+ }
+
+ /*
+ * Allocate memory to hold a kernel copy of the user buffer. The
+ * buffer contents are either copied in or out (or both) of user
+ * space depending on the flags encoded in the requested operation.
+ */
+ if (a.ptr) {
+ p = vmalloc(a.sz);
+ if (!p) {
+ r = -ENOMEM;
+ goto error;
+ }
+ }
+
+ if (op & SN_HWPERF_OP_MEM_COPYIN) {
+ r = copy_from_user(p, (const void *)a.ptr, a.sz);
+ if (r != 0) {
+ r = -EFAULT;
+ goto error;
+ }
+ }
+
+ switch (op) {
+ case SN_HWPERF_GET_CPU_INFO:
+ if (a.sz == sizeof(u64)) {
+ /* special case to get size needed */
+ *(u64 *) p = (u64) num_online_cpus() *
+ sizeof(struct sn_hwperf_object_info);
+ } else
+ if (a.sz < num_online_cpus() * sizeof(struct sn_hwperf_object_info)) {
+ r = -ENOMEM;
+ goto error;
+ } else
+ if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) {
+ memset(p, 0, a.sz);
+ for (i = 0; i < nobj; i++) {
+ node = sn_hwperf_obj_to_cnode(objs + i);
+ for_each_online_cpu(j) {
+ if (node != cpu_to_node(j))
+ continue;
+ cpuobj = (struct sn_hwperf_object_info *) p + j;
+ slice = 'a' + cpuid_to_slice(j);
+ cdata = cpu_data(j);
+ cpuobj->id = j;
+ snprintf(cpuobj->name,
+ sizeof(cpuobj->name),
+ "CPU %luMHz %s",
+ cdata->proc_freq / 1000000,
+ cdata->vendor);
+ snprintf(cpuobj->location,
+ sizeof(cpuobj->location),
+ "%s%c", objs[i].location,
+ slice);
+ }
+ }
+
+ vfree(objs);
+ }
+ break;
+
+ case SN_HWPERF_GET_NODE_NASID:
+ if (a.sz != sizeof(u64) ||
+ (node = a.arg) < 0 || node >= numnodes) {
+ r = -EINVAL;
+ goto error;
+ }
+ *(u64 *)p = (u64)cnodeid_to_nasid(node);
+ break;
+
+ case SN_HWPERF_GET_OBJ_NODE:
+ if (a.sz != sizeof(u64) || a.arg < 0) {
+ r = -EINVAL;
+ goto error;
+ }
+ if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) {
+ if (a.arg >= nobj) {
+ r = -EINVAL;
+ vfree(objs);
+ goto error;
+ }
+ if (objs[(i = a.arg)].id != a.arg) {
+ for (i = 0; i < nobj; i++) {
+ if (objs[i].id == a.arg)
+ break;
+ }
+ }
+ if (i == nobj) {
+ r = -EINVAL;
+ vfree(objs);
+ goto error;
+ }
+ *(u64 *)p = (u64)sn_hwperf_obj_to_cnode(objs + i);
+ vfree(objs);
+ }
+ break;
+
+ case SN_HWPERF_GET_MMRS:
+ case SN_HWPERF_SET_MMRS:
+ case SN_HWPERF_OBJECT_DISTANCE:
+ op_info.p = p;
+ op_info.a = &a;
+ op_info.v0 = &v0;
+ op_info.op = op;
+ r = sn_hwperf_op_cpu(&op_info);
+ break;
+
+ default:
+ /* all other ops are a direct SAL call */
+ r = ia64_sn_hwperf_op(sn_hwperf_master_nasid, op,
+ a.arg, a.sz, (u64) p, 0, 0, &v0);
+ a.v0 = v0;
+ break;
+ }
+
+ if (op & SN_HWPERF_OP_MEM_COPYOUT) {
+ r = copy_to_user((void *)a.ptr, p, a.sz);
+ if (r != 0) {
+ r = -EFAULT;
+ goto error;
+ }
+ }
+
+error:
+ if (p)
+ vfree(p);
+
+ lock_kernel();
+ return r;
+}
+
+static struct file_operations sn_hwperf_fops = {
+ .ioctl = sn_hwperf_ioctl,
+};
+
+static struct miscdevice sn_hwperf_dev = {
+ MISC_DYNAMIC_MINOR,
+ "sn_hwperf",
+ &sn_hwperf_fops
+};
+
+static int sn_hwperf_init(void)
+{
+ u64 v;
+ int salr;
+ int e = 0;
+
+ /* single threaded, once-only initialization */
+ down(&sn_hwperf_init_mutex);
+ if (sn_hwperf_salheap) {
+ up(&sn_hwperf_init_mutex);
+ return e;
+ }
+
+ /*
+ * The PROM code needs a fixed reference node. For convenience the
+ * same node as the console I/O is used.
+ */
+ sn_hwperf_master_nasid = (nasid_t) ia64_sn_get_console_nasid();
+
+ /*
+ * Request the needed size and install the PROM scratch area.
+ * The PROM keeps various tracking bits in this memory area.
+ */
+ salr = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
+ (u64) SN_HWPERF_GET_HEAPSIZE, 0,
+ (u64) sizeof(u64), (u64) &v, 0, 0, NULL);
+ if (salr != SN_HWPERF_OP_OK) {
+ e = -EINVAL;
+ goto out;
+ }
+
+ if ((sn_hwperf_salheap = vmalloc(v)) == NULL) {
+ e = -ENOMEM;
+ goto out;
+ }
+ salr = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
+ SN_HWPERF_INSTALL_HEAP, 0, v,
+ (u64) sn_hwperf_salheap, 0, 0, NULL);
+ if (salr != SN_HWPERF_OP_OK) {
+ e = -EINVAL;
+ goto out;
+ }
+
+ salr = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
+ SN_HWPERF_OBJECT_COUNT, 0,
+ sizeof(u64), (u64) &v, 0, 0, NULL);
+ if (salr != SN_HWPERF_OP_OK) {
+ e = -EINVAL;
+ goto out;
+ }
+ sn_hwperf_obj_cnt = (int)v;
+
+out:
+ if (e < 0 && sn_hwperf_salheap) {
+ vfree(sn_hwperf_salheap);
+ sn_hwperf_salheap = NULL;
+ sn_hwperf_obj_cnt = 0;
+ }
+
+ if (!e) {
+ /*
+ * Register a dynamic misc device for ioctl. Platforms
+ * supporting hotplug will create /dev/sn_hwperf, else
+ * user can to look up the minor number in /proc/misc.
+ */
+ if ((e = misc_register(&sn_hwperf_dev)) != 0) {
+ printk(KERN_ERR "sn_hwperf_init: misc register "
+ "for \"sn_hwperf\" failed, err %d\n", e);
+ }
+ }
+
+ up(&sn_hwperf_init_mutex);
+ return e;
+}
+
+int sn_topology_open(struct inode *inode, struct file *file)
+{
+ int e;
+ struct seq_file *seq;
+ struct sn_hwperf_object_info *objbuf;
+ int nobj;
+
+ if ((e = sn_hwperf_enum_objects(&nobj, &objbuf)) == 0) {
+ e = seq_open(file, &sn_topology_seq_ops);
+ seq = file->private_data;
+ seq->private = objbuf;
+ }
+
+ return e;
+}
+
+int sn_topology_release(struct inode *inode, struct file *file)
+{
+ struct seq_file *seq = file->private_data;
+
+ if (seq->private)
+ vfree(seq->private);
+ return seq_release(inode, file);
+}
--- /dev/null
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+mainmenu "Linux Kernel Configuration"
+
+config M32R
+ bool
+ default y
+
+config SBUS
+ bool
+
+config UID16
+ bool
+ default y
+
+config GENERIC_ISA_DMA
+ bool
+ default y
+
+source "init/Kconfig"
+
+
+menu "Processor type and features"
+
+choice
+ prompt "Platform Type"
+ default PLAT_MAPPI
+
+config PLAT_MAPPI
+ bool "Mappi-I"
+ help
+ The Mappi-I is an FPGA board for SOC (System-On-a-Chip) prototyping.
+ You can operate a Linux system on this board by using an M32R
+ softmacro core, which is a fully-synthesizable functional model
+ described in Verilog-HDL.
+
+ The Mappi-I board was the first platform, which had been used
+ to port and develop a Linux system for the M32R processor.
+ Currently, the Mappi-II, an heir to the Mappi-I, is available.
+
+config PLAT_USRV
+ bool "uServer"
+
+config PLAT_M32700UT
+ bool "M32700UT"
+ help
+ The M3T-M32700UT is an evaluation board based on uT-Engine
+ specification. This board has an M32700 (Chaos) evaluation chip.
+ You can say Y for SMP, because the M32700 is a single chip
+ multiprocessor.
+
+config PLAT_OPSPUT
+ bool "OPSPUT"
+ help
+ The OPSPUT is an evaluation board based on uT-Engine
+ specification. This board has a OPSP-REP chip.
+
+config PLAT_OAKS32R
+ bool "OAKS32R"
+ help
+ The OAKS32R is a tiny, inexpensive evaluation board.
+ Please note that if you say Y here and choose chip "M32102",
+ say N for MMU and select a no-MMU version kernel, otherwise
+ a kernel with MMU support will not work, because the M32102
+ is a microcontroller for embedded systems and it has no MMU.
+
+config PLAT_MAPPI2
+ bool "Mappi-II(M3A-ZA36/M3A-ZA52)"
+
+endchoice
+
+choice
+ prompt "Processor family"
+ default CHIP_M32700
+
+config CHIP_M32700
+ bool "M32700 (Chaos)"
+
+config CHIP_M32102
+ bool "M32102"
+
+config CHIP_VDEC2
+ bool "VDEC2"
+
+config CHIP_OPSP
+ bool "OPSP"
+
+endchoice
+
+config MMU
+ bool "Support for memory management hardware"
+ depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
+ default y
+
+config TLB_ENTRIES
+ int "TLB Entries"
+ depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
+ default 32 if CHIP_M32700 || CHIP_OPSP
+ default 16 if CHIP_VDEC2
+
+
+config ISA_M32R
+ bool
+ depends on CHIP_M32102
+ default y
+
+config ISA_M32R2
+ bool
+ depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
+ default y
+
+config ISA_DSP_LEVEL2
+ bool
+ depends on CHIP_M32700 || CHIP_OPSP
+ default y
+
+config ISA_DUAL_ISSUE
+ bool
+ depends on CHIP_M32700 || CHIP_OPSP
+ default y
+
+config BUS_CLOCK
+ int "Bus Clock [Hz] (integer)"
+ default "70000000" if PLAT_MAPPI
+ default "25000000" if PLAT_USRV
+ default "50000000" if PLAT_M32700UT
+ default "50000000" if PLAT_OPSPUT
+ default "33333333" if PLAT_OAKS32R
+ default "20000000" if PLAT_MAPPI2
+
+config TIMER_DIVIDE
+ int "Timer divider (integer)"
+ default "128"
+
+config CPU_LITTLE_ENDIAN
+ bool "Generate little endian code"
+ default n
+
+config MEMORY_START
+ hex "Physical memory start address (hex)"
+ default "08000000" if PLAT_MAPPI || PLAT_MAPPI2
+ default "08000000" if PLAT_USRV
+ default "08000000" if PLAT_M32700UT
+ default "08000000" if PLAT_OPSPUT
+ default "01000000" if PLAT_OAKS32R
+
+config MEMORY_SIZE
+ hex "Physical memory size (hex)"
+ default "04000000" if PLAT_MAPPI || PLAT_MAPPI2
+ default "02000000" if PLAT_USRV
+ default "01000000" if PLAT_M32700UT
+ default "01000000" if PLAT_OPSPUT
+ default "00800000" if PLAT_OAKS32R
+
+config NOHIGHMEM
+ bool
+ default y
+
+config DISCONTIGMEM
+ bool "Internal RAM Support"
+ depends on CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP
+ default y
+
+config IRAM_START
+ hex "Internal memory start address (hex)"
+ default "00f00000"
+ depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP) && DISCONTIGMEM
+
+config IRAM_SIZE
+ hex "Internal memory size (hex)"
+ depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP) && DISCONTIGMEM
+ default "00080000" if CHIP_M32700
+ default "00010000" if CHIP_M32102 || CHIP_OPSP
+ default "00008000" if CHIP_VDEC2
+
+#
+# Define implied options from the CPU selection here
+#
+
+config RWSEM_GENERIC_SPINLOCK
+ bool
+ depends on M32R
+ default y
+
+config RWSEM_XCHGADD_ALGORITHM
+ bool
+ default n
+
+config PREEMPT
+ bool "Preemptible Kernel"
+ help
+ This option reduces the latency of the kernel when reacting to
+ real-time or interactive events by allowing a low priority process to
+ be preempted even if it is in kernel mode executing a system call.
+ This allows applications to run more reliably even when the system is
+ under load.
+
+ Say Y here if you are building a kernel for a desktop, embedded
+ or real-time system. Say N if you are unsure.
+
+config HAVE_DEC_LOCK
+ bool
+ depends on (SMP || PREEMPT)
+ default n
+
+config SMP
+ bool "Symmetric multi-processing support"
+ ---help---
+ This enables support for systems with more than one CPU. If you have
+ a system with only one CPU, like most personal computers, say N. If
+ you have a system with more than one CPU, say Y.
+
+ If you say N here, the kernel will run on single and multiprocessor
+ machines, but will use only one CPU of a multiprocessor machine. If
+ you say Y here, the kernel will run on many, but not all,
+ singleprocessor machines. On a singleprocessor machine, the kernel
+ will run faster if you say N here.
+
+ People using multiprocessor machines who say Y here should also say
+ Y to "Enhanced Real Time Clock Support", below. The "Advanced Power
+ Management" code will be disabled if you say Y here.
+
+ See also the <file:Documentation/smp.tex>,
+ <file:Documentation/smp.txt> and the SMP-HOWTO available at
+ <http://www.linuxdoc.org/docs.html#howto>.
+
+ If you don't know what to do here, say N.
+
+config CHIP_M32700_TS1
+ bool "Workaround code for the M32700 TS1 chip's bug"
+ depends on (CHIP_M32700 && SMP)
+ default n
+
+config NR_CPUS
+ int "Maximum number of CPUs (2-32)"
+ range 2 32
+ depends on SMP
+ default "2"
+ help
+ This allows you to specify the maximum number of CPUs which this
+ kernel will support. The maximum supported value is 32 and the
+ minimum value which makes sense is 2.
+
+ This is purely to save memory - each supported CPU adds
+ approximately eight kilobytes to the kernel image.
+
+# Common NUMA Features
+config NUMA
+ bool "Numa Memory Allocation Support"
+ depends on SMP
+ default n
+
+# turning this on wastes a bunch of space.
+# Summit needs it only when NUMA is on
+config BOOT_IOREMAP
+ bool
+ depends on NUMA
+ default n
+
+endmenu
+
+
+menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
+
+config PCI
+ bool "PCI support"
+ default n
+ help
+ Find out whether you have a PCI motherboard. PCI is the name of a
+ bus system, i.e. the way the CPU talks to the other stuff inside
+ your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
+ VESA. If you have PCI, say Y, otherwise N.
+
+ The PCI-HOWTO, available from
+ <http://www.linuxdoc.org/docs.html#howto>, contains valuable
+ information about which PCI hardware does work under Linux and which
+ doesn't.
+
+choice
+ prompt "PCI access mode"
+ depends on PCI
+ default PCI_GOANY
+
+config PCI_GOBIOS
+ bool "BIOS"
+ ---help---
+ On PCI systems, the BIOS can be used to detect the PCI devices and
+ determine their configuration. However, some old PCI motherboards
+ have BIOS bugs and may crash if this is done. Also, some embedded
+ PCI-based systems don't have any BIOS at all. Linux can also try to
+ detect the PCI hardware directly without using the BIOS.
+
+ With this option, you can specify how Linux should detect the PCI
+ devices. If you choose "BIOS", the BIOS will be used, if you choose
+ "Direct", the BIOS won't be used, and if you choose "Any", the
+ kernel will try the direct access method and falls back to the BIOS
+ if that doesn't work. If unsure, go with the default, which is
+ "Any".
+
+config PCI_GODIRECT
+ bool "Direct"
+
+config PCI_GOANY
+ bool "Any"
+
+endchoice
+
+config PCI_BIOS
+ bool
+ depends on PCI && (PCI_GOBIOS || PCI_GOANY)
+ default y
+
+config PCI_DIRECT
+ bool
+ depends on PCI && (PCI_GODIRECT || PCI_GOANY)
+ default y
+
+source "drivers/pci/Kconfig"
+
+config ISA
+ bool "ISA support"
+ help
+ Find out whether you have ISA slots on your motherboard. ISA is the
+ name of a bus system, i.e. the way the CPU talks to the other stuff
+ inside your box. If you have ISA, say Y, otherwise N.
+
+source "drivers/pcmcia/Kconfig"
+
+source "drivers/pci/hotplug/Kconfig"
+
+endmenu
+
+
+menu "Executable file formats"
+
+source "fs/Kconfig.binfmt"
+
+endmenu
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "arch/m32r/oprofile/Kconfig"
+
+menu "Kernel hacking"
+
+config DEBUG_KERNEL
+ bool "Kernel debugging"
+ help
+ Say Y here if you are developing drivers or trying to debug and
+ identify kernel problems.
+
+config DEBUG_STACKOVERFLOW
+ bool "Check for stack overflows"
+ depends on DEBUG_KERNEL
+
+config DEBUG_SLAB
+ bool "Debug memory allocations"
+ depends on DEBUG_KERNEL
+ help
+ Say Y here to have the kernel do limited verification on memory
+ allocation as well as poisoning memory on free to catch use of freed
+ memory.
+
+config DEBUG_IOVIRT
+ bool "Memory mapped I/O debugging"
+ depends on DEBUG_KERNEL
+ help
+ Say Y here to get warned whenever an attempt is made to do I/O on
+ obviously invalid addresses such as those generated when ioremap()
+ calls are forgotten. Memory mapped I/O will go through an extra
+ check to catch access to unmapped ISA addresses, an access method
+ that can still be used by old drivers that are being ported from
+ 2.0/2.2.
+
+config MAGIC_SYSRQ
+ bool "Magic SysRq key"
+ depends on DEBUG_KERNEL
+ help
+ If you say Y here, you will have some control over the system even
+ if the system crashes for example during kernel debugging (e.g., you
+ will be able to flush the buffer cache to disk, reboot the system
+ immediately or dump some status information). This is accomplished
+ by pressing various keys while holding SysRq (Alt+PrintScreen). It
+ also works on a serial console (on PC hardware at least), if you
+ send a BREAK and then within 5 seconds a command keypress. The
+ keys are documented in <file:Documentation/sysrq.txt>. Don't say Y
+ unless you really know what this hack does.
+
+config DEBUG_SPINLOCK
+ bool "Spinlock debugging"
+ depends on DEBUG_KERNEL
+ help
+ Say Y here and build SMP to catch missing spinlock initialization
+ and certain other kinds of spinlock errors commonly made. This is
+ best used in conjunction with the NMI watchdog so that spinlock
+ deadlocks are also debuggable.
+
+config DEBUG_PAGEALLOC
+ bool "Page alloc debugging"
+ depends on DEBUG_KERNEL
+ help
+ Unmap pages from the kernel linear mapping after free_pages().
+ This results in a large slowdown, but helps to find certain types
+ of memory corruptions.
+
+config DEBUG_INFO
+ bool "Compile the kernel with debug info"
+ depends on DEBUG_KERNEL
+ help
+ If you say Y here the resulting kernel image will include
+ debugging info resulting in a larger kernel image.
+ Say Y here only if you plan to use gdb to debug the kernel.
+ If you don't debug the kernel, you can say N.
+
+config DEBUG_SPINLOCK_SLEEP
+ bool "Sleep-inside-spinlock checking"
+ help
+ If you say Y here, various routines which may sleep will become very
+ noisy if they are called with a spinlock held.
+
+config FRAME_POINTER
+ bool "Compile the kernel with frame pointers"
+ help
+ If you say Y here the resulting kernel image will be slightly larger
+ and slower, but it will give very useful debugging information.
+ If you don't debug the kernel, you can say N, but we may not be able
+ to solve problems without frame pointers.
+
+endmenu
+
+source "security/Kconfig"
+
+source "crypto/Kconfig"
+
+source "lib/Kconfig"
+
--- /dev/null
+#
+# m32r/Makefile
+#
+
+LDFLAGS :=
+OBJCOPYFLAGS := -O binary -R .note -R .comment -S
+LDFLAGS_vmlinux := -e startup_32
+LDFLAGS_BLOB := --format binary --oformat elf32-m32r
+
+CFLAGS += -pipe -fno-schedule-insns
+CFLAGS_KERNEL += -mmodel=medium
+CFLAGS_MODULE += -mmodel=large
+
+ifdef CONFIG_CHIP_VDEC2
+cflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -Wa,-bitinst
+aflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -Wa,-bitinst
+else
+cflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -m32r2
+aflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -m32r2
+endif
+
+cflags-$(CONFIG_ISA_M32R) += -DNO_FPU
+aflags-$(CONFIG_ISA_M32R) += -DNO_FPU -Wa,-no-bitinst
+
+CFLAGS += $(cflags-y)
+AFLAGS += $(aflags-y)
+
+CHECKFLAGS := $(CHECK) -D__m32r__
+
+head-y := arch/m32r/kernel/head.o arch/m32r/kernel/init_task.o
+
+LIBGCC := $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+
+libs-y += arch/m32r/lib/ $(LIBGCC)
+core-y += arch/m32r/kernel/ \
+ arch/m32r/mm/ \
+ arch/m32r/boot/
+
+drivers-$(CONFIG_OPROFILE) += arch/m32r/oprofile/
+
+boot := arch/m32r/boot
+
+.PHONY: zImage
+
+zImage: vmlinux
+ $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+
+compressed: zImage
+
+archclean:
+ $(Q)$(MAKE) $(clean)=$(boot)
+
+define archhelp
+ @echo ' zImage - Compressed kernel image (arch/m32r/boot/zImage)'
+endef
--- /dev/null
+#
+# arch/m32r/boot/Makefile
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License. See the file "COPYING" in the main directory of this archive
+# for more details.
+
+targets := zImage
+subdir- := compressed
+
+obj-y := setup.o
+
+$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
+ $(call if_changed,objcopy)
+ @echo 'Kernel: $@ is ready'
+
+$(obj)/compressed/vmlinux: FORCE
+ $(Q)$(MAKE) $(build)=$(obj)/compressed $@
+
--- /dev/null
+#
+# linux/arch/sh/boot/compressed/Makefile
+#
+# create a compressed vmlinux image from the original vmlinux
+#
+
+targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o \
+ m32r-sio.o piggy.o vmlinux.lds
+EXTRA_AFLAGS := -traditional
+
+OBJECTS = $(obj)/head.o $(obj)/misc.o $(obj)/m32r_sio.o
+
+#
+# IMAGE_OFFSET is the load offset of the compression loader
+#
+#IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+0x2000])
+#IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+0x00400000])
+
+LDFLAGS_vmlinux := -T
+
+$(obj)/vmlinux: $(obj)/vmlinux.lds $(OBJECTS) $(obj)/piggy.o FORCE
+ $(call if_changed,ld)
+ @:
+
+$(obj)/vmlinux.bin: vmlinux FORCE
+ $(call if_changed,objcopy)
+
+$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
+ $(call if_changed,gzip)
+
+$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.S FORCE
+ $(CPP) $(EXTRA_AFLAGS) -C -P -I include $< >$@
+
+LDFLAGS_piggy.o := -r --format binary --oformat elf32-m32r-linux -T
+OBJCOPYFLAGS += -R .empty_zero_page
+
+$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.gz FORCE
+ $(call if_changed,ld)
--- /dev/null
+/*
+ * 1. load vmlinuz
+ *
+ * CONFIG_MEMORY_START +-----------------------+
+ * | vmlinuz |
+ * +-----------------------+
+ * 2. decompressed
+ *
+ * CONFIG_MEMORY_START +-----------------------+
+ * | vmlinuz |
+ * +-----------------------+
+ * | |
+ * BOOT_RELOC_ADDR +-----------------------+
+ * | |
+ * KERNEL_DECOMPRESS_ADDR +-----------------------+
+ * | vmlinux |
+ * +-----------------------+
+ *
+ * 3. relocate copy & jump code
+ *
+ * CONFIG_MEMORY_START +-----------------------+
+ * | vmlinuz |
+ * +-----------------------+
+ * | |
+ * BOOT_RELOC_ADDR +-----------------------+
+ * | boot(copy&jump) |
+ * KERNEL_DECOMPRESS_ADDR +-----------------------+
+ * | vmlinux |
+ * +-----------------------+
+ *
+ * 4. relocate decompressed kernel
+ *
+ * CONFIG_MEMORY_START +-----------------------+
+ * | vmlinux |
+ * +-----------------------+
+ * | |
+ * BOOT_RELOC_ADDR +-----------------------+
+ * | boot(copy&jump) |
+ * KERNEL_DECOMPRESS_ADDR +-----------------------+
+ * | |
+ * +-----------------------+
+ *
+ */
+#ifdef __ASSEMBLY__
+#define __val(x) x
+#else
+#define __val(x) (x)
+#endif
+
+#define DECOMPRESS_OFFSET_BASE __val(0x00900000)
+#define BOOT_RELOC_SIZE __val(0x00001000)
+
+#define KERNEL_EXEC_ADDR __val(CONFIG_MEMORY_START)
+#define KERNEL_DECOMPRESS_ADDR __val(CONFIG_MEMORY_START + \
+ DECOMPRESS_OFFSET_BASE + BOOT_RELOC_SIZE)
+#define KERNEL_ENTRY __val(CONFIG_MEMORY_START + 0x1000)
+
+#define BOOT_EXEC_ADDR __val(CONFIG_MEMORY_START)
+#define BOOT_RELOC_ADDR __val(CONFIG_MEMORY_START + DECOMPRESS_OFFSET_BASE)
--- /dev/null
+/*
+ * linux/arch/m32r/boot/compressed/head.S
+ *
+ * Copyright (c) 2001-2003 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi
+ * Copyright (c) 2004 Hirokazu Takata
+ */
+
+ .text
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/assembler.h>
+
+ .global startup
+ __ALIGN
+startup:
+ ldi r0, #0x0000 /* SPI, disable EI */
+ mvtc r0, psw
+
+/*
+ * Clear BSS first so that there are no surprises...
+ */
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ LDIMM (r2, __bss_start)
+ LDIMM (r3, _end)
+ sub r3, r2 ; BSS size in bytes
+ ; R4 = BSS size in longwords (rounded down)
+ mv r4, r3 || ldi r1, #0
+ srli r4, #4 || addi r2, #-4
+ beqz r4, .Lendloop1
+.Lloop1:
+#ifndef CONFIG_CHIP_M32310
+ ; Touch memory for the no-write-allocating cache.
+ ld r0, @(4,r2)
+#endif
+ st r1, @+r2 || addi r4, #-1
+ st r1, @+r2
+ st r1, @+r2
+ st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
+ bnc .Lloop1
+.Lendloop1:
+ and3 r4, r3, #15
+ addi r2, #4
+ beqz r4, .Lendloop2
+.Lloop2:
+ stb r1, @r2 || addi r4, #-1
+ addi r2, #1
+ bnez r4, .Lloop2
+.Lendloop2:
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ LDIMM (r2, __bss_start)
+ LDIMM (r3, _end)
+ sub r3, r2 ; BSS size in bytes
+ mv r4, r3
+ srli r4, #2 ; R4 = BSS size in longwords (rounded down)
+ ldi r1, #0 ; clear R1 for longwords store
+ addi r2, #-4 ; account for pre-inc store
+ beqz r4, .Lendloop1 ; any more to go?
+.Lloop1:
+ st r1, @+r2 ; yep, zero out another longword
+ addi r4, #-1 ; decrement count
+ bnez r4, .Lloop1 ; go do some more
+.Lendloop1:
+ and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
+ addi r2, #4 ; account for pre-inc store
+ beqz r4, .Lendloop2 ; any more to go?
+.Lloop2:
+ stb r1, @r2 ; yep, zero out another byte
+ addi r2, #1 ; bump address
+ addi r4, #-1 ; decrement count
+ bnez r4, .Lloop2 ; go do some more
+.Lendloop2:
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+ seth r0, #shigh(stack_start)
+ ld sp, @(r0, low(stack_start)) /* set stack point */
+
+/*
+ * decompress the kernel
+ */
+ bl decompress_kernel
+
+#if defined(CONFIG_CHIP_M32700)
+ /* Cache flush */
+ ldi r0, -1
+ ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
+ stb r1, @r0
+#else
+#error "put your cache flush function, please"
+#endif
+ seth r0, #high(CONFIG_MEMORY_START)
+ or3 r0, r0, #0x2000
+ jmp r0
+
+ .balign 512
+fake_headers_as_bzImage:
+ .short 0
+ .ascii "HdrS"
+ .short 0x0202
+ .short 0
+ .short 0
+ .byte 0x00, 0x10
+ .short 0
+ .byte 0
+ .byte 1
+ .byte 0x00, 0x80
+ .long 0
+ .long 0
+
--- /dev/null
+#!/bin/sh
+#
+# arch/sh/boot/install.sh
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License. See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1995 by Linus Torvalds
+#
+# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
+# Adapted from code in arch/i386/boot/install.sh by Russell King
+# Adapted from code in arch/arm/boot/install.sh by Stuart Menefy
+# Adapted from code in arch/sh/boot/install.sh by Takeo Takahashi
+#
+# "make install" script for sh architecture
+#
+# Arguments:
+# $1 - kernel version
+# $2 - kernel image file
+# $3 - kernel map file
+# $4 - default install path (blank if root directory)
+#
+
+# User may have a custom install script
+
+if [ -x /sbin/installkernel ]; then
+ exec /sbin/installkernel "$@"
+fi
+
+if [ "$2" = "zImage" ]; then
+# Compressed install
+ echo "Installing compressed kernel"
+ if [ -f $4/vmlinuz-$1 ]; then
+ mv $4/vmlinuz-$1 $4/vmlinuz.old
+ fi
+
+ if [ -f $4/System.map-$1 ]; then
+ mv $4/System.map-$1 $4/System.old
+ fi
+
+ cat $2 > $4/vmlinuz-$1
+ cp $3 $4/System.map-$1
+else
+# Normal install
+ echo "Installing normal kernel"
+ if [ -f $4/vmlinux-$1 ]; then
+ mv $4/vmlinux-$1 $4/vmlinux.old
+ fi
+
+ if [ -f $4/System.map ]; then
+ mv $4/System.map $4/System.old
+ fi
+
+ cat $2 > $4/vmlinux-$1
+ cp $3 $4/System.map
+fi
--- /dev/null
+/*
+ * arch/m32r/boot/compressed/m32r_sio.c
+ *
+ * 2003-02-12: Takeo Takahashi
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+void putc(char c);
+
+int puts(const char *s)
+{
+ char c;
+ while ((c = *s++)) putc(c);
+ return 0;
+}
+
+#if defined(CONFIG_PLAT_M32700UT_Alpha) || defined(CONFIG_PLAT_M32700UT)
+#define USE_FPGA_MAP 0
+
+#if USE_FPGA_MAP
+/*
+ * fpga configuration program uses MMU, and define map as same as
+ * M32104 uT-Engine board.
+ */
+#define BOOT_SIO0STS (volatile unsigned short *)(0x02c00000 + 0x20006)
+#define BOOT_SIO0TXB (volatile unsigned short *)(0x02c00000 + 0x2000c)
+#else
+#undef PLD_BASE
+#define PLD_BASE 0xa4c00000
+#define BOOT_SIO0STS PLD_ESIO0STS
+#define BOOT_SIO0TXB PLD_ESIO0TXB
+#endif
+
+void putc(char c)
+{
+
+ while ((*BOOT_SIO0STS & 0x3) != 0x3) ;
+ if (c == '\n') {
+ *BOOT_SIO0TXB = '\r';
+ while ((*BOOT_SIO0STS & 0x3) != 0x3) ;
+ }
+ *BOOT_SIO0TXB = c;
+}
+#else
+void putc(char c)
+{
+ /* do nothing */
+}
+#endif
--- /dev/null
+/*
+ * arch/m32r/boot/compressed/misc.c
+ *
+ * This is a collection of several routines from gzip-1.0.3
+ * adapted for Linux.
+ *
+ * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
+ *
+ * Adapted for SH by Stuart Menefy, Aug 1999
+ *
+ * Modified to use standard LinuxSH BIOS by Greg Banks 7Jul2000
+ *
+ * 2003-02-12: Support M32R by Takeo Takahashi
+ * This is based on arch/sh/boot/compressed/misc.c.
+ */
+
+#include <linux/config.h>
+#include <linux/string.h>
+
+/*
+ * gzip declarations
+ */
+
+#define OF(args) args
+#define STATIC static
+
+#undef memset
+#undef memcpy
+#define memzero(s, n) memset ((s), 0, (n))
+
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+
+#define WSIZE 0x8000 /* Window size must be at least 32k, */
+ /* and a power of two */
+
+static uch *inbuf; /* input buffer */
+static uch window[WSIZE]; /* Sliding window buffer */
+
+static unsigned insize; /* valid bytes in inbuf */
+static unsigned inptr; /* index of next byte to be processed in inbuf */
+static unsigned outcnt; /* bytes in output buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
+#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
+#define COMMENT 0x10 /* bit 4 set: file comment present */
+#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
+#define RESERVED 0xC0 /* bit 6,7: reserved */
+
+#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
+
+/* Diagnostic functions */
+#ifdef DEBUG
+# define Assert(cond,msg) {if(!(cond)) error(msg);}
+# define Trace(x) fprintf x
+# define Tracev(x) {if (verbose) fprintf x ;}
+# define Tracevv(x) {if (verbose>1) fprintf x ;}
+# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+# define Assert(cond,msg)
+# define Trace(x)
+# define Tracev(x)
+# define Tracevv(x)
+# define Tracec(c,x)
+# define Tracecv(c,x)
+#endif
+
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char input_data[];
+extern int input_len;
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern int puts(const char *);
+
+extern int _text; /* Defined in vmlinux.lds.S */
+extern int _end;
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#define HEAP_SIZE 0x10000
+
+#include "../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+ void *p;
+
+ if (size <0) error("Malloc error\n");
+ if (free_mem_ptr == 0) error("Memory error\n");
+
+ free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
+
+ p = (void *)free_mem_ptr;
+ free_mem_ptr += size;
+
+ if (free_mem_ptr >= free_mem_end_ptr)
+ error("\nOut of memory\n");
+
+ return p;
+}
+
+static void free(void *where)
+{ /* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+ *ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+ free_mem_ptr = (long) *ptr;
+}
+
+void* memset(void* s, int c, size_t n)
+{
+ int i;
+ char *ss = (char*)s;
+
+ for (i=0;i<n;i++) ss[i] = c;
+ return s;
+}
+
+void* memcpy(void* __dest, __const void* __src,
+ size_t __n)
+{
+ int i;
+ char *d = (char *)__dest, *s = (char *)__src;
+
+ for (i=0;i<__n;i++) d[i] = s[i];
+ return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+ if (insize != 0) {
+ error("ran out of input data\n");
+ }
+
+ inbuf = input_data;
+ insize = input_len;
+ inptr = 1;
+ return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+ ulg c = crc; /* temporary variable */
+ unsigned n;
+ uch *in, *out, ch;
+
+ in = window;
+ out = &output_data[output_ptr];
+ for (n = 0; n < outcnt; n++) {
+ ch = *out++ = *in++;
+ c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
+ }
+ crc = c;
+ bytes_out += (ulg)outcnt;
+ output_ptr += (ulg)outcnt;
+ outcnt = 0;
+}
+
+static void error(char *x)
+{
+ puts("\n\n");
+ puts(x);
+ puts("\n\n -- System halted");
+
+ while(1); /* Halt */
+}
+
+#define STACK_SIZE (4096)
+long user_stack [STACK_SIZE];
+long* stack_start = &user_stack[STACK_SIZE];
+
+/* return decompressed size */
+long decompress_kernel(void)
+{
+ insize = 0;
+ inptr = 0;
+ bytes_out = 0;
+ outcnt = 0;
+ output_data = 0;
+ output_ptr = CONFIG_MEMORY_START + 0x2000;
+ free_mem_ptr = (unsigned long)&_end;
+ free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
+
+ makecrc();
+ puts("Uncompressing Linux... ");
+ gunzip();
+ puts("Ok, booting the kernel.\n");
+ return bytes_out;
+}
--- /dev/null
+#include <linux/config.h>
+
+OUTPUT_ARCH(m32r)
+ENTRY(startup)
+SECTIONS
+{
+ . = CONFIG_MEMORY_START + 0x00400000;
+
+ _text = .;
+ .text : { *(.text) } = 0
+ .rodata : { *(.rodata) }
+ _etext = .;
+
+ . = ALIGN(32) + (. & (32 - 1));
+ .data : { *(.data) }
+ _edata = .;
+
+ . = ALIGN(32 / 8);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ . = ALIGN(32 / 8);
+ _end = . ;
+}
--- /dev/null
+SECTIONS
+{
+ .data : {
+ input_len = .;
+ LONG(input_data_end - input_data) input_data = .;
+ *(.data)
+ input_data_end = .;
+ }
+}
--- /dev/null
+/*
+ * linux/arch/m32r/boot/setup.S -- A setup code.
+ *
+ * Copyright (C) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * and Hitoshi Yamamoto
+ *
+ */
+/* $Id$ */
+
+#include <linux/linkage.h>
+#include <asm/segment.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include <linux/config.h>
+#include <asm/assembler.h>
+#include <asm/mmu_context.h>
+#include <asm/m32r.h>
+
+/*
+ * References to members of the boot_cpu_data structure.
+ */
+
+#define CPU_PARAMS boot_cpu_data
+#define M32R_MCICAR 0xfffffff0
+#define M32R_MCDCAR 0xfffffff4
+#define M32R_MCCR 0xfffffffc
+#define M32R_BSCR0 0xffffffd2
+
+;BSEL
+#define BSEL0CR0 0x00ef5000
+#define BSEL0CR1 0x00ef5004
+#define BSEL1CR0 0x00ef5100
+#define BSEL1CR1 0x00ef5104
+#define BSEL0CR0_VAL 0x00000000
+#define BSEL0CR1_VAL 0x01200100
+#define BSEL1CR0_VAL 0x01018000
+#define BSEL1CR1_VAL 0x00200001
+
+;SDRAMC
+#define SDRAMC_SDRF0 0x00ef6000
+#define SDRAMC_SDRF1 0x00ef6004
+#define SDRAMC_SDIR0 0x00ef6008
+#define SDRAMC_SDIR1 0x00ef600c
+#define SDRAMC_SD0ADR 0x00ef6020
+#define SDRAMC_SD0ER 0x00ef6024
+#define SDRAMC_SD0TR 0x00ef6028
+#define SDRAMC_SD0MOD 0x00ef602c
+#define SDRAMC_SD1ADR 0x00ef6040
+#define SDRAMC_SD1ER 0x00ef6044
+#define SDRAMC_SD1TR 0x00ef6048
+#define SDRAMC_SD1MOD 0x00ef604c
+#define SDRAM0 0x18000000
+#define SDRAM1 0x1c000000
+
+/*------------------------------------------------------------------------
+ * start up
+ */
+
+/*------------------------------------------------------------------------
+ * Kernel entry
+ */
+ .section .boot, "ax"
+ENTRY(boot)
+
+/* Set cache mode */
+#if defined(CONFIG_CHIP_XNUX2)
+ ldi r0, #-2 ;LDIMM (r0, M32R_MCCR)
+ ldi r1, #0x0101 ; cache on (with invalidation)
+; ldi r1, #0x00 ; cache off
+ sth r1, @r0
+#elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
+ || defined(CONFIG_CHIP_OPSP)
+ ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
+ ldi r1, #0x73 ; cache on (with invalidation)
+; ldi r1, #0x00 ; cache off
+ st r1, @r0
+#else
+#error unknown chip configuration
+#endif
+
+#ifdef CONFIG_SMP
+ ;; if not BSP (CPU#0) goto AP_loop
+ seth r5, #shigh(M32R_CPUID_PORTL)
+ ld r5, @(low(M32R_CPUID_PORTL), r5)
+ bnez r5, AP_loop
+#if !defined(CONFIG_PLAT_USRV)
+ ;; boot AP
+ ld24 r5, #0xeff2f8 ; IPICR7
+ ldi r6, #0x2 ; IPI to CPU1
+ st r6, @r5
+#endif
+#endif
+
+/*
+ * Now, Jump to stext
+ * if with MMU, TLB on.
+ * if with no MMU, only jump.
+ */
+ .global eit_vector
+mmu_on:
+ LDIMM (r13, stext)
+#ifdef CONFIG_MMU
+ bl init_tlb
+ LDIMM (r2, eit_vector) ; set EVB(cr5)
+ mvtc r2, cr5
+ seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
+ or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
+ ldi r1, #0x01
+ st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
+ ld r0, @(MATM_offset,r0) ; Check
+#else
+ seth r0,#high(M32R_MCDCAR)
+ or3 r0,r0,#low(M32R_MCDCAR)
+ ld24 r1,#0x8080
+ st r1,@r0
+#endif /* CONFIG_MMU */
+ jmp r13
+ nop
+ nop
+
+#ifdef CONFIG_SMP
+/*
+ * AP wait loop
+ */
+ENTRY(AP_loop)
+ ;; disable interrupt
+ clrpsw #0x40
+ ;; reset EVB
+ LDIMM (r4, _AP_RE)
+ seth r5, #high(__PAGE_OFFSET)
+ or3 r5, r5, #low(__PAGE_OFFSET)
+ not r5, r5
+ and r4, r5
+ mvtc r4, cr5
+ ;; disable maskable interrupt
+ seth r4, #high(M32R_ICU_IMASK_PORTL)
+ or3 r4, r4, #low(M32R_ICU_IMASK_PORTL)
+ ldi r5, #0
+ st r5, @r4
+ ld r5, @r4
+ ;; enable only IPI
+ setpsw #0x40
+ ;; LOOOOOOOOOOOOOOP!!!
+ .fillinsn
+2:
+ nop
+ nop
+ bra 2b
+ nop
+ nop
+
+#ifdef CONFIG_CHIP_M32700_TS1
+ .global dcache_dummy
+ .balign 16, 0
+dcache_dummy:
+ .byte 16
+#endif /* CONFIG_CHIP_M32700_TS1 */
+#endif /* CONFIG_SMP */
+
+ .end
+
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Processor type and features
+#
+# CONFIG_PLAT_MAPPI is not set
+# CONFIG_PLAT_USRV is not set
+CONFIG_PLAT_M32700UT=y
+# CONFIG_PLAT_OPSPUT is not set
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+CONFIG_CHIP_M32700=y
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+CONFIG_MMU=y
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=50000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x01000000
+CONFIG_NOHIGHMEM=y
+# CONFIG_DISCONTIGMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+# CONFIG_SMP is not set
+
+#
+# M32R drivers
+#
+# CONFIG_M32RPCC is not set
+CONFIG_M32R_CFC=y
+CONFIG_M32700UT_CFC=y
+CONFIG_CFC_NUM=1
+# CONFIG_MTD_M32R is not set
+CONFIG_M32R_SMC91111=y
+CONFIG_M32700UT_DS1302=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=m
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_M32R_SIO is not set
+CONFIG_SERIAL_M32R_PLDSIO=y
+CONFIG_SERIAL_M32R_PLDSIO_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+
+#
+# Video For Linux
+#
+
+#
+# Video Adapters
+#
+# CONFIG_VIDEO_CPIA is not set
+CONFIG_M32R_AR=y
+CONFIG_M32R_AR_VGA=y
+
+#
+# Radio Adapters
+#
+# CONFIG_RADIO_MAESTRO is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+#
+# Makefile for the Linux/M32R kernel.
+#
+
+extra-y := head.o init_task.o vmlinux.lds
+
+obj-y := process.o entry.o traps.o align.o irq.o setup.o time.o \
+ m32r_ksyms.o sys_m32r.o semaphore.o signal.o ptrace.o
+
+obj-$(CONFIG_SMP) += smp.o smpboot.o
+obj-$(CONFIG_PLAT_MAPPI) += setup_mappi.o io_mappi.o
+obj-$(CONFIG_PLAT_MAPPI2) += setup_mappi2.o io_mappi2.o
+obj-$(CONFIG_PLAT_USRV) += setup_usrv.o io_usrv.o
+obj-$(CONFIG_PLAT_M32700UT) += setup_m32700ut.o io_m32700ut.o
+obj-$(CONFIG_PLAT_OPSPUT) += setup_opsput.o io_opsput.o
+obj-$(CONFIG_MODULES) += module.o
+obj-$(CONFIG_PLAT_OAKS32R) += setup_oaks32r.o io_oaks32r.o
+
+EXTRA_AFLAGS := -traditional
+
--- /dev/null
+/*
+ * align.c - address exception handler for M32R
+ *
+ * Copyright (c) 2003 Hitoshi Yamamoto
+ */
+
+#include <linux/config.h>
+#include <asm/ptrace.h>
+#include <asm/uaccess.h>
+
+static int get_reg(struct pt_regs *regs, int nr)
+{
+ int val;
+
+ if (nr < 4)
+ val = *(unsigned long *)(®s->r0 + nr);
+ else if (nr < 7)
+ val = *(unsigned long *)(®s->r4 + (nr - 4));
+ else if (nr < 13)
+ val = *(unsigned long *)(®s->r7 + (nr - 7));
+ else
+ val = *(unsigned long *)(®s->fp + (nr - 13));
+
+ return val;
+}
+
+static void set_reg(struct pt_regs *regs, int nr, int val)
+{
+ if (nr < 4)
+ *(unsigned long *)(®s->r0 + nr) = val;
+ else if (nr < 7)
+ *(unsigned long *)(®s->r4 + (nr - 4)) = val;
+ else if (nr < 13)
+ *(unsigned long *)(®s->r7 + (nr - 7)) = val;
+ else
+ *(unsigned long *)(®s->fp + (nr - 13)) = val;
+}
+
+#define REG1(insn) (((insn) & 0x0f00) >> 8)
+#define REG2(insn) ((insn) & 0x000f)
+#define PSW_BC 0x100
+
+/* O- instruction */
+#define ISA_LD1 0x20c0 /* ld Rdest, @Rsrc */
+#define ISA_LD2 0x20e0 /* ld Rdest, @Rsrc+ */
+#define ISA_LDH 0x20a0 /* ldh Rdest, @Rsrc */
+#define ISA_LDUH 0x20b0 /* lduh Rdest, @Rsrc */
+#define ISA_ST1 0x2040 /* st Rsrc1, @Rsrc2 */
+#define ISA_ST2 0x2060 /* st Rsrc1, @+Rsrc2 */
+#define ISA_ST3 0x2070 /* st Rsrc1, @-Rsrc2 */
+#define ISA_STH1 0x2020 /* sth Rsrc1, @Rsrc2 */
+#define ISA_STH2 0x2030 /* sth Rsrc1, @Rsrc2+ */
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+/* OS instruction */
+#define ISA_ADD 0x00a0 /* add Rdest, Rsrc */
+#define ISA_ADDI 0x4000 /* addi Rdest, #imm8 */
+#define ISA_ADDX 0x0090 /* addx Rdest, Rsrc */
+#define ISA_AND 0x00c0 /* and Rdest, Rsrc */
+#define ISA_CMP 0x0040 /* cmp Rsrc1, Rsrc2 */
+#define ISA_CMPEQ 0x0060 /* cmpeq Rsrc1, Rsrc2 */
+#define ISA_CMPU 0x0050 /* cmpu Rsrc1, Rsrc2 */
+#define ISA_CMPZ 0x0070 /* cmpz Rsrc */
+#define ISA_LDI 0x6000 /* ldi Rdest, #imm8 */
+#define ISA_MV 0x1080 /* mv Rdest, Rsrc */
+#define ISA_NEG 0x0030 /* neg Rdest, Rsrc */
+#define ISA_NOP 0x7000 /* nop */
+#define ISA_NOT 0x00b0 /* not Rdest, Rsrc */
+#define ISA_OR 0x00e0 /* or Rdest, Rsrc */
+#define ISA_SUB 0x0020 /* sub Rdest, Rsrc */
+#define ISA_SUBX 0x0010 /* subx Rdest, Rsrc */
+#define ISA_XOR 0x00d0 /* xor Rdest, Rsrc */
+
+/* -S instruction */
+#define ISA_MUL 0x1060 /* mul Rdest, Rsrc */
+#define ISA_MULLO_A0 0x3010 /* mullo Rsrc1, Rsrc2, A0 */
+#define ISA_MULLO_A1 0x3090 /* mullo Rsrc1, Rsrc2, A1 */
+#define ISA_MVFACMI_A0 0x50f2 /* mvfacmi Rdest, A0 */
+#define ISA_MVFACMI_A1 0x50f6 /* mvfacmi Rdest, A1 */
+
+static int emu_addi(unsigned short insn, struct pt_regs *regs)
+{
+ char imm = (char)(insn & 0xff);
+ int dest = REG1(insn);
+ int val;
+
+ val = get_reg(regs, dest);
+ val += imm;
+ set_reg(regs, dest, val);
+
+ return 0;
+}
+
+static int emu_ldi(unsigned short insn, struct pt_regs *regs)
+{
+ char imm = (char)(insn & 0xff);
+
+ set_reg(regs, REG1(insn), (int)imm);
+
+ return 0;
+}
+
+static int emu_add(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ int src = REG2(insn);
+ int val;
+
+ val = get_reg(regs, dest);
+ val += get_reg(regs, src);
+ set_reg(regs, dest, val);
+
+ return 0;
+}
+
+static int emu_addx(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ unsigned int val, tmp;
+
+ val = regs->psw & PSW_BC ? 1 : 0;
+ tmp = get_reg(regs, dest);
+ val += tmp;
+ val += (unsigned int)get_reg(regs, REG2(insn));
+ set_reg(regs, dest, val);
+
+ /* C bit set */
+ if (val < tmp)
+ regs->psw |= PSW_BC;
+ else
+ regs->psw &= ~(PSW_BC);
+
+ return 0;
+}
+
+static int emu_and(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ int val;
+
+ val = get_reg(regs, dest);
+ val &= get_reg(regs, REG2(insn));
+ set_reg(regs, dest, val);
+
+ return 0;
+}
+
+static int emu_cmp(unsigned short insn, struct pt_regs *regs)
+{
+ if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn)))
+ regs->psw |= PSW_BC;
+ else
+ regs->psw &= ~(PSW_BC);
+
+ return 0;
+}
+
+static int emu_cmpeq(unsigned short insn, struct pt_regs *regs)
+{
+ if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn)))
+ regs->psw |= PSW_BC;
+ else
+ regs->psw &= ~(PSW_BC);
+
+ return 0;
+}
+
+static int emu_cmpu(unsigned short insn, struct pt_regs *regs)
+{
+ if ((unsigned int)get_reg(regs, REG1(insn))
+ < (unsigned int)get_reg(regs, REG2(insn)))
+ regs->psw |= PSW_BC;
+ else
+ regs->psw &= ~(PSW_BC);
+
+ return 0;
+}
+
+static int emu_cmpz(unsigned short insn, struct pt_regs *regs)
+{
+ if (!get_reg(regs, REG2(insn)))
+ regs->psw |= PSW_BC;
+ else
+ regs->psw &= ~(PSW_BC);
+
+ return 0;
+}
+
+static int emu_mv(unsigned short insn, struct pt_regs *regs)
+{
+ int val;
+
+ val = get_reg(regs, REG2(insn));
+ set_reg(regs, REG1(insn), val);
+
+ return 0;
+}
+
+static int emu_neg(unsigned short insn, struct pt_regs *regs)
+{
+ int val;
+
+ val = get_reg(regs, REG2(insn));
+ set_reg(regs, REG1(insn), 0 - val);
+
+ return 0;
+}
+
+static int emu_not(unsigned short insn, struct pt_regs *regs)
+{
+ int val;
+
+ val = get_reg(regs, REG2(insn));
+ set_reg(regs, REG1(insn), ~val);
+
+ return 0;
+}
+
+static int emu_or(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ int val;
+
+ val = get_reg(regs, dest);
+ val |= get_reg(regs, REG2(insn));
+ set_reg(regs, dest, val);
+
+ return 0;
+}
+
+static int emu_sub(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ int val;
+
+ val = get_reg(regs, dest);
+ val -= get_reg(regs, REG2(insn));
+ set_reg(regs, dest, val);
+
+ return 0;
+}
+
+static int emu_subx(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ unsigned int val, tmp;
+
+ val = tmp = get_reg(regs, dest);
+ val -= (unsigned int)get_reg(regs, REG2(insn));
+ val -= regs->psw & PSW_BC ? 1 : 0;
+ set_reg(regs, dest, val);
+
+ /* C bit set */
+ if (val > tmp)
+ regs->psw |= PSW_BC;
+ else
+ regs->psw &= ~(PSW_BC);
+
+ return 0;
+}
+
+static int emu_xor(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ unsigned int val;
+
+ val = (unsigned int)get_reg(regs, dest);
+ val ^= (unsigned int)get_reg(regs, REG2(insn));
+ set_reg(regs, dest, val);
+
+ return 0;
+}
+
+static int emu_mul(unsigned short insn, struct pt_regs *regs)
+{
+ int dest = REG1(insn);
+ int reg1, reg2;
+
+ reg1 = get_reg(regs, dest);
+ reg2 = get_reg(regs, REG2(insn));
+
+ __asm__ __volatile__ (
+ "mul %0, %1; \n\t"
+ : "+r" (reg1) : "r" (reg2)
+ );
+
+ set_reg(regs, dest, reg1);
+
+ return 0;
+}
+
+static int emu_mullo_a0(unsigned short insn, struct pt_regs *regs)
+{
+ int reg1, reg2;
+
+ reg1 = get_reg(regs, REG1(insn));
+ reg2 = get_reg(regs, REG2(insn));
+
+ __asm__ __volatile__ (
+ "mullo %0, %1, a0; \n\t"
+ "mvfachi %0, a0; \n\t"
+ "mvfaclo %1, a0; \n\t"
+ : "+r" (reg1), "+r" (reg2)
+ );
+
+ regs->acc0h = reg1;
+ regs->acc0l = reg2;
+
+ return 0;
+}
+
+static int emu_mullo_a1(unsigned short insn, struct pt_regs *regs)
+{
+ int reg1, reg2;
+
+ reg1 = get_reg(regs, REG1(insn));
+ reg2 = get_reg(regs, REG2(insn));
+
+ __asm__ __volatile__ (
+ "mullo %0, %1, a0; \n\t"
+ "mvfachi %0, a0; \n\t"
+ "mvfaclo %1, a0; \n\t"
+ : "+r" (reg1), "+r" (reg2)
+ );
+
+ regs->acc1h = reg1;
+ regs->acc1l = reg2;
+
+ return 0;
+}
+
+static int emu_mvfacmi_a0(unsigned short insn, struct pt_regs *regs)
+{
+ unsigned long val;
+
+ val = (regs->acc0h << 16) | (regs->acc0l >> 16);
+ set_reg(regs, REG1(insn), (int)val);
+
+ return 0;
+}
+
+static int emu_mvfacmi_a1(unsigned short insn, struct pt_regs *regs)
+{
+ unsigned long val;
+
+ val = (regs->acc1h << 16) | (regs->acc1l >> 16);
+ set_reg(regs, REG1(insn), (int)val);
+
+ return 0;
+}
+
+static int emu_m32r2(unsigned short insn, struct pt_regs *regs)
+{
+ int res = -1;
+
+ if ((insn & 0x7fff) == ISA_NOP) /* nop */
+ return 0;
+
+ switch(insn & 0x7000) {
+ case ISA_ADDI: /* addi Rdest, #imm8 */
+ res = emu_addi(insn, regs);
+ break;
+ case ISA_LDI: /* ldi Rdest, #imm8 */
+ res = emu_ldi(insn, regs);
+ break;
+ default:
+ break;
+ }
+
+ if (!res)
+ return 0;
+
+ switch(insn & 0x70f0) {
+ case ISA_ADD: /* add Rdest, Rsrc */
+ res = emu_add(insn, regs);
+ break;
+ case ISA_ADDX: /* addx Rdest, Rsrc */
+ res = emu_addx(insn, regs);
+ break;
+ case ISA_AND: /* and Rdest, Rsrc */
+ res = emu_and(insn, regs);
+ break;
+ case ISA_CMP: /* cmp Rsrc1, Rsrc2 */
+ res = emu_cmp(insn, regs);
+ break;
+ case ISA_CMPEQ: /* cmpeq Rsrc1, Rsrc2 */
+ res = emu_cmpeq(insn, regs);
+ break;
+ case ISA_CMPU: /* cmpu Rsrc1, Rsrc2 */
+ res = emu_cmpu(insn, regs);
+ break;
+ case ISA_CMPZ: /* cmpz Rsrc */
+ res = emu_cmpz(insn, regs);
+ break;
+ case ISA_MV: /* mv Rdest, Rsrc */
+ res = emu_mv(insn, regs);
+ break;
+ case ISA_NEG: /* neg Rdest, Rsrc */
+ res = emu_neg(insn, regs);
+ break;
+ case ISA_NOT: /* not Rdest, Rsrc */
+ res = emu_not(insn, regs);
+ break;
+ case ISA_OR: /* or Rdest, Rsrc */
+ res = emu_or(insn, regs);
+ break;
+ case ISA_SUB: /* sub Rdest, Rsrc */
+ res = emu_sub(insn, regs);
+ break;
+ case ISA_SUBX: /* subx Rdest, Rsrc */
+ res = emu_subx(insn, regs);
+ break;
+ case ISA_XOR: /* xor Rdest, Rsrc */
+ res = emu_xor(insn, regs);
+ break;
+ case ISA_MUL: /* mul Rdest, Rsrc */
+ res = emu_mul(insn, regs);
+ break;
+ case ISA_MULLO_A0: /* mullo Rsrc1, Rsrc2 */
+ res = emu_mullo_a0(insn, regs);
+ break;
+ case ISA_MULLO_A1: /* mullo Rsrc1, Rsrc2 */
+ res = emu_mullo_a1(insn, regs);
+ break;
+ default:
+ break;
+ }
+
+ if (!res)
+ return 0;
+
+ switch(insn & 0x70ff) {
+ case ISA_MVFACMI_A0: /* mvfacmi Rdest */
+ res = emu_mvfacmi_a0(insn, regs);
+ break;
+ case ISA_MVFACMI_A1: /* mvfacmi Rdest */
+ res = emu_mvfacmi_a1(insn, regs);
+ break;
+ default:
+ break;
+ }
+
+ return res;
+}
+
+#endif /* CONFIG_ISA_DUAL_ISSUE */
+
+/*
+ * ld : ?010 dest 1100 src
+ * 0010 dest 1110 src : ld Rdest, @Rsrc+
+ * ldh : ?010 dest 1010 src
+ * lduh : ?010 dest 1011 src
+ * st : ?010 src1 0100 src2
+ * 0010 src1 0110 src2 : st Rsrc1, @+Rsrc2
+ * 0010 src1 0111 src2 : st Rsrc1, @-Rsrc2
+ * sth : ?010 src1 0010 src2
+ */
+
+static int insn_check(unsigned long insn, struct pt_regs *regs,
+ unsigned char **ucp)
+{
+ int res = 0;
+
+ /*
+ * 32bit insn
+ * ld Rdest, @(disp16, Rsrc)
+ * st Rdest, @(disp16, Rsrc)
+ */
+ if (insn & 0x80000000) { /* 32bit insn */
+ *ucp += (short)(insn & 0x0000ffff);
+ regs->bpc += 4;
+ } else { /* 16bit insn */
+#ifdef CONFIG_ISA_DUAL_ISSUE
+ /* parallel exec check */
+ if (!(regs->bpc & 0x2) && insn & 0x8000) {
+ res = emu_m32r2((unsigned short)insn, regs);
+ regs->bpc += 4;
+ } else
+#endif /* CONFIG_ISA_DUAL_ISSUE */
+ regs->bpc += 2;
+ }
+
+ return res;
+}
+
+static int emu_ld(unsigned long insn32, struct pt_regs *regs)
+{
+ unsigned char *ucp;
+ unsigned long val;
+ unsigned short insn16;
+ int size, src;
+
+ insn16 = insn32 >> 16;
+ src = REG2(insn16);
+ ucp = (unsigned char *)get_reg(regs, src);
+
+ if (insn_check(insn32, regs, &ucp))
+ return -1;
+
+ size = insn16 & 0x0040 ? 4 : 2;
+ if (copy_from_user(&val, ucp, size))
+ return -1;
+
+ if (size == 2)
+ val >>= 16;
+
+ /* ldh sign check */
+ if ((insn16 & 0x00f0) == 0x00a0 && (val & 0x8000))
+ val |= 0xffff0000;
+
+ set_reg(regs, REG1(insn16), val);
+
+ /* ld increment check */
+ if ((insn16 & 0xf0f0) == ISA_LD2) /* ld Rdest, @Rsrc+ */
+ set_reg(regs, src, (unsigned long)(ucp + 4));
+
+ return 0;
+}
+
+static int emu_st(unsigned long insn32, struct pt_regs *regs)
+{
+ unsigned char *ucp;
+ unsigned long val;
+ unsigned short insn16;
+ int size, src2;
+
+ insn16 = insn32 >> 16;
+ src2 = REG2(insn16);
+
+ ucp = (unsigned char *)get_reg(regs, src2);
+
+ if (insn_check(insn32, regs, &ucp))
+ return -1;
+
+ size = insn16 & 0x0040 ? 4 : 2;
+ val = get_reg(regs, REG1(insn16));
+ if (size == 2)
+ val <<= 16;
+
+ /* st inc/dec check */
+ if ((insn16 & 0xf0e0) == 0x2060) {
+ if (insn16 & 0x0010)
+ ucp -= 4;
+ else
+ ucp += 4;
+
+ set_reg(regs, src2, (unsigned long)ucp);
+ }
+
+ if (copy_to_user(ucp, &val, size))
+ return -1;
+
+ /* sth inc check */
+ if ((insn16 & 0xf0f0) == ISA_STH2) {
+ ucp += 2;
+ set_reg(regs, src2, (unsigned long)ucp);
+ }
+
+ return 0;
+}
+
+int handle_unaligned_access(unsigned long insn32, struct pt_regs *regs)
+{
+ unsigned short insn16;
+ int res;
+
+ insn16 = insn32 >> 16;
+
+ /* ld or st check */
+ if ((insn16 & 0x7000) != 0x2000)
+ return -1;
+
+ /* insn alignment check */
+ if ((insn16 & 0x8000) && (regs->bpc & 3))
+ return -1;
+
+ if (insn16 & 0x0080) /* ld */
+ res = emu_ld(insn32, regs);
+ else /* st */
+ res = emu_st(insn32, regs);
+
+ return res;
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/entry.S
+ *
+ * Copyright (c) 2001, 2002 Hirokazu Takata, Hitoshi Yamamoto, H. Kondo
+ * Copyright (c) 2003 Hitoshi Yamamoto
+ * Copyright (c) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ *
+ * Taken from i386 version.
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ */
+
+/*
+ * entry.S contains the system-call and fault low-level handling routines.
+ * This also contains the timer-interrupt handler, as well as all interrupts
+ * and faults that can result in a task-switch.
+ *
+ * NOTE: This code handles signal-recognition, which happens every time
+ * after a timer-interrupt and after each system call.
+ *
+ * Stack layout in 'ret_from_system_call':
+ * ptrace needs to have all regs on the stack.
+ * if the order here is changed, it needs to be
+ * updated in fork.c:copy_process, signal.c:do_signal,
+ * ptrace.c and ptrace.h
+ *
+ * M32Rx/M32R2 M32R
+ * @(sp) - r4 ditto
+ * @(0x04,sp) - r5 ditto
+ * @(0x08,sp) - r6 ditto
+ * @(0x0c,sp) - *pt_regs ditto
+ * @(0x10,sp) - r0 ditto
+ * @(0x14,sp) - r1 ditto
+ * @(0x18,sp) - r2 ditto
+ * @(0x1c,sp) - r3 ditto
+ * @(0x20,sp) - r7 ditto
+ * @(0x24,sp) - r8 ditto
+ * @(0x28,sp) - r9 ditto
+ * @(0x2c,sp) - r10 ditto
+ * @(0x30,sp) - r11 ditto
+ * @(0x34,sp) - r12 ditto
+ * @(0x38,sp) - syscall_nr ditto
+ * @(0x3c,sp) - acc0h @(0x3c,sp) - acch
+ * @(0x40,sp) - acc0l @(0x40,sp) - accl
+ * @(0x44,sp) - acc1h @(0x44,sp) - psw
+ * @(0x48,sp) - acc1l @(0x48,sp) - bpc
+ * @(0x4c,sp) - psw @(0x4c,sp) - bbpsw
+ * @(0x50,sp) - bpc @(0x50,sp) - bbpc
+ * @(0x54,sp) - bbpsw @(0x54,sp) - spu (cr3)
+ * @(0x58,sp) - bbpc @(0x58,sp) - fp (r13)
+ * @(0x5c,sp) - spu (cr3) @(0x5c,sp) - lr (r14)
+ * @(0x60,sp) - fp (r13) @(0x60,sp) - spi (cr12)
+ * @(0x64,sp) - lr (r14) @(0x64,sp) - orig_r0
+ * @(0x68,sp) - spi (cr2)
+ * @(0x6c,sp) - orig_r0
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/irq.h>
+#include <asm/unistd.h>
+#include <asm/assembler.h>
+#include <asm/thread_info.h>
+#include <asm/errno.h>
+#include <asm/segment.h>
+#include <asm/smp.h>
+#include <asm/page.h>
+#include <asm/m32r.h>
+#include <asm/mmu_context.h>
+
+#if !defined(CONFIG_MMU)
+#define sys_madvise sys_ni_syscall
+#define sys_readahead sys_ni_syscall
+#define sys_mprotect sys_ni_syscall
+#define sys_msync sys_ni_syscall
+#define sys_mlock sys_ni_syscall
+#define sys_munlock sys_ni_syscall
+#define sys_mlockall sys_ni_syscall
+#define sys_munlockall sys_ni_syscall
+#define sys_mremap sys_ni_syscall
+#define sys_mincore sys_ni_syscall
+#endif /* CONFIG_MMU */
+
+#define R4(reg) @reg
+#define R5(reg) @(0x04,reg)
+#define R6(reg) @(0x08,reg)
+#define PTREGS(reg) @(0x0C,reg)
+#define R0(reg) @(0x10,reg)
+#define R1(reg) @(0x14,reg)
+#define R2(reg) @(0x18,reg)
+#define R3(reg) @(0x1C,reg)
+#define R7(reg) @(0x20,reg)
+#define R8(reg) @(0x24,reg)
+#define R9(reg) @(0x28,reg)
+#define R10(reg) @(0x2C,reg)
+#define R11(reg) @(0x30,reg)
+#define R12(reg) @(0x34,reg)
+#define SYSCALL_NR(reg) @(0x38,reg)
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+#define ACC0H(reg) @(0x3C,reg)
+#define ACC0L(reg) @(0x40,reg)
+#define ACC1H(reg) @(0x44,reg)
+#define ACC1L(reg) @(0x48,reg)
+#define PSW(reg) @(0x4C,reg)
+#define BPC(reg) @(0x50,reg)
+#define BBPSW(reg) @(0x54,reg)
+#define BBPC(reg) @(0x58,reg)
+#define SPU(reg) @(0x5C,reg)
+#define FP(reg) @(0x60,reg) /* FP = R13 */
+#define LR(reg) @(0x64,reg)
+#define SP(reg) @(0x68,reg)
+#define ORIG_R0(reg) @(0x6C,reg)
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+#define ACCH(reg) @(0x3C,reg)
+#define ACCL(reg) @(0x40,reg)
+#define PSW(reg) @(0x44,reg)
+#define BPC(reg) @(0x48,reg)
+#define BBPSW(reg) @(0x4C,reg)
+#define BBPC(reg) @(0x50,reg)
+#define SPU(reg) @(0x54,reg)
+#define FP(reg) @(0x58,reg) /* FP = R13 */
+#define LR(reg) @(0x5C,reg)
+#define SP(reg) @(0x60,reg)
+#define ORIG_R0(reg) @(0x64,reg)
+#else
+#error unknown isa configuration
+#endif
+
+CF_MASK = 0x00000001
+TF_MASK = 0x00000100
+IF_MASK = 0x00000200
+DF_MASK = 0x00000400
+NT_MASK = 0x00004000
+VM_MASK = 0x00020000
+
+#ifdef CONFIG_PREEMPT
+#define preempt_stop(x) CLI(x)
+#else
+#define preempt_stop(x)
+#define resume_kernel restore_all
+#endif
+
+ENTRY(ret_from_fork)
+ ld r0, @sp+
+ bl schedule_tail
+ GET_THREAD_INFO(r8)
+ bra syscall_exit
+
+/*
+ * Return to user mode is not as complex as all this looks,
+ * but we want the default path for a system call return to
+ * go as quickly as possible which is why some of this is
+ * less clear than it otherwise should be.
+ */
+
+ ; userspace resumption stub bypassing syscall exit tracing
+ ALIGN
+ret_from_exception:
+ preempt_stop(r4)
+ret_from_intr:
+ ld r4, PSW(sp)
+#ifdef CONFIG_ISA_M32R2
+ and3 r4, r4, #0x8800 ; check BSM and BPM bits
+#else
+ and3 r4, r4, #0x8000 ; check BSM bit
+#endif
+ beqz r4, resume_kernel
+ENTRY(resume_userspace)
+ CLI(r4) ; make sure we don't miss an interrupt
+ ; setting need_resched or sigpending
+ ; between sampling and the iret
+ GET_THREAD_INFO(r8)
+ ld r9, @(TI_FLAGS, r8)
+ and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done on
+ ; int/exception return?
+ bnez r4, work_pending
+ bra restore_all
+
+#ifdef CONFIG_PREEMPT
+ENTRY(resume_kernel)
+ GET_THREAD_INFO(r8)
+ ld r9, @(TI_PRE_COUNT, r8) ; non-zero preempt_count ?
+ bnez r9, restore_all
+need_resched:
+ ld r9, @(TI_FLAGS, r8) ; need_resched set ?
+ and3 r4, r9, #_TIF_NEED_RESCHED
+ beqz r4, restore_all
+ ld r4, PSW(sp) ; interrupts off (exception path) ?
+ and3 r4, r4, #0x4000
+ beqz r4, restore_all
+ LDIMM (r4, PREEMPT_ACTIVE)
+ st r4, @(TI_PRE_COUNT, r8)
+ STI(r4)
+ bl schedule
+ ldi r4, #0
+ st r4, @(TI_PRE_COUNT, r8)
+ CLI(r4)
+ bra need_resched
+#endif
+
+ ; system call handler stub
+ENTRY(system_call)
+ SWITCH_TO_KERNEL_STACK
+ SAVE_ALL
+ STI(r4) ; Enable interrupt
+ st sp, PTREGS(sp) ; implicit pt_regs parameter
+ cmpui r7, #NR_syscalls
+ bnc syscall_badsys
+ st r7, SYSCALL_NR(sp) ; syscall_nr
+ ; system call tracing in operation
+ GET_THREAD_INFO(r8)
+ ld r9, @(TI_FLAGS, r8)
+ and3 r4, r9, #_TIF_SYSCALL_TRACE
+ bnez r4, syscall_trace_entry
+syscall_call:
+ slli r7, #2 ; table jump for the system call
+ LDIMM (r4, sys_call_table)
+ add r7, r4
+ ld r7, @r7
+ jl r7 ; execute system call
+ st r0, R0(sp) ; save the return value
+syscall_exit:
+ CLI(r4) ; make sure we don't miss an interrupt
+ ; setting need_resched or sigpending
+ ; between sampling and the iret
+ ld r9, @(TI_FLAGS, r8)
+ and3 r4, r9, #_TIF_ALLWORK_MASK ; current->work
+ bnez r4, syscall_exit_work
+restore_all:
+ RESTORE_ALL
+
+ # perform work that needs to be done immediately before resumption
+ # r9 : frags
+ ALIGN
+work_pending:
+ and3 r4, r9, #_TIF_NEED_RESCHED
+ beqz r4, work_notifysig
+work_resched:
+ bl schedule
+ CLI(r4) ; make sure we don't miss an interrupt
+ ; setting need_resched or sigpending
+ ; between sampling and the iret
+ ld r9, @(TI_FLAGS, r8)
+ and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done other
+ ; than syscall tracing?
+ beqz r4, restore_all
+ and3 r4, r4, #_TIF_NEED_RESCHED
+ bnez r4, work_resched
+
+work_notifysig: ; deal with pending signals and
+ ; notify-resume requests
+ mv r0, sp ; arg1 : struct pt_regs *regs
+ ldi r1, #0 ; arg2 : sigset_t *oldset
+ mv r2, r9 ; arg3 : __u32 thread_info_flags
+ bl do_notify_resume
+ bra restore_all
+
+ ; perform syscall exit tracing
+ ALIGN
+syscall_trace_entry:
+ ldi r4, #-ENOSYS
+ st r4, R0(sp)
+ bl do_syscall_trace
+ ld r0, ORIG_R0(sp)
+ ld r1, R1(sp)
+ ld r2, R2(sp)
+ ld r3, R3(sp)
+ ld r4, R4(sp)
+ ld r5, R5(sp)
+ ld r6, R6(sp)
+ ld r7, SYSCALL_NR(sp)
+ cmpui r7, #NR_syscalls
+ bc syscall_call
+ bra syscall_exit
+
+ ; perform syscall exit tracing
+ ALIGN
+syscall_exit_work:
+ ld r9, @(TI_FLAGS, r8)
+ and3 r4, r9, #_TIF_SYSCALL_TRACE
+ beqz r4, work_pending
+ STI(r4) ; could let do_syscall_trace() call
+ ; schedule() instead
+ bl do_syscall_trace
+ bra resume_userspace
+
+ ALIGN
+syscall_fault:
+ SAVE_ALL
+ GET_THREAD_INFO(r8)
+ ldi r4, #-EFAULT
+ st r4, R0(sp)
+ bra resume_userspace
+
+ ALIGN
+syscall_badsys:
+ ldi r4, #-ENOSYS
+ st r4, R0(sp)
+ bra resume_userspace
+
+ .global eit_vector
+
+ .equ ei_vec_table, eit_vector + 0x0200
+
+/*
+ * EI handler routine
+ */
+ENTRY(ei_handler)
+#if defined(CONFIG_CHIP_M32700)
+ SWITCH_TO_KERNEL_STACK
+ ; WORKAROUND: force to clear SM bit and use the kernel stack (SPI).
+#endif
+ SAVE_ALL
+ mv r1, sp ; arg1(regs)
+#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
+ || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
+ || defined(CONFIG_CHIP_OPSP)
+
+; GET_ICU_STATUS;
+ seth r0, #shigh(M32R_ICU_ISTS_ADDR)
+ ld r0, @(low(M32R_ICU_ISTS_ADDR),r0)
+ st r0, @-sp
+#if defined(CONFIG_SMP)
+ /*
+ * If IRQ == 0 --> Nothing to do, Not write IMASK
+ * If IRQ == IPI --> Do IPI handler, Not write IMASK
+ * If IRQ != 0, IPI --> Do do_IRQ(), Write IMASK
+ */
+ slli r0, #4
+ srli r0, #24 ; r0(irq_num<<2)
+ ;; IRQ exist check
+#if defined(CONFIG_CHIP_M32700)
+ /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
+ beqz r0, 3f ; if (!irq_num) goto exit
+#else
+ beqz r0, 1f ; if (!irq_num) goto exit
+#endif /* WORKAROUND */
+ ;; IPI check
+ cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check
+ bc 2f
+ cmpi r0, #((M32R_IRQ_IPI7+1)<<2) ; ISN > IPI7 check
+ bnc 2f
+ LDIMM (r2, ei_vec_table)
+ add r2, r0
+ ld r2, @r2
+ beqz r2, 1f ; if (no IPI handler) goto exit
+ mv r0, r1 ; arg0(regs)
+ jl r2
+ .fillinsn
+1:
+ addi sp, #4
+ bra ret_to_intr
+#if defined(CONFIG_CHIP_M32700)
+ /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
+ .fillinsn
+3:
+ ld24 r14, #0x00070000
+ seth r0, #shigh(M32R_ICU_IMASK_ADDR)
+ st r14, @(low(M32R_ICU_IMASK_ADDR), r0)
+ addi sp, #4
+ bra ret_to_intr
+#endif /* WORKAROUND */
+ ;; do_IRQ
+ .fillinsn
+2:
+ srli r0, #2
+#if defined(CONFIG_PLAT_USRV)
+ add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
+ bnez r2, 9f
+ ; read ICU status register of PLD
+ seth r0, #high(PLD_ICUISTS)
+ or3 r0, r0, #low(PLD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ addi r0, #(M32700UT_PLD_IRQ_BASE)
+ .fillinsn
+9:
+#elif defined(CONFIG_PLAT_M32700UT)
+ add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
+ bnez r2, check_int0
+ ; read ICU status register of PLD
+ seth r0, #high(PLD_ICUISTS)
+ or3 r0, r0, #low(PLD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ addi r0, #(M32700UT_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int0:
+ add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
+ bnez r2, check_int2
+ ; read ICU status of LAN-board
+ seth r0, #high(M32700UT_LAN_ICUISTS)
+ or3 r0, r0, #low(M32700UT_LAN_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int2:
+ add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
+ bnez r2, check_end
+ ; read ICU status of LCD-board
+ seth r0, #high(M32700UT_LCD_ICUISTS)
+ or3 r0, r0, #low(M32700UT_LCD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_end:
+#elif defined(CONFIG_PLAT_OPSPUT)
+ add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
+ bnez r2, check_int0
+ ; read ICU status register of PLD
+ seth r0, #high(PLD_ICUISTS)
+ or3 r0, r0, #low(PLD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ addi r0, #(OPSPUT_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int0:
+ add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
+ bnez r2, check_int2
+ ; read ICU status of LAN-board
+ seth r0, #high(OPSPUT_LAN_ICUISTS)
+ or3 r0, r0, #low(OPSPUT_LAN_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int2:
+ add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
+ bnez r2, check_end
+ ; read ICU status of LCD-board
+ seth r0, #high(OPSPUT_LCD_ICUISTS)
+ or3 r0, r0, #low(OPSPUT_LCD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_end:
+#endif /* CONFIG_PLAT_OPSPUT */
+ bl do_IRQ ; r0(irq), r1(regs)
+#else /* not CONFIG_SMP */
+ srli r0, #22 ; r0(irq)
+#if defined(CONFIG_PLAT_USRV)
+ add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
+ bnez r2, 1f
+ ; read ICU status register of PLD
+ seth r0, #high(PLD_ICUISTS)
+ or3 r0, r0, #low(PLD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ addi r0, #(M32700UT_PLD_IRQ_BASE)
+ .fillinsn
+1:
+#elif defined(CONFIG_PLAT_M32700UT)
+ add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
+ bnez r2, check_int0
+ ; read ICU status register of PLD
+ seth r0, #high(PLD_ICUISTS)
+ or3 r0, r0, #low(PLD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ addi r0, #(M32700UT_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int0:
+ add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
+ bnez r2, check_int2
+ ; read ICU status of LAN-board
+ seth r0, #high(M32700UT_LAN_ICUISTS)
+ or3 r0, r0, #low(M32700UT_LAN_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int2:
+ add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
+ bnez r2, check_end
+ ; read ICU status of LCD-board
+ seth r0, #high(M32700UT_LCD_ICUISTS)
+ or3 r0, r0, #low(M32700UT_LCD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_end:
+#elif defined(CONFIG_PLAT_OPSPUT)
+ add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
+ bnez r2, check_int0
+ ; read ICU status register of PLD
+ seth r0, #high(PLD_ICUISTS)
+ or3 r0, r0, #low(PLD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ addi r0, #(OPSPUT_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int0:
+ add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
+ bnez r2, check_int2
+ ; read ICU status of LAN-board
+ seth r0, #high(OPSPUT_LAN_ICUISTS)
+ or3 r0, r0, #low(OPSPUT_LAN_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_int2:
+ add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
+ bnez r2, check_end
+ ; read ICU status of LCD-board
+ seth r0, #high(OPSPUT_LCD_ICUISTS)
+ or3 r0, r0, #low(OPSPUT_LCD_ICUISTS)
+ lduh r0, @r0
+ slli r0, #21
+ srli r0, #27 ; ISN
+ add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE)
+ bra check_end
+ .fillinsn
+check_end:
+#endif /* CONFIG_PLAT_OPSPUT */
+ bl do_IRQ
+#endif /* CONFIG_SMP */
+ ld r14, @sp+
+ seth r0, #shigh(M32R_ICU_IMASK_ADDR)
+ st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
+#else
+#error no chip configuration
+#endif
+ret_to_intr:
+ bra ret_from_intr
+
+/*
+ * Default EIT handler
+ */
+ ALIGN
+int_msg:
+ .asciz "Unknown interrupt\n"
+ .byte 0
+
+ENTRY(default_eit_handler)
+ push r0
+ mvfc r0, psw
+ push r1
+ push r2
+ push r3
+ push r0
+ LDIMM (r0, __KERNEL_DS)
+ mv r0, r1
+ mv r0, r2
+ LDIMM (r0, int_msg)
+ bl printk
+ pop r0
+ pop r3
+ pop r2
+ pop r1
+ mvtc r0, psw
+ pop r0
+infinit:
+ bra infinit
+
+#ifdef CONFIG_MMU
+/*
+ * Access Exception handler
+ */
+ENTRY(ace_handler)
+ SWITCH_TO_KERNEL_STACK
+ SAVE_ALL
+
+ seth r2, #shigh(MMU_REG_BASE) /* Check status register */
+ ld r4, @(low(MESTS_offset),r2)
+ st r4, @(low(MESTS_offset),r2)
+ srl3 r1, r4, #4
+#ifdef CONFIG_CHIP_M32700
+ and3 r1, r1, #0x0000ffff
+ ; WORKAROUND: ignore TME bit for the M32700(TS1).
+#endif /* CONFIG_CHIP_M32700 */
+ beqz r1, inst
+oprand:
+ ld r2, @(low(MDEVA_offset),r2) ; set address
+ srli r2, #12
+ slli r2, #12
+ srli r1, #1
+ bra 1f
+inst:
+ and3 r1, r4, #2
+ srli r1, #1
+ or3 r1, r1, #8
+ mvfc r2, bpc ; set address
+ .fillinsn
+1:
+ mvfc r3, psw
+ mv r0, sp
+ and3 r3, r3, 0x800
+ srli r3, #9
+ or r1, r3
+ /*
+ * do_page_fault():
+ * r0 : struct pt_regs *regs
+ * r1 : unsigned long error-code
+ * r2 : unsigned long address
+ * error-code:
+ * +------+------+------+------+
+ * | bit3 | bit2 | bit1 | bit0 |
+ * +------+------+------+------+
+ * bit 3 == 0:means data, 1:means instruction
+ * bit 2 == 0:means kernel, 1:means user-mode
+ * bit 1 == 0:means read, 1:means write
+ * bit 0 == 0:means no page found 1:means protection fault
+ *
+ */
+ bl do_page_fault
+ bra ret_from_intr
+#endif /* CONFIG_MMU */
+
+
+ENTRY(alignment_check)
+/* void alignment_check(int error_code) */
+ SWITCH_TO_KERNEL_STACK
+ SAVE_ALL
+ ldi r1, #0x30 ; error_code
+ mv r0, sp ; pt_regs
+ bl do_alignment_check
+error_code:
+ bra ret_from_exception
+
+ENTRY(rie_handler)
+/* void rie_handler(int error_code) */
+ SWITCH_TO_KERNEL_STACK
+ SAVE_ALL
+ mvfc r0, bpc
+ ld r1, @r0
+ seth r0, #0xa0f0
+ st r1, @r0
+ ldi r1, #0x20 ; error_code
+ mv r0, sp ; pt_regs
+ bl do_rie_handler
+ bra error_code
+
+ENTRY(pie_handler)
+/* void pie_handler(int error_code) */
+ SWITCH_TO_KERNEL_STACK
+ SAVE_ALL
+ ldi r1, #0 ; error_code ; FIXME
+ mv r0, sp ; pt_regs
+ bl do_pie_handler
+ bra error_code
+
+ENTRY(debug_trap)
+ .global withdraw_debug_trap
+ /* void debug_trap(void) */
+ SWITCH_TO_KERNEL_STACK
+ SAVE_ALL
+ mv r0, sp ; pt_regs
+ bl withdraw_debug_trap
+ ldi r1, #0 ; error_code
+ mv r0, sp ; pt_regs
+ bl do_debug_trap
+ bra error_code
+
+
+/* Cache flushing handler */
+ENTRY(cache_flushing_handler)
+ .global _flush_cache_all
+ /* void _flush_cache_all(void); */
+ SWITCH_TO_KERNEL_STACK
+ push r0
+ push r1
+ push r2
+ push r3
+ push r4
+ push r5
+ push r6
+ push r7
+ push lr
+ bl _flush_cache_all
+ pop lr
+ pop r7
+ pop r6
+ pop r5
+ pop r4
+ pop r3
+ pop r2
+ pop r1
+ pop r0
+ rte
+
+.data
+ENTRY(sys_call_table)
+ .long sys_restart_syscall /* 0 - old "setup()" system call*/
+ .long sys_exit
+ .long sys_fork
+ .long sys_read
+ .long sys_write
+ .long sys_open /* 5 */
+ .long sys_close
+ .long sys_waitpid
+ .long sys_creat
+ .long sys_link
+ .long sys_unlink /* 10 */
+ .long sys_execve
+ .long sys_chdir
+ .long sys_time
+ .long sys_mknod
+ .long sys_chmod /* 15 */
+ .long sys_lchown
+ .long sys_ni_syscall /* old break syscall holder */
+ .long sys_stat
+ .long sys_lseek
+ .long sys_getpid /* 20 */
+ .long sys_mount
+ .long sys_oldumount
+ .long sys_setuid
+ .long sys_getuid
+ .long sys_stime /* 25 */
+ .long sys_ptrace
+ .long sys_alarm
+ .long sys_fstat
+ .long sys_pause
+ .long sys_utime /* 30 */
+ .long sys_cacheflush /* for M32R */ /* old stty syscall holder */
+ .long sys_cachectl /* for M32R */ /* old gtty syscall holder */
+ .long sys_access
+ .long sys_nice
+ .long sys_ni_syscall /* 35 - old ftime syscall holder */
+ .long sys_sync
+ .long sys_kill
+ .long sys_rename
+ .long sys_mkdir
+ .long sys_rmdir /* 40 */
+ .long sys_dup
+ .long sys_pipe
+ .long sys_times
+ .long sys_ni_syscall /* old prof syscall holder */
+ .long sys_brk /* 45 */
+ .long sys_setgid
+ .long sys_getgid
+ .long sys_signal
+ .long sys_geteuid
+ .long sys_getegid /* 50 */
+ .long sys_acct
+ .long sys_umount /* recycled never used phys() */
+ .long sys_ni_syscall /* old lock syscall holder */
+ .long sys_ioctl
+ .long sys_fcntl /* 55 */
+ .long sys_ni_syscall /* old mpx syscall holder */
+ .long sys_setpgid
+ .long sys_ni_syscall /* old ulimit syscall holder */
+ .long sys_ni_syscall /* sys_olduname */
+ .long sys_umask /* 60 */
+ .long sys_chroot
+ .long sys_ustat
+ .long sys_dup2
+ .long sys_getppid
+ .long sys_getpgrp /* 65 */
+ .long sys_setsid
+ .long sys_sigaction
+ .long sys_sgetmask
+ .long sys_ssetmask
+ .long sys_setreuid /* 70 */
+ .long sys_setregid
+ .long sys_sigsuspend
+ .long sys_sigpending
+ .long sys_sethostname
+ .long sys_setrlimit /* 75 */
+ .long sys_getrlimit
+ .long sys_getrusage
+ .long sys_gettimeofday
+ .long sys_settimeofday
+ .long sys_getgroups /* 80 */
+ .long sys_setgroups
+ .long sys_ni_syscall /* sys_oldselect */
+ .long sys_symlink
+ .long sys_lstat
+ .long sys_readlink /* 85 */
+ .long sys_uselib
+ .long sys_swapon
+ .long sys_reboot
+ .long old_readdir
+ .long sys_ni_syscall /* 90 - old_mmap syscall holder */
+ .long sys_munmap
+ .long sys_truncate
+ .long sys_ftruncate
+ .long sys_fchmod
+ .long sys_fchown /* 95 */
+ .long sys_getpriority
+ .long sys_setpriority
+ .long sys_ni_syscall /* old profil syscall holder */
+ .long sys_statfs
+ .long sys_fstatfs /* 100 */
+ .long sys_ni_syscall /* ioperm */
+ .long sys_socketcall
+ .long sys_syslog
+ .long sys_setitimer
+ .long sys_getitimer /* 105 */
+ .long sys_newstat
+ .long sys_newlstat
+ .long sys_newfstat
+ .long sys_uname
+ .long sys_ni_syscall /* 110 - iopl */
+ .long sys_vhangup
+ .long sys_ni_syscall /* for idle */
+ .long sys_ni_syscall /* for vm86old */
+ .long sys_wait4
+ .long sys_swapoff /* 115 */
+ .long sys_sysinfo
+ .long sys_ipc
+ .long sys_fsync
+ .long sys_sigreturn
+ .long sys_clone /* 120 */
+ .long sys_setdomainname
+ .long sys_newuname
+ .long sys_ni_syscall /* sys_modify_ldt */
+ .long sys_adjtimex
+ .long sys_mprotect /* 125 */
+ .long sys_sigprocmask
+ .long sys_ni_syscall /* sys_create_module */
+ .long sys_init_module
+ .long sys_delete_module
+ .long sys_ni_syscall /* 130 sys_get_kernel_syms */
+ .long sys_quotactl
+ .long sys_getpgid
+ .long sys_fchdir
+ .long sys_bdflush
+ .long sys_sysfs /* 135 */
+ .long sys_personality
+ .long sys_ni_syscall /* for afs_syscall */
+ .long sys_setfsuid
+ .long sys_setfsgid
+ .long sys_llseek /* 140 */
+ .long sys_getdents
+ .long sys_select
+ .long sys_flock
+ .long sys_msync
+ .long sys_readv /* 145 */
+ .long sys_writev
+ .long sys_getsid
+ .long sys_fdatasync
+ .long sys_sysctl
+ .long sys_mlock /* 150 */
+ .long sys_munlock
+ .long sys_mlockall
+ .long sys_munlockall
+ .long sys_sched_setparam
+ .long sys_sched_getparam /* 155 */
+ .long sys_sched_setscheduler
+ .long sys_sched_getscheduler
+ .long sys_sched_yield
+ .long sys_sched_get_priority_max
+ .long sys_sched_get_priority_min /* 160 */
+ .long sys_sched_rr_get_interval
+ .long sys_nanosleep
+ .long sys_mremap
+ .long sys_setresuid
+ .long sys_getresuid /* 165 */
+ .long sys_tas /* vm86 */
+ .long sys_ni_syscall /* sys_query_module */
+ .long sys_poll
+ .long sys_nfsservctl
+ .long sys_setresgid /* 170 */
+ .long sys_getresgid
+ .long sys_prctl
+ .long sys_rt_sigreturn
+ .long sys_rt_sigaction
+ .long sys_rt_sigprocmask /* 175 */
+ .long sys_rt_sigpending
+ .long sys_rt_sigtimedwait
+ .long sys_rt_sigqueueinfo
+ .long sys_rt_sigsuspend
+ .long sys_pread64 /* 180 */
+ .long sys_pwrite64
+ .long sys_chown
+ .long sys_getcwd
+ .long sys_capget
+ .long sys_capset /* 185 */
+ .long sys_sigaltstack
+ .long sys_sendfile
+ .long sys_ni_syscall /* streams1 */
+ .long sys_ni_syscall /* streams2 */
+ .long sys_vfork /* 190 */
+ .long sys_getrlimit
+ .long sys_mmap2
+ .long sys_truncate64
+ .long sys_ftruncate64
+ .long sys_stat64 /* 195 */
+ .long sys_lstat64
+ .long sys_fstat64
+ .long sys_lchown
+ .long sys_getuid
+ .long sys_getgid /* 200 */
+ .long sys_geteuid
+ .long sys_getegid
+ .long sys_setreuid
+ .long sys_setregid
+ .long sys_getgroups /* 205 */
+ .long sys_setgroups
+ .long sys_fchown
+ .long sys_setresuid
+ .long sys_getresuid
+ .long sys_setresgid /* 210 */
+ .long sys_getresgid
+ .long sys_chown
+ .long sys_setuid
+ .long sys_setgid
+ .long sys_setfsuid /* 215 */
+ .long sys_setfsgid
+ .long sys_pivot_root
+ .long sys_mincore
+ .long sys_madvise
+ .long sys_getdents64 /* 220 */
+ .long sys_fcntl64
+ .long sys_ni_syscall /* reserved for TUX */
+ .long sys_ni_syscall /* Reserved for Security */
+ .long sys_gettid
+ .long sys_readahead /* 225 */
+ .long sys_setxattr
+ .long sys_lsetxattr
+ .long sys_fsetxattr
+ .long sys_getxattr
+ .long sys_lgetxattr /* 230 */
+ .long sys_fgetxattr
+ .long sys_listxattr
+ .long sys_llistxattr
+ .long sys_flistxattr
+ .long sys_removexattr /* 235 */
+ .long sys_lremovexattr
+ .long sys_fremovexattr
+ .long sys_tkill
+ .long sys_sendfile64
+ .long sys_futex /* 240 */
+ .long sys_sched_setaffinity
+ .long sys_sched_getaffinity
+ .long sys_ni_syscall /* reserved for "set_thread_area" system call */
+ .long sys_ni_syscall /* reserved for "get_thread_area" system call */
+ .long sys_io_setup /* 245 */
+ .long sys_io_destroy
+ .long sys_io_getevents
+ .long sys_io_submit
+ .long sys_io_cancel
+ .long sys_fadvise64 /* 250 */
+ .long sys_ni_syscall
+ .long sys_exit_group
+ .long sys_lookup_dcookie
+ .long sys_epoll_create
+ .long sys_epoll_ctl /* 255 */
+ .long sys_epoll_wait
+ .long sys_remap_file_pages
+ .long sys_set_tid_address
+ .long sys_timer_create
+ .long sys_timer_settime /* 260 */
+ .long sys_timer_gettime
+ .long sys_timer_getoverrun
+ .long sys_timer_delete
+ .long sys_clock_settime
+ .long sys_clock_gettime /* 265 */
+ .long sys_clock_getres
+ .long sys_clock_nanosleep
+ .long sys_statfs64
+ .long sys_fstatfs64
+ .long sys_tgkill /* 270 */
+ .long sys_utimes
+ .long sys_fadvise64_64
+ .long sys_ni_syscall /* Reserved for sys_vserver */
+ .long sys_ni_syscall /* Reserved for sys_mbind */
+ .long sys_ni_syscall /* Reserved for sys_get_mempolicy */
+ .long sys_ni_syscall /* Reserved for sys_set_mempolicy */
+ .long sys_mq_open
+ .long sys_mq_unlink
+ .long sys_mq_timedsend
+ .long sys_mq_timedreceive /* 280 */
+ .long sys_mq_notify
+ .long sys_mq_getsetattr
+ .long sys_ni_syscall /* reserved for kexec */
+ .long sys_waitid
+
+syscall_table_size=(.-sys_call_table)
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/head.S
+ *
+ * M32R startup code.
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ */
+
+/* $Id$ */
+
+#include <linux/init.h>
+__INIT
+__INITDATA
+
+ .text
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/segment.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/assembler.h>
+#include <asm/m32r.h>
+#include <asm/mmu_context.h>
+
+/*
+ * References to members of the boot_cpu_data structure.
+ */
+ .text
+ .global start_kernel
+ .global __bss_start
+ .global _end
+ENTRY(stext)
+ENTRY(_stext)
+ENTRY(startup_32)
+ /* Setup up the stack pointer */
+ LDIMM (r0, spi_stack_top)
+ LDIMM (r1, spu_stack_top)
+ mvtc r0, spi
+ mvtc r1, spu
+
+ /* Initilalize PSW */
+ ldi r0, #0x0000 /* use SPI, disable EI */
+ mvtc r0, psw
+
+ /* Set up the stack pointer */
+ LDIMM (r0, stack_start)
+ ld r0, @r0
+ mvtc r0, spi
+
+/*
+ * Clear BSS first so that there are no surprises...
+ */
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ LDIMM (r2, __bss_start)
+ LDIMM (r3, _end)
+ sub r3, r2 ; BSS size in bytes
+ ; R4 = BSS size in longwords (rounded down)
+ mv r4, r3 || ldi r1, #0
+ srli r4, #4 || addi r2, #-4
+ beqz r4, .Lendloop1
+.Lloop1:
+#ifndef CONFIG_CHIP_M32310
+ ; Touch memory for the no-write-allocating cache.
+ ld r0, @(4,r2)
+#endif
+ st r1, @+r2 || addi r4, #-1
+ st r1, @+r2
+ st r1, @+r2
+ st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
+ bnc .Lloop1
+.Lendloop1:
+ and3 r4, r3, #15
+ addi r2, #4
+ beqz r4, .Lendloop2
+.Lloop2:
+ stb r1, @r2 || addi r4, #-1
+ addi r2, #1
+ bnez r4, .Lloop2
+.Lendloop2:
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ LDIMM (r2, __bss_start)
+ LDIMM (r3, _end)
+ sub r3, r2 ; BSS size in bytes
+ mv r4, r3
+ srli r4, #2 ; R4 = BSS size in longwords (rounded down)
+ ldi r1, #0 ; clear R1 for longwords store
+ addi r2, #-4 ; account for pre-inc store
+ beqz r4, .Lendloop1 ; any more to go?
+.Lloop1:
+ st r1, @+r2 ; yep, zero out another longword
+ addi r4, #-1 ; decrement count
+ bnez r4, .Lloop1 ; go do some more
+.Lendloop1:
+ and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
+ addi r2, #4 ; account for pre-inc store
+ beqz r4, .Lendloop2 ; any more to go?
+.Lloop2:
+ stb r1, @r2 ; yep, zero out another byte
+ addi r2, #1 ; bump address
+ addi r4, #-1 ; decrement count
+ bnez r4, .Lloop2 ; go do some more
+.Lendloop2:
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+#if 0 /* M32R_FIXME */
+/*
+ * Copy data segment from ROM to RAM.
+ */
+ .global ROM_D, TOP_DATA, END_DATA
+
+ LDIMM (r1, ROM_D)
+ LDIMM (r2, TOP_DATA)
+ LDIMM (r3, END_DATA)
+ addi r2, #-4
+ addi r3, #-4
+loop1:
+ ld r0, @r1+
+ st r0, @+r2
+ cmp r2, r3
+ bc loop1
+#endif /* 0 */
+
+/* Jump to kernel */
+ LDIMM (r2, start_kernel)
+ jl r2
+ .fillinsn
+1:
+ bra 1b ; main should never return here, but
+ ; just in case, we know what happens.
+
+#ifdef CONFIG_SMP
+/*
+ * AP startup routine
+ */
+ .text
+ .global eit_vector
+ENTRY(startup_AP)
+;; setup EVB
+ LDIMM (r4, eit_vector)
+ mvtc r4, cr5
+
+;; enable MMU
+ LDIMM (r2, init_tlb)
+ jl r2
+ seth r4, #high(MATM)
+ or3 r4, r4, #low(MATM)
+ ldi r5, #0x01
+ st r5, @r4 ; Set MATM Reg(T bit ON)
+ ld r6, @r4 ; MATM Check
+ LDIMM (r5, 1f)
+ jmp r5 ; enable MMU
+ nop
+ .fillinsn
+1:
+;; ISN check
+ ld r6, @r4 ; MATM Check
+ seth r4, #high(M32R_ICU_ISTS_ADDR)
+ or3 r4, r4, #low(M32R_ICU_ISTS_ADDR)
+ ld r5, @r4 ; Read ISTSi reg.
+ mv r6, r5
+ slli r5, #13 ; PIML check
+ srli r5, #13 ;
+ seth r4, #high(M32R_ICU_IMASK_ADDR)
+ or3 r4, r4, #low(M32R_ICU_IMASK_ADDR)
+ st r5, @r4 ; Write IMASKi reg.
+ slli r6, #4 ; ISN check
+ srli r6, #26 ;
+ seth r4, #high(M32R_IRQ_IPI5)
+ or3 r4, r4, #low(M32R_IRQ_IPI5)
+ bne r4, r6, 2f ; if (ISN != CPU_BOOT_IPI) goto sleep;
+
+;; check cpu_bootout_map and set cpu_bootin_map
+ LDIMM (r4, cpu_bootout_map)
+ ld r4, @r4
+ seth r5, #high(M32R_CPUID_PORTL)
+ or3 r5, r5, #low(M32R_CPUID_PORTL)
+ ld r5, @r5
+ ldi r6, #1
+ sll r6, r5
+ and r4, r6
+ beqz r4, 2f
+ LDIMM (r4, cpu_bootin_map)
+ ld r5, @r4
+ or r5, r6
+ st r6, @r4
+
+;; clear PSW
+ ldi r4, #0
+ mvtc r4, psw
+
+;; setup SPI
+ LDIMM (r4, stack_start)
+ ld r4, @r4
+ mvtc r4, spi
+
+;; setup BPC (start_secondary)
+ LDIMM (r4, start_secondary)
+ mvtc r4, bpc
+
+ rte ; goto startup_secondary
+ nop
+ nop
+
+ .fillinsn
+2:
+ ;; disable MMU
+ seth r4, #high(MATM)
+ or3 r4, r4, #low(MATM)
+ ldi r5, #0
+ st r5, @r4 ; Set MATM Reg(T bit OFF)
+ ld r6, @r4 ; MATM Check
+ LDIMM (r4, 3f)
+ seth r5, #high(__PAGE_OFFSET)
+ or3 r5, r5, #low(__PAGE_OFFSET)
+ not r5, r5
+ and r4, r5
+ jmp r4 ; disable MMU
+ nop
+ .fillinsn
+3:
+ ;; SLEEP and wait IPI
+ LDIMM (r4, AP_loop)
+ seth r5, #high(__PAGE_OFFSET)
+ or3 r5, r5, #low(__PAGE_OFFSET)
+ not r5, r5
+ and r4, r5
+ jmp r4
+ nop
+ nop
+#endif /* CONFIG_SMP */
+
+ENTRY(stack_start)
+ .long init_thread_union+8192
+ .long __KERNEL_DS
+
+/*
+ * This is initialized to create a identity-mapping at 0-4M (for bootup
+ * purposes) and another mapping of the 0-4M area at virtual address
+ * PAGE_OFFSET.
+ */
+ .text
+
+#define MOUNT_ROOT_RDONLY 1
+#define RAMDISK_FLAGS 0 ; 1024KB
+#define ORIG_ROOT_DEV 0x0100 ; /dev/ram0 (major:01, minor:00)
+#define LOADER_TYPE 1 ; (??? - non-zero value seems
+ ; to be needed to boot from initrd)
+
+#define COMMAND_LINE ""
+
+ .section .empty_zero_page, "aw"
+ENTRY(empty_zero_page)
+ .long MOUNT_ROOT_RDONLY /* offset: +0x00 */
+ .long RAMDISK_FLAGS
+ .long ORIG_ROOT_DEV
+ .long LOADER_TYPE
+ .long 0 /* INITRD_START */ /* +0x10 */
+ .long 0 /* INITRD_SIZE */
+ .long 0 /* CPU_CLOCK */
+ .long 0 /* BUS_CLOCK */
+ .long 0 /* TIMER_DIVIDE */ /* +0x20 */
+ .balign 256,0
+ .asciz COMMAND_LINE
+ .byte 0
+ .balign 4096,0,4096
+
+/*------------------------------------------------------------------------
+ * Stack area
+ */
+ .section .spi
+ ALIGN
+ .global spi_stack_top
+ .zero 1024
+spi_stack_top:
+
+ .section .spu
+ ALIGN
+ .global spu_stack_top
+ .zero 1024
+spu_stack_top:
+
+ .end
--- /dev/null
+/* orig : i386 init_task.c */
+
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/init_task.h>
+#include <linux/fs.h>
+#include <linux/mqueue.h>
+
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+
+static struct fs_struct init_fs = INIT_FS;
+static struct files_struct init_files = INIT_FILES;
+static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
+static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
+struct mm_struct init_mm = INIT_MM(init_mm);
+
+EXPORT_SYMBOL(init_mm);
+
+/*
+ * Initial thread structure.
+ *
+ * We need to make sure that this is 8192-byte aligned due to the
+ * way process stacks are handled. This is done by having a special
+ * "init_task" linker map entry..
+ */
+union thread_union init_thread_union
+ __attribute__((__section__(".data.init_task"))) =
+ { INIT_THREAD_INFO(init_task) };
+
+/*
+ * Initial task structure.
+ *
+ * All other task structs will be allocated on slabs in fork.c
+ */
+struct task_struct init_task = INIT_TASK(init_task);
+
+EXPORT_SYMBOL(init_task);
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/io_mappi.c
+ *
+ * Typical I/O routines for M32700UT board.
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+#include <linux/types.h>
+
+#define M32R_PCC_IOMAP_SIZE 0x1000
+
+#define M32R_PCC_IOSTART0 0x1000
+#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
+
+extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
+#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
+
+#define PORT2ADDR(port) _port2addr(port)
+#define PORT2ADDR_USB(port) _port2addr_usb(port)
+
+static __inline__ void *_port2addr(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET);
+}
+
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+static __inline__ void *__port2addr_ata(unsigned long port)
+{
+ static int dummy_reg;
+
+ switch (port) {
+ case 0x1f0: return (void *)0xac002000;
+ case 0x1f1: return (void *)0xac012800;
+ case 0x1f2: return (void *)0xac012002;
+ case 0x1f3: return (void *)0xac012802;
+ case 0x1f4: return (void *)0xac012004;
+ case 0x1f5: return (void *)0xac012804;
+ case 0x1f6: return (void *)0xac012006;
+ case 0x1f7: return (void *)0xac012806;
+ case 0x3f6: return (void *)0xac01200e;
+ default: return (void *)&dummy_reg;
+ }
+}
+#endif
+
+/*
+ * M32700UT-LAN is located in the extended bus space
+ * from 0x10000000 to 0x13ffffff on physical address.
+ * The base address of LAN controller(LAN91C111) is 0x300.
+ */
+#define LAN_IOSTART 0x300
+#define LAN_IOEND 0x320
+static __inline__ void *_port2addr_ne(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET + 0x10000000);
+}
+static __inline__ void *_port2addr_usb(unsigned long port)
+{
+ return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
+}
+
+static __inline__ void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+/*
+ * NIC I/O function
+ */
+
+#define PORT2ADDR_NE(port) _port2addr_ne(port)
+
+static __inline__ unsigned char _ne_inb(void *portp)
+{
+ return *(volatile unsigned char *)portp;
+}
+
+static __inline__ unsigned short _ne_inw(void *portp)
+{
+ return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
+}
+
+static __inline__ void _ne_insb(void *portp, void * addr, unsigned long count)
+{
+ unsigned char *buf = (unsigned char *)addr;
+
+ while (count--) *buf++ = _ne_inb(portp);
+}
+
+static __inline__ void _ne_outb(unsigned char b, void *portp)
+{
+ *(volatile unsigned char *)portp = b;
+}
+
+static __inline__ void _ne_outw(unsigned short w, void *portp)
+{
+ *(volatile unsigned short *)portp = cpu_to_le16(w);
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ return _ne_inb(PORT2ADDR_NE(port));
+
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ return *(volatile unsigned char *)__port2addr_ata(port);
+ }
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ return _ne_inw(PORT2ADDR_NE(port));
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ return *(volatile unsigned short *)__port2addr_ata(port);
+ }
+#endif
+#if defined(CONFIG_USB)
+ else if(port >= 0x340 && port < 0x3a0)
+ return *(volatile unsigned short *)PORT2ADDR_USB(port);
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned long l;
+ pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else
+#endif
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char v;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ v = _ne_inb(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ return *(volatile unsigned char *)__port2addr_ata(port);
+ } else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+ v = *(volatile unsigned char *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short v;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ v = _ne_inw(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ return *(volatile unsigned short *)__port2addr_ata(port);
+ } else
+#endif
+#if defined(CONFIG_USB)
+ if(port >= 0x340 && port < 0x3a0)
+ return *(volatile unsigned short *)PORT2ADDR_USB(port);
+ else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ v = *(volatile unsigned short *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v;
+
+ v = *(volatile unsigned long *)PORT2ADDR(port);
+ delay();
+ return (v);
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ *(volatile unsigned char *)__port2addr_ata(port) = b;
+ } else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ *(volatile unsigned short *)__port2addr_ata(port) = w;
+ } else
+#endif
+#if defined(CONFIG_USB)
+ if(port >= 0x340 && port < 0x3a0)
+ *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
+ else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
+ } else
+#endif
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ *(volatile unsigned char *)__port2addr_ata(port) = b;
+ } else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ *(volatile unsigned short *)__port2addr_ata(port) = w;
+ } else
+#endif
+#if defined(CONFIG_USB)
+ if(port >= 0x340 && port < 0x3a0)
+ *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
+ else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_insb(PORT2ADDR_NE(port), addr, count);
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ unsigned char *buf = addr;
+ unsigned char *portp = __port2addr_ata(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+ }
+#endif
+ else {
+ unsigned char *buf = addr;
+ unsigned char *portp = PORT2ADDR(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND) {
+ /*
+ * This portion is only used by smc91111.c to read data
+ * from the DATA_REG. Do not swap the data.
+ */
+ portp = PORT2ADDR_NE(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ portp = __port2addr_ata(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outb(*buf++, portp);
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ portp = __port2addr_ata(port);
+ while(count--) *(volatile unsigned char *)portp = *buf++;
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND) {
+ /*
+ * This portion is only used by smc91111.c to write data
+ * into the DATA_REG. Do not swap the data.
+ */
+ portp = PORT2ADDR_NE(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
+ } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
+ portp = __port2addr_ata(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned long *)portp = *buf++;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/io_mappi.c
+ *
+ * Typical I/O routines for Mappi board.
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ */
+
+/* $Id: io_mappi.c,v 1.9 2003/12/02 07:18:08 fujiwara Exp $ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+#include <linux/types.h>
+
+#define M32R_PCC_IOMAP_SIZE 0x1000
+
+#define M32R_PCC_IOSTART0 0x1000
+#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
+#define M32R_PCC_IOSTART1 0x2000
+#define M32R_PCC_IOEND1 (M32R_PCC_IOSTART1 + M32R_PCC_IOMAP_SIZE - 1)
+
+extern void pcc_ioread(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite(int, unsigned long, void *, size_t, size_t, int);
+#endif /* CONFIG_PCMCIA && CONFIG_M32RPCC */
+
+#define PORT2ADDR(port) _port2addr(port)
+
+static __inline__ void *_port2addr(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET);
+}
+
+static __inline__ void *_port2addr_ne(unsigned long port)
+{
+ return (void *)((port<<1) + NONCACHE_OFFSET + 0x0C000000);
+}
+
+static __inline__ void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+/*
+ * NIC I/O function
+ */
+
+#define PORT2ADDR_NE(port) _port2addr_ne(port)
+
+static __inline__ unsigned char _ne_inb(void *portp)
+{
+ return (unsigned char) *(volatile unsigned short *)portp;
+}
+
+static __inline__ unsigned short _ne_inw(void *portp)
+{
+ unsigned short tmp;
+
+ tmp = *(volatile unsigned short *)portp;
+ return le16_to_cpu(tmp);
+}
+
+static __inline__ void _ne_outb(unsigned char b, void *portp)
+{
+ *(volatile unsigned short *)portp = (unsigned short)b;
+}
+
+static __inline__ void _ne_outw(unsigned short w, void *portp)
+{
+ *(volatile unsigned short *)portp = cpu_to_le16(w);
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ return _ne_inb(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ unsigned char b;
+ pcc_ioread(1, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ return _ne_inw(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ unsigned short w;
+ pcc_ioread(1, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned long l;
+ pcc_ioread(0, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ unsigned short l;
+ pcc_ioread(1, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else
+#endif
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char v;
+
+ if (port >= 0x300 && port < 0x320)
+ v = _ne_inb(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ unsigned char b;
+ pcc_ioread(1, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+ v = *(volatile unsigned char *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short v;
+
+ if (port >= 0x300 && port < 0x320)
+ v = _ne_inw(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ unsigned short w;
+ pcc_ioread(1, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ v = *(volatile unsigned short *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v;
+
+ v = *(volatile unsigned long *)PORT2ADDR(port);
+ delay();
+ return (v);
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, &b, sizeof(b), 1, 0);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, &w, sizeof(w), 1, 0);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, &l, sizeof(l), 1, 0);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, &l, sizeof(l), 1, 0);
+ } else
+#endif
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, &b, sizeof(b), 1, 0);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, &w, sizeof(w), 1, 0);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= 0x300 && port < 0x320){
+ portp = PORT2ADDR_NE(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_ioread(1, port, (void *)addr, sizeof(unsigned char), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= 0x300 && port < 0x320) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) *buf++ = _ne_inw(portp);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread(0, port, (void *)addr, sizeof(unsigned short), count, 1);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_ioread(1, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= 0x300 && port < 0x320) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outb(*buf++, portp);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, (void *)addr, sizeof(unsigned char), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= 0x300 && port < 0x320) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outw(*buf++, portp);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32RPCC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite(0, port, (void *)addr, sizeof(unsigned short), count, 1);
+ } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
+ pcc_iowrite(1, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned long *)portp = *buf++;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/io_mappi2.c
+ *
+ * Typical I/O routines for Mappi2 board.
+ *
+ * Copyright (c) 2001-2003 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Mamoru Sakugawa
+ */
+
+/* $Id:$ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+#include <linux/types.h>
+
+#define M32R_PCC_IOMAP_SIZE 0x1000
+
+#define M32R_PCC_IOSTART0 0x1000
+#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
+
+extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
+#endif /* CONFIG_PCMCIA && CONFIG_MAPPI2_CFC */
+
+#define PORT2ADDR(port) _port2addr(port)
+#define PORT2ADDR_NE(port) _port2addr_ne(port)
+#define PORT2ADDR_USB(port) _port2addr_usb(port)
+
+static __inline__ void *_port2addr(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET);
+}
+
+#define LAN_IOSTART 0x300
+#define LAN_IOEND 0x320
+#ifdef CONFIG_CHIP_OPSP
+static __inline__ void *_port2addr_ne(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET + 0x10000000);
+}
+#else
+static __inline__ void *_port2addr_ne(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET + 0x04000000);
+}
+#endif
+static __inline__ void *_port2addr_usb(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET + 0x14000000);
+}
+static __inline__ void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+/*
+ * NIC I/O function
+ */
+
+static __inline__ unsigned char _ne_inb(void *portp)
+{
+ return (unsigned char) *(volatile unsigned char *)portp;
+}
+
+static __inline__ unsigned short _ne_inw(void *portp)
+{
+#if 1 /* byte swap */
+ unsigned short tmp,tmp2;
+ tmp = *(volatile unsigned short *)portp;
+ tmp2 = (tmp>>8|tmp<<8);
+ return tmp2;
+#else
+ return *(volatile unsigned short *)portp;
+#endif
+}
+
+static __inline__ void _ne_insb(void *portp, void * addr, unsigned long count)
+{
+ unsigned short tmp;
+ unsigned char *buf = addr;
+
+ tmp = *(volatile unsigned char *)portp;
+ while (count--) *buf++ = *(volatile unsigned char *)portp;
+}
+
+static __inline__ void _ne_outb(unsigned char b, void *portp)
+{
+ *(volatile unsigned char *)portp = (unsigned char)b;
+}
+
+static __inline__ void _ne_outw(unsigned short w, void *portp)
+{
+ *(volatile unsigned short *)portp = (w>>8|w<<8);
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ return _ne_inb(PORT2ADDR_NE(port));
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ return _ne_inw(PORT2ADDR_NE(port));
+#if defined(CONFIG_USB)
+ else if (port >= 0x340 && port < 0x3a0)
+ return *(volatile unsigned short *)PORT2ADDR_USB(port);
+#endif
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned long l;
+ pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else
+#endif
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char v;
+
+ if (port >= 0x300 && port < 0x320)
+ v = _ne_inb(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+ v = *(volatile unsigned char *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short v;
+
+ if (port >= 0x300 && port < 0x320)
+ v = _ne_inw(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_USB)
+ if (port >= 0x340 && port < 0x3a0)
+ v = *(volatile unsigned short *)PORT2ADDR_USB(port);
+ else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ v = *(volatile unsigned short *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v;
+
+ v = *(volatile unsigned long *)PORT2ADDR(port);
+ delay();
+ return (v);
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_USB)
+ if (port >= 0x340 && port < 0x3a0)
+ *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
+ else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
+ } else
+#endif
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_USB)
+ if (port >= 0x340 && port < 0x3a0)
+ *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
+ else
+#endif
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_insb(PORT2ADDR_NE(port), addr, count);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+ }
+#endif
+ else {
+ unsigned char *buf = addr;
+ unsigned char *portp = PORT2ADDR(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ portp = PORT2ADDR_NE(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outb(*buf++, portp);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ portp = PORT2ADDR_NE(port);
+ while (count--) *(volatile unsigned short *)portp = *buf++;
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned long *)portp = *buf++;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/io_oaks32r.c
+ *
+ * Typical I/O routines for OAKS32R board.
+ *
+ * Copyright (c) 2001-2004 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Mamoru Sakugawa
+ */
+
+/* $Id$ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+
+#define PORT2ADDR(port) _port2addr(port)
+
+static __inline__ void *_port2addr(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET);
+}
+
+static __inline__ void *_port2addr_ne(unsigned long port)
+{
+ return (void *)((port<<1) + NONCACHE_OFFSET + 0x02000000);
+}
+
+static __inline__ void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+/*
+ * NIC I/O function
+ */
+
+#define PORT2ADDR_NE(port) _port2addr_ne(port)
+
+static __inline__ unsigned char _ne_inb(void *portp)
+{
+ return *(volatile unsigned char *)(portp+1);
+}
+
+static __inline__ unsigned short _ne_inw(void *portp)
+{
+ unsigned short tmp;
+
+ tmp = *(unsigned short *)(portp) & 0xff;
+ tmp |= *(unsigned short *)(portp+2) << 8;
+ return tmp;
+}
+
+static __inline__ void _ne_insb(void *portp, void * addr, unsigned long count)
+{
+ unsigned char *buf = addr;
+ while (count--) *buf++ = *(volatile unsigned char *)(portp+1);
+}
+
+static __inline__ void _ne_outb(unsigned char b, void *portp)
+{
+ *(volatile unsigned char *)(portp+1) = b;
+}
+
+static __inline__ void _ne_outw(unsigned short w, void *portp)
+{
+ *(volatile unsigned short *)portp = (w >> 8);
+ *(volatile unsigned short *)(portp+2) = (w & 0xff);
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ return _ne_inb(PORT2ADDR_NE(port));
+
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ return _ne_inw(PORT2ADDR_NE(port));
+
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char v;
+
+ if (port >= 0x300 && port < 0x320)
+ v = _ne_inb(PORT2ADDR_NE(port));
+ else
+ v = *(volatile unsigned char *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short v;
+
+ if (port >= 0x300 && port < 0x320)
+ v = _ne_inw(PORT2ADDR_NE(port));
+ else
+ v = *(volatile unsigned short *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v;
+
+ v = *(volatile unsigned long *)PORT2ADDR(port);
+ delay();
+ return (v);
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ if (port >= 0x300 && port < 0x320)
+ _ne_insb(PORT2ADDR_NE(port), addr, count);
+ else {
+ unsigned char *buf = addr;
+ unsigned char *portp = PORT2ADDR(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= 0x300 && port < 0x320) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) *buf++ = _ne_inw(portp);
+ } else {
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= 0x300 && port < 0x320) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outb(*buf++, portp);
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= 0x300 && port < 0x320) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outw(*buf++, portp);
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned long *)portp = *buf++;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/io_mappi.c
+ *
+ * Typical I/O routines for OPSPUT board.
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+#include <linux/types.h>
+
+#define M32R_PCC_IOMAP_SIZE 0x1000
+
+#define M32R_PCC_IOSTART0 0x1000
+#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
+
+extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
+#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
+
+#define PORT2ADDR(port) _port2addr(port)
+#define PORT2ADDR_USB(port) _port2addr_usb(port)
+
+static __inline__ void *_port2addr(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET);
+}
+
+/*
+ * OPSPUT-LAN is located in the extended bus space
+ * from 0x10000000 to 0x13ffffff on physical address.
+ * The base address of LAN controller(LAN91C111) is 0x300.
+ */
+#define LAN_IOSTART 0x300
+#define LAN_IOEND 0x320
+static __inline__ void *_port2addr_ne(unsigned long port)
+{
+ return (void *)(port + NONCACHE_OFFSET + 0x10000000);
+}
+static __inline__ void *_port2addr_usb(unsigned long port)
+{
+ return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
+}
+
+static __inline__ void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+/*
+ * NIC I/O function
+ */
+
+#define PORT2ADDR_NE(port) _port2addr_ne(port)
+
+static __inline__ unsigned char _ne_inb(void *portp)
+{
+ return *(volatile unsigned char *)portp;
+}
+
+static __inline__ unsigned short _ne_inw(void *portp)
+{
+ return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
+}
+
+static __inline__ void _ne_insb(void *portp, void * addr, unsigned long count)
+{
+ unsigned char *buf = (unsigned char *)addr;
+
+ while (count--) *buf++ = _ne_inb(portp);
+}
+
+static __inline__ void _ne_outb(unsigned char b, void *portp)
+{
+ *(volatile unsigned char *)portp = b;
+}
+
+static __inline__ void _ne_outw(unsigned short w, void *portp)
+{
+ *(volatile unsigned short *)portp = cpu_to_le16(w);
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ return _ne_inb(PORT2ADDR_NE(port));
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ return _ne_inw(PORT2ADDR_NE(port));
+#if defined(CONFIG_USB)
+ else if(port >= 0x340 && port < 0x3a0)
+ return *(volatile unsigned short *)PORT2ADDR_USB(port);
+#endif
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned long l;
+ pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else
+#endif
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char v;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ v = _ne_inb(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+#endif
+ v = *(volatile unsigned char *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short v;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ v = _ne_inw(PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_USB)
+ if(port >= 0x340 && port < 0x3a0)
+ return *(volatile unsigned short *)PORT2ADDR_USB(port);
+ else
+#endif
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+#endif
+ v = *(volatile unsigned short *)PORT2ADDR(port);
+
+ delay();
+ return (v);
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v;
+
+ v = *(volatile unsigned long *)PORT2ADDR(port);
+ delay();
+ return (v);
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_USB)
+ if(port >= 0x340 && port < 0x3a0)
+ *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
+ else
+#endif
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
+ } else
+#endif
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outb(b, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ } else
+#endif
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_outw(w, PORT2ADDR_NE(port));
+ else
+#if defined(CONFIG_USB)
+ if(port >= 0x340 && port < 0x3a0)
+ *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
+ else
+#endif
+
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ } else
+#endif
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ if (port >= LAN_IOSTART && port < LAN_IOEND)
+ _ne_insb(PORT2ADDR_NE(port), addr, count);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+ }
+#endif
+ else {
+ unsigned char *buf = addr;
+ unsigned char *portp = PORT2ADDR(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND) {
+ /*
+ * This portion is only used by smc91111.c to read data
+ * from the DATA_REG. Do not swap the data.
+ */
+ portp = PORT2ADDR_NE(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND) {
+ portp = PORT2ADDR_NE(port);
+ while (count--) _ne_outb(*buf++, portp);
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= LAN_IOSTART && port < LAN_IOEND) {
+ /*
+ * This portion is only used by smc91111.c to write data
+ * into the DATA_REG. Do not swap the data.
+ */
+ portp = PORT2ADDR_NE(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
+ } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
+ pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short), count, 1);
+#endif
+ } else {
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while(count--) *(volatile unsigned long *)portp = *buf++;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/io_usrv.c
+ *
+ * Typical I/O routines for uServer board.
+ *
+ * Copyright (c) 2001 - 2003 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+
+#include <linux/types.h>
+#include "../drivers/m32r_cfc.h"
+
+extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
+#define CFC_IOSTART CFC_IOPORT_BASE
+#define CFC_IOEND (CFC_IOSTART + (M32R_PCC_MAPSIZE * M32R_MAX_PCC) - 1)
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+#define UART0_REGSTART 0x04c20000
+#define UART1_REGSTART 0x04c20100
+#define UART_IOMAP_SIZE 8
+#define UART0_IOSTART 0x3f8
+#define UART0_IOEND (UART0_IOSTART + UART_IOMAP_SIZE - 1)
+#define UART1_IOSTART 0x2f8
+#define UART1_IOEND (UART1_IOSTART + UART_IOMAP_SIZE - 1)
+#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
+
+#define PORT2ADDR(port) _port2addr(port)
+
+static __inline__ void *_port2addr(unsigned long port)
+{
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ if (port >= UART0_IOSTART && port <= UART0_IOEND)
+ port = ((port - UART0_IOSTART) << 1) + UART0_REGSTART;
+ else if (port >= UART1_IOSTART && port <= UART1_IOEND)
+ port = ((port - UART1_IOSTART) << 1) + UART1_REGSTART;
+#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
+ return (void *)(port + NONCACHE_OFFSET);
+}
+
+static __inline__ void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ unsigned long l;
+ pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char b;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else {
+ b = *(volatile unsigned char *)PORT2ADDR(port);
+ delay();
+ return b;
+ }
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short w;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else {
+ w = *(volatile unsigned short *)PORT2ADDR(port);
+ delay();
+ return w;
+ }
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v;
+
+ v = *(volatile unsigned long *)PORT2ADDR(port);
+ delay();
+
+ return v;
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ else
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ else
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
+ else
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ else
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ else
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_ioread_byte(0, port, addr, sizeof(unsigned char), count, 1);
+ else {
+ unsigned char *buf = addr;
+ unsigned char *portp = PORT2ADDR(port);
+ while(count--) *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_ioread_word(0, port, addr, sizeof(unsigned short), count,
+ 1);
+ else {
+ portp = PORT2ADDR(port);
+ while (count--) *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--)
+ *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
+ count, 1);
+ else {
+ portp = PORT2ADDR(port);
+ while (count--)
+ *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, (void *)addr, sizeof(unsigned short),
+ count, 1);
+ else {
+ portp = PORT2ADDR(port);
+ while (count--)
+ *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--)
+ *(volatile unsigned long *)portp = *buf++;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/irq.c
+ *
+ * Copyright (c) 2003, 2004 Hitoshi Yamamoto
+ *
+ * Taken from i386 2.6.4 version.
+ */
+
+/*
+ * linux/arch/i386/kernel/irq.c
+ *
+ * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
+ *
+ * This file contains the code used by various IRQ handling routines:
+ * asking for different IRQ's should be done through these routines
+ * instead of just grabbing them. Thus setups with different IRQ numbers
+ * shouldn't result in any weird surprises, and installing new handlers
+ * should be easier.
+ */
+
+/*
+ * (mostly architecture independent, will move to kernel/irq.c in 2.5.)
+ *
+ * IRQs are in fact implemented a bit like signal handlers for the kernel.
+ * Naturally it's not a 1:1 relation, but there are similarities.
+ */
+
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/smp_lock.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/irq.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/kallsyms.h>
+
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <asm/uaccess.h>
+#include <asm/delay.h>
+#include <asm/irq.h>
+
+/*
+ * Linux has a controller-independent x86 interrupt architecture.
+ * every controller has a 'controller-template', that is used
+ * by the main code to do the right thing. Each driver-visible
+ * interrupt source is transparently wired to the apropriate
+ * controller. Thus drivers need not be aware of the
+ * interrupt-controller.
+ *
+ * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
+ * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
+ * (IO-APICs assumed to be messaging to Pentium local-APICs)
+ *
+ * the code is designed to be easily extended with new/different
+ * interrupt controllers, without having to do assembly magic.
+ */
+
+/*
+ * Controller mappings for all interrupt sources:
+ */
+irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned = {
+ [0 ... NR_IRQS-1] = {
+ .handler = &no_irq_type,
+ .lock = SPIN_LOCK_UNLOCKED
+ }
+};
+
+static void register_irq_proc (unsigned int irq);
+
+/*
+ * Special irq handlers.
+ */
+
+irqreturn_t no_action(int cpl, void *dev_id, struct pt_regs *regs)
+{ return IRQ_NONE; }
+
+/*
+ * Generic no controller code
+ */
+
+static void enable_none(unsigned int irq) { }
+static unsigned int startup_none(unsigned int irq) { return 0; }
+static void disable_none(unsigned int irq) { }
+static void ack_none(unsigned int irq)
+{
+/*
+ * 'what should we do if we get a hw irq event on an illegal vector'.
+ * each architecture has to answer this themselves, it doesn't deserve
+ * a generic callback i think.
+ */
+ printk("unexpected IRQ trap at vector %02x\n", irq);
+}
+
+/* startup is the same as "enable", shutdown is same as "disable" */
+#define shutdown_none disable_none
+#define end_none enable_none
+
+struct hw_interrupt_type no_irq_type = {
+ "none",
+ startup_none,
+ shutdown_none,
+ enable_none,
+ disable_none,
+ ack_none,
+ end_none
+};
+
+atomic_t irq_err_count;
+atomic_t irq_mis_count;
+
+/*
+ * Generic, controller-independent functions:
+ */
+
+int show_interrupts(struct seq_file *p, void *v)
+{
+ int i = *(loff_t *) v, j;
+ struct irqaction * action;
+ unsigned long flags;
+
+ if (i == 0) {
+ seq_printf(p, " ");
+ for (j=0; j<NR_CPUS; j++)
+ if (cpu_online(j))
+ seq_printf(p, "CPU%d ",j);
+ seq_putc(p, '\n');
+ }
+
+ if (i < NR_IRQS) {
+ spin_lock_irqsave(&irq_desc[i].lock, flags);
+ action = irq_desc[i].action;
+ if (!action)
+ goto skip;
+ seq_printf(p, "%3d: ",i);
+#ifndef CONFIG_SMP
+ seq_printf(p, "%10u ", kstat_irqs(i));
+#else
+ for (j = 0; j < NR_CPUS; j++)
+ if (cpu_online(j))
+ seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
+#endif
+ seq_printf(p, " %14s", irq_desc[i].handler->typename);
+ seq_printf(p, " %s", action->name);
+
+ for (action=action->next; action; action = action->next)
+ seq_printf(p, ", %s", action->name);
+
+ seq_putc(p, '\n');
+skip:
+ spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+ } else if (i == NR_IRQS) {
+ seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
+ seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
+ }
+ return 0;
+}
+
+#ifdef CONFIG_SMP
+inline void synchronize_irq(unsigned int irq)
+{
+ while (irq_desc[irq].status & IRQ_INPROGRESS)
+ cpu_relax();
+}
+#endif
+
+/*
+ * This should really return information about whether
+ * we should do bottom half handling etc. Right now we
+ * end up _always_ checking the bottom half, which is a
+ * waste of time and is not what some drivers would
+ * prefer.
+ */
+int handle_IRQ_event(unsigned int irq,
+ struct pt_regs *regs, struct irqaction *action)
+{
+ int status = 1; /* Force the "do bottom halves" bit */
+ int ret, retval = 0;
+
+ if (!(action->flags & SA_INTERRUPT))
+ local_irq_enable();
+
+ do {
+ ret = action->handler(irq, action->dev_id, regs);
+ if (ret == IRQ_HANDLED)
+ status |= action->flags;
+ action = action->next;
+ retval |= ret;
+ } while (action);
+ if (status & SA_SAMPLE_RANDOM)
+ add_interrupt_randomness(irq);
+ local_irq_disable();
+ return retval;
+}
+
+static void __report_bad_irq(int irq, irq_desc_t *desc, irqreturn_t action_ret)
+{
+ struct irqaction *action;
+
+ if (action_ret != IRQ_HANDLED && action_ret != IRQ_NONE) {
+ printk(KERN_ERR "irq event %d: bogus return value %x\n",
+ irq, action_ret);
+ } else {
+ printk(KERN_ERR "irq %d: nobody cared!\n", irq);
+ }
+ dump_stack();
+ printk(KERN_ERR "handlers:\n");
+ action = desc->action;
+ do {
+ printk(KERN_ERR "[<%p>]", action->handler);
+ print_symbol(" (%s)",
+ (unsigned long)action->handler);
+ printk("\n");
+ action = action->next;
+ } while (action);
+}
+
+static void report_bad_irq(int irq, irq_desc_t *desc, irqreturn_t action_ret)
+{
+ static int count = 100;
+
+ if (count) {
+ count--;
+ __report_bad_irq(irq, desc, action_ret);
+ }
+}
+
+static int noirqdebug;
+
+static int __init noirqdebug_setup(char *str)
+{
+ noirqdebug = 1;
+ printk("IRQ lockup detection disabled\n");
+ return 1;
+}
+
+__setup("noirqdebug", noirqdebug_setup);
+
+/*
+ * If 99,900 of the previous 100,000 interrupts have not been handled then
+ * assume that the IRQ is stuck in some manner. Drop a diagnostic and try to
+ * turn the IRQ off.
+ *
+ * (The other 100-of-100,000 interrupts may have been a correctly-functioning
+ * device sharing an IRQ with the failing one)
+ *
+ * Called under desc->lock
+ */
+static void note_interrupt(int irq, irq_desc_t *desc, irqreturn_t action_ret)
+{
+ if (action_ret != IRQ_HANDLED) {
+ desc->irqs_unhandled++;
+ if (action_ret != IRQ_NONE)
+ report_bad_irq(irq, desc, action_ret);
+ }
+
+ desc->irq_count++;
+ if (desc->irq_count < 100000)
+ return;
+
+ desc->irq_count = 0;
+ if (desc->irqs_unhandled > 99900) {
+ /*
+ * The interrupt is stuck
+ */
+ __report_bad_irq(irq, desc, action_ret);
+ /*
+ * Now kill the IRQ
+ */
+ printk(KERN_EMERG "Disabling IRQ #%d\n", irq);
+ desc->status |= IRQ_DISABLED;
+ desc->handler->disable(irq);
+ }
+ desc->irqs_unhandled = 0;
+}
+
+/*
+ * Generic enable/disable code: this just calls
+ * down into the PIC-specific version for the actual
+ * hardware disable after having gotten the irq
+ * controller lock.
+ */
+
+/**
+ * disable_irq_nosync - disable an irq without waiting
+ * @irq: Interrupt to disable
+ *
+ * Disable the selected interrupt line. Disables and Enables are
+ * nested.
+ * Unlike disable_irq(), this function does not ensure existing
+ * instances of the IRQ handler have completed before returning.
+ *
+ * This function may be called from IRQ context.
+ */
+
+inline void disable_irq_nosync(unsigned int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&desc->lock, flags);
+ if (!desc->depth++) {
+ desc->status |= IRQ_DISABLED;
+ desc->handler->disable(irq);
+ }
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+/**
+ * disable_irq - disable an irq and wait for completion
+ * @irq: Interrupt to disable
+ *
+ * Disable the selected interrupt line. Enables and Disables are
+ * nested.
+ * This function waits for any pending IRQ handlers for this interrupt
+ * to complete before returning. If you use this function while
+ * holding a resource the IRQ handler may need you will deadlock.
+ *
+ * This function may be called - with care - from IRQ context.
+ */
+
+void disable_irq(unsigned int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ disable_irq_nosync(irq);
+ if (desc->action)
+ synchronize_irq(irq);
+}
+
+/**
+ * enable_irq - enable handling of an irq
+ * @irq: Interrupt to enable
+ *
+ * Undoes the effect of one call to disable_irq(). If this
+ * matches the last disable, processing of interrupts on this
+ * IRQ line is re-enabled.
+ *
+ * This function may be called from IRQ context.
+ */
+
+void enable_irq(unsigned int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&desc->lock, flags);
+ switch (desc->depth) {
+ case 1: {
+ unsigned int status = desc->status & ~IRQ_DISABLED;
+ desc->status = status;
+ if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {
+ desc->status = status | IRQ_REPLAY;
+ hw_resend_irq(desc->handler,irq);
+ }
+ desc->handler->enable(irq);
+ /* fall-through */
+ }
+ default:
+ desc->depth--;
+ break;
+ case 0:
+ printk("enable_irq(%u) unbalanced from %p\n", irq,
+ __builtin_return_address(0));
+ }
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ */
+asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs)
+{
+ /*
+ * We ack quickly, we don't want the irq controller
+ * thinking we're snobs just because some other CPU has
+ * disabled global interrupts (we have already done the
+ * INT_ACK cycles, it's too late to try to pretend to the
+ * controller that we aren't taking the interrupt).
+ *
+ * 0 return value means that this irq is already being
+ * handled by some other CPU. (or is disabled)
+ */
+ irq_desc_t *desc = irq_desc + irq;
+ struct irqaction * action;
+ unsigned int status;
+
+ irq_enter();
+
+#ifdef CONFIG_DEBUG_STACKOVERFLOW
+ /* FIXME M32R */
+#endif
+ kstat_this_cpu.irqs[irq]++;
+ spin_lock(&desc->lock);
+ desc->handler->ack(irq);
+ /*
+ REPLAY is when Linux resends an IRQ that was dropped earlier
+ WAITING is used by probe to mark irqs that are being tested
+ */
+ status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
+ status |= IRQ_PENDING; /* we _want_ to handle it */
+
+ /*
+ * If the IRQ is disabled for whatever reason, we cannot
+ * use the action we have.
+ */
+ action = NULL;
+ if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) {
+ action = desc->action;
+ status &= ~IRQ_PENDING; /* we commit to handling */
+ status |= IRQ_INPROGRESS; /* we are handling it */
+ }
+ desc->status = status;
+
+ /*
+ * If there is no IRQ handler or it was disabled, exit early.
+ Since we set PENDING, if another processor is handling
+ a different instance of this same irq, the other processor
+ will take care of it.
+ */
+ if (unlikely(!action))
+ goto out;
+
+ /*
+ * Edge triggered interrupts need to remember
+ * pending events.
+ * This applies to any hw interrupts that allow a second
+ * instance of the same irq to arrive while we are in do_IRQ
+ * or in the handler. But the code here only handles the _second_
+ * instance of the irq, not the third or fourth. So it is mostly
+ * useful for irq hardware that does not mask cleanly in an
+ * SMP environment.
+ */
+ for (;;) {
+ irqreturn_t action_ret;
+
+ spin_unlock(&desc->lock);
+ action_ret = handle_IRQ_event(irq, regs, action);
+ spin_lock(&desc->lock);
+ if (!noirqdebug)
+ note_interrupt(irq, desc, action_ret);
+ if (likely(!(desc->status & IRQ_PENDING)))
+ break;
+ desc->status &= ~IRQ_PENDING;
+ }
+ desc->status &= ~IRQ_INPROGRESS;
+
+out:
+ /*
+ * The ->end() handler has to deal with interrupts which got
+ * disabled while the handler was running.
+ */
+ desc->handler->end(irq);
+ spin_unlock(&desc->lock);
+
+ irq_exit();
+
+#if defined(CONFIG_SMP)
+ if (irq == M32R_IRQ_MFT2)
+ smp_send_timer();
+#endif /* CONFIG_SMP */
+
+ return 1;
+}
+
+int can_request_irq(unsigned int irq, unsigned long irqflags)
+{
+ struct irqaction *action;
+
+ if (irq >= NR_IRQS)
+ return 0;
+ action = irq_desc[irq].action;
+ if (action) {
+ if (irqflags & action->flags & SA_SHIRQ)
+ action = NULL;
+ }
+ return !action;
+}
+
+/**
+ * request_irq - allocate an interrupt line
+ * @irq: Interrupt line to allocate
+ * @handler: Function to be called when the IRQ occurs
+ * @irqflags: Interrupt type flags
+ * @devname: An ascii name for the claiming device
+ * @dev_id: A cookie passed back to the handler function
+ *
+ * This call allocates interrupt resources and enables the
+ * interrupt line and IRQ handling. From the point this
+ * call is made your handler function may be invoked. Since
+ * your handler function must clear any interrupt the board
+ * raises, you must take care both to initialise your hardware
+ * and to set up the interrupt handler in the right order.
+ *
+ * Dev_id must be globally unique. Normally the address of the
+ * device data structure is used as the cookie. Since the handler
+ * receives this value it makes sense to use it.
+ *
+ * If your interrupt is shared you must pass a non NULL dev_id
+ * as this is required when freeing the interrupt.
+ *
+ * Flags:
+ *
+ * SA_SHIRQ Interrupt is shared
+ *
+ * SA_INTERRUPT Disable local interrupts while processing
+ *
+ * SA_SAMPLE_RANDOM The interrupt can be used for entropy
+ *
+ */
+
+int request_irq(unsigned int irq,
+ irqreturn_t (*handler)(int, void *, struct pt_regs *),
+ unsigned long irqflags,
+ const char * devname,
+ void *dev_id)
+{
+ int retval;
+ struct irqaction * action;
+
+#if 1
+ /*
+ * Sanity-check: shared interrupts should REALLY pass in
+ * a real dev-ID, otherwise we'll have trouble later trying
+ * to figure out which interrupt is which (messes up the
+ * interrupt freeing logic etc).
+ */
+ if (irqflags & SA_SHIRQ) {
+ if (!dev_id)
+ printk("Bad boy: %s (at 0x%x) called us without a dev_id!\n", devname, (&irq)[-1]);
+ }
+#endif
+
+ if (irq >= NR_IRQS)
+ return -EINVAL;
+ if (!handler)
+ return -EINVAL;
+
+ action = (struct irqaction *)
+ kmalloc(sizeof(struct irqaction), GFP_ATOMIC);
+ if (!action)
+ return -ENOMEM;
+
+ action->handler = handler;
+ action->flags = irqflags;
+ cpus_clear(action->mask);
+ action->name = devname;
+ action->next = NULL;
+ action->dev_id = dev_id;
+
+ retval = setup_irq(irq, action);
+ if (retval)
+ kfree(action);
+ return retval;
+}
+
+EXPORT_SYMBOL(request_irq);
+
+/**
+ * free_irq - free an interrupt
+ * @irq: Interrupt line to free
+ * @dev_id: Device identity to free
+ *
+ * Remove an interrupt handler. The handler is removed and if the
+ * interrupt line is no longer in use by any driver it is disabled.
+ * On a shared IRQ the caller must ensure the interrupt is disabled
+ * on the card it drives before calling this function. The function
+ * does not return until any executing interrupts for this IRQ
+ * have completed.
+ *
+ * This function must not be called from interrupt context.
+ */
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+ irq_desc_t *desc;
+ struct irqaction **p;
+ unsigned long flags;
+
+ if (irq >= NR_IRQS)
+ return;
+
+ desc = irq_desc + irq;
+ spin_lock_irqsave(&desc->lock,flags);
+ p = &desc->action;
+ for (;;) {
+ struct irqaction * action = *p;
+ if (action) {
+ struct irqaction **pp = p;
+ p = &action->next;
+ if (action->dev_id != dev_id)
+ continue;
+
+ /* Found it - now remove it from the list of entries */
+ *pp = action->next;
+ if (!desc->action) {
+ desc->status |= IRQ_DISABLED;
+ desc->handler->shutdown(irq);
+ }
+ spin_unlock_irqrestore(&desc->lock,flags);
+
+ /* Wait to make sure it's not being used on another CPU */
+ synchronize_irq(irq);
+ kfree(action);
+ return;
+ }
+ printk("Trying to free free IRQ%d\n",irq);
+ spin_unlock_irqrestore(&desc->lock,flags);
+ return;
+ }
+}
+
+EXPORT_SYMBOL(free_irq);
+
+/*
+ * IRQ autodetection code..
+ *
+ * This depends on the fact that any interrupt that
+ * comes in on to an unassigned handler will get stuck
+ * with "IRQ_WAITING" cleared and the interrupt
+ * disabled.
+ */
+
+static DECLARE_MUTEX(probe_sem);
+
+/**
+ * probe_irq_on - begin an interrupt autodetect
+ *
+ * Commence probing for an interrupt. The interrupts are scanned
+ * and a mask of potential interrupt lines is returned.
+ *
+ */
+
+unsigned long probe_irq_on(void)
+{
+ unsigned int i;
+ irq_desc_t *desc;
+ unsigned long val;
+ unsigned long delay;
+
+ down(&probe_sem);
+ /*
+ * something may have generated an irq long ago and we want to
+ * flush such a longstanding irq before considering it as spurious.
+ */
+ for (i = NR_IRQS-1; i > 0; i--) {
+ desc = irq_desc + i;
+
+ spin_lock_irq(&desc->lock);
+ if (!irq_desc[i].action)
+ irq_desc[i].handler->startup(i);
+ spin_unlock_irq(&desc->lock);
+ }
+
+ /* Wait for longstanding interrupts to trigger. */
+ for (delay = jiffies + HZ/50; time_after(delay, jiffies); )
+ /* about 20ms delay */ barrier();
+
+ /*
+ * enable any unassigned irqs
+ * (we must startup again here because if a longstanding irq
+ * happened in the previous stage, it may have masked itself)
+ */
+ for (i = NR_IRQS-1; i > 0; i--) {
+ desc = irq_desc + i;
+
+ spin_lock_irq(&desc->lock);
+ if (!desc->action) {
+ desc->status |= IRQ_AUTODETECT | IRQ_WAITING;
+ if (desc->handler->startup(i))
+ desc->status |= IRQ_PENDING;
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+
+ /*
+ * Wait for spurious interrupts to trigger
+ */
+ for (delay = jiffies + HZ/10; time_after(delay, jiffies); )
+ /* about 100ms delay */ barrier();
+
+ /*
+ * Now filter out any obviously spurious interrupts
+ */
+ val = 0;
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc_t *desc = irq_desc + i;
+ unsigned int status;
+
+ spin_lock_irq(&desc->lock);
+ status = desc->status;
+
+ if (status & IRQ_AUTODETECT) {
+ /* It triggered already - consider it spurious. */
+ if (!(status & IRQ_WAITING)) {
+ desc->status = status & ~IRQ_AUTODETECT;
+ desc->handler->shutdown(i);
+ } else
+ if (i < 32)
+ val |= 1 << i;
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+
+ return val;
+}
+
+EXPORT_SYMBOL(probe_irq_on);
+
+/*
+ * Return a mask of triggered interrupts (this
+ * can handle only legacy ISA interrupts).
+ */
+
+/**
+ * probe_irq_mask - scan a bitmap of interrupt lines
+ * @val: mask of interrupts to consider
+ *
+ * Scan the ISA bus interrupt lines and return a bitmap of
+ * active interrupts. The interrupt probe logic state is then
+ * returned to its previous value.
+ *
+ * Note: we need to scan all the irq's even though we will
+ * only return ISA irq numbers - just so that we reset them
+ * all to a known state.
+ */
+unsigned int probe_irq_mask(unsigned long val)
+{
+ int i;
+ unsigned int mask;
+
+ mask = 0;
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc_t *desc = irq_desc + i;
+ unsigned int status;
+
+ spin_lock_irq(&desc->lock);
+ status = desc->status;
+
+ if (status & IRQ_AUTODETECT) {
+ if (i < 16 && !(status & IRQ_WAITING))
+ mask |= 1 << i;
+
+ desc->status = status & ~IRQ_AUTODETECT;
+ desc->handler->shutdown(i);
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+ up(&probe_sem);
+
+ return mask & val;
+}
+
+/*
+ * Return the one interrupt that triggered (this can
+ * handle any interrupt source).
+ */
+
+/**
+ * probe_irq_off - end an interrupt autodetect
+ * @val: mask of potential interrupts (unused)
+ *
+ * Scans the unused interrupt lines and returns the line which
+ * appears to have triggered the interrupt. If no interrupt was
+ * found then zero is returned. If more than one interrupt is
+ * found then minus the first candidate is returned to indicate
+ * their is doubt.
+ *
+ * The interrupt probe logic state is returned to its previous
+ * value.
+ *
+ * BUGS: When used in a module (which arguably shouldnt happen)
+ * nothing prevents two IRQ probe callers from overlapping. The
+ * results of this are non-optimal.
+ */
+
+int probe_irq_off(unsigned long val)
+{
+ int i, irq_found, nr_irqs;
+
+ nr_irqs = 0;
+ irq_found = 0;
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc_t *desc = irq_desc + i;
+ unsigned int status;
+
+ spin_lock_irq(&desc->lock);
+ status = desc->status;
+
+ if (status & IRQ_AUTODETECT) {
+ if (!(status & IRQ_WAITING)) {
+ if (!nr_irqs)
+ irq_found = i;
+ nr_irqs++;
+ }
+ desc->status = status & ~IRQ_AUTODETECT;
+ desc->handler->shutdown(i);
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+ up(&probe_sem);
+
+ if (nr_irqs > 1)
+ irq_found = -irq_found;
+ return irq_found;
+}
+
+EXPORT_SYMBOL(probe_irq_off);
+
+/* this was setup_x86_irq but it seems pretty generic */
+int setup_irq(unsigned int irq, struct irqaction * new)
+{
+ int shared = 0;
+ unsigned long flags;
+ struct irqaction *old, **p;
+ irq_desc_t *desc = irq_desc + irq;
+
+ if (desc->handler == &no_irq_type)
+ return -ENOSYS;
+ /*
+ * Some drivers like serial.c use request_irq() heavily,
+ * so we have to be careful not to interfere with a
+ * running system.
+ */
+ if (new->flags & SA_SAMPLE_RANDOM) {
+ /*
+ * This function might sleep, we want to call it first,
+ * outside of the atomic block.
+ * Yes, this might clear the entropy pool if the wrong
+ * driver is attempted to be loaded, without actually
+ * installing a new handler, but is this really a problem,
+ * only the sysadmin is able to do this.
+ */
+ rand_initialize_irq(irq);
+ }
+
+ /*
+ * The following block of code has to be executed atomically
+ */
+ spin_lock_irqsave(&desc->lock,flags);
+ p = &desc->action;
+ if ((old = *p) != NULL) {
+ /* Can't share interrupts unless both agree to */
+ if (!(old->flags & new->flags & SA_SHIRQ)) {
+ spin_unlock_irqrestore(&desc->lock,flags);
+ return -EBUSY;
+ }
+
+ /* add new interrupt at end of irq queue */
+ do {
+ p = &old->next;
+ old = *p;
+ } while (old);
+ shared = 1;
+ }
+
+ *p = new;
+
+ if (!shared) {
+ desc->depth = 0;
+ desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
+ desc->handler->startup(irq);
+ }
+ spin_unlock_irqrestore(&desc->lock,flags);
+
+ register_irq_proc(irq);
+ return 0;
+}
+
+static struct proc_dir_entry * root_irq_dir;
+static struct proc_dir_entry * irq_dir [NR_IRQS];
+
+#ifdef CONFIG_SMP
+
+static struct proc_dir_entry *smp_affinity_entry[NR_IRQS];
+
+cpumask_t irq_affinity[NR_IRQS] = { [0 ... NR_IRQS-1] = CPU_MASK_ALL };
+
+static int irq_affinity_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len = cpumask_scnprintf(page, count, irq_affinity[(long)data]);
+ if (count - len < 2)
+ return -EINVAL;
+ len += sprintf(page + len, "\n");
+ return len;
+}
+
+static int irq_affinity_write_proc(struct file *file, const char __user *buffer,
+ unsigned long count, void *data)
+{
+ int irq = (long)data, full_count = count, err;
+ cpumask_t new_value, tmp;
+
+ if (!irq_desc[irq].handler->set_affinity)
+ return -EIO;
+
+ err = cpumask_parse(buffer, count, new_value);
+ if (err)
+ return err;
+
+ /*
+ * Do not allow disabling IRQs completely - it's a too easy
+ * way to make the system unusable accidentally :-) At least
+ * one online CPU still has to be targeted.
+ */
+ cpus_and(tmp, new_value, cpu_online_map);
+ if (cpus_empty(tmp))
+ return -EINVAL;
+
+ irq_affinity[irq] = new_value;
+ irq_desc[irq].handler->set_affinity(irq,
+ cpumask_of_cpu(first_cpu(new_value)));
+
+ return full_count;
+}
+
+#endif
+
+static int prof_cpu_mask_read_proc (char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len = cpumask_scnprintf(page, count, *(cpumask_t *)data);
+ if (count - len < 2)
+ return -EINVAL;
+ len += sprintf(page + len, "\n");
+ return len;
+}
+
+static int prof_cpu_mask_write_proc (struct file *file, const char __user *buffer,
+ unsigned long count, void *data)
+{
+ cpumask_t *mask = (cpumask_t *)data;
+ unsigned long full_count = count, err;
+ cpumask_t new_value;
+
+ err = cpumask_parse(buffer, count, new_value);
+ if (err)
+ return err;
+
+ *mask = new_value;
+ return full_count;
+}
+
+#define MAX_NAMELEN 10
+
+static void register_irq_proc (unsigned int irq)
+{
+ char name [MAX_NAMELEN];
+
+ if (!root_irq_dir || (irq_desc[irq].handler == &no_irq_type) ||
+ irq_dir[irq])
+ return;
+
+ memset(name, 0, MAX_NAMELEN);
+ sprintf(name, "%d", irq);
+
+ /* create /proc/irq/1234 */
+ irq_dir[irq] = proc_mkdir(name, root_irq_dir);
+
+#ifdef CONFIG_SMP
+ {
+ struct proc_dir_entry *entry;
+
+ /* create /proc/irq/1234/smp_affinity */
+ entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
+
+ if (entry) {
+ entry->nlink = 1;
+ entry->data = (void *)(long)irq;
+ entry->read_proc = irq_affinity_read_proc;
+ entry->write_proc = irq_affinity_write_proc;
+ }
+
+ smp_affinity_entry[irq] = entry;
+ }
+#endif
+}
+
+unsigned long prof_cpu_mask = -1;
+
+void init_irq_proc (void)
+{
+ struct proc_dir_entry *entry;
+ int i;
+
+ /* create /proc/irq */
+ root_irq_dir = proc_mkdir("irq", NULL);
+
+ /* create /proc/irq/prof_cpu_mask */
+ entry = create_proc_entry("prof_cpu_mask", 0600, root_irq_dir);
+
+ if (!entry)
+ return;
+
+ entry->nlink = 1;
+ entry->data = (void *)&prof_cpu_mask;
+ entry->read_proc = prof_cpu_mask_read_proc;
+ entry->write_proc = prof_cpu_mask_write_proc;
+
+ /*
+ * Create entries for all existing IRQs.
+ */
+ for (i = 0; i < NR_IRQS; i++)
+ register_irq_proc(i);
+}
+
--- /dev/null
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/smp.h>
+#include <linux/user.h>
+#include <linux/elfcore.h>
+#include <linux/sched.h>
+#include <linux/in6.h>
+#include <linux/interrupt.h>
+#include <linux/smp_lock.h>
+#include <linux/string.h>
+
+#include <asm/semaphore.h>
+#include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/checksum.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+#include <asm/irq.h>
+#include <asm/tlbflush.h>
+
+extern void dump_thread(struct pt_regs *, struct user *);
+
+#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_HD) || defined(CONFIG_BLK_DEV_IDE_MODULE) || defined(CONFIG_BLK_DEV_HD_MODULE)
+extern struct drive_info_struct drive_info;
+EXPORT_SYMBOL(drive_info);
+#endif
+
+/* platform dependent support */
+EXPORT_SYMBOL(boot_cpu_data);
+EXPORT_SYMBOL(dump_thread);
+EXPORT_SYMBOL(dump_fpu);
+EXPORT_SYMBOL(__ioremap);
+EXPORT_SYMBOL(iounmap);
+EXPORT_SYMBOL(enable_irq);
+EXPORT_SYMBOL(disable_irq);
+EXPORT_SYMBOL(disable_irq_nosync);
+EXPORT_SYMBOL(kernel_thread);
+EXPORT_SYMBOL(__down);
+EXPORT_SYMBOL(__down_interruptible);
+EXPORT_SYMBOL(__up);
+EXPORT_SYMBOL(__down_trylock);
+
+/* Networking helper routines. */
+/* Delay loops */
+EXPORT_SYMBOL(__udelay);
+EXPORT_SYMBOL(__delay);
+EXPORT_SYMBOL(__const_udelay);
+
+EXPORT_SYMBOL(__get_user_1);
+EXPORT_SYMBOL(__get_user_2);
+EXPORT_SYMBOL(__get_user_4);
+
+EXPORT_SYMBOL(strpbrk);
+EXPORT_SYMBOL(strstr);
+
+EXPORT_SYMBOL(strncpy_from_user);
+EXPORT_SYMBOL(__strncpy_from_user);
+EXPORT_SYMBOL(clear_user);
+EXPORT_SYMBOL(__clear_user);
+EXPORT_SYMBOL(__generic_copy_from_user);
+EXPORT_SYMBOL(__generic_copy_to_user);
+EXPORT_SYMBOL(strnlen_user);
+
+#ifdef CONFIG_SMP
+#ifdef CONFIG_CHIP_M32700_TS1
+extern void *dcache_dummy;
+EXPORT_SYMBOL(dcache_dummy);
+#endif
+EXPORT_SYMBOL(cpu_data);
+EXPORT_SYMBOL(cpu_online_map);
+EXPORT_SYMBOL(cpu_callout_map);
+
+/* Global SMP stuff */
+EXPORT_SYMBOL(synchronize_irq);
+EXPORT_SYMBOL(smp_call_function);
+
+/* TLB flushing */
+EXPORT_SYMBOL(smp_flush_tlb_page);
+EXPORT_SYMBOL_GPL(smp_flush_tlb_all);
+#endif
+
+/* compiler generated symbol */
+extern void __ashldi3(void);
+extern void __ashrdi3(void);
+extern void __lshldi3(void);
+extern void __lshrdi3(void);
+extern void __muldi3(void);
+EXPORT_SYMBOL(__ashldi3);
+EXPORT_SYMBOL(__ashrdi3);
+EXPORT_SYMBOL(__lshldi3);
+EXPORT_SYMBOL(__lshrdi3);
+EXPORT_SYMBOL(__muldi3);
+
+/* memory and string operations */
+EXPORT_SYMBOL(memchr);
+EXPORT_SYMBOL(memcpy);
+/* EXPORT_SYMBOL(memcpy_fromio); // not implement yet */
+/* EXPORT_SYMBOL(memcpy_toio); // not implement yet */
+EXPORT_SYMBOL(memset);
+/* EXPORT_SYMBOL(memset_io); // not implement yet */
+EXPORT_SYMBOL(memmove);
+EXPORT_SYMBOL(memcmp);
+EXPORT_SYMBOL(memscan);
+EXPORT_SYMBOL(copy_page);
+EXPORT_SYMBOL(clear_page);
+
+EXPORT_SYMBOL(strcat);
+EXPORT_SYMBOL(strchr);
+EXPORT_SYMBOL(strcmp);
+EXPORT_SYMBOL(strcpy);
+EXPORT_SYMBOL(strlen);
+EXPORT_SYMBOL(strncat);
+EXPORT_SYMBOL(strncmp);
+EXPORT_SYMBOL(strnlen);
+EXPORT_SYMBOL(strncpy);
+
+EXPORT_SYMBOL(_inb);
+EXPORT_SYMBOL(_inw);
+EXPORT_SYMBOL(_inl);
+EXPORT_SYMBOL(_outb);
+EXPORT_SYMBOL(_outw);
+EXPORT_SYMBOL(_outl);
+EXPORT_SYMBOL(_inb_p);
+EXPORT_SYMBOL(_inw_p);
+EXPORT_SYMBOL(_inl_p);
+EXPORT_SYMBOL(_outb_p);
+EXPORT_SYMBOL(_outw_p);
+EXPORT_SYMBOL(_outl_p);
+EXPORT_SYMBOL(_insb);
+EXPORT_SYMBOL(_insw);
+EXPORT_SYMBOL(_insl);
+EXPORT_SYMBOL(_outsb);
+EXPORT_SYMBOL(_outsw);
+EXPORT_SYMBOL(_outsl);
+EXPORT_SYMBOL(_readb);
+EXPORT_SYMBOL(_readw);
+EXPORT_SYMBOL(_readl);
+EXPORT_SYMBOL(_writeb);
+EXPORT_SYMBOL(_writew);
+EXPORT_SYMBOL(_writel);
+
--- /dev/null
+/* Kernel module help for M32R.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+#include <linux/moduleloader.h>
+#include <linux/elf.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#if 0
+#define DEBUGP printk
+#else
+#define DEBUGP(fmt...)
+#endif
+
+void *module_alloc(unsigned long size)
+{
+ if (size == 0)
+ return NULL;
+ return vmalloc_exec(size);
+}
+
+
+/* Free memory returned from module_alloc */
+void module_free(struct module *mod, void *module_region)
+{
+ vfree(module_region);
+ /* FIXME: If module_region == mod->init_region, trim exception
+ table entries. */
+}
+
+/* We don't need anything special. */
+int module_frob_arch_sections(Elf_Ehdr *hdr,
+ Elf_Shdr *sechdrs,
+ char *secstrings,
+ struct module *mod)
+{
+ return 0;
+}
+
+#define COPY_UNALIGNED_WORD(sw, tw, align) \
+{ \
+ void *__s = &(sw), *__t = &(tw); \
+ unsigned short *__s2 = __s, *__t2 =__t; \
+ unsigned char *__s1 = __s, *__t1 =__t; \
+ switch ((align)) \
+ { \
+ case 0: \
+ *(unsigned long *) __t = *(unsigned long *) __s; \
+ break; \
+ case 2: \
+ *__t2++ = *__s2++; \
+ *__t2 = *__s2; \
+ break; \
+ default: \
+ *__t1++ = *__s1++; \
+ *__t1++ = *__s1++; \
+ *__t1++ = *__s1++; \
+ *__t1 = *__s1; \
+ break; \
+ } \
+}
+
+#define COPY_UNALIGNED_HWORD(sw, tw, align) \
+ { \
+ void *__s = &(sw), *__t = &(tw); \
+ unsigned short *__s2 = __s, *__t2 =__t; \
+ unsigned char *__s1 = __s, *__t1 =__t; \
+ switch ((align)) \
+ { \
+ case 0: \
+ *__t2 = *__s2; \
+ break; \
+ default: \
+ *__t1++ = *__s1++; \
+ *__t1 = *__s1; \
+ break; \
+ } \
+ }
+
+int apply_relocate_add(Elf32_Shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relsec,
+ struct module *me)
+{
+ unsigned int i;
+ Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
+ Elf32_Sym *sym;
+ Elf32_Addr relocation;
+ uint32_t *location;
+ uint32_t value;
+ unsigned short *hlocation;
+ unsigned short hvalue;
+ int svalue;
+ int align;
+
+ DEBUGP("Applying relocate section %u to %u\n", relsec,
+ sechdrs[relsec].sh_info);
+ for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
+ /* This is where to make the change */
+ location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+ + rel[i].r_offset;
+ /* This is the symbol it is referring to. Note that all
+ undefined symbols have been resolved. */
+ sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
+ + ELF32_R_SYM(rel[i].r_info);
+ relocation = sym->st_value + rel[i].r_addend;
+ align = (int)location & 3;
+
+ switch (ELF32_R_TYPE(rel[i].r_info)) {
+ case R_M32R_32_RELA:
+ COPY_UNALIGNED_WORD (*location, value, align);
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ case R_M32R_HI16_ULO_RELA:
+ COPY_UNALIGNED_WORD (*location, value, align);
+ relocation = (relocation >>16) & 0xffff;
+ /* RELA must has 0 at relocation field. */
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ case R_M32R_HI16_SLO_RELA:
+ COPY_UNALIGNED_WORD (*location, value, align);
+ if (relocation & 0x8000) relocation += 0x10000;
+ relocation = (relocation >>16) & 0xffff;
+ /* RELA must has 0 at relocation field. */
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ case R_M32R_16_RELA:
+ hlocation = (unsigned short *)location;
+ relocation = relocation & 0xffff;
+ /* RELA must has 0 at relocation field. */
+ hvalue = relocation;
+ COPY_UNALIGNED_WORD (hvalue, *hlocation, align);
+ break;
+ case R_M32R_SDA16_RELA:
+ case R_M32R_LO16_RELA:
+ COPY_UNALIGNED_WORD (*location, value, align);
+ relocation = relocation & 0xffff;
+ /* RELA must has 0 at relocation field. */
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ case R_M32R_24_RELA:
+ COPY_UNALIGNED_WORD (*location, value, align);
+ relocation = relocation & 0xffffff;
+ /* RELA must has 0 at relocation field. */
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ case R_M32R_18_PCREL_RELA:
+ relocation = (relocation - (Elf32_Addr) location);
+ if (relocation < -0x20000 || 0x1fffc < relocation)
+ {
+ printk(KERN_ERR "module %s: relocation overflow: %u\n",
+ me->name, relocation);
+ return -ENOEXEC;
+ }
+ COPY_UNALIGNED_WORD (*location, value, align);
+ if (value & 0xffff)
+ {
+ /* RELA must has 0 at relocation field. */
+ printk(KERN_ERR "module %s: illegal relocation field: %u\n",
+ me->name, value);
+ return -ENOEXEC;
+ }
+ relocation = (relocation >> 2) & 0xffff;
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ case R_M32R_10_PCREL_RELA:
+ hlocation = (unsigned short *)location;
+ relocation = (relocation - (Elf32_Addr) location);
+ COPY_UNALIGNED_HWORD (*hlocation, hvalue, align);
+ svalue = (int)hvalue;
+ svalue = (signed char)svalue << 2;
+ relocation += svalue;
+ relocation = (relocation >> 2) & 0xff;
+ hvalue = hvalue & 0xff00;
+ hvalue += relocation;
+ COPY_UNALIGNED_HWORD (hvalue, *hlocation, align);
+ break;
+ case R_M32R_26_PCREL_RELA:
+ relocation = (relocation - (Elf32_Addr) location);
+ if (relocation < -0x2000000 || 0x1fffffc < relocation)
+ {
+ printk(KERN_ERR "module %s: relocation overflow: %u\n",
+ me->name, relocation);
+ return -ENOEXEC;
+ }
+ COPY_UNALIGNED_WORD (*location, value, align);
+ if (value & 0xffffff)
+ {
+ /* RELA must has 0 at relocation field. */
+ printk(KERN_ERR "module %s: illegal relocation field: %u\n",
+ me->name, value);
+ return -ENOEXEC;
+ }
+ relocation = (relocation >> 2) & 0xffffff;
+ value += relocation;
+ COPY_UNALIGNED_WORD (value, *location, align);
+ break;
+ default:
+ printk(KERN_ERR "module %s: Unknown relocation: %u\n",
+ me->name, ELF32_R_TYPE(rel[i].r_info));
+ return -ENOEXEC;
+ }
+ }
+ return 0;
+}
+
+int apply_relocate(Elf32_Shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relsec,
+ struct module *me)
+{
+#if 0
+ printk(KERN_ERR "module %s: REL RELOCATION unsupported\n",
+ me->name);
+ return -ENOEXEC;
+#endif
+ return 0;
+
+}
+
+int module_finalize(const Elf_Ehdr *hdr,
+ const Elf_Shdr *sechdrs,
+ struct module *me)
+{
+ return 0;
+}
+
+void module_arch_cleanup(struct module *mod)
+{
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/process.c
+ * orig : sh
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ * Taken from sh version.
+ * Copyright (C) 1995 Linus Torvalds
+ * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
+ */
+
+#undef DEBUG_PROCESS
+#ifdef DEBUG_PROCESS
+#define DPRINTK(fmt, args...) printk("%s:%d:%s: " fmt, __FILE__, __LINE__, \
+ __FUNCTION__, ##args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+/*
+ * This file handles the architecture-dependent parts of process handling..
+ */
+
+#include <linux/fs.h>
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/ptrace.h>
+#include <linux/unistd.h>
+#include <linux/slab.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/mmu_context.h>
+#include <asm/elf.h>
+#include <asm/m32r.h>
+
+#include <linux/err.h>
+
+static int hlt_counter=0;
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+unsigned long thread_saved_pc(struct task_struct *tsk)
+{
+ return tsk->thread.lr;
+}
+
+/*
+ * Powermanagement idle function, if any..
+ */
+void (*pm_idle)(void) = NULL;
+
+void disable_hlt(void)
+{
+ hlt_counter++;
+}
+
+EXPORT_SYMBOL(disable_hlt);
+
+void enable_hlt(void)
+{
+ hlt_counter--;
+}
+
+EXPORT_SYMBOL(enable_hlt);
+
+/*
+ * We use this is we don't have any better
+ * idle routine..
+ */
+void default_idle(void)
+{
+ /* M32R_FIXME: Please use "cpu_sleep" mode. */
+ cpu_relax();
+}
+
+/*
+ * On SMP it's slightly faster (but much more power-consuming!)
+ * to poll the ->work.need_resched flag instead of waiting for the
+ * cross-CPU IPI to arrive. Use this option with caution.
+ */
+static void poll_idle (void)
+{
+ /* M32R_FIXME */
+ cpu_relax();
+}
+
+/*
+ * The idle thread. There's no useful work to be
+ * done, so just try to conserve power and have a
+ * low exit latency (ie sit in a loop waiting for
+ * somebody to say that they'd like to reschedule)
+ */
+void cpu_idle (void)
+{
+ /* endless idle loop with no priority at all */
+ while (1) {
+ while (!need_resched()) {
+ void (*idle)(void) = pm_idle;
+
+ if (!idle)
+ idle = default_idle;
+
+ idle();
+ }
+ schedule();
+ }
+}
+
+void machine_restart(char *__unused)
+{
+ printk("Please push reset button!\n");
+ while (1)
+ cpu_relax();
+}
+
+EXPORT_SYMBOL(machine_restart);
+
+void machine_halt(void)
+{
+ printk("Please push reset button!\n");
+ while (1)
+ cpu_relax();
+}
+
+EXPORT_SYMBOL(machine_halt);
+
+void machine_power_off(void)
+{
+ /* M32R_FIXME */
+}
+
+EXPORT_SYMBOL(machine_power_off);
+
+static int __init idle_setup (char *str)
+{
+ if (!strncmp(str, "poll", 4)) {
+ printk("using poll in idle threads.\n");
+ pm_idle = poll_idle;
+ } else if (!strncmp(str, "sleep", 4)) {
+ printk("using sleep in idle threads.\n");
+ pm_idle = default_idle;
+ }
+
+ return 1;
+}
+
+__setup("idle=", idle_setup);
+
+void show_regs(struct pt_regs * regs)
+{
+ printk("\n");
+ printk("BPC[%08lx]:PSW[%08lx]:LR [%08lx]:FP [%08lx]\n", \
+ regs->bpc, regs->psw, regs->lr, regs->fp);
+ printk("BBPC[%08lx]:BBPSW[%08lx]:SPU[%08lx]:SPI[%08lx]\n", \
+ regs->bbpc, regs->bbpsw, regs->spu, regs->spi);
+ printk("R0 [%08lx]:R1 [%08lx]:R2 [%08lx]:R3 [%08lx]\n", \
+ regs->r0, regs->r1, regs->r2, regs->r3);
+ printk("R4 [%08lx]:R5 [%08lx]:R6 [%08lx]:R7 [%08lx]\n", \
+ regs->r4, regs->r5, regs->r6, regs->r7);
+ printk("R8 [%08lx]:R9 [%08lx]:R10[%08lx]:R11[%08lx]\n", \
+ regs->r8, regs->r9, regs->r10, regs->r11);
+ printk("R12[%08lx]\n", \
+ regs->r12);
+
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ printk("ACC0H[%08lx]:ACC0L[%08lx]\n", \
+ regs->acc0h, regs->acc0l);
+ printk("ACC1H[%08lx]:ACC1L[%08lx]\n", \
+ regs->acc1h, regs->acc1l);
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ printk("ACCH[%08lx]:ACCL[%08lx]\n", \
+ regs->acch, regs->accl);
+#else
+#error unknown isa configuration
+#endif
+}
+
+/*
+ * Create a kernel thread
+ */
+
+/*
+ * This is the mechanism for creating a new kernel thread.
+ *
+ * NOTE! Only a kernel-only process(ie the swapper or direct descendants
+ * who haven't done an "execve()") should use this: it will work within
+ * a system call from a "real" process, but the process memory space will
+ * not be free'd until both the parent and the child have exited.
+ */
+static void kernel_thread_helper(void *nouse, int (*fn)(void *), void *arg)
+{
+ fn(arg);
+ do_exit(-1);
+}
+
+int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof (regs));
+ regs.r1 = (unsigned long)fn;
+ regs.r2 = (unsigned long)arg;
+
+ regs.bpc = (unsigned long)kernel_thread_helper;
+
+ regs.psw = M32R_PSW_BIE;
+
+ /* Ok, create the new process. */
+ return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL,
+ NULL);
+}
+
+/*
+ * Free current thread data structures etc..
+ */
+void exit_thread(void)
+{
+ /* Nothing to do. */
+ DPRINTK("pid = %d\n", current->pid);
+}
+
+void flush_thread(void)
+{
+ DPRINTK("pid = %d\n", current->pid);
+ memset(¤t->thread.debug_trap, 0, sizeof(struct debug_trap));
+}
+
+void release_thread(struct task_struct *dead_task)
+{
+ /* do nothing */
+ DPRINTK("pid = %d\n", dead_task->pid);
+}
+
+/* Fill in the fpu structure for a core dump.. */
+int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
+{
+ return 0; /* Task didn't use the fpu at all. */
+}
+
+int copy_thread(int nr, unsigned long clone_flags, unsigned long spu,
+ unsigned long unused, struct task_struct *tsk, struct pt_regs *regs)
+{
+ struct pt_regs *childregs;
+ unsigned long sp = (unsigned long)tsk->thread_info + THREAD_SIZE;
+ extern void ret_from_fork(void);
+
+ tsk->set_child_tid = tsk->clear_child_tid = NULL;
+
+ /* Copy registers */
+ sp -= sizeof (struct pt_regs);
+ childregs = (struct pt_regs *)sp;
+ *childregs = *regs;
+
+ childregs->spu = spu;
+ childregs->r0 = 0; /* Child gets zero as return value */
+ regs->r0 = tsk->pid;
+ tsk->thread.sp = (unsigned long)childregs;
+ tsk->thread.lr = (unsigned long)ret_from_fork;
+
+ return 0;
+}
+
+/*
+ * fill in the user structure for a core dump..
+ */
+void dump_thread(struct pt_regs * regs, struct user * dump)
+{
+ /* M32R_FIXME */
+}
+
+/*
+ * Capture the user space registers if the task is not running (in user space)
+ */
+int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
+{
+ /* M32R_FIXME */
+ return 1;
+}
+
+asmlinkage int sys_fork(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
+ struct pt_regs regs)
+{
+#ifdef CONFIG_MMU
+ return do_fork(SIGCHLD, regs.spu, ®s, 0, NULL, NULL);
+#else
+ return -EINVAL;
+#endif /* CONFIG_MMU */
+}
+
+asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
+ unsigned long r2, unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, struct pt_regs regs)
+{
+ if (!newsp)
+ newsp = regs.spu;
+
+ return do_fork(clone_flags, newsp, ®s, 0, NULL, NULL);
+}
+
+/*
+ * This is trivial, and on the face of it looks like it
+ * could equally well be done in user mode.
+ *
+ * Not so, for quite unobvious reasons - register pressure.
+ * In user mode vfork() cannot have a stack frame, and if
+ * done by calling the "clone()" system call directly, you
+ * do not have enough call-clobbered registers to hold all
+ * the information you need.
+ */
+asmlinkage int sys_vfork(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
+ struct pt_regs regs)
+{
+ return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs.spu, ®s, 0,
+ NULL, NULL);
+}
+
+/*
+ * sys_execve() executes a new program.
+ */
+asmlinkage int sys_execve(char __user *ufilename, char __user * __user *uargv, char __user * __user *uenvp,
+ unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
+ struct pt_regs regs)
+{
+ int error;
+ char *filename;
+
+ filename = getname(ufilename);
+ error = PTR_ERR(filename);
+ if (IS_ERR(filename))
+ goto out;
+
+ error = do_execve(filename, uargv, uenvp, ®s);
+ if (error == 0)
+ current->ptrace &= ~PT_DTRACE;
+ putname(filename);
+out:
+ return error;
+}
+
+/*
+ * These bracket the sleeping functions..
+ */
+#define first_sched ((unsigned long) scheduling_functions_start_here)
+#define last_sched ((unsigned long) scheduling_functions_end_here)
+
+unsigned long get_wchan(struct task_struct *p)
+{
+ /* M32R_FIXME */
+ return (0);
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/ptrace.c
+ *
+ * Copyright (C) 2002 Hirokazu Takata, Takeo Takahashi
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ *
+ * Original x86 implementation:
+ * By Ross Biro 1/23/92
+ * edited by Linus Torvalds
+ *
+ * Some code taken from sh version:
+ * Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
+ * Some code taken from arm version:
+ * Copyright (C) 2000 Russell King
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/string.h>
+
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/mmu_context.h>
+
+/*
+ * Get the address of the live pt_regs for the specified task.
+ * These are saved onto the top kernel stack when the process
+ * is not running.
+ *
+ * Note: if a user thread is execve'd from kernel space, the
+ * kernel stack will not be empty on entry to the kernel, so
+ * ptracing these tasks will fail.
+ */
+static inline struct pt_regs *
+get_user_regs(struct task_struct *task)
+{
+ return (struct pt_regs *)
+ ((unsigned long)task->thread_info + THREAD_SIZE
+ - sizeof(struct pt_regs));
+}
+
+/*
+ * This routine will get a word off of the process kernel stack.
+ */
+static inline unsigned long int
+get_stack_long(struct task_struct *task, int offset)
+{
+ unsigned long *stack;
+
+ stack = (unsigned long *)get_user_regs(task);
+
+ return stack[offset];
+}
+
+/*
+ * This routine will put a word on the process kernel stack.
+ */
+static inline int
+put_stack_long(struct task_struct *task, int offset, unsigned long data)
+{
+ unsigned long *stack;
+
+ stack = (unsigned long *)get_user_regs(task);
+ stack[offset] = data;
+
+ return 0;
+}
+
+static int reg_offset[] = {
+ PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
+ PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_FP, PT_LR, PT_SPU,
+};
+
+/*
+ * Read the word at offset "off" into the "struct user". We
+ * actually access the pt_regs stored on the kernel stack.
+ */
+static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
+ unsigned long __user *data)
+{
+ unsigned long tmp;
+#ifndef NO_FPU
+ struct user * dummy = NULL;
+#endif
+
+ if ((off & 3) || (off < 0) || (off > sizeof(struct user) - 3))
+ return -EIO;
+
+ off >>= 2;
+ switch (off) {
+ case PT_EVB:
+ __asm__ __volatile__ (
+ "mvfc %0, cr5 \n\t"
+ : "=r" (tmp)
+ );
+ break;
+ case PT_CBR: {
+ unsigned long psw;
+ psw = get_stack_long(tsk, PT_PSW);
+ tmp = ((psw >> 8) & 1);
+ }
+ break;
+ case PT_PSW: {
+ unsigned long psw, bbpsw;
+ psw = get_stack_long(tsk, PT_PSW);
+ bbpsw = get_stack_long(tsk, PT_BBPSW);
+ tmp = ((psw >> 8) & 0xff) | ((bbpsw & 0xff) << 8);
+ }
+ break;
+ case PT_PC:
+ tmp = get_stack_long(tsk, PT_BPC);
+ break;
+ case PT_BPC:
+ off = PT_BBPC;
+ /* fall through */
+ default:
+ if (off < (sizeof(struct pt_regs) >> 2))
+ tmp = get_stack_long(tsk, off);
+#ifndef NO_FPU
+ else if (off >= (long)(&dummy->fpu >> 2) &&
+ off < (long)(&dummy->u_fpvalid >> 2)) {
+ if (!tsk->used_math) {
+ if (off == (long)(&dummy->fpu.fpscr >> 2))
+ tmp = FPSCR_INIT;
+ else
+ tmp = 0;
+ } else
+ tmp = ((long *)(&tsk->thread.fpu >> 2))
+ [off - (long)&dummy->fpu];
+ } else if (off == (long)(&dummy->u_fpvalid >> 2))
+ tmp = tsk->used_math;
+#endif /* not NO_FPU */
+ else
+ tmp = 0;
+ }
+
+ return put_user(tmp, data);
+}
+
+static int ptrace_write_user(struct task_struct *tsk, unsigned long off,
+ unsigned long data)
+{
+ int ret = -EIO;
+#ifndef NO_FPU
+ struct user * dummy = NULL;
+#endif
+
+ if ((off & 3) || off < 0 ||
+ off > sizeof(struct user) - 3)
+ return -EIO;
+
+ off >>= 2;
+ switch (off) {
+ case PT_EVB:
+ case PT_BPC:
+ case PT_SPI:
+ /* We don't allow to modify evb. */
+ ret = 0;
+ break;
+ case PT_PSW:
+ case PT_CBR: {
+ /* We allow to modify only cbr in psw */
+ unsigned long psw;
+ psw = get_stack_long(tsk, PT_PSW);
+ psw = (psw & ~0x100) | ((data & 1) << 8);
+ ret = put_stack_long(tsk, PT_PSW, psw);
+ }
+ break;
+ case PT_PC:
+ off = PT_BPC;
+ data &= ~1;
+ /* fall through */
+ default:
+ if (off < (sizeof(struct pt_regs) >> 2))
+ ret = put_stack_long(tsk, off, data);
+#ifndef NO_FPU
+ else if (off >= (long)(&dummy->fpu >> 2) &&
+ off < (long)(&dummy->u_fpvalid >> 2)) {
+ tsk->used_math = 1;
+ ((long *)&tsk->thread.fpu)
+ [off - (long)&dummy->fpu] = data;
+ ret = 0;
+ } else if (off == (long)(&dummy->u_fpvalid >> 2)) {
+ tsk->used_math = data ? 1 : 0;
+ ret = 0;
+ }
+#endif /* not NO_FPU */
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Get all user integer registers.
+ */
+static int ptrace_getregs(struct task_struct *tsk, void __user *uregs)
+{
+ struct pt_regs *regs = get_user_regs(tsk);
+
+ return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
+}
+
+/*
+ * Set all user integer registers.
+ */
+static int ptrace_setregs(struct task_struct *tsk, void __user *uregs)
+{
+ struct pt_regs newregs;
+ int ret;
+
+ ret = -EFAULT;
+ if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) {
+ struct pt_regs *regs = get_user_regs(tsk);
+ *regs = newregs;
+ ret = 0;
+ }
+
+ return ret;
+}
+
+
+static inline int
+check_condition_bit(struct task_struct *child)
+{
+ return (int)((get_stack_long(child, PT_PSW) >> 8) & 1);
+}
+
+static int
+check_condition_src(unsigned long op, unsigned long regno1,
+ unsigned long regno2, struct task_struct *child)
+{
+ unsigned long reg1, reg2;
+
+ reg2 = get_stack_long(child, reg_offset[regno2]);
+
+ switch (op) {
+ case 0x0: /* BEQ */
+ reg1 = get_stack_long(child, reg_offset[regno1]);
+ return reg1 == reg2;
+ case 0x1: /* BNE */
+ reg1 = get_stack_long(child, reg_offset[regno1]);
+ return reg1 != reg2;
+ case 0x8: /* BEQZ */
+ return reg2 == 0;
+ case 0x9: /* BNEZ */
+ return reg2 != 0;
+ case 0xa: /* BLTZ */
+ return (int)reg2 < 0;
+ case 0xb: /* BGEZ */
+ return (int)reg2 >= 0;
+ case 0xc: /* BLEZ */
+ return (int)reg2 <= 0;
+ case 0xd: /* BGTZ */
+ return (int)reg2 > 0;
+ default:
+ /* never reached */
+ return 0;
+ }
+}
+
+static void
+compute_next_pc_for_16bit_insn(unsigned long insn, unsigned long pc,
+ unsigned long *next_pc,
+ struct task_struct *child)
+{
+ unsigned long op, op2, op3;
+ unsigned long disp;
+ unsigned long regno;
+ int parallel = 0;
+
+ if (insn & 0x00008000)
+ parallel = 1;
+ if (pc & 3)
+ insn &= 0x7fff; /* right slot */
+ else
+ insn >>= 16; /* left slot */
+
+ op = (insn >> 12) & 0xf;
+ op2 = (insn >> 8) & 0xf;
+ op3 = (insn >> 4) & 0xf;
+
+ if (op == 0x7) {
+ switch (op2) {
+ case 0xd: /* BNC */
+ case 0x9: /* BNCL */
+ if (!check_condition_bit(child)) {
+ disp = (long)(insn << 24) >> 22;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ }
+ break;
+ case 0x8: /* BCL */
+ case 0xc: /* BC */
+ if (check_condition_bit(child)) {
+ disp = (long)(insn << 24) >> 22;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ }
+ break;
+ case 0xe: /* BL */
+ case 0xf: /* BRA */
+ disp = (long)(insn << 24) >> 22;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ break;
+ }
+ } else if (op == 0x1) {
+ switch (op2) {
+ case 0x0:
+ if (op3 == 0xf) { /* TRAP */
+#if 1
+ /* pass through */
+#else
+ /* kernel space is not allowed as next_pc */
+ unsigned long evb;
+ unsigned long trapno;
+ trapno = insn & 0xf;
+ __asm__ __volatile__ (
+ "mvfc %0, cr5\n"
+ :"=r"(evb)
+ :
+ );
+ *next_pc = evb + (trapno << 2);
+ return;
+#endif
+ } else if (op3 == 0xd) { /* RTE */
+ *next_pc = get_stack_long(child, PT_BPC);
+ return;
+ }
+ break;
+ case 0xc: /* JC */
+ if (op3 == 0xc && check_condition_bit(child)) {
+ regno = insn & 0xf;
+ *next_pc = get_stack_long(child,
+ reg_offset[regno]);
+ return;
+ }
+ break;
+ case 0xd: /* JNC */
+ if (op3 == 0xc && !check_condition_bit(child)) {
+ regno = insn & 0xf;
+ *next_pc = get_stack_long(child,
+ reg_offset[regno]);
+ return;
+ }
+ break;
+ case 0xe: /* JL */
+ case 0xf: /* JMP */
+ if (op3 == 0xc) { /* JMP */
+ regno = insn & 0xf;
+ *next_pc = get_stack_long(child,
+ reg_offset[regno]);
+ return;
+ }
+ break;
+ }
+ }
+ if (parallel)
+ *next_pc = pc + 4;
+ else
+ *next_pc = pc + 2;
+}
+
+static void
+compute_next_pc_for_32bit_insn(unsigned long insn, unsigned long pc,
+ unsigned long *next_pc,
+ struct task_struct *child)
+{
+ unsigned long op;
+ unsigned long op2;
+ unsigned long disp;
+ unsigned long regno1, regno2;
+
+ op = (insn >> 28) & 0xf;
+ if (op == 0xf) { /* branch 24-bit relative */
+ op2 = (insn >> 24) & 0xf;
+ switch (op2) {
+ case 0xd: /* BNC */
+ case 0x9: /* BNCL */
+ if (!check_condition_bit(child)) {
+ disp = (long)(insn << 8) >> 6;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ }
+ break;
+ case 0x8: /* BCL */
+ case 0xc: /* BC */
+ if (check_condition_bit(child)) {
+ disp = (long)(insn << 8) >> 6;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ }
+ break;
+ case 0xe: /* BL */
+ case 0xf: /* BRA */
+ disp = (long)(insn << 8) >> 6;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ }
+ } else if (op == 0xb) { /* branch 16-bit relative */
+ op2 = (insn >> 20) & 0xf;
+ switch (op2) {
+ case 0x0: /* BEQ */
+ case 0x1: /* BNE */
+ case 0x8: /* BEQZ */
+ case 0x9: /* BNEZ */
+ case 0xa: /* BLTZ */
+ case 0xb: /* BGEZ */
+ case 0xc: /* BLEZ */
+ case 0xd: /* BGTZ */
+ regno1 = ((insn >> 24) & 0xf);
+ regno2 = ((insn >> 16) & 0xf);
+ if (check_condition_src(op2, regno1, regno2, child)) {
+ disp = (long)(insn << 16) >> 14;
+ *next_pc = (pc & ~0x3) + disp;
+ return;
+ }
+ break;
+ }
+ }
+ *next_pc = pc + 4;
+}
+
+static inline void
+compute_next_pc(unsigned long insn, unsigned long pc,
+ unsigned long *next_pc, struct task_struct *child)
+{
+ if (insn & 0x80000000)
+ compute_next_pc_for_32bit_insn(insn, pc, next_pc, child);
+ else
+ compute_next_pc_for_16bit_insn(insn, pc, next_pc, child);
+}
+
+static int
+register_debug_trap(struct task_struct *child, unsigned long next_pc,
+ unsigned long next_insn, unsigned long *code)
+{
+ struct debug_trap *p = &child->thread.debug_trap;
+ unsigned long addr = next_pc & ~3;
+
+ if (p->nr_trap != 0) {
+ printk("kernel BUG at %s %d: p->nr_trap = %d\n",
+ __FILE__, __LINE__, p->nr_trap);
+ return -1;
+ }
+ p->addr = addr;
+ p->insn = next_insn;
+ p->nr_trap++;
+ if (next_pc & 3) {
+ *code = (next_insn & 0xffff0000) | 0x10f1;
+ /* xxx --> TRAP1 */
+ } else {
+ if ((next_insn & 0x80000000) || (next_insn & 0x8000)) {
+ *code = 0x10f17000;
+ /* TRAP1 --> NOP */
+ } else {
+ *code = (next_insn & 0xffff) | 0x10f10000;
+ /* TRAP1 --> xxx */
+ }
+ }
+ return 0;
+}
+
+int withdraw_debug_trap_for_signal(struct task_struct *child)
+{
+ struct debug_trap *p = &child->thread.debug_trap;
+ int nr_trap = p->nr_trap;
+
+ if (nr_trap) {
+ access_process_vm(child, p->addr, &p->insn, sizeof(p->insn), 1);
+ p->nr_trap = 0;
+ p->addr = 0;
+ p->insn = 0;
+ }
+ return nr_trap;
+}
+
+static int
+unregister_debug_trap(struct task_struct *child, unsigned long addr,
+ unsigned long *code)
+{
+ struct debug_trap *p = &child->thread.debug_trap;
+
+ if (p->nr_trap != 1 || p->addr != addr) {
+ /* The trap may be requested from debugger.
+ * ptrace should do nothing in this case.
+ */
+ return 0;
+ }
+ *code = p->insn;
+ p->insn = 0;
+ p->addr = 0;
+ p->nr_trap--;
+ return 1;
+}
+
+static void
+unregister_all_debug_traps(struct task_struct *child)
+{
+ struct debug_trap *p = &child->thread.debug_trap;
+
+ if (p->nr_trap) {
+ access_process_vm(child, p->addr, &p->insn, sizeof(p->insn), 1);
+ p->addr = 0;
+ p->insn = 0;
+ p->nr_trap = 0;
+ }
+}
+
+static inline void
+invalidate_cache(void)
+{
+#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP)
+
+ _flush_cache_copyback_all();
+
+#else /* ! CONFIG_CHIP_M32700 */
+
+ /* Invalidate cache */
+ __asm__ __volatile__ (
+ "ldi r0, #-1 \n\t"
+ "ldi r1, #0 \n\t"
+ "stb r1, @r0 ; cache off \n\t"
+ "; \n\t"
+ "ldi r0, #-2 \n\t"
+ "ldi r1, #1 \n\t"
+ "stb r1, @r0 ; cache invalidate \n\t"
+ ".fillinsn \n"
+ "0: \n\t"
+ "ldb r1, @r0 ; invalidate check \n\t"
+ "bnez r1, 0b \n\t"
+ "; \n\t"
+ "ldi r0, #-1 \n\t"
+ "ldi r1, #1 \n\t"
+ "stb r1, @r0 ; cache on \n\t"
+ : : : "r0", "r1", "memory"
+ );
+ /* FIXME: copying-back d-cache and invalidating i-cache are needed.
+ */
+#endif /* CONFIG_CHIP_M32700 */
+}
+
+/* Embed a debug trap (TRAP1) code */
+static int
+embed_debug_trap(struct task_struct *child, unsigned long next_pc)
+{
+ unsigned long next_insn, code;
+ unsigned long addr = next_pc & ~3;
+
+ if (access_process_vm(child, addr, &next_insn, sizeof(next_insn), 0)
+ != sizeof(next_insn)) {
+ return -1; /* error */
+ }
+
+ /* Set a trap code. */
+ if (register_debug_trap(child, next_pc, next_insn, &code)) {
+ return -1; /* error */
+ }
+ if (access_process_vm(child, addr, &code, sizeof(code), 1)
+ != sizeof(code)) {
+ return -1; /* error */
+ }
+ return 0; /* success */
+}
+
+void
+embed_debug_trap_for_signal(struct task_struct *child)
+{
+ unsigned long next_pc;
+ unsigned long pc, insn;
+ int ret;
+
+ pc = get_stack_long(child, PT_BPC);
+ ret = access_process_vm(child, pc&~3, &insn, sizeof(insn), 0);
+ if (ret != sizeof(insn)) {
+ printk("kernel BUG at %s %d: access_process_vm returns %d\n",
+ __FILE__, __LINE__, ret);
+ return;
+ }
+ compute_next_pc(insn, pc, &next_pc, child);
+ if (next_pc & 0x80000000) {
+ printk("kernel BUG at %s %d: next_pc = 0x%08x\n",
+ __FILE__, __LINE__, (int)next_pc);
+ return;
+ }
+ if (embed_debug_trap(child, next_pc)) {
+ printk("kernel BUG at %s %d: embed_debug_trap error\n",
+ __FILE__, __LINE__);
+ return;
+ }
+ invalidate_cache();
+}
+
+void
+withdraw_debug_trap(struct pt_regs *regs)
+{
+ unsigned long addr;
+ unsigned long code;
+
+ addr = (regs->bpc - 2) & ~3;
+ regs->bpc -= 2;
+ if (unregister_debug_trap(current, addr, &code)) {
+ access_process_vm(current, addr, &code, sizeof(code), 1);
+ invalidate_cache();
+ }
+}
+
+static void
+init_debug_traps(struct task_struct *child)
+{
+ struct debug_trap *p = &child->thread.debug_trap;
+ p->nr_trap = 0;
+ p->addr = 0;
+ p->insn = 0;
+}
+
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ *
+ * Make sure single step bits etc are not set.
+ */
+void ptrace_disable(struct task_struct *child)
+{
+ /* nothing to do.. */
+}
+
+static int
+do_ptrace(long request, struct task_struct *child, long addr, long data)
+{
+ unsigned long tmp;
+ int ret;
+
+ switch (request) {
+ /*
+ * read word at location "addr" in the child process.
+ */
+ case PTRACE_PEEKTEXT:
+ case PTRACE_PEEKDATA:
+ ret = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
+ if (ret == sizeof(tmp))
+ ret = put_user(tmp,(unsigned long __user *) data);
+ else
+ ret = -EIO;
+ break;
+
+ /*
+ * read the word at location addr in the USER area.
+ */
+ case PTRACE_PEEKUSR:
+ ret = ptrace_read_user(child, addr,
+ (unsigned long __user *)data);
+ break;
+
+ /*
+ * write the word at location addr.
+ */
+ case PTRACE_POKETEXT:
+ case PTRACE_POKEDATA:
+ ret = access_process_vm(child, addr, &data, sizeof(data), 1);
+ if (ret == sizeof(data)) {
+ ret = 0;
+ if (request == PTRACE_POKETEXT) {
+ invalidate_cache();
+ }
+ } else {
+ ret = -EIO;
+ }
+ break;
+
+ /*
+ * write the word at location addr in the USER area.
+ */
+ case PTRACE_POKEUSR:
+ ret = ptrace_write_user(child, addr, data);
+ break;
+
+ /*
+ * continue/restart and stop at next (return from) syscall
+ */
+ case PTRACE_SYSCALL:
+ case PTRACE_CONT:
+ ret = -EIO;
+ if ((unsigned long) data > _NSIG)
+ break;
+ if (request == PTRACE_SYSCALL)
+ set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+ else
+ clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+ child->exit_code = data;
+ wake_up_process(child);
+ ret = 0;
+ break;
+
+ /*
+ * make the child exit. Best I can do is send it a sigkill.
+ * perhaps it should be put in the status that it wants to
+ * exit.
+ */
+ case PTRACE_KILL: {
+ ret = 0;
+ unregister_all_debug_traps(child);
+ invalidate_cache();
+ if (child->state == TASK_ZOMBIE) /* already dead */
+ break;
+ child->exit_code = SIGKILL;
+ wake_up_process(child);
+ break;
+ }
+
+ /*
+ * execute single instruction.
+ */
+ case PTRACE_SINGLESTEP: {
+ unsigned long next_pc;
+ unsigned long pc, insn;
+
+ ret = -EIO;
+ if ((unsigned long) data > _NSIG)
+ break;
+ clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+ if ((child->ptrace & PT_DTRACE) == 0) {
+ /* Spurious delayed TF traps may occur */
+ child->ptrace |= PT_DTRACE;
+ }
+
+ /* Compute next pc. */
+ pc = get_stack_long(child, PT_BPC);
+
+ if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0)
+ != sizeof(insn))
+ break;
+
+ compute_next_pc(insn, pc, &next_pc, child);
+ if (next_pc & 0x80000000)
+ break;
+
+ if (embed_debug_trap(child, next_pc))
+ break;
+
+ invalidate_cache();
+ child->exit_code = data;
+
+ /* give it a chance to run. */
+ wake_up_process(child);
+ ret = 0;
+ break;
+ }
+
+ /*
+ * detach a process that was attached.
+ */
+ case PTRACE_DETACH:
+ ret = 0;
+ ret = ptrace_detach(child, data);
+ break;
+
+ case PTRACE_GETREGS:
+ ret = ptrace_getregs(child, (void __user *)data);
+ break;
+
+ case PTRACE_SETREGS:
+ ret = ptrace_setregs(child, (void __user *)data);
+ break;
+
+ default:
+ ret = ptrace_request(child, request, addr, data);
+ break;
+ }
+
+ return ret;
+}
+
+asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
+{
+ struct task_struct *child;
+ int ret;
+
+ lock_kernel();
+ ret = -EPERM;
+ if (request == PTRACE_TRACEME) {
+ /* are we already being traced? */
+ if (current->ptrace & PT_PTRACED)
+ goto out;
+ /* set the ptrace bit in the process flags. */
+ current->ptrace |= PT_PTRACED;
+ ret = 0;
+ goto out;
+ }
+ ret = -ESRCH;
+ read_lock(&tasklist_lock);
+ child = find_task_by_pid(pid);
+ if (child)
+ get_task_struct(child);
+ read_unlock(&tasklist_lock);
+ if (!child)
+ goto out;
+
+ ret = -EPERM;
+ if (pid == 1) /* you may not mess with init */
+ goto out;
+
+ if (request == PTRACE_ATTACH) {
+ ret = ptrace_attach(child);
+ if (ret == 0)
+ init_debug_traps(child);
+ goto out_tsk;
+ }
+
+ ret = ptrace_check_attach(child, request == PTRACE_KILL);
+ if (ret == 0)
+ ret = do_ptrace(request, child, addr, data);
+
+out_tsk:
+ put_task_struct(child);
+out:
+ unlock_kernel();
+
+ return ret;
+}
+
+/* notification of system call entry/exit
+ * - triggered by current->work.syscall_trace
+ */
+void do_syscall_trace(void)
+{
+ if (!test_thread_flag(TIF_SYSCALL_TRACE))
+ return;
+ if (!(current->ptrace & PT_PTRACED))
+ return;
+ /* the 0x80 provides a way for the tracing parent to distinguish
+ between a syscall stop and SIGTRAP delivery */
+ ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
+ ? 0x80 : 0));
+
+ /*
+ * this isn't the same as continuing with a signal, but it will do
+ * for normal use. strace only continues with a signal if the
+ * stopping signal is not SIGTRAP. -brl
+ */
+ if (current->exit_code) {
+ send_sig(current->exit_code, current, 1);
+ current->exit_code = 0;
+ }
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/semaphore.c
+ * orig : i386 2.6.4
+ *
+ * M32R semaphore implementation.
+ *
+ * Copyright (c) 2002 - 2004 Hitoshi Yamamoto
+ */
+
+/*
+ * i386 semaphore implementation.
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ *
+ * Portions Copyright 1999 Red Hat, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * rw semaphores implemented November 1999 by Benjamin LaHaise <bcrl@redhat.com>
+ */
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <asm/semaphore.h>
+
+/*
+ * Semaphores are implemented using a two-way counter:
+ * The "count" variable is decremented for each process
+ * that tries to acquire the semaphore, while the "sleeping"
+ * variable is a count of such acquires.
+ *
+ * Notably, the inline "up()" and "down()" functions can
+ * efficiently test if they need to do any extra work (up
+ * needs to do something only if count was negative before
+ * the increment operation.
+ *
+ * "sleeping" and the contention routine ordering is protected
+ * by the spinlock in the semaphore's waitqueue head.
+ *
+ * Note that these functions are only called when there is
+ * contention on the lock, and as such all this is the
+ * "non-critical" part of the whole semaphore business. The
+ * critical part is the inline stuff in <asm/semaphore.h>
+ * where we want to avoid any extra jumps and calls.
+ */
+
+/*
+ * Logic:
+ * - only on a boundary condition do we need to care. When we go
+ * from a negative count to a non-negative, we wake people up.
+ * - when we go from a non-negative count to a negative do we
+ * (a) synchronize with the "sleeper" count and (b) make sure
+ * that we're on the wakeup list before we synchronize so that
+ * we cannot lose wakeup events.
+ */
+
+asmlinkage void __up(struct semaphore *sem)
+{
+ wake_up(&sem->wait);
+}
+
+asmlinkage void __sched __down(struct semaphore * sem)
+{
+ struct task_struct *tsk = current;
+ DECLARE_WAITQUEUE(wait, tsk);
+ unsigned long flags;
+
+ tsk->state = TASK_UNINTERRUPTIBLE;
+ spin_lock_irqsave(&sem->wait.lock, flags);
+ add_wait_queue_exclusive_locked(&sem->wait, &wait);
+
+ sem->sleepers++;
+ for (;;) {
+ int sleepers = sem->sleepers;
+
+ /*
+ * Add "everybody else" into it. They aren't
+ * playing, because we own the spinlock in
+ * the wait_queue_head.
+ */
+ if (!atomic_add_negative(sleepers - 1, &sem->count)) {
+ sem->sleepers = 0;
+ break;
+ }
+ sem->sleepers = 1; /* us - see -1 above */
+ spin_unlock_irqrestore(&sem->wait.lock, flags);
+
+ schedule();
+
+ spin_lock_irqsave(&sem->wait.lock, flags);
+ tsk->state = TASK_UNINTERRUPTIBLE;
+ }
+ remove_wait_queue_locked(&sem->wait, &wait);
+ wake_up_locked(&sem->wait);
+ spin_unlock_irqrestore(&sem->wait.lock, flags);
+ tsk->state = TASK_RUNNING;
+}
+
+asmlinkage int __sched __down_interruptible(struct semaphore * sem)
+{
+ int retval = 0;
+ struct task_struct *tsk = current;
+ DECLARE_WAITQUEUE(wait, tsk);
+ unsigned long flags;
+
+ tsk->state = TASK_INTERRUPTIBLE;
+ spin_lock_irqsave(&sem->wait.lock, flags);
+ add_wait_queue_exclusive_locked(&sem->wait, &wait);
+
+ sem->sleepers++;
+ for (;;) {
+ int sleepers = sem->sleepers;
+
+ /*
+ * With signals pending, this turns into
+ * the trylock failure case - we won't be
+ * sleeping, and we* can't get the lock as
+ * it has contention. Just correct the count
+ * and exit.
+ */
+ if (signal_pending(current)) {
+ retval = -EINTR;
+ sem->sleepers = 0;
+ atomic_add(sleepers, &sem->count);
+ break;
+ }
+
+ /*
+ * Add "everybody else" into it. They aren't
+ * playing, because we own the spinlock in
+ * wait_queue_head. The "-1" is because we're
+ * still hoping to get the semaphore.
+ */
+ if (!atomic_add_negative(sleepers - 1, &sem->count)) {
+ sem->sleepers = 0;
+ break;
+ }
+ sem->sleepers = 1; /* us - see -1 above */
+ spin_unlock_irqrestore(&sem->wait.lock, flags);
+
+ schedule();
+
+ spin_lock_irqsave(&sem->wait.lock, flags);
+ tsk->state = TASK_INTERRUPTIBLE;
+ }
+ remove_wait_queue_locked(&sem->wait, &wait);
+ wake_up_locked(&sem->wait);
+ spin_unlock_irqrestore(&sem->wait.lock, flags);
+
+ tsk->state = TASK_RUNNING;
+ return retval;
+}
+
+/*
+ * Trylock failed - make sure we correct for
+ * having decremented the count.
+ *
+ * We could have done the trylock with a
+ * single "cmpxchg" without failure cases,
+ * but then it wouldn't work on a 386.
+ */
+asmlinkage int __down_trylock(struct semaphore * sem)
+{
+ int sleepers;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sem->wait.lock, flags);
+ sleepers = sem->sleepers + 1;
+ sem->sleepers = 0;
+
+ /*
+ * Add "everybody else" and us into it. They aren't
+ * playing, because we own the spinlock in the
+ * wait_queue_head.
+ */
+ if (!atomic_add_negative(sleepers, &sem->count)) {
+ wake_up_locked(&sem->wait);
+ }
+
+ spin_unlock_irqrestore(&sem->wait.lock, flags);
+ return 1;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup.c
+ *
+ * Setup routines for Renesas M32R
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ */
+
+/* $Id$ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/stddef.h>
+#include <linux/fs.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/console.h>
+#include <linux/initrd.h>
+#include <linux/major.h>
+#include <linux/root_dev.h>
+#include <linux/seq_file.h>
+#include <linux/timex.h>
+#include <linux/tty.h>
+#include <asm/processor.h>
+#include <asm/pgtable.h>
+#include <asm/io.h>
+#include <asm/mmu_context.h>
+#include <asm/m32r.h>
+#include <asm/setup.h>
+#include <asm/sections.h>
+
+#ifdef CONFIG_MMU
+extern void init_mmu(void);
+#endif
+
+#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_HD) \
+ || defined(CONFIG_BLK_DEV_IDE_MODULE) \
+ || defined(CONFIG_BLK_DEV_HD_MODULE)
+struct drive_info_struct { char dummy[32]; } drive_info;
+#endif
+
+extern char _end[];
+
+/*
+ * Machine setup..
+ */
+struct cpuinfo_m32r boot_cpu_data;
+
+#ifdef CONFIG_BLK_DEV_RAM
+extern int rd_doload; /* 1 = load ramdisk, 0 = don't load */
+extern int rd_prompt; /* 1 = prompt for ramdisk, 0 = don't prompt */
+extern int rd_image_start; /* starting block # of image */
+#endif
+
+#if defined(CONFIG_VGA_CONSOLE)
+struct screen_info screen_info = {
+ .orig_video_lines = 25,
+ .orig_video_cols = 80,
+ .orig_video_mode = 0,
+ .orig_video_ega_bx = 0,
+ .orig_video_isVGA = 1,
+ .orig_video_points = 8
+};
+#endif
+
+extern int root_mountflags;
+
+static char command_line[COMMAND_LINE_SIZE];
+
+static struct resource data_resource = {
+ .name = "Kernel data",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_BUSY | IORESOURCE_MEM
+};
+
+static struct resource code_resource = {
+ .name = "Kernel code",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_BUSY | IORESOURCE_MEM
+};
+
+unsigned long memory_start;
+unsigned long memory_end;
+
+void __init setup_arch(char **);
+int get_cpuinfo(char *);
+
+static __inline__ void parse_mem_cmdline(char ** cmdline_p)
+{
+ char c = ' ';
+ char *to = command_line;
+ char *from = COMMAND_LINE;
+ int len = 0;
+ int usermem = 0;
+
+ /* Save unparsed command line copy for /proc/cmdline */
+ memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
+ saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
+
+ memory_start = (unsigned long)CONFIG_MEMORY_START+PAGE_OFFSET;
+ memory_end = memory_start+(unsigned long)CONFIG_MEMORY_SIZE;
+
+ for ( ; ; ) {
+ if (c == ' ' && !memcmp(from, "mem=", 4)) {
+ if (to != command_line)
+ to--;
+
+ {
+ unsigned long mem_size;
+
+ usermem = 1;
+ mem_size = memparse(from+4, &from);
+ memory_end = memory_start + mem_size;
+ }
+ }
+ c = *(from++);
+ if (!c)
+ break;
+
+ if (COMMAND_LINE_SIZE <= ++len)
+ break;
+
+ *(to++) = c;
+ }
+ *to = '\0';
+ *cmdline_p = command_line;
+ if (usermem)
+ printk(KERN_INFO "user-defined physical RAM map:\n");
+}
+
+#ifndef CONFIG_DISCONTIGMEM
+static unsigned long __init setup_memory(void)
+{
+ unsigned long start_pfn, max_low_pfn, bootmap_size;
+
+ start_pfn = PFN_UP( __pa(_end) );
+ max_low_pfn = PFN_DOWN( __pa(memory_end) );
+
+ /*
+ * Initialize the boot-time allocator (with low memory only):
+ */
+ bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
+ CONFIG_MEMORY_START>>PAGE_SHIFT, max_low_pfn);
+
+ /*
+ * Register fully available low RAM pages with the bootmem allocator.
+ */
+ {
+ unsigned long curr_pfn;
+ unsigned long last_pfn;
+ unsigned long pages;
+
+ /*
+ * We are rounding up the start address of usable memory:
+ */
+ curr_pfn = PFN_UP(__pa(memory_start));
+
+ /*
+ * ... and at the end of the usable range downwards:
+ */
+ last_pfn = PFN_DOWN(__pa(memory_end));
+
+ if (last_pfn > max_low_pfn)
+ last_pfn = max_low_pfn;
+
+ pages = last_pfn - curr_pfn;
+ free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(pages));
+ }
+
+ /*
+ * Reserve the kernel text and
+ * Reserve the bootmem bitmap. We do this in two steps (first step
+ * was init_bootmem()), because this catches the (definitely buggy)
+ * case of us accidentally initializing the bootmem allocator with
+ * an invalid RAM area.
+ */
+ reserve_bootmem(CONFIG_MEMORY_START + PAGE_SIZE,
+ (PFN_PHYS(start_pfn) + bootmap_size + PAGE_SIZE - 1)
+ - CONFIG_MEMORY_START);
+
+ /*
+ * reserve physical page 0 - it's a special BIOS page on many boxes,
+ * enabling clean reboots, SMP operation, laptop functions.
+ */
+ reserve_bootmem(CONFIG_MEMORY_START, PAGE_SIZE);
+
+ /*
+ * reserve memory hole
+ */
+#ifdef CONFIG_MEMHOLE
+ reserve_bootmem(CONFIG_MEMHOLE_START, CONFIG_MEMHOLE_SIZE);
+#endif
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (LOADER_TYPE && INITRD_START) {
+ if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
+ reserve_bootmem(INITRD_START, INITRD_SIZE);
+ initrd_start = INITRD_START ?
+ INITRD_START + PAGE_OFFSET : 0;
+
+ initrd_end = initrd_start + INITRD_SIZE;
+ printk("initrd:start[%08lx],size[%08lx]\n",
+ initrd_start, INITRD_SIZE);
+ } else {
+ printk("initrd extends beyond end of memory "
+ "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
+ INITRD_START + INITRD_SIZE,
+ max_low_pfn << PAGE_SHIFT);
+
+ initrd_start = 0;
+ }
+ }
+#endif
+
+ return max_low_pfn;
+}
+#else /* CONFIG_DISCONTIGMEM */
+extern unsigned long setup_memory(void);
+#endif /* CONFIG_DISCONTIGMEM */
+
+#define M32R_PCC_PCATCR 0x00ef7014 /* will move to m32r.h */
+
+void __init setup_arch(char **cmdline_p)
+{
+ ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
+
+ boot_cpu_data.cpu_clock = M32R_CPUCLK;
+ boot_cpu_data.bus_clock = M32R_BUSCLK;
+ boot_cpu_data.timer_divide = M32R_TIMER_DIVIDE;
+
+#ifdef CONFIG_BLK_DEV_RAM
+ rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
+ rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
+ rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
+#endif
+
+ if (!MOUNT_ROOT_RDONLY)
+ root_mountflags &= ~MS_RDONLY;
+
+#ifdef CONFIG_VT
+#if defined(CONFIG_VGA_CONSOLE)
+ conswitchp = &vga_con;
+#elif defined(CONFIG_DUMMY_CONSOLE)
+ conswitchp = &dummy_con;
+#endif
+#endif
+
+#ifdef CONFIG_DISCONTIGMEM
+ numnodes = 2;
+#endif /* CONFIG_DISCONTIGMEM */
+
+ init_mm.start_code = (unsigned long) _text;
+ init_mm.end_code = (unsigned long) _etext;
+ init_mm.end_data = (unsigned long) _edata;
+ init_mm.brk = (unsigned long) _end;
+
+ code_resource.start = virt_to_phys(_text);
+ code_resource.end = virt_to_phys(_etext)-1;
+ data_resource.start = virt_to_phys(_etext);
+ data_resource.end = virt_to_phys(_edata)-1;
+
+ parse_mem_cmdline(cmdline_p);
+
+ setup_memory();
+
+ paging_init();
+}
+
+#ifdef CONFIG_PROC_FS
+/*
+ * Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+ struct cpuinfo_m32r *c = v;
+ unsigned long cpu = c - cpu_data;
+
+#ifdef CONFIG_SMP
+ if (!cpu_online(cpu))
+ return 0;
+#endif /* CONFIG_SMP */
+
+ seq_printf(m, "processor\t: %ld\n", cpu);
+
+#ifdef CONFIG_CHIP_VDEC2
+ seq_printf(m, "cpu family\t: VDEC2\n"
+ "cache size\t: Unknown\n");
+#elif CONFIG_CHIP_M32700
+ seq_printf(m,"cpu family\t: M32700\n"
+ "cache size\t: I-8KB/D-8KB\n");
+#elif CONFIG_CHIP_M32102
+ seq_printf(m,"cpu family\t: M32102\n"
+ "cache size\t: I-8KB\n");
+#elif CONFIG_CHIP_OPSP
+ seq_printf(m,"cpu family\t: OPSP\n"
+ "cache size\t: I-8KB/D-8KB\n");
+#elif CONFIG_CHIP_MP
+ seq_printf(m, "cpu family\t: M32R-MP\n"
+ "cache size\t: I-xxKB/D-xxKB\n");
+#else
+ seq_printf(m, "cpu family\t: Unknown\n");
+#endif
+ seq_printf(m, "bogomips\t: %lu.%02lu\n",
+ c->loops_per_jiffy/(500000/HZ),
+ (c->loops_per_jiffy/(5000/HZ)) % 100);
+#ifdef CONFIG_PLAT_MAPPI
+ seq_printf(m, "Machine\t\t: Mappi Evaluation board\n");
+#elif CONFIG_PLAT_MAPPI2
+ seq_printf(m, "Machine\t\t: Mappi-II Evaluation board\n");
+#elif CONFIG_PLAT_M32700UT
+ seq_printf(m, "Machine\t\t: M32700UT Evaluation board\n");
+#elif CONFIG_PLAT_OPSPUT
+ seq_printf(m, "Machine\t\t: OPSPUT Evaluation board\n");
+#elif CONFIG_PLAT_USRV
+ seq_printf(m, "Machine\t\t: uServer\n");
+#elif CONFIG_PLAT_OAKS32R
+ seq_printf(m, "Machine\t\t: OAKS32R\n");
+#else
+ seq_printf(m, "Machine\t\t: Unknown\n");
+#endif
+
+#define PRINT_CLOCK(name, value) \
+ seq_printf(m, name " clock\t: %d.%02dMHz\n", \
+ ((value) / 1000000), ((value) % 1000000)/10000)
+
+ PRINT_CLOCK("CPU", (int)c->cpu_clock);
+ PRINT_CLOCK("Bus", (int)c->bus_clock);
+
+ seq_printf(m, "\n");
+
+ return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+ return *pos < NR_CPUS ? cpu_data + *pos : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+ ++*pos;
+ return c_start(m, pos);
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+struct seq_operations cpuinfo_op = {
+ start: c_start,
+ next: c_next,
+ stop: c_stop,
+ show: show_cpuinfo,
+};
+#endif /* CONFIG_PROC_FS */
+
+unsigned long cpu_initialized __initdata = 0;
+
+/*
+ * cpu_init() initializes state that is per-CPU. Some data is already
+ * initialized (naturally) in the bootstrap process.
+ * We reload them nevertheless, this function acts as a
+ * 'CPU state barrier', nothing should get across.
+ */
+#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
+ || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
+ || defined(CONFIG_CHIP_OPSP)
+void __init cpu_init (void)
+{
+ int cpu_id = smp_processor_id();
+
+ if (test_and_set_bit(cpu_id, &cpu_initialized)) {
+ printk(KERN_WARNING "CPU#%d already initialized!\n", cpu_id);
+ for ( ; ; )
+ local_irq_enable();
+ }
+ printk(KERN_INFO "Initializing CPU#%d\n", cpu_id);
+
+ /* Set up and load the per-CPU TSS and LDT */
+ atomic_inc(&init_mm.mm_count);
+ current->active_mm = &init_mm;
+ if (current->mm)
+ BUG();
+
+ /* Force FPU initialization */
+ current_thread_info()->status = 0;
+ current->used_math = 0;
+
+#ifdef CONFIG_MMU
+ /* Set up MMU */
+ init_mmu();
+#endif
+
+ /* Set up ICUIMASK */
+ outl(0x00070000, M32R_ICU_IMASK_PORTL); /* imask=111 */
+}
+#endif /* defined(CONFIG_CHIP_VDEC2) ... */
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup_m32700ut.c
+ *
+ * Setup routines for Renesas M32700UT Board
+ *
+ * Copyright (c) 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ */
+
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/system.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+/*
+ * M32700 Interrupt Control Unit (Level 1)
+ */
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+#ifndef CONFIG_SMP
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+#endif /* CONFIG_SMP */
+
+static icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
+
+static void disable_m32700ut_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_m32700ut_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_and_ack_m32700ut(unsigned int irq)
+{
+ disable_m32700ut_irq(irq);
+}
+
+static void end_m32700ut_irq(unsigned int irq)
+{
+ enable_m32700ut_irq(irq);
+}
+
+static unsigned int startup_m32700ut_irq(unsigned int irq)
+{
+ enable_m32700ut_irq(irq);
+ return (0);
+}
+
+static void shutdown_m32700ut_irq(unsigned int irq)
+{
+ unsigned long port;
+
+ port = irq2port(irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type m32700ut_irq_type =
+{
+ "M32700UT-IRQ",
+ startup_m32700ut_irq,
+ shutdown_m32700ut_irq,
+ enable_m32700ut_irq,
+ disable_m32700ut_irq,
+ mask_and_ack_m32700ut,
+ end_m32700ut_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on M32700UT (Level 2)
+ */
+#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
+#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+typedef struct {
+ unsigned short icucr; /* ICU Control Register */
+} pld_icu_data_t;
+
+static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
+
+static void disable_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+// disable_m32700ut_irq(M32R_IRQ_INT1);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+// enable_m32700ut_irq(M32R_IRQ_INT1);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_m32700ut_pld(unsigned int irq)
+{
+ disable_m32700ut_pld_irq(irq);
+// mask_and_ack_m32700ut(M32R_IRQ_INT1);
+}
+
+static void end_m32700ut_pld_irq(unsigned int irq)
+{
+ enable_m32700ut_pld_irq(irq);
+ end_m32700ut_irq(M32R_IRQ_INT1);
+}
+
+static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
+{
+ enable_m32700ut_pld_irq(irq);
+ return (0);
+}
+
+static void shutdown_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+// shutdown_m32700ut_irq(M32R_IRQ_INT1);
+ port = pldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type m32700ut_pld_irq_type =
+{
+ "M32700UT-PLD-IRQ",
+ startup_m32700ut_pld_irq,
+ shutdown_m32700ut_pld_irq,
+ enable_m32700ut_pld_irq,
+ disable_m32700ut_pld_irq,
+ mask_and_ack_m32700ut_pld,
+ end_m32700ut_pld_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
+ */
+#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
+#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
+
+static void disable_m32700ut_lanpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lanpldirq(irq);
+ port = lanpldirq2port(pldirq);
+ data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_m32700ut_lanpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lanpldirq(irq);
+ port = lanpldirq2port(pldirq);
+ data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
+{
+ disable_m32700ut_lanpld_irq(irq);
+}
+
+static void end_m32700ut_lanpld_irq(unsigned int irq)
+{
+ enable_m32700ut_lanpld_irq(irq);
+ end_m32700ut_irq(M32R_IRQ_INT0);
+}
+
+static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
+{
+ enable_m32700ut_lanpld_irq(irq);
+ return (0);
+}
+
+static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2lanpldirq(irq);
+ port = lanpldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type m32700ut_lanpld_irq_type =
+{
+ "M32700UT-PLD-LAN-IRQ",
+ startup_m32700ut_lanpld_irq,
+ shutdown_m32700ut_lanpld_irq,
+ enable_m32700ut_lanpld_irq,
+ disable_m32700ut_lanpld_irq,
+ mask_and_ack_m32700ut_lanpld,
+ end_m32700ut_lanpld_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
+ */
+#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
+#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
+
+static void disable_m32700ut_lcdpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lcdpldirq(irq);
+ port = lcdpldirq2port(pldirq);
+ data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_m32700ut_lcdpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lcdpldirq(irq);
+ port = lcdpldirq2port(pldirq);
+ data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
+{
+ disable_m32700ut_lcdpld_irq(irq);
+}
+
+static void end_m32700ut_lcdpld_irq(unsigned int irq)
+{
+ enable_m32700ut_lcdpld_irq(irq);
+ end_m32700ut_irq(M32R_IRQ_INT2);
+}
+
+static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
+{
+ enable_m32700ut_lcdpld_irq(irq);
+ return (0);
+}
+
+static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2lcdpldirq(irq);
+ port = lcdpldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
+{
+ "M32700UT-PLD-LCD-IRQ",
+ startup_m32700ut_lcdpld_irq,
+ shutdown_m32700ut_lcdpld_irq,
+ enable_m32700ut_lcdpld_irq,
+ disable_m32700ut_lcdpld_irq,
+ mask_and_ack_m32700ut_lcdpld,
+ end_m32700ut_lcdpld_irq
+};
+
+void __init init_IRQ(void)
+{
+#if defined(CONFIG_SMC91X)
+ /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
+ irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
+ irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
+ irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
+ irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
+ lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
+ disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
+#endif /* CONFIG_SMC91X */
+
+ /* MFT2 : system timer */
+ irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_MFT2].action = 0;
+ irq_desc[M32R_IRQ_MFT2].depth = 1;
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_m32700ut_irq(M32R_IRQ_MFT2);
+
+ /* SIO0 : receive */
+ irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].action = 0;
+ irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_m32700ut_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0 : send */
+ irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].action = 0;
+ irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_m32700ut_irq(M32R_IRQ_SIO0_S);
+
+ /* SIO1 : receive */
+ irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].action = 0;
+ irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_m32700ut_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1 : send */
+ irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].action = 0;
+ irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_m32700ut_irq(M32R_IRQ_SIO1_S);
+
+ /* DMA1 : */
+ irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_DMA1].action = 0;
+ irq_desc[M32R_IRQ_DMA1].depth = 1;
+ icu_data[M32R_IRQ_DMA1].icucr = 0;
+ disable_m32700ut_irq(M32R_IRQ_DMA1);
+
+#ifdef CONFIG_SERIAL_M32R_PLDSIO
+ /* INT#1: SIO0 Receive on PLD */
+ irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
+ irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
+ disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
+
+ /* INT#1: SIO0 Send on PLD */
+ irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_SND].action = 0;
+ irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
+ disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
+#endif /* CONFIG_SERIAL_M32R_PLDSIO */
+
+ /* INT#1: CFC IREQ on PLD */
+ irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].action = 0;
+ irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
+
+ /* INT#1: CFC Insert on PLD */
+ irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
+ irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
+
+ /* INT#1: CFC Eject on PLD */
+ irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
+ irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
+
+ /*
+ * INT0# is used for LAN, DIO
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
+ enable_m32700ut_irq(M32R_IRQ_INT0);
+
+ /*
+ * INT1# is used for UART, MMC, CF Controller in FPGA.
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
+ enable_m32700ut_irq(M32R_IRQ_INT1);
+
+#if defined(CONFIG_USB)
+ outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
+
+ irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
+ irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
+ irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
+ irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
+ lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
+ disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
+#endif
+ /*
+ * INT2# is used for BAT, USB, AUDIO
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
+ enable_m32700ut_irq(M32R_IRQ_INT2);
+
+//#if defined(CONFIG_M32R_AR_VGA)
+ /*
+ * INT3# is used for AR
+ */
+ irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
+ irq_desc[M32R_IRQ_INT3].action = 0;
+ irq_desc[M32R_IRQ_INT3].depth = 1;
+ icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
+ disable_m32700ut_irq(M32R_IRQ_INT3);
+//#endif /* CONFIG_M32R_ARV */
+}
+
+#define LAN_IOSTART 0x300
+#define LAN_IOEND 0x320
+static struct resource smc91x_resources[] = {
+ [0] = {
+ .start = (LAN_IOSTART),
+ .end = (LAN_IOEND),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = M32700UT_LAN_IRQ_LAN,
+ .end = M32700UT_LAN_IRQ_LAN,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device smc91x_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smc91x_resources),
+ .resource = smc91x_resources,
+};
+
+static int __init platform_init(void)
+{
+ platform_device_register(&smc91x_device);
+ return 0;
+}
+arch_initcall(platform_init);
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup_mappi.c
+ *
+ * Setup routines for Renesas MAPPI Board
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ */
+
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/system.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+#ifndef CONFIG_SMP
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+#endif /* CONFIG_SMP */
+
+icu_data_t icu_data[NR_IRQS];
+
+static void disable_mappi_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_mappi_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_and_ack_mappi(unsigned int irq)
+{
+ disable_mappi_irq(irq);
+}
+
+static void end_mappi_irq(unsigned int irq)
+{
+ enable_mappi_irq(irq);
+}
+
+static unsigned int startup_mappi_irq(unsigned int irq)
+{
+ enable_mappi_irq(irq);
+ return (0);
+}
+
+static void shutdown_mappi_irq(unsigned int irq)
+{
+ unsigned long port;
+
+ port = irq2port(irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type mappi_irq_type =
+{
+ "MAPPI-IRQ",
+ startup_mappi_irq,
+ shutdown_mappi_irq,
+ enable_mappi_irq,
+ disable_mappi_irq,
+ mask_and_ack_mappi,
+ end_mappi_irq
+};
+
+void __init init_IRQ(void)
+{
+ static int once = 0;
+
+ if (once)
+ return;
+ else
+ once++;
+
+#ifdef CONFIG_NE2000
+ /* INT0 : LAN controller (RTL8019AS) */
+ irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT0].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_INT0].action = 0;
+ irq_desc[M32R_IRQ_INT0].depth = 1;
+ icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
+ disable_mappi_irq(M32R_IRQ_INT0);
+#endif /* CONFIG_M32R_NE2000 */
+
+ /* MFT2 : system timer */
+ irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_MFT2].action = 0;
+ irq_desc[M32R_IRQ_MFT2].depth = 1;
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_mappi_irq(M32R_IRQ_MFT2);
+
+#ifdef CONFIG_SERIAL_M32R_SIO
+ /* SIO0_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].action = 0;
+ irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0_S : uart send data */
+ irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].action = 0;
+ irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO0_S);
+
+ /* SIO1_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].action = 0;
+ irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1_S : uart send data */
+ irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].action = 0;
+ irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO1_S);
+#endif /* CONFIG_SERIAL_M32R_SIO */
+
+#if defined(CONFIG_M32RPCC)
+ /* INT1 : pccard0 interrupt */
+ irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT1].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_INT1].action = 0;
+ irq_desc[M32R_IRQ_INT1].depth = 1;
+ icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
+ disable_mappi_irq(M32R_IRQ_INT1);
+
+ /* INT2 : pccard1 interrupt */
+ irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT2].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_INT2].action = 0;
+ irq_desc[M32R_IRQ_INT2].depth = 1;
+ icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
+ disable_mappi_irq(M32R_IRQ_INT2);
+#endif /* CONFIG_M32RPCC */
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup_mappi.c
+ *
+ * Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Mamoru Sakugawa
+ */
+
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/system.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+#ifndef CONFIG_SMP
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+#endif /* CONFIG_SMP */
+
+icu_data_t icu_data[NR_IRQS];
+
+static void disable_mappi2_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ if ((irq == 0) ||(irq >= NR_IRQS)) {
+ printk("bad irq 0x%08x\n", irq);
+ return;
+ }
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_mappi2_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ if ((irq == 0) ||(irq >= NR_IRQS)) {
+ printk("bad irq 0x%08x\n", irq);
+ return;
+ }
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_and_ack_mappi2(unsigned int irq)
+{
+ disable_mappi2_irq(irq);
+}
+
+static void end_mappi2_irq(unsigned int irq)
+{
+ enable_mappi2_irq(irq);
+}
+
+static unsigned int startup_mappi2_irq(unsigned int irq)
+{
+ enable_mappi2_irq(irq);
+ return (0);
+}
+
+static void shutdown_mappi2_irq(unsigned int irq)
+{
+ unsigned long port;
+
+ port = irq2port(irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type mappi2_irq_type =
+{
+ "MAPPI2-IRQ",
+ startup_mappi2_irq,
+ shutdown_mappi2_irq,
+ enable_mappi2_irq,
+ disable_mappi2_irq,
+ mask_and_ack_mappi2,
+ end_mappi2_irq
+};
+
+void __init init_IRQ(void)
+{
+#if defined(CONFIG_SMC91X)
+ /* INT0 : LAN controller (SMC91111) */
+ irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT0].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_INT0].action = 0;
+ irq_desc[M32R_IRQ_INT0].depth = 1;
+ icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
+ disable_mappi2_irq(M32R_IRQ_INT0);
+#endif /* CONFIG_SMC91X */
+
+ /* MFT2 : system timer */
+ irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_MFT2].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_MFT2].action = 0;
+ irq_desc[M32R_IRQ_MFT2].depth = 1;
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_mappi2_irq(M32R_IRQ_MFT2);
+
+#ifdef CONFIG_SERIAL_M32R_SIO
+ /* SIO0_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_R].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].action = 0;
+ irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_mappi2_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0_S : uart send data */
+ irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_S].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].action = 0;
+ irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_mappi2_irq(M32R_IRQ_SIO0_S);
+ /* SIO1_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_R].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].action = 0;
+ irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_mappi2_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1_S : uart send data */
+ irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_S].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].action = 0;
+ irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_mappi2_irq(M32R_IRQ_SIO1_S);
+#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
+
+#if defined(CONFIG_USB)
+ /* INT1 : USB Host controller interrupt */
+ irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT1].handler = &mappi2_irq_type;
+ irq_desc[M32R_IRQ_INT1].action = 0;
+ irq_desc[M32R_IRQ_INT1].depth = 1;
+ icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
+ disable_mappi2_irq(M32R_IRQ_INT1);
+#endif /* CONFIG_USB */
+
+#if defined(CONFIG_M32R_CFC)
+ /* ICUCR40: CFC IREQ */
+ irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFIREQ].handler = &mappi2_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].action = 0;
+ irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
+// icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
+ icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
+ disable_mappi2_irq(PLD_IRQ_CFIREQ);
+
+ /* ICUCR41: CFC Insert */
+ irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi2_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
+ irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
+ icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
+// icu_data[PLD_IRQ_CFC_INSERT].icucr = 0;
+ disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
+
+ /* ICUCR42: CFC Eject */
+ irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFC_EJECT].handler = &mappi2_irq_type;
+ irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
+ irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
+ icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
+// icu_data[PLD_IRQ_CFC_EJECT].icucr = 0;
+ disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
+
+#endif /* CONFIG_MAPPI2_CFC */
+}
+
+#define LAN_IOSTART 0x300
+#define LAN_IOEND 0x320
+static struct resource smc91x_resources[] = {
+ [0] = {
+ .start = (LAN_IOSTART),
+ .end = (LAN_IOEND),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = M32R_IRQ_INT0,
+ .end = M32R_IRQ_INT0,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device smc91x_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smc91x_resources),
+ .resource = smc91x_resources,
+};
+
+static int __init platform_init(void)
+{
+ platform_device_register(&smc91x_device);
+ return 0;
+}
+arch_initcall(platform_init);
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup_oaks32r.c
+ *
+ * Setup routines for OAKS32R Board
+ *
+ * Copyright (c) 2002-2004 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Mamoru Sakugawa
+ */
+
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/system.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+#ifndef CONFIG_SMP
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+#endif /* CONFIG_SMP */
+
+icu_data_t icu_data[NR_IRQS];
+
+static void disable_oaks32r_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_oaks32r_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_and_ack_mappi(unsigned int irq)
+{
+ disable_oaks32r_irq(irq);
+}
+
+static void end_oaks32r_irq(unsigned int irq)
+{
+ enable_oaks32r_irq(irq);
+}
+
+static unsigned int startup_oaks32r_irq(unsigned int irq)
+{
+ enable_oaks32r_irq(irq);
+ return (0);
+}
+
+static void shutdown_oaks32r_irq(unsigned int irq)
+{
+ unsigned long port;
+
+ port = irq2port(irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type oaks32r_irq_type =
+{
+ "OAKS32R-IRQ",
+ startup_oaks32r_irq,
+ shutdown_oaks32r_irq,
+ enable_oaks32r_irq,
+ disable_oaks32r_irq,
+ mask_and_ack_mappi,
+ end_oaks32r_irq
+};
+
+void __init init_IRQ(void)
+{
+ static int once = 0;
+
+ if (once)
+ return;
+ else
+ once++;
+
+#ifdef CONFIG_NE2000
+ /* INT3 : LAN controller (RTL8019AS) */
+ irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT3].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_INT3].action = 0;
+ irq_desc[M32R_IRQ_INT3].depth = 1;
+ icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
+ disable_oaks32r_irq(M32R_IRQ_INT3);
+#endif /* CONFIG_M32R_NE2000 */
+
+ /* MFT2 : system timer */
+ irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_MFT2].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_MFT2].action = 0;
+ irq_desc[M32R_IRQ_MFT2].depth = 1;
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_oaks32r_irq(M32R_IRQ_MFT2);
+
+#ifdef CONFIG_SERIAL_M32R_SIO
+ /* SIO0_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_R].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].action = 0;
+ irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_oaks32r_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0_S : uart send data */
+ irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_S].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].action = 0;
+ irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_oaks32r_irq(M32R_IRQ_SIO0_S);
+
+ /* SIO1_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_R].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].action = 0;
+ irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_oaks32r_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1_S : uart send data */
+ irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_S].handler = &oaks32r_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].action = 0;
+ irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_oaks32r_irq(M32R_IRQ_SIO1_S);
+#endif /* CONFIG_SERIAL_M32R_SIO */
+
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup_opsput.c
+ *
+ * Setup routines for Renesas OPSPUT Board
+ *
+ * Copyright (c) 2002-2004
+ * Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ */
+
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/system.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+/*
+ * OPSP Interrupt Control Unit (Level 1)
+ */
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+#ifndef CONFIG_SMP
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+#endif /* CONFIG_SMP */
+
+static icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
+
+static void disable_opsput_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_opsput_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_and_ack_opsput(unsigned int irq)
+{
+ disable_opsput_irq(irq);
+}
+
+static void end_opsput_irq(unsigned int irq)
+{
+ enable_opsput_irq(irq);
+}
+
+static unsigned int startup_opsput_irq(unsigned int irq)
+{
+ enable_opsput_irq(irq);
+ return (0);
+}
+
+static void shutdown_opsput_irq(unsigned int irq)
+{
+ unsigned long port;
+
+ port = irq2port(irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type opsput_irq_type =
+{
+ "OPSPUT-IRQ",
+ startup_opsput_irq,
+ shutdown_opsput_irq,
+ enable_opsput_irq,
+ disable_opsput_irq,
+ mask_and_ack_opsput,
+ end_opsput_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on OPSPUT (Level 2)
+ */
+#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
+#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+typedef struct {
+ unsigned short icucr; /* ICU Control Register */
+} pld_icu_data_t;
+
+static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
+
+static void disable_opsput_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+// disable_opsput_irq(M32R_IRQ_INT1);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_opsput_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+// enable_opsput_irq(M32R_IRQ_INT1);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_opsput_pld(unsigned int irq)
+{
+ disable_opsput_pld_irq(irq);
+// mask_and_ack_opsput(M32R_IRQ_INT1);
+}
+
+static void end_opsput_pld_irq(unsigned int irq)
+{
+ enable_opsput_pld_irq(irq);
+ end_opsput_irq(M32R_IRQ_INT1);
+}
+
+static unsigned int startup_opsput_pld_irq(unsigned int irq)
+{
+ enable_opsput_pld_irq(irq);
+ return (0);
+}
+
+static void shutdown_opsput_pld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+// shutdown_opsput_irq(M32R_IRQ_INT1);
+ port = pldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type opsput_pld_irq_type =
+{
+ "OPSPUT-PLD-IRQ",
+ startup_opsput_pld_irq,
+ shutdown_opsput_pld_irq,
+ enable_opsput_pld_irq,
+ disable_opsput_pld_irq,
+ mask_and_ack_opsput_pld,
+ end_opsput_pld_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
+ */
+#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
+#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
+
+static void disable_opsput_lanpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lanpldirq(irq);
+ port = lanpldirq2port(pldirq);
+ data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_opsput_lanpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lanpldirq(irq);
+ port = lanpldirq2port(pldirq);
+ data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_opsput_lanpld(unsigned int irq)
+{
+ disable_opsput_lanpld_irq(irq);
+}
+
+static void end_opsput_lanpld_irq(unsigned int irq)
+{
+ enable_opsput_lanpld_irq(irq);
+ end_opsput_irq(M32R_IRQ_INT0);
+}
+
+static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
+{
+ enable_opsput_lanpld_irq(irq);
+ return (0);
+}
+
+static void shutdown_opsput_lanpld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2lanpldirq(irq);
+ port = lanpldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type opsput_lanpld_irq_type =
+{
+ "OPSPUT-PLD-LAN-IRQ",
+ startup_opsput_lanpld_irq,
+ shutdown_opsput_lanpld_irq,
+ enable_opsput_lanpld_irq,
+ disable_opsput_lanpld_irq,
+ mask_and_ack_opsput_lanpld,
+ end_opsput_lanpld_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
+ */
+#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
+#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
+
+static void disable_opsput_lcdpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lcdpldirq(irq);
+ port = lcdpldirq2port(pldirq);
+ data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_opsput_lcdpld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2lcdpldirq(irq);
+ port = lcdpldirq2port(pldirq);
+ data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_opsput_lcdpld(unsigned int irq)
+{
+ disable_opsput_lcdpld_irq(irq);
+}
+
+static void end_opsput_lcdpld_irq(unsigned int irq)
+{
+ enable_opsput_lcdpld_irq(irq);
+ end_opsput_irq(M32R_IRQ_INT2);
+}
+
+static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
+{
+ enable_opsput_lcdpld_irq(irq);
+ return (0);
+}
+
+static void shutdown_opsput_lcdpld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2lcdpldirq(irq);
+ port = lcdpldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type opsput_lcdpld_irq_type =
+{
+ "OPSPUT-PLD-LCD-IRQ",
+ startup_opsput_lcdpld_irq,
+ shutdown_opsput_lcdpld_irq,
+ enable_opsput_lcdpld_irq,
+ disable_opsput_lcdpld_irq,
+ mask_and_ack_opsput_lcdpld,
+ end_opsput_lcdpld_irq
+};
+
+void __init init_IRQ(void)
+{
+#if defined(CONFIG_SMC91X)
+ /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
+ irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
+ irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
+ irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
+ irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
+ lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
+ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
+#endif /* CONFIG_SMC91X */
+
+ /* MFT2 : system timer */
+ irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_MFT2].action = 0;
+ irq_desc[M32R_IRQ_MFT2].depth = 1;
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_opsput_irq(M32R_IRQ_MFT2);
+
+ /* SIO0 : receive */
+ irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].action = 0;
+ irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_opsput_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0 : send */
+ irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].action = 0;
+ irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_opsput_irq(M32R_IRQ_SIO0_S);
+
+ /* SIO1 : receive */
+ irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].action = 0;
+ irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_opsput_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1 : send */
+ irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].action = 0;
+ irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_opsput_irq(M32R_IRQ_SIO1_S);
+
+ /* DMA1 : */
+ irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_DMA1].action = 0;
+ irq_desc[M32R_IRQ_DMA1].depth = 1;
+ icu_data[M32R_IRQ_DMA1].icucr = 0;
+ disable_opsput_irq(M32R_IRQ_DMA1);
+
+#ifdef CONFIG_SERIAL_M32R_PLDSIO
+ /* INT#1: SIO0 Receive on PLD */
+ irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
+ irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
+ disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
+
+ /* INT#1: SIO0 Send on PLD */
+ irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_SIO0_SND].action = 0;
+ irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
+ disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
+#endif /* CONFIG_SERIAL_M32R_PLDSIO */
+
+#if defined(CONFIG_M32R_CFC)
+ /* INT#1: CFC IREQ on PLD */
+ irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_CFIREQ].action = 0;
+ irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
+ disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
+
+ /* INT#1: CFC Insert on PLD */
+ irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
+ irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
+ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
+
+ /* INT#1: CFC Eject on PLD */
+ irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
+ irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
+ irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
+ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
+#endif /* CONFIG_M32R_CFC */
+
+
+ /*
+ * INT0# is used for LAN, DIO
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
+ enable_opsput_irq(M32R_IRQ_INT0);
+
+ /*
+ * INT1# is used for UART, MMC, CF Controller in FPGA.
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
+ enable_opsput_irq(M32R_IRQ_INT1);
+
+#if defined(CONFIG_USB)
+ outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
+
+ irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
+ irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
+ irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
+ irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
+ lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
+ disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
+#endif
+ /*
+ * INT2# is used for BAT, USB, AUDIO
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
+ enable_opsput_irq(M32R_IRQ_INT2);
+
+//#if defined(CONFIG_M32R_AR_VGA)
+ /*
+ * INT3# is used for AR
+ */
+ irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
+ irq_desc[M32R_IRQ_INT3].action = 0;
+ irq_desc[M32R_IRQ_INT3].depth = 1;
+ icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
+ disable_opsput_irq(M32R_IRQ_INT3);
+//#endif /* CONFIG_M32R_ARV */
+}
+
+#define LAN_IOSTART 0x300
+#define LAN_IOEND 0x320
+static struct resource smc91x_resources[] = {
+ [0] = {
+ .start = (LAN_IOSTART),
+ .end = (LAN_IOEND),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = OPSPUT_LAN_IRQ_LAN,
+ .end = OPSPUT_LAN_IRQ_LAN,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device smc91x_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smc91x_resources),
+ .resource = smc91x_resources,
+};
+
+static int __init platform_init(void)
+{
+ platform_device_register(&smc91x_device);
+ return 0;
+}
+arch_initcall(platform_init);
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/setup_usrv.c
+ *
+ * Setup routines for MITSUBISHI uServer
+ *
+ * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ */
+
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/system.h>
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+#if !defined(CONFIG_SMP)
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+#endif /* CONFIG_SMP */
+
+icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
+
+static void disable_mappi_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_mappi_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_and_ack_mappi(unsigned int irq)
+{
+ disable_mappi_irq(irq);
+}
+
+static void end_mappi_irq(unsigned int irq)
+{
+ enable_mappi_irq(irq);
+}
+
+static unsigned int startup_mappi_irq(unsigned int irq)
+{
+ enable_mappi_irq(irq);
+ return 0;
+}
+
+static void shutdown_mappi_irq(unsigned int irq)
+{
+ unsigned long port;
+
+ port = irq2port(irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type mappi_irq_type =
+{
+ "M32700-IRQ",
+ startup_mappi_irq,
+ shutdown_mappi_irq,
+ enable_mappi_irq,
+ disable_mappi_irq,
+ mask_and_ack_mappi,
+ end_mappi_irq
+};
+
+/*
+ * Interrupt Control Unit of PLD on M32700UT (Level 2)
+ */
+#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
+#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+typedef struct {
+ unsigned short icucr; /* ICU Control Register */
+} pld_icu_data_t;
+
+static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
+
+static void disable_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_and_ack_m32700ut_pld(unsigned int irq)
+{
+ disable_m32700ut_pld_irq(irq);
+}
+
+static void end_m32700ut_pld_irq(unsigned int irq)
+{
+ enable_m32700ut_pld_irq(irq);
+ end_mappi_irq(M32R_IRQ_INT1);
+}
+
+static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
+{
+ enable_m32700ut_pld_irq(irq);
+ return 0;
+}
+
+static void shutdown_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+ port = pldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct hw_interrupt_type m32700ut_pld_irq_type =
+{
+ "USRV-PLD-IRQ",
+ startup_m32700ut_pld_irq,
+ shutdown_m32700ut_pld_irq,
+ enable_m32700ut_pld_irq,
+ disable_m32700ut_pld_irq,
+ mask_and_ack_m32700ut_pld,
+ end_m32700ut_pld_irq
+};
+
+void __init init_IRQ(void)
+{
+ static int once = 0;
+ int i;
+
+ if (once)
+ return;
+ else
+ once++;
+
+ /* MFT2 : system timer */
+ irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_MFT2].action = 0;
+ irq_desc[M32R_IRQ_MFT2].depth = 1;
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_mappi_irq(M32R_IRQ_MFT2);
+
+#if defined(CONFIG_SERIAL_M32R_SIO)
+ /* SIO0_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_R].action = 0;
+ irq_desc[M32R_IRQ_SIO0_R].depth = 1;
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0_S : uart send data */
+ irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO0_S].action = 0;
+ irq_desc[M32R_IRQ_SIO0_S].depth = 1;
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO0_S);
+
+ /* SIO1_R : uart receive data */
+ irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_R].action = 0;
+ irq_desc[M32R_IRQ_SIO1_R].depth = 1;
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1_S : uart send data */
+ irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
+ irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type;
+ irq_desc[M32R_IRQ_SIO1_S].action = 0;
+ irq_desc[M32R_IRQ_SIO1_S].depth = 1;
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO1_S);
+#endif /* CONFIG_SERIAL_M32R_SIO */
+
+ /* INT#67-#71: CFC#0 IREQ on PLD */
+ for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) {
+ irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_CF0 + i].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_CF0 + i].action = 0;
+ irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
+ = PLD_ICUCR_ISMOD01; /* 'L' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
+ }
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ /* INT#76: 16552D#0 IREQ on PLD */
+ irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_UART0].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_UART0].action = 0;
+ irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
+ = PLD_ICUCR_ISMOD03; /* 'H' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_UART0);
+
+ /* INT#77: 16552D#1 IREQ on PLD */
+ irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_UART1].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_UART1].action = 0;
+ irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
+ = PLD_ICUCR_ISMOD03; /* 'H' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_UART1);
+#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
+
+#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
+ /* INT#80: AK4524 IREQ on PLD */
+ irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
+ irq_desc[PLD_IRQ_SNDINT].handler = &m32700ut_pld_irq_type;
+ irq_desc[PLD_IRQ_SNDINT].action = 0;
+ irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
+ pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
+ = PLD_ICUCR_ISMOD01; /* 'L' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
+#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
+
+ /*
+ * INT1# is used for UART, MMC, CF Controller in FPGA.
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
+ enable_mappi_irq(M32R_IRQ_INT1);
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/signal.c
+ *
+ * Copyright (c) 2003 Hitoshi Yamamoto
+ *
+ * Taken from i386 version.
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson
+ * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes
+ */
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/unistd.h>
+#include <linux/stddef.h>
+#include <linux/personality.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/ucontext.h>
+#include <asm/uaccess.h>
+
+#define DEBUG_SIG 0
+
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+int do_signal(struct pt_regs *, sigset_t *);
+
+/*
+ * Atomically swap in the new signal mask, and wait for a signal.
+ */
+asmlinkage int
+sys_sigsuspend(old_sigset_t mask, unsigned long r1,
+ unsigned long r2, unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, struct pt_regs regs)
+{
+ sigset_t saveset;
+
+ mask &= _BLOCKABLE;
+ spin_lock_irq(¤t->sighand->siglock);
+ saveset = current->blocked;
+ siginitset(¤t->blocked, mask);
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ regs.r0 = -EINTR;
+ while (1) {
+ current->state = TASK_INTERRUPTIBLE;
+ schedule();
+ if (do_signal(®s, &saveset))
+ return regs.r0;
+ }
+}
+
+asmlinkage int
+sys_rt_sigsuspend(sigset_t *unewset, size_t sigsetsize,
+ unsigned long r2, unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, struct pt_regs regs)
+{
+ sigset_t saveset, newset;
+
+ /* XXX: Don't preclude handling different sized sigset_t's. */
+ if (sigsetsize != sizeof(sigset_t))
+ return -EINVAL;
+
+ if (copy_from_user(&newset, unewset, sizeof(newset)))
+ return -EFAULT;
+ sigdelsetmask(&newset, ~_BLOCKABLE);
+
+ spin_lock_irq(¤t->sighand->siglock);
+ saveset = current->blocked;
+ current->blocked = newset;
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ regs.r0 = -EINTR;
+ while (1) {
+ current->state = TASK_INTERRUPTIBLE;
+ schedule();
+ if (do_signal(®s, &saveset))
+ return regs.r0;
+ }
+}
+
+asmlinkage int
+sys_sigaction(int sig, const struct old_sigaction __user *act,
+ struct old_sigaction __user *oact)
+{
+ struct k_sigaction new_ka, old_ka;
+ int ret;
+
+ if (act) {
+ old_sigset_t mask;
+ if (verify_area(VERIFY_READ, act, sizeof(*act)) ||
+ __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
+ __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
+ return -EFAULT;
+ __get_user(new_ka.sa.sa_flags, &act->sa_flags);
+ __get_user(mask, &act->sa_mask);
+ siginitset(&new_ka.sa.sa_mask, mask);
+ }
+
+ ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+
+ if (!ret && oact) {
+ if (verify_area(VERIFY_WRITE, oact, sizeof(*oact)) ||
+ __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
+ __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
+ return -EFAULT;
+ __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
+ __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
+ }
+
+ return ret;
+}
+
+asmlinkage int
+sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
+ unsigned long r2, unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, struct pt_regs regs)
+{
+ return do_sigaltstack(uss, uoss, regs.spu);
+}
+
+
+/*
+ * Do a signal return; undo the signal stack.
+ */
+
+struct sigframe
+{
+// char *pretcode;
+ int sig;
+ struct sigcontext sc;
+// struct _fpstate fpstate;
+ unsigned long extramask[_NSIG_WORDS-1];
+ char retcode[4];
+};
+
+struct rt_sigframe
+{
+// char *pretcode;
+ int sig;
+ struct siginfo *pinfo;
+ void *puc;
+ struct siginfo info;
+ struct ucontext uc;
+// struct _fpstate fpstate;
+ char retcode[8];
+};
+
+static int
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc,
+ int *r0_p)
+{
+ unsigned int err = 0;
+
+ /* Always make any pending restarted system calls return -EINTR */
+ current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+#define COPY(x) err |= __get_user(regs->x, &sc->sc_##x)
+ COPY(r4);
+ COPY(r5);
+ COPY(r6);
+ COPY(pt_regs);
+ /* COPY(r0); Skip r0 */
+ COPY(r1);
+ COPY(r2);
+ COPY(r3);
+ COPY(r7);
+ COPY(r8);
+ COPY(r9);
+ COPY(r10);
+ COPY(r11);
+ COPY(r12);
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ COPY(acc0h);
+ COPY(acc0l);
+ COPY(acc1h);
+ COPY(acc1l);
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ COPY(acch);
+ COPY(accl);
+#else
+#error unknown isa configuration
+#endif
+ COPY(psw);
+ COPY(bpc);
+ COPY(bbpsw);
+ COPY(bbpc);
+ COPY(spu);
+ COPY(fp);
+ COPY(lr);
+ COPY(spi);
+#undef COPY
+
+ regs->syscall_nr = -1; /* disable syscall checks */
+ err |= __get_user(*r0_p, &sc->sc_r0);
+
+ return err;
+}
+
+asmlinkage int
+sys_sigreturn(unsigned long r0, unsigned long r1,
+ unsigned long r2, unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, struct pt_regs regs)
+{
+ struct sigframe __user *frame = (struct sigframe __user *)regs.spu;
+ sigset_t set;
+ int result;
+
+ if (verify_area(VERIFY_READ, frame, sizeof(*frame)))
+ goto badframe;
+ if (__get_user(set.sig[0], &frame->sc.oldmask)
+ || (_NSIG_WORDS > 1
+ && __copy_from_user(&set.sig[1], &frame->extramask,
+ sizeof(frame->extramask))))
+ goto badframe;
+
+ sigdelsetmask(&set, ~_BLOCKABLE);
+ spin_lock_irq(¤t->sighand->siglock);
+ current->blocked = set;
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ if (restore_sigcontext(®s, &frame->sc, &result))
+ goto badframe;
+ return result;
+
+badframe:
+ force_sig(SIGSEGV, current);
+ return 0;
+}
+
+asmlinkage int
+sys_rt_sigreturn(unsigned long r0, unsigned long r1,
+ unsigned long r2, unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, struct pt_regs regs)
+{
+ struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs.spu;
+ sigset_t set;
+ stack_t st;
+ int result;
+
+ if (verify_area(VERIFY_READ, frame, sizeof(*frame)))
+ goto badframe;
+ if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+ goto badframe;
+
+ sigdelsetmask(&set, ~_BLOCKABLE);
+ spin_lock_irq(¤t->sighand->siglock);
+ current->blocked = set;
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ if (restore_sigcontext(®s, &frame->uc.uc_mcontext, &result))
+ goto badframe;
+
+ if (__copy_from_user(&st, &frame->uc.uc_stack, sizeof(st)))
+ goto badframe;
+ /* It is more difficult to avoid calling this function than to
+ call it and ignore errors. */
+ do_sigaltstack(&st, NULL, regs.spu);
+
+ return result;
+
+badframe:
+ force_sig(SIGSEGV, current);
+ return 0;
+}
+
+/*
+ * Set up a signal frame.
+ */
+
+static int
+setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
+ unsigned long mask)
+{
+ int err = 0;
+
+#define COPY(x) err |= __put_user(regs->x, &sc->sc_##x)
+ COPY(r4);
+ COPY(r5);
+ COPY(r6);
+ COPY(pt_regs);
+ COPY(r0);
+ COPY(r1);
+ COPY(r2);
+ COPY(r3);
+ COPY(r7);
+ COPY(r8);
+ COPY(r9);
+ COPY(r10);
+ COPY(r11);
+ COPY(r12);
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ COPY(acc0h);
+ COPY(acc0l);
+ COPY(acc1h);
+ COPY(acc1l);
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ COPY(acch);
+ COPY(accl);
+#else
+#error unknown isa configuration
+#endif
+ COPY(psw);
+ COPY(bpc);
+ COPY(bbpsw);
+ COPY(bbpc);
+ COPY(spu);
+ COPY(fp);
+ COPY(lr);
+ COPY(spi);
+#undef COPY
+
+ err |= __put_user(mask, &sc->oldmask);
+
+ return err;
+}
+
+/*
+ * Determine which stack to use..
+ */
+static inline void __user *
+get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
+{
+ /* This is the X/Open sanctioned signal stack switching. */
+ if (ka->sa.sa_flags & SA_ONSTACK) {
+ if (sas_ss_flags(sp) == 0)
+ sp = current->sas_ss_sp + current->sas_ss_size;
+ }
+
+ return (void __user *)((sp - frame_size) & -8ul);
+}
+
+static void setup_frame(int sig, struct k_sigaction *ka,
+ sigset_t *set, struct pt_regs *regs)
+{
+ struct sigframe __user *frame;
+ int err = 0;
+ int signal;
+
+ frame = get_sigframe(ka, regs->spu, sizeof(*frame));
+
+ if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+ goto give_sigsegv;
+
+ signal = current_thread_info()->exec_domain
+ && current_thread_info()->exec_domain->signal_invmap
+ && sig < 32
+ ? current_thread_info()->exec_domain->signal_invmap[sig]
+ : sig;
+
+ err |= __put_user(signal, &frame->sig);
+ if (err)
+ goto give_sigsegv;
+
+ err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
+ if (err)
+ goto give_sigsegv;
+
+ if (_NSIG_WORDS > 1) {
+ err |= __copy_to_user(frame->extramask, &set->sig[1],
+ sizeof(frame->extramask));
+ if (err)
+ goto give_sigsegv;
+ }
+
+ if (ka->sa.sa_flags & SA_RESTORER)
+ regs->lr = (unsigned long)ka->sa.sa_restorer;
+ else {
+ /* This is : ldi r7, #__NR_sigreturn ; trap #2 */
+ unsigned long code = 0x670010f2 | (__NR_sigreturn << 16);
+
+ regs->lr = (unsigned long)frame->retcode;
+ err |= __put_user(code, (long __user *)(frame->retcode+0));
+ if (err)
+ goto give_sigsegv;
+ flush_cache_sigtramp((unsigned long)frame->retcode);
+ }
+
+ /* Set up registers for signal handler */
+ regs->spu = (unsigned long)frame;
+ regs->r0 = signal; /* Arg for signal handler */
+ regs->r1 = (unsigned long)&frame->sc;
+ regs->bpc = (unsigned long)ka->sa.sa_handler;
+
+ set_fs(USER_DS);
+
+#if DEBUG_SIG
+ printk("SIG deliver (%s:%d): sp=%p pc=%p\n",
+ current->comm, current->pid, frame, regs->pc);
+#endif
+
+ return;
+
+give_sigsegv:
+ force_sigsegv(sig, current);
+}
+
+static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+ sigset_t *set, struct pt_regs *regs)
+{
+ struct rt_sigframe __user *frame;
+ int err = 0;
+ int signal;
+
+ frame = get_sigframe(ka, regs->spu, sizeof(*frame));
+
+ if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+ goto give_sigsegv;
+
+ signal = current_thread_info()->exec_domain
+ && current_thread_info()->exec_domain->signal_invmap
+ && sig < 32
+ ? current_thread_info()->exec_domain->signal_invmap[sig]
+ : sig;
+
+ err |= __put_user(signal, &frame->sig);
+ if (err)
+ goto give_sigsegv;
+
+ err |= __put_user(&frame->info, &frame->pinfo);
+ err |= __put_user(&frame->uc, &frame->puc);
+ err |= copy_siginfo_to_user(&frame->info, info);
+ if (err)
+ goto give_sigsegv;
+
+ /* Create the ucontext. */
+ err |= __put_user(0, &frame->uc.uc_flags);
+ err |= __put_user(0, &frame->uc.uc_link);
+ err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
+ err |= __put_user(sas_ss_flags(regs->spu),
+ &frame->uc.uc_stack.ss_flags);
+ err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
+ err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
+ err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
+ if (err)
+ goto give_sigsegv;
+
+ /* Set up to return from userspace. */
+ if (ka->sa.sa_flags & SA_RESTORER)
+ regs->lr = (unsigned long)ka->sa.sa_restorer;
+ else {
+ /* This is : ldi r7, #__NR_rt_sigreturn ; trap #2 */
+ unsigned long code1 = 0x97f00000 | (__NR_rt_sigreturn);
+ unsigned long code2 = 0x10f2f000;
+
+ regs->lr = (unsigned long)frame->retcode;
+ err |= __put_user(code1, (long __user *)(frame->retcode+0));
+ err |= __put_user(code2, (long __user *)(frame->retcode+4));
+ if (err)
+ goto give_sigsegv;
+ flush_cache_sigtramp((unsigned long)frame->retcode);
+ }
+
+ /* Set up registers for signal handler */
+ regs->spu = (unsigned long)frame;
+ regs->r0 = signal; /* Arg for signal handler */
+ regs->r1 = (unsigned long)&frame->info;
+ regs->r2 = (unsigned long)&frame->uc;
+ regs->bpc = (unsigned long)ka->sa.sa_handler;
+
+ set_fs(USER_DS);
+
+#if DEBUG_SIG
+ printk("SIG deliver (%s:%d): sp=%p pc=%p\n",
+ current->comm, current->pid, frame, regs->pc);
+#endif
+
+ return;
+
+give_sigsegv:
+ force_sigsegv(sig, current);
+}
+
+/*
+ * OK, we're invoking a handler
+ */
+
+static void
+handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
+ sigset_t *oldset, struct pt_regs *regs)
+{
+ unsigned short inst;
+
+ /* Are we from a system call? */
+ if (regs->syscall_nr >= 0) {
+ /* If so, check system call restarting.. */
+ switch (regs->r0) {
+ case -ERESTART_RESTARTBLOCK:
+ case -ERESTARTNOHAND:
+ regs->r0 = -EINTR;
+ break;
+
+ case -ERESTARTSYS:
+ if (!(ka->sa.sa_flags & SA_RESTART)) {
+ regs->r0 = -EINTR;
+ break;
+ }
+ /* fallthrough */
+ case -ERESTARTNOINTR:
+ regs->r0 = regs->orig_r0;
+ inst = *(unsigned short *)(regs->bpc - 2);
+ if ((inst & 0xfff0) == 0x10f0) /* trap ? */
+ regs->bpc -= 2;
+ else
+ regs->bpc -= 4;
+ }
+ }
+
+ /* Set up the stack frame */
+ if (ka->sa.sa_flags & SA_SIGINFO)
+ setup_rt_frame(sig, ka, info, oldset, regs);
+ else
+ setup_frame(sig, ka, oldset, regs);
+
+ if (!(ka->sa.sa_flags & SA_NODEFER)) {
+ spin_lock_irq(¤t->sighand->siglock);
+ sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
+ sigaddset(¤t->blocked,sig);
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+ }
+}
+
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ */
+int do_signal(struct pt_regs *regs, sigset_t *oldset)
+{
+ siginfo_t info;
+ int signr;
+ struct k_sigaction ka;
+ unsigned short inst;
+
+ /*
+ * We want the common case to go fast, which
+ * is why we may in certain cases get here from
+ * kernel mode. Just return without doing anything
+ * if so.
+ */
+ if (!user_mode(regs))
+ return 1;
+
+ if (current->flags & PF_FREEZE) {
+ refrigerator(0);
+ goto no_signal;
+ }
+
+ if (!oldset)
+ oldset = ¤t->blocked;
+
+ signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+ if (signr > 0) {
+ /* Reenable any watchpoints before delivering the
+ * signal to user space. The processor register will
+ * have been cleared if the watchpoint triggered
+ * inside the kernel.
+ */
+
+ /* Whee! Actually deliver the signal. */
+ handle_signal(signr, &ka, &info, oldset, regs);
+ return 1;
+ }
+
+ no_signal:
+ /* Did we come from a system call? */
+ if (regs->syscall_nr >= 0) {
+ /* Restart the system call - no handlers present */
+ if (regs->r0 == -ERESTARTNOHAND ||
+ regs->r0 == -ERESTARTSYS ||
+ regs->r0 == -ERESTARTNOINTR) {
+ regs->r0 = regs->orig_r0;
+ inst = *(unsigned short *)(regs->bpc - 2);
+ if ((inst & 0xfff0) == 0x10f0) /* trap ? */
+ regs->bpc -= 2;
+ else
+ regs->bpc -= 4;
+ }
+ if (regs->r0 == -ERESTART_RESTARTBLOCK){
+ regs->r0 = regs->orig_r0;
+ regs->r7 = __NR_restart_syscall;
+ inst = *(unsigned short *)(regs->bpc - 2);
+ if ((inst & 0xfff0) == 0x10f0) /* trap ? */
+ regs->bpc -= 2;
+ else
+ regs->bpc -= 4;
+ }
+ }
+ return 0;
+}
+
+/*
+ * notification of userspace execution resumption
+ * - triggered by current->work.notify_resume
+ */
+void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
+ __u32 thread_info_flags)
+{
+ /* Pending single-step? */
+ if (thread_info_flags & _TIF_SINGLESTEP)
+ clear_thread_flag(TIF_SINGLESTEP);
+
+ /* deal with pending signal delivery */
+ if (thread_info_flags & _TIF_SIGPENDING)
+ do_signal(regs,oldset);
+
+ clear_thread_flag(TIF_IRET);
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/smp.c
+ *
+ * M32R SMP support routines.
+ *
+ * Copyright (c) 2001, 2002 Hitoshi Yamamoto
+ *
+ * Taken from i386 version.
+ * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
+ * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
+ *
+ * This code is released under the GNU General Public License version 2 or
+ * later.
+ */
+
+#undef DEBUG_SMP
+
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/profile.h>
+#include <linux/cpu.h>
+
+#include <asm/cacheflush.h>
+#include <asm/pgalloc.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/mmu_context.h>
+#include <asm/m32r.h>
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Data structures and variables */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*
+ * Structure and data for smp_call_function(). This is designed to minimise
+ * static memory requirements. It also looks cleaner.
+ */
+static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
+
+struct call_data_struct {
+ void (*func) (void *info);
+ void *info;
+ atomic_t started;
+ atomic_t finished;
+ int wait;
+} __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
+
+static struct call_data_struct *call_data;
+
+/*
+ * For flush_cache_all()
+ */
+static spinlock_t flushcache_lock = SPIN_LOCK_UNLOCKED;
+static volatile unsigned long flushcache_cpumask = 0;
+
+/*
+ * For flush_tlb_others()
+ */
+static volatile cpumask_t flush_cpumask;
+static struct mm_struct *flush_mm;
+static struct vm_area_struct *flush_vma;
+static volatile unsigned long flush_va;
+static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
+#define FLUSH_ALL 0xffffffff
+
+DECLARE_PER_CPU(int, prof_multiplier);
+DECLARE_PER_CPU(int, prof_old_multiplier);
+DECLARE_PER_CPU(int, prof_counter);
+
+extern spinlock_t ipi_lock[];
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Function Prototypes */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+void smp_send_reschedule(int);
+void smp_reschedule_interrupt(void);
+
+void smp_flush_cache_all(void);
+void smp_flush_cache_all_interrupt(void);
+
+void smp_flush_tlb_all(void);
+static void flush_tlb_all_ipi(void *);
+
+void smp_flush_tlb_mm(struct mm_struct *);
+void smp_flush_tlb_range(struct vm_area_struct *, unsigned long, \
+ unsigned long);
+void smp_flush_tlb_page(struct vm_area_struct *, unsigned long);
+static void flush_tlb_others(cpumask_t, struct mm_struct *,
+ struct vm_area_struct *, unsigned long);
+void smp_invalidate_interrupt(void);
+
+void smp_send_stop(void);
+static void stop_this_cpu(void *);
+
+int smp_call_function(void (*) (void *), void *, int, int);
+void smp_call_function_interrupt(void);
+
+void smp_send_timer(void);
+void smp_ipi_timer_interrupt(struct pt_regs *);
+void smp_local_timer_interrupt(struct pt_regs *);
+
+void send_IPI_allbutself(int, int);
+static void send_IPI_mask(cpumask_t, int, int);
+unsigned long send_IPI_mask_phys(cpumask_t, int, int);
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Rescheduling request Routines */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: smp_send_reschedule
+ *
+ * Description: This routine requests other CPU to execute rescheduling.
+ * 1.Send 'RESCHEDULE_IPI' to other CPU.
+ * Request other CPU to execute 'smp_reschedule_interrupt()'.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: cpu_id - Target CPU ID
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_send_reschedule(int cpu_id)
+{
+ WARN_ON(cpu_is_offline(cpu_id));
+ send_IPI_mask(cpumask_of_cpu(cpu_id), RESCHEDULE_IPI, 1);
+}
+
+/*==========================================================================*
+ * Name: smp_reschedule_interrupt
+ *
+ * Description: This routine executes on CPU which received
+ * 'RESCHEDULE_IPI'.
+ * Rescheduling is processed at the exit of interrupt
+ * operation.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_reschedule_interrupt(void)
+{
+ /* nothing to do */
+}
+
+/*==========================================================================*
+ * Name: smp_flush_cache_all
+ *
+ * Description: This routine sends a 'INVALIDATE_CACHE_IPI' to all other
+ * CPUs in the system.
+ *
+ * Born on Date: 2003-05-28
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_flush_cache_all(void)
+{
+ cpumask_t cpumask;
+ unsigned long *mask;
+
+ preempt_disable();
+ cpumask = cpu_online_map;
+ cpu_clear(smp_processor_id(), cpumask);
+ spin_lock(&flushcache_lock);
+ mask=cpus_addr(cpumask);
+ atomic_set_mask(*mask, (atomic_t *)&flushcache_cpumask);
+ send_IPI_mask(cpumask, INVALIDATE_CACHE_IPI, 0);
+ _flush_cache_copyback_all();
+ while (flushcache_cpumask)
+ mb();
+ spin_unlock(&flushcache_lock);
+ preempt_enable();
+}
+
+void smp_flush_cache_all_interrupt(void)
+{
+ _flush_cache_copyback_all();
+ clear_bit(smp_processor_id(), &flushcache_cpumask);
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* TLB flush request Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: smp_flush_tlb_all
+ *
+ * Description: This routine flushes all processes TLBs.
+ * 1.Request other CPU to execute 'flush_tlb_all_ipi()'.
+ * 2.Execute 'do_flush_tlb_all_local()'.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_flush_tlb_all(void)
+{
+ unsigned long flags;
+
+ preempt_disable();
+ local_irq_save(flags);
+ __flush_tlb_all();
+ local_irq_restore(flags);
+ smp_call_function(flush_tlb_all_ipi, 0, 1, 1);
+ preempt_enable();
+}
+
+/*==========================================================================*
+ * Name: flush_tlb_all_ipi
+ *
+ * Description: This routine flushes all local TLBs.
+ * 1.Execute 'do_flush_tlb_all_local()'.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *info - not used
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+static void flush_tlb_all_ipi(void *info)
+{
+ __flush_tlb_all();
+}
+
+/*==========================================================================*
+ * Name: smp_flush_tlb_mm
+ *
+ * Description: This routine flushes the specified mm context TLB's.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *mm - a pointer to the mm struct for flush TLB
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_flush_tlb_mm(struct mm_struct *mm)
+{
+ int cpu_id = smp_processor_id();
+ cpumask_t cpu_mask;
+ unsigned long *mmc = &mm->context[cpu_id];
+ unsigned long flags;
+
+ preempt_disable();
+ cpu_mask = mm->cpu_vm_mask;
+ cpu_clear(cpu_id, cpu_mask);
+
+ if (*mmc != NO_CONTEXT) {
+ local_irq_save(flags);
+ *mmc = NO_CONTEXT;
+ if (mm == current->mm)
+ activate_context(mm);
+ else
+ cpu_clear(cpu_id, mm->cpu_vm_mask);
+ local_irq_restore(flags);
+ }
+ if (!cpus_empty(cpu_mask))
+ flush_tlb_others(cpu_mask, mm, NULL, FLUSH_ALL);
+
+ preempt_enable();
+}
+
+/*==========================================================================*
+ * Name: smp_flush_tlb_range
+ *
+ * Description: This routine flushes a range of pages.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *mm - a pointer to the mm struct for flush TLB
+ * start - not used
+ * end - not used
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+ unsigned long end)
+{
+ smp_flush_tlb_mm(vma->vm_mm);
+}
+
+/*==========================================================================*
+ * Name: smp_flush_tlb_page
+ *
+ * Description: This routine flushes one page.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *vma - a pointer to the vma struct include va
+ * va - virtual address for flush TLB
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
+{
+ struct mm_struct *mm = vma->vm_mm;
+ int cpu_id = smp_processor_id();
+ cpumask_t cpu_mask;
+ unsigned long *mmc = &mm->context[cpu_id];
+ unsigned long flags;
+
+ preempt_disable();
+ cpu_mask = mm->cpu_vm_mask;
+ cpu_clear(cpu_id, cpu_mask);
+
+#ifdef DEBUG_SMP
+ if (!mm)
+ BUG();
+#endif
+
+ if (*mmc != NO_CONTEXT) {
+ local_irq_save(flags);
+ va &= PAGE_MASK;
+ va |= (*mmc & MMU_CONTEXT_ASID_MASK);
+ __flush_tlb_page(va);
+ local_irq_restore(flags);
+ }
+ if (!cpus_empty(cpu_mask))
+ flush_tlb_others(cpu_mask, mm, vma, va);
+
+ preempt_enable();
+}
+
+/*==========================================================================*
+ * Name: flush_tlb_others
+ *
+ * Description: This routine requests other CPU to execute flush TLB.
+ * 1.Setup parmeters.
+ * 2.Send 'INVALIDATE_TLB_IPI' to other CPU.
+ * Request other CPU to execute 'smp_invalidate_interrupt()'.
+ * 3.Wait for other CPUs operation finished.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: cpumask - bitmap of target CPUs
+ * *mm - a pointer to the mm struct for flush TLB
+ * *vma - a pointer to the vma struct include va
+ * va - virtual address for flush TLB
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
+ struct vm_area_struct *vma, unsigned long va)
+{
+ unsigned long *mask;
+#ifdef DEBUG_SMP
+ unsigned long flags;
+ __save_flags(flags);
+ if (!(flags & 0x0040)) /* Interrupt Disable NONONO */
+ BUG();
+#endif /* DEBUG_SMP */
+
+ /*
+ * A couple of (to be removed) sanity checks:
+ *
+ * - we do not send IPIs to not-yet booted CPUs.
+ * - current CPU must not be in mask
+ * - mask must exist :)
+ */
+ BUG_ON(cpus_empty(cpumask));
+
+ BUG_ON(cpu_isset(smp_processor_id(), cpumask));
+ BUG_ON(!mm);
+
+ /* If a CPU which we ran on has gone down, OK. */
+ cpus_and(cpumask, cpumask, cpu_online_map);
+ if (cpus_empty(cpumask))
+ return;
+
+ /*
+ * i'm not happy about this global shared spinlock in the
+ * MM hot path, but we'll see how contended it is.
+ * Temporarily this turns IRQs off, so that lockups are
+ * detected by the NMI watchdog.
+ */
+ spin_lock(&tlbstate_lock);
+
+ flush_mm = mm;
+ flush_vma = vma;
+ flush_va = va;
+ mask=cpus_addr(cpumask);
+ atomic_set_mask(*mask, (atomic_t *)&flush_cpumask);
+
+ /*
+ * We have to send the IPI only to
+ * CPUs affected.
+ */
+ send_IPI_mask(cpumask, INVALIDATE_TLB_IPI, 0);
+
+ while (!cpus_empty(flush_cpumask)) {
+ /* nothing. lockup detection does not belong here */
+ mb();
+ }
+
+ flush_mm = NULL;
+ flush_vma = NULL;
+ flush_va = 0;
+ spin_unlock(&tlbstate_lock);
+}
+
+/*==========================================================================*
+ * Name: smp_invalidate_interrupt
+ *
+ * Description: This routine executes on CPU which received
+ * 'INVALIDATE_TLB_IPI'.
+ * 1.Flush local TLB.
+ * 2.Report flush TLB process was finished.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_invalidate_interrupt(void)
+{
+ int cpu_id = smp_processor_id();
+ unsigned long *mmc = &flush_mm->context[cpu_id];
+
+ if (!cpu_isset(cpu_id, flush_cpumask))
+ return;
+
+ if (flush_va == FLUSH_ALL) {
+ *mmc = NO_CONTEXT;
+ if (flush_mm == current->active_mm)
+ activate_context(flush_mm);
+ else
+ cpu_clear(cpu_id, flush_mm->cpu_vm_mask);
+ } else {
+ unsigned long va = flush_va;
+
+ if (*mmc != NO_CONTEXT) {
+ va &= PAGE_MASK;
+ va |= (*mmc & MMU_CONTEXT_ASID_MASK);
+ __flush_tlb_page(va);
+ }
+ }
+ cpu_clear(cpu_id, flush_cpumask);
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Stop CPU request Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: smp_send_stop
+ *
+ * Description: This routine requests stop all CPUs.
+ * 1.Request other CPU to execute 'stop_this_cpu()'.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_send_stop(void)
+{
+ smp_call_function(stop_this_cpu, NULL, 1, 0);
+}
+
+/*==========================================================================*
+ * Name: stop_this_cpu
+ *
+ * Description: This routine halt CPU.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+static void stop_this_cpu(void *dummy)
+{
+ int cpu_id = smp_processor_id();
+
+ /*
+ * Remove this CPU:
+ */
+ cpu_clear(cpu_id, cpu_online_map);
+
+ /*
+ * PSW IE = 1;
+ * IMASK = 0;
+ * goto SLEEP
+ */
+ local_irq_disable();
+ outl(0, M32R_ICU_IMASK_PORTL);
+ inl(M32R_ICU_IMASK_PORTL); /* dummy read */
+ local_irq_enable();
+
+ for ( ; ; );
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Call function Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: smp_call_function
+ *
+ * Description: This routine sends a 'CALL_FUNCTION_IPI' to all other CPUs
+ * in the system.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *func - The function to run. This must be fast and
+ * non-blocking.
+ * *info - An arbitrary pointer to pass to the function.
+ * nonatomic - currently unused.
+ * wait - If true, wait (atomically) until function has
+ * completed on other CPUs.
+ *
+ * Returns: 0 on success, else a negative status code. Does not return
+ * until remote CPUs are nearly ready to execute <<func>> or
+ * are or have executed.
+ *
+ * Cautions: You must not call this function with disabled interrupts or
+ * from a hardware interrupt handler, you may call it from a
+ * bottom half handler.
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+int smp_call_function(void (*func) (void *info), void *info, int nonatomic,
+ int wait)
+{
+ struct call_data_struct data;
+ int cpus;
+
+#ifdef DEBUG_SMP
+ unsigned long flags;
+ __save_flags(flags);
+ if (!(flags & 0x0040)) /* Interrupt Disable NONONO */
+ BUG();
+#endif /* DEBUG_SMP */
+
+ /* Holding any lock stops cpus from going down. */
+ spin_lock(&call_lock);
+ cpus = num_online_cpus() - 1;
+
+ if (!cpus) {
+ spin_unlock(&call_lock);
+ return 0;
+ }
+
+ /* Can deadlock when called with interrupts disabled */
+ WARN_ON(irqs_disabled());
+
+ data.func = func;
+ data.info = info;
+ atomic_set(&data.started, 0);
+ data.wait = wait;
+ if (wait)
+ atomic_set(&data.finished, 0);
+
+ call_data = &data;
+ mb();
+
+ /* Send a message to all other CPUs and wait for them to respond */
+ send_IPI_allbutself(CALL_FUNCTION_IPI, 0);
+
+ /* Wait for response */
+ while (atomic_read(&data.started) != cpus)
+ barrier();
+
+ if (wait)
+ while (atomic_read(&data.finished) != cpus)
+ barrier();
+ spin_unlock(&call_lock);
+
+ return 0;
+}
+
+/*==========================================================================*
+ * Name: smp_call_function_interrupt
+ *
+ * Description: This routine executes on CPU which received
+ * 'CALL_FUNCTION_IPI'.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_call_function_interrupt(void)
+{
+ void (*func) (void *info) = call_data->func;
+ void *info = call_data->info;
+ int wait = call_data->wait;
+
+ /*
+ * Notify initiating CPU that I've grabbed the data and am
+ * about to execute the function
+ */
+ mb();
+ atomic_inc(&call_data->started);
+ /*
+ * At this point the info structure may be out of scope unless wait==1
+ */
+ irq_enter();
+ (*func)(info);
+ irq_exit();
+
+ if (wait) {
+ mb();
+ atomic_inc(&call_data->finished);
+ }
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Timer Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: smp_send_timer
+ *
+ * Description: This routine sends a 'LOCAL_TIMER_IPI' to all other CPUs
+ * in the system.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_send_timer(void)
+{
+ send_IPI_allbutself(LOCAL_TIMER_IPI, 1);
+}
+
+/*==========================================================================*
+ * Name: smp_send_timer
+ *
+ * Description: This routine executes on CPU which received
+ * 'LOCAL_TIMER_IPI'.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *regs - a pointer to the saved regster info
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void smp_ipi_timer_interrupt(struct pt_regs *regs)
+{
+ irq_enter();
+ smp_local_timer_interrupt(regs);
+ irq_exit();
+}
+
+/*==========================================================================*
+ * Name: smp_local_timer_interrupt
+ *
+ * Description: Local timer interrupt handler. It does both profiling and
+ * process statistics/rescheduling.
+ * We do profiling in every local tick, statistics/rescheduling
+ * happen only every 'profiling multiplier' ticks. The default
+ * multiplier is 1 and it can be changed by writing the new
+ * multiplier value into /proc/profile.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *regs - a pointer to the saved regster info
+ *
+ * Returns: void (cannot fail)
+ *
+ * Original: arch/i386/kernel/apic.c
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ * 2003-06-24 hy use per_cpu structure.
+ *==========================================================================*/
+void smp_local_timer_interrupt(struct pt_regs *regs)
+{
+ int user = user_mode(regs);
+ int cpu_id = smp_processor_id();
+
+ /*
+ * The profiling function is SMP safe. (nothing can mess
+ * around with "current", and the profiling counters are
+ * updated with atomic operations). This is especially
+ * useful with a profiling multiplier != 1
+ */
+
+ profile_tick(CPU_PROFILING, regs);
+
+ if (--per_cpu(prof_counter, cpu_id) <= 0) {
+ /*
+ * The multiplier may have changed since the last time we got
+ * to this point as a result of the user writing to
+ * /proc/profile. In this case we need to adjust the APIC
+ * timer accordingly.
+ *
+ * Interrupts are already masked off at this point.
+ */
+ per_cpu(prof_counter, cpu_id)
+ = per_cpu(prof_multiplier, cpu_id);
+ if (per_cpu(prof_counter, cpu_id)
+ != per_cpu(prof_old_multiplier, cpu_id))
+ {
+ per_cpu(prof_old_multiplier, cpu_id)
+ = per_cpu(prof_counter, cpu_id);
+ }
+
+ update_process_times(user);
+ }
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Send IPI Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: send_IPI_allbutself
+ *
+ * Description: This routine sends a IPI to all other CPUs in the system.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: ipi_num - Number of IPI
+ * try - 0 : Send IPI certainly.
+ * !0 : The following IPI is not sended when Target CPU
+ * has not received the before IPI.
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+void send_IPI_allbutself(int ipi_num, int try)
+{
+ cpumask_t cpumask;
+
+ cpumask = cpu_online_map;
+ cpu_clear(smp_processor_id(), cpumask);
+
+ send_IPI_mask(cpumask, ipi_num, try);
+}
+
+/*==========================================================================*
+ * Name: send_IPI_mask
+ *
+ * Description: This routine sends a IPI to CPUs in the system.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: cpu_mask - Bitmap of target CPUs logical ID
+ * ipi_num - Number of IPI
+ * try - 0 : Send IPI certainly.
+ * !0 : The following IPI is not sended when Target CPU
+ * has not received the before IPI.
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+static void send_IPI_mask(cpumask_t cpumask, int ipi_num, int try)
+{
+ cpumask_t physid_mask, tmp;
+ int cpu_id, phys_id;
+ int num_cpus = num_online_cpus();
+
+ if (num_cpus <= 1) /* NO MP */
+ return;
+
+ cpus_and(tmp, cpumask, cpu_online_map);
+ BUG_ON(!cpus_equal(cpumask, tmp));
+
+ physid_mask = CPU_MASK_NONE;
+ for_each_cpu_mask(cpu_id, cpumask){
+ if ((phys_id = cpu_to_physid(cpu_id)) != -1)
+ cpu_set(phys_id, physid_mask);
+ }
+
+ send_IPI_mask_phys(physid_mask, ipi_num, try);
+}
+
+/*==========================================================================*
+ * Name: send_IPI_mask_phys
+ *
+ * Description: This routine sends a IPI to other CPUs in the system.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: cpu_mask - Bitmap of target CPUs physical ID
+ * ipi_num - Number of IPI
+ * try - 0 : Send IPI certainly.
+ * !0 : The following IPI is not sended when Target CPU
+ * has not received the before IPI.
+ *
+ * Returns: IPICRi regster value.
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ *
+ *==========================================================================*/
+unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num,
+ int try)
+{
+ spinlock_t *ipilock;
+ unsigned long flags = 0;
+ volatile unsigned long *ipicr_addr;
+ unsigned long ipicr_val;
+ unsigned long my_physid_mask;
+ unsigned long mask = cpus_addr(physid_mask)[0];
+
+
+ if (mask & ~physids_coerce(phys_cpu_present_map))
+ BUG();
+ if (ipi_num >= NR_IPIS)
+ BUG();
+
+ mask <<= IPI_SHIFT;
+ ipilock = &ipi_lock[ipi_num];
+ ipicr_addr = (volatile unsigned long *)(M32R_ICU_IPICR_ADDR
+ + (ipi_num << 2));
+ my_physid_mask = ~(1 << smp_processor_id());
+
+ /*
+ * lock ipi_lock[i]
+ * check IPICRi == 0
+ * write IPICRi (send IPIi)
+ * unlock ipi_lock[i]
+ */
+ __asm__ __volatile__ (
+ ";; LOCK ipi_lock[i] \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "mvfc %1, psw \n\t"
+ "clrpsw #0x40 -> nop \n\t"
+ DCACHE_CLEAR("r4", "r5", "%2")
+ "lock r4, @%2 \n\t"
+ "addi r4, #-1 \n\t"
+ "unlock r4, @%2 \n\t"
+ "mvtc %1, psw \n\t"
+ "bnez r4, 2f \n\t"
+ LOCK_SECTION_START(".balign 4 \n\t")
+ ".fillinsn \n"
+ "2: \n\t"
+ "ld r4, @%2 \n\t"
+ "blez r4, 2b \n\t"
+ "bra 1b \n\t"
+ LOCK_SECTION_END
+ ";; CHECK IPICRi == 0 \n\t"
+ ".fillinsn \n"
+ "3: \n\t"
+ "ld %0, @%3 \n\t"
+ "and %0, %6 \n\t"
+ "beqz %0, 4f \n\t"
+ "bnez %5, 5f \n\t"
+ "bra 3b \n\t"
+ ";; WRITE IPICRi (send IPIi) \n\t"
+ ".fillinsn \n"
+ "4: \n\t"
+ "st %4, @%3 \n\t"
+ ";; UNLOCK ipi_lock[i] \n\t"
+ ".fillinsn \n"
+ "5: \n\t"
+ "ldi r4, #1 \n\t"
+ "st r4, @%2 \n\t"
+ : "=&r"(ipicr_val)
+ : "r"(flags), "r"(&ipilock->lock), "r"(ipicr_addr),
+ "r"(mask), "r"(try), "r"(my_physid_mask)
+ : "memory", "r4"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r5"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+
+ return ipicr_val;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/smpboot.c
+ * orig : i386 2.4.10
+ *
+ * M32R SMP booting functions
+ *
+ * Copyright (c) 2001, 2002, 2003 Hitoshi Yamamoto
+ *
+ * Taken from i386 version.
+ * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
+ * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
+ *
+ * Much of the core SMP work is based on previous work by Thomas Radke, to
+ * whom a great many thanks are extended.
+ *
+ * Thanks to Intel for making available several different Pentium,
+ * Pentium Pro and Pentium-II/Xeon MP machines.
+ * Original development of Linux SMP code supported by Caldera.
+ *
+ * This code is released under the GNU General Public License version 2 or
+ * later.
+ *
+ * Fixes
+ * Felix Koop : NR_CPUS used properly
+ * Jose Renau : Handle single CPU case.
+ * Alan Cox : By repeated request
+ * 8) - Total BogoMIP report.
+ * Greg Wright : Fix for kernel stacks panic.
+ * Erich Boleyn : MP v1.4 and additional changes.
+ * Matthias Sattler : Changes for 2.1 kernel map.
+ * Michel Lespinasse : Changes for 2.1 kernel map.
+ * Michael Chastain : Change trampoline.S to gnu as.
+ * Alan Cox : Dumb bug: 'B' step PPro's are fine
+ * Ingo Molnar : Added APIC timers, based on code
+ * from Jose Renau
+ * Ingo Molnar : various cleanups and rewrites
+ * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
+ * Maciej W. Rozycki : Bits for genuine 82489DX APICs
+ * Martin J. Bligh : Added support for multi-quad systems
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/smp_lock.h>
+#include <linux/irq.h>
+#include <linux/bootmem.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+#define DEBUG_SMP
+#ifdef DEBUG_SMP
+#define Dprintk(x...) printk(x)
+#else
+#define Dprintk(x...)
+#endif
+
+extern int cpu_idle(void);
+extern cpumask_t cpu_initialized;
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Data structures and variables */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/* Processor that is doing the boot up */
+static unsigned int bsp_phys_id = -1;
+
+/* Bitmask of physically existing CPUs */
+physid_mask_t phys_cpu_present_map;
+
+/* Bitmask of currently online CPUs */
+cpumask_t cpu_online_map;
+
+cpumask_t cpu_bootout_map;
+cpumask_t cpu_bootin_map;
+cpumask_t cpu_callout_map;
+static cpumask_t cpu_callin_map;
+
+/* Per CPU bogomips and other parameters */
+struct cpuinfo_m32r cpu_data[NR_CPUS] __cacheline_aligned;
+
+/* Set when the idlers are all forked */
+int smp_threads_ready;
+
+static int cpucount;
+static cpumask_t smp_commenced_mask;
+
+extern struct {
+ void * spi;
+ unsigned short ss;
+} stack_start;
+
+/* which physical physical ID maps to which logical CPU number */
+static volatile int physid_2_cpu[NR_CPUS];
+
+/* which logical CPU number maps to which physical ID */
+volatile int cpu_2_physid[NR_CPUS];
+
+DEFINE_PER_CPU(int, prof_multiplier) = 1;
+DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
+DEFINE_PER_CPU(int, prof_counter) = 1;
+
+spinlock_t ipi_lock[NR_IPIS];
+
+static unsigned int calibration_result;
+
+unsigned long cache_decay_ticks = HZ / 100;
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Function Prototypes */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+void smp_prepare_boot_cpu(void);
+void smp_prepare_cpus(unsigned int);
+static void smp_tune_scheduling(void);
+static void init_ipi_lock(void);
+static void do_boot_cpu(int);
+int __cpu_up(unsigned int);
+void smp_cpus_done(unsigned int);
+
+int start_secondary(void *);
+static void smp_callin(void);
+static void smp_online(void);
+
+static void show_mp_info(int);
+static void smp_store_cpu_info(int);
+static void show_cpu_info(int);
+int setup_profiling_timer(unsigned int);
+static void init_cpu_to_physid(void);
+static void map_cpu_to_physid(int, int);
+static void unmap_cpu_to_physid(int, int);
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Boot up APs Routins : BSP */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+void __devinit smp_prepare_boot_cpu(void)
+{
+ bsp_phys_id = hard_smp_processor_id();
+ physid_set(bsp_phys_id, phys_cpu_present_map);
+ cpu_set(0, cpu_online_map); /* BSP's cpu_id == 0 */
+ cpu_set(0, cpu_callout_map);
+ cpu_set(0, cpu_callin_map);
+
+ /*
+ * Initialize the logical to physical CPU number mapping
+ */
+ init_cpu_to_physid();
+ map_cpu_to_physid(0, bsp_phys_id);
+ current_thread_info()->cpu = 0;
+}
+
+/*==========================================================================*
+ * Name: smp_prepare_cpus (old smp_boot_cpus)
+ *
+ * Description: This routine boot up APs.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ * 2003-06-24 hy modify for linux-2.5.69
+ *
+ *==========================================================================*/
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+ int phys_id;
+ unsigned long nr_cpu;
+
+ nr_cpu = inl(M32R_FPGA_NUM_OF_CPUS_PORTL);
+ if (nr_cpu > NR_CPUS) {
+ printk(KERN_INFO "NUM_OF_CPUS reg. value [%ld] > NR_CPU [%d]",
+ nr_cpu, NR_CPUS);
+ goto smp_done;
+ }
+ for (phys_id = 0 ; phys_id < nr_cpu ; phys_id++)
+ physid_set(phys_id, phys_cpu_present_map);
+
+ show_mp_info(nr_cpu);
+
+ init_ipi_lock();
+
+ /*
+ * Setup boot CPU information
+ */
+ smp_store_cpu_info(0); /* Final full version of the data */
+ smp_tune_scheduling();
+
+ /*
+ * If SMP should be disabled, then really disable it!
+ */
+ if (!max_cpus) {
+ printk(KERN_INFO "SMP mode deactivated by commandline.\n");
+ goto smp_done;
+ }
+
+ /*
+ * Now scan the CPU present map and fire up the other CPUs.
+ */
+ Dprintk("CPU present map : %lx\n", physids_coerce(phys_cpu_present_map));
+
+ for (phys_id = 0 ; phys_id < NR_CPUS ; phys_id++) {
+ /*
+ * Don't even attempt to start the boot CPU!
+ */
+ if (phys_id == bsp_phys_id)
+ continue;
+
+ if (!physid_isset(phys_id, phys_cpu_present_map))
+ continue;
+
+ if ((max_cpus >= 0) && (max_cpus <= cpucount + 1))
+ continue;
+
+ do_boot_cpu(phys_id);
+
+ /*
+ * Make sure we unmap all failed CPUs
+ */
+ if (physid_to_cpu(phys_id) == -1) {
+ physid_clear(phys_id, phys_cpu_present_map);
+ printk("phys CPU#%d not responding - " \
+ "cannot use it.\n", phys_id);
+ }
+ }
+
+smp_done:
+ Dprintk("Boot done.\n");
+}
+
+static void __init smp_tune_scheduling(void)
+{
+ /* Nothing to do. */
+}
+
+/*
+ * init_ipi_lock : Initialize IPI locks.
+ */
+static void __init init_ipi_lock(void)
+{
+ int ipi;
+
+ for (ipi = 0 ; ipi < NR_IPIS ; ipi++)
+ ipi_lock[ipi] = SPIN_LOCK_UNLOCKED;
+}
+
+/*==========================================================================*
+ * Name: do_boot_cpu
+ *
+ * Description: This routine boot up one AP.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: phys_id - Target CPU physical ID
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ * 2003-06-24 hy modify for linux-2.5.69
+ *
+ *==========================================================================*/
+static void __init do_boot_cpu(int phys_id)
+{
+ struct task_struct *idle;
+ unsigned long send_status, boot_status;
+ int timeout, cpu_id;
+
+ cpu_id = ++cpucount;
+
+ /*
+ * We can't use kernel_thread since we must avoid to
+ * reschedule the child.
+ */
+ idle = fork_idle(cpu_id);
+ if (IS_ERR(idle))
+ panic("failed fork for CPU#%d.", cpu_id);
+
+ idle->thread.lr = (unsigned long)start_secondary;
+
+ map_cpu_to_physid(cpu_id, phys_id);
+
+ /* So we see what's up */
+ printk("Booting processor %d/%d\n", phys_id, cpu_id);
+ stack_start.spi = (void *)idle->thread.sp;
+ idle->thread_info->cpu = cpu_id;
+
+ /*
+ * Send Startup IPI
+ * 1.IPI received by CPU#(phys_id).
+ * 2.CPU#(phys_id) enter startup_AP (arch/m32r/kernel/head.S)
+ * 3.CPU#(phys_id) enter start_secondary()
+ */
+ send_status = 0;
+ boot_status = 0;
+
+ cpu_set(phys_id, cpu_bootout_map);
+
+ /* Send Startup IPI */
+ send_IPI_mask_phys(cpumask_of_cpu(phys_id), CPU_BOOT_IPI, 0);
+
+ Dprintk("Waiting for send to finish...\n");
+ timeout = 0;
+
+ /* Wait 100[ms] */
+ do {
+ Dprintk("+");
+ udelay(1000);
+ send_status = !cpu_isset(phys_id, cpu_bootin_map);
+ } while (send_status && (timeout++ < 100));
+
+ Dprintk("After Startup.\n");
+
+ if (!send_status) {
+ /*
+ * allow APs to start initializing.
+ */
+ Dprintk("Before Callout %d.\n", cpu_id);
+ cpu_set(cpu_id, cpu_callout_map);
+ Dprintk("After Callout %d.\n", cpu_id);
+
+ /*
+ * Wait 5s total for a response
+ */
+ for (timeout = 0; timeout < 5000; timeout++) {
+ if (cpu_isset(cpu_id, cpu_callin_map))
+ break; /* It has booted */
+ udelay(1000);
+ }
+
+ if (cpu_isset(cpu_id, cpu_callin_map)) {
+ /* number CPUs logically, starting from 1 (BSP is 0) */
+ Dprintk("OK.\n");
+ } else {
+ boot_status = 1;
+ printk("Not responding.\n");
+ }
+ } else
+ printk("IPI never delivered???\n");
+
+ if (send_status || boot_status) {
+ unmap_cpu_to_physid(cpu_id, phys_id);
+ cpu_clear(cpu_id, cpu_callout_map);
+ cpu_clear(cpu_id, cpu_callin_map);
+ cpu_clear(cpu_id, cpu_initialized);
+ cpucount--;
+ }
+}
+
+int __devinit __cpu_up(unsigned int cpu_id)
+{
+ int timeout;
+
+ cpu_set(cpu_id, smp_commenced_mask);
+
+ /*
+ * Wait 5s total for a response
+ */
+ for (timeout = 0; timeout < 5000; timeout++) {
+ if (cpu_isset(cpu_id, cpu_online_map))
+ break;
+ udelay(1000);
+ }
+ if (!cpu_isset(cpu_id, cpu_online_map))
+ BUG();
+
+ return 0;
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+ int cpu_id, timeout;
+ unsigned long bogosum = 0;
+
+ for (timeout = 0; timeout < 5000; timeout++) {
+ if (cpus_equal(cpu_callin_map, cpu_online_map))
+ break;
+ udelay(1000);
+ }
+ if (!cpus_equal(cpu_callin_map, cpu_online_map))
+ BUG();
+
+ for (cpu_id = 0 ; cpu_id < num_online_cpus() ; cpu_id++)
+ show_cpu_info(cpu_id);
+
+ /*
+ * Allow the user to impress friends.
+ */
+ Dprintk("Before bogomips.\n");
+ if (cpucount) {
+ for_each_cpu_mask(cpu_id, cpu_online_map)
+ bogosum += cpu_data[cpu_id].loops_per_jiffy;
+
+ printk(KERN_INFO "Total of %d processors activated " \
+ "(%lu.%02lu BogoMIPS).\n", cpucount + 1,
+ bogosum / (500000 / HZ),
+ (bogosum / (5000 / HZ)) % 100);
+ Dprintk("Before bogocount - setting activated=1.\n");
+ }
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Activate a secondary processor Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+
+/*==========================================================================*
+ * Name: start_secondary
+ *
+ * Description: This routine activate a secondary processor.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: *unused - currently unused.
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ * 2003-06-24 hy modify for linux-2.5.69
+ *
+ *==========================================================================*/
+int __init start_secondary(void *unused)
+{
+ cpu_init();
+ smp_callin();
+ while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
+ rep_nop();
+
+ smp_online();
+
+ /*
+ * low-memory mappings have been cleared, flush them from
+ * the local TLBs too.
+ */
+ local_flush_tlb_all();
+
+ return cpu_idle();
+}
+
+/*==========================================================================*
+ * Name: smp_callin
+ *
+ * Description: This routine activate a secondary processor.
+ *
+ * Born on Date: 2002.02.05
+ *
+ * Arguments: NONE
+ *
+ * Returns: void (cannot fail)
+ *
+ * Modification log:
+ * Date Who Description
+ * ---------- --- --------------------------------------------------------
+ * 2003-06-24 hy modify for linux-2.5.69
+ *
+ *==========================================================================*/
+static void __init smp_callin(void)
+{
+ int phys_id = hard_smp_processor_id();
+ int cpu_id = smp_processor_id();
+ unsigned long timeout;
+
+ if (cpu_isset(cpu_id, cpu_callin_map)) {
+ printk("huh, phys CPU#%d, CPU#%d already present??\n",
+ phys_id, cpu_id);
+ BUG();
+ }
+ Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpu_id, phys_id);
+
+ /* Waiting 2s total for startup (udelay is not yet working) */
+ timeout = jiffies + (2 * HZ);
+ while (time_before(jiffies, timeout)) {
+ /* Has the boot CPU finished it's STARTUP sequence ? */
+ if (cpu_isset(cpu_id, cpu_callout_map))
+ break;
+ rep_nop();
+ }
+
+ if (!time_before(jiffies, timeout)) {
+ printk("BUG: CPU#%d started up but did not get a callout!\n",
+ cpu_id);
+ BUG();
+ }
+
+ /* Allow the master to continue. */
+ cpu_set(cpu_id, cpu_callin_map);
+}
+
+static void __init smp_online(void)
+{
+ int cpu_id = smp_processor_id();
+
+ local_irq_enable();
+
+ /* Get our bogomips. */
+ calibrate_delay();
+
+ /* Save our processor parameters */
+ smp_store_cpu_info(cpu_id);
+
+ cpu_set(cpu_id, cpu_online_map);
+}
+
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+/* Boot up CPUs common Routins */
+/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
+static void __init show_mp_info(int nr_cpu)
+{
+ int i;
+ char cpu_model0[17], cpu_model1[17], cpu_ver[9];
+
+ strncpy(cpu_model0, (char *)M32R_FPGA_CPU_NAME_ADDR, 16);
+ strncpy(cpu_model1, (char *)M32R_FPGA_MODEL_ID_ADDR, 16);
+ strncpy(cpu_ver, (char *)M32R_FPGA_VERSION_ADDR, 8);
+
+ cpu_model0[16] = '\0';
+ for (i = 15 ; i >= 0 ; i--) {
+ if (cpu_model0[i] != ' ')
+ break;
+ cpu_model0[i] = '\0';
+ }
+ cpu_model1[16] = '\0';
+ for (i = 15 ; i >= 0 ; i--) {
+ if (cpu_model1[i] != ' ')
+ break;
+ cpu_model1[i] = '\0';
+ }
+ cpu_ver[8] = '\0';
+ for (i = 7 ; i >= 0 ; i--) {
+ if (cpu_ver[i] != ' ')
+ break;
+ cpu_ver[i] = '\0';
+ }
+
+ printk(KERN_INFO "M32R-mp information\n");
+ printk(KERN_INFO " On-chip CPUs : %d\n", nr_cpu);
+ printk(KERN_INFO " CPU model : %s/%s(%s)\n", cpu_model0,
+ cpu_model1, cpu_ver);
+}
+
+/*
+ * The bootstrap kernel entry code has set these up. Save them for
+ * a given CPU
+ */
+static void __init smp_store_cpu_info(int cpu_id)
+{
+ struct cpuinfo_m32r *ci = cpu_data + cpu_id;
+
+ *ci = boot_cpu_data;
+ ci->loops_per_jiffy = loops_per_jiffy;
+}
+
+static void __init show_cpu_info(int cpu_id)
+{
+ struct cpuinfo_m32r *ci = &cpu_data[cpu_id];
+
+ printk("CPU#%d : ", cpu_id);
+
+#define PRINT_CLOCK(name, value) \
+ printk(name " clock %d.%02dMHz", \
+ ((value) / 1000000), ((value) % 1000000) / 10000)
+
+ PRINT_CLOCK("CPU", (int)ci->cpu_clock);
+ PRINT_CLOCK(", Bus", (int)ci->bus_clock);
+ printk(", loops_per_jiffy[%ld]\n", ci->loops_per_jiffy);
+}
+
+/*
+ * the frequency of the profiling timer can be changed
+ * by writing a multiplier value into /proc/profile.
+ */
+int setup_profiling_timer(unsigned int multiplier)
+{
+ int i;
+
+ /*
+ * Sanity check. [at least 500 APIC cycles should be
+ * between APIC interrupts as a rule of thumb, to avoid
+ * irqs flooding us]
+ */
+ if ( (!multiplier) || (calibration_result / multiplier < 500))
+ return -EINVAL;
+
+ /*
+ * Set the new multiplier for each CPU. CPUs don't start using the
+ * new values until the next timer interrupt in which they do process
+ * accounting. At that time they also adjust their APIC timers
+ * accordingly.
+ */
+ for (i = 0; i < NR_CPUS; ++i)
+ per_cpu(prof_multiplier, i) = multiplier;
+
+ return 0;
+}
+
+/* Initialize all maps between cpu number and apicids */
+static void __init init_cpu_to_physid(void)
+{
+ int i;
+
+ for (i = 0 ; i < NR_CPUS ; i++) {
+ cpu_2_physid[i] = -1;
+ physid_2_cpu[i] = -1;
+ }
+}
+
+/*
+ * set up a mapping between cpu and apicid. Uses logical apicids for multiquad,
+ * else physical apic ids
+ */
+static void __init map_cpu_to_physid(int cpu_id, int phys_id)
+{
+ physid_2_cpu[phys_id] = cpu_id;
+ cpu_2_physid[cpu_id] = phys_id;
+}
+
+/*
+ * undo a mapping between cpu and apicid. Uses logical apicids for multiquad,
+ * else physical apic ids
+ */
+static void __init unmap_cpu_to_physid(int cpu_id, int phys_id)
+{
+ physid_2_cpu[phys_id] = -1;
+ cpu_2_physid[cpu_id] = -1;
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/sys_m32r.c
+ *
+ * This file contains various random system calls that
+ * have a non-standard calling sequence on the Linux/M32R platform.
+ *
+ * Taken from i386 version.
+ */
+
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/sem.h>
+#include <linux/msg.h>
+#include <linux/shm.h>
+#include <linux/stat.h>
+#include <linux/syscalls.h>
+#include <linux/mman.h>
+#include <linux/file.h>
+#include <linux/utsname.h>
+
+#include <asm/uaccess.h>
+#include <asm/cachectl.h>
+#include <asm/cacheflush.h>
+#include <asm/ipc.h>
+
+/*
+ * sys_tas() - test-and-set
+ * linuxthreads testing version
+ */
+#ifndef CONFIG_SMP
+asmlinkage int sys_tas(int *addr)
+{
+ int oldval;
+ unsigned long flags;
+
+ if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
+ return -EFAULT;
+ local_irq_save(flags);
+ oldval = *addr;
+ *addr = 1;
+ local_irq_restore(flags);
+ return oldval;
+}
+#else /* CONFIG_SMP */
+#include <linux/spinlock.h>
+
+static spinlock_t tas_lock = SPIN_LOCK_UNLOCKED;
+
+asmlinkage int sys_tas(int *addr)
+{
+ int oldval;
+
+ if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
+ return -EFAULT;
+
+ spin_lock(&tas_lock);
+ oldval = *addr;
+ *addr = 1;
+ spin_unlock(&tas_lock);
+
+ return oldval;
+}
+#endif /* CONFIG_SMP */
+
+/*
+ * sys_pipe() is the normal C calling standard for creating
+ * a pipe. It's not the way Unix traditionally does this, though.
+ */
+asmlinkage int
+sys_pipe(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, struct pt_regs regs)
+{
+ int fd[2];
+ int error;
+
+ error = do_pipe(fd);
+ if (!error) {
+ if (copy_to_user((void *)r0, (void *)fd, 2*sizeof(int)))
+ error = -EFAULT;
+ }
+ return error;
+}
+
+asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
+ unsigned long prot, unsigned long flags,
+ unsigned long fd, unsigned long pgoff)
+{
+ int error = -EBADF;
+ struct file *file = NULL;
+
+ flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
+ if (!(flags & MAP_ANONYMOUS)) {
+ file = fget(fd);
+ if (!file)
+ goto out;
+ }
+
+ down_write(¤t->mm->mmap_sem);
+ error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
+ up_write(¤t->mm->mmap_sem);
+
+ if (file)
+ fput(file);
+out:
+ return error;
+}
+
+/*
+ * sys_ipc() is the de-multiplexer for the SysV IPC calls..
+ *
+ * This is really horribly ugly.
+ */
+asmlinkage int sys_ipc(uint call, int first, int second,
+ int third, void __user *ptr, long fifth)
+{
+ int version, ret;
+
+ version = call >> 16; /* hack for backward compatibility */
+ call &= 0xffff;
+
+ switch (call) {
+ case SEMOP:
+ return sys_semtimedop(first, (struct sembuf __user *)ptr,
+ second, NULL);
+ case SEMTIMEDOP:
+ return sys_semtimedop(first, (struct sembuf __user *)ptr,
+ second, (const struct timespec __user *)fifth);
+ case SEMGET:
+ return sys_semget (first, second, third);
+ case SEMCTL: {
+ union semun fourth;
+ if (!ptr)
+ return -EINVAL;
+ if (get_user(fourth.__pad, (void __user * __user *) ptr))
+ return -EFAULT;
+ return sys_semctl (first, second, third, fourth);
+ }
+
+ case MSGSND:
+ return sys_msgsnd (first, (struct msgbuf __user *) ptr,
+ second, third);
+ case MSGRCV:
+ switch (version) {
+ case 0: {
+ struct ipc_kludge tmp;
+ if (!ptr)
+ return -EINVAL;
+
+ if (copy_from_user(&tmp,
+ (struct ipc_kludge __user *) ptr,
+ sizeof (tmp)))
+ return -EFAULT;
+ return sys_msgrcv (first, tmp.msgp, second,
+ tmp.msgtyp, third);
+ }
+ default:
+ return sys_msgrcv (first,
+ (struct msgbuf __user *) ptr,
+ second, fifth, third);
+ }
+ case MSGGET:
+ return sys_msgget ((key_t) first, second);
+ case MSGCTL:
+ return sys_msgctl (first, second,
+ (struct msqid_ds __user *) ptr);
+ case SHMAT: {
+ ulong raddr;
+
+ if ((ret = verify_area(VERIFY_WRITE, (ulong __user *) third,
+ sizeof(ulong))))
+ return ret;
+ ret = do_shmat (first, (char __user *) ptr, second, &raddr);
+ if (ret)
+ return ret;
+ return put_user (raddr, (ulong __user *) third);
+ }
+ case SHMDT:
+ return sys_shmdt ((char __user *)ptr);
+ case SHMGET:
+ return sys_shmget (first, second, third);
+ case SHMCTL:
+ return sys_shmctl (first, second,
+ (struct shmid_ds __user *) ptr);
+ default:
+ return -ENOSYS;
+ }
+}
+
+asmlinkage int sys_uname(struct old_utsname * name)
+{
+ int err;
+ if (!name)
+ return -EFAULT;
+ down_read(&uts_sem);
+ err=copy_to_user(name, &system_utsname, sizeof (*name));
+ up_read(&uts_sem);
+ return err?-EFAULT:0;
+}
+
+asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
+{
+ /* This should flush more selectivly ... */
+ _flush_cache_all();
+ return 0;
+}
+
+asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
+{
+ /* Not implemented yet. */
+ return -ENOSYS;
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/time.c
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ * Taken from i386 version.
+ * Copyright (C) 1991, 1992, 1995 Linus Torvalds
+ * Copyright (C) 1996, 1997, 1998 Ralf Baechle
+ *
+ * This file contains the time handling details for PC-style clocks as
+ * found in some MIPS systems.
+ *
+ * Some code taken from sh version.
+ * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
+ * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
+ */
+
+#undef DEBUG_TIMER
+
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/profile.h>
+
+#include <asm/io.h>
+#include <asm/m32r.h>
+
+#include <asm/hw_irq.h>
+
+#ifdef CONFIG_SMP
+extern void send_IPI_allbutself(int, int);
+extern void smp_local_timer_interrupt(struct pt_regs *);
+#endif
+
+u64 jiffies_64 = INITIAL_JIFFIES;
+
+EXPORT_SYMBOL(jiffies_64);
+
+extern unsigned long wall_jiffies;
+#define TICK_SIZE (tick_nsec / 1000)
+
+/*
+ * Change this if you have some constant time drift
+ */
+
+/* This is for machines which generate the exact clock. */
+#define USECS_PER_JIFFY (1000000/HZ)
+
+static unsigned long latch;
+
+static unsigned long do_gettimeoffset(void)
+{
+ unsigned long elapsed_time = 0; /* [us] */
+
+#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
+ || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
+ || defined(CONFIG_CHIP_OPSP)
+#ifndef CONFIG_SMP
+
+ unsigned long count;
+
+ /* timer count may underflow right here */
+ count = inl(M32R_MFT2CUT_PORTL);
+
+ if (inl(M32R_ICU_CR18_PORTL) & 0x00000100) /* underflow check */
+ count = 0;
+
+ count = (latch - count) * TICK_SIZE;
+ elapsed_time = (count + latch / 2) / latch;
+ /* NOTE: LATCH is equal to the "interval" value (= reload count). */
+
+#else /* CONFIG_SMP */
+ unsigned long count;
+ static unsigned long p_jiffies = -1;
+ static unsigned long p_count = 0;
+
+ /* timer count may underflow right here */
+ count = inl(M32R_MFT2CUT_PORTL);
+
+ if (jiffies == p_jiffies && count > p_count)
+ count = 0;
+
+ p_jiffies = jiffies;
+ p_count = count;
+
+ count = (latch - count) * TICK_SIZE;
+ elapsed_time = (count + latch / 2) / latch;
+ /* NOTE: LATCH is equal to the "interval" value (= reload count). */
+#endif /* CONFIG_SMP */
+#elif defined(CONFIG_CHIP_M32310)
+#warning do_gettimeoffse not implemented
+#else
+#error no chip configuration
+#endif
+
+ return elapsed_time;
+}
+
+/*
+ * This version of gettimeofday has near microsecond resolution.
+ */
+void do_gettimeofday(struct timeval *tv)
+{
+ unsigned long seq;
+ unsigned long usec, sec;
+ unsigned long max_ntp_tick = tick_usec - tickadj;
+
+ do {
+ unsigned long lost;
+
+ seq = read_seqbegin(&xtime_lock);
+
+ usec = do_gettimeoffset();
+ lost = jiffies - wall_jiffies;
+
+ /*
+ * If time_adjust is negative then NTP is slowing the clock
+ * so make sure not to go into next possible interval.
+ * Better to lose some accuracy than have time go backwards..
+ */
+ if (unlikely(time_adjust < 0)) {
+ usec = min(usec, max_ntp_tick);
+ if (lost)
+ usec += lost * max_ntp_tick;
+ } else if (unlikely(lost))
+ usec += lost * tick_usec;
+
+ sec = xtime.tv_sec;
+ usec += (xtime.tv_nsec / 1000);
+ } while (read_seqretry(&xtime_lock, seq));
+
+ while (usec >= 1000000) {
+ usec -= 1000000;
+ sec++;
+ }
+
+ tv->tv_sec = sec;
+ tv->tv_usec = usec;
+}
+
+EXPORT_SYMBOL(do_gettimeofday);
+
+int do_settimeofday(struct timespec *tv)
+{
+ time_t wtm_sec, sec = tv->tv_sec;
+ long wtm_nsec, nsec = tv->tv_nsec;
+
+ if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
+ return -EINVAL;
+
+ write_seqlock_irq(&xtime_lock);
+ /*
+ * This is revolting. We need to set "xtime" correctly. However, the
+ * value in this location is the value at the most recent update of
+ * wall time. Discover what correction gettimeofday() would have
+ * made, and then undo it!
+ */
+ nsec -= do_gettimeoffset() * NSEC_PER_USEC;
+ nsec -= (jiffies - wall_jiffies) * TICK_NSEC;
+
+ wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
+ wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
+
+ set_normalized_timespec(&xtime, sec, nsec);
+ set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
+
+ time_adjust = 0; /* stop active adjtime() */
+ time_status |= STA_UNSYNC;
+ time_maxerror = NTP_PHASE_LIMIT;
+ time_esterror = NTP_PHASE_LIMIT;
+ write_sequnlock_irq(&xtime_lock);
+ clock_was_set();
+
+ return 0;
+}
+
+EXPORT_SYMBOL(do_settimeofday);
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be
+ * called 500 ms after the second nowtime has started, because when
+ * nowtime is written into the registers of the CMOS clock, it will
+ * jump to the next second precisely 500 ms later. Check the Motorola
+ * MC146818A or Dallas DS12887 data sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ * sets the minutes. Usually you won't notice until after reboot!
+ */
+static __inline__ int set_rtc_mmss(unsigned long nowtime)
+{
+ return 0;
+}
+
+/* last time the cmos clock got updated */
+static long last_rtc_update = 0;
+
+/*
+ * timer_interrupt() needs to keep up the real-time clock,
+ * as well as call the "do_timer()" routine every clocktick
+ */
+static __inline__ void do_timer_interrupt(int irq, void *dev_id,
+ struct pt_regs * regs)
+{
+ do_timer(regs);
+
+ /*
+ * If we have an externally synchronized Linux clock, then update
+ * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
+ * called as close as possible to 500 ms before the new second starts.
+ */
+ if ((time_status & STA_UNSYNC) == 0
+ && xtime.tv_sec > last_rtc_update + 660
+ && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned)TICK_SIZE) / 2
+ && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned)TICK_SIZE) / 2)
+ {
+ if (set_rtc_mmss(xtime.tv_sec) == 0)
+ last_rtc_update = xtime.tv_sec;
+ else /* do it again in 60 s */
+ last_rtc_update = xtime.tv_sec - 600;
+ }
+ /* As we return to user mode fire off the other CPU schedulers..
+ this is basically because we don't yet share IRQ's around.
+ This message is rigged to be safe on the 386 - basically it's
+ a hack, so don't look closely for now.. */
+
+#ifdef CONFIG_SMP
+ smp_local_timer_interrupt(regs);
+#endif
+}
+
+irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ write_seqlock(&xtime_lock);
+ do_timer_interrupt(irq, NULL, regs);
+ write_sequnlock(&xtime_lock);
+
+#ifndef CONFIG_SMP
+ profile_tick(CPU_PROFILING, regs);
+#endif
+
+ return IRQ_HANDLED;
+}
+
+struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE,
+ "MFT2", NULL, NULL };
+
+void __init time_init(void)
+{
+ unsigned int epoch, year, mon, day, hour, min, sec;
+
+ sec = min = hour = day = mon = year = 0;
+ epoch = 0;
+
+ year = 23;
+ mon = 4;
+ day = 17;
+
+ /* Attempt to guess the epoch. This is the same heuristic as in rtc.c
+ so no stupid things will happen to timekeeping. Who knows, maybe
+ Ultrix also uses 1952 as epoch ... */
+ if (year > 10 && year < 44)
+ epoch = 1980;
+ else if (year < 96)
+ epoch = 1952;
+ year += epoch;
+
+ xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
+ xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
+ wall_to_monotonic.tv_sec = -xtime.tv_sec;
+ wall_to_monotonic.tv_nsec = -xtime.tv_nsec;
+
+#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
+ || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
+ || defined(CONFIG_CHIP_OPSP)
+
+ /* M32102 MFT setup */
+ setup_irq(M32R_IRQ_MFT2, &irq0);
+ {
+ unsigned long bus_clock;
+ unsigned short divide;
+
+ bus_clock = boot_cpu_data.bus_clock;
+ divide = boot_cpu_data.timer_divide;
+ latch = (bus_clock/divide + HZ / 2) / HZ;
+
+ printk("Timer start : latch = %ld\n", latch);
+
+ outl((M32R_MFTMOD_CC_MASK | M32R_MFTMOD_TCCR \
+ |M32R_MFTMOD_CSSEL011), M32R_MFT2MOD_PORTL);
+ outl(latch, M32R_MFT2RLD_PORTL);
+ outl(latch, M32R_MFT2CUT_PORTL);
+ outl(0, M32R_MFT2CMPRLD_PORTL);
+ outl((M32R_MFTCR_MFT2MSK|M32R_MFTCR_MFT2EN), M32R_MFTCR_PORTL);
+ }
+
+#elif defined(CONFIG_CHIP_M32310)
+#warning time_init not implemented
+#else
+#error no chip configuration
+#endif
+}
+
+/*
+ * Scheduler clock - returns current time in nanosec units.
+ */
+unsigned long long sched_clock(void)
+{
+ return (unsigned long long)jiffies * (1000000000 / HZ);
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/kernel/traps.c
+ *
+ * Copyright (C) 2001, 2002 Hirokazu Takata, Hiroyuki Kondo,
+ * Hitoshi Yamamoto
+ */
+
+/* $Id$ */
+
+/*
+ * 'traps.c' handles hardware traps and faults after we have saved some
+ * state in 'entry.S'.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/kallsyms.h>
+#include <linux/stddef.h>
+#include <linux/ptrace.h>
+#include <linux/mm.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/atomic.h>
+
+#include <asm/smp.h>
+
+#include <linux/module.h>
+
+asmlinkage void alignment_check(void);
+asmlinkage void ei_handler(void);
+asmlinkage void rie_handler(void);
+asmlinkage void debug_trap(void);
+asmlinkage void cache_flushing_handler(void);
+
+#ifdef CONFIG_SMP
+extern void smp_reschedule_interrupt(void);
+extern void smp_invalidate_interrupt(void);
+extern void smp_call_function_interrupt(void);
+extern void smp_ipi_timer_interrupt(void);
+extern void smp_flush_cache_all_interrupt(void);
+
+/*
+ * for Boot AP function
+ */
+asm (
+ " .section .eit_vector4,\"ax\" \n"
+ " .global _AP_RE \n"
+ " .global startup_AP \n"
+ "_AP_RE: \n"
+ " .fill 32, 4, 0 \n"
+ "_AP_EI: bra startup_AP \n"
+ " .previous \n"
+);
+#endif /* CONFIG_SMP */
+
+extern unsigned long eit_vector[];
+#define BRA_INSN(func, entry) \
+ ((unsigned long)func - (unsigned long)eit_vector - entry*4)/4 \
+ + 0xff000000UL
+
+void set_eit_vector_entries(void)
+{
+ extern void default_eit_handler(void);
+ extern void system_call(void);
+ extern void pie_handler(void);
+ extern void ace_handler(void);
+ extern void tme_handler(void);
+ extern void _flush_cache_copyback_all(void);
+
+ eit_vector[0] = 0xd0c00001; /* seth r0, 0x01 */
+ eit_vector[1] = BRA_INSN(default_eit_handler, 1);
+ eit_vector[4] = 0xd0c00010; /* seth r0, 0x10 */
+ eit_vector[5] = BRA_INSN(default_eit_handler, 5);
+ eit_vector[8] = BRA_INSN(rie_handler, 8);
+ eit_vector[12] = BRA_INSN(alignment_check, 12);
+ eit_vector[16] = 0xff000000UL;
+ eit_vector[17] = BRA_INSN(debug_trap, 17);
+ eit_vector[18] = BRA_INSN(system_call, 18);
+ eit_vector[19] = 0xff000000UL;
+ eit_vector[20] = 0xff000000UL;
+ eit_vector[21] = 0xff000000UL;
+ eit_vector[22] = 0xff000000UL;
+ eit_vector[23] = 0xff000000UL;
+ eit_vector[24] = 0xff000000UL;
+ eit_vector[25] = 0xff000000UL;
+ eit_vector[26] = 0xff000000UL;
+ eit_vector[27] = 0xff000000UL;
+ eit_vector[28] = BRA_INSN(cache_flushing_handler, 28);
+ eit_vector[29] = 0xff000000UL;
+ eit_vector[30] = 0xff000000UL;
+ eit_vector[31] = 0xff000000UL;
+ eit_vector[32] = BRA_INSN(ei_handler, 32);
+ eit_vector[64] = BRA_INSN(pie_handler, 64);
+ eit_vector[68] = BRA_INSN(ace_handler, 68);
+ eit_vector[72] = BRA_INSN(tme_handler, 72);
+#ifdef CONFIG_SMP
+ eit_vector[184] = (unsigned long)smp_reschedule_interrupt;
+ eit_vector[185] = (unsigned long)smp_invalidate_interrupt;
+ eit_vector[186] = (unsigned long)smp_call_function_interrupt;
+ eit_vector[187] = (unsigned long)smp_ipi_timer_interrupt;
+ eit_vector[188] = (unsigned long)smp_flush_cache_all_interrupt;
+ eit_vector[189] = 0;
+ eit_vector[190] = 0;
+ eit_vector[191] = 0;
+#endif
+ _flush_cache_copyback_all();
+}
+
+void __init trap_init(void)
+{
+ set_eit_vector_entries();
+
+ /*
+ * Should be a barrier for any external CPU state.
+ */
+ cpu_init();
+}
+
+int kstack_depth_to_print = 24;
+
+void show_trace(struct task_struct *task, unsigned long *stack)
+{
+ unsigned long addr;
+
+ if (!stack)
+ stack = (unsigned long*)&stack;
+
+ printk("Call Trace: ");
+ while (!kstack_end(stack)) {
+ addr = *stack++;
+ if (__kernel_text_address(addr)) {
+ printk("[<%08lx>] ", addr);
+ print_symbol("%s\n", addr);
+ }
+ }
+ printk("\n");
+}
+
+void show_stack(struct task_struct *task, unsigned long *sp)
+{
+ unsigned long *stack;
+ int i;
+
+ /*
+ * debugging aid: "show_stack(NULL);" prints the
+ * back trace for this cpu.
+ */
+
+ if(sp==NULL) {
+ if (task)
+ sp = (unsigned long *)task->thread.sp;
+ else
+ sp=(unsigned long*)&sp;
+ }
+
+ stack = sp;
+ for(i=0; i < kstack_depth_to_print; i++) {
+ if (kstack_end(stack))
+ break;
+ if (i && ((i % 4) == 0))
+ printk("\n ");
+ printk("%08lx ", *stack++);
+ }
+ printk("\n");
+ show_trace(task, sp);
+}
+
+void dump_stack(void)
+{
+ unsigned long stack;
+
+ show_trace(current, &stack);
+}
+
+EXPORT_SYMBOL(dump_stack);
+
+static void show_registers(struct pt_regs *regs)
+{
+ int i = 0;
+ int in_kernel = 1;
+ unsigned long sp;
+
+ printk("CPU: %d\n", smp_processor_id());
+ show_regs(regs);
+
+ sp = (unsigned long) (1+regs);
+ if (user_mode(regs)) {
+ in_kernel = 0;
+ sp = regs->spu;
+ printk("SPU: %08lx\n", sp);
+ } else {
+ printk("SPI: %08lx\n", sp);
+ }
+ printk("Process %s (pid: %d, process nr: %d, stackpage=%08lx)",
+ current->comm, current->pid, 0xffff & i, 4096+(unsigned long)current);
+
+ /*
+ * When in-kernel, we also print out the stack and code at the
+ * time of the fault..
+ */
+ if (in_kernel) {
+ printk("\nStack: ");
+ show_stack(current, (unsigned long*) sp);
+
+ printk("\nCode: ");
+ if (regs->bpc < PAGE_OFFSET)
+ goto bad;
+
+ for(i=0;i<20;i++) {
+ unsigned char c;
+ if (__get_user(c, &((unsigned char*)regs->bpc)[i])) {
+bad:
+ printk(" Bad PC value.");
+ break;
+ }
+ printk("%02x ", c);
+ }
+ }
+ printk("\n");
+}
+
+spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
+
+void die(const char * str, struct pt_regs * regs, long err)
+{
+ console_verbose();
+ spin_lock_irq(&die_lock);
+ bust_spinlocks(1);
+ printk("%s: %04lx\n", str, err & 0xffff);
+ show_registers(regs);
+ bust_spinlocks(0);
+ spin_unlock_irq(&die_lock);
+ do_exit(SIGSEGV);
+}
+
+static __inline__ void die_if_kernel(const char * str,
+ struct pt_regs * regs, long err)
+{
+ if (!user_mode(regs))
+ die(str, regs, err);
+}
+
+static __inline__ void do_trap(int trapnr, int signr, const char * str,
+ struct pt_regs * regs, long error_code, siginfo_t *info)
+{
+ if (user_mode(regs)) {
+ /* trap_signal */
+ struct task_struct *tsk = current;
+ tsk->thread.error_code = error_code;
+ tsk->thread.trap_no = trapnr;
+ if (info)
+ force_sig_info(signr, info, tsk);
+ else
+ force_sig(signr, tsk);
+ return;
+ } else {
+ /* kernel_trap */
+ if (!fixup_exception(regs))
+ die(str, regs, error_code);
+ return;
+ }
+}
+
+#define DO_ERROR(trapnr, signr, str, name) \
+asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
+{ \
+ do_trap(trapnr, signr, 0, regs, error_code, NULL); \
+}
+
+#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
+asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
+{ \
+ siginfo_t info; \
+ info.si_signo = signr; \
+ info.si_errno = 0; \
+ info.si_code = sicode; \
+ info.si_addr = (void __user *)siaddr; \
+ do_trap(trapnr, signr, str, regs, error_code, &info); \
+}
+
+DO_ERROR( 1, SIGTRAP, "debug trap", debug_trap)
+DO_ERROR_INFO(0x20, SIGILL, "reserved instruction ", rie_handler, ILL_ILLOPC, regs->bpc)
+DO_ERROR_INFO(0x100, SIGILL, "privilege instruction", pie_handler, ILL_PRVOPC, regs->bpc)
+
+extern int handle_unaligned_access(unsigned long, struct pt_regs *);
+
+/* This code taken from arch/sh/kernel/traps.c */
+asmlinkage void do_alignment_check(struct pt_regs *regs, long error_code)
+{
+ mm_segment_t oldfs;
+ unsigned long insn;
+ int tmp;
+
+ oldfs = get_fs();
+
+ if (user_mode(regs)) {
+ local_irq_enable();
+ current->thread.error_code = error_code;
+ current->thread.trap_no = 0x17;
+
+ set_fs(USER_DS);
+ if (copy_from_user(&insn, (void *)regs->bpc, 4)) {
+ set_fs(oldfs);
+ goto uspace_segv;
+ }
+ tmp = handle_unaligned_access(insn, regs);
+ set_fs(oldfs);
+
+ if (!tmp)
+ return;
+
+ uspace_segv:
+ printk(KERN_NOTICE "Killing process \"%s\" due to unaligned "
+ "access\n", current->comm);
+ force_sig(SIGSEGV, current);
+ } else {
+ set_fs(KERNEL_DS);
+ if (copy_from_user(&insn, (void *)regs->bpc, 4)) {
+ set_fs(oldfs);
+ die("insn faulting in do_address_error", regs, 0);
+ }
+ handle_unaligned_access(insn, regs);
+ set_fs(oldfs);
+ }
+}
+
--- /dev/null
+/* ld script to make M32R Linux kernel
+ */
+
+#include <linux/config.h>
+#include <asm-generic/vmlinux.lds.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+
+OUTPUT_ARCH(m32r)
+ENTRY(startup_32)
+#if defined(__LITTLE_ENDIAN__)
+ jiffies = jiffies_64;
+#else
+ jiffies = jiffies_64 + 4;
+#endif
+SECTIONS
+{
+ . = CONFIG_MEMORY_START + __PAGE_OFFSET;
+ eit_vector = .;
+
+ . = . + 0x1000;
+ .empty_zero_page : { *(.empty_zero_page) } = 0
+
+ /* read-only */
+ _text = .; /* Text and read-only data */
+ .boot : { *(.boot) } = 0
+ .text : {
+ *(.text)
+ SCHED_TEXT
+ LOCK_TEXT
+ *(.fixup)
+ *(.gnu.warning)
+ } = 0x9090
+#ifdef CONFIG_SMP
+ . = ALIGN(65536);
+ .eit_vector4 : { *(.eit_vector4) }
+#endif
+ _etext = .; /* End of text section */
+
+ . = ALIGN(16); /* Exception table */
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ RODATA
+
+ /* writeable */
+ .data : { /* Data */
+ *(.spu)
+ *(.spi)
+ *(.data)
+ CONSTRUCTORS
+ }
+
+ . = ALIGN(4096);
+ __nosave_begin = .;
+ .data_nosave : { *(.data.nosave) }
+ . = ALIGN(4096);
+ __nosave_end = .;
+
+ . = ALIGN(4096);
+ .data.page_aligned : { *(.data.idt) }
+
+ . = ALIGN(32);
+ .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
+ _edata = .; /* End of data section */
+
+ . = ALIGN(8192); /* init_task */
+ .data.init_task : { *(.data.init_task) }
+
+ /* will be freed after init */
+ . = ALIGN(4096); /* Init code and data */
+ __init_begin = .;
+ .init.text : {
+ _sinittext = .;
+ *(.init.text)
+ _einittext = .;
+ }
+ .init.data : { *(.init.data) }
+ . = ALIGN(16);
+ __setup_start = .;
+ .init.setup : { *(.init.setup) }
+ __setup_end = .;
+ __initcall_start = .;
+ .initcall.init : {
+ *(.initcall1.init)
+ *(.initcall2.init)
+ *(.initcall3.init)
+ *(.initcall4.init)
+ *(.initcall5.init)
+ *(.initcall6.init)
+ *(.initcall7.init)
+ }
+ __initcall_end = .;
+ __con_initcall_start = .;
+ .con_initcall.init : { *(.con_initcall.init) }
+ __con_initcall_end = .;
+ SECURITY_INIT
+ . = ALIGN(4);
+ __alt_instructions = .;
+ .altinstructions : { *(.altinstructions) }
+ __alt_instructions_end = .;
+ .altinstr_replacement : { *(.altinstr_replacement) }
+ /* .exit.text is discard at runtime, not link time, to deal with references
+ from .altinstructions and .eh_frame */
+ .exit.text : { *(.exit.text) }
+ .exit.data : { *(.exit.data) }
+ . = ALIGN(4096);
+ __initramfs_start = .;
+ .init.ramfs : { *(.init.ramfs) }
+ __initramfs_end = .;
+ . = ALIGN(32);
+ __per_cpu_start = .;
+ .data.percpu : { *(.data.percpu) }
+ __per_cpu_end = .;
+ . = ALIGN(4096);
+ __init_end = .;
+ /* freed after init ends here */
+
+ __bss_start = .; /* BSS */
+ .bss : { *(.bss) }
+ . = ALIGN(4);
+ __bss_stop = .;
+
+ _end = . ;
+
+ /* Sections to be discarded */
+ /DISCARD/ : {
+ *(.exit.text)
+ *(.exit.data)
+ *(.exitcall.exit)
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+}
--- /dev/null
+#
+# Makefile for M32R-specific library files..
+#
+
+lib-y := checksum.o ashxdi3.o memset.o memcpy.o getuser.o \
+ putuser.o delay.o strlen.o usercopy.o csum_partial_copy.o
+
--- /dev/null
+/*
+ * linux/arch/m32r/lib/ashxdi3.S
+ *
+ * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
+ *
+ */
+/* $Id$ */
+
+#include <linux/config.h>
+
+;
+; input (r0,r1) src
+; input r2 shift val
+; r3 scratch
+; output (r0,r1)
+;
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+#ifndef __LITTLE_ENDIAN__
+
+ .text
+ .align 4
+ .globl __ashrdi3
+__ashrdi3:
+ cmpz r2 || ldi r3, #32
+ jc r14 || cmpu r2, r3
+ bc 1f
+ ; case 32 =< shift
+ mv r1, r0 || srai r0, #31
+ addi r2, #-32
+ sra r1, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r0 || srl r1, r2
+ sra r0, r2 || neg r2, r2
+ sll r3, r2
+ or r1, r3 || jmp r14
+
+ .align 4
+ .globl __ashldi3
+ .globl __lshldi3
+__ashldi3:
+__lshldi3:
+ cmpz r2 || ldi r3, #32
+ jc r14 || cmpu r2, r3
+ bc 1f
+ ; case 32 =< shift
+ mv r0, r1 || addi r2, #-32
+ sll r0, r2 || ldi r1, #0
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r1 || sll r0, r2
+ sll r1, r2 || neg r2, r2
+ srl r3, r2
+ or r0, r3 || jmp r14
+
+ .align 4
+ .globl __lshrdi3
+__lshrdi3:
+ cmpz r2 || ldi r3, #32
+ jc r14 || cmpu r2, r3
+ bc 1f
+ ; case 32 =< shift
+ mv r1, r0 || addi r2, #-32
+ ldi r0, #0 || srl r1, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r0 || srl r1, r2
+ srl r0, r2 || neg r2, r2
+ sll r3, r2
+ or r1, r3 || jmp r14
+
+#else /* LITTLE_ENDIAN */
+
+ .text
+ .align 4
+ .globl __ashrdi3
+__ashrdi3:
+ cmpz r2 || ldi r3, #32
+ jc r14 || cmpu r2, r3
+ bc 1f
+ ; case 32 =< shift
+ mv r0, r1 || srai r1, #31
+ addi r2, #-32
+ sra r0, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r1 || srl r0, r2
+ sra r1, r2 || neg r2, r2
+ sll r3, r2
+ or r0, r3 || jmp r14
+
+ .align 4
+ .globl __ashldi3
+ .globl __lshldi3
+__ashldi3:
+__lshldi3:
+ cmpz r2 || ldi r3, #32
+ jc r14 || cmpu r2, r3
+ bc 1f
+ ; case 32 =< shift
+ mv r1, r0 || addi r2, #-32
+ sll r1, r2 || ldi r0, #0
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r0 || sll r1, r2
+ sll r0, r2 || neg r2, r2
+ srl r3, r2
+ or r1, r3 || jmp r14
+
+ .align 4
+ .globl __lshrdi3
+__lshrdi3:
+ cmpz r2 || ldi r3, #32
+ jc r14 || cmpu r2, r3
+ bc 1f
+ ; case 32 =< shift
+ mv r0, r1 || addi r2, #-32
+ ldi r1, #0 || srl r0, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r1 || srl r0, r2
+ srl r1, r2 || neg r2, r2
+ sll r3, r2
+ or r0, r3 || jmp r14
+
+#endif
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+#ifndef __LITTLE_ENDIAN__
+
+ .text
+ .align 4
+ .globl __ashrdi3
+__ashrdi3:
+ beqz r2, 2f
+ cmpui r2, #32
+ bc 1f
+ ; case 32 =< shift
+ mv r1, r0
+ srai r0, #31
+ addi r2, #-32
+ sra r1, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r0
+ srl r1, r2
+ sra r0, r2
+ neg r2, r2
+ sll r3, r2
+ or r1, r3
+ .fillinsn
+2:
+ jmp r14
+
+ .align 4
+ .globl __ashldi3
+ .globl __lshldi3
+__ashldi3:
+__lshldi3:
+ beqz r2, 2f
+ cmpui r2, #32
+ bc 1f
+ ; case 32 =< shift
+ mv r0, r1
+ addi r2, #-32
+ sll r0, r2
+ ldi r1, #0
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r1
+ sll r0, r2
+ sll r1, r2
+ neg r2, r2
+ srl r3, r2
+ or r0, r3
+ .fillinsn
+2:
+ jmp r14
+
+ .align 4
+ .globl __lshrdi3
+__lshrdi3:
+ beqz r2, 2f
+ cmpui r2, #32
+ bc 1f
+ ; case 32 =< shift
+ mv r1, r0
+ ldi r0, #0
+ addi r2, #-32
+ srl r1, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r0
+ srl r1, r2
+ srl r0, r2
+ neg r2, r2
+ sll r3, r2
+ or r1, r3
+ .fillinsn
+2:
+ jmp r14
+
+#else
+
+ .text
+ .align 4
+ .globl __ashrdi3
+__ashrdi3:
+ beqz r2, 2f
+ cmpui r2, #32
+ bc 1f
+ ; case 32 =< shift
+ mv r0, r1
+ srai r1, #31
+ addi r2, #-32
+ sra r0, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r1
+ srl r0, r2
+ sra r1, r2
+ neg r2, r2
+ sll r3, r2
+ or r0, r3
+ .fillinsn
+2:
+ jmp r14
+
+ .align 4
+ .globl __ashldi3
+ .globl __lshldi3
+__ashldi3:
+__lshldi3:
+ beqz r2, 2f
+ cmpui r2, #32
+ bc 1f
+ ; case 32 =< shift
+ mv r1, r0
+ addi r2, #-32
+ sll r1, r2
+ ldi r0, #0
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r0
+ sll r1, r2
+ sll r0, r2
+ neg r2, r2
+ srl r3, r2
+ or r1, r3
+ .fillinsn
+2:
+ jmp r14
+
+ .align 4
+ .globl __lshrdi3
+__lshrdi3:
+ beqz r2, 2f
+ cmpui r2, #32
+ bc 1f
+ ; case 32 =< shift
+ mv r0, r1
+ ldi r1, #0
+ addi r2, #-32
+ srl r0, r2
+ jmp r14
+ .fillinsn
+1: ; case shift <32
+ mv r3, r1
+ srl r0, r2
+ srl r1, r2
+ neg r2, r2
+ sll r3, r2
+ or r0, r3
+ .fillinsn
+2:
+ jmp r14
+
+#endif
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .end
+
--- /dev/null
+/*
+ * INET An implementation of the TCP/IP protocol suite for the LINUX
+ * operating system. INET is implemented using the BSD Socket
+ * interface as the means of communication with the user level.
+ *
+ * IP/TCP/UDP checksumming routines
+ *
+ * Authors: Jorge Cwik, <jorge@laser.satlink.net>
+ * Arnt Gulbrandsen, <agulbra@nvg.unit.no>
+ * Tom May, <ftom@netcom.com>
+ * Pentium Pro/II routines:
+ * Alexander Kjeldaas <astor@guardian.no>
+ * Finn Arne Gangstad <finnag@guardian.no>
+ * Lots of code moved from tcp.c and ip.c; see those files
+ * for more names.
+ *
+ * Changes: Ingo Molnar, converted csum_partial_copy() to 2.1 exception
+ * handling.
+ * Andi Kleen, add zeroing on error
+ * converted to pure assembler
+ * Hirokazu Takata,Hiroyuki Kondo rewrite for the m32r architecture.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+/* $Id$ */
+
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+
+/*
+ * computes a partial checksum, e.g. for TCP/UDP fragments
+ */
+
+/*
+unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum)
+ */
+
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ /*
+ * Experiments with Ethernet and SLIP connections show that buff
+ * is aligned on either a 2-byte or 4-byte boundary. We get at
+ * least a twofold speedup on 486 and Pentium if it is 4-byte aligned.
+ * Fortunately, it is easy to convert 2-byte alignment to 4-byte
+ * alignment for the unrolled loop.
+ */
+
+ .text
+ENTRY(csum_partial)
+ ; Function args
+ ; r0: unsigned char *buff
+ ; r1: int len
+ ; r2: unsigned int sum
+
+ push r2 || ldi r2, #0
+ and3 r7, r0, #1 ; Check alignment.
+ beqz r7, 1f ; Jump if alignment is ok.
+ ; 1-byte mis aligned
+ ldub r4, @r0 || addi r0, #1
+ ; clear c-bit || Alignment uses up bytes.
+ cmp r0, r0 || addi r1, #-1
+ ldi r3, #0 || addx r2, r4
+ addx r2, r3
+ .fillinsn
+1:
+ and3 r4, r0, #2 ; Check alignment.
+ beqz r4, 2f ; Jump if alignment is ok.
+ ; clear c-bit || Alignment uses up two bytes.
+ cmp r0, r0 || addi r1, #-2
+ bgtz r1, 1f ; Jump if we had at least two bytes.
+ bra 4f || addi r1, #2
+ .fillinsn ; len(r1) was < 2. Deal with it.
+1:
+ ; 2-byte aligned
+ lduh r4, @r0 || ldi r3, #0
+ addx r2, r4 || addi r0, #2
+ addx r2, r3
+ .fillinsn
+2:
+ ; 4-byte aligned
+ cmp r0, r0 ; clear c-bit
+ srl3 r6, r1, #5
+ beqz r6, 2f
+ .fillinsn
+
+1: ld r3, @r0+
+ ld r4, @r0+ ; +4
+ ld r5, @r0+ ; +8
+ ld r3, @r0+ || addx r2, r3 ; +12
+ ld r4, @r0+ || addx r2, r4 ; +16
+ ld r5, @r0+ || addx r2, r5 ; +20
+ ld r3, @r0+ || addx r2, r3 ; +24
+ ld r4, @r0+ || addx r2, r4 ; +28
+ addx r2, r5 || addi r6, #-1
+ addx r2, r3
+ addx r2, r4
+ bnez r6, 1b
+
+ addx r2, r6 ; r6=0
+ cmp r0, r0 ; This clears c-bit
+ .fillinsn
+2: and3 r6, r1, #0x1c ; withdraw len
+ beqz r6, 4f
+ srli r6, #2
+ .fillinsn
+
+3: ld r4, @r0+ || addi r6, #-1
+ addx r2, r4
+ bnez r6, 3b
+
+ addx r2, r6 ; r6=0
+ cmp r0, r0 ; This clears c-bit
+ .fillinsn
+4: and3 r1, r1, #3
+ beqz r1, 7f ; if len == 0 goto end
+ and3 r6, r1, #2
+ beqz r6, 5f ; if len < 2 goto 5f(1byte)
+ lduh r4, @r0 || addi r0, #2
+ addi r1, #-2 || slli r4, #16
+ addx r2, r4
+ beqz r1, 6f
+ .fillinsn
+5: ldub r4, @r0 || ldi r1, #0
+#ifndef __LITTLE_ENDIAN__
+ slli r4, #8
+#endif
+ addx r2, r4
+ .fillinsn
+6: addx r2, r1
+ .fillinsn
+7:
+ and3 r0, r2, #0xffff
+ srli r2, #16
+ add r0, r2
+ srl3 r2, r0, #16
+ beqz r2, 1f
+ addi r0, #1
+ and3 r0, r0, #0xffff
+ .fillinsn
+1:
+ beqz r7, 1f ; swap the upper byte for the lower
+ and3 r2, r0, #0xff
+ srl3 r0, r0, #8
+ slli r2, #8
+ or r0, r2
+ .fillinsn
+1:
+ pop r2 || cmp r0, r0
+ addx r0, r2 || ldi r2, #0
+ addx r0, r2
+ jmp r14
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ /*
+ * Experiments with Ethernet and SLIP connections show that buff
+ * is aligned on either a 2-byte or 4-byte boundary. We get at
+ * least a twofold speedup on 486 and Pentium if it is 4-byte aligned.
+ * Fortunately, it is easy to convert 2-byte alignment to 4-byte
+ * alignment for the unrolled loop.
+ */
+
+ .text
+ENTRY(csum_partial)
+ ; Function args
+ ; r0: unsigned char *buff
+ ; r1: int len
+ ; r2: unsigned int sum
+
+ push r2
+ ldi r2, #0
+ and3 r7, r0, #1 ; Check alignment.
+ beqz r7, 1f ; Jump if alignment is ok.
+ ; 1-byte mis aligned
+ ldub r4, @r0
+ addi r0, #1
+ addi r1, #-1 ; Alignment uses up bytes.
+ cmp r0, r0 ; clear c-bit
+ ldi r3, #0
+ addx r2, r4
+ addx r2, r3
+ .fillinsn
+1:
+ and3 r4, r0, #2 ; Check alignment.
+ beqz r4, 2f ; Jump if alignment is ok.
+ addi r1, #-2 ; Alignment uses up two bytes.
+ cmp r0, r0 ; clear c-bit
+ bgtz r1, 1f ; Jump if we had at least two bytes.
+ addi r1, #2 ; len(r1) was < 2. Deal with it.
+ bra 4f
+ .fillinsn
+1:
+ ; 2-byte aligned
+ lduh r4, @r0
+ addi r0, #2
+ ldi r3, #0
+ addx r2, r4
+ addx r2, r3
+ .fillinsn
+2:
+ ; 4-byte aligned
+ cmp r0, r0 ; clear c-bit
+ srl3 r6, r1, #5
+ beqz r6, 2f
+ .fillinsn
+
+1: ld r3, @r0+
+ ld r4, @r0+ ; +4
+ ld r5, @r0+ ; +8
+ addx r2, r3
+ addx r2, r4
+ addx r2, r5
+ ld r3, @r0+ ; +12
+ ld r4, @r0+ ; +16
+ ld r5, @r0+ ; +20
+ addx r2, r3
+ addx r2, r4
+ addx r2, r5
+ ld r3, @r0+ ; +24
+ ld r4, @r0+ ; +28
+ addi r6, #-1
+ addx r2, r3
+ addx r2, r4
+ bnez r6, 1b
+ addx r2, r6 ; r6=0
+ cmp r0, r0 ; This clears c-bit
+ .fillinsn
+
+2: and3 r6, r1, #0x1c ; withdraw len
+ beqz r6, 4f
+ srli r6, #2
+ .fillinsn
+
+3: ld r4, @r0+
+ addi r6, #-1
+ addx r2, r4
+ bnez r6, 3b
+ addx r2, r6 ; r6=0
+ cmp r0, r0 ; This clears c-bit
+ .fillinsn
+
+4: and3 r1, r1, #3
+ beqz r1, 7f ; if len == 0 goto end
+ and3 r6, r1, #2
+ beqz r6, 5f ; if len < 2 goto 5f(1byte)
+
+ lduh r4, @r0
+ addi r0, #2
+ addi r1, #-2
+ slli r4, #16
+ addx r2, r4
+ beqz r1, 6f
+ .fillinsn
+5: ldub r4, @r0
+#ifndef __LITTLE_ENDIAN__
+ slli r4, #8
+#endif
+ addx r2, r4
+ .fillinsn
+6: ldi r5, #0
+ addx r2, r5
+ .fillinsn
+7:
+ and3 r0, r2, #0xffff
+ srli r2, #16
+ add r0, r2
+ srl3 r2, r0, #16
+ beqz r2, 1f
+ addi r0, #1
+ and3 r0, r0, #0xffff
+ .fillinsn
+1:
+ beqz r7, 1f
+ mv r2, r0
+ srl3 r0, r2, #8
+ and3 r2, r2, #0xff
+ slli r2, #8
+ or r0, r2
+ .fillinsn
+1:
+ pop r2
+ cmp r0, r0
+ addx r0, r2
+ ldi r2, #0
+ addx r0, r2
+ jmp r14
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+/*
+unsigned int csum_partial_copy_generic (const char *src, char *dst,
+ int len, int sum, int *src_err_ptr, int *dst_err_ptr)
+ */
+
+/*
+ * Copy from ds while checksumming, otherwise like csum_partial
+ *
+ * The macros SRC and DST specify the type of access for the instruction.
+ * thus we can call a custom exception handler for all access types.
+ *
+ * FIXME: could someone double-check whether I haven't mixed up some SRC and
+ * DST definitions? It's damn hard to trigger all cases. I hope I got
+ * them all but there's no guarantee.
+ */
+
+ENTRY(csum_partial_copy_generic)
+ nop
+ nop
+ nop
+ nop
+ jmp r14
+ nop
+ nop
+ nop
+
--- /dev/null
+/*
+ * INET An implementation of the TCP/IP protocol suite for the LINUX
+ * operating system. INET is implemented using the BSD Socket
+ * interface as the means of communication with the user level.
+ *
+ * MIPS specific IP/TCP/UDP checksumming routines
+ *
+ * Authors: Ralf Baechle, <ralf@waldorf-gmbh.de>
+ * Lots of code moved from tcp.c and ip.c; see those files
+ * for more names.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+
+#include <net/checksum.h>
+#include <asm/byteorder.h>
+#include <asm/string.h>
+#include <asm/uaccess.h>
+
+/*
+ * Copy while checksumming, otherwise like csum_partial
+ */
+unsigned int csum_partial_copy_nocheck (const char *src, char *dst,
+ int len, unsigned int sum)
+{
+ sum = csum_partial(src, len, sum);
+ memcpy(dst, src, len);
+
+ return sum;
+}
+EXPORT_SYMBOL(csum_partial_copy_nocheck);
+
+/*
+ * Copy from userspace and compute checksum. If we catch an exception
+ * then zero the rest of the buffer.
+ */
+unsigned int csum_partial_copy_from_user (const char __user *src, char *dst,
+ int len, unsigned int sum,
+ int *err_ptr)
+{
+ int missing;
+
+ missing = copy_from_user(dst, src, len);
+ if (missing) {
+ memset(dst + len - missing, 0, missing);
+ *err_ptr = -EFAULT;
+ }
+
+ return csum_partial(dst, len-missing, sum);
+}
+EXPORT_SYMBOL(csum_partial_copy_from_user);
--- /dev/null
+/*
+ * linux/arch/m32r/lib/delay.c
+ *
+ * Copyright (c) 2002 Hitoshi Yamamoto, Hirokazu Takata
+ * Copyright (c) 2004 Hirokazu Takata
+ */
+
+/* $Id$ */
+
+#include <linux/config.h>
+#include <linux/param.h>
+#ifdef CONFIG_SMP
+#include <linux/sched.h>
+#include <asm/current.h>
+#include <asm/smp.h>
+#endif /* CONFIG_SMP */
+#include <asm/processor.h>
+
+void __delay(unsigned long loops)
+{
+#ifdef CONFIG_ISA_DUAL_ISSUE
+ __asm__ __volatile__ (
+ "beqz %0, 2f \n\t"
+ "addi %0, #-1 \n\t"
+
+ " .fillinsn \n\t"
+ "1: \n\t"
+ "cmpz %0 || addi %0, #-1 \n\t"
+ "bc 2f || cmpz %0 \n\t"
+ "bc 2f || addi %0, #-1 \n\t"
+ "cmpz %0 || addi %0, #-1 \n\t"
+ "bc 2f || cmpz %0 \n\t"
+ "bnc 1b || addi %0, #-1 \n\t"
+ " .fillinsn \n\t"
+ "2: \n\t"
+ : "+r" (loops)
+ : "r" (0)
+ : "cbit"
+ );
+#else
+ __asm__ __volatile__ (
+ "beqz %0, 2f \n\t"
+ " .fillinsn \n\t"
+ "1: \n\t"
+ "addi %0, #-1 \n\t"
+ "blez %0, 2f \n\t"
+ "addi %0, #-1 \n\t"
+ "blez %0, 2f \n\t"
+ "addi %0, #-1 \n\t"
+ "blez %0, 2f \n\t"
+ "addi %0, #-1 \n\t"
+ "bgtz %0, 1b \n\t"
+ " .fillinsn \n\t"
+ "2:i \n\t"
+ : "+r" (loops)
+ : "r" (0)
+ );
+#endif
+}
+
+void __const_udelay(unsigned long xloops)
+{
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ /*
+ * loops [1] = (xloops >> 32) [sec] * loops_per_jiffy [1/jiffy]
+ * * HZ [jiffy/sec]
+ * = (xloops >> 32) [sec] * (loops_per_jiffy * HZ) [1/sec]
+ * = (((xloops * loops_per_jiffy) >> 32) * HZ) [1]
+ *
+ * NOTE:
+ * - '[]' depicts variable's dimension in the above equation.
+ * - "rac" instruction rounds the accumulator in word size.
+ */
+ __asm__ __volatile__ (
+ "srli %0, #1 \n\t"
+ "mulwhi %0, %1 ; a0 \n\t"
+ "mulwu1 %0, %1 ; a1 \n\t"
+ "sadd ; a0 += (a1 >> 16) \n\t"
+ "rac a0, a0, #1 \n\t"
+ "mvfacmi %0, a0 \n\t"
+ : "+r" (xloops)
+ : "r" (current_cpu_data.loops_per_jiffy)
+ : "a0", "a1"
+ );
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ /*
+ * u64 ull;
+ * ull = (u64)xloops * (u64)current_cpu_data.loops_per_jiffy;
+ * xloops = (ull >> 32);
+ */
+ __asm__ __volatile__ (
+ "and3 r4, %0, #0xffff \n\t"
+ "and3 r5, %1, #0xffff \n\t"
+ "mul r4, r5 \n\t"
+ "srl3 r6, %0, #16 \n\t"
+ "srli r4, #16 \n\t"
+ "mul r5, r6 \n\t"
+ "add r4, r5 \n\t"
+ "and3 r5, %0, #0xffff \n\t"
+ "srl3 r6, %1, #16 \n\t"
+ "mul r5, r6 \n\t"
+ "add r4, r5 \n\t"
+ "srl3 r5, %0, #16 \n\t"
+ "srli r4, #16 \n\t"
+ "mul r5, r6 \n\t"
+ "add r4, r5 \n\t"
+ "mv %0, r4 \n\t"
+ : "+r" (xloops)
+ : "r" (current_cpu_data.loops_per_jiffy)
+ : "r4", "r5", "r6"
+ );
+#else
+#error unknown isa configuration
+#endif
+ __delay(xloops * HZ);
+}
+
+void __udelay(unsigned long usecs)
+{
+ __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
+}
+
+void __ndelay(unsigned long nsecs)
+{
+ __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
+}
--- /dev/null
+/*
+ * __get_user functions.
+ *
+ * (C) Copyright 2001 Hirokazu Takata
+ *
+ * These functions have a non-standard call interface
+ * to make them more efficient, especially as they
+ * return an error value in addition to the "real"
+ * return value.
+ */
+
+#include <linux/config.h>
+
+/*
+ * __get_user_X
+ *
+ * Inputs: r0 contains the address
+ *
+ * Outputs: r0 is error code (0 or -EFAULT)
+ * r1 contains zero-extended value
+ *
+ * These functions should not modify any other registers,
+ * as they get called from within inline assembly.
+ */
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ .text
+ .balign 4
+ .globl __get_user_1
+__get_user_1:
+1: ldub r1, @r0 || ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __get_user_2
+__get_user_2:
+2: lduh r1, @r0 || ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __get_user_4
+__get_user_4:
+3: ld r1, @r0 || ldi r0, #0
+ jmp r14
+
+bad_get_user:
+ ldi r1, #0 || ldi r0, #-14
+ jmp r14
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .text
+ .balign 4
+ .globl __get_user_1
+__get_user_1:
+1: ldub r1, @r0
+ ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __get_user_2
+__get_user_2:
+2: lduh r1, @r0
+ ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __get_user_4
+__get_user_4:
+3: ld r1, @r0
+ ldi r0, #0
+ jmp r14
+
+bad_get_user:
+ ldi r1, #0
+ ldi r0, #-14
+ jmp r14
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+.section __ex_table,"a"
+ .long 1b,bad_get_user
+ .long 2b,bad_get_user
+ .long 3b,bad_get_user
+.previous
+
+ .end
--- /dev/null
+/*
+ * linux/arch/m32r/lib/memcpy.S
+ *
+ * Copyright (C) 2001 Hiroyuki Kondo, and Hirokazu Takata
+ * Copyright (C) 2004 Hirokazu Takata
+ *
+ * void *memcopy(void *dst, const void *src, int n);
+ *
+ * dst: r0
+ * src: r1
+ * n : r2
+ */
+/* $Id$ */
+
+
+ .text
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ .text
+ENTRY(memcpy)
+memcopy:
+ mv r4, r0 || mv r7, r0
+ or r7, r1 || cmpz r2
+ jc r14 || cmpeq r0, r1 ; return if r2=0
+ jc r14 ; return if r0=r1
+
+ and3 r7, r7, #3
+ bnez r7, byte_copy
+ srl3 r3, r2, #2
+ and3 r2, r2, #3
+ beqz r3, byte_copy
+ addi r4, #-4
+word_copy:
+ ld r7, @r1+ || addi r3, #-1
+ st r7, @+r4 || cmpz r2
+ bnez r3, word_copy
+ addi r4, #4 || jc r14 ; return if r2=0
+#if defined(CONFIG_ISA_M32R2)
+byte_copy:
+ ldb r7, @r1 || addi r1, #1
+ addi r2, #-1 || stb r7, @r4+
+ bnez r2, byte_copy
+#elif defined(CONFIG_ISA_M32R)
+byte_copy:
+ ldb r7, @r1 || addi r1, #1
+ addi r2, #-1 || stb r7, @r4
+ addi r4, #1
+ bnez r2, byte_copy
+#else
+#error unknown isa configuration
+#endif
+end_memcopy:
+ jmp r14
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .text
+ENTRY(memcpy)
+memcopy:
+ mv r4, r0
+ mv r7, r0
+ or r7, r1
+ beq r0, r1, end_memcopy
+ beqz r2, end_memcopy
+
+ and3 r7, r7, #3
+ bnez r7, byte_copy
+ srl3 r3, r2, #2
+ and3 r2, r2, #3
+ beqz r3, byte_copy
+ addi r4, #-4
+word_copy:
+ ld r7, @r1+
+ addi r3, #-1
+ st r7, @+r4
+ bnez r3, word_copy
+ beqz r2, end_memcopy
+ addi r4, #4
+byte_copy:
+ ldb r7, @r1
+ addi r1, #1
+ addi r2, #-1
+ stb r7, @r4
+ addi r4, #1
+ bnez r2, byte_copy
+end_memcopy:
+ jmp r14
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .end
--- /dev/null
+/*
+ * linux/arch/m32r/lib/memset.S
+ *
+ * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
+ * Copyright (C) 2004 Hirokazu Takata
+ *
+ * void *memset(void *dst, int val, int len);
+ *
+ * dst: r0
+ * val: r1
+ * len: r2
+ * ret: r0
+ *
+ */
+/* $Id$ */
+
+#include <linux/config.h>
+
+ .text
+ .global memset
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ .align 4
+memset:
+ mv r4, r0 || cmpz r2
+ jc r14
+ cmpui r2, #16
+ bnc qword_align_check
+ cmpui r2, #4
+ bc byte_set
+word_align_check: /* len >= 4 */
+ and3 r3, r4, #3
+ beqz r3, word_set
+ addi r3, #-4
+ neg r3, r3 /* r3 = -(r3 - 4) */
+align_word:
+ stb r1, @r4 || addi r4, #1
+ addi r2, #-1 || addi r3, #-1
+ bnez r3, align_word
+ cmpui r2, #4
+ bc byte_set
+word_set:
+ and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
+ sll3 r3, r1, #8
+ or r1, r3 || addi r4, #-4
+ sll3 r3, r1, #16
+ or r1, r3 || addi r2, #-4
+word_set_loop:
+ st r1, @+r4 || addi r2, #-4
+ bgtz r2, word_set_loop
+ bnez r2, byte_set_wrap
+ st r1, @+r4
+ jmp r14
+
+qword_align_check: /* len >= 16 */
+ and3 r3, r4, #15
+ bnez r3, word_align_check
+qword_set:
+ and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
+ sll3 r3, r1, #8
+ or r1, r3 || addi r4, #-4
+ sll3 r3, r1, #16
+ or r1, r3 || ldi r5, #16
+qword_set_loop:
+ ld r3, @(4,r4) /* cache line allocate */
+ st r1, @+r4 || addi r2, #-16
+ st r1, @+r4 || cmpu r2, r5
+ st r1, @+r4
+ st r1, @+r4
+ bnc qword_set_loop || cmpz r2
+ jc r14
+word_set_wrap:
+ cmpui r2, #4
+ bc byte_set
+ addi r2, #-4
+ bra word_set_loop
+
+byte_set_wrap:
+ addi r2, #4
+ addi r4, #4 || cmpz r2
+ jc r14
+#if defined(CONFIG_ISA_M32R2)
+byte_set:
+ addi r2, #-1 || stb r1, @r4+
+ bnez r2, byte_set
+#elif defined(CONFIG_ISA_M32R)
+byte_set:
+ addi r2, #-1 || stb r1, @r4
+ addi r4, #1
+ bnez r2, byte_set
+#else
+#error unknown isa configuration
+#endif
+end_memset:
+ jmp r14
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .align 4
+memset:
+ mv r4, r0
+ beqz r2, end_memset
+ cmpui r2, #16
+ bnc qword_align_check
+ cmpui r2, #4
+ bc byte_set
+word_align_check: /* len >= 4 */
+ and3 r3, r4, #3
+ beqz r3, word_set
+ addi r3, #-4
+ neg r3, r3 /* r3 = -(r3 - 4) */
+align_word:
+ stb r1, @r4
+ addi r4, #1
+ addi r2, #-1
+ addi r3, #-1
+ bnez r3, align_word
+ cmpui r2, #4
+ bc byte_set
+word_set:
+ and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
+ sll3 r3, r1, #8
+ or r1, r3
+ sll3 r3, r1, #16
+ or r1, r3
+ addi r2, #-4
+ addi r4, #-4
+word_set_loop:
+ st r1, @+r4
+ addi r2, #-4
+ bgtz r2, word_set_loop
+ bnez r2, byte_set_wrap
+ st r1, @+r4
+ jmp r14
+
+qword_align_check: /* len >= 16 */
+ and3 r3, r4, #15
+ bnez r3, word_align_check
+qword_set:
+ and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
+ sll3 r3, r1, #8
+ or r1, r3
+ sll3 r3, r1, #16
+ or r1, r3
+ addi r4, #-4
+qword_set_loop:
+ ld r3, @(4,r4) /* cache line allocate */
+ addi r2, #-16
+ st r1, @+r4
+ st r1, @+r4
+ cmpui r2, #16
+ st r1, @+r4
+ st r1, @+r4
+ bnc qword_set_loop
+ bnez r2, word_set_wrap
+ jmp r14
+word_set_wrap:
+ cmpui r2, #4
+ bc byte_set
+ addi r2, #-4
+ bra word_set_loop
+
+byte_set_wrap:
+ addi r2, #4
+ addi r4, #4
+ beqz r2, end_memset
+byte_set:
+ addi r2, #-1
+ stb r1, @r4
+ addi r4, #1
+ bnez r2, byte_set
+end_memset:
+ jmp r14
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .end
--- /dev/null
+/*
+ * __put_user functions.
+ *
+ * (C) Copyright 1998 Linus Torvalds
+ * (C) Copyright 2001 Hirokazu Takata
+ *
+ * These functions have a non-standard call interface
+ * to make them more efficient.
+ */
+
+#include <linux/config.h>
+
+/*
+ * __put_user_X
+ *
+ * Inputs: r0 contains the address
+ * r1 contains the value
+ *
+ * Outputs: r0 is error code (0 or -EFAULT)
+ * r1 is corrupted (will contain "current_task").
+ *
+ * These functions should not modify any other registers,
+ * as they get called from within inline assembly.
+ */
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ .text
+ .balign 4
+ .globl __put_user_1
+__put_user_1:
+1: stb r1, @r0 || ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __put_user_2
+__put_user_2:
+2: sth r1, @r0 || ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __put_user_4
+__put_user_4:
+3: st r1, @r0 || ldi r0, #0
+ jmp r14
+
+bad_put_user:
+ ldi r0, #-14 || jmp r14
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .text
+ .balign 4
+ .globl __put_user_1
+__put_user_1:
+1: stb r1, @r0
+ ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __put_user_2
+__put_user_2:
+2: sth r1, @r0
+ ldi r0, #0
+ jmp r14
+
+ .balign 4
+ .globl __put_user_4
+__put_user_4:
+3: st r1, @r0
+ ldi r0, #0
+ jmp r14
+
+bad_put_user:
+ ldi r0, #-14
+ jmp r14
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+.section __ex_table,"a"
+ .long 1b,bad_put_user
+ .long 2b,bad_put_user
+ .long 3b,bad_put_user
+.previous
--- /dev/null
+/*
+ * linux/arch/m32r/strlen.S -- strlen code.
+ *
+ * Copyright (C) 2001 Hirokazu Takata
+ *
+ * size_t strlen(const char *s);
+ *
+ */
+/* $Id$ */
+
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+ .text
+ENTRY(strlen)
+ mv r6, r0 || ldi r2, #0
+ and3 r0, r0, #3
+ bnez r0, strlen_byte
+;
+strlen_word:
+ ld r0, @r6+
+;
+ seth r5, #high(0x01010101)
+ or3 r5, r5, #low(0x01010101)
+ sll3 r7, r5, #7
+strlen_word_loop:
+ ld r1, @r6+ || not r4, r0
+ sub r0, r5 || and r4, r7
+ and r4, r0
+ bnez r4, strlen_last_bytes
+ ld r0, @r6+ || not r4, r1
+ sub r1, r5 || and r4, r7
+ and r4, r1 || addi r2, #4
+ bnez r4, strlen_last_bytes
+ addi r2, #4 || bra.s strlen_word_loop
+
+ ; NOTE: If a null char. exists, return 0.
+ ; if ((x - 0x01010101) & ~x & 0x80808080)
+ ; return 0;
+;
+strlen_byte:
+ ldb r1, @r6 || addi r6, #1
+ beqz r1, strlen_exit
+ addi r2, #1 || bra.s strlen_byte
+;
+strlen_last_bytes:
+ ldi r0, #4 || addi r6, #-8
+;
+strlen_byte_loop:
+ ldb r1, @r6 || addi r6, #1
+ addi r0, #-1 || cmpz r1
+ bc.s strlen_exit || cmpz r0
+ addi r2, #1 || bnc.s strlen_byte_loop
+;
+strlen_exit:
+ mv r0, r2 || jmp r14
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .text
+ENTRY(strlen)
+ mv r6, r0
+ ldi r2, #0
+ and3 r0, r0, #3
+ bnez r0, strlen_byte
+;
+strlen_word:
+ ld r0, @r6+
+;
+ seth r5, #high(0x01010101)
+ or3 r5, r5, #low(0x01010101)
+ sll3 r7, r5, #7
+strlen_word_loop:
+ ld r1, @r6+
+ not r4, r0 ; NOTE: If a null char. exists, return 0.
+ sub r0, r5 ; if ((x - 0x01010101) & ~x & 0x80808080)
+ and r4, r7 ; return 0;
+ and r4, r0
+ bnez r4, strlen_last_bytes
+ addi r2, #4
+;
+ ld r0, @r6+
+ not r4, r1 ; NOTE: If a null char. exists, return 0.
+ sub r1, r5 ; if ((x - 0x01010101) & ~x & 0x80808080)
+ and r4, r7 ; return 0;
+ and r4, r1
+ bnez r4, strlen_last_bytes
+ addi r2, #4
+ bra strlen_word_loop
+;
+strlen_byte:
+ ldb r1, @r6
+ addi r6, #1
+ beqz r1, strlen_exit
+ addi r2, #1
+ bra strlen_byte
+;
+strlen_last_bytes:
+ ldi r0, #4
+ addi r6, #-8
+;
+strlen_byte_loop:
+ ldb r1, @r6
+ addi r6, #1
+ addi r0, #-1
+ beqz r1, strlen_exit
+ addi r2, #1
+ bnez r0, strlen_byte_loop
+;
+strlen_exit:
+ mv r0, r2
+ jmp r14
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+ .end
--- /dev/null
+/*
+ * User address space access functions.
+ * The non inlined parts of asm-m32r/uaccess.h are here.
+ *
+ * Copyright 1997 Andi Kleen <ak@muc.de>
+ * Copyright 1997 Linus Torvalds
+ * Copyright 2001, 2002, 2004 Hirokazu Takata
+ */
+#include <linux/config.h>
+#include <linux/prefetch.h>
+#include <linux/string.h>
+#include <linux/thread_info.h>
+#include <asm/uaccess.h>
+
+unsigned long
+__generic_copy_to_user(void *to, const void *from, unsigned long n)
+{
+ prefetch(from);
+ if (access_ok(VERIFY_WRITE, to, n))
+ __copy_user(to,from,n);
+ return n;
+}
+
+unsigned long
+__generic_copy_from_user(void *to, const void *from, unsigned long n)
+{
+ prefetchw(to);
+ if (access_ok(VERIFY_READ, from, n))
+ __copy_user_zeroing(to,from,n);
+ else
+ memset(to, 0, n);
+ return n;
+}
+
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+#define __do_strncpy_from_user(dst,src,count,res) \
+do { \
+ int __d0, __d1, __d2; \
+ __asm__ __volatile__( \
+ " beqz %1, 2f\n" \
+ " .fillinsn\n" \
+ "0: ldb r14, @%3 || addi %3, #1\n" \
+ " stb r14, @%4 || addi %4, #1\n" \
+ " beqz r14, 1f\n" \
+ " addi %1, #-1\n" \
+ " bnez %1, 0b\n" \
+ " .fillinsn\n" \
+ "1: sub %0, %1\n" \
+ " .fillinsn\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "3: seth r14, #high(2b)\n" \
+ " or3 r14, r14, #low(2b)\n" \
+ " jmp r14 || ldi %0, #%5\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ ".previous" \
+ : "=r"(res), "=r"(count), "=&r" (__d0), "=&r" (__d1), \
+ "=&r" (__d2) \
+ : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), \
+ "4"(dst) \
+ : "r14", "cbit", "memory"); \
+} while (0)
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+#define __do_strncpy_from_user(dst,src,count,res) \
+do { \
+ int __d0, __d1, __d2; \
+ __asm__ __volatile__( \
+ " beqz %1, 2f\n" \
+ " .fillinsn\n" \
+ "0: ldb r14, @%3\n" \
+ " stb r14, @%4\n" \
+ " addi %3, #1\n" \
+ " addi %4, #1\n" \
+ " beqz r14, 1f\n" \
+ " addi %1, #-1\n" \
+ " bnez %1, 0b\n" \
+ " .fillinsn\n" \
+ "1: sub %0, %1\n" \
+ " .fillinsn\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "3: ldi %0, #%5\n" \
+ " seth r14, #high(2b)\n" \
+ " or3 r14, r14, #low(2b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ ".previous" \
+ : "=r"(res), "=r"(count), "=&r" (__d0), "=&r" (__d1), \
+ "=&r" (__d2) \
+ : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), \
+ "4"(dst) \
+ : "r14", "cbit", "memory"); \
+} while (0)
+
+#endif /* CONFIG_ISA_DUAL_ISSUE */
+
+long
+__strncpy_from_user(char *dst, const char *src, long count)
+{
+ long res;
+ __do_strncpy_from_user(dst, src, count, res);
+ return res;
+}
+
+long
+strncpy_from_user(char *dst, const char *src, long count)
+{
+ long res = -EFAULT;
+ if (access_ok(VERIFY_READ, src, 1))
+ __do_strncpy_from_user(dst, src, count, res);
+ return res;
+}
+
+
+/*
+ * Zero Userspace
+ */
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+#define __do_clear_user(addr,size) \
+do { \
+ int __dst, __c; \
+ __asm__ __volatile__( \
+ " beqz %1, 9f\n" \
+ " and3 r14, %0, #3\n" \
+ " bnez r14, 2f\n" \
+ " and3 r14, %1, #3\n" \
+ " bnez r14, 2f\n" \
+ " and3 %1, %1, #3\n" \
+ " beqz %2, 2f\n" \
+ " addi %0, #-4\n" \
+ " .fillinsn\n" \
+ "0: ; word clear \n" \
+ " st %6, @+%0 || addi %2, #-1\n" \
+ " bnez %2, 0b\n" \
+ " beqz %1, 9f\n" \
+ " .fillinsn\n" \
+ "2: ; byte clear \n" \
+ " stb %6, @%0 || addi %1, #-1\n" \
+ " addi %0, #1\n" \
+ " bnez %1, 2b\n" \
+ " .fillinsn\n" \
+ "9:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "4: slli %2, #2\n" \
+ " seth r14, #high(9b)\n" \
+ " or3 r14, r14, #low(9b)\n" \
+ " jmp r14 || add %1, %2\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,4b\n" \
+ " .long 2b,9b\n" \
+ ".previous\n" \
+ : "=&r"(__dst), "=&r"(size), "=&r"(__c) \
+ : "0"(addr), "1"(size), "2"(size / 4), "r"(0) \
+ : "r14", "cbit", "memory"); \
+} while (0)
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+#define __do_clear_user(addr,size) \
+do { \
+ int __dst, __c; \
+ __asm__ __volatile__( \
+ " beqz %1, 9f\n" \
+ " and3 r14, %0, #3\n" \
+ " bnez r14, 2f\n" \
+ " and3 r14, %1, #3\n" \
+ " bnez r14, 2f\n" \
+ " and3 %1, %1, #3\n" \
+ " beqz %2, 2f\n" \
+ " addi %0, #-4\n" \
+ " .fillinsn\n" \
+ "0: st %6, @+%0 ; word clear \n" \
+ " addi %2, #-1\n" \
+ " bnez %2, 0b\n" \
+ " beqz %1, 9f\n" \
+ " .fillinsn\n" \
+ "2: stb %6, @%0 ; byte clear \n" \
+ " addi %1, #-1\n" \
+ " addi %0, #1\n" \
+ " bnez %1, 2b\n" \
+ " .fillinsn\n" \
+ "9:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "4: slli %2, #2\n" \
+ " add %1, %2\n" \
+ " seth r14, #high(9b)\n" \
+ " or3 r14, r14, #low(9b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,4b\n" \
+ " .long 2b,9b\n" \
+ ".previous\n" \
+ : "=&r"(__dst), "=&r"(size), "=&r"(__c) \
+ : "0"(addr), "1"(size), "2"(size / 4), "r"(0) \
+ : "r14", "cbit", "memory"); \
+} while (0)
+
+#endif /* not CONFIG_ISA_DUAL_ISSUE */
+
+unsigned long
+clear_user(void *to, unsigned long n)
+{
+ if (access_ok(VERIFY_WRITE, to, n))
+ __do_clear_user(to, n);
+ return n;
+}
+
+unsigned long
+__clear_user(void *to, unsigned long n)
+{
+ __do_clear_user(to, n);
+ return n;
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+
+#ifdef CONFIG_ISA_DUAL_ISSUE
+
+long strnlen_user(const char *s, long n)
+{
+ unsigned long mask = -__addr_ok(s);
+ unsigned long res;
+
+ __asm__ __volatile__(
+ " and %0, %5 || mv r1, %1\n"
+ " beqz %0, strnlen_exit\n"
+ " and3 r0, %1, #3\n"
+ " bnez r0, strnlen_byte_loop\n"
+ " cmpui %0, #4\n"
+ " bc strnlen_byte_loop\n"
+ "strnlen_word_loop:\n"
+ "0: ld r0, @%1+\n"
+ " pcmpbz r0\n"
+ " bc strnlen_last_bytes_fixup\n"
+ " addi %0, #-4\n"
+ " beqz %0, strnlen_exit\n"
+ " bgtz %0, strnlen_word_loop\n"
+ "strnlen_last_bytes:\n"
+ " mv %0, %4\n"
+ "strnlen_last_bytes_fixup:\n"
+ " addi %1, #-4\n"
+ "strnlen_byte_loop:\n"
+ "1: ldb r0, @%1 || addi %0, #-1\n"
+ " beqz r0, strnlen_exit\n"
+ " addi %1, #1\n"
+ " bnez %0, strnlen_byte_loop\n"
+ "strnlen_exit:\n"
+ " sub %1, r1\n"
+ " add3 %0, %1, #1\n"
+ " .fillinsn\n"
+ "9:\n"
+ ".section .fixup,\"ax\"\n"
+ " .balign 4\n"
+ "4: addi %1, #-4\n"
+ " .fillinsn\n"
+ "5: seth r1, #high(9b)\n"
+ " or3 r1, r1, #low(9b)\n"
+ " jmp r1 || ldi %0, #0\n"
+ ".previous\n"
+ ".section __ex_table,\"a\"\n"
+ " .balign 4\n"
+ " .long 0b,4b\n"
+ " .long 1b,5b\n"
+ ".previous"
+ : "=&r" (res), "=r" (s)
+ : "0" (n), "1" (s), "r" (n & 3), "r" (mask), "r"(0x01010101)
+ : "r0", "r1", "cbit");
+
+ /* NOTE: strnlen_user() algorism:
+ * {
+ * char *p;
+ * for (p = s; n-- && *p != '\0'; ++p)
+ * ;
+ * return p - s + 1;
+ * }
+ */
+
+ /* NOTE: If a null char. exists, return 0.
+ * if ((x - 0x01010101) & ~x & 0x80808080)\n"
+ * return 0;\n"
+ */
+
+ return res & mask;
+}
+
+#else /* not CONFIG_ISA_DUAL_ISSUE */
+
+long strnlen_user(const char *s, long n)
+{
+ unsigned long mask = -__addr_ok(s);
+ unsigned long res;
+
+ __asm__ __volatile__(
+ " and %0, %5\n"
+ " mv r1, %1\n"
+ " beqz %0, strnlen_exit\n"
+ " and3 r0, %1, #3\n"
+ " bnez r0, strnlen_byte_loop\n"
+ " cmpui %0, #4\n"
+ " bc strnlen_byte_loop\n"
+ " sll3 r3, %6, #7\n"
+ "strnlen_word_loop:\n"
+ "0: ld r0, @%1+\n"
+ " not r2, r0\n"
+ " sub r0, %6\n"
+ " and r2, r3\n"
+ " and r2, r0\n"
+ " bnez r2, strnlen_last_bytes_fixup\n"
+ " addi %0, #-4\n"
+ " beqz %0, strnlen_exit\n"
+ " bgtz %0, strnlen_word_loop\n"
+ "strnlen_last_bytes:\n"
+ " mv %0, %4\n"
+ "strnlen_last_bytes_fixup:\n"
+ " addi %1, #-4\n"
+ "strnlen_byte_loop:\n"
+ "1: ldb r0, @%1\n"
+ " addi %0, #-1\n"
+ " beqz r0, strnlen_exit\n"
+ " addi %1, #1\n"
+ " bnez %0, strnlen_byte_loop\n"
+ "strnlen_exit:\n"
+ " sub %1, r1\n"
+ " add3 %0, %1, #1\n"
+ " .fillinsn\n"
+ "9:\n"
+ ".section .fixup,\"ax\"\n"
+ " .balign 4\n"
+ "4: addi %1, #-4\n"
+ " .fillinsn\n"
+ "5: ldi %0, #0\n"
+ " seth r1, #high(9b)\n"
+ " or3 r1, r1, #low(9b)\n"
+ " jmp r1\n"
+ ".previous\n"
+ ".section __ex_table,\"a\"\n"
+ " .balign 4\n"
+ " .long 0b,4b\n"
+ " .long 1b,5b\n"
+ ".previous"
+ : "=&r" (res), "=r" (s)
+ : "0" (n), "1" (s), "r" (n & 3), "r" (mask), "r"(0x01010101)
+ : "r0", "r1", "r2", "r3", "cbit");
+
+ /* NOTE: strnlen_user() algorism:
+ * {
+ * char *p;
+ * for (p = s; n-- && *p != '\0'; ++p)
+ * ;
+ * return p - s + 1;
+ * }
+ */
+
+ /* NOTE: If a null char. exists, return 0.
+ * if ((x - 0x01010101) & ~x & 0x80808080)\n"
+ * return 0;\n"
+ */
+
+ return res & mask;
+}
+
+#endif /* CONFIG_ISA_DUAL_ISSUE */
+
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+
+#
+# Processor type and features
+#
+# CONFIG_PLAT_MAPPI is not set
+# CONFIG_PLAT_USRV is not set
+CONFIG_PLAT_M32700UT=y
+# CONFIG_PLAT_OPSPUT is not set
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+CONFIG_CHIP_M32700=y
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+CONFIG_MMU=y
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=50000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x01000000
+CONFIG_NOHIGHMEM=y
+# CONFIG_DISCONTIGMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+CONFIG_SMP=y
+CONFIG_CHIP_M32700_TS1=y
+CONFIG_NR_CPUS=2
+# CONFIG_NUMA is not set
+
+#
+# M32R drivers
+#
+# CONFIG_M32RPCC is not set
+CONFIG_M32R_CFC=y
+CONFIG_M32700UT_CFC=y
+CONFIG_CFC_NUM=1
+# CONFIG_MTD_M32R is not set
+CONFIG_M32R_SMC91111=y
+CONFIG_M32700UT_DS1302=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=m
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_M32R_SIO is not set
+CONFIG_SERIAL_M32R_PLDSIO=y
+CONFIG_SERIAL_M32R_PLDSIO_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+
+#
+# Video For Linux
+#
+
+#
+# Video Adapters
+#
+# CONFIG_VIDEO_CPIA is not set
+CONFIG_M32R_AR=y
+CONFIG_M32R_AR_VGA=y
+
+#
+# Radio Adapters
+#
+# CONFIG_RADIO_MAESTRO is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+CONFIG_FB=y
+CONFIG_FB_EPSON_S1D13806=y
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Logo configuration
+#
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_M32R_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Processor type and features
+#
+# CONFIG_PLAT_MAPPI is not set
+# CONFIG_PLAT_USRV is not set
+CONFIG_PLAT_M32700UT=y
+# CONFIG_PLAT_OPSPUT is not set
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+CONFIG_CHIP_M32700=y
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+CONFIG_MMU=y
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=50000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x01000000
+CONFIG_NOHIGHMEM=y
+# CONFIG_DISCONTIGMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+# CONFIG_SMP is not set
+
+#
+# M32R drivers
+#
+# CONFIG_M32RPCC is not set
+CONFIG_M32R_CFC=y
+CONFIG_M32700UT_CFC=y
+CONFIG_CFC_NUM=1
+# CONFIG_MTD_M32R is not set
+CONFIG_M32R_SMC91111=y
+CONFIG_M32700UT_DS1302=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=m
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_M32R_SIO is not set
+CONFIG_SERIAL_M32R_PLDSIO=y
+CONFIG_SERIAL_M32R_PLDSIO_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+
+#
+# Video For Linux
+#
+
+#
+# Video Adapters
+#
+# CONFIG_VIDEO_CPIA is not set
+CONFIG_M32R_AR=y
+CONFIG_M32R_AR_VGA=y
+
+#
+# Radio Adapters
+#
+# CONFIG_RADIO_MAESTRO is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+CONFIG_FB=y
+CONFIG_FB_EPSON_S1D13806=y
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+
+#
+# Logo configuration
+#
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_M32R_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+# .gdbinit file
+# $Id: dot.gdbinit_200MHz_16MB,v 1.1 2004/08/17 02:58:11 takata Exp $
+#-----
+# NOTE: this file is generated by a script, "gen_gdbinit.pl".
+# (Please type "gen_gdbinit.pl --help" and check the help message).
+# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
+#-----
+# target platform: m32700ut
+
+# setting
+set width 0d70
+set radix 0d16
+
+debug_chaos
+
+# clk xin:cpu:bif:bus=25:200:50:50
+define clock_init
+ set *(unsigned long *)0x00ef4008 = 0x00000000
+ set *(unsigned long *)0x00ef4004 = 0
+ shell sleep 0.1
+ # NOTE: Please change the master clock source from PLL-clock to Xin-clock
+ # and switch off PLL, before resetting the clock gear ratio.
+
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 2
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 3
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x00000200
+end
+
+# Initialize SDRAM controller
+define sdram_init
+ # SDIR0
+ set *(unsigned long *)0x00ef6008 = 0x00000182
+ # SDIR1
+ set *(unsigned long *)0x00ef600c = 0x00000001
+ # Initialize wait
+ shell sleep 0.1
+ # Ch0-MOD
+ set *(unsigned long *)0x00ef602c = 0x00000020
+ # Ch0-TR
+ set *(unsigned long *)0x00ef6028 = 0x00041302
+ # Ch0-ADR (size:16MB)
+ set *(unsigned long *)0x00ef6020 = 0x08000002
+ # AutoRef On
+ set *(unsigned long *)0x00ef6004 = 0x00010517
+ # Access enable
+ set *(unsigned long *)0x00ef6024 = 0x00000001
+end
+document sdram_init
+ SDRAM controller initialization
+ 0x08000000 - 0x08ffffff (16MB)
+end
+
+# Initialize BSEL3 for UT-CFC
+define cfc_init
+ set $sfrbase = 0xa0ef0000
+# too fast
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
+end
+document cfc_init
+ CF controller initialization
+end
+
+# MMU enable
+define mmu_enable
+ set $evb=0x88000000
+ set *(unsigned long *)0xffff0024=1
+end
+
+# MMU disable
+define mmu_disable
+ set $evb=0
+ set *(unsigned long *)0xffff0024=0
+end
+
+# Show TLB entries
+define show_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ set $nr_entries = $arg1
+ use_mon_code
+ while ($i < $nr_entries)
+ set $tlb_tag = *(unsigned long*)$addr
+ set $tlb_data = *(unsigned long*)($addr + 4)
+ printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define itlb
+ set $itlb=0xfe000000
+ show_tlb_entries $itlb 0d32
+end
+define dtlb
+ set $dtlb=0xfe000800
+ show_tlb_entries $dtlb 0d32
+end
+
+# Initialize TLB entries
+define init_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ set $nr_entries = $arg1
+ use_mon_code
+ while ($i < $nr_entries)
+ set *(unsigned long *)($addr + 0x4) = 0
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define tlb_init
+ set $itlb=0xfe000000
+ init_tlb_entries $itlb 0d32
+ set $dtlb=0xfe000800
+ init_tlb_entries $dtlb 0d32
+end
+
+# Show current task structure
+define show_current
+ set $current = $spi & 0xffffe000
+ printf "$current=0x%08lX\n",$current
+ print *(struct task_struct *)$current
+end
+
+# Show user assigned task structure
+define show_task
+ set = $arg0 & 0xffffe000
+ printf "$task=0x%08lX\n",$task
+ print *(struct task_struct *)$task
+end
+document show_task
+ Show user assigned task structure
+ arg0 : task structure address
+end
+
+# Show M32R registers
+define show_regs
+ printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
+ printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
+ printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
+ printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
+ printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
+ printf "EVB[0x%08lX]\n",$evb
+end
+
+# Setup all
+define setup
+ use_mon_code
+ set *(unsigned int)0xfffffffc=0x60
+ shell sleep 0.1
+ clock_init
+ shell sleep 0.1
+ # SDRAM: 16MB
+ set *(unsigned long *)0x00ef6020 = 0x08000002
+ cfc_init
+ # USB
+ set *(unsigned short *)0xb0301000 = 0x100
+
+ set $evb=0x08000000
+end
+
+# Load modules
+define load_modules
+ use_debug_dma
+ load
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x08002000
+ # INITRD_START
+ set *(unsigned long *)($param + 0x0010) = 0x082a0000
+ # INITRD_SIZE
+ set *(unsigned long *)($param + 0x0014) = 0x00000000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d200000000
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d50000000
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+ set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x console=tty1 video=s1d13xxxfb:mode:240x320-16 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=16M \0"
+end
+
+# Boot
+define boot
+ set_kernel_parameters
+ set $fp = 0
+ set $pc = 0x08001000
+ set *(unsigned char *)0xffffffff = 0x03
+ si
+ c
+end
+
+# Set breakpoints
+define set_breakpoints
+ b *0x08000030
+end
+
+# Restart
+define restart
+ sdireset
+ sdireset
+ set $pc = 0
+ b *0x04001000
+ b *0x08001000
+ b *0x08002000
+ si
+ c
+ tlb_init
+ del
+ setup
+ load_modules
+ boot
+end
+
+define si
+ stepi
+ x/i $pc
+ show_reg
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+set $pc = 0
+b *0x04001000
+b *0x08001000
+b *0x08002000
+c
+tlb_init
+del
+setup
+load_modules
+boot
+
--- /dev/null
+# .gdbinit file
+# $Id: dot.gdbinit_300MHz_32MB,v 1.1 2004/08/17 02:58:11 takata Exp $
+#-----
+# NOTE: this file is generated by a script, "gen_gdbinit.pl".
+# (Please type "gen_gdbinit.pl --help" and check the help message).
+# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
+#-----
+# target platform: m32700ut
+
+# setting
+set width 0d70
+set radix 0d16
+
+debug_chaos
+
+# clk xin:cpu:bif:bus=25:300:75:75
+define clock_init
+ set *(unsigned long *)0x00ef4008 = 0x00000000
+ set *(unsigned long *)0x00ef4004 = 0
+ shell sleep 0.1
+ # NOTE: Please change the master clock source from PLL-clock to Xin-clock
+ # and switch off PLL, before resetting the clock gear ratio.
+
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 2
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 5
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x00000200
+end
+
+# Initialize SDRAM controller
+define sdram_init
+ # SDIR0
+ set *(unsigned long *)0x00ef6008 = 0x00000182
+ # SDIR1
+ set *(unsigned long *)0x00ef600c = 0x00000001
+ # Initialize wait
+ shell sleep 0.1
+ # Ch0-MOD
+ set *(unsigned long *)0x00ef602c = 0x00000020
+ # Ch0-TR
+ set *(unsigned long *)0x00ef6028 = 0x00051502
+ # Ch0-ADR (size:16MB)
+ set *(unsigned long *)0x00ef6020 = 0x08000002
+ # AutoRef On
+ set *(unsigned long *)0x00ef6004 = 0x00010e24
+ # Access enable
+ set *(unsigned long *)0x00ef6024 = 0x00000001
+end
+document sdram_init
+ SDRAM controller initialization
+ 0x08000000 - 0x08ffffff (16MB)
+end
+
+# Initialize BSEL3 for UT-CFC
+define cfc_init
+ set $sfrbase = 0xa0ef0000
+# too fast
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
+end
+document cfc_init
+ CF controller initialization
+end
+
+# MMU enable
+define mmu_enable
+ set $evb=0x88000000
+ set *(unsigned long *)0xffff0024=1
+end
+
+# MMU disable
+define mmu_disable
+ set $evb=0
+ set *(unsigned long *)0xffff0024=0
+end
+
+# Show TLB entries
+define show_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ set $nr_entries = $arg1
+ use_mon_code
+ while ($i < $nr_entries)
+ set $tlb_tag = *(unsigned long*)$addr
+ set $tlb_data = *(unsigned long*)($addr + 4)
+ printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define itlb
+ set $itlb=0xfe000000
+ show_tlb_entries $itlb 0d32
+end
+define dtlb
+ set $dtlb=0xfe000800
+ show_tlb_entries $dtlb 0d32
+end
+
+# Initialize TLB entries
+define init_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ set $nr_entries = $arg1
+ use_mon_code
+ while ($i < $nr_entries)
+ set *(unsigned long *)($addr + 0x4) = 0
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define tlb_init
+ set $itlb=0xfe000000
+ init_tlb_entries $itlb 0d32
+ set $dtlb=0xfe000800
+ init_tlb_entries $dtlb 0d32
+end
+
+# Show current task structure
+define show_current
+ set $current = $spi & 0xffffe000
+ printf "$current=0x%08lX\n",$current
+ print *(struct task_struct *)$current
+end
+
+# Show user assigned task structure
+define show_task
+ set = $arg0 & 0xffffe000
+ printf "$task=0x%08lX\n",$task
+ print *(struct task_struct *)$task
+end
+document show_task
+ Show user assigned task structure
+ arg0 : task structure address
+end
+
+# Show M32R registers
+define show_regs
+ printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
+ printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
+ printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
+ printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
+ printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
+ printf "EVB[0x%08lX]\n",$evb
+end
+
+# Setup all
+define setup
+ use_mon_code
+ set *(unsigned int)0xfffffffc=0x60
+ shell sleep 0.1
+ clock_init
+ shell sleep 0.1
+ # SDRAM: 16MB
+ set *(unsigned long *)0x00ef6020 = 0x08000002
+ cfc_init
+ # USB
+ set *(unsigned short *)0xb0301000 = 0x100
+
+ set $evb=0x08000000
+end
+
+# Load modules
+define load_modules
+ use_debug_dma
+ load
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x08002000
+ # INITRD_START
+ set *(unsigned long *)($param + 0x0010) = 0x082a0000
+ # INITRD_SIZE
+ set *(unsigned long *)($param + 0x0014) = 0x00000000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d300000000
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d75000000
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+ set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x console=tty1 video=s1d13xxxfb:mode:240x320-16 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=16M \0"
+end
+
+# Boot
+define boot
+ set_kernel_parameters
+ set $fp = 0
+ set $pc = 0x08001000
+ set *(unsigned char *)0xffffffff = 0x03
+ si
+ c
+end
+
+# Set breakpoints
+define set_breakpoints
+ b *0x08000030
+end
+
+# Restart
+define restart
+ sdireset
+ sdireset
+ set $pc = 0
+ b *0x04001000
+ b *0x08001000
+ b *0x08002000
+ si
+ c
+ tlb_init
+ del
+ setup
+ load_modules
+ boot
+end
+
+define si
+ stepi
+ x/i $pc
+ show_reg
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+set $pc = 0
+b *0x04001000
+b *0x08001000
+b *0x08002000
+c
+tlb_init
+del
+setup
+load_modules
+boot
+
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Processor type and features
+#
+CONFIG_PLAT_MAPPI=y
+# CONFIG_PLAT_USRV is not set
+# CONFIG_PLAT_M32700UT is not set
+# CONFIG_PLAT_OPSPUT is not set
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+CONFIG_CHIP_M32700=y
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+# CONFIG_MMU is not set
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=50000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x00000000
+CONFIG_MEMORY_SIZE=0x00E00000
+CONFIG_NOHIGHMEM=y
+# CONFIG_DISCONTIGMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+# CONFIG_SMP is not set
+
+#
+# M32R drivers
+#
+# CONFIG_M32RPCC is not set
+CONFIG_M32R_NE2000=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+# CONFIG_PCMCIA is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_FLAT=y
+# CONFIG_BINFMT_ZFLAT is not set
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_M32R_SIO=y
+CONFIG_SERIAL_M32R_SIO_CONSOLE=y
+# CONFIG_SERIAL_M32R_PLDSIO is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS_XATTR=y
+CONFIG_DEVPTS_FS_SECURITY=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_CLEAN_COMPILE is not set
+CONFIG_BROKEN=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+
+#
+# Processor type and features
+#
+CONFIG_PLAT_MAPPI=y
+# CONFIG_PLAT_USRV is not set
+# CONFIG_PLAT_M32700UT is not set
+# CONFIG_PLAT_OPSPUT is not set
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+CONFIG_CHIP_M32700=y
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+CONFIG_MMU=y
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=10000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_NOHIGHMEM=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IRAM_START=0x00f00000
+CONFIG_IRAM_SIZE=0x00080000
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+CONFIG_SMP=y
+CONFIG_CHIP_M32700_TS1=y
+CONFIG_NR_CPUS=2
+# CONFIG_NUMA is not set
+
+#
+# M32R drivers
+#
+CONFIG_M32RPCC=y
+CONFIG_M32R_NE2000=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_M32R_SIO=y
+CONFIG_SERIAL_M32R_SIO_CONSOLE=y
+# CONFIG_SERIAL_M32R_PLDSIO is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+CONFIG_JFFS_PROC_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_CLEAN_COMPILE is not set
+CONFIG_BROKEN=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Processor type and features
+#
+CONFIG_PLAT_MAPPI=y
+# CONFIG_PLAT_USRV is not set
+# CONFIG_PLAT_M32700UT is not set
+# CONFIG_PLAT_OPSPUT is not set
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+CONFIG_CHIP_M32700=y
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+CONFIG_MMU=y
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=10000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_NOHIGHMEM=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IRAM_START=0x00f00000
+CONFIG_IRAM_SIZE=0x00080000
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+# CONFIG_SMP is not set
+
+#
+# M32R drivers
+#
+CONFIG_M32RPCC=y
+CONFIG_M32R_NE2000=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+CONFIG_BLK_DEV_IDECD=m
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_M32R_SIO=y
+CONFIG_SERIAL_M32R_SIO_CONSOLE=y
+# CONFIG_SERIAL_M32R_PLDSIO is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+CONFIG_JFFS_PROC_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- /dev/null
+# .gdbinit file
+# $Id$
+#-----
+# NOTE: this file is generated by a script, "gen_gdbinit.pl".
+# (Please type "gen_gdbinit.pl --help" and check the help message).
+# $ Id: gen_gdbinit.pl,v 1.8 2004/02/27 07:08:32 takata Exp $
+#-----
+# target platform: mappi
+
+# setting
+set width 0d70
+set radix 0d16
+debug_chaos
+
+# clk xin:cpu:bif:bus=30:360:180:90
+define clock_init
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 1
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 5
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x00000200
+end
+
+# Initialize programmable ports
+define port_init
+ set $sfrbase = 0x00ef0000
+ set *(unsigned short *)0x00ef1060 = 0x5555
+ set *(unsigned short *)0x00ef1062 = 0x5555
+ set *(unsigned short *)0x00ef1064 = 0x5555
+ set *(unsigned short *)0x00ef1066 = 0x5555
+ set *(unsigned short *)0x00ef1068 = 0x5555
+ set *(unsigned short *)0x00ef106a = 0x0000
+ set *(unsigned short *)0x00ef106e = 0x5555
+ set *(unsigned short *)0x00ef1070 = 0x5555
+ # LED ON
+ set *(unsigned char *)($sfrbase + 0x1015) = 0xff
+ set *(unsigned char *)($sfrbase + 0x1085) = 0xff
+ shell sleep 0.1
+ # LED OFF
+ set *(unsigned char *)($sfrbase + 0x1085) = 0x00
+end
+document port_init
+ P5=LED(output), P6.b4=LAN_RESET(output)
+end
+
+# Initialize SDRAM controller
+define sdram_init
+ # SDIR0
+ set *(unsigned long *)0x00ef6008 = 0x00000182
+ # SDIR1
+ set *(unsigned long *)0x00ef600c = 0x00000001
+ # Initialize wait
+ shell sleep 0.1
+ # Ch0-MOD
+ set *(unsigned long *)0x00ef602c = 0x00000020
+ # Ch0-TR
+ set *(unsigned long *)0x00ef6028 = 0x00051502
+ # Ch0-ADR (size:64MB)
+ set *(unsigned long *)0x00ef6020 = 0x08000004
+ # AutoRef On
+ set *(unsigned long *)0x00ef6004 = 0x00010e2b
+ # Access enable
+ set *(unsigned long *)0x00ef6024 = 0x00000001
+end
+document sdram_init
+ SDRAM controller initialization
+ 0x08000000 - 0x0bffffff (64MB)
+end
+
+# Initialize LAN controller
+define lanc_init
+ set $sfrbase = 0x00ef0000
+ # Set BSEL3 (BSEL3 for the Chaos's bselc)
+ set *(unsigned long *)($sfrbase + 0x5300) = 0x0a0a8040
+ set *(unsigned long *)($sfrbase + 0x5304) = 0x01120203
+ set *(unsigned long *)($sfrbase + 0x5308) = 0x00000001
+ # Reset (P5=LED,P6.b4=LAN_RESET)
+ set *(unsigned short *)($sfrbase + 0x106c) = 0x0000
+ set *(unsigned char *)($sfrbase + 0x1016) = 0xff
+ set *(unsigned char *)($sfrbase + 0x1086) = 0xff
+ shell sleep 0.1
+ # swivel: 0=normal, 4=reverse
+# set *(unsigned char *)($sfrbase + 0x1086) = 0x00
+ set *(unsigned char *)($sfrbase + 0x1086) = 0x04
+ set *(unsigned long *)(0x0c000330) = 0xffffffff
+ # Set mac address
+ set $lanc = (void*)0x0c000300
+ set *(unsigned long *)($lanc + 0x0000) = 0x00610010
+ set *(unsigned long *)($lanc + 0x0004) = 0x00200030
+ set *(unsigned long *)($lanc + 0x0008) = 0x00400050
+ set *(unsigned long *)($lanc + 0x000c) = 0x00600007
+end
+document lanc_init
+ LAN controller initialization
+ ex.) MAC address: 10 20 30 40 50 60
+end
+
+# LCD & CRT dual-head setting (8bpp)
+define dispc_init
+ set $sfrbase = 0x00ef0000
+ # BSEL4 Dispc
+ set *(unsigned long *)($sfrbase + 0x5400) = 0x0e0e8000
+ set *(unsigned long *)($sfrbase + 0x5404) = 0x0012220a
+end
+
+# MMU enable
+define mmu_enable
+ set $evb=0x88000000
+ set *(unsigned long *)0xffff0024=1
+end
+
+# MMU disable
+define mmu_disable
+ set $evb=0
+ set *(unsigned long *)0xffff0024=0
+end
+
+# Show TLB entries
+define show_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ set $nr_entries = $arg1
+ use_mon_code
+ while ($i < $nr_entries)
+ set $tlb_tag = *(unsigned long*)$addr
+ set $tlb_data = *(unsigned long*)($addr + 4)
+ printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define itlb
+ set $itlb=0xfe000000
+ show_tlb_entries $itlb 0d32
+end
+define dtlb
+ set $dtlb=0xfe000800
+ show_tlb_entries $dtlb 0d32
+end
+
+# Show current task structure
+define show_current
+ set $current = $spi & 0xffffe000
+ printf "$current=0x%08lX\n",$current
+ print *(struct task_struct *)$current
+end
+
+# Show user assigned task structure
+define show_task
+ set = $arg0 & 0xffffe000
+ printf "$task=0x%08lX\n",$task
+ print *(struct task_struct *)$task
+end
+document show_task
+ Show user assigned task structure
+ arg0 : task structure address
+end
+
+# Show M32R registers
+define show_regs
+ printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
+ printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
+ printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
+ printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
+ printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
+ printf "EVB[0x%08lX]\n",$evb
+end
+
+# Setup all
+define setup
+ use_mon_code
+ set *(unsigned int)0xfffffffc=0x60
+ shell sleep 0.1
+ clock_init
+ shell sleep 0.1
+ port_init
+ sdram_init
+ lanc_init
+ dispc_init
+ set $evb=0x08000000
+end
+
+# Load modules
+define load_modules
+ use_debug_dma
+ load
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x08002000
+ # INITRD_START
+ set *(unsigned long *)($param + 0x0010) = 0x082a0000
+ # INITRD_SIZE
+ set *(unsigned long *)($param + 0x0014) = 0x00000000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d360000000
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d90000000
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+ set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.x nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
+end
+
+# Boot
+define boot
+ set_kernel_parameters
+ set $fp = 0
+ set $pc=0x08001000
+ si
+ c
+end
+
+# Set breakpoints
+define set_breakpoints
+ b *0x08000030
+end
+
+# Restart
+define restart
+ sdireset
+ sdireset
+ setup
+ load_modules
+ boot
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+setup
+#load_module
+#set_breakpoints
+#boot
+
--- /dev/null
+# .gdbinit file
+# $Id$
+#-----
+# NOTE: this file is generated by a script, "gen_gdbinit.pl".
+# (Please type "gen_gdbinit.pl --help" and check the help message).
+# $ Id: gen_gdbinit.pl,v 1.5 2004/01/23 08:23:25 takata Exp $
+#-----
+# target platform: mappi
+
+# setting
+set width 0d70
+set radix 0d16
+debug_chaos
+
+# clk xin:cpu:bif:bus=25:200:50:50
+define clock_init
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 2
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 3
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x00000200
+end
+
+# Initialize programmable ports
+define port_init
+ set $sfrbase = 0x00ef0000
+ set *(unsigned short *)0x00ef1060 = 0x5555
+ set *(unsigned short *)0x00ef1062 = 0x5555
+ set *(unsigned short *)0x00ef1064 = 0x5555
+ set *(unsigned short *)0x00ef1066 = 0x5555
+ set *(unsigned short *)0x00ef1068 = 0x5555
+ set *(unsigned short *)0x00ef106a = 0x0000
+ set *(unsigned short *)0x00ef106e = 0x5555
+ set *(unsigned short *)0x00ef1070 = 0x5555
+ # LED ON
+ set *(unsigned char *)($sfrbase + 0x1015) = 0xff
+ set *(unsigned char *)($sfrbase + 0x1085) = 0xff
+ shell sleep 0.1
+ # LED OFF
+ set *(unsigned char *)($sfrbase + 0x1085) = 0x00
+end
+document port_init
+ P5=LED(output), P6.b4=LAN_RESET(output)
+end
+
+# Initialize SDRAM controller
+define sdram_init
+ # SDIR0
+ set *(unsigned long *)0x00ef6008 = 0x00000182
+ # SDIR1
+ set *(unsigned long *)0x00ef600c = 0x00000001
+ # Initialize wait
+ shell sleep 0.1
+ # Ch0-MOD
+ set *(unsigned long *)0x00ef602c = 0x00000020
+ # Ch0-TR
+ set *(unsigned long *)0x00ef6028 = 0x00051502
+ # Ch0-ADR (size:64MB)
+ set *(unsigned long *)0x00ef6020 = 0x00000004
+ # AutoRef On
+ set *(unsigned long *)0x00ef6004 = 0x00010f05
+ # Access enable
+ set *(unsigned long *)0x00ef6024 = 0x00000001
+end
+document sdram_init
+ SDRAM controller initialization
+ 0x08000000 - 0x0bffffff (64MB)
+end
+
+# Initialize LAN controller
+define lanc_init
+ set $sfrbase = 0x00ef0000
+ # Set BSEL3 (BSEL3 for the Chaos's bselc)
+ set *(unsigned long *)($sfrbase + 0x5300) = 0x07078040
+ set *(unsigned long *)($sfrbase + 0x5304) = 0x01110102
+ set *(unsigned long *)($sfrbase + 0x5308) = 0x00000001
+ # Reset (P5=LED,P6.b4=LAN_RESET)
+ set *(unsigned short *)($sfrbase + 0x106c) = 0x0000
+ set *(unsigned char *)($sfrbase + 0x1016) = 0xff
+ set *(unsigned char *)($sfrbase + 0x1086) = 0xff
+ shell sleep 0.1
+ # swivel: 0=normal, 4=reverse
+# set *(unsigned char *)($sfrbase + 0x1086) = 0x00
+ set *(unsigned char *)($sfrbase + 0x1086) = 0x04
+ set *(unsigned long *)(0x0c000330) = 0xffffffff
+ # Set mac address
+ set $lanc = (void*)0x0c000300
+ set *(unsigned long *)($lanc + 0x0000) = 0x00610010
+ set *(unsigned long *)($lanc + 0x0004) = 0x00200030
+ set *(unsigned long *)($lanc + 0x0008) = 0x00400050
+ set *(unsigned long *)($lanc + 0x000c) = 0x00600007
+end
+document lanc_init
+ LAN controller initialization
+ ex.) MAC address: 10 20 30 40 50 60
+end
+
+# LCD & CRT dual-head setting (8bpp)
+define dispc_init
+ set $sfrbase = 0x00ef0000
+ # BSEL4 Dispc
+ set *(unsigned long *)($sfrbase + 0x5400) = 0x06078000
+ set *(unsigned long *)($sfrbase + 0x5404) = 0x00101101
+end
+
+# MMU enable
+define mmu_enable
+ set $evb=0x88000000
+ set *(unsigned long *)0xffff0024=1
+end
+
+# MMU disable
+define mmu_disable
+ set $evb=0
+ set *(unsigned long *)0xffff0024=0
+end
+
+# Show TLB entries
+define show_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ set $nr_entries = $arg1
+ use_mon_code
+ while ($i < $nr_entries)
+ set $tlb_tag = *(unsigned long*)$addr
+ set $tlb_data = *(unsigned long*)($addr + 4)
+ printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define itlb
+ set $itlb=0xfe000000
+ show_tlb_entries $itlb 0d32
+end
+define dtlb
+ set $dtlb=0xfe000800
+ show_tlb_entries $dtlb 0d32
+end
+
+# Show current task structure
+define show_current
+ set $current = $spi & 0xffffe000
+ printf "$current=0x%08lX\n",$current
+ print *(struct task_struct *)$current
+end
+
+# Show user assigned task structure
+define show_task
+ set = $arg0 & 0xffffe000
+ printf "$task=0x%08lX\n",$task
+ print *(struct task_struct *)$task
+end
+document show_task
+ Show user assigned task structure
+ arg0 : task structure address
+end
+
+# Show M32R registers
+define show_regs
+ printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
+ printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
+ printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
+ printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
+ printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
+ printf "EVB[0x%08lX]\n",$evb
+end
+
+# Setup all
+define setup
+ use_mon_code
+ set *(unsigned int)0xfffffffc=0x60
+ shell sleep 0.1
+ clock_init
+ shell sleep 0.1
+ port_init
+ sdram_init
+ lanc_init
+ dispc_init
+ set $evb=0x00000000
+end
+
+# Load modules
+define load_modules
+ use_debug_dma
+ load
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x00002000
+ # INITRD_START
+ #set *(unsigned long *)($param + 0x0010) = 0x082a0000
+ # INITRD_SIZE
+ #set *(unsigned long *)($param + 0x0014) = 0x00000000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d200000000
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d50000000
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+ set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.bbox-httpd nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
+end
+
+# Boot
+define boot
+ set_kernel_parameters
+ set $fp = 0
+ set $pc=0x00001000
+ set *(long *)0xfffffff4=0x8080
+# b load_flat_binary
+# set *(unsigned char *)0x08001003=0x63
+# set *(unsigned char *)0x08001003=0x02
+ si
+# c
+end
+
+# Set breakpoints
+define set_breakpoints
+ b *0x08000030
+end
+
+# Restart
+define restart
+ sdireset
+ sdireset
+ setup
+ load_modules
+ boot
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+setup
+load_modules
+boot
+
--- /dev/null
+# .gdbinit file
+# $Id$
+
+# setting
+set width 0d70
+set radix 0d16
+debug_chaos
+
+# clk xin:cpu:bif:bus=1:4:2:1
+define clock_init_on
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 1
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 0x1
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x0200
+# set *(unsigned long *)0x00ef4008 = 0x0201
+end
+
+# clk xin:cpu:bif:bus=1:4:1:1
+define clock_init_on_1411
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 2
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 0x1
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x0200
+end
+
+# clk xin:cpu:bif:bus=1:4:2:1
+define clock_init_on_1421
+ set *(unsigned long *)0x00ef4024 = 2
+ set *(unsigned long *)0x00ef4020 = 1
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 0x1
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x0200
+end
+
+# clk xin:cpu:bif:bus=1:8:2:1
+define clock_init_on_1821
+ set *(unsigned long *)0x00ef4024 = 3
+ set *(unsigned long *)0x00ef4020 = 2
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 0x3
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x0200
+end
+
+# clk xin:cpu:bif:bus=1:8:4:1
+define clock_init_on_1841
+ set *(unsigned long *)0x00ef4024 = 3
+ set *(unsigned long *)0x00ef4020 = 1
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 0x3
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x0200
+end
+
+# clk xin:cpu:bif:bus=1:16:8:1
+define clock_init_on_11681
+ set *(unsigned long *)0x00ef4024 = 4
+ set *(unsigned long *)0x00ef4020 = 2
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ set *(unsigned long *)0x00ef4004 = 0x7
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4008 = 0x0200
+end
+
+# clk xin:cpu:bif:bus=1:1:1:1
+define clock_init_off
+ # CPU
+ set *(unsigned long *)0x00ef4010 = 0
+ set *(unsigned long *)0x00ef4014 = 0
+ # BIF
+ set *(unsigned long *)0x00ef4020 = 0
+ # BUS
+ set *(unsigned long *)0x00ef4024 = 0
+ # PLL
+ set *(unsigned long *)0x00ef4008 = 0x0000
+end
+
+# Initialize programmable ports
+define port_init
+ set $sfrbase = 0x00ef0000
+ set *(unsigned short *)0x00ef1060 = 0x5555
+ set *(unsigned short *)0x00ef1062 = 0x5555
+ set *(unsigned short *)0x00ef1064 = 0x5555
+ set *(unsigned short *)0x00ef1066 = 0x5555
+ set *(unsigned short *)0x00ef1068 = 0x5555
+ set *(unsigned short *)0x00ef106a = 0x0000
+ set *(unsigned short *)0x00ef106e = 0x5555
+ set *(unsigned short *)0x00ef1070 = 0x5555
+ # LED ON
+ set *(unsigned char *)($sfrbase + 0x1015) = 0xff
+ set *(unsigned char *)($sfrbase + 0x1085) = 0xff
+ shell sleep 0.1
+ # LED OFF
+ set *(unsigned char *)($sfrbase + 0x1085) = 0x00
+end
+document port_init
+ P5=LED(output), P6.b4=LAN_RESET(output)
+end
+
+# Initialize SDRAM controller for Mappi
+define sdram_init
+ # SDIR0
+ set *(unsigned long *)0x00ef6008 = 0x00000182
+ # SDIR1
+ set *(unsigned long *)0x00ef600c = 0x00000001
+ # Initialize wait
+ shell sleep 0.1
+ # Ch0-MOD
+ set *(unsigned long *)0x00ef602c = 0x00000020
+ # Ch0-TR
+ set *(unsigned long *)0x00ef6028 = 0x00010002
+ # Ch0-ADR
+ set *(unsigned long *)0x00ef6020 = 0x08000004
+ # AutoRef On
+ set *(unsigned long *)0x00ef6004 = 0x00010107
+ # Access enable
+ set *(unsigned long *)0x00ef6024 = 0x00000001
+end
+document sdram_init
+ Mappi SDRAM controller initialization
+ 0x08000000 - 0x0bffffff (64MB)
+end
+
+# Initialize LAN controller for Mappi
+define lanc_init
+ set $sfrbase = 0x00ef0000
+ # Set BSEL3 (BSEL3 for the Chaos's bselc)
+# set *(unsigned long *)($sfrbase + 0x5300) = 0x01018040
+# set *(unsigned long *)($sfrbase + 0x5304) = 0x01011101
+ set *(unsigned long *)($sfrbase + 0x5300) = 0x04048000
+ set *(unsigned long *)($sfrbase + 0x5304) = 0x01011103
+ set *(unsigned long *)($sfrbase + 0x5308) = 0x00000001
+ # Reset (P5=LED,P6.b4=LAN_RESET)
+ set *(unsigned short *)($sfrbase + 0x106c) = 0x0000
+ set *(unsigned char *)($sfrbase + 0x1016) = 0xff
+ set *(unsigned char *)($sfrbase + 0x1086) = 0xff
+ shell sleep 0.1
+# set *(unsigned char *)($sfrbase + 0x1086) = 0x00
+ set *(unsigned char *)($sfrbase + 0x1086) = 0x04
+ set *(unsigned long *)(0x0c000330) = 0xffffffff
+ # Set mac address
+ set $lanc = (void*)0x0c000300
+ set *(unsigned long *)($lanc + 0x0000) = 0x00610010
+ set *(unsigned long *)($lanc + 0x0004) = 0x00200030
+ set *(unsigned long *)($lanc + 0x0008) = 0x00400050
+ set *(unsigned long *)($lanc + 0x000c) = 0x00600007
+end
+document lanc_init
+ Mappi LAN controller initialization
+ ex.) MAC address: 10 20 30 40 50 60
+end
+
+# LCD & CRT dual-head setting (8bpp)
+define dispc_init
+ set $sfrbase = 0x00ef0000
+ # BSEL4 Dispc
+ # 20MHz
+# set *(unsigned long *)($sfrbase + 0x5400) = 0x02028282
+# set *(unsigned long *)($sfrbase + 0x5404) = 0x00122202
+ # 40MHz
+ set *(unsigned long *)($sfrbase + 0x5400) = 0x04048000
+ set *(unsigned long *)($sfrbase + 0x5404) = 0x00101103
+end
+
+# MMU enable
+define mmu_enable
+ set $evb=0x88000000
+ set *(unsigned long *)0xffff0024=1
+end
+
+# MMU disable
+define mmu_disable
+ set $evb=0
+ set *(unsigned long *)0xffff0024=0
+end
+
+# Show TLB entries
+define show_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ use_mon_code
+ while ($i < 0d32 )
+ set $tlb_tag = *(unsigned long*)$addr
+ set $tlb_data = *(unsigned long*)($addr + 4)
+ printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+ use_debug_dma
+end
+define itlb
+ set $itlb=0xfe000000
+ show_tlb_entries $itlb
+end
+define dtlb
+ set $dtlb=0xfe000800
+ show_tlb_entries $dtlb
+end
+
+
+# Show current task structure
+define show_current
+ set $current = $spi & 0xffffe000
+ printf "$current=0x%08lX\n",$current
+ print *(struct task_struct *)$current
+end
+
+# Show user assigned task structure
+define show_task
+ set $task = $arg0 & 0xffffe000
+ printf "$task=0x%08lX\n",$task
+ print *(struct task_struct *)$task
+end
+document show_task
+ Show user assigned task structure
+ arg0 : task structure address
+end
+
+# Show M32R registers
+define show_regs
+ printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
+ printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
+ printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
+ printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$fp
+ printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
+ printf "EVB[0x%08lX]\n",$evb
+end
+
+
+# Setup all
+define setup
+ use_mon_code
+ set *(unsigned int)0xfffffffc=0x60
+ shell sleep 0.1
+# clock_init_on_1411
+ clock_init_on_1421
+# clock_init_on_1821
+# clock_init_on_1841
+# clock_init_on_11681
+# clock_init_off
+ shell sleep 0.1
+ port_init
+ sdram_init
+ lanc_init
+ dispc_init
+ set $evb=0x08000000
+end
+
+# Load modules
+define load_modules
+ use_debug_dma
+ load
+# load ramdisk_082a0000.mot
+# load romfs_082a0000.mot
+# use_mon_code
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x08002000
+ # INITRD_START
+# set *(unsigned long *)($param + 0x0010) = 0x082a0000
+ # INITRD_SIZE
+ set *(unsigned long *)($param + 0x0014) = 0x00000000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d160000000
+# set *(unsigned long *)($param + 0x0018) = 0d80000000
+# set *(unsigned long *)($param + 0x0018) = 0d40000000
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d40000000
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+ set {char[0x200]}($param + 0x100) = "console=tty1 console=ttyD0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.x nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
+# set {char[0x200]}($param + 0x100) = "console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.x nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
+end
+
+# Boot
+define boot
+ set_kernel_parameters
+ set $pc=0x08001000
+ set *(unsigned char *)0x08001003=0x03
+ si
+ c
+end
+
+# Set breakpoints
+define set_breakpoints
+ b *0x08000030
+end
+
+## Boot MP
+define boot_mp
+ set_kernel_parameters
+ set *(unsigned long *)0x00f00000 = boot - 0x80000000
+ set *(unsigned long *)0x00eff2f8 = 0x2
+ x 0x00eff2f8
+
+ set $pc=0x08001000
+ si
+ c
+end
+document boot_mp
+ Boot BSP
+end
+
+## Boot UP
+define boot_up
+ set_kernel_parameters
+ set $pc=0x08001000
+ si
+ c
+end
+document boot_up
+ Boot BSP
+end
+
+# Restart
+define restart
+ sdireset
+ sdireset
+ setup
+ load_modules
+ boot_mp
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+setup
--- /dev/null
+#
+# Makefile for the Linux M32R-specific parts of the memory manager.
+#
+
+ifdef CONFIG_MMU
+obj-y := init.o fault.o mmu.o extable.o ioremap.o cache.o page.o
+else
+obj-y := init.o fault-nommu.o mmu.o extable.o ioremap-nommu.o cache.o page.o
+endif
+
+obj-$(CONFIG_DISCONTIGMEM) += discontig.o
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/cache.c
+ *
+ * Copyright (C) 2002 Hirokazu Takata
+ */
+
+/* $Id$ */
+
+#include <linux/config.h>
+#include <asm/pgtable.h>
+
+#undef MCCR
+
+#if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP)
+/* Cache Control Register */
+#define MCCR ((volatile unsigned long*)0xfffffffc)
+#define MCCR_CC (1UL << 7) /* Cache mode modify bit */
+#define MCCR_IIV (1UL << 6) /* I-cache invalidate */
+#define MCCR_DIV (1UL << 5) /* D-cache invalidate */
+#define MCCR_DCB (1UL << 4) /* D-cache copy back */
+#define MCCR_ICM (1UL << 1) /* I-cache mode [0:off,1:on] */
+#define MCCR_DCM (1UL << 0) /* D-cache mode [0:off,1:on] */
+#define MCCR_ICACHE_INV (MCCR_CC|MCCR_IIV)
+#define MCCR_DCACHE_CB (MCCR_CC|MCCR_DCB)
+#define MCCR_DCACHE_CBINV (MCCR_CC|MCCR_DIV|MCCR_DCB)
+#define CHECK_MCCR(mccr) (mccr = *MCCR)
+#elif defined(CONFIG_CHIP_M32102)
+#define MCCR ((volatile unsigned long*)0xfffffffc)
+#define MCCR_IIV (1UL << 8) /* I-cache invalidate */
+#define MCCR_ICACHE_INV MCCR_IIV
+#endif /* CONFIG_CHIP_XNUX2 || CONFIG_CHIP_M32700 */
+
+#ifndef MCCR
+#error Unknown cache type.
+#endif
+
+
+/* Copy back and invalidate D-cache and invalidate I-cache all */
+void _flush_cache_all(void)
+{
+#if defined(CONFIG_CHIP_M32102)
+ *MCCR = MCCR_ICACHE_INV;
+#else
+ unsigned long mccr;
+
+ /* Copyback and invalidate D-cache */
+ /* Invalidate I-cache */
+ *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV;
+ while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
+#endif
+}
+
+/* Copy back D-cache and invalidate I-cache all */
+void _flush_cache_copyback_all(void)
+{
+#if defined(CONFIG_CHIP_M32102)
+ *MCCR = MCCR_ICACHE_INV;
+#else
+ unsigned long mccr;
+
+ /* Copyback D-cache */
+ /* Invalidate I-cache */
+ *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB;
+ while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
+
+#endif
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/discontig.c
+ *
+ * Discontig memory support
+ *
+ * Copyright (c) 2003 Hitoshi Yamamoto
+ */
+
+#include <linux/config.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/mmzone.h>
+#include <linux/initrd.h>
+
+#include <asm/setup.h>
+
+extern char _end[];
+
+struct pglist_data *node_data[MAX_NUMNODES];
+static bootmem_data_t node_bdata[MAX_NUMNODES] __initdata;
+
+pg_data_t m32r_node_data[MAX_NUMNODES];
+
+/* Memory profile */
+typedef struct {
+ unsigned long start_pfn;
+ unsigned long pages;
+ unsigned long holes;
+ unsigned long free_pfn;
+} mem_prof_t;
+static mem_prof_t mem_prof[MAX_NUMNODES];
+
+static void __init mem_prof_init(void)
+{
+ unsigned long start_pfn, holes, free_pfn;
+ const unsigned long zone_alignment = 1UL << (MAX_ORDER - 1);
+ unsigned long ul;
+ mem_prof_t *mp;
+
+ /* Node#0 SDRAM */
+ mp = &mem_prof[0];
+ mp->start_pfn = PFN_UP(CONFIG_MEMORY_START);
+ mp->pages = PFN_DOWN(CONFIG_MEMORY_SIZE);
+ mp->holes = 0;
+ mp->free_pfn = PFN_UP(__pa(_end));
+
+ /* Node#1 internal SRAM */
+ mp = &mem_prof[1];
+ start_pfn = free_pfn = PFN_UP(CONFIG_IRAM_START);
+ holes = 0;
+ if (start_pfn & (zone_alignment - 1)) {
+ ul = zone_alignment;
+ while (start_pfn >= ul)
+ ul += zone_alignment;
+
+ start_pfn = ul - zone_alignment;
+ holes = free_pfn - start_pfn;
+ }
+
+ mp->start_pfn = start_pfn;
+ mp->pages = PFN_DOWN(CONFIG_IRAM_SIZE) + holes;
+ mp->holes = holes;
+ mp->free_pfn = PFN_UP(CONFIG_IRAM_START);
+}
+
+unsigned long __init setup_memory(void)
+{
+ unsigned long bootmap_size;
+ unsigned long min_pfn;
+ int nid;
+ mem_prof_t *mp;
+
+ max_low_pfn = 0;
+ min_low_pfn = -1;
+
+ mem_prof_init();
+
+ for (nid = 0 ; nid < numnodes ; nid++) {
+ mp = &mem_prof[nid];
+ NODE_DATA(nid)=(pg_data_t *)&m32r_node_data[nid];
+ NODE_DATA(nid)->bdata = &node_bdata[nid];
+ min_pfn = mp->start_pfn;
+ max_pfn = mp->start_pfn + mp->pages;
+ bootmap_size = init_bootmem_node(NODE_DATA(nid), mp->free_pfn,
+ mp->start_pfn, max_pfn);
+
+ free_bootmem_node(NODE_DATA(nid), PFN_PHYS(mp->start_pfn),
+ PFN_PHYS(mp->pages));
+
+ reserve_bootmem_node(NODE_DATA(nid), PFN_PHYS(mp->start_pfn),
+ PFN_PHYS(mp->free_pfn - mp->start_pfn) + bootmap_size);
+
+ if (max_low_pfn < max_pfn)
+ max_low_pfn = max_pfn;
+
+ if (min_low_pfn > min_pfn)
+ min_low_pfn = min_pfn;
+ }
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (LOADER_TYPE && INITRD_START) {
+ if (INITRD_START + INITRD_SIZE <= PFN_PHYS(max_low_pfn)) {
+ reserve_bootmem_node(NODE_DATA(0), INITRD_START,
+ INITRD_SIZE);
+ initrd_start = INITRD_START ?
+ INITRD_START + PAGE_OFFSET : 0;
+
+ initrd_end = initrd_start + INITRD_SIZE;
+ printk("initrd:start[%08lx],size[%08lx]\n",
+ initrd_start, INITRD_SIZE);
+ } else {
+ printk("initrd extends beyond end of memory "
+ "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
+ INITRD_START + INITRD_SIZE,
+ PFN_PHYS(max_low_pfn));
+
+ initrd_start = 0;
+ }
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ return max_low_pfn;
+}
+
+#define START_PFN(nid) \
+ (NODE_DATA(nid)->bdata->node_boot_start >> PAGE_SHIFT)
+#define MAX_LOW_PFN(nid) (NODE_DATA(nid)->bdata->node_low_pfn)
+
+unsigned long __init zone_sizes_init(void)
+{
+ unsigned long zones_size[MAX_NR_ZONES], zholes_size[MAX_NR_ZONES];
+ unsigned long low, start_pfn;
+ unsigned long holes = 0;
+ int nid, i;
+ mem_prof_t *mp;
+
+ pgdat_list = NULL;
+ for (nid = numnodes - 1 ; nid >= 0 ; nid--) {
+ NODE_DATA(nid)->pgdat_next = pgdat_list;
+ pgdat_list = NODE_DATA(nid);
+ }
+
+ for (nid = 0 ; nid < numnodes ; nid++) {
+ mp = &mem_prof[nid];
+ for (i = 0 ; i < MAX_NR_ZONES ; i++) {
+ zones_size[i] = 0;
+ zholes_size[i] = 0;
+ }
+ start_pfn = START_PFN(nid);
+ low = MAX_LOW_PFN(nid);
+ zones_size[ZONE_DMA] = low - start_pfn;
+ zholes_size[ZONE_DMA] = mp->holes;
+ holes += zholes_size[ZONE_DMA];
+
+ free_area_init_node(nid, NODE_DATA(nid), zones_size,
+ start_pfn, zholes_size);
+ }
+
+ /*
+ * For test
+ * Use all area of internal RAM.
+ * see __alloc_pages()
+ */
+ NODE_DATA(1)->node_zones->pages_min = 0;
+ NODE_DATA(1)->node_zones->pages_low = 0;
+ NODE_DATA(1)->node_zones->pages_high = 0;
+
+ return holes;
+}
+
--- /dev/null
+/*
+ * linux/arch/i386/mm/extable.c
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <asm/uaccess.h>
+
+int fixup_exception(struct pt_regs *regs)
+{
+ const struct exception_table_entry *fixup;
+
+ fixup = search_exception_tables(regs->bpc);
+ if (fixup) {
+ regs->bpc = fixup->fixup;
+ return 1;
+ }
+
+ return 0;
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/fault.c
+ *
+ * Copyright (c) 2001, 2002 Hitoshi Yamamoto, and H. Kondo
+ *
+ * Some code taken from i386 version.
+ * Copyright (C) 1995 Linus Torvalds
+ */
+
+/* $Id: fault-nommu.c,v 1.1 2004/03/30 06:40:59 sakugawa Exp $ */
+
+#include <linux/config.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+
+#include <asm/m32r.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
+#include <asm/hardirq.h>
+#include <asm/mmu_context.h>
+
+extern void die(const char *, struct pt_regs *, long);
+
+#ifndef CONFIG_SMP
+asmlinkage unsigned int tlb_entry_i_dat;
+asmlinkage unsigned int tlb_entry_d_dat;
+#define tlb_entry_i tlb_entry_i_dat
+#define tlb_entry_d tlb_entry_d_dat
+#else
+unsigned int tlb_entry_i_dat[NR_CPUS];
+unsigned int tlb_entry_d_dat[NR_CPUS];
+#define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
+#define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
+#endif
+
+/*
+ * Unlock any spinlocks which will prevent us from getting the
+ * message out
+ */
+void bust_spinlocks(int yes)
+{
+ int loglevel_save = console_loglevel;
+
+ if (yes) {
+ oops_in_progress = 1;
+ return;
+ }
+#ifdef CONFIG_VT
+ unblank_screen();
+#endif
+ oops_in_progress = 0;
+ /*
+ * OK, the message is on the console. Now we call printk()
+ * without oops_in_progress set so that printk will give klogd
+ * a poke. Hold onto your hats...
+ */
+ console_loglevel = 15; /* NMI oopser may have shut the console up */
+ printk(" ");
+ console_loglevel = loglevel_save;
+}
+
+void do_BUG(const char *file, int line)
+{
+ bust_spinlocks(1);
+ printk("kernel BUG at %s:%d!\n", file, line);
+}
+
+/*======================================================================*
+ * do_page_fault()
+ *======================================================================*
+ * This routine handles page faults. It determines the address,
+ * and the problem, and then passes it off to one of the appropriate
+ * routines.
+ *
+ * ARGUMENT:
+ * regs : M32R SP reg.
+ * error_code : See below
+ * address : M32R MMU MDEVA reg. (Operand ACE)
+ * : M32R BPC reg. (Instruction ACE)
+ *
+ * error_code :
+ * bit 0 == 0 means no page found, 1 means protection fault
+ * bit 1 == 0 means read, 1 means write
+ * bit 2 == 0 means kernel, 1 means user-mode
+ *======================================================================*/
+asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
+ unsigned long address)
+{
+
+/*
+ * Oops. The kernel tried to access some bad page. We'll have to
+ * terminate things with extreme prejudice.
+ */
+
+ bust_spinlocks(1);
+
+ if (address < PAGE_SIZE)
+ printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
+ else
+ printk(KERN_ALERT "Unable to handle kernel paging request");
+ printk(" at virtual address %08lx\n",address);
+ printk(" printing bpc:\n");
+ printk(KERN_ALERT "bpc = %08lx\n", regs->bpc);
+
+ die("Oops", regs, error_code);
+ bust_spinlocks(0);
+ do_exit(SIGKILL);
+}
+
+/*======================================================================*
+ * update_mmu_cache()
+ *======================================================================*/
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+ pte_t pte)
+{
+ BUG();
+}
+
+/*======================================================================*
+ * flush_tlb_page() : flushes one page
+ *======================================================================*/
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
+{
+ BUG();
+}
+
+/*======================================================================*
+ * flush_tlb_range() : flushes a range of pages
+ *======================================================================*/
+void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+ unsigned long end)
+{
+ BUG();
+}
+
+/*======================================================================*
+ * flush_tlb_mm() : flushes the specified mm context TLB's
+ *======================================================================*/
+void local_flush_tlb_mm(struct mm_struct *mm)
+{
+ BUG();
+}
+
+/*======================================================================*
+ * flush_tlb_all() : flushes all processes TLBs
+ *======================================================================*/
+void local_flush_tlb_all(void)
+{
+ BUG();
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/fault.c
+ *
+ * Copyright (c) 2001, 2002 Hitoshi Yamamoto, and H. Kondo
+ *
+ * Some code taken from i386 version.
+ * Copyright (C) 1995 Linus Torvalds
+ */
+
+/* $Id$ */
+
+#include <linux/config.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/tty.h>
+#include <linux/vt_kern.h> /* For unblank_screen() */
+#include <linux/highmem.h>
+#include <linux/module.h>
+
+#include <asm/m32r.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/hardirq.h>
+#include <asm/mmu_context.h>
+#include <asm/tlbflush.h>
+
+extern void die(const char *, struct pt_regs *, long);
+
+#ifndef CONFIG_SMP
+asmlinkage unsigned int tlb_entry_i_dat;
+asmlinkage unsigned int tlb_entry_d_dat;
+#define tlb_entry_i tlb_entry_i_dat
+#define tlb_entry_d tlb_entry_d_dat
+#else
+unsigned int tlb_entry_i_dat[NR_CPUS];
+unsigned int tlb_entry_d_dat[NR_CPUS];
+#define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
+#define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
+#endif
+
+extern void init_tlb(void);
+
+/*
+ * Unlock any spinlocks which will prevent us from getting the
+ * message out
+ */
+void bust_spinlocks(int yes)
+{
+ int loglevel_save = console_loglevel;
+
+ if (yes) {
+ oops_in_progress = 1;
+ return;
+ }
+#ifdef CONFIG_VT
+ unblank_screen();
+#endif
+ oops_in_progress = 0;
+ /*
+ * OK, the message is on the console. Now we call printk()
+ * without oops_in_progress set so that printk will give klogd
+ * a poke. Hold onto your hats...
+ */
+ console_loglevel = 15; /* NMI oopser may have shut the console up */
+ printk(" ");
+ console_loglevel = loglevel_save;
+}
+
+/*======================================================================*
+ * do_page_fault()
+ *======================================================================*
+ * This routine handles page faults. It determines the address,
+ * and the problem, and then passes it off to one of the appropriate
+ * routines.
+ *
+ * ARGUMENT:
+ * regs : M32R SP reg.
+ * error_code : See below
+ * address : M32R MMU MDEVA reg. (Operand ACE)
+ * : M32R BPC reg. (Instruction ACE)
+ *
+ * error_code :
+ * bit 0 == 0 means no page found, 1 means protection fault
+ * bit 1 == 0 means read, 1 means write
+ * bit 2 == 0 means kernel, 1 means user-mode
+ * bit 3 == 0 means data, 1 means instruction
+ *======================================================================*/
+asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
+ unsigned long address)
+{
+ struct task_struct *tsk;
+ struct mm_struct *mm;
+ struct vm_area_struct * vma;
+ unsigned long page, addr;
+ int write;
+ siginfo_t info;
+
+ /*
+ * If BPSW IE bit enable --> set PSW IE bit
+ */
+ if (regs->psw & M32R_PSW_BIE)
+ local_irq_enable();
+
+ tsk = current;
+
+ info.si_code = SEGV_MAPERR;
+
+ /*
+ * We fault-in kernel-space virtual memory on-demand. The
+ * 'reference' page table is init_mm.pgd.
+ *
+ * NOTE! We MUST NOT take any locks for this case. We may
+ * be in an interrupt or a critical region, and should
+ * only copy the information from the master page table,
+ * nothing more.
+ *
+ * This verifies that the fault happens in kernel space
+ * (error_code & 4) == 0, and that the fault was not a
+ * protection error (error_code & 1) == 0.
+ */
+ if (address >= TASK_SIZE && !(error_code & 4))
+ goto vmalloc_fault;
+
+ mm = tsk->mm;
+
+ /*
+ * If we're in an interrupt or have no user context or are running in an
+ * atomic region then we must not take the fault..
+ */
+ if (in_atomic() || !mm)
+ goto bad_area_nosemaphore;
+
+ /* When running in the kernel we expect faults to occur only to
+ * addresses in user space. All other faults represent errors in the
+ * kernel and should generate an OOPS. Unfortunatly, in the case of an
+ * erroneous fault occuring in a code path which already holds mmap_sem
+ * we will deadlock attempting to validate the fault against the
+ * address space. Luckily the kernel only validly references user
+ * space from well defined areas of code, which are listed in the
+ * exceptions table.
+ *
+ * As the vast majority of faults will be valid we will only perform
+ * the source reference check when there is a possibilty of a deadlock.
+ * Attempt to lock the address space, if we cannot we then validate the
+ * source. If this is invalid we can skip the address space check,
+ * thus avoiding the deadlock.
+ */
+ if (!down_read_trylock(&mm->mmap_sem)) {
+ if ((error_code & 4) == 0 &&
+ !search_exception_tables(regs->psw))
+ goto bad_area_nosemaphore;
+ down_read(&mm->mmap_sem);
+ }
+
+ vma = find_vma(mm, address);
+ if (!vma)
+ goto bad_area;
+ if (vma->vm_start <= address)
+ goto good_area;
+ if (!(vma->vm_flags & VM_GROWSDOWN))
+ goto bad_area;
+#if 0
+ if (error_code & 4) {
+ /*
+ * accessing the stack below "spu" is always a bug.
+ * The "+ 4" is there due to the push instruction
+ * doing pre-decrement on the stack and that
+ * doesn't show up until later..
+ */
+ if (address + 4 < regs->spu)
+ goto bad_area;
+ }
+#endif
+ if (expand_stack(vma, address))
+ goto bad_area;
+/*
+ * Ok, we have a good vm_area for this memory access, so
+ * we can handle it..
+ */
+good_area:
+ info.si_code = SEGV_ACCERR;
+ write = 0;
+ switch (error_code & 3) {
+ default: /* 3: write, present */
+ /* fall through */
+ case 2: /* write, not present */
+ if (!(vma->vm_flags & VM_WRITE))
+ goto bad_area;
+ write++;
+ break;
+ case 1: /* read, present */
+ case 0: /* read, not present */
+ if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
+ goto bad_area;
+ }
+
+survive:
+ /*
+ * If for any reason at all we couldn't handle the fault,
+ * make sure we exit gracefully rather than endlessly redo
+ * the fault.
+ */
+ addr = (address & PAGE_MASK) | (error_code & 8);
+ switch (handle_mm_fault(mm, vma, addr, write)) {
+ case VM_FAULT_MINOR:
+ tsk->min_flt++;
+ break;
+ case VM_FAULT_MAJOR:
+ tsk->maj_flt++;
+ break;
+ case VM_FAULT_SIGBUS:
+ goto do_sigbus;
+ case VM_FAULT_OOM:
+ goto out_of_memory;
+ default:
+ BUG();
+ }
+
+ up_read(&mm->mmap_sem);
+ return;
+
+/*
+ * Something tried to access memory that isn't in our memory map..
+ * Fix it, but check if it's kernel or user first..
+ */
+bad_area:
+ up_read(&mm->mmap_sem);
+
+bad_area_nosemaphore:
+ /* User mode accesses just cause a SIGSEGV */
+ if (error_code & 4) {
+ tsk->thread.address = address;
+ tsk->thread.error_code = error_code | (address >= TASK_SIZE);
+ tsk->thread.trap_no = 14;
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ /* info.si_code has been set above */
+ info.si_addr = (void __user *)address;
+ force_sig_info(SIGSEGV, &info, tsk);
+ return;
+ }
+
+no_context:
+ /* Are we prepared to handle this kernel fault? */
+ if (fixup_exception(regs))
+ return;
+
+/*
+ * Oops. The kernel tried to access some bad page. We'll have to
+ * terminate things with extreme prejudice.
+ */
+
+ bust_spinlocks(1);
+
+ if (address < PAGE_SIZE)
+ printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
+ else
+ printk(KERN_ALERT "Unable to handle kernel paging request");
+ printk(" at virtual address %08lx\n",address);
+ printk(KERN_ALERT " printing bpc:\n");
+ printk("%08lx\n", regs->bpc);
+ page = *(unsigned long *)MPTB;
+ page = ((unsigned long *) page)[address >> PGDIR_SHIFT];
+ printk(KERN_ALERT "*pde = %08lx\n", page);
+ if (page & _PAGE_PRESENT) {
+ page &= PAGE_MASK;
+ address &= 0x003ff000;
+ page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
+ printk(KERN_ALERT "*pte = %08lx\n", page);
+ }
+ die("Oops", regs, error_code);
+ bust_spinlocks(0);
+ do_exit(SIGKILL);
+
+/*
+ * We ran out of memory, or some other thing happened to us that made
+ * us unable to handle the page fault gracefully.
+ */
+out_of_memory:
+ up_read(&mm->mmap_sem);
+ if (tsk->pid == 1) {
+ yield();
+ down_read(&mm->mmap_sem);
+ goto survive;
+ }
+ printk("VM: killing process %s\n", tsk->comm);
+ if (error_code & 4)
+ do_exit(SIGKILL);
+ goto no_context;
+
+do_sigbus:
+ up_read(&mm->mmap_sem);
+
+ /* Kernel mode? Handle exception or die */
+ if (!(error_code & 4))
+ goto no_context;
+
+ tsk->thread.address = address;
+ tsk->thread.error_code = error_code;
+ tsk->thread.trap_no = 14;
+ info.si_signo = SIGBUS;
+ info.si_errno = 0;
+ info.si_code = BUS_ADRERR;
+ info.si_addr = (void __user *)address;
+ force_sig_info(SIGBUS, &info, tsk);
+ return;
+
+vmalloc_fault:
+ {
+ /*
+ * Synchronize this task's top level page-table
+ * with the 'reference' page table.
+ *
+ * Do _not_ use "tsk" here. We might be inside
+ * an interrupt in the middle of a task switch..
+ */
+ int offset = pgd_index(address);
+ pgd_t *pgd, *pgd_k;
+ pmd_t *pmd, *pmd_k;
+ pte_t *pte_k;
+
+ pgd = (pgd_t *)*(unsigned long *)MPTB;
+ pgd = offset + (pgd_t *)pgd;
+ pgd_k = init_mm.pgd + offset;
+
+ if (!pgd_present(*pgd_k))
+ goto no_context;
+
+ /*
+ * set_pgd(pgd, *pgd_k); here would be useless on PAE
+ * and redundant with the set_pmd() on non-PAE.
+ */
+
+ pmd = pmd_offset(pgd, address);
+ pmd_k = pmd_offset(pgd_k, address);
+ if (!pmd_present(*pmd_k))
+ goto no_context;
+ set_pmd(pmd, *pmd_k);
+
+ pte_k = pte_offset_kernel(pmd_k, address);
+ if (!pte_present(*pte_k))
+ goto no_context;
+
+ addr = (address & PAGE_MASK) | (error_code & 8);
+ update_mmu_cache(NULL, addr, *pte_k);
+ return;
+ }
+}
+
+/*======================================================================*
+ * update_mmu_cache()
+ *======================================================================*/
+#define TLB_MASK (NR_TLB_ENTRIES - 1)
+#define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
+#define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
+ pte_t pte)
+{
+ unsigned long *entry1, *entry2;
+ unsigned long pte_data, flags;
+ unsigned int *entry_dat;
+ int inst = vaddr & 8;
+ int i;
+
+ /* Ptrace may call this routine. */
+ if (vma && current->active_mm != vma->vm_mm)
+ return;
+
+ local_irq_save(flags);
+
+ vaddr = (vaddr & PAGE_MASK) | get_asid();
+
+#ifdef CONFIG_CHIP_OPSP
+ entry1 = (unsigned long *)ITLB_BASE;
+ for(i = 0 ; i < NR_TLB_ENTRIES; i++) {
+ if(*entry1++ == vaddr) {
+ pte_data = pte_val(pte);
+ set_tlb_data(entry1, pte_data);
+ break;
+ }
+ entry1++;
+ }
+ entry2 = (unsigned long *)DTLB_BASE;
+ for(i = 0 ; i < NR_TLB_ENTRIES ; i++) {
+ if(*entry2++ == vaddr) {
+ pte_data = pte_val(pte);
+ set_tlb_data(entry2, pte_data);
+ break;
+ }
+ entry2++;
+ }
+ local_irq_restore(flags);
+ return;
+#else
+ pte_data = pte_val(pte);
+
+ /*
+ * Update TLB entries
+ * entry1: ITLB entry address
+ * entry2: DTLB entry address
+ */
+ __asm__ __volatile__ (
+ "seth %0, #high(%4) \n\t"
+ "st %2, @(%5, %0) \n\t"
+ "ldi %1, #1 \n\t"
+ "st %1, @(%6, %0) \n\t"
+ "add3 r4, %0, %7 \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "ld %1, @(%6, %0) \n\t"
+ "bnez %1, 1b \n\t"
+ "ld %0, @r4+ \n\t"
+ "ld %1, @r4 \n\t"
+ "st %3, @+%0 \n\t"
+ "st %3, @+%1 \n\t"
+ : "=&r" (entry1), "=&r" (entry2)
+ : "r" (vaddr), "r" (pte_data), "i" (MMU_REG_BASE),
+ "i" (MSVA_offset), "i" (MTOP_offset), "i" (MIDXI_offset)
+ : "r4", "memory"
+ );
+
+ if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END))
+ goto notfound;
+
+found:
+ local_irq_restore(flags);
+
+ return;
+
+ /* Valid entry not found */
+notfound:
+ /*
+ * Update ITLB or DTLB entry
+ * entry1: TLB entry address
+ * entry2: TLB base address
+ */
+ if (!inst) {
+ entry2 = (unsigned long *)DTLB_BASE;
+ entry_dat = &tlb_entry_d;
+ } else {
+ entry2 = (unsigned long *)ITLB_BASE;
+ entry_dat = &tlb_entry_i;
+ }
+ entry1 = entry2 + (((*entry_dat - 1) & TLB_MASK) << 1);
+
+ for (i = 0 ; i < NR_TLB_ENTRIES ; i++) {
+ if (!(entry1[1] & 2)) /* Valid bit check */
+ break;
+
+ if (entry1 != entry2)
+ entry1 -= 2;
+ else
+ entry1 += TLB_MASK << 1;
+ }
+
+ if (i >= NR_TLB_ENTRIES) { /* Empty entry not found */
+ entry1 = entry2 + (*entry_dat << 1);
+ *entry_dat = (*entry_dat + 1) & TLB_MASK;
+ }
+ *entry1++ = vaddr; /* Set TLB tag */
+ set_tlb_data(entry1, pte_data);
+
+ goto found;
+#endif
+}
+
+/*======================================================================*
+ * flush_tlb_page() : flushes one page
+ *======================================================================*/
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
+{
+ if (vma->vm_mm && mm_context(vma->vm_mm) != NO_CONTEXT) {
+ unsigned long flags;
+
+ local_irq_save(flags);
+ page &= PAGE_MASK;
+ page |= (mm_context(vma->vm_mm) & MMU_CONTEXT_ASID_MASK);
+ __flush_tlb_page(page);
+ local_irq_restore(flags);
+ }
+}
+
+/*======================================================================*
+ * flush_tlb_range() : flushes a range of pages
+ *======================================================================*/
+void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+ unsigned long end)
+{
+ struct mm_struct *mm;
+
+ mm = vma->vm_mm;
+ if (mm_context(mm) != NO_CONTEXT) {
+ unsigned long flags;
+ int size;
+
+ local_irq_save(flags);
+ size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+ if (size > (NR_TLB_ENTRIES / 4)) { /* Too many TLB to flush */
+ mm_context(mm) = NO_CONTEXT;
+ if (mm == current->mm)
+ activate_context(mm);
+ } else {
+ unsigned long asid;
+
+ asid = mm_context(mm) & MMU_CONTEXT_ASID_MASK;
+ start &= PAGE_MASK;
+ end += (PAGE_SIZE - 1);
+ end &= PAGE_MASK;
+
+ start |= asid;
+ end |= asid;
+ while (start < end) {
+ __flush_tlb_page(start);
+ start += PAGE_SIZE;
+ }
+ }
+ local_irq_restore(flags);
+ }
+}
+
+/*======================================================================*
+ * flush_tlb_mm() : flushes the specified mm context TLB's
+ *======================================================================*/
+void local_flush_tlb_mm(struct mm_struct *mm)
+{
+ /* Invalidate all TLB of this process. */
+ /* Instead of invalidating each TLB, we get new MMU context. */
+ if (mm_context(mm) != NO_CONTEXT) {
+ unsigned long flags;
+
+ local_irq_save(flags);
+ mm_context(mm) = NO_CONTEXT;
+ if (mm == current->mm)
+ activate_context(mm);
+ local_irq_restore(flags);
+ }
+}
+
+/*======================================================================*
+ * flush_tlb_all() : flushes all processes TLBs
+ *======================================================================*/
+void local_flush_tlb_all(void)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ __flush_tlb_all();
+ local_irq_restore(flags);
+}
+
+/*======================================================================*
+ * init_mmu()
+ *======================================================================*/
+void __init init_mmu(void)
+{
+ tlb_entry_i = 0;
+ tlb_entry_d = 0;
+ mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
+ set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
+ *(volatile unsigned long *)MPTB = (unsigned long)swapper_pg_dir;
+}
--- /dev/null
+/*
+ * linux/arch/m32r/mm/init.c
+ *
+ * Copyright (c) 2001, 2002 Hitoshi Yamamoto
+ *
+ * Some code taken from sh version.
+ * Copyright (C) 1999 Niibe Yutaka
+ * Based on linux/arch/i386/mm/init.c:
+ * Copyright (C) 1995 Linus Torvalds
+ */
+
+/* $Id$ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+#include <linux/bootmem.h>
+#include <linux/swap.h>
+#include <linux/highmem.h>
+#include <asm/types.h>
+#include <asm/processor.h>
+#include <asm/bitops.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/mmu_context.h>
+#include <asm/setup.h>
+#include <asm/tlb.h>
+
+/* References to section boundaries */
+extern char _text, _etext, _edata;
+extern char __init_begin, __init_end;
+
+pgd_t swapper_pg_dir[1024];
+
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+void show_mem(void)
+{
+ int total = 0, reserved = 0;
+ int shared = 0, cached = 0;
+ int highmem = 0;
+ struct page *page;
+ pg_data_t *pgdat;
+ unsigned long i;
+
+ printk("Mem-info:\n");
+ show_free_areas();
+ printk("Free swap: %6ldkB\n",nr_swap_pages<<(PAGE_SHIFT-10));
+ for_each_pgdat(pgdat) {
+ for (i = 0; i < pgdat->node_spanned_pages; ++i) {
+ page = pgdat->node_mem_map + i;
+ total++;
+ if (PageHighMem(page))
+ highmem++;
+ if (PageReserved(page))
+ reserved++;
+ else if (PageSwapCache(page))
+ cached++;
+ else if (page_count(page))
+ shared += page_count(page) - 1;
+ }
+ }
+ printk("%d pages of RAM\n", total);
+ printk("%d pages of HIGHMEM\n",highmem);
+ printk("%d reserved pages\n",reserved);
+ printk("%d pages shared\n",shared);
+ printk("%d pages swap cached\n",cached);
+}
+
+/*
+ * Cache of MMU context last used.
+ */
+#ifndef CONFIG_SMP
+unsigned long mmu_context_cache_dat;
+#else
+unsigned long mmu_context_cache_dat[NR_CPUS];
+#endif
+static unsigned long hole_pages;
+
+/*
+ * function prototype
+ */
+void __init paging_init(void);
+void __init mem_init(void);
+void free_initmem(void);
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long, unsigned long);
+#endif
+
+/* It'd be good if these lines were in the standard header file. */
+#define START_PFN(nid) \
+ (NODE_DATA(nid)->bdata->node_boot_start >> PAGE_SHIFT)
+#define MAX_LOW_PFN(nid) (NODE_DATA(nid)->bdata->node_low_pfn)
+
+#ifndef CONFIG_DISCONTIGMEM
+unsigned long __init zone_sizes_init(void)
+{
+ unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
+ unsigned long max_dma;
+ unsigned long low;
+ unsigned long start_pfn;
+
+#ifdef CONFIG_MMU
+ start_pfn = START_PFN(0);
+ max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
+ low = MAX_LOW_PFN(0);
+
+ if (low < max_dma){
+ zones_size[ZONE_DMA] = low - start_pfn;
+ zones_size[ZONE_NORMAL] = 0;
+ } else {
+ zones_size[ZONE_DMA] = low - start_pfn;
+ zones_size[ZONE_NORMAL] = low - max_dma;
+ }
+#else
+ zones_size[ZONE_DMA] = 0 >> PAGE_SHIFT;
+ zones_size[ZONE_NORMAL] = __MEMORY_SIZE >> PAGE_SHIFT;
+ start_pfn = __MEMORY_START >> PAGE_SHIFT;
+#endif /* CONFIG_MMU */
+
+ free_area_init_node(0, NODE_DATA(0), zones_size, start_pfn, 0);
+
+ mem_map = contig_page_data.node_mem_map;
+
+ return 0;
+}
+#else /* CONFIG_DISCONTIGMEM */
+extern unsigned long zone_sizes_init(void);
+#endif /* CONFIG_DISCONTIGMEM */
+
+/*======================================================================*
+ * paging_init() : sets up the page tables
+ *======================================================================*/
+void __init paging_init(void)
+{
+#ifdef CONFIG_MMU
+ int i;
+ pgd_t *pg_dir;
+
+ /* We don't need kernel mapping as hardware support that. */
+ pg_dir = swapper_pg_dir;
+
+ for (i = 0 ; i < USER_PTRS_PER_PGD * 2 ; i++)
+ pgd_val(pg_dir[i]) = 0;
+#endif /* CONFIG_MMU */
+ hole_pages = zone_sizes_init();
+}
+
+int __init reservedpages_count(void)
+{
+ int reservedpages, nid, i;
+
+ reservedpages = 0;
+ for (nid = 0 ; nid < numnodes ; nid++)
+ for (i = 0 ; i < MAX_LOW_PFN(nid) - START_PFN(nid) ; i++)
+ if (PageReserved(NODE_DATA(nid)->node_mem_map + i))
+ reservedpages++;
+
+ return reservedpages;
+}
+
+/*======================================================================*
+ * mem_init() :
+ * orig : arch/sh/mm/init.c
+ *======================================================================*/
+void __init mem_init(void)
+{
+ int codesize, reservedpages, datasize, initsize;
+ int nid;
+#ifndef CONFIG_MMU
+ extern unsigned long memory_end;
+#endif
+
+ num_physpages = 0;
+ for (nid = 0 ; nid < numnodes ; nid++)
+ num_physpages += MAX_LOW_PFN(nid) - START_PFN(nid) + 1;
+
+ num_physpages -= hole_pages;
+
+#ifndef CONFIG_DISCONTIGMEM
+ max_mapnr = num_physpages;
+#endif /* CONFIG_DISCONTIGMEM */
+
+#ifdef CONFIG_MMU
+ high_memory = (void *)__va(PFN_PHYS(MAX_LOW_PFN(0)));
+#else
+ high_memory = (void *)(memory_end & PAGE_MASK);
+#endif /* CONFIG_MMU */
+
+ /* clear the zero-page */
+ memset(empty_zero_page, 0, PAGE_SIZE);
+
+ /* this will put all low memory onto the freelists */
+ for (nid = 0 ; nid < numnodes ; nid++)
+ totalram_pages += free_all_bootmem_node(NODE_DATA(nid));
+
+ reservedpages = reservedpages_count() - hole_pages;
+ codesize = (unsigned long) &_etext - (unsigned long)&_text;
+ datasize = (unsigned long) &_edata - (unsigned long)&_etext;
+ initsize = (unsigned long) &__init_end - (unsigned long)&__init_begin;
+
+ printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, "
+ "%dk reserved, %dk data, %dk init)\n",
+ (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
+ num_physpages << (PAGE_SHIFT-10),
+ codesize >> 10,
+ reservedpages << (PAGE_SHIFT-10),
+ datasize >> 10,
+ initsize >> 10);
+}
+
+/*======================================================================*
+ * free_initmem() :
+ * orig : arch/sh/mm/init.c
+ *======================================================================*/
+void free_initmem(void)
+{
+ unsigned long addr;
+
+ addr = (unsigned long)(&__init_begin);
+ for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
+ ClearPageReserved(virt_to_page(addr));
+ set_page_count(virt_to_page(addr), 1);
+ free_page(addr);
+ totalram_pages++;
+ }
+ printk (KERN_INFO "Freeing unused kernel memory: %dk freed\n", \
+ (int)(&__init_end - &__init_begin) >> 10);
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+/*======================================================================*
+ * free_initrd_mem() :
+ * orig : arch/sh/mm/init.c
+ *======================================================================*/
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+ unsigned long p;
+ for (p = start; p < end; p += PAGE_SIZE) {
+ ClearPageReserved(virt_to_page(p));
+ set_page_count(virt_to_page(p), 1);
+ free_page(p);
+ totalram_pages++;
+ }
+ printk (KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+}
+#endif
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/ioremap-nommu.c
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo
+ *
+ * Taken from mips version.
+ * (C) Copyright 1995 1996 Linus Torvalds
+ * (C) Copyright 2001 Ralf Baechle
+ */
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <linux/vmalloc.h>
+#include <asm/io.h>
+#include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+
+/*
+ * Remap an arbitrary physical address space into the kernel virtual
+ * address space. Needed when the kernel wants to access high addresses
+ * directly.
+ *
+ * NOTE! We need to allow non-page-aligned mappings too: we will obviously
+ * have to convert them into an offset in a page-aligned mapping, but the
+ * caller shouldn't need to know that small detail.
+ */
+
+#define IS_LOW512(addr) (!((unsigned long)(addr) & ~0x1fffffffUL))
+
+void __iomem *
+__ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
+{
+ return (void *)phys_addr;
+}
+
+#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1)
+
+void iounmap(volatile void __iomem *addr)
+{
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/ioremap.c
+ *
+ * Copyright (c) 2001, 2002 Hiroyuki Kondo
+ *
+ * Taken from mips version.
+ * (C) Copyright 1995 1996 Linus Torvalds
+ * (C) Copyright 2001 Ralf Baechle
+ */
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <linux/vmalloc.h>
+#include <asm/io.h>
+#include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+static inline void
+remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
+ unsigned long phys_addr, unsigned long flags)
+{
+ unsigned long end;
+ unsigned long pfn;
+ pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_READ
+ | _PAGE_WRITE | flags);
+
+ address &= ~PMD_MASK;
+ end = address + size;
+ if (end > PMD_SIZE)
+ end = PMD_SIZE;
+ if (address >= end)
+ BUG();
+ pfn = phys_addr >> PAGE_SHIFT;
+ do {
+ if (!pte_none(*pte)) {
+ printk("remap_area_pte: page already exists\n");
+ BUG();
+ }
+ set_pte(pte, pfn_pte(pfn, pgprot));
+ address += PAGE_SIZE;
+ pfn++;
+ pte++;
+ } while (address && (address < end));
+}
+
+static inline int
+remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size,
+ unsigned long phys_addr, unsigned long flags)
+{
+ unsigned long end;
+
+ address &= ~PGDIR_MASK;
+ end = address + size;
+ if (end > PGDIR_SIZE)
+ end = PGDIR_SIZE;
+ phys_addr -= address;
+ if (address >= end)
+ BUG();
+ do {
+ pte_t * pte = pte_alloc_kernel(&init_mm, pmd, address);
+ if (!pte)
+ return -ENOMEM;
+ remap_area_pte(pte, address, end - address, address + phys_addr, flags);
+ address = (address + PMD_SIZE) & PMD_MASK;
+ pmd++;
+ } while (address && (address < end));
+ return 0;
+}
+
+static int
+remap_area_pages(unsigned long address, unsigned long phys_addr,
+ unsigned long size, unsigned long flags)
+{
+ int error;
+ pgd_t * dir;
+ unsigned long end = address + size;
+
+ phys_addr -= address;
+ dir = pgd_offset(&init_mm, address);
+ flush_cache_all();
+ if (address >= end)
+ BUG();
+ spin_lock(&init_mm.page_table_lock);
+ do {
+ pmd_t *pmd;
+ pmd = pmd_alloc(&init_mm, dir, address);
+ error = -ENOMEM;
+ if (!pmd)
+ break;
+ if (remap_area_pmd(pmd, address, end - address,
+ phys_addr + address, flags))
+ break;
+ error = 0;
+ address = (address + PGDIR_SIZE) & PGDIR_MASK;
+ dir++;
+ } while (address && (address < end));
+ spin_unlock(&init_mm.page_table_lock);
+ flush_tlb_all();
+ return error;
+}
+
+/*
+ * Generic mapping function (not visible outside):
+ */
+
+/*
+ * Remap an arbitrary physical address space into the kernel virtual
+ * address space. Needed when the kernel wants to access high addresses
+ * directly.
+ *
+ * NOTE! We need to allow non-page-aligned mappings too: we will obviously
+ * have to convert them into an offset in a page-aligned mapping, but the
+ * caller shouldn't need to know that small detail.
+ */
+
+#define IS_LOW512(addr) (!((unsigned long)(addr) & ~0x1fffffffUL))
+
+void __iomem *
+__ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
+{
+ void __iomem * addr;
+ struct vm_struct * area;
+ unsigned long offset, last_addr;
+
+ /* Don't allow wraparound or zero size */
+ last_addr = phys_addr + size - 1;
+ if (!size || last_addr < phys_addr)
+ return NULL;
+
+ /*
+ * Map objects in the low 512mb of address space using KSEG1, otherwise
+ * map using page tables.
+ */
+ if (IS_LOW512(phys_addr) && IS_LOW512(phys_addr + size - 1))
+ return (void *) KSEG1ADDR(phys_addr);
+
+ /*
+ * Don't allow anybody to remap normal RAM that we're using..
+ */
+ if (phys_addr < virt_to_phys(high_memory)) {
+ char *t_addr, *t_end;
+ struct page *page;
+
+ t_addr = __va(phys_addr);
+ t_end = t_addr + (size - 1);
+
+ for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++)
+ if(!PageReserved(page))
+ return NULL;
+ }
+
+ /*
+ * Mappings have to be page-aligned
+ */
+ offset = phys_addr & ~PAGE_MASK;
+ phys_addr &= PAGE_MASK;
+ size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+
+ /*
+ * Ok, go for it..
+ */
+ area = get_vm_area(size, VM_IOREMAP);
+ if (!area)
+ return NULL;
+ area->phys_addr = phys_addr;
+ addr = (void __iomem *) area->addr;
+ if (remap_area_pages((unsigned long)addr, phys_addr, size, flags)) {
+ vunmap((void __force *) addr);
+ return NULL;
+ }
+
+ return (void __iomem *) (offset + (char __iomem *)addr);
+}
+
+#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1)
+
+void iounmap(volatile void __iomem *addr)
+{
+ if (!IS_KSEG1(addr))
+ vfree((void *) (PAGE_MASK & (unsigned long) addr));
+}
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/mmu.S
+ *
+ * Copyright (C) 2001 by Hiroyuki Kondo
+ */
+
+/* $Id: mmu.S,v 1.15 2004/03/16 02:56:27 takata Exp $ */
+
+#include <linux/config.h> /* CONFIG_MMU */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/smp.h>
+
+ .text
+#ifdef CONFIG_MMU
+
+#include <asm/mmu_context.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/m32r.h>
+
+/*
+ * TLB Miss Exception handler
+ */
+ .balign 16
+ENTRY(tme_handler)
+ .global tlb_entry_i_dat
+ .global tlb_entry_d_dat
+
+ SWITCH_TO_KERNEL_STACK
+
+#if defined(CONFIG_ISA_M32R2)
+ st r0, @-sp
+ st r1, @-sp
+ st r2, @-sp
+ st r3, @-sp
+
+ seth r3, #high(MMU_REG_BASE)
+ ld r1, @(MESTS_offset, r3) ; r1: status (MESTS reg.)
+ ld r0, @(MDEVP_offset, r3) ; r0: PFN + ASID (MDEVP reg.)
+ st r1, @(MESTS_offset, r3) ; clear status (MESTS reg.)
+ and3 r1, r1, #(MESTS_IT)
+ bnez r1, 1f ; instruction TLB miss?
+
+;; data TLB miss
+;; input
+;; r0: PFN + ASID (MDEVP reg.)
+;; r1 - r3: free
+;; output
+;; r0: PFN + ASID
+;; r1: TLB entry base address
+;; r2: &tlb_entry_{i|d}_dat
+;; r3: free
+
+#ifndef CONFIG_SMP
+ seth r2, #high(tlb_entry_d_dat)
+ or3 r2, r2, #low(tlb_entry_d_dat)
+#else /* CONFIG_SMP */
+ ldi r1, #-8192
+ seth r2, #high(tlb_entry_d_dat)
+ or3 r2, r2, #low(tlb_entry_d_dat)
+ and r1, sp
+ ld r1, @(16, r1) ; current_thread_info->cpu
+ slli r1, #2
+ add r2, r1
+#endif /* !CONFIG_SMP */
+ seth r1, #high(DTLB_BASE)
+ or3 r1, r1, #low(DTLB_BASE)
+ bra 2f
+
+ .balign 16
+ .fillinsn
+1:
+;; instrucntion TLB miss
+;; input
+;; r0: MDEVP reg. (included ASID)
+;; r1 - r3: free
+;; output
+;; r0: PFN + ASID
+;; r1: TLB entry base address
+;; r2: &tlb_entry_{i|d}_dat
+;; r3: free
+ ldi r3, #-4096
+ and3 r0, r0, #(MMU_CONTEXT_ASID_MASK)
+ mvfc r1, bpc
+ and r1, r3
+ or r0, r1 ; r0: PFN + ASID
+#ifndef CONFIG_SMP
+ seth r2, #high(tlb_entry_i_dat)
+ or3 r2, r2, #low(tlb_entry_i_dat)
+#else /* CONFIG_SMP */
+ ldi r1, #-8192
+ seth r2, #high(tlb_entry_i_dat)
+ or3 r2, r2, #low(tlb_entry_i_dat)
+ and r1, sp
+ ld r1, @(16, r1) ; current_thread_info->cpu
+ slli r1, #2
+ add r2, r1
+#endif /* !CONFIG_SMP */
+ seth r1, #high(ITLB_BASE)
+ or3 r1, r1, #low(ITLB_BASE)
+
+ .fillinsn
+2:
+;; select TLB entry
+;; input
+;; r0: PFN + ASID
+;; r1: TLB entry base address
+;; r2: &tlb_entry_{i|d}_dat
+;; r3: free
+;; output
+;; r0: PFN + ASID
+;; r1: TLB entry address
+;; r2, r3: free
+#ifdef CONFIG_ISA_DUAL_ISSUE
+ ld r3, @r2 || srli r1, #3
+#else
+ ld r3, @r2
+ srli r1, #3
+#endif
+ add r1, r3
+ ; tlb_entry_{d|i}_dat++;
+ addi r3, #1
+ and3 r3, r3, #(NR_TLB_ENTRIES - 1)
+#ifdef CONFIG_ISA_DUAL_ISSUE
+ st r3, @r2 || slli r1, #3
+#else
+ st r3, @r2
+ slli r1, #3
+#endif
+
+;; load pte
+;; input
+;; r0: PFN + ASID
+;; r1: TLB entry address
+;; r2, r3: free
+;; output
+;; r0: PFN + ASID
+;; r1: TLB entry address
+;; r2: pte_data
+;; r3: free
+ ; pgd = *(unsigned long *)MPTB;
+ ld24 r2, #(-MPTB - 1)
+ srl3 r3, r0, #22
+#ifdef CONFIG_ISA_DUAL_ISSUE
+ not r2, r2 || slli r3, #2 ; r3: pgd offset
+#else
+ not r2, r2
+ slli r3, #2
+#endif
+ ld r2, @r2 ; r2: pgd base addr (MPTB reg.)
+ or r3, r2 ; r3: pmd addr
+
+ ; pmd = pmd_offset(pgd, address);
+ ld r3, @r3 ; r3: pmd data
+ ldi r2, #-4096
+ beqz r3, 3f ; pmd_none(*pmd) ?
+
+ ; pte = pte_offset(pmd, address);
+ and r2, r3 ; r2: pte base addr
+ srl3 r3, r0, #10
+ and3 r3, r3, #0xffc ; r3: pte offset
+ or r3, r2
+ seth r2, #0x8000
+ or r3, r2 ; r3: pte addr
+
+ ; pte_data = (unsigned long)pte_val(*pte);
+ ld r2, @r3 ; r2: pte data
+ or3 r2, r2, #2 ; _PAGE_PRESENT(=2)
+
+ .fillinsn
+5:
+;; set tlb
+;; input
+;; r0: PFN + ASID
+;; r1: TLB entry address
+;; r2: pte_data
+;; r3: free
+ st r0, @r1 ; set_tlb_tag(entry++, address);
+ st r2, @+r1 ; set_tlb_data(entry, pte_data);
+
+ .fillinsn
+6:
+ ld r3, @sp+
+ ld r2, @sp+
+ ld r1, @sp+
+ ld r0, @sp+
+ rte
+
+ .fillinsn
+3:
+;; error
+;; input
+;; r0: PFN + ASID
+;; r1: TLB entry address
+;; r2, r3: free
+;; output
+;; r0: PFN + ASID
+;; r1: TLB entry address
+;; r2: pte_data
+;; r3: free
+#ifdef CONFIG_ISA_DUAL_ISSUE
+ bra 5b || ldi r2, #2
+#else
+ ldi r2, #2 ; r2: pte_data = 0 | _PAGE_PRESENT(=2)
+ bra 5b
+#endif
+
+#elif defined (CONFIG_ISA_M32R)
+
+ st sp, @-sp
+ st r0, @-sp
+ st r1, @-sp
+ st r2, @-sp
+ st r3, @-sp
+ st r4, @-sp
+
+ seth r3, #high(MMU_REG_BASE)
+ ld r0, @(MDEVA_offset,r3) ; r0: address (MDEVA reg.)
+ mvfc r2, bpc ; r2: bpc
+ ld r1, @(MESTS_offset,r3) ; r1: status (MESTS reg.)
+ st r1, @(MESTS_offset,r3) ; clear status (MESTS reg.)
+ and3 r1, r1, #(MESTS_IT)
+ beqz r1, 1f ; data TLB miss?
+
+;; instrucntion TLB miss
+ mv r0, r2 ; address = bpc;
+ ; entry = (unsigned long *)ITLB_BASE+tlb_entry_i*2;
+ seth r3, #shigh(tlb_entry_i_dat)
+ ld r4, @(low(tlb_entry_i_dat),r3)
+ sll3 r2, r4, #3
+ seth r1, #high(ITLB_BASE)
+ or3 r1, r1, #low(ITLB_BASE)
+ add r2, r1 ; r2: entry
+ addi r4, #1 ; tlb_entry_i++;
+ and3 r4, r4, #(NR_TLB_ENTRIES-1)
+ st r4, @(low(tlb_entry_i_dat),r3)
+ bra 2f
+ .fillinsn
+1:
+;; data TLB miss
+ ; entry = (unsigned long *)DTLB_BASE+tlb_entry_d*2;
+ seth r3, #shigh(tlb_entry_d_dat)
+ ld r4, @(low(tlb_entry_d_dat),r3)
+ sll3 r2, r4, #3
+ seth r1, #high(DTLB_BASE)
+ or3 r1, r1, #low(DTLB_BASE)
+ add r2, r1 ; r2: entry
+ addi r4, #1 ; tlb_entry_d++;
+ and3 r4, r4, #(NR_TLB_ENTRIES-1)
+ st r4, @(low(tlb_entry_d_dat),r3)
+ .fillinsn
+2:
+;; load pte
+; r0: address, r2: entry
+; r1,r3,r4: (free)
+ ; pgd = *(unsigned long *)MPTB;
+ ld24 r1, #(-MPTB-1)
+ not r1, r1
+ ld r1, @r1
+ srl3 r4, r0, #22
+ sll3 r3, r4, #2
+ add r3, r1 ; r3: pgd
+ ; pmd = pmd_offset(pgd, address);
+ ld r1, @r3 ; r1: pmd
+ beqz r1, 3f ; pmd_none(*pmd) ?
+;
+ and3 r1, r1, #0xeff
+ ldi r4, #611 ; _KERNPG_TABLE(=611)
+ beq r1, r4, 4f ; !pmd_bad(*pmd) ?
+ .fillinsn
+3:
+ ldi r1, #0 ; r1: pte_data = 0
+ bra 5f
+ .fillinsn
+4:
+ ; pte = pte_offset(pmd, address);
+ ld r4, @r3 ; r4: pte
+ ldi r3, #-4096
+ and r4, r3
+ srl3 r3, r0, #10
+ and3 r3, r3, #0xffc
+ add r4, r3
+ seth r3, #0x8000
+ add r4, r3 ; r4: pte
+ ; pte_data = (unsigned long)pte_val(*pte);
+ ld r1, @r4 ; r1: pte_data
+ .fillinsn
+
+;; set tlb
+; r0: address, r1: pte_data, r2: entry
+; r3,r4: (free)
+5:
+ ldi r3, #-4096 ; set_tlb_tag(entry++, address);
+ and r3, r0
+ seth r4, #shigh(MASID)
+ ld r4, @(low(MASID),r4) ; r4: MASID
+ and3 r4, r4, #(MMU_CONTEXT_ASID_MASK)
+ or r3, r4
+ st r3, @r2
+ or3 r4, r1, #2 ; _PAGE_PRESENT(=2)
+ st r4, @(4,r2) ; set_tlb_data(entry, pte_data);
+
+ ld r4, @sp+
+ ld r3, @sp+
+ ld r2, @sp+
+ ld r1, @sp+
+ ld r0, @sp+
+ ld sp, @sp+
+ rte
+
+#else
+#error unknown isa configuration
+#endif
+
+ENTRY(init_tlb)
+;; Set MMU Register
+ seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
+ or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
+ ldi r1, #0
+ st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
+ ldi r1, #0
+ st r1, @(MASID_offset,r0) ; Set ASID Zero
+
+;; Set TLB
+ seth r0, #high(ITLB_BASE) ; Set ITLB_BASE higher
+ or3 r0, r0, #low(ITLB_BASE) ; Set ITLB_BASE lower
+ seth r1, #high(DTLB_BASE) ; Set DTLB_BASE higher
+ or3 r1, r1, #low(DTLB_BASE) ; Set DTLB_BASE lower
+ ldi r2, #0
+ ldi r3, #NR_TLB_ENTRIES
+ addi r0, #-4
+ addi r1, #-4
+clear_tlb:
+ st r2, @+r0 ; VPA <- 0
+ st r2, @+r0 ; PPA <- 0
+ st r2, @+r1 ; VPA <- 0
+ st r2, @+r1 ; PPA <- 0
+ addi r3, #-1
+ bnez r3, clear_tlb
+;;
+ jmp r14
+
+ENTRY(m32r_itlb_entrys)
+ENTRY(m32r_otlb_entrys)
+
+#endif /* CONFIG_MMU */
+
+.end
+
--- /dev/null
+/*
+ * linux/arch/m32r/mm/page.S
+ *
+ * Clear/Copy page with CPU
+ *
+ * Copyright (C) 2004 The Free Software Initiative of Japan
+ *
+ * Written by Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+ .text
+ .global copy_page
+ /*
+ * copy_page (to, from)
+ *
+ * PAGE_SIZE = 4096-byte
+ * Cache line = 16-byte
+ * 16 * 256
+ */
+ .align 4
+copy_page:
+ ldi r2, #255
+ ld r3, @r0 /* cache line allocate */
+ ld r4, @r1+
+ ld r5, @r1+
+ ld r6, @r1+
+ ld r7, @r1+
+ .fillinsn
+0:
+ st r4, @r0
+ st r5, @+r0
+ st r6, @+r0
+ st r7, @+r0
+ ld r4, @r1+
+ addi r0, #4
+ ld r5, @r1+
+ ld r6, @r1+
+ ld r7, @r1+
+ ld r3, @r0 /* cache line allocate */
+ addi r2, #-1
+ bnez r2, 0b
+
+ st r4, @r0
+ st r5, @+r0
+ st r6, @+r0
+ st r7, @+r0
+ jmp r14
+
+ .text
+ .global clear_page
+ /*
+ * clear_page (to)
+ *
+ * PAGE_SIZE = 4096-byte
+ * Cache line = 16-byte
+ * 16 * 256
+ */
+ .align 4
+clear_page:
+ ldi r2, #255
+ ldi r4, #0
+ ld r3, @r0 /* cache line allocate */
+ .fillinsn
+0:
+ st r4, @r0
+ st r4, @+r0
+ st r4, @+r0
+ st r4, @+r0
+ addi r0, #4
+ ld r3, @r0 /* cache line allocate */
+ addi r2, #-1
+ bnez r2, 0b
+
+ st r4, @r0
+ st r4, @+r0
+ st r4, @+r0
+ st r4, @+r0
+ jmp r14
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Processor type and features
+#
+# CONFIG_PLAT_MAPPI is not set
+# CONFIG_PLAT_USRV is not set
+# CONFIG_PLAT_M32700UT is not set
+# CONFIG_PLAT_OPSPUT is not set
+CONFIG_PLAT_OAKS32R=y
+# CONFIG_PLAT_MAPPI2 is not set
+# CONFIG_CHIP_M32700 is not set
+CONFIG_CHIP_M32102=y
+# CONFIG_CHIP_VDEC2 is not set
+# CONFIG_CHIP_OPSP is not set
+CONFIG_ISA_M32R=y
+CONFIG_BUS_CLOCK=33333333
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x01000000
+CONFIG_MEMORY_SIZE=0x00800000
+CONFIG_NOHIGHMEM=y
+# CONFIG_DISCONTIGMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_PREEMPT=y
+# CONFIG_HAVE_DEC_LOCK is not set
+# CONFIG_SMP is not set
+
+#
+# M32R drivers
+#
+CONFIG_M32R_NE2000=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+# CONFIG_PCMCIA is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_FLAT=y
+# CONFIG_BINFMT_ZFLAT is not set
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_M32R_SIO=y
+CONFIG_SERIAL_M32R_SIO_CONSOLE=y
+# CONFIG_SERIAL_M32R_PLDSIO is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_DEVPTS_FS_XATTR=y
+CONFIG_DEVPTS_FS_SECURITY=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+# .gdbinit file
+# $Id: dot.gdbinit.oaks32r,v 1.2 2004/04/15 02:33:14 takata Exp $
+#-----
+# NOTE: this file is generated by a script, "gen_gdbinit.pl".
+# (Please type "gen_gdbinit.pl --help" and check the help message).
+# $ Id: gen_gdbinit.pl,v 1.10 2004/04/15 02:10:45 takata Exp $
+#-----
+# target platform: oaks32r
+
+# setting
+set width 0d70
+set radix 0d16
+
+# clk xin:cpu:bus=16:66:33
+define clock_init
+ set *(unsigned long *)0x00ef4008 = 1
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef4000 = 0x00020100
+end
+
+# Initialize programmable ports
+define port_init
+ set *(unsigned long *)0x00ef1000 = 0x1
+ set *(unsigned long *)0x00ef1060 = 0x01400001
+ set *(unsigned long *)0x00ef1064 = 0x00015555
+ set *(unsigned long *)0x00ef1068 = 0x55555050
+ set *(unsigned long *)0x00ef106c = 0x05150040
+end
+
+# Initialize SDRAM controller
+define sdram_init
+ set *(unsigned long *)0x00ef6008 = 0x00000182
+ set *(unsigned long *)0x00ef600c = 0x00000001
+ shell sleep 0.1
+ set *(unsigned long *)0x00ef602c = 0x00000010
+ set *(unsigned long *)0x00ef6028 = 0x00000300
+ set *(unsigned long *)0x00ef6048 = 0x00000001
+ set *(unsigned long *)0x00ef6020 = 0x01000041
+ set *(unsigned long *)0x00ef6004 = 0x00010117
+ set *(unsigned long *)0x00ef6010 = 0x00000001
+ set *(unsigned long *)0x00ef6024 = 0x00000001
+end
+document sdram_init
+ SDRAM controller initialization
+ 0x01000000 - 0x017fffff (8MB)
+end
+
+# Initialize LAN controller
+define lanc_init
+ set *(unsigned long *)0x00ef5008 = 0x03031303
+ #RST DRV (P64)
+ set *(unsigned char *)0x00ef1046 = 0x08
+ set *(unsigned char *)0x00ef1026 = 0xff
+ set *(unsigned char *)0x00ef1026 = 0x00
+ set *(unsigned short *)0x02000630 = 0xffff
+end
+
+# Show current task structure
+define show_current
+ set $current = $spi & 0xffffe000
+ printf "$current=0x%08lX\n",$current
+ print *(struct task_struct *)$current
+end
+
+# Show user assigned task structure
+define show_task
+ set = $arg0 & 0xffffe000
+ printf "$task=0x%08lX\n",$task
+ print *(struct task_struct *)$task
+end
+document show_task
+ Show user assigned task structure
+ arg0 : task structure address
+end
+
+# Show M32R registers
+define show_regs
+ printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
+ printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
+ printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
+ printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
+ printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
+end
+
+# Setup all
+define setup
+ use_mon_code
+ set *(unsigned int)0xfffffffc=0x60
+ shell sleep 0.1
+ clock_init
+ shell sleep 0.1
+ port_init
+ sdram_init
+ lanc_init
+end
+
+# Load modules
+define load_modules
+ use_debug_dma
+ load
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x01002000
+ # INITRD_START
+ set *(unsigned long *)($param + 0x0010) = 0x00000000
+ # INITRD_SIZE
+ set *(unsigned long *)($param + 0x0014) = 0x00000000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d66666667
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d33333333
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+# set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
+ set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.busybox.flat nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
+end
+
+# Boot
+define boot
+ set_kernel_parameters
+ set $fp = 0
+ set $pc = 0x01001000
+ si
+ c
+end
+
+# Set breakpoints
+define set_breakpoints
+ b *0x00000020
+ b *0x00000030
+end
+
+# Restart
+define restart
+ sdireset
+ sdireset
+ setup
+ load_modules
+ boot
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+setup
+#load_modules
+#set_breakpoints
+#boot
+
--- /dev/null
+
+menu "Profiling support"
+ depends on EXPERIMENTAL
+
+config PROFILING
+ bool "Profiling support (EXPERIMENTAL)"
+ help
+ Say Y here to enable the extended profiling support mechanisms used
+ by profilers such as OProfile.
+
+
+config OPROFILE
+ tristate "OProfile system profiling (EXPERIMENTAL)"
+ depends on PROFILING
+ help
+ OProfile is a profiling system capable of profiling the
+ whole system, include the kernel, kernel modules, libraries,
+ and applications.
+
+ If unsure, say N.
+
+endmenu
+
--- /dev/null
+obj-$(CONFIG_OPROFILE) += oprofile.o
+
+DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
+ oprof.o cpu_buffer.o buffer_sync.o \
+ event_buffer.o oprofile_files.o \
+ oprofilefs.o oprofile_stats.o \
+ timer_int.o )
+
+oprofile-y := $(DRIVER_OBJS) init.o
--- /dev/null
+/**
+ * @file init.c
+ *
+ * @remark Copyright 2002 OProfile authors
+ * @remark Read the file COPYING
+ *
+ * @author John Levon <levon@movementarian.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/oprofile.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+
+extern void timer_init(struct oprofile_operations ** ops);
+
+int __init oprofile_arch_init(struct oprofile_operations ** ops)
+{
+ return -ENODEV;
+}
+
+
+void oprofile_arch_exit(void)
+{
+}
--- /dev/null
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_M32R=y
+CONFIG_UID16=y
+CONFIG_GENERIC_ISA_DMA=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_HOTPLUG=y
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Processor type and features
+#
+# CONFIG_PLAT_MAPPI is not set
+# CONFIG_PLAT_USRV is not set
+# CONFIG_PLAT_M32700UT is not set
+CONFIG_PLAT_OPSPUT=y
+# CONFIG_PLAT_OAKS32R is not set
+# CONFIG_PLAT_MAPPI2 is not set
+# CONFIG_CHIP_M32700 is not set
+# CONFIG_CHIP_M32102 is not set
+# CONFIG_CHIP_VDEC2 is not set
+CONFIG_CHIP_OPSP=y
+CONFIG_MMU=y
+CONFIG_TLB_ENTRIES=32
+CONFIG_ISA_M32R2=y
+CONFIG_ISA_DSP_LEVEL2=y
+CONFIG_ISA_DUAL_ISSUE=y
+CONFIG_BUS_CLOCK=50000000
+CONFIG_TIMER_DIVIDE=128
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x01000000
+CONFIG_NOHIGHMEM=y
+# CONFIG_DISCONTIGMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_SMP is not set
+
+#
+# M32R drivers
+#
+# CONFIG_M32R_CFC is not set
+CONFIG_M32R_SMC91111=y
+CONFIG_M32700UT_DS1302=y
+
+#
+# Power management options (ACPI, APM)
+#
+# CONFIG_PM is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI is not set
+# CONFIG_ISA is not set
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_TCIC is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=m
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_M32R_SIO is not set
+CONFIG_SERIAL_M32R_PLDSIO=y
+CONFIG_SERIAL_M32R_PLDSIO_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_IOVIRT is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_FRAME_POINTER is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
--- /dev/null
+# .gdbinit file
+# $Id: dot.gdbinit,v 1.1 2004/07/27 06:54:20 sakugawa Exp $
+
+# setting
+set width 0d70
+set radix 0d16
+set height 0
+debug_chaos
+
+define tlb_init
+ set $tlbbase = 0xfe000000
+ set *(unsigned long *)($tlbbase + 0x04) = 0x0
+ set *(unsigned long *)($tlbbase + 0x0c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x14) = 0x0
+ set *(unsigned long *)($tlbbase + 0x1c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x24) = 0x0
+ set *(unsigned long *)($tlbbase + 0x2c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x34) = 0x0
+ set *(unsigned long *)($tlbbase + 0x3c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x44) = 0x0
+ set *(unsigned long *)($tlbbase + 0x4c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x54) = 0x0
+ set *(unsigned long *)($tlbbase + 0x5c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x64) = 0x0
+ set *(unsigned long *)($tlbbase + 0x6c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x74) = 0x0
+ set *(unsigned long *)($tlbbase + 0x7c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x84) = 0x0
+ set *(unsigned long *)($tlbbase + 0x8c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x94) = 0x0
+ set *(unsigned long *)($tlbbase + 0x9c) = 0x0
+ set *(unsigned long *)($tlbbase + 0xa4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xac) = 0x0
+ set *(unsigned long *)($tlbbase + 0xb4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xbc) = 0x0
+ set *(unsigned long *)($tlbbase + 0xc4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xcc) = 0x0
+ set *(unsigned long *)($tlbbase + 0xd4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xdc) = 0x0
+ set *(unsigned long *)($tlbbase + 0xe4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xec) = 0x0
+ set *(unsigned long *)($tlbbase + 0xf4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xfc) = 0x0
+ set $tlbbase = 0xfe000800
+ set *(unsigned long *)($tlbbase + 0x04) = 0x0
+ set *(unsigned long *)($tlbbase + 0x0c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x14) = 0x0
+ set *(unsigned long *)($tlbbase + 0x1c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x24) = 0x0
+ set *(unsigned long *)($tlbbase + 0x2c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x34) = 0x0
+ set *(unsigned long *)($tlbbase + 0x3c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x44) = 0x0
+ set *(unsigned long *)($tlbbase + 0x4c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x54) = 0x0
+ set *(unsigned long *)($tlbbase + 0x5c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x64) = 0x0
+ set *(unsigned long *)($tlbbase + 0x6c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x74) = 0x0
+ set *(unsigned long *)($tlbbase + 0x7c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x84) = 0x0
+ set *(unsigned long *)($tlbbase + 0x8c) = 0x0
+ set *(unsigned long *)($tlbbase + 0x94) = 0x0
+ set *(unsigned long *)($tlbbase + 0x9c) = 0x0
+ set *(unsigned long *)($tlbbase + 0xa4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xac) = 0x0
+ set *(unsigned long *)($tlbbase + 0xb4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xbc) = 0x0
+ set *(unsigned long *)($tlbbase + 0xc4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xcc) = 0x0
+ set *(unsigned long *)($tlbbase + 0xd4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xdc) = 0x0
+ set *(unsigned long *)($tlbbase + 0xe4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xec) = 0x0
+ set *(unsigned long *)($tlbbase + 0xf4) = 0x0
+ set *(unsigned long *)($tlbbase + 0xfc) = 0x0
+end
+
+define load_modules
+ use_debug_dma
+ load
+end
+
+# Set kernel parameters
+define set_kernel_parameters
+ set $param = (void*)0x88002000
+ # INITRD_START
+# set *(unsigned long *)($param + 0x0010) = 0x08300000
+ # INITRD_SIZE
+# set *(unsigned long *)($param + 0x0014) = 0x00400000
+ # M32R_CPUCLK
+ set *(unsigned long *)($param + 0x0018) = 0d200000000
+ # M32R_BUSCLK
+ set *(unsigned long *)($param + 0x001c) = 0d50000000
+# set *(unsigned long *)($param + 0x001c) = 0d25000000
+
+ # M32R_TIMER_DIVIDE
+ set *(unsigned long *)($param + 0x0020) = 0d128
+
+ set {char[0x200]}($param + 0x100) = "console=ttyD0,115200n8x\
+ root=/dev/nfsroot \
+ nfsroot=192.168.0.1:/project/m32r-linux/export/root.2.6 \
+ nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \
+ mem=16m \0"
+end
+
+define boot
+ set_kernel_parameters
+ set $pc=0x88001000
+ set $fp=0
+ set $evb=0x88000000
+ # I/D-Cache ON
+
+# IPI
+# set *(long *)0x00eff2f8 = 0x2
+ set $fp=0
+# set *(unsigned long *)0xa0ef4000 = 0x100
+ si
+end
+
+# Show TLB entries
+define show_tlb_entries
+ set $i = 0
+ set $addr = $arg0
+ use_mon_code
+ while ($i < 0d32 )
+ set $tlb_tag = *(unsigned long*)$addr
+ set $tlb_data = *(unsigned long*)($addr + 4)
+ printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
+ set $i = $i + 1
+ set $addr = $addr + 8
+ end
+# use_debug_dma
+end
+define itlb
+ set $itlb=0xfe000000
+ show_tlb_entries $itlb
+end
+define dtlb
+ set $dtlb=0xfe000800
+ show_tlb_entries $dtlb
+end
+
+define show_regs
+ printf " R0[%08lx] R1[%08lx] R2[%08lx] R3[%08lx]\n",$r0,$r1,$r2,$r3
+ printf " R4[%08lx] R5[%08lx] R6[%08lx] R7[%08lx]\n",$r4,$r5,$r6,$r7
+ printf " R8[%08lx] R9[%08lx] R10[%08lx] R11[%08lx]\n",$r8,$r9,$r10,$r11
+ printf "R12[%08lx] FP[%08lx] LR[%08lx] SP[%08lx]\n",$r12,$fp,$lr,$sp
+ printf "PSW[%08lx] CBR[%08lx] SPI[%08lx] SPU[%08lx]\n",$psw,$cbr,$spi,$spu
+ printf "BPC[%08lx] PC[%08lx] ACCL[%08lx] ACCH[%08lx]\n",$bpc,$pc,$accl,$acch
+ printf "EVB[%08lx]\n",$evb
+end
+
+define setup
+ debug_chaos
+ set *(unsigned long *)0xa0ef6004 = 0x0001053f
+ set *(unsigned long *)0xa0ef6028 = 0x00031102
+# set *(unsigned long *)0xa0ef400c = 0x2
+end
+
+sdireset
+sdireset
+file vmlinux
+target m32rsdi
+set $pc=0x0
+b *0x30000
+c
+setup
+tlb_init
+load_modules
+#set *(long *)0xa0ef4000=0x101
+#set *(long *)0xa0ef400c=0x002
+
+boot
+#b tme_handler
+b *0x88000020
+
+
+
+
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config FULLDEBUG
+ bool "Full Symbolic/Source Debugging support"
+ help
+ Enable debuging symbols on kernel build.
+
+config HIGHPROFILE
+ bool "Use fast second timer for profiling"
+ depends on COLDFIRE
+ help
+ Use a fast secondary clock to produce profiling information.
+
+config BOOTPARAM
+ bool 'Compiled-in Kernel Boot Parameter'
+
+config BOOTPARAM_STRING
+ string 'Kernel Boot Parameter'
+ default 'console=ttyS0,19200'
+ depends on BOOTPARAM
+
+config DUMPTOFLASH
+ bool "Panic/Dump to FLASH"
+ depends on COLDFIRE
+ help
+ Dump any panic of trap output into a flash memory segment
+ for later analysis.
+
+config NO_KERNEL_MSG
+ bool "Suppress Kernel BUG Messages"
+ help
+ Do not output any debug BUG messages within the kernel.
+
+config BDM_DISABLE
+ bool "Disable BDM signals"
+ depends on (EXPERIMENTAL && COLDFIRE)
+ help
+ Disable the ColdFire CPU's BDM signals.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config CROSSCOMPILE
+ bool "Are you using a crosscompiler"
+ help
+ Say Y here if you are compiling the kernel on a different
+ architecture than the one it is intended to run on.
+
+config CMDLINE
+ string "Default kernel command string"
+ default ""
+ help
+ On some platforms, there is currently no way for the boot loader to
+ pass arguments to the kernel. For these platforms, you can supply
+ some command-line options at build time by entering them here. In
+ other cases you can specify kernel args so that you don't have
+ to set them up in board prom initialization routines.
+
+config DEBUG_STACK_USAGE
+ bool "Enable stack utilization instrumentation"
+ depends on DEBUG_KERNEL
+ help
+ Enables the display of the minimum amount of free stack which each
+ task has ever had available in the sysrq-T and sysrq-P debug output.
+
+ This option will slow down process creation somewhat.
+
+config KGDB
+ bool "Remote GDB kernel debugging"
+ depends on DEBUG_KERNEL
+ select DEBUG_INFO
+ help
+ If you say Y here, it will be possible to remotely debug the MIPS
+ kernel using gdb. This enlarges your kernel image disk size by
+ several megabytes and requires a machine with more than 16 MB,
+ better 32 MB RAM to avoid excessive linking time. This is only
+ useful for kernel hackers. If unsure, say N.
+
+config GDB_CONSOLE
+ bool "Console output to GDB"
+ depends on KGDB
+ help
+ If you are using GDB for remote debugging over a serial port and
+ would like kernel messages to be formatted into GDB $O packets so
+ that GDB prints them as program output, say 'Y'.
+
+config SB1XXX_CORELIS
+ bool "Corelis Debugger"
+ depends on SIBYTE_SB1xxx_SOC
+ select DEBUG_INFO
+ help
+ Select compile flags that produce code that can be processed by the
+ Corelis mksym utility and UDB Emulator.
+
+config RUNTIME_DEBUG
+ bool "Enable run-time debugging"
+ depends on DEBUG_KERNEL
+ help
+ If you say Y here, some debugging macros will do run-time checking.
+ If you say N here, those macros will mostly turn to no-ops. See
+ include/asm-mips/debug.h for debuging macros.
+ If unsure, say N.
+
+config MIPS_UNCACHED
+ bool "Run uncached"
+ depends on DEBUG_KERNEL && !SMP && !SGI_IP27
+ help
+ If you say Y here there kernel will disable all CPU caches. This will
+ reduce the system's performance dramatically but can help finding
+ otherwise hard to track bugs. It can also useful if you're doing
+ hardware debugging with a logic analyzer and need to see all traffic
+ on the bus.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config DEBUG_RWLOCK
+ bool "Read-write spinlock debugging"
+ depends on DEBUG_KERNEL && SMP
+ help
+ If you say Y here then read-write lock processing will count how many
+ times it has tried to get the lock and issue an error message after
+ too many attempts. If you suspect a rwlock problem or a kernel
+ hacker asks for this option then say Y. Otherwise say N.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config KGDB
+ bool "Include kgdb kernel debugger"
+ depends on DEBUG_KERNEL && (BROKEN || PPC_GEN550 || 4xx)
+ select DEBUG_INFO
+ help
+ Include in-kernel hooks for kgdb, the Linux kernel source level
+ debugger. See <http://kgdb.sourceforge.net/> for more information.
+ Unless you are intending to debug the kernel, say N here.
+
+choice
+ prompt "Serial Port"
+ depends on KGDB
+ default KGDB_TTYS1
+
+config KGDB_TTYS0
+ bool "ttyS0"
+
+config KGDB_TTYS1
+ bool "ttyS1"
+
+config KGDB_TTYS2
+ bool "ttyS2"
+
+config KGDB_TTYS3
+ bool "ttyS3"
+
+endchoice
+
+config KGDB_CONSOLE
+ bool "Enable serial console thru kgdb port"
+ depends on KGDB && 8xx || CPM2
+ help
+ If you enable this, all serial console messages will be sent
+ over the gdb stub.
+ If unsure, say N.
+
+config XMON
+ bool "Include xmon kernel debugger"
+ depends on DEBUG_KERNEL
+ help
+ Include in-kernel hooks for the xmon kernel monitor/debugger.
+ Unless you are intending to debug the kernel, say N here.
+
+config BDI_SWITCH
+ bool "Include BDI-2000 user context switcher"
+ depends on DEBUG_KERNEL
+ help
+ Include in-kernel support for the Abatron BDI2000 debugger.
+ Unless you are intending to debug the kernel with one of these
+ machines, say N here.
+
+config SCHEDSTATS
+ bool "Collect scheduler statistics"
+ depends on DEBUG_KERNEL && PROC_FS
+ help
+ If you say Y here, additional code will be inserted into the
+ scheduler and related routines to collect statistics about
+ scheduler behavior and provide them in /proc/schedstat. These
+ stats may be useful for both tuning and debugging the scheduler
+ If you aren't debugging the scheduler or trying to tune a specific
+ application, you can say N to avoid the very slight overhead
+ this adds.
+
+config BOOTX_TEXT
+ bool "Support for early boot text console (BootX or OpenFirmware only)"
+ depends PPC_OF
+ help
+ Say Y here to see progress messages from the boot firmware in text
+ mode. Requires either BootX or Open Firmware.
+
+config SERIAL_TEXT_DEBUG
+ bool "Support for early boot texts over serial port"
+ depends on 4xx || GT64260 || LOPEC || PPLUS || PRPMC800 || PPC_GEN550 || PPC_MPC52xx
+
+config PPC_OCP
+ bool
+ depends on IBM_OCP || FSL_OCP
+ default y
+
+endmenu
--- /dev/null
+/*
+ * A really private header file for the (dumb) serial driver in arch/ppc/boot
+ *
+ * Shamelessly taken from include/linux/serialP.h:
+ *
+ * Copyright (C) 1997 by Theodore Ts'o.
+ *
+ * Redistribution of this file is permitted under the terms of the GNU
+ * Public License (GPL)
+ */
+
+#ifndef _PPC_BOOT_SERIALP_H
+#define _PPC_BOOT_SERIALP_H
+
+/*
+ * This is our internal structure for each serial port's state.
+ *
+ * Many fields are paralleled by the structure used by the serial_struct
+ * structure.
+ *
+ * Given that this is how SERIAL_PORT_DFNS are done, and that we need
+ * to use a few of their fields, we need to have our own copy of it.
+ */
+struct serial_state {
+ int magic;
+ int baud_base;
+ unsigned long port;
+ int irq;
+ int flags;
+ int hub6;
+ int type;
+ int line;
+ int revision; /* Chip revision (950) */
+ int xmit_fifo_size;
+ int custom_divisor;
+ int count;
+ u8 *iomem_base;
+ u16 iomem_reg_shift;
+ unsigned short close_delay;
+ unsigned short closing_wait; /* time to wait before closing */
+ unsigned long icount;
+ int io_type;
+ void *info;
+ void *dev;
+};
+#endif /* _PPC_BOOT_SERIAL_H */
--- /dev/null
+/*
+ * 2004 (C) IBM. This file is licensed under the terms of the GNU General
+ * Public License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <nonstdio.h>
+
+void board_isa_init(void)
+{
+ ISA_init(0xFE000000);
+}
--- /dev/null
+/*
+ * 2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <asm/ppcboot.h>
+#include <platforms/4xx/ocotea.h>
+
+extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
+ unsigned long cksum);
+
+/* We need to make sure that this is before the images to ensure
+ * that it's in a mapped location. - Tom */
+bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot")));
+bd_t *hold_residual = &hold_resid_buf;
+
+/* String functions lifted from lib/vsprintf.c and lib/ctype.c */
+unsigned char _ctype[] = {
+_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */
+_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */
+_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */
+_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */
+_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */
+_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */
+_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */
+_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */
+_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */
+_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */
+_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */
+_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */
+_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */
+_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */
+_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */
+_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */
+0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
+0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
+_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */
+_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */
+_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */
+_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */
+_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */
+_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */
+
+/**
+ * simple_strtoull - convert a string to an unsigned long long
+ * @cp: The start of the string
+ * @endp: A pointer to the end of the parsed string will be placed here
+ * @base: The number base to use
+ */
+unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base)
+{
+ unsigned long long result = 0,value;
+
+ if (!base) {
+ base = 10;
+ if (*cp == '0') {
+ base = 8;
+ cp++;
+ if ((toupper(*cp) == 'X') && isxdigit(cp[1])) {
+ cp++;
+ base = 16;
+ }
+ }
+ } else if (base == 16) {
+ if (cp[0] == '0' && toupper(cp[1]) == 'X')
+ cp += 2;
+ }
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
+ ? toupper(*cp) : *cp)-'A'+10) < base) {
+ result = result*base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *)cp;
+ return result;
+}
+
+void *
+load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
+ void *ign1, void *ign2)
+{
+ unsigned long long mac64;
+
+ decompress_kernel(load_addr, num_words, cksum);
+
+ mac64 = simple_strtoull((char *)OCOTEA_PIBS_MAC_BASE, 0, 16);
+ memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
+ mac64 = simple_strtoull((char *)(OCOTEA_PIBS_MAC_BASE+OCOTEA_PIBS_MAC_OFFSET), 0, 16);
+ memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
+ mac64 = simple_strtoull((char *)(OCOTEA_PIBS_MAC_BASE+OCOTEA_PIBS_MAC_OFFSET*2), 0, 16);
+ memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
+ mac64 = simple_strtoull((char *)(OCOTEA_PIBS_MAC_BASE+OCOTEA_PIBS_MAC_OFFSET*3), 0, 16);
+ memcpy(hold_residual->bi_enet3addr, (char *)&mac64+2, 6);
+ return (void *)hold_residual;
+}
--- /dev/null
+/*
+ * 2004 (C) IBM. This file is licensed under the terms of the GNU General
+ * Public License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <nonstdio.h>
+
+void board_isa_init(void)
+{
+ ISA_init(0x80000000);
+}
--- /dev/null
+#ifndef __HEAD_BOOKE_H__
+#define __HEAD_BOOKE_H__
+
+/*
+ * Macros used for common Book-e exception handling
+ */
+
+#define SET_IVOR(vector_number, vector_label) \
+ li r26,vector_label@l; \
+ mtspr SPRN_IVOR##vector_number,r26; \
+ sync
+
+#define NORMAL_EXCEPTION_PROLOG \
+ mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
+ mtspr SPRN_SPRG1,r11; \
+ mtspr SPRN_SPRG4W,r1; \
+ mfcr r10; /* save CR in r10 for now */\
+ mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
+ andi. r11,r11,MSR_PR; \
+ beq 1f; \
+ mfspr r1,SPRG3; /* if from user, start at top of */\
+ lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
+ addi r1,r1,THREAD_SIZE; \
+1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
+ tophys(r11,r1); \
+ stw r10,_CCR(r11); /* save various registers */\
+ stw r12,GPR12(r11); \
+ stw r9,GPR9(r11); \
+ mfspr r10,SPRG0; \
+ stw r10,GPR10(r11); \
+ mfspr r12,SPRG1; \
+ stw r12,GPR11(r11); \
+ mflr r10; \
+ stw r10,_LINK(r11); \
+ mfspr r10,SPRG4R; \
+ mfspr r12,SRR0; \
+ stw r10,GPR1(r11); \
+ mfspr r9,SRR1; \
+ stw r10,0(r11); \
+ rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
+ stw r0,GPR0(r11); \
+ SAVE_4GPRS(3, r11); \
+ SAVE_2GPRS(7, r11)
+
+/*
+ * Exception prolog for critical exceptions. This is a little different
+ * from the normal exception prolog above since a critical exception
+ * can potentially occur at any point during normal exception processing.
+ * Thus we cannot use the same SPRG registers as the normal prolog above.
+ * Instead we use a couple of words of memory at low physical addresses.
+ * This is OK since we don't support SMP on these processors. For Book E
+ * processors, we also have a reserved register (SPRG2) that is only used
+ * in critical exceptions so we can free up a GPR to use as the base for
+ * indirect access to the critical exception save area. This is necessary
+ * since the MMU is always on and the save area is offset from KERNELBASE.
+ */
+#define CRITICAL_EXCEPTION_PROLOG \
+ mtspr SPRG2,r8; /* SPRG2 only used in criticals */ \
+ lis r8,crit_save@ha; \
+ stw r10,crit_r10@l(r8); \
+ stw r11,crit_r11@l(r8); \
+ mfspr r10,SPRG0; \
+ stw r10,crit_sprg0@l(r8); \
+ mfspr r10,SPRG1; \
+ stw r10,crit_sprg1@l(r8); \
+ mfspr r10,SPRG4R; \
+ stw r10,crit_sprg4@l(r8); \
+ mfspr r10,SPRG5R; \
+ stw r10,crit_sprg5@l(r8); \
+ mfspr r10,SPRG7R; \
+ stw r10,crit_sprg7@l(r8); \
+ mfspr r10,SPRN_PID; \
+ stw r10,crit_pid@l(r8); \
+ mfspr r10,SRR0; \
+ stw r10,crit_srr0@l(r8); \
+ mfspr r10,SRR1; \
+ stw r10,crit_srr1@l(r8); \
+ mfspr r8,SPRG2; /* SPRG2 only used in criticals */ \
+ mfcr r10; /* save CR in r10 for now */\
+ mfspr r11,SPRN_CSRR1; /* check whether user or kernel */\
+ andi. r11,r11,MSR_PR; \
+ lis r11,critical_stack_top@h; \
+ ori r11,r11,critical_stack_top@l; \
+ beq 1f; \
+ /* COMING FROM USER MODE */ \
+ mfspr r11,SPRG3; /* if from user, start at top of */\
+ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
+ addi r11,r11,THREAD_SIZE; \
+1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
+ stw r10,_CCR(r11); /* save various registers */\
+ stw r12,GPR12(r11); \
+ stw r9,GPR9(r11); \
+ mflr r10; \
+ stw r10,_LINK(r11); \
+ mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
+ stw r12,_DEAR(r11); /* since they may have had stuff */\
+ mfspr r9,SPRN_ESR; /* in them at the point where the */\
+ stw r9,_ESR(r11); /* exception was taken */\
+ mfspr r12,CSRR0; \
+ stw r1,GPR1(r11); \
+ mfspr r9,CSRR1; \
+ stw r1,0(r11); \
+ tovirt(r1,r11); \
+ rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
+ stw r0,GPR0(r11); \
+ SAVE_4GPRS(3, r11); \
+ SAVE_2GPRS(7, r11)
+
+/*
+ * Exception prolog for machine check exceptions. This is similar to
+ * the critical exception prolog, except that machine check exceptions
+ * have their own save area. For Book E processors, we also have a
+ * reserved register (SPRG6) that is only used in machine check exceptions
+ * so we can free up a GPR to use as the base for indirect access to the
+ * machine check exception save area. This is necessary since the MMU
+ * is always on and the save area is offset from KERNELBASE.
+ */
+#define MCHECK_EXCEPTION_PROLOG \
+ mtspr SPRG6W,r8; /* SPRG6 used in machine checks */ \
+ lis r8,mcheck_save@ha; \
+ stw r10,mcheck_r10@l(r8); \
+ stw r11,mcheck_r11@l(r8); \
+ mfspr r10,SPRG0; \
+ stw r10,mcheck_sprg0@l(r8); \
+ mfspr r10,SPRG1; \
+ stw r10,mcheck_sprg1@l(r8); \
+ mfspr r10,SPRG4R; \
+ stw r10,mcheck_sprg4@l(r8); \
+ mfspr r10,SPRG5R; \
+ stw r10,mcheck_sprg5@l(r8); \
+ mfspr r10,SPRG7R; \
+ stw r10,mcheck_sprg7@l(r8); \
+ mfspr r10,SPRN_PID; \
+ stw r10,mcheck_pid@l(r8); \
+ mfspr r10,SRR0; \
+ stw r10,mcheck_srr0@l(r8); \
+ mfspr r10,SRR1; \
+ stw r10,mcheck_srr1@l(r8); \
+ mfspr r10,CSRR0; \
+ stw r10,mcheck_csrr0@l(r8); \
+ mfspr r10,CSRR1; \
+ stw r10,mcheck_csrr1@l(r8); \
+ mfspr r8,SPRG6R; /* SPRG6 used in machine checks */ \
+ mfcr r10; /* save CR in r10 for now */\
+ mfspr r11,SPRN_MCSRR1; /* check whether user or kernel */\
+ andi. r11,r11,MSR_PR; \
+ lis r11,mcheck_stack_top@h; \
+ ori r11,r11,mcheck_stack_top@l; \
+ beq 1f; \
+ /* COMING FROM USER MODE */ \
+ mfspr r11,SPRG3; /* if from user, start at top of */\
+ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
+ addi r11,r11,THREAD_SIZE; \
+1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
+ stw r10,_CCR(r11); /* save various registers */\
+ stw r12,GPR12(r11); \
+ stw r9,GPR9(r11); \
+ mflr r10; \
+ stw r10,_LINK(r11); \
+ mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
+ stw r12,_DEAR(r11); /* since they may have had stuff */\
+ mfspr r9,SPRN_ESR; /* in them at the point where the */\
+ stw r9,_ESR(r11); /* exception was taken */\
+ mfspr r12,MCSRR0; \
+ stw r1,GPR1(r11); \
+ mfspr r9,MCSRR1; \
+ stw r1,0(r11); \
+ tovirt(r1,r11); \
+ rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
+ stw r0,GPR0(r11); \
+ SAVE_4GPRS(3, r11); \
+ SAVE_2GPRS(7, r11)
+
+/*
+ * Exception vectors.
+ */
+#define START_EXCEPTION(label) \
+ .align 5; \
+label:
+
+#define FINISH_EXCEPTION(func) \
+ bl transfer_to_handler_full; \
+ .long func; \
+ .long ret_from_except_full
+
+#define EXCEPTION(n, label, hdlr, xfer) \
+ START_EXCEPTION(label); \
+ NORMAL_EXCEPTION_PROLOG; \
+ addi r3,r1,STACK_FRAME_OVERHEAD; \
+ xfer(n, hdlr)
+
+#define CRITICAL_EXCEPTION(n, label, hdlr) \
+ START_EXCEPTION(label); \
+ CRITICAL_EXCEPTION_PROLOG; \
+ addi r3,r1,STACK_FRAME_OVERHEAD; \
+ EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
+ NOCOPY, transfer_to_handler_full, \
+ ret_from_except_full)
+
+#define MCHECK_EXCEPTION(n, label, hdlr) \
+ START_EXCEPTION(label); \
+ MCHECK_EXCEPTION_PROLOG; \
+ mfspr r5,SPRN_ESR; \
+ stw r5,_ESR(r11); \
+ addi r3,r1,STACK_FRAME_OVERHEAD; \
+ EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
+ NOCOPY, mcheck_transfer_to_handler, \
+ ret_from_mcheck_exc)
+
+#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
+ li r10,trap; \
+ stw r10,TRAP(r11); \
+ lis r10,msr@h; \
+ ori r10,r10,msr@l; \
+ copyee(r10, r9); \
+ bl tfer; \
+ .long hdlr; \
+ .long ret
+
+#define COPY_EE(d, s) rlwimi d,s,0,16,16
+#define NOCOPY(d, s)
+
+#define EXC_XFER_STD(n, hdlr) \
+ EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
+ ret_from_except_full)
+
+#define EXC_XFER_LITE(n, hdlr) \
+ EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
+ ret_from_except)
+
+#define EXC_XFER_EE(n, hdlr) \
+ EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
+ ret_from_except_full)
+
+#define EXC_XFER_EE_LITE(n, hdlr) \
+ EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
+ ret_from_except)
+
+
+#endif /* __HEAD_BOOKE_H__ */
--- /dev/null
+/*
+ * arch/ppc/platforms/lopec.c
+ *
+ * Setup routines for the Motorola LoPEC.
+ *
+ * Author: Dan Cox
+ * Maintainer: Tom Rini <trini@kernel.crashing.org>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/pci_ids.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+#include <linux/seq_file.h>
+#include <linux/initrd.h>
+#include <linux/console.h>
+#include <linux/root_dev.h>
+#include <linux/pci.h>
+
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/io.h>
+#include <asm/open_pic.h>
+#include <asm/i8259.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/mpc10x.h>
+#include <asm/hw_irq.h>
+#include <asm/prep_nvram.h>
+#include <asm/kgdb.h>
+
+/*
+ * Define all of the IRQ senses and polarities. Taken from the
+ * LoPEC Programmer's Reference Guide.
+ */
+static u_char lopec_openpic_initsenses[16] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 4 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 5 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 6 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 7 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 8 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 9 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 10 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 11 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 12 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 13 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ 14 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* IRQ 15 */
+};
+
+static inline int __init
+lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ int irq;
+ static char pci_irq_table[][4] = {
+ {16, 0, 0, 0}, /* ID 11 - Winbond */
+ {22, 0, 0, 0}, /* ID 12 - SCSI */
+ {0, 0, 0, 0}, /* ID 13 - nothing */
+ {17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */
+ {27, 0, 0, 0}, /* ID 15 - USB */
+ {23, 0, 0, 0}, /* ID 16 - PMC slot 1 */
+ {24, 0, 0, 0}, /* ID 17 - PMC slot 2 */
+ {25, 0, 0, 0}, /* ID 18 - PCI slot */
+ {0, 0, 0, 0}, /* ID 19 - nothing */
+ {0, 0, 0, 0}, /* ID 20 - nothing */
+ {0, 0, 0, 0}, /* ID 21 - nothing */
+ {0, 0, 0, 0}, /* ID 22 - nothing */
+ {0, 0, 0, 0}, /* ID 23 - nothing */
+ {0, 0, 0, 0}, /* ID 24 - PMC slot 1b */
+ {0, 0, 0, 0}, /* ID 25 - nothing */
+ {0, 0, 0, 0} /* ID 26 - PMC Slot 2b */
+ };
+ const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4;
+
+ irq = PCI_IRQ_TABLE_LOOKUP;
+ if (!irq)
+ return 0;
+
+ return irq;
+}
+
+static void __init
+lopec_setup_winbond_83553(struct pci_controller *hose)
+{
+ int devfn;
+
+ devfn = PCI_DEVFN(11,0);
+
+ /* IDE interrupt routing (primary 14, secondary 15) */
+ early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
+ /* PCI interrupt routing */
+ early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
+
+ /* ISA-PCI address decoder */
+ early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
+
+ /* RTC, kb, not used in PPC */
+ early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
+ early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
+ devfn = PCI_DEVFN(11, 1);
+ early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
+ early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
+}
+
+static void __init
+lopec_find_bridges(void)
+{
+ struct pci_controller *hose;
+
+ hose = pcibios_alloc_controller();
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
+ MPC10X_MAPB_EUMB_BASE) == 0) {
+
+ hose->mem_resources[0].end = 0xffffffff;
+ lopec_setup_winbond_83553(hose);
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = lopec_map_irq;
+ }
+}
+
+static int
+lopec_show_cpuinfo(struct seq_file *m)
+{
+ seq_printf(m, "machine\t\t: Motorola LoPEC\n");
+ return 0;
+}
+
+static u32
+lopec_irq_canonicalize(u32 irq)
+{
+ if (irq == 2)
+ return 9;
+ else
+ return irq;
+}
+
+static void
+lopec_restart(char *cmd)
+{
+#define LOPEC_SYSSTAT1 0xffe00000
+ /* force a hard reset, if possible */
+ unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
+ reg |= 0x80;
+ *((unsigned char *) LOPEC_SYSSTAT1) = reg;
+
+ local_irq_disable();
+ while(1);
+#undef LOPEC_SYSSTAT1
+}
+
+static void
+lopec_halt(void)
+{
+ local_irq_disable();
+ while(1);
+}
+
+static void
+lopec_power_off(void)
+{
+ lopec_halt();
+}
+
+#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
+int lopec_ide_ports_known = 0;
+static unsigned long lopec_ide_regbase[MAX_HWIFS];
+static unsigned long lopec_ide_ctl_regbase[MAX_HWIFS];
+static unsigned long lopec_idedma_regbase;
+
+static void
+lopec_ide_probe(void)
+{
+ struct pci_dev *dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
+ PCI_DEVICE_ID_WINBOND_82C105,
+ NULL);
+ lopec_ide_ports_known = 1;
+
+ if (dev) {
+ lopec_ide_regbase[0] = dev->resource[0].start;
+ lopec_ide_regbase[1] = dev->resource[2].start;
+ lopec_ide_ctl_regbase[0] = dev->resource[1].start;
+ lopec_ide_ctl_regbase[1] = dev->resource[3].start;
+ lopec_idedma_regbase = dev->resource[4].start;
+ }
+}
+
+static int
+lopec_ide_default_irq(unsigned long base)
+{
+ if (lopec_ide_ports_known == 0)
+ lopec_ide_probe();
+
+ if (base == lopec_ide_regbase[0])
+ return 14;
+ else if (base == lopec_ide_regbase[1])
+ return 15;
+ else
+ return 0;
+}
+
+static unsigned long
+lopec_ide_default_io_base(int index)
+{
+ if (lopec_ide_ports_known == 0)
+ lopec_ide_probe();
+ return lopec_ide_regbase[index];
+}
+
+static void __init
+lopec_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data,
+ unsigned long ctl, int *irq)
+{
+ unsigned long reg = data;
+ uint alt_status_base;
+ int i;
+
+ for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
+ hw->io_ports[i] = reg++;
+
+ if (data == lopec_ide_regbase[0]) {
+ alt_status_base = lopec_ide_ctl_regbase[0] + 2;
+ hw->irq = 14;
+ } else if (data == lopec_ide_regbase[1]) {
+ alt_status_base = lopec_ide_ctl_regbase[1] + 2;
+ hw->irq = 15;
+ } else {
+ alt_status_base = 0;
+ hw->irq = 0;
+ }
+
+ if (ctl)
+ hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
+ else
+ hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
+
+ if (irq != NULL)
+ *irq = hw->irq;
+
+}
+#endif /* BLK_DEV_IDE */
+
+static void __init
+lopec_init_IRQ(void)
+{
+ int i;
+
+ /*
+ * Provide the open_pic code with the correct table of interrupts.
+ */
+ OpenPIC_InitSenses = lopec_openpic_initsenses;
+ OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
+
+ mpc10x_set_openpic();
+
+ /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
+ openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
+ &i8259_irq);
+
+ /* Map i8259 interrupts */
+ for(i = 0; i < NUM_8259_INTERRUPTS; i++)
+ irq_desc[i].handler = &i8259_pic;
+
+ /*
+ * The EPIC allows for a read in the range of 0xFEF00000 ->
+ * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
+ */
+ i8259_init(0xfef00000);
+}
+
+static int __init
+lopec_request_io(void)
+{
+ outb(0x00, 0x4d0);
+ outb(0xc0, 0x4d1);
+
+ request_region(0x00, 0x20, "dma1");
+ request_region(0x20, 0x20, "pic1");
+ request_region(0x40, 0x20, "timer");
+ request_region(0x80, 0x10, "dma page reg");
+ request_region(0xa0, 0x20, "pic2");
+ request_region(0xc0, 0x20, "dma2");
+
+ return 0;
+}
+
+device_initcall(lopec_request_io);
+
+static void __init
+lopec_map_io(void)
+{
+ io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
+ io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
+}
+
+/*
+ * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
+ */
+static __inline__ void
+lopec_set_bat(void)
+{
+ mb();
+ mtspr(DBAT1U, 0xf8000ffe);
+ mtspr(DBAT1L, 0xf800002a);
+ mb();
+}
+
+TODC_ALLOC();
+
+static void __init
+lopec_setup_arch(void)
+{
+
+ TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
+ ioremap(0xffe80000, 0x8000), 8);
+
+ loops_per_jiffy = 100000000/HZ;
+
+ lopec_find_bridges();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#elif defined(CONFIG_ROOT_NFS)
+ ROOT_DEV = Root_NFS;
+#elif defined(CONFIG_BLK_DEV_IDEDISK)
+ ROOT_DEV = Root_HDA1;
+#else
+ ROOT_DEV = Root_SDA1;
+#endif
+
+#ifdef CONFIG_PPCBUG_NVRAM
+ /* Read in NVRAM data */
+ init_prep_nvram();
+
+ /* if no bootargs, look in NVRAM */
+ if ( cmd_line[0] == '\0' ) {
+ char *bootargs;
+ bootargs = prep_nvram_get_var("bootargs");
+ if (bootargs != NULL) {
+ strcpy(cmd_line, bootargs);
+ /* again.. */
+ strcpy(saved_command_line, cmd_line);
+ }
+ }
+#endif
+}
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ parse_bootinfo(find_bootinfo());
+ lopec_set_bat();
+
+ isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
+ isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
+ pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
+ ISA_DMA_THRESHOLD = 0x00ffffff;
+ DMA_MODE_READ = 0x44;
+ DMA_MODE_WRITE = 0x48;
+
+ ppc_md.setup_arch = lopec_setup_arch;
+ ppc_md.show_cpuinfo = lopec_show_cpuinfo;
+ ppc_md.irq_canonicalize = lopec_irq_canonicalize;
+ ppc_md.init_IRQ = lopec_init_IRQ;
+ ppc_md.get_irq = openpic_get_irq;
+
+ ppc_md.restart = lopec_restart;
+ ppc_md.power_off = lopec_power_off;
+ ppc_md.halt = lopec_halt;
+
+ ppc_md.setup_io_mappings = lopec_map_io;
+
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+ ppc_md.calibrate_decr = todc_calibrate_decr;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+
+#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
+ ppc_ide_md.default_irq = lopec_ide_default_irq;
+ ppc_ide_md.default_io_base = lopec_ide_default_io_base;
+ ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
+#endif
+#ifdef CONFIG_SERIAL_TEXT_DEBUG
+ ppc_md.progress = gen550_progress;
+#endif
+}
--- /dev/null
+/*
+ * include/asm-ppc/lopec_serial.h
+ *
+ * Definitions for Motorola LoPEC board.
+ *
+ * Author: Dan Cox
+ * danc@mvista.com (or, alternately, source@mvista.com)
+ *
+ * 2001 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __H_LOPEC_SERIAL
+#define __H_LOPEC_SERIAL
+
+#define RS_TABLE_SIZE 3
+
+#define BASE_BAUD (1843200 / 16)
+
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
+#endif
+
+#define SERIAL_PORT_DFNS \
+ { 0, BASE_BAUD, 0xffe10000, 29, STD_COM_FLAGS, \
+ iomem_base: (u8 *) 0xffe10000, \
+ io_type: SERIAL_IO_MEM }, \
+ { 0, BASE_BAUD, 0xffe11000, 20, STD_COM_FLAGS, \
+ iomem_base: (u8 *) 0xffe11000, \
+ io_type: SERIAL_IO_MEM }, \
+ { 0, BASE_BAUD, 0xffe12000, 21, STD_COM_FLAGS, \
+ iomem_base: (u8 *) 0xffe12000, \
+ io_type: SERIAL_IO_MEM }
+
+#endif
--- /dev/null
+/*
+ * arch/ppc/platforms/mvme5100.c
+ *
+ * Board setup routines for the Motorola MVME5100.
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/initrd.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/ide.h>
+#include <linux/seq_file.h>
+#include <linux/kdev_t.h>
+#include <linux/root_dev.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/open_pic.h>
+#include <asm/i8259.h>
+#include <asm/todc.h>
+#include <asm/pci-bridge.h>
+#include <asm/bootinfo.h>
+#include <asm/hawk.h>
+
+#include <platforms/pplus.h>
+#include <platforms/mvme5100.h>
+
+static u_char mvme5100_openpic_initsenses[16] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* i8259 cascade */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* TL16C550 UART 1,2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet1 front panel or P2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Hawk Watchdog 1,2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* DS1621 thermal alarm */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT0# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT1# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT2# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT3# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTA#, PMC2 INTB# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTB#, PMC2 INTC# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTC#, PMC2 INTD# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTD#, PMC2 INTA# */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet 2 (front panel) */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Abort Switch */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* RTC Alarm */
+};
+
+static inline int
+mvme5100_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ int irq;
+
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { 0, 0, 0, 0 }, /* IDSEL 11 - Winbond */
+ { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
+ { 21, 22, 23, 24 }, /* IDSEL 13 - Universe II */
+ { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
+ { 0, 0, 0, 0 }, /* IDSEL 15 - unused */
+ { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
+ { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
+ { 0, 0, 0, 0 }, /* IDSEL 18 - unused */
+ { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
+ { 0, 0, 0, 0 }, /* IDSEL 20 - PMCSPAN */
+ };
+
+ const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
+ irq = PCI_IRQ_TABLE_LOOKUP;
+ /* If lookup is zero, always return 0 */
+ if (!irq)
+ return 0;
+ else
+#ifdef CONFIG_MVME5100_IPMC761_PRESENT
+ /* If IPMC761 present, return table value */
+ return irq;
+#else
+ /* If IPMC761 not present, we don't have an i8259 so adjust */
+ return (irq - NUM_8259_INTERRUPTS);
+#endif
+}
+
+static void
+mvme5100_pcibios_fixup_resources(struct pci_dev *dev)
+{
+ int i;
+
+ if ((dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
+ (dev->device == PCI_DEVICE_ID_MOTOROLA_HAWK))
+ for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
+ {
+ dev->resource[i].start = 0;
+ dev->resource[i].end = 0;
+ }
+}
+
+static void __init
+mvme5100_setup_bridge(void)
+{
+ struct pci_controller* hose;
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
+
+ pci_init_resource(&hose->io_resource, MVME5100_PCI_LOWER_IO,
+ MVME5100_PCI_UPPER_IO, IORESOURCE_IO,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[0], MVME5100_PCI_LOWER_MEM,
+ MVME5100_PCI_UPPER_MEM, IORESOURCE_MEM,
+ "PCI host bridge");
+
+ hose->io_space.start = MVME5100_PCI_LOWER_IO;
+ hose->io_space.end = MVME5100_PCI_UPPER_IO;
+ hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
+ hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
+ hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
+
+ /* Use indirect method of Hawk */
+ setup_indirect_pci(hose, MVME5100_PCI_CONFIG_ADDR,
+ MVME5100_PCI_CONFIG_DATA);
+
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = mvme5100_map_irq;
+}
+
+static void __init
+mvme5100_setup_arch(void)
+{
+ if ( ppc_md.progress )
+ ppc_md.progress("mvme5100_setup_arch: enter", 0);
+
+ loops_per_jiffy = 50000000 / HZ;
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_SDA2;
+#endif
+
+ if ( ppc_md.progress )
+ ppc_md.progress("mvme5100_setup_arch: find_bridges", 0);
+
+ /* Setup PCI host bridge */
+ mvme5100_setup_bridge();
+
+ /* Find and map our OpenPIC */
+ hawk_mpic_init(MVME5100_PCI_MEM_OFFSET);
+ OpenPIC_InitSenses = mvme5100_openpic_initsenses;
+ OpenPIC_NumInitSenses = sizeof(mvme5100_openpic_initsenses);
+
+ printk("MVME5100 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
+
+ if ( ppc_md.progress )
+ ppc_md.progress("mvme5100_setup_arch: exit", 0);
+
+ return;
+}
+
+static void __init
+mvme5100_init2(void)
+{
+#ifdef CONFIG_MVME5100_IPMC761_PRESENT
+ request_region(0x00,0x20,"dma1");
+ request_region(0x20,0x20,"pic1");
+ request_region(0x40,0x20,"timer");
+ request_region(0x80,0x10,"dma page reg");
+ request_region(0xa0,0x20,"pic2");
+ request_region(0xc0,0x20,"dma2");
+#endif
+ return;
+}
+
+/*
+ * Interrupt setup and service.
+ * Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC.
+ */
+static void __init
+mvme5100_init_IRQ(void)
+{
+#ifdef CONFIG_MVME5100_IPMC761_PRESENT
+ int i;
+#endif
+
+ if ( ppc_md.progress )
+ ppc_md.progress("init_irq: enter", 0);
+
+ openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
+#ifdef CONFIG_MVME5100_IPMC761_PRESENT
+ openpic_init(NUM_8259_INTERRUPTS);
+ openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
+ &i8259_irq);
+
+ /* Map i8259 interrupts. */
+ for (i = 0; i < NUM_8259_INTERRUPTS; i++)
+ irq_desc[i].handler = &i8259_pic;
+
+ i8259_init(NULL);
+#else
+ openpic_init(0);
+#endif
+
+ if ( ppc_md.progress )
+ ppc_md.progress("init_irq: exit", 0);
+
+ return;
+}
+
+/*
+ * Set BAT 3 to map 0xf0000000 to end of physical memory space.
+ */
+static __inline__ void
+mvme5100_set_bat(void)
+{
+ mb();
+ mtspr(DBAT1U, 0xf0001ffe);
+ mtspr(DBAT1L, 0xf000002a);
+ mb();
+}
+
+static unsigned long __init
+mvme5100_find_end_of_memory(void)
+{
+ return hawk_get_mem_size(MVME5100_HAWK_SMC_BASE);
+}
+
+static void __init
+mvme5100_map_io(void)
+{
+ io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
+ ioremap_base = 0xfe000000;
+}
+
+static void
+mvme5100_reset_board(void)
+{
+ local_irq_disable();
+
+ /* Set exception prefix high - to the firmware */
+ _nmask_and_or_msr(0, MSR_IP);
+
+ out_8((u_char *)MVME5100_BOARD_MODRST_REG, 0x01);
+
+ return;
+}
+
+static void
+mvme5100_restart(char *cmd)
+{
+ volatile ulong i = 10000000;
+
+ mvme5100_reset_board();
+
+ while (i-- > 0);
+ panic("restart failed\n");
+}
+
+static void
+mvme5100_halt(void)
+{
+ local_irq_disable();
+ while (1);
+}
+
+static void
+mvme5100_power_off(void)
+{
+ mvme5100_halt();
+}
+
+static int
+mvme5100_show_cpuinfo(struct seq_file *m)
+{
+ seq_printf(m, "vendor\t\t: Motorola\n");
+ seq_printf(m, "machine\t\t: MVME5100\n");
+
+ return 0;
+}
+
+TODC_ALLOC();
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ parse_bootinfo(find_bootinfo());
+ mvme5100_set_bat();
+
+ isa_io_base = MVME5100_ISA_IO_BASE;
+ isa_mem_base = MVME5100_ISA_MEM_BASE;
+ pci_dram_offset = MVME5100_PCI_DRAM_OFFSET;
+
+ ppc_md.setup_arch = mvme5100_setup_arch;
+ ppc_md.show_cpuinfo = mvme5100_show_cpuinfo;
+ ppc_md.init_IRQ = mvme5100_init_IRQ;
+ ppc_md.get_irq = openpic_get_irq;
+ ppc_md.init = mvme5100_init2;
+
+ ppc_md.restart = mvme5100_restart;
+ ppc_md.power_off = mvme5100_power_off;
+ ppc_md.halt = mvme5100_halt;
+
+ ppc_md.find_end_of_memory = mvme5100_find_end_of_memory;
+ ppc_md.setup_io_mappings = mvme5100_map_io;
+
+ TODC_INIT(TODC_TYPE_MK48T37, MVME5100_NVRAM_AS0, MVME5100_NVRAM_AS1,
+ MVME5100_NVRAM_DATA, 8);
+
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+ ppc_md.calibrate_decr = todc_calibrate_decr;
+
+ ppc_md.nvram_read_val = todc_m48txx_read_val;
+ ppc_md.nvram_write_val = todc_m48txx_write_val;
+}
--- /dev/null
+/*
+ * arch/ppc/platforms/pq2ads.c
+ *
+ * PQ2ADS platform support
+ *
+ * Author: Kumar Gala <kumar.gala@freescale.com>
+ * Derived from: est8260_setup.c by Allen Curtis
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+
+#include <asm/mpc8260.h>
+
+void __init
+m82xx_board_init(void)
+{
+ /* Enable the 2nd UART port */
+ *(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_RS232_EN2;
+}
--- /dev/null
+/*
+ * m8xx_wdt.c - MPC8xx watchdog driver
+ *
+ * Author: Florian Schirmer <jolt@tuxbox.org>
+ *
+ * 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/8xx_immap.h>
+#include <syslib/m8xx_wdt.h>
+
+static int wdt_timeout;
+
+void m8xx_wdt_reset(void)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+
+ imap->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
+ imap->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
+}
+
+static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+
+ m8xx_wdt_reset();
+
+ imap->im_sit.sit_piscr |= PISCR_PS; /* clear irq */
+
+ return IRQ_HANDLED;
+}
+
+void __init m8xx_wdt_handler_install(bd_t * binfo)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ u32 pitc;
+ u32 sypcr;
+ u32 pitrtclk;
+
+ sypcr = imap->im_siu_conf.sc_sypcr;
+
+ if (!(sypcr & 0x04)) {
+ printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
+ sypcr);
+ return;
+ }
+
+ m8xx_wdt_reset();
+
+ printk(KERN_NOTICE
+ "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n",
+ (sypcr >> 16), sypcr & 0x01);
+
+ wdt_timeout = (sypcr >> 16) & 0xFFFF;
+
+ if (!wdt_timeout)
+ wdt_timeout = 0xFFFF;
+
+ if (sypcr & 0x01)
+ wdt_timeout *= 2048;
+
+ /*
+ * Fire trigger if half of the wdt ticked down
+ */
+
+ if (imap->im_sit.sit_rtcsc & RTCSC_38K)
+ pitrtclk = 9600;
+ else
+ pitrtclk = 8192;
+
+ if ((wdt_timeout) > (UINT_MAX / pitrtclk))
+ pitc = wdt_timeout / binfo->bi_intfreq * pitrtclk / 2;
+ else
+ pitc = pitrtclk * wdt_timeout / binfo->bi_intfreq / 2;
+
+ imap->im_sit.sit_pitc = pitc << 16;
+ imap->im_sit.sit_piscr =
+ (mk_int_int_mask(PIT_INTERRUPT) << 8) | PISCR_PIE | PISCR_PTE;
+
+ if (request_irq(PIT_INTERRUPT, m8xx_wdt_interrupt, 0, "watchdog", NULL))
+ panic("m8xx_wdt: could not allocate watchdog irq!");
+
+ printk(KERN_NOTICE
+ "m8xx_wdt: keep-alive trigger installed (PITC: 0x%04X)\n", pitc);
+
+ wdt_timeout /= binfo->bi_intfreq;
+}
+
+int m8xx_wdt_get_timeout(void)
+{
+ return wdt_timeout;
+}
--- /dev/null
+/*
+ * Author: Florian Schirmer <jolt@tuxbox.org>
+ *
+ * 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef _PPC_SYSLIB_M8XX_WDT_H
+#define _PPC_SYSLIB_M8XX_WDT_H
+
+extern void m8xx_wdt_handler_install(bd_t * binfo);
+extern int m8xx_wdt_get_timeout(void);
+extern void m8xx_wdt_reset(void);
+
+#endif /* _PPC_SYSLIB_M8XX_WDT_H */
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config DEBUG_STACKOVERFLOW
+ bool "Check for stack overflows"
+ depends on DEBUG_KERNEL
+
+config DEBUG_STACK_USAGE
+ bool "Stack utilization instrumentation"
+ depends on DEBUG_KERNEL
+ help
+ Enables the display of the minimum amount of free stack which each
+ task has ever had available in the sysrq-T and sysrq-P debug output.
+
+ This option will slow down process creation somewhat.
+
+config DEBUGGER
+ bool "Enable debugger hooks"
+ depends on DEBUG_KERNEL
+ help
+ Include in-kernel hooks for kernel debuggers. Unless you are
+ intending to debug the kernel, say N here.
+
+config XMON
+ bool "Include xmon kernel debugger"
+ depends on DEBUGGER
+ help
+ Include in-kernel hooks for the xmon kernel monitor/debugger.
+ Unless you are intending to debug the kernel, say N here.
+
+config XMON_DEFAULT
+ bool "Enable xmon by default"
+ depends on XMON
+
+config PPCDBG
+ bool "Include PPCDBG realtime debugging"
+ depends on DEBUG_KERNEL
+
+config IRQSTACKS
+ bool "Use separate kernel stacks when processing interrupts"
+ help
+ If you say Y here the kernel will use separate kernel stacks
+ for handling hard and soft interrupts. This can help avoid
+ overflowing the process kernel stacks.
+
+config SCHEDSTATS
+ bool "Collect scheduler statistics"
+ depends on DEBUG_KERNEL && PROC_FS
+ help
+ If you say Y here, additional code will be inserted into the
+ scheduler and related routines to collect statistics about
+ scheduler behavior and provide them in /proc/schedstat. These
+ stats may be useful for both tuning and debugging the scheduler
+ If you aren't debugging the scheduler or trying to tune a specific
+ application, you can say N to avoid the very slight overhead
+ this adds.
+
+endmenu
--- /dev/null
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+
+/*
+ * Here comes the ppc64 implementation of the IOMAP
+ * interfaces.
+ */
+unsigned int fastcall ioread8(void __iomem *addr)
+{
+ return readb(addr);
+}
+unsigned int fastcall ioread16(void __iomem *addr)
+{
+ return readw(addr);
+}
+unsigned int fastcall ioread32(void __iomem *addr)
+{
+ return readl(addr);
+}
+EXPORT_SYMBOL(ioread8);
+EXPORT_SYMBOL(ioread16);
+EXPORT_SYMBOL(ioread32);
+
+void fastcall iowrite8(u8 val, void __iomem *addr)
+{
+ writeb(val, addr);
+}
+void fastcall iowrite16(u16 val, void __iomem *addr)
+{
+ writew(val, addr);
+}
+void fastcall iowrite32(u32 val, void __iomem *addr)
+{
+ writel(val, addr);
+}
+EXPORT_SYMBOL(iowrite8);
+EXPORT_SYMBOL(iowrite16);
+EXPORT_SYMBOL(iowrite32);
+
+/*
+ * These are the "repeat read/write" functions. Note the
+ * non-CPU byte order. We do things in "IO byteorder"
+ * here.
+ *
+ * FIXME! We could make these do EEH handling if we really
+ * wanted. Not clear if we do.
+ */
+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ _insb((u8 __force *) addr, dst, count);
+}
+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ _insw_ns((u16 __force *) addr, dst, count);
+}
+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ _insl_ns((u32 __force *) addr, dst, count);
+}
+EXPORT_SYMBOL(ioread8_rep);
+EXPORT_SYMBOL(ioread16_rep);
+EXPORT_SYMBOL(ioread32_rep);
+
+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ _outsb((u8 __force *) addr, src, count);
+}
+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ _outsw_ns((u16 __force *) addr, src, count);
+}
+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ _outsl_ns((u32 __force *) addr, src, count);
+}
+EXPORT_SYMBOL(iowrite8_rep);
+EXPORT_SYMBOL(iowrite16_rep);
+EXPORT_SYMBOL(iowrite32_rep);
+
+void __iomem *ioport_map(unsigned long port, unsigned int len)
+{
+ if (!_IO_IS_VALID(port))
+ return NULL;
+ return (void __iomem *) (port+pci_io_base);
+}
+
+void ioport_unmap(void __iomem *addr)
+{
+ /* Nothing to do */
+}
+EXPORT_SYMBOL(ioport_map);
+EXPORT_SYMBOL(ioport_unmap);
+
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
+{
+ unsigned long start = pci_resource_start(dev, bar);
+ unsigned long len = pci_resource_len(dev, bar);
+ unsigned long flags = pci_resource_flags(dev, bar);
+
+ if (!len)
+ return NULL;
+ if (max && len > max)
+ len = max;
+ if (flags & IORESOURCE_IO)
+ return ioport_map(start, len);
+ if (flags & IORESOURCE_MEM)
+ return (void __iomem *) start;
+ /* What? */
+ return NULL;
+}
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{
+ /* Nothing to do */
+}
+EXPORT_SYMBOL(pci_iomap);
+EXPORT_SYMBOL(pci_iounmap);
--- /dev/null
+/*
+ * linux/arch/ppc/kernel/setup.c
+ *
+ * Copyright (C) 1995 Linus Torvalds
+ * Adapted from 'alpha' version by Gary Thomas
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * Modified by PPC64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * bootup setup stuff..
+ */
+
+#undef DEBUG
+
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/slab.h>
+#include <linux/user.h>
+#include <linux/a.out.h>
+#include <linux/tty.h>
+#include <linux/major.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/console.h>
+#include <linux/pci.h>
+#include <linux/version.h>
+#include <linux/adb.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/prom.h>
+#include <asm/rtas.h>
+#include <asm/pci-bridge.h>
+#include <asm/iommu.h>
+#include <asm/dma.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/naca.h>
+#include <asm/time.h>
+#include <asm/nvram.h>
+
+#include "i8259.h"
+#include "open_pic.h"
+#include <asm/xics.h>
+#include <asm/ppcdebug.h>
+#include <asm/cputable.h>
+
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+extern void pSeries_init_openpic(void);
+
+extern void find_and_init_phbs(void);
+extern void pSeries_final_fixup(void);
+
+extern void pSeries_get_boot_time(struct rtc_time *rtc_time);
+extern void pSeries_get_rtc_time(struct rtc_time *rtc_time);
+extern int pSeries_set_rtc_time(struct rtc_time *rtc_time);
+extern void find_udbg_vterm(void);
+extern void SystemReset_FWNMI(void), MachineCheck_FWNMI(void); /* from head.S */
+int fwnmi_active; /* TRUE if an FWNMI handler is present */
+
+unsigned long virtPython0Facilities = 0; // python0 facility area (memory mapped io) (64-bit format) VIRTUAL address.
+
+extern unsigned long loops_per_jiffy;
+
+extern unsigned long ppc_proc_freq;
+extern unsigned long ppc_tb_freq;
+
+void pSeries_get_cpuinfo(struct seq_file *m)
+{
+ struct device_node *root;
+ const char *model = "";
+
+ root = of_find_node_by_path("/");
+ if (root)
+ model = get_property(root, "model", NULL);
+ seq_printf(m, "machine\t\t: CHRP %s\n", model);
+ of_node_put(root);
+}
+
+/* Initialize firmware assisted non-maskable interrupts if
+ * the firmware supports this feature.
+ *
+ */
+static void __init fwnmi_init(void)
+{
+ int ret;
+ int ibm_nmi_register = rtas_token("ibm,nmi-register");
+ if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE)
+ return;
+ ret = rtas_call(ibm_nmi_register, 2, 1, NULL,
+ __pa((unsigned long)SystemReset_FWNMI),
+ __pa((unsigned long)MachineCheck_FWNMI));
+ if (ret == 0)
+ fwnmi_active = 1;
+}
+
+static void __init pSeries_setup_arch(void)
+{
+ struct device_node *root;
+ unsigned int *opprop;
+
+ /* Fixup ppc_md depending on the type of interrupt controller */
+ if (naca->interrupt_controller == IC_OPEN_PIC) {
+ ppc_md.init_IRQ = pSeries_init_openpic;
+ ppc_md.get_irq = openpic_get_irq;
+ } else {
+ ppc_md.init_IRQ = xics_init_IRQ;
+ ppc_md.get_irq = xics_get_irq;
+ }
+
+#ifdef CONFIG_SMP
+ smp_init_pSeries();
+#endif
+ /* openpic global configuration register (64-bit format). */
+ /* openpic Interrupt Source Unit pointer (64-bit format). */
+ /* python0 facility area (mmio) (64-bit format) REAL address. */
+
+ /* init to some ~sane value until calibrate_delay() runs */
+ loops_per_jiffy = 50000000;
+
+ if (ROOT_DEV == 0) {
+ printk("No ramdisk, default root is /dev/sda2\n");
+ ROOT_DEV = Root_SDA2;
+ }
+
+ fwnmi_init();
+
+ /* Find and initialize PCI host bridges */
+ /* iSeries needs to be done much later. */
+ eeh_init();
+ find_and_init_phbs();
+
+ /* Find the Open PIC if present */
+ root = of_find_node_by_path("/");
+ opprop = (unsigned int *) get_property(root,
+ "platform-open-pic", NULL);
+ if (opprop != 0) {
+ int n = prom_n_addr_cells(root);
+ unsigned long openpic;
+
+ for (openpic = 0; n > 0; --n)
+ openpic = (openpic << 32) + *opprop++;
+ printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic);
+ OpenPIC_Addr = __ioremap(openpic, 0x40000, _PAGE_NO_CACHE);
+ }
+ of_node_put(root);
+
+#ifdef CONFIG_DUMMY_CONSOLE
+ conswitchp = &dummy_con;
+#endif
+
+ pSeries_nvram_init();
+}
+
+static int __init pSeries_init_panel(void)
+{
+ /* Manually leave the kernel version on the panel. */
+ ppc_md.progress("Linux ppc64\n", 0);
+ ppc_md.progress(UTS_RELEASE, 0);
+
+ return 0;
+}
+arch_initcall(pSeries_init_panel);
+
+
+
+void __init pSeries_find_serial_port(void)
+{
+ struct device_node *np;
+ unsigned long encode_phys_size = 32;
+ u32 *sizeprop;
+
+ struct isa_reg_property {
+ u32 space;
+ u32 address;
+ u32 size;
+ };
+ struct pci_reg_property {
+ struct pci_address addr;
+ u32 size_hi;
+ u32 size_lo;
+ };
+
+ DBG(" -> pSeries_find_serial_port()\n");
+
+ naca->serialPortAddr = 0;
+
+ np = of_find_node_by_path("/");
+ if (!np)
+ return;
+ sizeprop = (u32 *)get_property(np, "#size-cells", NULL);
+ if (sizeprop != NULL)
+ encode_phys_size = (*sizeprop) << 5;
+
+ for (np = NULL; (np = of_find_node_by_type(np, "serial"));) {
+ struct device_node *isa, *pci;
+ struct isa_reg_property *reg;
+ union pci_range *rangesp;
+ char *typep;
+
+ typep = (char *)get_property(np, "ibm,aix-loc", NULL);
+ if ((typep == NULL) || (typep && strcmp(typep, "S1")))
+ continue;
+
+ reg = (struct isa_reg_property *)get_property(np, "reg", NULL);
+
+ isa = of_get_parent(np);
+ if (!isa) {
+ DBG("no isa parent found\n");
+ break;
+ }
+ pci = of_get_parent(isa);
+ if (!pci) {
+ DBG("no pci parent found\n");
+ break;
+ }
+
+ rangesp = (union pci_range *)get_property(pci, "ranges", NULL);
+
+ if ( encode_phys_size == 32 )
+ naca->serialPortAddr = rangesp->pci32.phys+reg->address;
+ else {
+ naca->serialPortAddr =
+ ((((unsigned long)rangesp->pci64.phys_hi) << 32)
+ |
+ (rangesp->pci64.phys_lo)) + reg->address;
+ }
+ break;
+ }
+
+ DBG(" <- pSeries_find_serial_port()\n");
+}
+
+
+/* Build up the firmware_features bitmask field
+ * using contents of device-tree/ibm,hypertas-functions.
+ * Ultimately this functionality may be moved into prom.c prom_init().
+ */
+void __init fw_feature_init(void)
+{
+ struct device_node * dn;
+ char * hypertas;
+ unsigned int len;
+
+ DBG(" -> fw_feature_init()\n");
+
+ cur_cpu_spec->firmware_features = 0;
+ dn = of_find_node_by_path("/rtas");
+ if (dn == NULL) {
+ printk(KERN_ERR "WARNING ! Cannot find RTAS in device-tree !\n");
+ goto no_rtas;
+ }
+
+ hypertas = get_property(dn, "ibm,hypertas-functions", &len);
+ if (hypertas) {
+ while (len > 0){
+ int i, hypertas_len;
+ /* check value against table of strings */
+ for(i=0; i < FIRMWARE_MAX_FEATURES ;i++) {
+ if ((firmware_features_table[i].name) &&
+ (strcmp(firmware_features_table[i].name,hypertas))==0) {
+ /* we have a match */
+ cur_cpu_spec->firmware_features |=
+ (firmware_features_table[i].val);
+ break;
+ }
+ }
+ hypertas_len = strlen(hypertas);
+ len -= hypertas_len +1;
+ hypertas+= hypertas_len +1;
+ }
+ }
+
+ of_node_put(dn);
+ no_rtas:
+ printk(KERN_INFO "firmware_features = 0x%lx\n",
+ cur_cpu_spec->firmware_features);
+
+ DBG(" <- fw_feature_init()\n");
+}
+
+
+static void __init pSeries_discover_pic(void)
+{
+ struct device_node *np;
+ char *typep;
+
+ /*
+ * Setup interrupt mapping options that are needed for finish_device_tree
+ * to properly parse the OF interrupt tree & do the virtual irq mapping
+ */
+ __irq_offset_value = NUM_ISA_INTERRUPTS;
+ naca->interrupt_controller = IC_INVALID;
+ for (np = NULL; (np = of_find_node_by_name(np, "interrupt-controller"));) {
+ typep = (char *)get_property(np, "compatible", NULL);
+ if (strstr(typep, "open-pic"))
+ naca->interrupt_controller = IC_OPEN_PIC;
+ else if (strstr(typep, "ppc-xicp"))
+ naca->interrupt_controller = IC_PPC_XIC;
+ else
+ printk("initialize_naca: failed to recognize"
+ " interrupt-controller\n");
+ break;
+ }
+}
+
+/*
+ * Early initialization. Relocation is on but do not reference unbolted pages
+ */
+static void __init pSeries_init_early(void)
+{
+ void *comport;
+ int iommu_off = 0;
+
+ DBG(" -> pSeries_init_early()\n");
+
+ fw_feature_init();
+
+ if (systemcfg->platform & PLATFORM_LPAR)
+ hpte_init_lpar();
+ else {
+ hpte_init_native();
+ iommu_off = (of_chosen &&
+ get_property(of_chosen, "linux,iommu-off", NULL));
+ }
+
+ pSeries_find_serial_port();
+
+ if (systemcfg->platform & PLATFORM_LPAR)
+ find_udbg_vterm();
+ else if (naca->serialPortAddr) {
+ /* Map the uart for udbg. */
+ comport = (void *)__ioremap(naca->serialPortAddr, 16, _PAGE_NO_CACHE);
+ udbg_init_uart(comport);
+
+ ppc_md.udbg_putc = udbg_putc;
+ ppc_md.udbg_getc = udbg_getc;
+ ppc_md.udbg_getc_poll = udbg_getc_poll;
+ DBG("Hello World !\n");
+ }
+
+
+ if (iommu_off)
+ pci_dma_init_direct();
+ else
+ tce_init_pSeries();
+
+ pSeries_discover_pic();
+
+ DBG(" <- pSeries_init_early()\n");
+}
+
+
+static void pSeries_progress(char *s, unsigned short hex)
+{
+ struct device_node *root;
+ int width, *p;
+ char *os;
+ static int display_character, set_indicator;
+ static int max_width;
+ static spinlock_t progress_lock = SPIN_LOCK_UNLOCKED;
+ static int pending_newline = 0; /* did last write end with unprinted newline? */
+
+ if (!rtas.base)
+ return;
+
+ if (max_width == 0) {
+ if ((root = find_path_device("/rtas")) &&
+ (p = (unsigned int *)get_property(root,
+ "ibm,display-line-length",
+ NULL)))
+ max_width = *p;
+ else
+ max_width = 0x10;
+ display_character = rtas_token("display-character");
+ set_indicator = rtas_token("set-indicator");
+ }
+
+ if (display_character == RTAS_UNKNOWN_SERVICE) {
+ /* use hex display if available */
+ if (set_indicator != RTAS_UNKNOWN_SERVICE)
+ rtas_call(set_indicator, 3, 1, NULL, 6, 0, hex);
+ return;
+ }
+
+ spin_lock(&progress_lock);
+
+ /*
+ * Last write ended with newline, but we didn't print it since
+ * it would just clear the bottom line of output. Print it now
+ * instead.
+ *
+ * If no newline is pending, print a CR to start output at the
+ * beginning of the line.
+ */
+ if (pending_newline) {
+ rtas_call(display_character, 1, 1, NULL, '\r');
+ rtas_call(display_character, 1, 1, NULL, '\n');
+ pending_newline = 0;
+ } else {
+ rtas_call(display_character, 1, 1, NULL, '\r');
+ }
+
+ width = max_width;
+ os = s;
+ while (*os) {
+ if (*os == '\n' || *os == '\r') {
+ /* Blank to end of line. */
+ while (width-- > 0)
+ rtas_call(display_character, 1, 1, NULL, ' ');
+
+ /* If newline is the last character, save it
+ * until next call to avoid bumping up the
+ * display output.
+ */
+ if (*os == '\n' && !os[1]) {
+ pending_newline = 1;
+ spin_unlock(&progress_lock);
+ return;
+ }
+
+ /* RTAS wants CR-LF, not just LF */
+
+ if (*os == '\n') {
+ rtas_call(display_character, 1, 1, NULL, '\r');
+ rtas_call(display_character, 1, 1, NULL, '\n');
+ } else {
+ /* CR might be used to re-draw a line, so we'll
+ * leave it alone and not add LF.
+ */
+ rtas_call(display_character, 1, 1, NULL, *os);
+ }
+
+ width = max_width;
+ } else {
+ width--;
+ rtas_call(display_character, 1, 1, NULL, *os);
+ }
+
+ os++;
+
+ /* if we overwrite the screen length */
+ if (width <= 0)
+ while ((*os != 0) && (*os != '\n') && (*os != '\r'))
+ os++;
+ }
+
+ /* Blank to end of line. */
+ while (width-- > 0)
+ rtas_call(display_character, 1, 1, NULL, ' ');
+
+ spin_unlock(&progress_lock);
+}
+
+extern void setup_default_decr(void);
+
+/* Some sane defaults: 125 MHz timebase, 1GHz processor */
+#define DEFAULT_TB_FREQ 125000000UL
+#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
+
+static void __init pSeries_calibrate_decr(void)
+{
+ struct device_node *cpu;
+ struct div_result divres;
+ unsigned int *fp;
+ int node_found;
+
+ /*
+ * The cpu node should have a timebase-frequency property
+ * to tell us the rate at which the decrementer counts.
+ */
+ cpu = of_find_node_by_type(NULL, "cpu");
+
+ ppc_tb_freq = DEFAULT_TB_FREQ; /* hardcoded default */
+ node_found = 0;
+ if (cpu != 0) {
+ fp = (unsigned int *)get_property(cpu, "timebase-frequency",
+ NULL);
+ if (fp != 0) {
+ node_found = 1;
+ ppc_tb_freq = *fp;
+ }
+ }
+ if (!node_found)
+ printk(KERN_ERR "WARNING: Estimating decrementer frequency "
+ "(not found)\n");
+
+ ppc_proc_freq = DEFAULT_PROC_FREQ;
+ node_found = 0;
+ if (cpu != 0) {
+ fp = (unsigned int *)get_property(cpu, "clock-frequency",
+ NULL);
+ if (fp != 0) {
+ node_found = 1;
+ ppc_proc_freq = *fp;
+ }
+ }
+ if (!node_found)
+ printk(KERN_ERR "WARNING: Estimating processor frequency "
+ "(not found)\n");
+
+ of_node_put(cpu);
+
+ printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
+ ppc_tb_freq/1000000, ppc_tb_freq%1000000);
+ printk(KERN_INFO "time_init: processor frequency = %lu.%.6lu MHz\n",
+ ppc_proc_freq/1000000, ppc_proc_freq%1000000);
+
+ tb_ticks_per_jiffy = ppc_tb_freq / HZ;
+ tb_ticks_per_sec = tb_ticks_per_jiffy * HZ;
+ tb_ticks_per_usec = ppc_tb_freq / 1000000;
+ tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
+ div128_by_32(1024*1024, 0, tb_ticks_per_sec, &divres);
+ tb_to_xs = divres.result_low;
+
+ setup_default_decr();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+extern struct machdep_calls pSeries_md;
+
+static int __init pSeries_probe(int platform)
+{
+ if (platform != PLATFORM_PSERIES &&
+ platform != PLATFORM_PSERIES_LPAR)
+ return 0;
+
+ /* if we have some ppc_md fixups for LPAR to do, do
+ * it here ...
+ */
+
+ return 1;
+}
+
+struct machdep_calls __initdata pSeries_md = {
+ .probe = pSeries_probe,
+ .setup_arch = pSeries_setup_arch,
+ .init_early = pSeries_init_early,
+ .get_cpuinfo = pSeries_get_cpuinfo,
+ .log_error = pSeries_log_error,
+ .pcibios_fixup = pSeries_final_fixup,
+ .restart = rtas_restart,
+ .power_off = rtas_power_off,
+ .halt = rtas_halt,
+ .panic = rtas_os_term,
+ .get_boot_time = pSeries_get_boot_time,
+ .get_rtc_time = pSeries_get_rtc_time,
+ .set_rtc_time = pSeries_set_rtc_time,
+ .calibrate_decr = pSeries_calibrate_decr,
+ .progress = pSeries_progress,
+};
--- /dev/null
+/*
+ *
+ *
+ * Procedures for interfacing to Open Firmware.
+ *
+ * Paul Mackerras August 1996.
+ * Copyright (C) 1996 Paul Mackerras.
+ *
+ * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
+ * {engebret|bergner}@us.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#undef DEBUG_PROM
+
+#include <stdarg.h>
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/version.h>
+#include <linux/threads.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include <linux/stringify.h>
+#include <linux/delay.h>
+#include <linux/initrd.h>
+#include <asm/prom.h>
+#include <asm/rtas.h>
+#include <asm/abs_addr.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/system.h>
+#include <asm/mmu.h>
+#include <asm/pgtable.h>
+#include <asm/bitops.h>
+#include <asm/naca.h>
+#include <asm/pci.h>
+#include <asm/iommu.h>
+#include <asm/bootinfo.h>
+#include <asm/ppcdebug.h>
+#include <asm/btext.h>
+#include <asm/sections.h>
+#include <asm/machdep.h>
+#include "open_pic.h"
+
+#ifdef CONFIG_LOGO_LINUX_CLUT224
+#include <linux/linux_logo.h>
+extern const struct linux_logo logo_linux_clut224;
+#endif
+
+/*
+ * Properties whose value is longer than this get excluded from our
+ * copy of the device tree. This value does need to be big enough to
+ * ensure that we don't lose things like the interrupt-map property
+ * on a PCI-PCI bridge.
+ */
+#define MAX_PROPERTY_LENGTH (1UL * 1024 * 1024)
+
+/*
+ * Eventually bump that one up
+ */
+#define DEVTREE_CHUNK_SIZE 0x100000
+
+/*
+ * This is the size of the local memory reserve map that gets copied
+ * into the boot params passed to the kernel. That size is totally
+ * flexible as the kernel just reads the list until it encounters an
+ * entry with size 0, so it can be changed without breaking binary
+ * compatibility
+ */
+#define MEM_RESERVE_MAP_SIZE 8
+
+/*
+ * prom_init() is called very early on, before the kernel text
+ * and data have been mapped to KERNELBASE. At this point the code
+ * is running at whatever address it has been loaded at, so
+ * references to extern and static variables must be relocated
+ * explicitly. The procedure reloc_offset() returns the address
+ * we're currently running at minus the address we were linked at.
+ * (Note that strings count as static variables.)
+ *
+ * Because OF may have mapped I/O devices into the area starting at
+ * KERNELBASE, particularly on CHRP machines, we can't safely call
+ * OF once the kernel has been mapped to KERNELBASE. Therefore all
+ * OF calls should be done within prom_init(), and prom_init()
+ * and all routines called within it must be careful to relocate
+ * references as necessary.
+ *
+ * Note that the bss is cleared *after* prom_init runs, so we have
+ * to make sure that any static or extern variables it accesses
+ * are put in the data segment.
+ */
+
+
+#define PROM_BUG() do { \
+ prom_printf("kernel BUG at %s line 0x%x!\n", \
+ RELOC(__FILE__), __LINE__); \
+ __asm__ __volatile__(".long " BUG_ILLEGAL_INSTR); \
+} while (0)
+
+#ifdef DEBUG_PROM
+#define prom_debug(x...) prom_printf(x)
+#else
+#define prom_debug(x...)
+#endif
+
+
+typedef u32 prom_arg_t;
+
+struct prom_args {
+ u32 service;
+ u32 nargs;
+ u32 nret;
+ prom_arg_t args[10];
+ prom_arg_t *rets; /* Pointer to return values in args[16]. */
+};
+
+struct prom_t {
+ unsigned long entry;
+ ihandle root;
+ ihandle chosen;
+ int cpu;
+ ihandle stdout;
+ ihandle disp_node;
+ struct prom_args args;
+ unsigned long version;
+ unsigned long root_size_cells;
+ unsigned long root_addr_cells;
+};
+
+struct pci_reg_property {
+ struct pci_address addr;
+ u32 size_hi;
+ u32 size_lo;
+};
+
+struct mem_map_entry {
+ u64 base;
+ u64 size;
+};
+
+typedef u32 cell_t;
+
+extern void __start(unsigned long r3, unsigned long r4, unsigned long r5);
+
+extern unsigned long reloc_offset(void);
+extern void enter_prom(struct prom_args *args, unsigned long entry);
+extern void copy_and_flush(unsigned long dest, unsigned long src,
+ unsigned long size, unsigned long offset);
+
+extern unsigned long klimit;
+
+//int global_width = 640, global_height = 480, global_depth = 8, global_pitch;
+//unsigned global_address;
+/* prom structure */
+static struct prom_t __initdata prom;
+
+#define PROM_SCRATCH_SIZE 256
+
+static char __initdata of_stdout_device[256];
+static char __initdata prom_scratch[PROM_SCRATCH_SIZE];
+
+static unsigned long __initdata dt_header_start;
+static unsigned long __initdata dt_struct_start, dt_struct_end;
+static unsigned long __initdata dt_string_start, dt_string_end;
+
+static unsigned long __initdata prom_initrd_start, prom_initrd_end;
+
+static int __initdata iommu_force_on;
+static int __initdata ppc64_iommu_off;
+static int __initdata of_platform;
+
+static char __initdata prom_cmd_line[COMMAND_LINE_SIZE];
+
+static unsigned long __initdata alloc_top;
+static unsigned long __initdata alloc_top_high;
+static unsigned long __initdata alloc_bottom;
+static unsigned long __initdata rmo_top;
+static unsigned long __initdata ram_top;
+
+static struct mem_map_entry __initdata mem_reserve_map[MEM_RESERVE_MAP_SIZE];
+static int __initdata mem_reserve_cnt;
+
+static cell_t __initdata regbuf[1024];
+
+
+#define MAX_CPU_THREADS 2
+
+/* TO GO */
+#ifdef CONFIG_HMT
+struct {
+ unsigned int pir;
+ unsigned int threadid;
+} hmt_thread_data[NR_CPUS];
+#endif /* CONFIG_HMT */
+
+/*
+ * This are used in calls to call_prom. The 4th and following
+ * arguments to call_prom should be 32-bit values. 64 bit values
+ * are truncated to 32 bits (and fortunately don't get interpreted
+ * as two arguments).
+ */
+#define ADDR(x) (u32) ((unsigned long)(x) - offset)
+
+/* This is the one and *ONLY* place where we actually call open
+ * firmware from, since we need to make sure we're running in 32b
+ * mode when we do. We switch back to 64b mode upon return.
+ */
+
+#define PROM_ERROR (-1)
+
+static int __init call_prom(const char *service, int nargs, int nret, ...)
+{
+ int i;
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ va_list list;
+
+ _prom->args.service = ADDR(service);
+ _prom->args.nargs = nargs;
+ _prom->args.nret = nret;
+ _prom->args.rets = (prom_arg_t *)&(_prom->args.args[nargs]);
+
+ va_start(list, nret);
+ for (i=0; i < nargs; i++)
+ _prom->args.args[i] = va_arg(list, prom_arg_t);
+ va_end(list);
+
+ for (i=0; i < nret ;i++)
+ _prom->args.rets[i] = 0;
+
+ enter_prom(&_prom->args, _prom->entry);
+
+ return (nret > 0) ? _prom->args.rets[0] : 0;
+}
+
+
+static unsigned int __init prom_claim(unsigned long virt, unsigned long size,
+ unsigned long align)
+{
+ return (unsigned int)call_prom("claim", 3, 1,
+ (prom_arg_t)virt, (prom_arg_t)size,
+ (prom_arg_t)align);
+}
+
+static void __init prom_print(const char *msg)
+{
+ const char *p, *q;
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ if (_prom->stdout == 0)
+ return;
+
+ for (p = msg; *p != 0; p = q) {
+ for (q = p; *q != 0 && *q != '\n'; ++q)
+ ;
+ if (q > p)
+ call_prom("write", 3, 1, _prom->stdout, p, q - p);
+ if (*q == 0)
+ break;
+ ++q;
+ call_prom("write", 3, 1, _prom->stdout, ADDR("\r\n"), 2);
+ }
+}
+
+
+static void __init prom_print_hex(unsigned long val)
+{
+ unsigned long offset = reloc_offset();
+ int i, nibbles = sizeof(val)*2;
+ char buf[sizeof(val)*2+1];
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ for (i = nibbles-1; i >= 0; i--) {
+ buf[i] = (val & 0xf) + '0';
+ if (buf[i] > '9')
+ buf[i] += ('a'-'0'-10);
+ val >>= 4;
+ }
+ buf[nibbles] = '\0';
+ call_prom("write", 3, 1, _prom->stdout, buf, nibbles);
+}
+
+
+static void __init prom_printf(const char *format, ...)
+{
+ unsigned long offset = reloc_offset();
+ const char *p, *q, *s;
+ va_list args;
+ unsigned long v;
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ va_start(args, format);
+ for (p = PTRRELOC(format); *p != 0; p = q) {
+ for (q = p; *q != 0 && *q != '\n' && *q != '%'; ++q)
+ ;
+ if (q > p)
+ call_prom("write", 3, 1, _prom->stdout, p, q - p);
+ if (*q == 0)
+ break;
+ if (*q == '\n') {
+ ++q;
+ call_prom("write", 3, 1, _prom->stdout,
+ ADDR("\r\n"), 2);
+ continue;
+ }
+ ++q;
+ if (*q == 0)
+ break;
+ switch (*q) {
+ case 's':
+ ++q;
+ s = va_arg(args, const char *);
+ prom_print(s);
+ break;
+ case 'x':
+ ++q;
+ v = va_arg(args, unsigned long);
+ prom_print_hex(v);
+ break;
+ }
+ }
+}
+
+
+static void __init __attribute__((noreturn)) prom_panic(const char *reason)
+{
+ unsigned long offset = reloc_offset();
+
+ prom_print(PTRRELOC(reason));
+ /* ToDo: should put up an SRC here */
+ call_prom("exit", 0, 0);
+
+ for (;;) /* should never get here */
+ ;
+}
+
+
+static int __init prom_next_node(phandle *nodep)
+{
+ phandle node;
+
+ if ((node = *nodep) != 0
+ && (*nodep = call_prom("child", 1, 1, node)) != 0)
+ return 1;
+ if ((*nodep = call_prom("peer", 1, 1, node)) != 0)
+ return 1;
+ for (;;) {
+ if ((node = call_prom("parent", 1, 1, node)) == 0)
+ return 0;
+ if ((*nodep = call_prom("peer", 1, 1, node)) != 0)
+ return 1;
+ }
+}
+
+static int __init prom_getprop(phandle node, const char *pname,
+ void *value, size_t valuelen)
+{
+ unsigned long offset = reloc_offset();
+
+ return call_prom("getprop", 4, 1, node, ADDR(pname),
+ (u32)(unsigned long) value, (u32) valuelen);
+}
+
+static int __init prom_getproplen(phandle node, const char *pname)
+{
+ unsigned long offset = reloc_offset();
+
+ return call_prom("getproplen", 2, 1, node, ADDR(pname));
+}
+
+static int __init prom_setprop(phandle node, const char *pname,
+ void *value, size_t valuelen)
+{
+ unsigned long offset = reloc_offset();
+
+ return call_prom("setprop", 4, 1, node, ADDR(pname),
+ (u32)(unsigned long) value, (u32) valuelen);
+}
+
+
+/*
+ * Early parsing of the command line passed to the kernel, used for
+ * the options that affect the iommu
+ */
+static void __init early_cmdline_parse(void)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ char *opt, *p;
+ int l = 0;
+
+ RELOC(prom_cmd_line[0]) = 0;
+ p = RELOC(prom_cmd_line);
+ if ((long)_prom->chosen > 0)
+ l = prom_getprop(_prom->chosen, "bootargs", p, COMMAND_LINE_SIZE-1);
+#ifdef CONFIG_CMDLINE
+ if (l == 0) /* dbl check */
+ strlcpy(RELOC(prom_cmd_line),
+ RELOC(CONFIG_CMDLINE), sizeof(prom_cmd_line));
+#endif /* CONFIG_CMDLINE */
+ prom_printf("command line: %s\n", RELOC(prom_cmd_line));
+
+ opt = strstr(RELOC(prom_cmd_line), RELOC("iommu="));
+ if (opt) {
+ prom_printf("iommu opt is: %s\n", opt);
+ opt += 6;
+ while (*opt && *opt == ' ')
+ opt++;
+ if (!strncmp(opt, RELOC("off"), 3))
+ RELOC(ppc64_iommu_off) = 1;
+ else if (!strncmp(opt, RELOC("force"), 5))
+ RELOC(iommu_force_on) = 1;
+ }
+}
+
+/*
+ * Memory allocation strategy... our layout is normally:
+ *
+ * at 14Mb or more we vmlinux, then a gap and initrd. In some rare cases, initrd
+ * might end up beeing before the kernel though. We assume this won't override
+ * the final kernel at 0, we have no provision to handle that in this version,
+ * but it should hopefully never happen.
+ *
+ * alloc_top is set to the top of RMO, eventually shrink down if the TCEs overlap
+ * alloc_bottom is set to the top of kernel/initrd
+ *
+ * from there, allocations are done that way : rtas is allocated topmost, and
+ * the device-tree is allocated from the bottom. We try to grow the device-tree
+ * allocation as we progress. If we can't, then we fail, we don't currently have
+ * a facility to restart elsewhere, but that shouldn't be necessary neither
+ *
+ * Note that calls to reserve_mem have to be done explicitely, memory allocated
+ * with either alloc_up or alloc_down isn't automatically reserved.
+ */
+
+
+/*
+ * Allocates memory in the RMO upward from the kernel/initrd
+ *
+ * When align is 0, this is a special case, it means to allocate in place
+ * at the current location of alloc_bottom or fail (that is basically
+ * extending the previous allocation). Used for the device-tree flattening
+ */
+static unsigned long __init alloc_up(unsigned long size, unsigned long align)
+{
+ unsigned long offset = reloc_offset();
+ unsigned long base = _ALIGN_UP(RELOC(alloc_bottom), align);
+ unsigned long addr = 0;
+
+ prom_debug("alloc_up(%x, %x)\n", size, align);
+ if (RELOC(ram_top) == 0)
+ prom_panic("alloc_up() called with mem not initialized\n");
+
+ if (align)
+ base = _ALIGN_UP(RELOC(alloc_bottom), align);
+ else
+ base = RELOC(alloc_bottom);
+
+ for(; (base + size) <= RELOC(alloc_top);
+ base = _ALIGN_UP(base + 0x100000, align)) {
+ prom_debug(" trying: 0x%x\n\r", base);
+ addr = (unsigned long)prom_claim(base, size, 0);
+ if ((int)addr != PROM_ERROR)
+ break;
+ addr = 0;
+ if (align == 0)
+ break;
+ }
+ if (addr == 0)
+ return 0;
+ RELOC(alloc_bottom) = addr;
+
+ prom_debug(" -> %x\n", addr);
+ prom_debug(" alloc_bottom : %x\n", RELOC(alloc_bottom));
+ prom_debug(" alloc_top : %x\n", RELOC(alloc_top));
+ prom_debug(" alloc_top_hi : %x\n", RELOC(alloc_top_high));
+ prom_debug(" rmo_top : %x\n", RELOC(rmo_top));
+ prom_debug(" ram_top : %x\n", RELOC(ram_top));
+
+ return addr;
+}
+
+/*
+ * Allocates memory downard, either from top of RMO, or if highmem
+ * is set, from the top of RAM. Note that this one doesn't handle
+ * failures. In does claim memory if highmem is not set.
+ */
+static unsigned long __init alloc_down(unsigned long size, unsigned long align,
+ int highmem)
+{
+ unsigned long offset = reloc_offset();
+ unsigned long base, addr = 0;
+
+ prom_debug("alloc_down(%x, %x, %s)\n", size, align,
+ highmem ? RELOC("(high)") : RELOC("(low)"));
+ if (RELOC(ram_top) == 0)
+ prom_panic("alloc_down() called with mem not initialized\n");
+
+ if (highmem) {
+ /* Carve out storage for the TCE table. */
+ addr = _ALIGN_DOWN(RELOC(alloc_top_high) - size, align);
+ if (addr <= RELOC(alloc_bottom))
+ return 0;
+ else {
+ /* Will we bump into the RMO ? If yes, check out that we
+ * didn't overlap existing allocations there, if we did,
+ * we are dead, we must be the first in town !
+ */
+ if (addr < RELOC(rmo_top)) {
+ /* Good, we are first */
+ if (RELOC(alloc_top) == RELOC(rmo_top))
+ RELOC(alloc_top) = RELOC(rmo_top) = addr;
+ else
+ return 0;
+ }
+ RELOC(alloc_top_high) = addr;
+ }
+ goto bail;
+ }
+
+ base = _ALIGN_DOWN(RELOC(alloc_top) - size, align);
+ for(; base > RELOC(alloc_bottom); base = _ALIGN_DOWN(base - 0x100000, align)) {
+ prom_debug(" trying: 0x%x\n\r", base);
+ addr = (unsigned long)prom_claim(base, size, 0);
+ if ((int)addr != PROM_ERROR)
+ break;
+ addr = 0;
+ }
+ if (addr == 0)
+ return 0;
+ RELOC(alloc_top) = addr;
+
+ bail:
+ prom_debug(" -> %x\n", addr);
+ prom_debug(" alloc_bottom : %x\n", RELOC(alloc_bottom));
+ prom_debug(" alloc_top : %x\n", RELOC(alloc_top));
+ prom_debug(" alloc_top_hi : %x\n", RELOC(alloc_top_high));
+ prom_debug(" rmo_top : %x\n", RELOC(rmo_top));
+ prom_debug(" ram_top : %x\n", RELOC(ram_top));
+
+ return addr;
+}
+
+/*
+ * Parse a "reg" cell
+ */
+static unsigned long __init prom_next_cell(int s, cell_t **cellp)
+{
+ cell_t *p = *cellp;
+ unsigned long r = 0;
+
+ /* Ignore more than 2 cells */
+ while (s > 2) {
+ p++;
+ s--;
+ }
+ while (s) {
+ r <<= 32;
+ r |= *(p++);
+ s--;
+ }
+
+ *cellp = p;
+ return r;
+}
+
+/*
+ * Very dumb function for adding to the memory reserve list, but
+ * we don't need anything smarter at this point
+ *
+ * XXX Eventually check for collisions. They should NEVER happen
+ * if problems seem to show up, it would be a good start to track
+ * them down.
+ */
+static void reserve_mem(unsigned long base, unsigned long size)
+{
+ unsigned long offset = reloc_offset();
+ unsigned long top = base + size;
+ unsigned long cnt = RELOC(mem_reserve_cnt);
+
+ if (size == 0)
+ return;
+
+ /* We need to always keep one empty entry so that we
+ * have our terminator with "size" set to 0 since we are
+ * dumb and just copy this entire array to the boot params
+ */
+ base = _ALIGN_DOWN(base, PAGE_SIZE);
+ top = _ALIGN_UP(top, PAGE_SIZE);
+ size = top - base;
+
+ if (cnt >= (MEM_RESERVE_MAP_SIZE - 1))
+ prom_panic("Memory reserve map exhausted !\n");
+ RELOC(mem_reserve_map)[cnt].base = base;
+ RELOC(mem_reserve_map)[cnt].size = size;
+ RELOC(mem_reserve_cnt) = cnt + 1;
+}
+
+/*
+ * Initialize memory allocation mecanism, parse "memory" nodes and
+ * obtain that way the top of memory and RMO to setup out local allocator
+ */
+static void __init prom_init_mem(void)
+{
+ phandle node;
+ char *path, type[64];
+ unsigned int plen;
+ cell_t *p, *endp;
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ /*
+ * We iterate the memory nodes to find
+ * 1) top of RMO (first node)
+ * 2) top of memory
+ */
+ prom_debug("root_addr_cells: %x\n", (long)_prom->root_addr_cells);
+ prom_debug("root_size_cells: %x\n", (long)_prom->root_size_cells);
+
+ prom_debug("scanning memory:\n");
+ path = RELOC(prom_scratch);
+
+ for (node = 0; prom_next_node(&node); ) {
+ type[0] = 0;
+ prom_getprop(node, "device_type", type, sizeof(type));
+
+ if (strcmp(type, RELOC("memory")))
+ continue;
+
+ plen = prom_getprop(node, "reg", RELOC(regbuf), sizeof(regbuf));
+ if (plen > sizeof(regbuf)) {
+ prom_printf("memory node too large for buffer !\n");
+ plen = sizeof(regbuf);
+ }
+ p = RELOC(regbuf);
+ endp = p + (plen / sizeof(cell_t));
+
+#ifdef DEBUG_PROM
+ memset(path, 0, PROM_SCRATCH_SIZE);
+ call_prom("package-to-path", 3, 1, node, path, PROM_SCRATCH_SIZE-1);
+ prom_debug(" node %s :\n", path);
+#endif /* DEBUG_PROM */
+
+ while ((endp - p) >= (_prom->root_addr_cells + _prom->root_size_cells)) {
+ unsigned long base, size;
+
+ base = prom_next_cell(_prom->root_addr_cells, &p);
+ size = prom_next_cell(_prom->root_size_cells, &p);
+
+ if (size == 0)
+ continue;
+ prom_debug(" %x %x\n", base, size);
+ if (base == 0)
+ RELOC(rmo_top) = size;
+ if ((base + size) > RELOC(ram_top))
+ RELOC(ram_top) = base + size;
+ }
+ }
+
+ /* Setup our top/bottom alloc points, that is top of RMO or top of
+ * segment 0 when running non-LPAR
+ */
+ if ( RELOC(of_platform) == PLATFORM_PSERIES_LPAR )
+ RELOC(alloc_top) = RELOC(rmo_top);
+ else
+ RELOC(alloc_top) = min(0x40000000ul, RELOC(ram_top));
+ RELOC(alloc_bottom) = PAGE_ALIGN(RELOC(klimit) - offset + 0x4000);
+ RELOC(alloc_top_high) = RELOC(ram_top);
+
+ /* Check if we have an initrd after the kernel, if we do move our bottom
+ * point to after it
+ */
+ if (RELOC(prom_initrd_start)) {
+ if ((RELOC(prom_initrd_start) + RELOC(prom_initrd_end))
+ > RELOC(alloc_bottom))
+ RELOC(alloc_bottom) = PAGE_ALIGN(RELOC(prom_initrd_end));
+ }
+
+ prom_printf("memory layout at init:\n");
+ prom_printf(" alloc_bottom : %x\n", RELOC(alloc_bottom));
+ prom_printf(" alloc_top : %x\n", RELOC(alloc_top));
+ prom_printf(" alloc_top_hi : %x\n", RELOC(alloc_top_high));
+ prom_printf(" rmo_top : %x\n", RELOC(rmo_top));
+ prom_printf(" ram_top : %x\n", RELOC(ram_top));
+}
+
+
+/*
+ * Allocate room for and instanciate RTAS
+ */
+static void __init prom_instantiate_rtas(void)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ phandle prom_rtas;
+ u64 base, entry = 0;
+ u32 size;
+
+ prom_debug("prom_instantiate_rtas: start...\n");
+
+ prom_rtas = call_prom("finddevice", 1, 1, ADDR("/rtas"));
+ if (prom_rtas != (phandle) -1) {
+ prom_getprop(prom_rtas, "rtas-size", &size, sizeof(size));
+ if (size != 0) {
+ base = alloc_down(size, PAGE_SIZE, 0);
+ if (base == 0) {
+ prom_printf("RTAS allocation failed !\n");
+ return;
+ }
+ prom_printf("instantiating rtas at 0x%x", base);
+
+ prom_rtas = call_prom("open", 1, 1, ADDR("/rtas"));
+ prom_printf("...");
+
+ if (call_prom("call-method", 3, 2,
+ ADDR("instantiate-rtas"),
+ prom_rtas, base) != PROM_ERROR) {
+ entry = (long)_prom->args.rets[1];
+ }
+ if (entry == 0) {
+ prom_printf(" failed\n");
+ return;
+ }
+ prom_printf(" done\n");
+
+ reserve_mem(base, size);
+ }
+
+ prom_setprop(_prom->chosen, "linux,rtas-base", &base, sizeof(base));
+ prom_setprop(_prom->chosen, "linux,rtas-entry", &entry, sizeof(entry));
+ prom_setprop(_prom->chosen, "linux,rtas-size", &size, sizeof(size));
+
+ prom_debug("rtas base = 0x%x\n", base);
+ prom_debug("rtas entry = 0x%x\n", entry);
+ prom_debug("rtas size = 0x%x\n", (long)size);
+ }
+ prom_debug("prom_instantiate_rtas: end...\n");
+}
+
+
+/*
+ * Allocate room for and initialize TCE tables
+ */
+static void __init prom_initialize_tce_table(void)
+{
+ phandle node;
+ ihandle phb_node;
+ unsigned long offset = reloc_offset();
+ char compatible[64], type[64], model[64];
+ char *path = RELOC(prom_scratch);
+ u64 base, vbase, align;
+ u32 minalign, minsize;
+ u64 tce_entry, *tce_entryp;
+ u64 local_alloc_top, local_alloc_bottom;
+ u64 i;
+
+ if (RELOC(ppc64_iommu_off))
+ return;
+
+ prom_debug("starting prom_initialize_tce_table\n");
+
+ /* Cache current top of allocs so we reserve a single block */
+ local_alloc_top = RELOC(alloc_top_high);
+ local_alloc_bottom = local_alloc_top;
+
+ /* Search all nodes looking for PHBs. */
+ for (node = 0; prom_next_node(&node); ) {
+ compatible[0] = 0;
+ type[0] = 0;
+ model[0] = 0;
+ prom_getprop(node, "compatible",
+ compatible, sizeof(compatible));
+ prom_getprop(node, "device_type", type, sizeof(type));
+ prom_getprop(node, "model", model, sizeof(model));
+
+ if ((type[0] == 0) || (strstr(type, RELOC("pci")) == NULL))
+ continue;
+
+ /* Keep the old logic in tack to avoid regression. */
+ if (compatible[0] != 0) {
+ if ((strstr(compatible, RELOC("python")) == NULL) &&
+ (strstr(compatible, RELOC("Speedwagon")) == NULL) &&
+ (strstr(compatible, RELOC("Winnipeg")) == NULL))
+ continue;
+ } else if (model[0] != 0) {
+ if ((strstr(model, RELOC("ython")) == NULL) &&
+ (strstr(model, RELOC("peedwagon")) == NULL) &&
+ (strstr(model, RELOC("innipeg")) == NULL))
+ continue;
+ }
+
+ if (prom_getprop(node, "tce-table-minalign", &minalign,
+ sizeof(minalign)) == PROM_ERROR)
+ minalign = 0;
+ if (prom_getprop(node, "tce-table-minsize", &minsize,
+ sizeof(minsize)) == PROM_ERROR)
+ minsize = 4UL << 20;
+
+ /*
+ * Even though we read what OF wants, we just set the table
+ * size to 4 MB. This is enough to map 2GB of PCI DMA space.
+ * By doing this, we avoid the pitfalls of trying to DMA to
+ * MMIO space and the DMA alias hole.
+ *
+ * On POWER4, firmware sets the TCE region by assuming
+ * each TCE table is 8MB. Using this memory for anything
+ * else will impact performance, so we always allocate 8MB.
+ * Anton
+ */
+ if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p))
+ minsize = 8UL << 20;
+ else
+ minsize = 4UL << 20;
+
+ /* Align to the greater of the align or size */
+ align = max(minalign, minsize);
+ base = alloc_down(minsize, align, 1);
+ if (base == 0)
+ prom_panic("ERROR, cannot find space for TCE table.\n");
+ if (base < local_alloc_bottom)
+ local_alloc_bottom = base;
+
+ vbase = (unsigned long)abs_to_virt(base);
+
+ /* Save away the TCE table attributes for later use. */
+ prom_setprop(node, "linux,tce-base", &vbase, sizeof(vbase));
+ prom_setprop(node, "linux,tce-size", &minsize, sizeof(minsize));
+ prom_setprop(node, "linux,has-tce-table", NULL, 0);
+
+ /* It seems OF doesn't null-terminate the path :-( */
+ memset(path, 0, sizeof(path));
+ /* Call OF to setup the TCE hardware */
+ if (call_prom("package-to-path", 3, 1, node,
+ path, PROM_SCRATCH_SIZE-1) == PROM_ERROR) {
+ prom_printf("package-to-path failed\n");
+ }
+
+ prom_debug("TCE table: %s\n", path);
+ prom_debug("\tnode = 0x%x\n", node);
+ prom_debug("\tbase = 0x%x\n", vbase);
+ prom_debug("\tsize = 0x%x\n", minsize);
+
+ /* Initialize the table to have a one-to-one mapping
+ * over the allocated size.
+ */
+ tce_entryp = (unsigned long *)base;
+ for (i = 0; i < (minsize >> 3) ;tce_entryp++, i++) {
+ tce_entry = (i << PAGE_SHIFT);
+ tce_entry |= 0x3;
+ *tce_entryp = tce_entry;
+ }
+
+ prom_printf("opening PHB %s", path);
+ phb_node = call_prom("open", 1, 1, path);
+ if ( (long)phb_node <= 0)
+ prom_printf("... failed\n");
+ else
+ prom_printf("... done\n");
+
+ call_prom("call-method", 6, 0, ADDR("set-64-bit-addressing"),
+ phb_node, -1, minsize,
+ (u32) base, (u32) (base >> 32));
+ call_prom("close", 1, 0, phb_node);
+ }
+
+ reserve_mem(local_alloc_bottom, local_alloc_top - local_alloc_bottom);
+
+ /* Flag the first invalid entry */
+ prom_debug("ending prom_initialize_tce_table\n");
+}
+
+/*
+ * With CHRP SMP we need to use the OF to start the other
+ * processors so we can't wait until smp_boot_cpus (the OF is
+ * trashed by then) so we have to put the processors into
+ * a holding pattern controlled by the kernel (not OF) before
+ * we destroy the OF.
+ *
+ * This uses a chunk of low memory, puts some holding pattern
+ * code there and sends the other processors off to there until
+ * smp_boot_cpus tells them to do something. The holding pattern
+ * checks that address until its cpu # is there, when it is that
+ * cpu jumps to __secondary_start(). smp_boot_cpus() takes care
+ * of setting those values.
+ *
+ * We also use physical address 0x4 here to tell when a cpu
+ * is in its holding pattern code.
+ *
+ * Fixup comment... DRENG / PPPBBB - Peter
+ *
+ * -- Cort
+ */
+static void __init prom_hold_cpus(void)
+{
+ unsigned long i;
+ unsigned int reg;
+ phandle node;
+ unsigned long offset = reloc_offset();
+ char type[64];
+ int cpuid = 0;
+ unsigned int interrupt_server[MAX_CPU_THREADS];
+ unsigned int cpu_threads, hw_cpu_num;
+ int propsize;
+ extern void __secondary_hold(void);
+ extern unsigned long __secondary_hold_spinloop;
+ extern unsigned long __secondary_hold_acknowledge;
+ unsigned long *spinloop
+ = (void *)virt_to_abs(&__secondary_hold_spinloop);
+ unsigned long *acknowledge
+ = (void *)virt_to_abs(&__secondary_hold_acknowledge);
+ unsigned long secondary_hold
+ = virt_to_abs(*PTRRELOC((unsigned long *)__secondary_hold));
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ prom_debug("prom_hold_cpus: start...\n");
+ prom_debug(" 1) spinloop = 0x%x\n", (unsigned long)spinloop);
+ prom_debug(" 1) *spinloop = 0x%x\n", *spinloop);
+ prom_debug(" 1) acknowledge = 0x%x\n",
+ (unsigned long)acknowledge);
+ prom_debug(" 1) *acknowledge = 0x%x\n", *acknowledge);
+ prom_debug(" 1) secondary_hold = 0x%x\n", secondary_hold);
+
+ /* Set the common spinloop variable, so all of the secondary cpus
+ * will block when they are awakened from their OF spinloop.
+ * This must occur for both SMP and non SMP kernels, since OF will
+ * be trashed when we move the kernel.
+ */
+ *spinloop = 0;
+
+#ifdef CONFIG_HMT
+ for (i=0; i < NR_CPUS; i++) {
+ RELOC(hmt_thread_data)[i].pir = 0xdeadbeef;
+ }
+#endif
+ /* look for cpus */
+ for (node = 0; prom_next_node(&node); ) {
+ type[0] = 0;
+ prom_getprop(node, "device_type", type, sizeof(type));
+ if (strcmp(type, RELOC("cpu")) != 0)
+ continue;
+
+ /* Skip non-configured cpus. */
+ prom_getprop(node, "status", type, sizeof(type));
+ if (strcmp(type, RELOC("okay")) != 0)
+ continue;
+
+ reg = -1;
+ prom_getprop(node, "reg", ®, sizeof(reg));
+
+ prom_debug("\ncpuid = 0x%x\n", cpuid);
+ prom_debug("cpu hw idx = 0x%x\n", reg);
+
+ /* Init the acknowledge var which will be reset by
+ * the secondary cpu when it awakens from its OF
+ * spinloop.
+ */
+ *acknowledge = (unsigned long)-1;
+
+ propsize = prom_getprop(node, "ibm,ppc-interrupt-server#s",
+ &interrupt_server,
+ sizeof(interrupt_server));
+ if (propsize < 0) {
+ /* no property. old hardware has no SMT */
+ cpu_threads = 1;
+ interrupt_server[0] = reg; /* fake it with phys id */
+ } else {
+ /* We have a threaded processor */
+ cpu_threads = propsize / sizeof(u32);
+ if (cpu_threads > MAX_CPU_THREADS) {
+ prom_printf("SMT: too many threads!\n"
+ "SMT: found %x, max is %x\n",
+ cpu_threads, MAX_CPU_THREADS);
+ cpu_threads = 1; /* ToDo: panic? */
+ }
+ }
+
+ hw_cpu_num = interrupt_server[0];
+ if (hw_cpu_num != _prom->cpu) {
+ /* Primary Thread of non-boot cpu */
+ prom_printf("%x : starting cpu hw idx %x... ", cpuid, reg);
+ call_prom("start-cpu", 3, 0, node,
+ secondary_hold, cpuid);
+
+ for ( i = 0 ; (i < 100000000) &&
+ (*acknowledge == ((unsigned long)-1)); i++ ) ;
+
+ if (*acknowledge == cpuid) {
+ prom_printf("done\n");
+ /* We have to get every CPU out of OF,
+ * even if we never start it. */
+ if (cpuid >= NR_CPUS)
+ goto next;
+ } else {
+ prom_printf("failed: %x\n", *acknowledge);
+ }
+ }
+#ifdef CONFIG_SMP
+ else
+ prom_printf("%x : boot cpu %x\n", cpuid, reg);
+#endif
+next:
+#ifdef CONFIG_SMP
+ /* Init paca for secondary threads. They start later. */
+ for (i=1; i < cpu_threads; i++) {
+ cpuid++;
+ if (cpuid >= NR_CPUS)
+ continue;
+ }
+#endif /* CONFIG_SMP */
+ cpuid++;
+ }
+#ifdef CONFIG_HMT
+ /* Only enable HMT on processors that provide support. */
+ if (__is_processor(PV_PULSAR) ||
+ __is_processor(PV_ICESTAR) ||
+ __is_processor(PV_SSTAR)) {
+ prom_printf(" starting secondary threads\n");
+
+ for (i = 0; i < NR_CPUS; i += 2) {
+ if (!cpu_online(i))
+ continue;
+
+ if (i == 0) {
+ unsigned long pir = mfspr(SPRN_PIR);
+ if (__is_processor(PV_PULSAR)) {
+ RELOC(hmt_thread_data)[i].pir =
+ pir & 0x1f;
+ } else {
+ RELOC(hmt_thread_data)[i].pir =
+ pir & 0x3ff;
+ }
+ }
+ }
+ } else {
+ prom_printf("Processor is not HMT capable\n");
+ }
+#endif
+
+ if (cpuid > NR_CPUS)
+ prom_printf("WARNING: maximum CPUs (" __stringify(NR_CPUS)
+ ") exceeded: ignoring extras\n");
+
+ prom_debug("prom_hold_cpus: end...\n");
+}
+
+
+static void __init prom_init_client_services(unsigned long pp)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ /* Get a handle to the prom entry point before anything else */
+ _prom->entry = pp;
+
+ /* Init default value for phys size */
+ _prom->root_size_cells = 1;
+ _prom->root_addr_cells = 2;
+
+ /* get a handle for the stdout device */
+ _prom->chosen = call_prom("finddevice", 1, 1, ADDR("/chosen"));
+ if ((long)_prom->chosen <= 0)
+ prom_panic("cannot find chosen"); /* msg won't be printed :( */
+
+ /* get device tree root */
+ _prom->root = call_prom("finddevice", 1, 1, ADDR("/"));
+ if ((long)_prom->root <= 0)
+ prom_panic("cannot find device tree root"); /* msg won't be printed :( */
+}
+
+static void __init prom_init_stdout(void)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ char *path = RELOC(of_stdout_device);
+ char type[16];
+ u32 val;
+
+ if (prom_getprop(_prom->chosen, "stdout", &val, sizeof(val)) <= 0)
+ prom_panic("cannot find stdout");
+
+ _prom->stdout = val;
+
+ /* Get the full OF pathname of the stdout device */
+ memset(path, 0, 256);
+ call_prom("instance-to-path", 3, 1, _prom->stdout, path, 255);
+ val = call_prom("instance-to-package", 1, 1, _prom->stdout);
+ prom_setprop(_prom->chosen, "linux,stdout-package", &val, sizeof(val));
+ prom_printf("OF stdout device is: %s\n", RELOC(of_stdout_device));
+ prom_setprop(_prom->chosen, "linux,stdout-path",
+ RELOC(of_stdout_device), strlen(RELOC(of_stdout_device))+1);
+
+ /* If it's a display, note it */
+ memset(type, 0, sizeof(type));
+ prom_getprop(val, "device_type", type, sizeof(type));
+ if (strcmp(type, RELOC("display")) == 0) {
+ _prom->disp_node = val;
+ prom_setprop(val, "linux,boot-display", NULL, 0);
+ }
+}
+
+static int __init prom_find_machine_type(void)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ char compat[256];
+ int len, i = 0;
+ phandle rtas;
+
+ len = prom_getprop(_prom->root, "compatible",
+ compat, sizeof(compat)-1);
+ if (len > 0) {
+ compat[len] = 0;
+ while (i < len) {
+ char *p = &compat[i];
+ int sl = strlen(p);
+ if (sl == 0)
+ break;
+ if (strstr(p, RELOC("Power Macintosh")) ||
+ strstr(p, RELOC("MacRISC4")))
+ return PLATFORM_POWERMAC;
+ i += sl + 1;
+ }
+ }
+ /* Default to pSeries. We need to know if we are running LPAR */
+ rtas = call_prom("finddevice", 1, 1, ADDR("/rtas"));
+ if (rtas != (phandle) -1) {
+ unsigned long x;
+ x = prom_getproplen(rtas, "ibm,hypertas-functions");
+ if (x != PROM_ERROR) {
+ prom_printf("Hypertas detected, assuming LPAR !\n");
+ return PLATFORM_PSERIES_LPAR;
+ }
+ }
+ return PLATFORM_PSERIES;
+}
+
+static int __init prom_set_color(ihandle ih, int i, int r, int g, int b)
+{
+ unsigned long offset = reloc_offset();
+
+ return call_prom("call-method", 6, 1, ADDR("color!"), ih, i, b, g, r);
+}
+
+/*
+ * If we have a display that we don't know how to drive,
+ * we will want to try to execute OF's open method for it
+ * later. However, OF will probably fall over if we do that
+ * we've taken over the MMU.
+ * So we check whether we will need to open the display,
+ * and if so, open it now.
+ */
+static unsigned long __init prom_check_displays(void)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ char type[16], *path;
+ phandle node;
+ ihandle ih;
+ int i;
+
+ static unsigned char default_colors[] = {
+ 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xaa,
+ 0x00, 0xaa, 0x00,
+ 0x00, 0xaa, 0xaa,
+ 0xaa, 0x00, 0x00,
+ 0xaa, 0x00, 0xaa,
+ 0xaa, 0xaa, 0x00,
+ 0xaa, 0xaa, 0xaa,
+ 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0xff,
+ 0x55, 0xff, 0x55,
+ 0x55, 0xff, 0xff,
+ 0xff, 0x55, 0x55,
+ 0xff, 0x55, 0xff,
+ 0xff, 0xff, 0x55,
+ 0xff, 0xff, 0xff
+ };
+ const unsigned char *clut;
+
+ prom_printf("Looking for displays\n");
+ for (node = 0; prom_next_node(&node); ) {
+ memset(type, 0, sizeof(type));
+ prom_getprop(node, "device_type", type, sizeof(type));
+ if (strcmp(type, RELOC("display")) != 0)
+ continue;
+
+ /* It seems OF doesn't null-terminate the path :-( */
+ path = RELOC(prom_scratch);
+ memset(path, 0, PROM_SCRATCH_SIZE);
+
+ /*
+ * leave some room at the end of the path for appending extra
+ * arguments
+ */
+ if (call_prom("package-to-path", 3, 1, node, path, PROM_SCRATCH_SIZE-10) < 0)
+ continue;
+ prom_printf("found display : %s, opening ... ", path);
+
+ ih = call_prom("open", 1, 1, path);
+ if (ih == (ihandle)0 || ih == (ihandle)-1) {
+ prom_printf("failed\n");
+ continue;
+ }
+
+ /* Success */
+ prom_printf("done\n");
+ prom_setprop(node, "linux,opened", NULL, 0);
+
+ /*
+ * stdout wasn't a display node, pick the first we can find
+ * for btext
+ */
+ if (_prom->disp_node == 0)
+ _prom->disp_node = node;
+
+ /* Setup a useable color table when the appropriate
+ * method is available. Should update this to set-colors */
+ clut = RELOC(default_colors);
+ for (i = 0; i < 32; i++, clut += 3)
+ if (prom_set_color(ih, i, clut[0], clut[1],
+ clut[2]) != 0)
+ break;
+
+#ifdef CONFIG_LOGO_LINUX_CLUT224
+ clut = PTRRELOC(RELOC(logo_linux_clut224.clut));
+ for (i = 0; i < RELOC(logo_linux_clut224.clutsize); i++, clut += 3)
+ if (prom_set_color(ih, i + 32, clut[0], clut[1],
+ clut[2]) != 0)
+ break;
+#endif /* CONFIG_LOGO_LINUX_CLUT224 */
+ }
+}
+
+
+/* Return (relocated) pointer to this much memory: moves initrd if reqd. */
+static void __init *make_room(unsigned long *mem_start, unsigned long *mem_end,
+ unsigned long needed, unsigned long align)
+{
+ unsigned long offset = reloc_offset();
+ void *ret;
+
+ *mem_start = _ALIGN(*mem_start, align);
+ while ((*mem_start + needed) > *mem_end) {
+ unsigned long room, chunk;
+
+ prom_debug("Chunk exhausted, claiming more at %x...\n",
+ RELOC(alloc_bottom));
+ room = RELOC(alloc_top) - RELOC(alloc_bottom);
+ if (room > DEVTREE_CHUNK_SIZE)
+ room = DEVTREE_CHUNK_SIZE;
+ if (room < PAGE_SIZE)
+ prom_panic("No memory for flatten_device_tree (no room)");
+ chunk = alloc_up(room, 0);
+ if (chunk == 0)
+ prom_panic("No memory for flatten_device_tree (claim failed)");
+ *mem_end = RELOC(alloc_top);
+ }
+
+ ret = (void *)*mem_start;
+ *mem_start += needed;
+
+ return ret;
+}
+
+#define dt_push_token(token, mem_start, mem_end) \
+ do { *((u32 *)make_room(mem_start, mem_end, 4, 4)) = token; } while(0)
+
+static unsigned long __init dt_find_string(char *str)
+{
+ unsigned long offset = reloc_offset();
+ char *s, *os;
+
+ s = os = (char *)RELOC(dt_string_start);
+ s += 4;
+ while (s < (char *)RELOC(dt_string_end)) {
+ if (strcmp(s, str) == 0)
+ return s - os;
+ s += strlen(s) + 1;
+ }
+ return 0;
+}
+
+static void __init scan_dt_build_strings(phandle node, unsigned long *mem_start,
+ unsigned long *mem_end)
+{
+ unsigned long offset = reloc_offset();
+ char *prev_name, *namep, *sstart;
+ unsigned long soff;
+ phandle child;
+
+ sstart = (char *)RELOC(dt_string_start);
+
+ /* get and store all property names */
+ prev_name = RELOC("");
+ for (;;) {
+
+ /* 32 is max len of name including nul. */
+ namep = make_room(mem_start, mem_end, 32, 1);
+ if (call_prom("nextprop", 3, 1, node, prev_name, namep) <= 0) {
+ /* No more nodes: unwind alloc */
+ *mem_start = (unsigned long)namep;
+ break;
+ }
+ soff = dt_find_string(namep);
+ if (soff != 0) {
+ *mem_start = (unsigned long)namep;
+ namep = sstart + soff;
+ } else {
+ /* Trim off some if we can */
+ *mem_start = (unsigned long)namep + strlen(namep) + 1;
+ RELOC(dt_string_end) = *mem_start;
+ }
+ prev_name = namep;
+ }
+
+ /* do all our children */
+ child = call_prom("child", 1, 1, node);
+ while (child != (phandle)0) {
+ scan_dt_build_strings(child, mem_start, mem_end);
+ child = call_prom("peer", 1, 1, child);
+ }
+}
+
+static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
+ unsigned long *mem_end)
+{
+ int l, align;
+ phandle child;
+ char *namep, *prev_name, *sstart;
+ unsigned long soff;
+ unsigned char *valp;
+ unsigned long offset = reloc_offset();
+ char pname[32];
+ char *path;
+
+ path = RELOC(prom_scratch);
+
+ dt_push_token(OF_DT_BEGIN_NODE, mem_start, mem_end);
+
+ /* get the node's full name */
+ namep = (char *)*mem_start;
+ l = call_prom("package-to-path", 3, 1, node,
+ namep, *mem_end - *mem_start);
+ if (l >= 0) {
+ /* Didn't fit? Get more room. */
+ if (l+1 > *mem_end - *mem_start) {
+ namep = make_room(mem_start, mem_end, l+1, 1);
+ call_prom("package-to-path", 3, 1, node, namep, l);
+ }
+ namep[l] = '\0';
+ *mem_start = _ALIGN(((unsigned long) namep) + strlen(namep) + 1, 4);
+ }
+
+ /* get it again for debugging */
+ memset(path, 0, PROM_SCRATCH_SIZE);
+ call_prom("package-to-path", 3, 1, node, path, PROM_SCRATCH_SIZE-1);
+
+ /* get and store all properties */
+ prev_name = RELOC("");
+ sstart = (char *)RELOC(dt_string_start);
+ for (;;) {
+ if (call_prom("nextprop", 3, 1, node, prev_name, pname) <= 0)
+ break;
+
+ /* find string offset */
+ soff = dt_find_string(pname);
+ if (soff == 0) {
+ prom_printf("WARNING: Can't find string index for <%s>, node %s\n",
+ pname, path);
+ break;
+ }
+ prev_name = sstart + soff;
+
+ /* get length */
+ l = call_prom("getproplen", 2, 1, node, pname);
+
+ /* sanity checks */
+ if (l < 0)
+ continue;
+ if (l > MAX_PROPERTY_LENGTH) {
+ prom_printf("WARNING: ignoring large property ");
+ /* It seems OF doesn't null-terminate the path :-( */
+ prom_printf("[%s] ", path);
+ prom_printf("%s length 0x%x\n", pname, l);
+ continue;
+ }
+
+ /* push property head */
+ dt_push_token(OF_DT_PROP, mem_start, mem_end);
+ dt_push_token(l, mem_start, mem_end);
+ dt_push_token(soff, mem_start, mem_end);
+
+ /* push property content */
+ align = (l >= 8) ? 8 : 4;
+ valp = make_room(mem_start, mem_end, l, align);
+ call_prom("getprop", 4, 1, node, pname, valp, l);
+ *mem_start = _ALIGN(*mem_start, 4);
+ }
+
+ /* Add a "linux,phandle" property. */
+ soff = dt_find_string(RELOC("linux,phandle"));
+ if (soff == 0)
+ prom_printf("WARNING: Can't find string index for <linux-phandle>"
+ " node %s\n", path);
+ else {
+ dt_push_token(OF_DT_PROP, mem_start, mem_end);
+ dt_push_token(4, mem_start, mem_end);
+ dt_push_token(soff, mem_start, mem_end);
+ valp = make_room(mem_start, mem_end, 4, 4);
+ *(u32 *)valp = node;
+ }
+
+ /* do all our children */
+ child = call_prom("child", 1, 1, node);
+ while (child != (phandle)0) {
+ scan_dt_build_struct(child, mem_start, mem_end);
+ child = call_prom("peer", 1, 1, child);
+ }
+
+ dt_push_token(OF_DT_END_NODE, mem_start, mem_end);
+}
+
+static void __init flatten_device_tree(void)
+{
+ phandle root;
+ unsigned long offset = reloc_offset();
+ unsigned long mem_start, mem_end, room;
+ struct boot_param_header *hdr;
+ char *namep;
+ u64 *rsvmap;
+
+ /*
+ * Check how much room we have between alloc top & bottom (+/- a
+ * few pages), crop to 4Mb, as this is our "chuck" size
+ */
+ room = RELOC(alloc_top) - RELOC(alloc_bottom) - 0x4000;
+ if (room > DEVTREE_CHUNK_SIZE)
+ room = DEVTREE_CHUNK_SIZE;
+ prom_debug("starting device tree allocs at %x\n", RELOC(alloc_bottom));
+
+ /* Now try to claim that */
+ mem_start = (unsigned long)alloc_up(room, PAGE_SIZE);
+ if (mem_start == 0)
+ prom_panic("Can't allocate initial device-tree chunk\n");
+ mem_end = RELOC(alloc_top);
+
+ /* Get root of tree */
+ root = call_prom("peer", 1, 1, (phandle)0);
+ if (root == (phandle)0)
+ prom_panic ("couldn't get device tree root\n");
+
+ /* Build header and make room for mem rsv map */
+ mem_start = _ALIGN(mem_start, 4);
+ hdr = make_room(&mem_start, &mem_end, sizeof(struct boot_param_header), 4);
+ RELOC(dt_header_start) = (unsigned long)hdr;
+ rsvmap = make_room(&mem_start, &mem_end, sizeof(mem_reserve_map), 8);
+
+ /* Start of strings */
+ mem_start = PAGE_ALIGN(mem_start);
+ RELOC(dt_string_start) = mem_start;
+ mem_start += 4; /* hole */
+
+ /* Add "linux,phandle" in there, we'll need it */
+ namep = make_room(&mem_start, &mem_end, 16, 1);
+ strcpy(namep, RELOC("linux,phandle"));
+ mem_start = (unsigned long)namep + strlen(namep) + 1;
+ RELOC(dt_string_end) = mem_start;
+
+ /* Build string array */
+ prom_printf("Building dt strings...\n");
+ scan_dt_build_strings(root, &mem_start, &mem_end);
+
+ /* Build structure */
+ mem_start = PAGE_ALIGN(mem_start);
+ RELOC(dt_struct_start) = mem_start;
+ prom_printf("Building dt structure...\n");
+ scan_dt_build_struct(root, &mem_start, &mem_end);
+ dt_push_token(OF_DT_END, &mem_start, &mem_end);
+ RELOC(dt_struct_end) = PAGE_ALIGN(mem_start);
+
+ /* Finish header */
+ hdr->magic = OF_DT_HEADER;
+ hdr->totalsize = RELOC(dt_struct_end) - RELOC(dt_header_start);
+ hdr->off_dt_struct = RELOC(dt_struct_start) - RELOC(dt_header_start);
+ hdr->off_dt_strings = RELOC(dt_string_start) - RELOC(dt_header_start);
+ hdr->off_mem_rsvmap = ((unsigned long)rsvmap) - RELOC(dt_header_start);
+ hdr->version = OF_DT_VERSION;
+ hdr->last_comp_version = 1;
+
+ /* Reserve the whole thing and copy the reserve map in, we
+ * also bump mem_reserve_cnt to cause further reservations to
+ * fail since it's too late.
+ */
+ reserve_mem(RELOC(dt_header_start), hdr->totalsize);
+ memcpy(rsvmap, RELOC(mem_reserve_map), sizeof(mem_reserve_map));
+
+#ifdef DEBUG_PROM
+ {
+ int i;
+ prom_printf("reserved memory map:\n");
+ for (i = 0; i < RELOC(mem_reserve_cnt); i++)
+ prom_printf(" %x - %x\n", RELOC(mem_reserve_map)[i].base,
+ RELOC(mem_reserve_map)[i].size);
+ }
+#endif
+ RELOC(mem_reserve_cnt) = MEM_RESERVE_MAP_SIZE;
+
+ prom_printf("Device tree strings 0x%x -> 0x%x\n",
+ RELOC(dt_string_start), RELOC(dt_string_end));
+ prom_printf("Device tree struct 0x%x -> 0x%x\n",
+ RELOC(dt_struct_start), RELOC(dt_struct_end));
+
+ }
+
+static void __init prom_find_boot_cpu(void)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ u32 getprop_rval;
+ ihandle prom_cpu;
+ phandle cpu_pkg;
+
+ if (prom_getprop(_prom->chosen, "cpu", &prom_cpu, sizeof(prom_cpu)) <= 0)
+ prom_panic("cannot find boot cpu");
+
+ cpu_pkg = call_prom("instance-to-package", 1, 1, prom_cpu);
+
+ prom_setprop(cpu_pkg, "linux,boot-cpu", NULL, 0);
+ prom_getprop(cpu_pkg, "reg", &getprop_rval, sizeof(getprop_rval));
+ _prom->cpu = getprop_rval;
+
+ prom_debug("Booting CPU hw index = 0x%x\n", _prom->cpu);
+}
+
+static void __init prom_check_initrd(unsigned long r3, unsigned long r4)
+{
+#ifdef CONFIG_BLK_DEV_INITRD
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+
+ if ( r3 && r4 && r4 != 0xdeadbeef) {
+ u64 val;
+
+ RELOC(prom_initrd_start) = (r3 >= KERNELBASE) ? __pa(r3) : r3;
+ RELOC(prom_initrd_end) = RELOC(prom_initrd_start) + r4;
+
+ val = (u64)RELOC(prom_initrd_start);
+ prom_setprop(_prom->chosen, "linux,initrd-start", &val, sizeof(val));
+ val = (u64)RELOC(prom_initrd_end);
+ prom_setprop(_prom->chosen, "linux,initrd-end", &val, sizeof(val));
+
+ reserve_mem(RELOC(prom_initrd_start),
+ RELOC(prom_initrd_end) - RELOC(prom_initrd_start));
+
+ prom_debug("initrd_start=0x%x\n", RELOC(prom_initrd_start));
+ prom_debug("initrd_end=0x%x\n", RELOC(prom_initrd_end));
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+}
+
+/*
+ * We enter here early on, when the Open Firmware prom is still
+ * handling exceptions and the MMU hash table for us.
+ */
+
+unsigned long __init prom_init(unsigned long r3, unsigned long r4, unsigned long pp,
+ unsigned long r6, unsigned long r7)
+{
+ unsigned long offset = reloc_offset();
+ struct prom_t *_prom = PTRRELOC(&prom);
+ unsigned long phys = KERNELBASE - offset;
+ u32 getprop_rval;
+
+ /*
+ * First zero the BSS
+ */
+ memset(PTRRELOC(&__bss_start), 0, __bss_stop - __bss_start);
+
+ /*
+ * Init interface to Open Firmware, get some node references,
+ * like /chosen
+ */
+ prom_init_client_services(pp);
+
+ /*
+ * Init prom stdout device
+ */
+ prom_init_stdout();
+ prom_debug("klimit=0x%x\n", RELOC(klimit));
+ prom_debug("offset=0x%x\n", offset);
+
+ /*
+ * Reserve kernel in reserve map
+ */
+ reserve_mem(0, __pa(RELOC(klimit)));
+
+ /*
+ * Check for an initrd
+ */
+ prom_check_initrd(r3, r4);
+
+ /*
+ * Get default machine type. At this point, we do not differenciate
+ * between pSeries SMP and pSeries LPAR
+ */
+ RELOC(of_platform) = prom_find_machine_type();
+ getprop_rval = RELOC(of_platform);
+ prom_setprop(_prom->chosen, "linux,platform",
+ &getprop_rval, sizeof(getprop_rval));
+
+ /*
+ * On pSeries, copy the CPU hold code
+ */
+ if (RELOC(of_platform) & PLATFORM_PSERIES)
+ copy_and_flush(0, KERNELBASE - offset, 0x100, 0);
+
+ /*
+ * Get memory cells format
+ */
+ getprop_rval = 1;
+ prom_getprop(_prom->root, "#size-cells",
+ &getprop_rval, sizeof(getprop_rval));
+ _prom->root_size_cells = getprop_rval;
+ getprop_rval = 2;
+ prom_getprop(_prom->root, "#address-cells",
+ &getprop_rval, sizeof(getprop_rval));
+ _prom->root_addr_cells = getprop_rval;
+
+ /*
+ * Do early parsing of command line
+ */
+ early_cmdline_parse();
+
+ /*
+ * Initialize memory management within prom_init
+ */
+ prom_init_mem();
+
+ /*
+ * Determine which cpu is actually running right _now_
+ */
+ prom_find_boot_cpu();
+
+ /*
+ * Initialize display devices
+ */
+ prom_check_displays();
+
+ /*
+ * Initialize IOMMU (TCE tables) on pSeries. Do that before anything else
+ * that uses the allocator, we need to make sure we get the top of memory
+ * available for us here...
+ */
+ if (RELOC(of_platform) == PLATFORM_PSERIES)
+ prom_initialize_tce_table();
+
+ /*
+ * On non-powermacs, try to instantiate RTAS and puts all CPUs
+ * in spin-loops. PowerMacs don't have a working RTAS and use
+ * a different way to spin CPUs
+ */
+ if (RELOC(of_platform) != PLATFORM_POWERMAC) {
+ prom_instantiate_rtas();
+ prom_hold_cpus();
+ }
+
+ /*
+ * Fill in some infos for use by the kernel later on
+ */
+ if (RELOC(ppc64_iommu_off))
+ prom_setprop(_prom->chosen, "linux,iommu-off", NULL, 0);
+ if (RELOC(iommu_force_on))
+ prom_setprop(_prom->chosen, "linux,iommu-force-on", NULL, 0);
+
+ /*
+ * Now finally create the flattened device-tree
+ */
+ prom_printf("copying OF device tree ...\n");
+ flatten_device_tree();
+
+ /*
+ * Call OF "quiesce" method to shut down pending DMA's from
+ * devices etc...
+ */
+ prom_printf("Calling quiesce ...\n");
+ call_prom("quiesce", 0, 0);
+
+ /*
+ * And finally, call the kernel passing it the flattened device
+ * tree and NULL as r5, thus triggering the new entry point which
+ * is common to us and kexec
+ */
+ prom_printf("returning from prom_init\n");
+ prom_debug("->dt_header_start=0x%x\n", RELOC(dt_header_start));
+ prom_debug("->phys=0x%x\n", phys);
+
+ __start(RELOC(dt_header_start), phys, 0);
+
+ return 0;
+}
+
--- /dev/null
+/*
+ * arch/ppc64/kernel/u3_iommu.c
+ *
+ * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
+ *
+ * Based on pSeries_iommu.c:
+ * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
+ * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
+ *
+ * Dynamic DMA mapping support, Apple U3 & IBM CPC925 "DART" iommu.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/ppcdebug.h>
+#include <asm/iommu.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/abs_addr.h>
+#include <asm/cacheflush.h>
+#include <asm/lmb.h>
+
+#include "pci.h"
+
+extern int iommu_force_on;
+
+/* physical base of DART registers */
+#define DART_BASE 0xf8033000UL
+
+/* Offset from base to control register */
+#define DARTCNTL 0
+/* Offset from base to exception register */
+#define DARTEXCP 0x10
+/* Offset from base to TLB tag registers */
+#define DARTTAG 0x1000
+
+
+/* Control Register fields */
+
+/* base address of table (pfn) */
+#define DARTCNTL_BASE_MASK 0xfffff
+#define DARTCNTL_BASE_SHIFT 12
+
+#define DARTCNTL_FLUSHTLB 0x400
+#define DARTCNTL_ENABLE 0x200
+
+/* size of table in pages */
+#define DARTCNTL_SIZE_MASK 0x1ff
+#define DARTCNTL_SIZE_SHIFT 0
+
+/* DART table fields */
+#define DARTMAP_VALID 0x80000000
+#define DARTMAP_RPNMASK 0x00ffffff
+
+/* Physical base address and size of the DART table */
+unsigned long dart_tablebase; /* exported to htab_initialize */
+static unsigned long dart_tablesize;
+
+/* Virtual base address of the DART table */
+static u32 *dart_vbase;
+
+/* Mapped base address for the dart */
+static unsigned int *dart;
+
+/* Dummy val that entries are set to when unused */
+static unsigned int dart_emptyval;
+
+static struct iommu_table iommu_table_u3;
+static int dart_dirty;
+
+#define DBG(...)
+
+static inline void dart_tlb_invalidate_all(void)
+{
+ unsigned long l = 0;
+ unsigned int reg;
+ unsigned long limit;
+
+ DBG("dart: flush\n");
+
+ /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
+ * control register and wait for it to clear.
+ *
+ * Gotcha: Sometimes, the DART won't detect that the bit gets
+ * set. If so, clear it and set it again.
+ */
+
+ limit = 0;
+
+retry:
+ reg = in_be32((unsigned int *)dart+DARTCNTL);
+ reg |= DARTCNTL_FLUSHTLB;
+ out_be32((unsigned int *)dart+DARTCNTL, reg);
+
+ l = 0;
+ while ((in_be32((unsigned int *)dart+DARTCNTL) & DARTCNTL_FLUSHTLB) &&
+ l < (1L<<limit)) {
+ l++;
+ }
+ if (l == (1L<<limit)) {
+ if (limit < 4) {
+ limit++;
+ reg = in_be32((unsigned int *)dart+DARTCNTL);
+ reg &= ~DARTCNTL_FLUSHTLB;
+ out_be32((unsigned int *)dart+DARTCNTL, reg);
+ goto retry;
+ } else
+ panic("U3-DART: TLB did not flush after waiting a long "
+ "time. Buggy U3 ?");
+ }
+}
+
+static void dart_flush(struct iommu_table *tbl)
+{
+ if (dart_dirty)
+ dart_tlb_invalidate_all();
+ dart_dirty = 0;
+}
+
+static void dart_build(struct iommu_table *tbl, long index,
+ long npages, unsigned long uaddr,
+ enum dma_data_direction direction)
+{
+ unsigned int *dp;
+ unsigned int rpn;
+
+ DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
+
+ dp = ((unsigned int*)tbl->it_base) + index;
+
+ /* On U3, all memory is contigous, so we can move this
+ * out of the loop.
+ */
+ while (npages--) {
+ rpn = virt_to_abs(uaddr) >> PAGE_SHIFT;
+
+ *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
+
+ rpn++;
+ uaddr += PAGE_SIZE;
+ }
+
+ dart_dirty = 1;
+}
+
+
+static void dart_free(struct iommu_table *tbl, long index, long npages)
+{
+ unsigned int *dp;
+
+ /* We don't worry about flushing the TLB cache. The only drawback of
+ * not doing it is that we won't catch buggy device drivers doing
+ * bad DMAs, but then no 32-bit architecture ever does either.
+ */
+
+ DBG("dart: free at: %lx, %lx\n", index, npages);
+
+ dp = ((unsigned int *)tbl->it_base) + index;
+
+ while (npages--)
+ *(dp++) = dart_emptyval;
+}
+
+
+static int dart_init(struct device_node *dart_node)
+{
+ unsigned int regword;
+ unsigned int i;
+ unsigned long tmp;
+ struct page *p;
+
+ if (dart_tablebase == 0 || dart_tablesize == 0) {
+ printk(KERN_INFO "U3-DART: table not allocated, using direct DMA\n");
+ return -ENODEV;
+ }
+
+ /* Make sure nothing from the DART range remains in the CPU cache
+ * from a previous mapping that existed before the kernel took
+ * over
+ */
+ flush_dcache_phys_range(dart_tablebase, dart_tablebase + dart_tablesize);
+
+ /* Allocate a spare page to map all invalid DART pages. We need to do
+ * that to work around what looks like a problem with the HT bridge
+ * prefetching into invalid pages and corrupting data
+ */
+ tmp = __get_free_pages(GFP_ATOMIC, 1);
+ if (tmp == 0)
+ panic("U3-DART: Cannot allocate spare page !");
+ dart_emptyval = DARTMAP_VALID |
+ ((virt_to_abs(tmp) >> PAGE_SHIFT) & DARTMAP_RPNMASK);
+
+ /* Map in DART registers. FIXME: Use device node to get base address */
+ dart = ioremap(DART_BASE, 0x7000);
+ if (dart == NULL)
+ panic("U3-DART: Cannot map registers !");
+
+ /* Set initial control register contents: table base,
+ * table size and enable bit
+ */
+ regword = DARTCNTL_ENABLE |
+ ((dart_tablebase >> PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) |
+ (((dart_tablesize >> PAGE_SHIFT) & DARTCNTL_SIZE_MASK)
+ << DARTCNTL_SIZE_SHIFT);
+ p = virt_to_page(dart_tablebase);
+ dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
+
+ /* Fill initial table */
+ for (i = 0; i < dart_tablesize/4; i++)
+ dart_vbase[i] = dart_emptyval;
+
+ /* Initialize DART with table base and enable it. */
+ out_be32((unsigned int *)dart, regword);
+
+ /* Invalidate DART to get rid of possible stale TLBs */
+ dart_tlb_invalidate_all();
+
+ iommu_table_u3.it_busno = 0;
+
+ /* Units of tce entries */
+ iommu_table_u3.it_offset = 0;
+
+ /* Set the tce table size - measured in pages */
+ iommu_table_u3.it_size = dart_tablesize >> PAGE_SHIFT;
+
+ /* Initialize the common IOMMU code */
+ iommu_table_u3.it_base = (unsigned long)dart_vbase;
+ iommu_table_u3.it_index = 0;
+ iommu_table_u3.it_blocksize = 1;
+ iommu_table_u3.it_entrysize = sizeof(u32);
+ iommu_init_table(&iommu_table_u3);
+
+ /* Reserve the last page of the DART to avoid possible prefetch
+ * past the DART mapped area
+ */
+ set_bit(iommu_table_u3.it_mapsize - 1, iommu_table_u3.it_map);
+
+ printk(KERN_INFO "U3/CPC925 DART IOMMU initialized\n");
+
+ return 0;
+}
+
+void iommu_setup_u3(void)
+{
+ struct pci_dev *dev = NULL;
+ struct device_node *dn;
+
+ /* Find the DART in the device-tree */
+ dn = of_find_compatible_node(NULL, "dart", "u3-dart");
+ if (dn == NULL)
+ return;
+
+ /* Setup low level TCE operations for the core IOMMU code */
+ ppc_md.tce_build = dart_build;
+ ppc_md.tce_free = dart_free;
+ ppc_md.tce_flush = dart_flush;
+
+ /* Initialize the DART HW */
+ if (dart_init(dn))
+ return;
+
+ /* Setup pci_dma ops */
+ pci_iommu_init();
+
+ /* We only have one iommu table on the mac for now, which makes
+ * things simple. Setup all PCI devices to point to this table
+ */
+ while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+ /* We must use pci_device_to_OF_node() to make sure that
+ * we get the real "final" pointer to the device in the
+ * pci_dev sysdata and not the temporary PHB one
+ */
+ struct device_node *dn = pci_device_to_OF_node(dev);
+ if (dn)
+ dn->iommu_table = &iommu_table_u3;
+ }
+}
+
+void __init alloc_u3_dart_table(void)
+{
+ /* Only reserve DART space if machine has more than 2GB of RAM
+ * or if requested with iommu=on on cmdline.
+ */
+ if (lmb_end_of_DRAM() <= 0x80000000ull && !iommu_force_on)
+ return;
+
+ /* 512 pages (2MB) is max DART tablesize. */
+ dart_tablesize = 1UL << 21;
+ /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
+ * will blow up an entire large page anyway in the kernel mapping
+ */
+ dart_tablebase = (unsigned long)
+ abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
+
+ printk(KERN_INFO "U3-DART allocated at: %lx\n", dart_tablebase);
+}
--- /dev/null
+/*
+ * native hashtable management.
+ *
+ * SMP scalability work:
+ * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/threads.h>
+#include <linux/smp.h>
+
+#include <asm/abs_addr.h>
+#include <asm/machdep.h>
+#include <asm/mmu.h>
+#include <asm/mmu_context.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+#include <asm/tlb.h>
+#include <asm/cputable.h>
+
+#define HPTE_LOCK_BIT 3
+
+static spinlock_t native_tlbie_lock = SPIN_LOCK_UNLOCKED;
+
+static inline void native_lock_hpte(HPTE *hptep)
+{
+ unsigned long *word = &hptep->dw0.dword0;
+
+ while (1) {
+ if (!test_and_set_bit(HPTE_LOCK_BIT, word))
+ break;
+ while(test_bit(HPTE_LOCK_BIT, word))
+ cpu_relax();
+ }
+}
+
+static inline void native_unlock_hpte(HPTE *hptep)
+{
+ unsigned long *word = &hptep->dw0.dword0;
+
+ asm volatile("lwsync":::"memory");
+ clear_bit(HPTE_LOCK_BIT, word);
+}
+
+long native_hpte_insert(unsigned long hpte_group, unsigned long va,
+ unsigned long prpn, int secondary,
+ unsigned long hpteflags, int bolted, int large)
+{
+ unsigned long arpn = physRpn_to_absRpn(prpn);
+ HPTE *hptep = htab_data.htab + hpte_group;
+ Hpte_dword0 dw0;
+ HPTE lhpte;
+ int i;
+
+ for (i = 0; i < HPTES_PER_GROUP; i++) {
+ dw0 = hptep->dw0.dw0;
+
+ if (!dw0.v) {
+ /* retry with lock held */
+ native_lock_hpte(hptep);
+ dw0 = hptep->dw0.dw0;
+ if (!dw0.v)
+ break;
+ native_unlock_hpte(hptep);
+ }
+
+ hptep++;
+ }
+
+ if (i == HPTES_PER_GROUP)
+ return -1;
+
+ lhpte.dw1.dword1 = 0;
+ lhpte.dw1.dw1.rpn = arpn;
+ lhpte.dw1.flags.flags = hpteflags;
+
+ lhpte.dw0.dword0 = 0;
+ lhpte.dw0.dw0.avpn = va >> 23;
+ lhpte.dw0.dw0.h = secondary;
+ lhpte.dw0.dw0.bolted = bolted;
+ lhpte.dw0.dw0.v = 1;
+
+ if (large) {
+ lhpte.dw0.dw0.l = 1;
+ lhpte.dw0.dw0.avpn &= ~0x1UL;
+ }
+
+ hptep->dw1.dword1 = lhpte.dw1.dword1;
+
+ /* Guarantee the second dword is visible before the valid bit */
+ __asm__ __volatile__ ("eieio" : : : "memory");
+
+ /*
+ * Now set the first dword including the valid bit
+ * NOTE: this also unlocks the hpte
+ */
+ hptep->dw0.dword0 = lhpte.dw0.dword0;
+
+ __asm__ __volatile__ ("ptesync" : : : "memory");
+
+ return i | (secondary << 3);
+}
+
+static long native_hpte_remove(unsigned long hpte_group)
+{
+ HPTE *hptep;
+ Hpte_dword0 dw0;
+ int i;
+ int slot_offset;
+
+ /* pick a random entry to start at */
+ slot_offset = mftb() & 0x7;
+
+ for (i = 0; i < HPTES_PER_GROUP; i++) {
+ hptep = htab_data.htab + hpte_group + slot_offset;
+ dw0 = hptep->dw0.dw0;
+
+ if (dw0.v && !dw0.bolted) {
+ /* retry with lock held */
+ native_lock_hpte(hptep);
+ dw0 = hptep->dw0.dw0;
+ if (dw0.v && !dw0.bolted)
+ break;
+ native_unlock_hpte(hptep);
+ }
+
+ slot_offset++;
+ slot_offset &= 0x7;
+ }
+
+ if (i == HPTES_PER_GROUP)
+ return -1;
+
+ /* Invalidate the hpte. NOTE: this also unlocks it */
+ hptep->dw0.dword0 = 0;
+
+ return i;
+}
+
+static inline void set_pp_bit(unsigned long pp, HPTE *addr)
+{
+ unsigned long old;
+ unsigned long *p = &addr->dw1.dword1;
+
+ __asm__ __volatile__(
+ "1: ldarx %0,0,%3\n\
+ rldimi %0,%2,0,61\n\
+ stdcx. %0,0,%3\n\
+ bne 1b"
+ : "=&r" (old), "=m" (*p)
+ : "r" (pp), "r" (p), "m" (*p)
+ : "cc");
+}
+
+/*
+ * Only works on small pages. Yes its ugly to have to check each slot in
+ * the group but we only use this during bootup.
+ */
+static long native_hpte_find(unsigned long vpn)
+{
+ HPTE *hptep;
+ unsigned long hash;
+ unsigned long i, j;
+ long slot;
+ Hpte_dword0 dw0;
+
+ hash = hpt_hash(vpn, 0);
+
+ for (j = 0; j < 2; j++) {
+ slot = (hash & htab_data.htab_hash_mask) * HPTES_PER_GROUP;
+ for (i = 0; i < HPTES_PER_GROUP; i++) {
+ hptep = htab_data.htab + slot;
+ dw0 = hptep->dw0.dw0;
+
+ if ((dw0.avpn == (vpn >> 11)) && dw0.v &&
+ (dw0.h == j)) {
+ /* HPTE matches */
+ if (j)
+ slot = -slot;
+ return slot;
+ }
+ ++slot;
+ }
+ hash = ~hash;
+ }
+
+ return -1;
+}
+
+static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
+ unsigned long va, int large, int local)
+{
+ HPTE *hptep = htab_data.htab + slot;
+ Hpte_dword0 dw0;
+ unsigned long avpn = va >> 23;
+ int ret = 0;
+
+ if (large)
+ avpn &= ~0x1UL;
+
+ native_lock_hpte(hptep);
+
+ dw0 = hptep->dw0.dw0;
+
+ /* Even if we miss, we need to invalidate the TLB */
+ if ((dw0.avpn != avpn) || !dw0.v) {
+ native_unlock_hpte(hptep);
+ ret = -1;
+ } else {
+ set_pp_bit(newpp, hptep);
+ native_unlock_hpte(hptep);
+ }
+
+ /* Ensure it is out of the tlb too */
+ if ((cur_cpu_spec->cpu_features & CPU_FTR_TLBIEL) && !large && local) {
+ tlbiel(va);
+ } else {
+ int lock_tlbie = !(cur_cpu_spec->cpu_features & CPU_FTR_LOCKLESS_TLBIE);
+
+ if (lock_tlbie)
+ spin_lock(&native_tlbie_lock);
+ tlbie(va, large);
+ if (lock_tlbie)
+ spin_unlock(&native_tlbie_lock);
+ }
+
+ return ret;
+}
+
+/*
+ * Update the page protection bits. Intended to be used to create
+ * guard pages for kernel data structures on pages which are bolted
+ * in the HPT. Assumes pages being operated on will not be stolen.
+ * Does not work on large pages.
+ *
+ * No need to lock here because we should be the only user.
+ */
+static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea)
+{
+ unsigned long vsid, va, vpn, flags;
+ long slot;
+ HPTE *hptep;
+ int lock_tlbie = !(cur_cpu_spec->cpu_features & CPU_FTR_LOCKLESS_TLBIE);
+
+ vsid = get_kernel_vsid(ea);
+ va = (vsid << 28) | (ea & 0x0fffffff);
+ vpn = va >> PAGE_SHIFT;
+
+ slot = native_hpte_find(vpn);
+ if (slot == -1)
+ panic("could not find page to bolt\n");
+ hptep = htab_data.htab + slot;
+
+ set_pp_bit(newpp, hptep);
+
+ /* Ensure it is out of the tlb too */
+ if (lock_tlbie)
+ spin_lock_irqsave(&native_tlbie_lock, flags);
+ tlbie(va, 0);
+ if (lock_tlbie)
+ spin_unlock_irqrestore(&native_tlbie_lock, flags);
+}
+
+static void native_hpte_invalidate(unsigned long slot, unsigned long va,
+ int large, int local)
+{
+ HPTE *hptep = htab_data.htab + slot;
+ Hpte_dword0 dw0;
+ unsigned long avpn = va >> 23;
+ unsigned long flags;
+ int lock_tlbie = !(cur_cpu_spec->cpu_features & CPU_FTR_LOCKLESS_TLBIE);
+
+ if (large)
+ avpn &= ~0x1UL;
+
+ local_irq_save(flags);
+ native_lock_hpte(hptep);
+
+ dw0 = hptep->dw0.dw0;
+
+ /* Even if we miss, we need to invalidate the TLB */
+ if ((dw0.avpn != avpn) || !dw0.v) {
+ native_unlock_hpte(hptep);
+ } else {
+ /* Invalidate the hpte. NOTE: this also unlocks it */
+ hptep->dw0.dword0 = 0;
+ }
+
+ /* Invalidate the tlb */
+ if ((cur_cpu_spec->cpu_features & CPU_FTR_TLBIEL) && !large && local) {
+ tlbiel(va);
+ } else {
+ if (lock_tlbie)
+ spin_lock(&native_tlbie_lock);
+ tlbie(va, large);
+ if (lock_tlbie)
+ spin_unlock(&native_tlbie_lock);
+ }
+ local_irq_restore(flags);
+}
+
+static void native_flush_hash_range(unsigned long context,
+ unsigned long number, int local)
+{
+ unsigned long vsid, vpn, va, hash, secondary, slot, flags, avpn;
+ int i, j;
+ HPTE *hptep;
+ Hpte_dword0 dw0;
+ struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
+
+ /* XXX fix for large ptes */
+ unsigned long large = 0;
+
+ local_irq_save(flags);
+
+ j = 0;
+ for (i = 0; i < number; i++) {
+ if ((batch->addr[i] >= USER_START) &&
+ (batch->addr[i] <= USER_END))
+ vsid = get_vsid(context, batch->addr[i]);
+ else
+ vsid = get_kernel_vsid(batch->addr[i]);
+
+ va = (vsid << 28) | (batch->addr[i] & 0x0fffffff);
+ batch->vaddr[j] = va;
+ if (large)
+ vpn = va >> HPAGE_SHIFT;
+ else
+ vpn = va >> PAGE_SHIFT;
+ hash = hpt_hash(vpn, large);
+ secondary = (pte_val(batch->pte[i]) & _PAGE_SECONDARY) >> 15;
+ if (secondary)
+ hash = ~hash;
+ slot = (hash & htab_data.htab_hash_mask) * HPTES_PER_GROUP;
+ slot += (pte_val(batch->pte[i]) & _PAGE_GROUP_IX) >> 12;
+
+ hptep = htab_data.htab + slot;
+
+ avpn = va >> 23;
+ if (large)
+ avpn &= ~0x1UL;
+
+ native_lock_hpte(hptep);
+
+ dw0 = hptep->dw0.dw0;
+
+ /* Even if we miss, we need to invalidate the TLB */
+ if ((dw0.avpn != avpn) || !dw0.v) {
+ native_unlock_hpte(hptep);
+ } else {
+ /* Invalidate the hpte. NOTE: this also unlocks it */
+ hptep->dw0.dword0 = 0;
+ }
+
+ j++;
+ }
+
+ if ((cur_cpu_spec->cpu_features & CPU_FTR_TLBIEL) && !large && local) {
+ asm volatile("ptesync":::"memory");
+
+ for (i = 0; i < j; i++)
+ __tlbiel(batch->vaddr[i]);
+
+ asm volatile("ptesync":::"memory");
+ } else {
+ int lock_tlbie = !(cur_cpu_spec->cpu_features & CPU_FTR_LOCKLESS_TLBIE);
+
+ if (lock_tlbie)
+ spin_lock(&native_tlbie_lock);
+
+ asm volatile("ptesync":::"memory");
+
+ for (i = 0; i < j; i++)
+ __tlbie(batch->vaddr[i], 0);
+
+ asm volatile("eieio; tlbsync; ptesync":::"memory");
+
+ if (lock_tlbie)
+ spin_unlock(&native_tlbie_lock);
+ }
+
+ local_irq_restore(flags);
+}
+
+void hpte_init_native(void)
+{
+#ifdef CONFIG_PPC_PSERIES
+ struct device_node *root;
+ const char *model;
+#endif /* CONFIG_PPC_PSERIES */
+
+ ppc_md.hpte_invalidate = native_hpte_invalidate;
+ ppc_md.hpte_updatepp = native_hpte_updatepp;
+ ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp;
+ ppc_md.hpte_insert = native_hpte_insert;
+ ppc_md.hpte_remove = native_hpte_remove;
+
+#ifdef CONFIG_PPC_PSERIES
+ /* Disable TLB batching on nighthawk */
+ root = of_find_node_by_path("/");
+ if (root) {
+ model = get_property(root, "model", NULL);
+ if (!strcmp(model, "CHRP IBM,9076-N81")) {
+ of_node_put(root);
+ goto bail;
+ }
+ of_node_put(root);
+ }
+#endif /* CONFIG_PPC_PSERIES */
+
+ ppc_md.flush_hash_range = native_flush_hash_range;
+ bail:
+ htab_finish_init();
+}
--- /dev/null
+/*
+ * linux/arch/ppc64/mm/mmap.c
+ *
+ * flexible mmap layout support
+ *
+ * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina.
+ * All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ *
+ * Started by Ingo Molnar <mingo@elte.hu>
+ */
+
+#include <linux/personality.h>
+#include <linux/mm.h>
+
+/*
+ * Top of mmap area (just below the process stack).
+ *
+ * Leave an at least ~128 MB hole.
+ */
+#define MIN_GAP (128*1024*1024)
+#define MAX_GAP (TASK_SIZE/6*5)
+
+static inline unsigned long mmap_base(void)
+{
+ unsigned long gap = current->rlim[RLIMIT_STACK].rlim_cur;
+
+ if (gap < MIN_GAP)
+ gap = MIN_GAP;
+ else if (gap > MAX_GAP)
+ gap = MAX_GAP;
+
+ return TASK_SIZE - (gap & PAGE_MASK);
+}
+
+static inline int mmap_is_legacy(void)
+{
+ /*
+ * Force standard allocation for 64 bit programs.
+ */
+ if (!test_thread_flag(TIF_32BIT))
+ return 1;
+
+ if (current->personality & ADDR_COMPAT_LAYOUT)
+ return 1;
+
+ if (current->rlim[RLIMIT_STACK].rlim_cur == RLIM_INFINITY)
+ return 1;
+
+ return sysctl_legacy_va_layout;
+}
+
+/*
+ * This function, called very early during the creation of a new
+ * process VM image, sets up which VM layout function to use:
+ */
+void arch_pick_mmap_layout(struct mm_struct *mm)
+{
+ /*
+ * Fall back to the standard layout if the personality
+ * bit is set, or if the expected stack growth is unlimited:
+ */
+ if (mmap_is_legacy()) {
+ mm->mmap_base = TASK_UNMAPPED_BASE;
+ mm->get_unmapped_area = arch_get_unmapped_area;
+ mm->unmap_area = arch_unmap_area;
+ } else {
+ mm->mmap_base = mmap_base();
+ mm->get_unmapped_area = arch_get_unmapped_area_topdown;
+ mm->get_unmapped_exec_area = arch_get_unmapped_exec_area;
+ mm->unmap_area = arch_unmap_area_topdown;
+ }
+}
--- /dev/null
+/*
+ * PowerPC64 Segment Translation Support.
+ *
+ * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
+ * Copyright (c) 2001 Dave Engebretsen
+ *
+ * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/config.h>
+#include <asm/pgtable.h>
+#include <asm/mmu.h>
+#include <asm/mmu_context.h>
+#include <asm/paca.h>
+#include <asm/naca.h>
+#include <asm/cputable.h>
+
+/* Both the segment table and SLB code uses the following cache */
+#define NR_STAB_CACHE_ENTRIES 8
+DEFINE_PER_CPU(long, stab_cache_ptr);
+DEFINE_PER_CPU(long, stab_cache[NR_STAB_CACHE_ENTRIES]);
+
+/*
+ * Create a segment table entry for the given esid/vsid pair.
+ */
+static int make_ste(unsigned long stab, unsigned long esid, unsigned long vsid)
+{
+ unsigned long esid_data, vsid_data;
+ unsigned long entry, group, old_esid, castout_entry, i;
+ unsigned int global_entry;
+ struct stab_entry *ste, *castout_ste;
+ unsigned long kernel_segment = (esid << SID_SHIFT) >= KERNELBASE;
+
+ vsid_data = vsid << STE_VSID_SHIFT;
+ esid_data = esid << SID_SHIFT | STE_ESID_KP | STE_ESID_V;
+ if (! kernel_segment)
+ esid_data |= STE_ESID_KS;
+
+ /* Search the primary group first. */
+ global_entry = (esid & 0x1f) << 3;
+ ste = (struct stab_entry *)(stab | ((esid & 0x1f) << 7));
+
+ /* Find an empty entry, if one exists. */
+ for (group = 0; group < 2; group++) {
+ for (entry = 0; entry < 8; entry++, ste++) {
+ if (!(ste->esid_data & STE_ESID_V)) {
+ ste->vsid_data = vsid_data;
+ asm volatile("eieio":::"memory");
+ ste->esid_data = esid_data;
+ return (global_entry | entry);
+ }
+ }
+ /* Now search the secondary group. */
+ global_entry = ((~esid) & 0x1f) << 3;
+ ste = (struct stab_entry *)(stab | (((~esid) & 0x1f) << 7));
+ }
+
+ /*
+ * Could not find empty entry, pick one with a round robin selection.
+ * Search all entries in the two groups.
+ */
+ castout_entry = get_paca()->stab_rr;
+ for (i = 0; i < 16; i++) {
+ if (castout_entry < 8) {
+ global_entry = (esid & 0x1f) << 3;
+ ste = (struct stab_entry *)(stab | ((esid & 0x1f) << 7));
+ castout_ste = ste + castout_entry;
+ } else {
+ global_entry = ((~esid) & 0x1f) << 3;
+ ste = (struct stab_entry *)(stab | (((~esid) & 0x1f) << 7));
+ castout_ste = ste + (castout_entry - 8);
+ }
+
+ /* Dont cast out the first kernel segment */
+ if ((castout_ste->esid_data & ESID_MASK) != KERNELBASE)
+ break;
+
+ castout_entry = (castout_entry + 1) & 0xf;
+ }
+
+ get_paca()->stab_rr = (castout_entry + 1) & 0xf;
+
+ /* Modify the old entry to the new value. */
+
+ /* Force previous translations to complete. DRENG */
+ asm volatile("isync" : : : "memory");
+
+ old_esid = castout_ste->esid_data >> SID_SHIFT;
+ castout_ste->esid_data = 0; /* Invalidate old entry */
+
+ asm volatile("sync" : : : "memory"); /* Order update */
+
+ castout_ste->vsid_data = vsid_data;
+ asm volatile("eieio" : : : "memory"); /* Order update */
+ castout_ste->esid_data = esid_data;
+
+ asm volatile("slbie %0" : : "r" (old_esid << SID_SHIFT));
+ /* Ensure completion of slbie */
+ asm volatile("sync" : : : "memory");
+
+ return (global_entry | (castout_entry & 0x7));
+}
+
+/*
+ * Allocate a segment table entry for the given ea and mm
+ */
+static int __ste_allocate(unsigned long ea, struct mm_struct *mm)
+{
+ unsigned long vsid;
+ unsigned char stab_entry;
+ unsigned long offset;
+
+ /* Kernel or user address? */
+ if (ea >= KERNELBASE) {
+ vsid = get_kernel_vsid(ea);
+ } else {
+ if ((ea >= TASK_SIZE_USER64) || (! mm))
+ return 1;
+
+ vsid = get_vsid(mm->context.id, ea);
+ }
+
+ stab_entry = make_ste(get_paca()->stab_addr, GET_ESID(ea), vsid);
+
+ if (ea < KERNELBASE) {
+ offset = __get_cpu_var(stab_cache_ptr);
+ if (offset < NR_STAB_CACHE_ENTRIES)
+ __get_cpu_var(stab_cache[offset++]) = stab_entry;
+ else
+ offset = NR_STAB_CACHE_ENTRIES+1;
+ __get_cpu_var(stab_cache_ptr) = offset;
+
+ /* Order update */
+ asm volatile("sync":::"memory");
+ }
+
+ return 0;
+}
+
+int ste_allocate(unsigned long ea)
+{
+ return __ste_allocate(ea, current->mm);
+}
+
+/*
+ * Do the segment table work for a context switch: flush all user
+ * entries from the table, then preload some probably useful entries
+ * for the new task
+ */
+void switch_stab(struct task_struct *tsk, struct mm_struct *mm)
+{
+ struct stab_entry *stab = (struct stab_entry *) get_paca()->stab_addr;
+ struct stab_entry *ste;
+ unsigned long offset = __get_cpu_var(stab_cache_ptr);
+ unsigned long pc = KSTK_EIP(tsk);
+ unsigned long stack = KSTK_ESP(tsk);
+ unsigned long unmapped_base;
+
+ /* Force previous translations to complete. DRENG */
+ asm volatile("isync" : : : "memory");
+
+ if (offset <= NR_STAB_CACHE_ENTRIES) {
+ int i;
+
+ for (i = 0; i < offset; i++) {
+ ste = stab + __get_cpu_var(stab_cache[i]);
+ ste->esid_data = 0; /* invalidate entry */
+ }
+ } else {
+ unsigned long entry;
+
+ /* Invalidate all entries. */
+ ste = stab;
+
+ /* Never flush the first entry. */
+ ste += 1;
+ for (entry = 1;
+ entry < (PAGE_SIZE / sizeof(struct stab_entry));
+ entry++, ste++) {
+ unsigned long ea;
+ ea = ste->esid_data & ESID_MASK;
+ if (ea < KERNELBASE) {
+ ste->esid_data = 0;
+ }
+ }
+ }
+
+ asm volatile("sync; slbia; sync":::"memory");
+
+ __get_cpu_var(stab_cache_ptr) = 0;
+
+ /* Now preload some entries for the new task */
+ if (test_tsk_thread_flag(tsk, TIF_32BIT))
+ unmapped_base = TASK_UNMAPPED_BASE_USER32;
+ else
+ unmapped_base = TASK_UNMAPPED_BASE_USER64;
+
+ __ste_allocate(pc, mm);
+
+ if (GET_ESID(pc) == GET_ESID(stack))
+ return;
+
+ __ste_allocate(stack, mm);
+
+ if ((GET_ESID(pc) == GET_ESID(unmapped_base))
+ || (GET_ESID(stack) == GET_ESID(unmapped_base)))
+ return;
+
+ __ste_allocate(unmapped_base, mm);
+
+ /* Order update */
+ asm volatile("sync" : : : "memory");
+}
+
+extern void slb_initialize(void);
+
+/*
+ * Build an entry for the base kernel segment and put it into
+ * the segment table or SLB. All other segment table or SLB
+ * entries are faulted in.
+ */
+void stab_initialize(unsigned long stab)
+{
+ unsigned long vsid = get_kernel_vsid(KERNELBASE);
+
+ if (cur_cpu_spec->cpu_features & CPU_FTR_SLB) {
+ slb_initialize();
+ } else {
+ asm volatile("isync; slbia; isync":::"memory");
+ make_ste(stab, GET_ESID(KERNELBASE), vsid);
+
+ /* Order update */
+ asm volatile("sync":::"memory");
+ }
+}
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+endmenu
--- /dev/null
+/*
+ * arch/s390/kernel/irq.c
+ *
+ * S390 version
+ * Copyright (C) 2004 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *
+ * This file contains interrupt related functions.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/interrupt.h>
+#include <linux/seq_file.h>
+#include <linux/cpu.h>
+
+/*
+ * show_interrupts is needed by /proc/interrupts.
+ */
+int show_interrupts(struct seq_file *p, void *v)
+{
+ static const char *intrclass_names[] = { "EXT", "I/O", };
+ int i = *(loff_t *) v, j;
+
+ if (i == 0) {
+ seq_puts(p, " ");
+ for (j=0; j<NR_CPUS; j++)
+ if (cpu_online(j))
+ seq_printf(p, "CPU%d ",j);
+ seq_putc(p, '\n');
+ }
+
+ if (i < NR_IRQS) {
+ seq_printf(p, "%s: ", intrclass_names[i]);
+#ifndef CONFIG_SMP
+ seq_printf(p, "%10u ", kstat_irqs(i));
+#else
+ for (j = 0; j < NR_CPUS; j++)
+ if (cpu_online(j))
+ seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
+#endif
+ seq_putc(p, '\n');
+
+ }
+
+ return 0;
+}
+
+/*
+ * For compatibilty only. S/390 specific setup of interrupts et al. is done
+ * much later in init_channel_subsystem().
+ */
+void __init
+init_IRQ(void)
+{
+ /* nothing... */
+}
+
+/*
+ * Switch to the asynchronous interrupt stack for softirq execution.
+ */
+extern void __do_softirq(void);
+
+asmlinkage void do_softirq(void)
+{
+ unsigned long flags, old, new;
+
+ if (in_interrupt())
+ return;
+
+ local_irq_save(flags);
+
+ if (local_softirq_pending()) {
+ /* Get current stack pointer. */
+ asm volatile("la %0,0(15)" : "=a" (old));
+ /* Check against async. stack address range. */
+ new = S390_lowcore.async_stack;
+ if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {
+ /* Need to switch to the async. stack. */
+ new -= STACK_FRAME_OVERHEAD;
+ ((struct stack_frame *) new)->back_chain = old;
+
+ asm volatile(" la 15,0(%0)\n"
+ " basr 14,%2\n"
+ " la 15,0(%1)\n"
+ : : "a" (new), "a" (old),
+ "a" (__do_softirq)
+ : "0", "1", "2", "3", "4", "5",
+ "cc", "memory" );
+ } else
+ /* We are already on the async stack. */
+ __do_softirq();
+ }
+
+ local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(do_softirq);
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config SH_STANDARD_BIOS
+ bool "Use LinuxSH standard BIOS"
+ help
+ Say Y here if your target has the gdb-sh-stub
+ package from www.m17n.org (or any conforming standard LinuxSH BIOS)
+ in FLASH or EPROM. The kernel will use standard BIOS calls during
+ boot for various housekeeping tasks (including calls to read and
+ write characters to a system console, get a MAC address from an
+ on-board Ethernet interface, and shut down the hardware). Note this
+ does not work with machines with an existing operating system in
+ mask ROM and no flash (WindowsCE machines fall in this category).
+ If unsure, say N.
+
+config EARLY_SCIF_CONSOLE
+ bool "Use early SCIF console"
+ depends on CPU_SH4
+
+config EARLY_PRINTK
+ bool "Early printk support"
+ depends on SH_STANDARD_BIOS || EARLY_SCIF_CONSOLE
+ help
+ Say Y here to redirect kernel printk messages to the serial port
+ used by the SH-IPL bootloader, starting very early in the boot
+ process and ending when the kernel's serial console is initialised.
+ This option is only useful porting the kernel to a new machine,
+ when the kernel may crash or hang before the serial console is
+ initialised. If unsure, say N.
+
+config KGDB
+ bool "Include KGDB kernel debugger"
+ help
+ Include in-kernel hooks for kgdb, the Linux kernel source level
+ debugger. See <http://kgdb.sourceforge.net/> for more information.
+ Unless you are intending to debug the kernel, say N here.
+
+menu "KGDB configuration options"
+ depends on KGDB
+
+config MORE_COMPILE_OPTIONS
+ bool "Add any additional compile options"
+ help
+ If you want to add additional CFLAGS to the kernel build, enable this
+ option and then enter what you would like to add in the next question.
+ Note however that -g is already appended with the selection of KGDB.
+
+config COMPILE_OPTIONS
+ string "Additional compile arguments"
+ depends on MORE_COMPILE_OPTIONS
+
+config KGDB_NMI
+ bool "Enter KGDB on NMI"
+ default n
+
+config KGDB_THREAD
+ bool "Include KGDB thread support"
+ default y
+
+config SH_KGDB_CONSOLE
+ bool "Console messages through GDB"
+ default n
+
+config KGDB_SYSRQ
+ bool "Allow SysRq 'G' to enter KGDB"
+ default y
+
+config KGDB_KERNEL_ASSERTS
+ bool "Include KGDB kernel assertions"
+ default n
+
+comment "Serial port setup"
+
+config KGDB_DEFPORT
+ int "Port number (ttySCn)"
+ default "1"
+
+config KGDB_DEFBAUD
+ int "Baud rate"
+ default "115200"
+
+choice
+ prompt "Parity"
+ depends on KGDB
+ default KGDB_DEFPARITY_N
+
+config KGDB_DEFPARITY_N
+ bool "None"
+
+config KGDB_DEFPARITY_E
+ bool "Even"
+
+config KGDB_DEFPARITY_O
+ bool "Odd"
+
+endchoice
+
+choice
+ prompt "Data bits"
+ depends on KGDB
+ default KGDB_DEFBITS_8
+
+config KGDB_DEFBITS_8
+ bool "8"
+
+config KGDB_DEFBITS_7
+ bool "7"
+
+endchoice
+
+endmenu
+
+config FRAME_POINTER
+ bool "Compile the kernel with frame pointers"
+ default y if KGDB
+ help
+ If you say Y here the resulting kernel image will be slightly larger
+ and slower, but it will give very useful debugging information.
+ If you don't debug the kernel, you can say N, but we may not be able
+ to solve problems without frame pointers.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config EARLY_PRINTK
+ bool "Early SCIF console support"
+
+config DEBUG_KERNEL_WITH_GDB_STUB
+ bool "GDB Stub kernel debug"
+
+config SH64_PROC_TLB
+ bool "Debug: report TLB fill/purge activity through /proc/tlb"
+ depends on PROC_FS
+
+config SH64_PROC_ASIDS
+ bool "Debug: report ASIDs through /proc/asids"
+ depends on PROC_FS
+
+config SH64_SR_WATCH
+ bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
+
+config SH_ALPHANUMERIC
+ bool "Enable debug outputs to on-board alphanumeric display"
+
+config SH_NO_BSS_INIT
+ bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)"
+
+config FRAME_POINTER
+ bool "Compile the kernel with frame pointers"
+ default y if KGDB
+ help
+ If you say Y here the resulting kernel image will be slightly larger
+ and slower, but it will give very useful debugging information.
+ If you don't debug the kernel, you can say N, but we may not be able
+ to solve problems without frame pointers.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config DEBUG_STACK_USAGE
+ bool "Enable stack utilization instrumentation"
+ depends on DEBUG_KERNEL
+ help
+ Enables the display of the minimum amount of free stack which each
+ task has ever had available in the sysrq-T and sysrq-P debug output.
+
+ This option will slow down process creation somewhat.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config DEBUG_STACK_USAGE
+ bool "Enable stack utilization instrumentation"
+ depends on DEBUG_KERNEL
+ help
+ Enables the display of the minimum amount of free stack which each
+ task has ever had available in the sysrq-T and sysrq-P debug output.
+
+ This option will slow down process creation somewhat.
+
+config KPROBES
+ bool "Kprobes"
+ depends on DEBUG_KERNEL
+ help
+ Kprobes allows you to trap at almost any kernel address and
+ execute a callback function. register_kprobe() establishes
+ a probepoint and specifies the callback. Kprobes is useful
+ for kernel debugging, non-intrusive instrumentation and testing.
+ If in doubt, say "N".
+
+config DEBUG_DCFLUSH
+ bool "D-cache flush debugging"
+ depends on DEBUG_KERNEL
+
+config STACK_DEBUG
+ depends on DEBUG_KERNEL
+ bool "Stack Overflow Detection Support"
+
+config DEBUG_BOOTMEM
+ depends on DEBUG_KERNEL
+ bool "Debug BOOTMEM initialization"
+
+# We have a custom atomic_dec_and_lock() implementation but it's not
+# compatible with spinlock debugging so we need to fall back on
+# the generic version in that case.
+config HAVE_DEC_LOCK
+ bool
+ depends on SMP && !DEBUG_SPINLOCK
+ default y
+
+config MCOUNT
+ bool
+ depends on STACK_DEBUG
+ default y
+
+config FRAME_POINTER
+ bool
+ depends on MCOUNT
+ default y
+
+endmenu
--- /dev/null
+/* arch/sparc64/kernel/kprobes.c
+ *
+ * Copyright (C) 2004 David S. Miller <davem@davemloft.net>
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/kprobes.h>
+
+#include <asm/kdebug.h>
+#include <asm/signal.h>
+
+/* We do not have hardware single-stepping on sparc64.
+ * So we implement software single-stepping with breakpoint
+ * traps. The top-level scheme is similar to that used
+ * in the x86 kprobes implementation.
+ *
+ * In the kprobe->insn[] array we store the original
+ * instruction at index zero and a break instruction at
+ * index one.
+ *
+ * When we hit a kprobe we:
+ * - Run the pre-handler
+ * - Remember "regs->tnpc" and interrupt level stored in
+ * "regs->tstate" so we can restore them later
+ * - Disable PIL interrupts
+ * - Set regs->tpc to point to kprobe->insn[0]
+ * - Set regs->tnpc to point to kprobe->insn[1]
+ * - Mark that we are actively in a kprobe
+ *
+ * At this point we wait for the second breakpoint at
+ * kprobe->insn[1] to hit. When it does we:
+ * - Run the post-handler
+ * - Set regs->tpc to "remembered" regs->tnpc stored above,
+ * restore the PIL interrupt level in "regs->tstate" as well
+ * - Make any adjustments necessary to regs->tnpc in order
+ * to handle relative branches correctly. See below.
+ * - Mark that we are no longer actively in a kprobe.
+ */
+
+void arch_prepare_kprobe(struct kprobe *p)
+{
+ p->insn[0] = *p->addr;
+ p->insn[1] = BREAKPOINT_INSTRUCTION_2;
+}
+
+/* kprobe_status settings */
+#define KPROBE_HIT_ACTIVE 0x00000001
+#define KPROBE_HIT_SS 0x00000002
+
+static struct kprobe *current_kprobe;
+static unsigned long current_kprobe_orig_tnpc;
+static unsigned long current_kprobe_orig_tstate_pil;
+static unsigned int kprobe_status;
+
+static inline void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+ current_kprobe_orig_tnpc = regs->tnpc;
+ current_kprobe_orig_tstate_pil = (regs->tstate & TSTATE_PIL);
+ regs->tstate |= TSTATE_PIL;
+
+ regs->tpc = (unsigned long) &p->insn[0];
+ regs->tnpc = (unsigned long) &p->insn[1];
+}
+
+static inline void disarm_kprobe(struct kprobe *p, struct pt_regs *regs)
+{
+ *p->addr = p->opcode;
+ flushi(p->addr);
+
+ regs->tpc = (unsigned long) p->addr;
+ regs->tnpc = current_kprobe_orig_tnpc;
+ regs->tstate = ((regs->tstate & ~TSTATE_PIL) |
+ current_kprobe_orig_tstate_pil);
+}
+
+static int kprobe_handler(struct pt_regs *regs)
+{
+ struct kprobe *p;
+ void *addr = (void *) regs->tpc;
+ int ret = 0;
+
+ preempt_disable();
+
+ if (kprobe_running()) {
+ /* We *are* holding lock here, so this is safe.
+ * Disarm the probe we just hit, and ignore it.
+ */
+ p = get_kprobe(addr);
+ if (p) {
+ disarm_kprobe(p, regs);
+ ret = 1;
+ } else {
+ p = current_kprobe;
+ if (p->break_handler && p->break_handler(p, regs))
+ goto ss_probe;
+ }
+ /* If it's not ours, can't be delete race, (we hold lock). */
+ goto no_kprobe;
+ }
+
+ lock_kprobes();
+ p = get_kprobe(addr);
+ if (!p) {
+ unlock_kprobes();
+ if (*(u32 *)addr != BREAKPOINT_INSTRUCTION) {
+ /*
+ * The breakpoint instruction was removed right
+ * after we hit it. Another cpu has removed
+ * either a probepoint or a debugger breakpoint
+ * at this address. In either case, no further
+ * handling of this interrupt is appropriate.
+ */
+ ret = 1;
+ }
+ /* Not one of ours: let kernel handle it */
+ goto no_kprobe;
+ }
+
+ kprobe_status = KPROBE_HIT_ACTIVE;
+ current_kprobe = p;
+ if (p->pre_handler(p, regs))
+ return 1;
+
+ss_probe:
+ prepare_singlestep(p, regs);
+ kprobe_status = KPROBE_HIT_SS;
+ return 1;
+
+no_kprobe:
+ preempt_enable_no_resched();
+ return ret;
+}
+
+/* If INSN is a relative control transfer instruction,
+ * return the corrected branch destination value.
+ *
+ * The original INSN location was REAL_PC, it actually
+ * executed at PC and produced destination address NPC.
+ */
+static unsigned long relbranch_fixup(u32 insn, unsigned long real_pc,
+ unsigned long pc, unsigned long npc)
+{
+ /* Branch not taken, no mods necessary. */
+ if (npc == pc + 0x4UL)
+ return real_pc + 0x4UL;
+
+ /* The three cases are call, branch w/prediction,
+ * and traditional branch.
+ */
+ if ((insn & 0xc0000000) == 0x40000000 ||
+ (insn & 0xc1c00000) == 0x00400000 ||
+ (insn & 0xc1c00000) == 0x00800000) {
+ /* The instruction did all the work for us
+ * already, just apply the offset to the correct
+ * instruction location.
+ */
+ return (real_pc + (npc - pc));
+ }
+
+ return real_pc + 0x4UL;
+}
+
+/* If INSN is an instruction which writes it's PC location
+ * into a destination register, fix that up.
+ */
+static void retpc_fixup(struct pt_regs *regs, u32 insn, unsigned long real_pc)
+{
+ unsigned long *slot = NULL;
+
+ /* Simplest cast is call, which always uses %o7 */
+ if ((insn & 0xc0000000) == 0x40000000) {
+ slot = ®s->u_regs[UREG_I7];
+ }
+
+ /* Jmpl encodes the register inside of the opcode */
+ if ((insn & 0xc1f80000) == 0x81c00000) {
+ unsigned long rd = ((insn >> 25) & 0x1f);
+
+ if (rd <= 15) {
+ slot = ®s->u_regs[rd];
+ } else {
+ /* Hard case, it goes onto the stack. */
+ flushw_all();
+
+ rd -= 16;
+ slot = (unsigned long *)
+ (regs->u_regs[UREG_FP] + STACK_BIAS);
+ slot += rd;
+ }
+ }
+ if (slot != NULL)
+ *slot = real_pc;
+}
+
+/*
+ * Called after single-stepping. p->addr is the address of the
+ * instruction whose first byte has been replaced by the breakpoint
+ * instruction. To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction. The address of this
+ * copy is p->insn.
+ *
+ * This function prepares to return from the post-single-step
+ * breakpoint trap.
+ */
+static void resume_execution(struct kprobe *p, struct pt_regs *regs)
+{
+ u32 insn = p->insn[0];
+
+ regs->tpc = current_kprobe_orig_tnpc;
+ regs->tnpc = relbranch_fixup(insn,
+ (unsigned long) p->addr,
+ (unsigned long) &p->insn[0],
+ regs->tnpc);
+ retpc_fixup(regs, insn, (unsigned long) p->addr);
+
+ regs->tstate = ((regs->tstate & ~TSTATE_PIL) |
+ current_kprobe_orig_tstate_pil);
+}
+
+static inline int post_kprobe_handler(struct pt_regs *regs)
+{
+ if (!kprobe_running())
+ return 0;
+
+ if (current_kprobe->post_handler)
+ current_kprobe->post_handler(current_kprobe, regs, 0);
+
+ resume_execution(current_kprobe, regs);
+
+ unlock_kprobes();
+ preempt_enable_no_resched();
+
+ return 1;
+}
+
+/* Interrupts disabled, kprobe_lock held. */
+static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+ if (current_kprobe->fault_handler
+ && current_kprobe->fault_handler(current_kprobe, regs, trapnr))
+ return 1;
+
+ if (kprobe_status & KPROBE_HIT_SS) {
+ resume_execution(current_kprobe, regs);
+
+ unlock_kprobes();
+ preempt_enable_no_resched();
+ }
+ return 0;
+}
+
+/*
+ * Wrapper routine to for handling exceptions.
+ */
+int kprobe_exceptions_notify(struct notifier_block *self, unsigned long val,
+ void *data)
+{
+ struct die_args *args = (struct die_args *)data;
+ switch (val) {
+ case DIE_DEBUG:
+ if (kprobe_handler(args->regs))
+ return NOTIFY_STOP;
+ break;
+ case DIE_DEBUG_2:
+ if (post_kprobe_handler(args->regs))
+ return NOTIFY_STOP;
+ break;
+ case DIE_GPF:
+ if (kprobe_running() &&
+ kprobe_fault_handler(args->regs, args->trapnr))
+ return NOTIFY_STOP;
+ break;
+ case DIE_PAGE_FAULT:
+ if (kprobe_running() &&
+ kprobe_fault_handler(args->regs, args->trapnr))
+ return NOTIFY_STOP;
+ break;
+ default:
+ break;
+ }
+ return NOTIFY_DONE;
+}
+
+asmlinkage void kprobe_trap(unsigned long trap_level, struct pt_regs *regs)
+{
+ BUG_ON(trap_level != 0x170 && trap_level != 0x171);
+
+ if (user_mode(regs)) {
+ local_irq_enable();
+ bad_trap(regs, trap_level);
+ return;
+ }
+
+ /* trap_level == 0x170 --> ta 0x70
+ * trap_level == 0x171 --> ta 0x71
+ */
+ if (notify_die((trap_level == 0x170) ? DIE_DEBUG : DIE_DEBUG_2,
+ (trap_level == 0x170) ? "debug" : "debug_2",
+ regs, 0, trap_level, SIGTRAP) != NOTIFY_STOP)
+ bad_trap(regs, trap_level);
+}
+
+/* Jprobes support. */
+static struct pt_regs jprobe_saved_regs;
+static struct pt_regs *jprobe_saved_regs_location;
+static struct sparc_stackf jprobe_saved_stack;
+
+int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+ struct jprobe *jp = container_of(p, struct jprobe, kp);
+
+ jprobe_saved_regs_location = regs;
+ memcpy(&jprobe_saved_regs, regs, sizeof(*regs));
+
+ /* Save a whole stack frame, this gets arguments
+ * pushed onto the stack after using up all the
+ * arg registers.
+ */
+ memcpy(&jprobe_saved_stack,
+ (char *) (regs->u_regs[UREG_FP] + STACK_BIAS),
+ sizeof(jprobe_saved_stack));
+
+ regs->tpc = (unsigned long) jp->entry;
+ regs->tnpc = ((unsigned long) jp->entry) + 0x4UL;
+ regs->tstate |= TSTATE_PIL;
+
+ return 1;
+}
+
+void jprobe_return(void)
+{
+ preempt_enable_no_resched();
+ __asm__ __volatile__(
+ ".globl jprobe_return_trap_instruction\n"
+"jprobe_return_trap_instruction:\n\t"
+ "ta 0x70");
+}
+
+extern void jprobe_return_trap_instruction(void);
+
+extern void __show_regs(struct pt_regs * regs);
+
+int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+ u32 *addr = (u32 *) regs->tpc;
+
+ if (addr == (u32 *) jprobe_return_trap_instruction) {
+ if (jprobe_saved_regs_location != regs) {
+ printk("JPROBE: Current regs (%p) does not match "
+ "saved regs (%p).\n",
+ regs, jprobe_saved_regs_location);
+ printk("JPROBE: Saved registers\n");
+ __show_regs(jprobe_saved_regs_location);
+ printk("JPROBE: Current registers\n");
+ __show_regs(regs);
+ BUG();
+ }
+ /* Restore old register state. Do pt_regs
+ * first so that UREG_FP is the original one for
+ * the stack frame restore.
+ */
+ memcpy(regs, &jprobe_saved_regs, sizeof(*regs));
+
+ memcpy((char *) (regs->u_regs[UREG_FP] + STACK_BIAS),
+ &jprobe_saved_stack,
+ sizeof(jprobe_saved_stack));
+
+ return 1;
+ }
+ return 0;
+}
--- /dev/null
+/* U1copy_from_user.S: UltraSparc-I/II/IIi/IIe optimized copy from userspace.
+ *
+ * Copyright (C) 1999, 2000, 2004 David S. Miller (davem@redhat.com)
+ */
+
+#define EX_LD(x) \
+98: x; \
+ .section .fixup; \
+ .align 4; \
+99: retl; \
+ mov 1, %o0; \
+ .section __ex_table; \
+ .align 4; \
+ .word 98b, 99b; \
+ .text; \
+ .align 4;
+
+#define FUNC_NAME ___copy_from_user
+#define LOAD(type,addr,dest) type##a [addr] %asi, dest
+#define LOAD_BLK(addr,dest) ldda [addr] ASI_BLK_AIUS, dest
+#define EX_RETVAL(x) 0
+
+ /* Writing to %asi is _expensive_ so we hardcode it.
+ * Reading %asi to check for KERNEL_DS is comparatively
+ * cheap.
+ */
+#define PREAMBLE \
+ rd %asi, %g1; \
+ cmp %g1, ASI_AIUS; \
+ bne,pn %icc, memcpy_user_stub; \
+ nop; \
+
+#include "U1memcpy.S"
--- /dev/null
+/* U1copy_to_user.S: UltraSparc-I/II/IIi/IIe optimized copy to userspace.
+ *
+ * Copyright (C) 1999, 2000, 2004 David S. Miller (davem@redhat.com)
+ */
+
+#define EX_ST(x) \
+98: x; \
+ .section .fixup; \
+ .align 4; \
+99: retl; \
+ mov 1, %o0; \
+ .section __ex_table; \
+ .align 4; \
+ .word 98b, 99b; \
+ .text; \
+ .align 4;
+
+#define FUNC_NAME ___copy_to_user
+#define STORE(type,src,addr) type##a src, [addr] ASI_AIUS
+#define STORE_BLK(src,addr) stda src, [addr] ASI_BLK_AIUS
+#define EX_RETVAL(x) 0
+
+ /* Writing to %asi is _expensive_ so we hardcode it.
+ * Reading %asi to check for KERNEL_DS is comparatively
+ * cheap.
+ */
+#define PREAMBLE \
+ rd %asi, %g1; \
+ cmp %g1, ASI_AIUS; \
+ bne,pn %icc, memcpy_user_stub; \
+ nop; \
+
+#include "U1memcpy.S"
--- /dev/null
+/* U1memcpy.S: UltraSPARC-I/II/IIi/IIe optimized memcpy.
+ *
+ * Copyright (C) 1997, 2004 David S. Miller (davem@redhat.com)
+ * Copyright (C) 1996, 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+#ifdef __KERNEL__
+#include <asm/visasm.h>
+#include <asm/asi.h>
+#else
+#define ASI_BLK_P 0xf0
+#define FPRS_FEF 0x04
+#ifdef MEMCPY_DEBUG
+#define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
+ clr %g1; clr %g2; clr %g3; subcc %g0, %g0, %g0;
+#define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
+#else
+#define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
+#define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
+#endif
+#endif
+
+#ifndef EX_LD
+#define EX_LD(x) x
+#endif
+
+#ifndef EX_ST
+#define EX_ST(x) x
+#endif
+
+#ifndef EX_RETVAL
+#define EX_RETVAL(x) x
+#endif
+
+#ifndef LOAD
+#define LOAD(type,addr,dest) type [addr], dest
+#endif
+
+#ifndef LOAD_BLK
+#define LOAD_BLK(addr,dest) ldda [addr] ASI_BLK_P, dest
+#endif
+
+#ifndef STORE
+#define STORE(type,src,addr) type src, [addr]
+#endif
+
+#ifndef STORE_BLK
+#define STORE_BLK(src,addr) stda src, [addr] ASI_BLK_P
+#endif
+
+#ifndef FUNC_NAME
+#define FUNC_NAME memcpy
+#endif
+
+#ifndef PREAMBLE
+#define PREAMBLE
+#endif
+
+#ifndef XCC
+#define XCC xcc
+#endif
+
+#define FREG_FROB(f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ faligndata %f1, %f2, %f48; \
+ faligndata %f2, %f3, %f50; \
+ faligndata %f3, %f4, %f52; \
+ faligndata %f4, %f5, %f54; \
+ faligndata %f5, %f6, %f56; \
+ faligndata %f6, %f7, %f58; \
+ faligndata %f7, %f8, %f60; \
+ faligndata %f8, %f9, %f62;
+
+#define MAIN_LOOP_CHUNK(src, dest, fdest, fsrc, len, jmptgt) \
+ EX_LD(LOAD_BLK(%src, %fdest)); \
+ EX_ST(STORE_BLK(%fsrc, %dest)); \
+ add %src, 0x40, %src; \
+ subcc %len, 0x40, %len; \
+ be,pn %xcc, jmptgt; \
+ add %dest, 0x40, %dest; \
+
+#define LOOP_CHUNK1(src, dest, len, branch_dest) \
+ MAIN_LOOP_CHUNK(src, dest, f0, f48, len, branch_dest)
+#define LOOP_CHUNK2(src, dest, len, branch_dest) \
+ MAIN_LOOP_CHUNK(src, dest, f16, f48, len, branch_dest)
+#define LOOP_CHUNK3(src, dest, len, branch_dest) \
+ MAIN_LOOP_CHUNK(src, dest, f32, f48, len, branch_dest)
+
+#define STORE_SYNC(dest, fsrc) \
+ EX_ST(STORE_BLK(%fsrc, %dest)); \
+ add %dest, 0x40, %dest;
+
+#define STORE_JUMP(dest, fsrc, target) \
+ EX_ST(STORE_BLK(%fsrc, %dest)); \
+ add %dest, 0x40, %dest; \
+ ba,pt %xcc, target;
+
+#define FINISH_VISCHUNK(dest, f0, f1, left) \
+ subcc %left, 8, %left;\
+ bl,pn %xcc, 95f; \
+ faligndata %f0, %f1, %f48; \
+ EX_ST(STORE(std, %f48, %dest)); \
+ add %dest, 8, %dest;
+
+#define UNEVEN_VISCHUNK_LAST(dest, f0, f1, left) \
+ subcc %left, 8, %left; \
+ bl,pn %xcc, 95f; \
+ fsrc1 %f0, %f1;
+
+#define UNEVEN_VISCHUNK(dest, f0, f1, left) \
+ UNEVEN_VISCHUNK_LAST(dest, f0, f1, left) \
+ ba,a,pt %xcc, 93f;
+
+ .register %g2,#scratch
+ .register %g3,#scratch
+
+ .text
+ .align 64
+
+ .globl FUNC_NAME
+ .type FUNC_NAME,#function
+FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
+ PREAMBLE
+ mov %o0, %g5
+ cmp %o2, 0
+ be,pn %XCC, 85f
+ or %o0, %o1, %o3
+ cmp %o2, 16
+ blu,a,pn %XCC, 80f
+ or %o3, %o2, %o3
+
+ cmp %o2, (5 * 64)
+ blu,pt %XCC, 70f
+ andcc %o3, 0x7, %g0
+
+ /* Clobbers o5/g1/g2/g3/g7/icc/xcc. */
+ VISEntry
+
+ /* Is 'dst' already aligned on an 64-byte boundary? */
+ andcc %o0, 0x3f, %g2
+ be,pt %XCC, 2f
+
+ /* Compute abs((dst & 0x3f) - 0x40) into %g2. This is the number
+ * of bytes to copy to make 'dst' 64-byte aligned. We pre-
+ * subtract this from 'len'.
+ */
+ sub %o0, %o1, %o4
+ sub %g2, 0x40, %g2
+ sub %g0, %g2, %g2
+ sub %o2, %g2, %o2
+ andcc %g2, 0x7, %g1
+ be,pt %icc, 2f
+ and %g2, 0x38, %g2
+
+1: subcc %g1, 0x1, %g1
+ EX_LD(LOAD(ldub, %o1 + 0x00, %o3))
+ EX_ST(STORE(stb, %o3, %o1 + %o4))
+ bgu,pt %XCC, 1b
+ add %o1, 0x1, %o1
+
+ add %o1, %o4, %o0
+
+2: cmp %g2, 0x0
+ and %o1, 0x7, %g1
+ be,pt %icc, 3f
+ alignaddr %o1, %g0, %o1
+
+ EX_LD(LOAD(ldd, %o1, %f4))
+1: EX_LD(LOAD(ldd, %o1 + 0x8, %f6))
+ add %o1, 0x8, %o1
+ subcc %g2, 0x8, %g2
+ faligndata %f4, %f6, %f0
+ EX_ST(STORE(std, %f0, %o0))
+ be,pn %icc, 3f
+ add %o0, 0x8, %o0
+
+ EX_LD(LOAD(ldd, %o1 + 0x8, %f4))
+ add %o1, 0x8, %o1
+ subcc %g2, 0x8, %g2
+ faligndata %f6, %f4, %f0
+ EX_ST(STORE(std, %f0, %o0))
+ bne,pt %icc, 1b
+ add %o0, 0x8, %o0
+
+ /* Destination is 64-byte aligned. */
+3:
+ membar #LoadStore | #StoreStore | #StoreLoad
+
+ subcc %o2, 0x40, %o4
+ add %o1, %g1, %g1
+ andncc %o4, (0x40 - 1), %o4
+ srl %g1, 3, %g2
+ sub %o2, %o4, %g3
+ andn %o1, (0x40 - 1), %o1
+ and %g2, 7, %g2
+ andncc %g3, 0x7, %g3
+ fmovd %f0, %f2
+ sub %g3, 0x8, %g3
+ sub %o2, %o4, %o2
+
+ add %g1, %o4, %g1
+ subcc %o2, %g3, %o2
+
+ EX_LD(LOAD_BLK(%o1, %f0))
+ add %o1, 0x40, %o1
+ add %g1, %g3, %g1
+ EX_LD(LOAD_BLK(%o1, %f16))
+ add %o1, 0x40, %o1
+ sub %o4, 0x80, %o4
+ EX_LD(LOAD_BLK(%o1, %f32))
+ add %o1, 0x40, %o1
+
+ /* There are 8 instances of the unrolled loop,
+ * one for each possible alignment of the
+ * source buffer. Each loop instance is 452
+ * bytes.
+ */
+ sll %g2, 3, %o3
+ sub %o3, %g2, %o3
+ sllx %o3, 4, %o3
+ add %o3, %g2, %o3
+ sllx %o3, 2, %g2
+1: rd %pc, %o3
+ add %o3, %lo(1f - 1b), %o3
+ jmpl %o3 + %g2, %g0
+ nop
+
+ .align 64
+1: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f0, %f2, %f48
+1: FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0)
+ STORE_JUMP(o0, f48, 40f) membar #Sync
+2: FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
+ STORE_JUMP(o0, f48, 48f) membar #Sync
+3: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32)
+ STORE_JUMP(o0, f48, 56f) membar #Sync
+
+1: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f2, %f4, %f48
+1: FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2)
+ STORE_JUMP(o0, f48, 41f) membar #Sync
+2: FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
+ STORE_JUMP(o0, f48, 49f) membar #Sync
+3: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34)
+ STORE_JUMP(o0, f48, 57f) membar #Sync
+
+1: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f4, %f6, %f48
+1: FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4)
+ STORE_JUMP(o0, f48, 42f) membar #Sync
+2: FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20)
+ STORE_JUMP(o0, f48, 50f) membar #Sync
+3: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36)
+ STORE_JUMP(o0, f48, 58f) membar #Sync
+
+1: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f6, %f8, %f48
+1: FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6)
+ STORE_JUMP(o0, f48, 43f) membar #Sync
+2: FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22)
+ STORE_JUMP(o0, f48, 51f) membar #Sync
+3: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38)
+ STORE_JUMP(o0, f48, 59f) membar #Sync
+
+1: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f8, %f10, %f48
+1: FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8)
+ STORE_JUMP(o0, f48, 44f) membar #Sync
+2: FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24)
+ STORE_JUMP(o0, f48, 52f) membar #Sync
+3: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40)
+ STORE_JUMP(o0, f48, 60f) membar #Sync
+
+1: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f10, %f12, %f48
+1: FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10)
+ STORE_JUMP(o0, f48, 45f) membar #Sync
+2: FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26)
+ STORE_JUMP(o0, f48, 53f) membar #Sync
+3: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42)
+ STORE_JUMP(o0, f48, 61f) membar #Sync
+
+1: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f12, %f14, %f48
+1: FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12)
+ STORE_JUMP(o0, f48, 46f) membar #Sync
+2: FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28)
+ STORE_JUMP(o0, f48, 54f) membar #Sync
+3: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44)
+ STORE_JUMP(o0, f48, 62f) membar #Sync
+
+1: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30)
+ LOOP_CHUNK1(o1, o0, o4, 1f)
+ FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46)
+ LOOP_CHUNK2(o1, o0, o4, 2f)
+ FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14)
+ LOOP_CHUNK3(o1, o0, o4, 3f)
+ ba,pt %xcc, 1b+4
+ faligndata %f14, %f16, %f48
+1: FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14)
+ STORE_JUMP(o0, f48, 47f) membar #Sync
+2: FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30)
+ STORE_JUMP(o0, f48, 55f) membar #Sync
+3: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30)
+ STORE_SYNC(o0, f48) membar #Sync
+ FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46)
+ STORE_JUMP(o0, f48, 63f) membar #Sync
+
+40: FINISH_VISCHUNK(o0, f0, f2, g3)
+41: FINISH_VISCHUNK(o0, f2, f4, g3)
+42: FINISH_VISCHUNK(o0, f4, f6, g3)
+43: FINISH_VISCHUNK(o0, f6, f8, g3)
+44: FINISH_VISCHUNK(o0, f8, f10, g3)
+45: FINISH_VISCHUNK(o0, f10, f12, g3)
+46: FINISH_VISCHUNK(o0, f12, f14, g3)
+47: UNEVEN_VISCHUNK(o0, f14, f0, g3)
+48: FINISH_VISCHUNK(o0, f16, f18, g3)
+49: FINISH_VISCHUNK(o0, f18, f20, g3)
+50: FINISH_VISCHUNK(o0, f20, f22, g3)
+51: FINISH_VISCHUNK(o0, f22, f24, g3)
+52: FINISH_VISCHUNK(o0, f24, f26, g3)
+53: FINISH_VISCHUNK(o0, f26, f28, g3)
+54: FINISH_VISCHUNK(o0, f28, f30, g3)
+55: UNEVEN_VISCHUNK(o0, f30, f0, g3)
+56: FINISH_VISCHUNK(o0, f32, f34, g3)
+57: FINISH_VISCHUNK(o0, f34, f36, g3)
+58: FINISH_VISCHUNK(o0, f36, f38, g3)
+59: FINISH_VISCHUNK(o0, f38, f40, g3)
+60: FINISH_VISCHUNK(o0, f40, f42, g3)
+61: FINISH_VISCHUNK(o0, f42, f44, g3)
+62: FINISH_VISCHUNK(o0, f44, f46, g3)
+63: UNEVEN_VISCHUNK_LAST(o0, f46, f0, g3)
+
+93: EX_LD(LOAD(ldd, %o1, %f2))
+ add %o1, 8, %o1
+ subcc %g3, 8, %g3
+ faligndata %f0, %f2, %f8
+ EX_ST(STORE(std, %f8, %o0))
+ bl,pn %xcc, 95f
+ add %o0, 8, %o0
+ EX_LD(LOAD(ldd, %o1, %f0))
+ add %o1, 8, %o1
+ subcc %g3, 8, %g3
+ faligndata %f2, %f0, %f8
+ EX_ST(STORE(std, %f8, %o0))
+ bge,pt %xcc, 93b
+ add %o0, 8, %o0
+
+95: brz,pt %o2, 2f
+ mov %g1, %o1
+
+1: EX_LD(LOAD(ldub, %o1, %o3))
+ add %o1, 1, %o1
+ subcc %o2, 1, %o2
+ EX_ST(STORE(stb, %o3, %o0))
+ bne,pt %xcc, 1b
+ add %o0, 1, %o0
+
+2: membar #StoreLoad | #StoreStore
+ VISExit
+ retl
+ mov EX_RETVAL(%g5), %o0
+
+ .align 64
+70: /* 16 < len <= (5 * 64) */
+ bne,pn %XCC, 75f
+ sub %o0, %o1, %o3
+
+72: andn %o2, 0xf, %o4
+ and %o2, 0xf, %o2
+1: EX_LD(LOAD(ldx, %o1 + 0x00, %o5))
+ EX_LD(LOAD(ldx, %o1 + 0x08, %g1))
+ subcc %o4, 0x10, %o4
+ EX_ST(STORE(stx, %o5, %o1 + %o3))
+ add %o1, 0x8, %o1
+ EX_ST(STORE(stx, %g1, %o1 + %o3))
+ bgu,pt %XCC, 1b
+ add %o1, 0x8, %o1
+73: andcc %o2, 0x8, %g0
+ be,pt %XCC, 1f
+ nop
+ EX_LD(LOAD(ldx, %o1, %o5))
+ sub %o2, 0x8, %o2
+ EX_ST(STORE(stx, %o5, %o1 + %o3))
+ add %o1, 0x8, %o1
+1: andcc %o2, 0x4, %g0
+ be,pt %XCC, 1f
+ nop
+ EX_LD(LOAD(lduw, %o1, %o5))
+ sub %o2, 0x4, %o2
+ EX_ST(STORE(stw, %o5, %o1 + %o3))
+ add %o1, 0x4, %o1
+1: cmp %o2, 0
+ be,pt %XCC, 85f
+ nop
+ ba,pt %xcc, 90f
+ nop
+
+75: andcc %o0, 0x7, %g1
+ sub %g1, 0x8, %g1
+ be,pn %icc, 2f
+ sub %g0, %g1, %g1
+ sub %o2, %g1, %o2
+
+1: EX_LD(LOAD(ldub, %o1, %o5))
+ subcc %g1, 1, %g1
+ EX_ST(STORE(stb, %o5, %o1 + %o3))
+ bgu,pt %icc, 1b
+ add %o1, 1, %o1
+
+2: add %o1, %o3, %o0
+ andcc %o1, 0x7, %g1
+ bne,pt %icc, 8f
+ sll %g1, 3, %g1
+
+ cmp %o2, 16
+ bgeu,pt %icc, 72b
+ nop
+ ba,a,pt %xcc, 73b
+
+8: mov 64, %o3
+ andn %o1, 0x7, %o1
+ EX_LD(LOAD(ldx, %o1, %g2))
+ sub %o3, %g1, %o3
+ andn %o2, 0x7, %o4
+ sllx %g2, %g1, %g2
+1: EX_LD(LOAD(ldx, %o1 + 0x8, %g3))
+ subcc %o4, 0x8, %o4
+ add %o1, 0x8, %o1
+ srlx %g3, %o3, %o5
+ or %o5, %g2, %o5
+ EX_ST(STORE(stx, %o5, %o0))
+ add %o0, 0x8, %o0
+ bgu,pt %icc, 1b
+ sllx %g3, %g1, %g2
+
+ srl %g1, 3, %g1
+ andcc %o2, 0x7, %o2
+ be,pn %icc, 85f
+ add %o1, %g1, %o1
+ ba,pt %xcc, 90f
+ sub %o0, %o1, %o3
+
+ .align 64
+80: /* 0 < len <= 16 */
+ andcc %o3, 0x3, %g0
+ bne,pn %XCC, 90f
+ sub %o0, %o1, %o3
+
+1: EX_LD(LOAD(lduw, %o1, %g1))
+ subcc %o2, 4, %o2
+ EX_ST(STORE(stw, %g1, %o1 + %o3))
+ bgu,pt %XCC, 1b
+ add %o1, 4, %o1
+
+85: retl
+ mov EX_RETVAL(%g5), %o0
+
+ .align 32
+90: EX_LD(LOAD(ldub, %o1, %g1))
+ subcc %o2, 1, %o2
+ EX_ST(STORE(stb, %g1, %o1 + %o3))
+ bgu,pt %XCC, 90b
+ add %o1, 1, %o1
+ retl
+ mov EX_RETVAL(%g5), %o0
+
+ .size FUNC_NAME, .-FUNC_NAME
--- /dev/null
+/* U3patch.S: Patch Ultra-I routines with Ultra-III variant.
+ *
+ * Copyright (C) 2004 David S. Miller <davem@redhat.com>
+ */
+
+#define BRANCH_ALWAYS 0x10680000
+#define NOP 0x01000000
+#define ULTRA3_DO_PATCH(OLD, NEW) \
+ sethi %hi(NEW), %g1; \
+ or %g1, %lo(NEW), %g1; \
+ sethi %hi(OLD), %g2; \
+ or %g2, %lo(OLD), %g2; \
+ sub %g1, %g2, %g1; \
+ sethi %hi(BRANCH_ALWAYS), %g3; \
+ srl %g1, 2, %g1; \
+ or %g3, %lo(BRANCH_ALWAYS), %g3; \
+ or %g3, %g1, %g3; \
+ stw %g3, [%g2]; \
+ sethi %hi(NOP), %g3; \
+ or %g3, %lo(NOP), %g3; \
+ stw %g3, [%g2 + 0x4]; \
+ flush %g2;
+
+ .globl cheetah_patch_copyops
+ .type cheetah_patch_copyops,#function
+cheetah_patch_copyops:
+ ULTRA3_DO_PATCH(memcpy, U3memcpy)
+ ULTRA3_DO_PATCH(___copy_from_user, U3copy_from_user)
+ ULTRA3_DO_PATCH(___copy_to_user, U3copy_to_user)
+ retl
+ nop
+ .size cheetah_patch_copyops,.-cheetah_patch_copyops
--- /dev/null
+/* copy_in_user.S: Copy from userspace to userspace.
+ *
+ * Copyright (C) 1999, 2000, 2004 David S. Miller (davem@redhat.com)
+ */
+
+#include <asm/asi.h>
+
+#define XCC xcc
+
+#define EX(x,y) \
+98: x,y; \
+ .section .fixup; \
+ .align 4; \
+99: retl; \
+ mov 1, %o0; \
+ .section __ex_table; \
+ .align 4; \
+ .word 98b, 99b; \
+ .text; \
+ .align 4;
+
+ .register %g2,#scratch
+ .register %g3,#scratch
+
+ .text
+ .align 32
+
+ /* Don't try to get too fancy here, just nice and
+ * simple. This is predominantly used for well aligned
+ * small copies in the compat layer. It is also used
+ * to copy register windows around during thread cloning.
+ */
+
+ .globl ___copy_in_user
+ .type ___copy_in_user,#function
+___copy_in_user: /* %o0=dst, %o1=src, %o2=len */
+ /* Writing to %asi is _expensive_ so we hardcode it.
+ * Reading %asi to check for KERNEL_DS is comparatively
+ * cheap.
+ */
+ rd %asi, %g1
+ cmp %g1, ASI_AIUS
+ bne,pn %icc, memcpy_user_stub
+ nop
+
+ cmp %o2, 0
+ be,pn %XCC, 85f
+ or %o0, %o1, %o3
+ cmp %o2, 16
+ bleu,a,pn %XCC, 80f
+ or %o3, %o2, %o3
+
+ /* 16 < len <= 64 */
+ andcc %o3, 0x7, %g0
+ bne,pn %XCC, 90f
+ sub %o0, %o1, %o3
+
+ andn %o2, 0x7, %o4
+ and %o2, 0x7, %o2
+1: subcc %o4, 0x8, %o4
+ EX(ldxa [%o1] %asi, %o5)
+ EX(stxa %o5, [%o1 + %o3] ASI_AIUS)
+ bgu,pt %XCC, 1b
+ add %o1, 0x8, %o1
+ andcc %o2, 0x4, %g0
+ be,pt %XCC, 1f
+ nop
+ sub %o2, 0x4, %o2
+ EX(lduwa [%o1] %asi, %o5)
+ EX(stwa %o5, [%o1 + %o3] ASI_AIUS)
+ add %o1, 0x4, %o1
+1: cmp %o2, 0
+ be,pt %XCC, 85f
+ nop
+ ba,pt %xcc, 90f
+ nop
+
+80: /* 0 < len <= 16 */
+ andcc %o3, 0x3, %g0
+ bne,pn %XCC, 90f
+ sub %o0, %o1, %o3
+
+82:
+ subcc %o2, 4, %o2
+ EX(lduwa [%o1] %asi, %g1)
+ EX(stwa %g1, [%o1 + %o3] ASI_AIUS)
+ bgu,pt %XCC, 82b
+ add %o1, 4, %o1
+
+85: retl
+ clr %o0
+
+ .align 32
+90:
+ subcc %o2, 1, %o2
+ EX(lduba [%o1] %asi, %g1)
+ EX(stba %g1, [%o1 + %o3] ASI_AIUS)
+ bgu,pt %XCC, 90b
+ add %o1, 1, %o1
+ retl
+ clr %o0
+
+ .size ___copy_in_user, .-___copy_in_user
+
+ /* Act like copy_{to,in}_user(), ie. return zero instead
+ * of original destination pointer. This is invoked when
+ * copy_{to,in}_user() finds that %asi is kernel space.
+ */
+ .globl memcpy_user_stub
+ .type memcpy_user_stub,#function
+memcpy_user_stub:
+ save %sp, -192, %sp
+ mov %i0, %o0
+ mov %i1, %o1
+ call memcpy
+ mov %i2, %o2
+ ret
+ restore %g0, %g0, %o0
+ .size memcpy_user_stub, .-memcpy_user_stub
--- /dev/null
+/* delay.c: Delay loops for sparc64
+ *
+ * Copyright (C) 2004 David S. Miller <davem@redhat.com>
+ *
+ * Based heavily upon x86 variant which is:
+ * Copyright (C) 1993 Linus Torvalds
+ * Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+ */
+
+#include <linux/delay.h>
+
+void __delay(unsigned long loops)
+{
+ __asm__ __volatile__(
+" b,pt %%xcc, 1f\n"
+" cmp %0, 0\n"
+" .align 32\n"
+"1:\n"
+" bne,pt %%xcc, 1b\n"
+" subcc %0, 1, %0\n"
+ : "=&r" (loops)
+ : "0" (loops)
+ : "cc");
+}
+
+/* We used to multiply by HZ after shifting down by 32 bits
+ * but that runs into problems for higher values of HZ and
+ * slow cpus.
+ */
+void __const_udelay(unsigned long n)
+{
+ n *= 4;
+
+ n *= (cpu_data(smp_processor_id()).udelay_val * (HZ/4));
+ n >>= 32;
+
+ __delay(n + 1);
+}
+
+void __udelay(unsigned long n)
+{
+ __const_udelay(n * 0x10c7UL);
+}
+
+
+void __ndelay(unsigned long n)
+{
+ __const_udelay(n * 0x5UL);
+}
--- /dev/null
+/*
+ * Implement the sparc64 iomap interfaces
+ */
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <asm/io.h>
+
+/* Create a virtual mapping cookie for an IO port range */
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+ return (void __iomem *) (unsigned long) port;
+}
+
+void ioport_unmap(void __iomem *addr)
+{
+ /* Nothing to do */
+}
+EXPORT_SYMBOL(ioport_map);
+EXPORT_SYMBOL(ioport_unmap);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
+{
+ unsigned long start = pci_resource_start(dev, bar);
+ unsigned long len = pci_resource_len(dev, bar);
+ unsigned long flags = pci_resource_flags(dev, bar);
+
+ if (!len || !start)
+ return NULL;
+ if (maxlen && len > maxlen)
+ len = maxlen;
+ if (flags & IORESOURCE_IO)
+ return ioport_map(start, len);
+ if (flags & IORESOURCE_MEM) {
+ if (flags & IORESOURCE_CACHEABLE)
+ return ioremap(start, len);
+ return ioremap_nocache(start, len);
+ }
+ /* What? */
+ return NULL;
+}
+
+void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
+{
+ /* nothing to do */
+}
+EXPORT_SYMBOL(pci_iomap);
+EXPORT_SYMBOL(pci_iounmap);
--- /dev/null
+/* memmove.S: Simple memmove implementation.
+ *
+ * Copyright (C) 1997, 2004 David S. Miller (davem@redhat.com)
+ * Copyright (C) 1996, 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+ .text
+ .align 32
+ .globl memmove
+ .type memmove,#function
+memmove:
+ mov %o0, %g1
+ cmp %o0, %o1
+ blu,pt %xcc, memcpy
+ sub %o0, %o1, %g5
+ add %o1, %o2, %g3
+ cmp %g3, %o0
+ bleu,pt %xcc, memcpy
+ add %o1, %o2, %g5
+ add %o0, %o2, %o5
+
+ sub %g5, 1, %o1
+ sub %o5, 1, %o0
+1: ldub [%o1], %g5
+ subcc %o2, 1, %o2
+ sub %o1, 1, %o1
+ stb %g5, [%o0]
+ bne,pt %icc, 1b
+ sub %o0, 1, %o0
+
+ retl
+ mov %g1, %o0
+ .size memmove, .-memmove
--- /dev/null
+/* user_fixup.c: Fix up user copy faults.
+ *
+ * Copyright (C) 2004 David S. Miller <davem@redhat.com>
+ */
+
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <asm/uaccess.h>
+
+/* Calculating the exact fault address when using
+ * block loads and stores can be very complicated.
+ * Instead of trying to be clever and handling all
+ * of the cases, just fix things up simply here.
+ */
+
+unsigned long copy_from_user_fixup(void *to, const void __user *from, unsigned long size)
+{
+ char *dst = to;
+ const char __user *src = from;
+
+ while (size--) {
+ if (__get_user(*dst, src))
+ break;
+ dst++;
+ src++;
+ }
+
+ if (size)
+ memset(dst, 0, size);
+
+ return size;
+}
+
+unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned long size)
+{
+ char __user *dst = to;
+ const char *src = from;
+
+ while (size--) {
+ if (__put_user(*src, dst))
+ break;
+ dst++;
+ src++;
+ }
+
+ return size;
+}
+
+unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned long size)
+{
+ char __user *dst = to;
+ char __user *src = from;
+
+ while (size--) {
+ char tmp;
+
+ if (__get_user(tmp, src))
+ break;
+ if (__put_user(tmp, dst))
+ break;
+ dst++;
+ src++;
+ }
+
+ return size;
+}
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config FRAME_POINTER
+ bool
+ default y if DEBUG_INFO
+
+config PT_PROXY
+ bool "Enable ptrace proxy"
+ depends on XTERM_CHAN && DEBUG_INFO
+ help
+ This option enables a debugging interface which allows gdb to debug
+ the kernel without needing to actually attach to kernel threads.
+ If you want to do kernel debugging, say Y here; otherwise say N.
+
+config GPROF
+ bool "Enable gprof support"
+ depends on DEBUG_INFO
+ help
+ This allows profiling of a User-Mode Linux kernel with the gprof
+ utility.
+
+ See <http://user-mode-linux.sourceforge.net/gprof.html> for more
+ details.
+
+ If you're involved in UML kernel development and want to use gprof,
+ say Y. If you're unsure, say N.
+
+config GCOV
+ bool "Enable gcov support"
+ depends on DEBUG_INFO
+ help
+ This option allows developers to retrieve coverage data from a UML
+ session.
+
+ See <http://user-mode-linux.sourceforge.net/gprof.html> for more
+ details.
+
+ If you're involved in UML kernel development and want to use gcov,
+ say Y. If you're unsure, say N.
+
+endmenu
--- /dev/null
+#ifndef __COW_SYS_H__
+#define __COW_SYS_H__
+
+#include "kern_util.h"
+#include "user_util.h"
+#include "os.h"
+#include "user.h"
+
+static inline void *cow_malloc(int size)
+{
+ return(um_kmalloc(size));
+}
+
+static inline void cow_free(void *ptr)
+{
+ kfree(ptr);
+}
+
+#define cow_printf printk
+
+static inline char *cow_strdup(char *str)
+{
+ return(uml_strdup(str));
+}
+
+static inline int cow_seek_file(int fd, __u64 offset)
+{
+ return(os_seek_file(fd, offset));
+}
+
+static inline int cow_file_size(char *file, __u64 *size_out)
+{
+ return(os_file_size(file, size_out));
+}
+
+static inline int cow_write_file(int fd, char *buf, int size)
+{
+ return(os_write_file(fd, buf, size));
+}
+
+#endif
+
+/*
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
--- /dev/null
+#include <asm-generic/vmlinux.lds.h>
+
+OUTPUT_FORMAT(ELF_FORMAT)
+OUTPUT_ARCH(ELF_ARCH)
+ENTRY(_start)
+jiffies = jiffies_64;
+
+SECTIONS
+{
+ . = START + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ __binary_start = .;
+ . = ALIGN(4096); /* Init code and data */
+ _stext = .;
+ __init_begin = .;
+ .init.text : {
+ _sinittext = .;
+ *(.init.text)
+ _einittext = .;
+ }
+
+ . = ALIGN(4096);
+
+ /* Read-only sections, merged into text segment: */
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rel.init : { *(.rel.init) }
+ .rela.init : { *(.rela.init) }
+ .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+ .rel.fini : { *(.rel.fini) }
+ .rela.fini : { *(.rela.fini) }
+ .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+ .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+ .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+ .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+ .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+ .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+ .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+ .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+ .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : {
+ KEEP (*(.init))
+ } =0x90909090
+ .plt : { *(.plt) }
+ .text : {
+ *(.text)
+ SCHED_TEXT
+ *(.stub .text.* .gnu.linkonce.t.*)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } =0x90909090
+ .fini : {
+ KEEP (*(.fini))
+ } =0x90909090
+
+ .kstrtab : { *(.kstrtab) }
+
+ #include "asm/common.lds.S"
+
+ init.data : { *(.init.data) }
+
+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ . = ALIGN(32 / 8);
+ .preinit_array : { *(.preinit_array) }
+ .init_array : { *(.init_array) }
+ .fini_array : { *(.fini_array) }
+ .data : {
+ . = ALIGN(KERNEL_STACK_SIZE); /* init_task */
+ *(.data.init_task)
+ *(.data .data.* .gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ }
+ .data1 : { *(.data1) }
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+ .eh_frame : { KEEP (*(.eh_frame)) }
+ .gcc_except_table : { *(.gcc_except_table) }
+ .dynamic : { *(.dynamic) }
+ .ctors : {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ }
+ .dtors : {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ }
+ .jcr : { KEEP (*(.jcr)) }
+ .got : { *(.got.plt) *(.got) }
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss : {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(32 / 8);
+ . = ALIGN(32 / 8);
+ }
+ _end = .;
+ PROVIDE (end = .);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
--- /dev/null
+/*
+ * Copyright (C) 2000, 2001 Jeff Dike (jdike@karaya.com)
+ * Licensed under the GPL
+ */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <signal.h>
+#include <errno.h>
+#include <sys/resource.h>
+#include <sys/mman.h>
+#include <sys/user.h>
+#include <asm/page.h>
+#include "user_util.h"
+#include "kern_util.h"
+#include "mem_user.h"
+#include "signal_user.h"
+#include "user.h"
+#include "init.h"
+#include "mode.h"
+#include "choose-mode.h"
+#include "uml-config.h"
+
+/* Set in set_stklim, which is called from main and __wrap_malloc.
+ * __wrap_malloc only calls it if main hasn't started.
+ */
+unsigned long stacksizelim;
+
+/* Set in main */
+char *linux_prog;
+
+#define PGD_BOUND (4 * 1024 * 1024)
+#define STACKSIZE (8 * 1024 * 1024)
+#define THREAD_NAME_LEN (256)
+
+static void set_stklim(void)
+{
+ struct rlimit lim;
+
+ if(getrlimit(RLIMIT_STACK, &lim) < 0){
+ perror("getrlimit");
+ exit(1);
+ }
+ if((lim.rlim_cur == RLIM_INFINITY) || (lim.rlim_cur > STACKSIZE)){
+ lim.rlim_cur = STACKSIZE;
+ if(setrlimit(RLIMIT_STACK, &lim) < 0){
+ perror("setrlimit");
+ exit(1);
+ }
+ }
+ stacksizelim = (lim.rlim_cur + PGD_BOUND - 1) & ~(PGD_BOUND - 1);
+}
+
+static __init void do_uml_initcalls(void)
+{
+ initcall_t *call;
+
+ call = &__uml_initcall_start;
+ while (call < &__uml_initcall_end){;
+ (*call)();
+ call++;
+ }
+}
+
+static void last_ditch_exit(int sig)
+{
+ CHOOSE_MODE(kmalloc_ok = 0, (void) 0);
+ signal(SIGINT, SIG_DFL);
+ signal(SIGTERM, SIG_DFL);
+ signal(SIGHUP, SIG_DFL);
+ uml_cleanup();
+ exit(1);
+}
+
+extern int uml_exitcode;
+
+int main(int argc, char **argv, char **envp)
+{
+ char **new_argv;
+ sigset_t mask;
+ int ret, i;
+
+ /* Enable all signals except SIGIO - in some environments, we can
+ * enter with some signals blocked
+ */
+
+ sigemptyset(&mask);
+ sigaddset(&mask, SIGIO);
+ if(sigprocmask(SIG_SETMASK, &mask, NULL) < 0){
+ perror("sigprocmask");
+ exit(1);
+ }
+
+#ifdef UML_CONFIG_MODE_TT
+ /* Allocate memory for thread command lines */
+ if(argc < 2 || strlen(argv[1]) < THREAD_NAME_LEN - 1){
+
+ char padding[THREAD_NAME_LEN] = {
+ [ 0 ... THREAD_NAME_LEN - 2] = ' ', '\0'
+ };
+
+ new_argv = malloc((argc + 2) * sizeof(char*));
+ if(!new_argv) {
+ perror("Allocating extended argv");
+ exit(1);
+ }
+
+ new_argv[0] = argv[0];
+ new_argv[1] = padding;
+
+ for(i = 2; i <= argc; i++)
+ new_argv[i] = argv[i - 1];
+ new_argv[argc + 1] = NULL;
+
+ execvp(new_argv[0], new_argv);
+ perror("execing with extended args");
+ exit(1);
+ }
+#endif
+
+ linux_prog = argv[0];
+
+ set_stklim();
+
+ new_argv = malloc((argc + 1) * sizeof(char *));
+ if(new_argv == NULL){
+ perror("Mallocing argv");
+ exit(1);
+ }
+ for(i=0;i<argc;i++){
+ new_argv[i] = strdup(argv[i]);
+ if(new_argv[i] == NULL){
+ perror("Mallocing an arg");
+ exit(1);
+ }
+ }
+ new_argv[argc] = NULL;
+
+ set_handler(SIGINT, last_ditch_exit, SA_ONESHOT | SA_NODEFER, -1);
+ set_handler(SIGTERM, last_ditch_exit, SA_ONESHOT | SA_NODEFER, -1);
+ set_handler(SIGHUP, last_ditch_exit, SA_ONESHOT | SA_NODEFER, -1);
+
+ do_uml_initcalls();
+ ret = linux_main(argc, argv);
+
+ /* Reboot */
+ if(ret){
+ int err;
+
+ printf("\n");
+
+ /* Let any pending signals fire, then disable them. This
+ * ensures that they won't be delivered after the exec, when
+ * they are definitely not expected.
+ */
+ unblock_signals();
+ disable_timer();
+ err = deactivate_all_fds();
+ if(err)
+ printf("deactivate_all_fds failed, errno = %d\n",
+ -err);
+
+ execvp(new_argv[0], new_argv);
+ perror("Failed to exec kernel");
+ ret = 1;
+ }
+ printf("\n");
+ return(uml_exitcode);
+}
+
+#define CAN_KMALLOC() \
+ (kmalloc_ok && CHOOSE_MODE((getpid() != tracing_pid), 1))
+
+extern void *__real_malloc(int);
+
+void *__wrap_malloc(int size)
+{
+ void *ret;
+
+ if(!CAN_KMALLOC())
+ return(__real_malloc(size));
+ else if(size <= PAGE_SIZE) /* finding contiguos pages can be hard*/
+ ret = um_kmalloc(size);
+ else ret = um_vmalloc(size);
+
+ /* glibc people insist that if malloc fails, errno should be
+ * set by malloc as well. So we do.
+ */
+ if(ret == NULL)
+ errno = ENOMEM;
+
+ return(ret);
+}
+
+void *__wrap_calloc(int n, int size)
+{
+ void *ptr = __wrap_malloc(n * size);
+
+ if(ptr == NULL) return(NULL);
+ memset(ptr, 0, n * size);
+ return(ptr);
+}
+
+extern void __real_free(void *);
+
+extern unsigned long high_physmem;
+
+void __wrap_free(void *ptr)
+{
+ unsigned long addr = (unsigned long) ptr;
+
+ /* We need to know how the allocation happened, so it can be correctly
+ * freed. This is done by seeing what region of memory the pointer is
+ * in -
+ * physical memory - kmalloc/kfree
+ * kernel virtual memory - vmalloc/vfree
+ * anywhere else - malloc/free
+ * If kmalloc is not yet possible, then the kernel memory regions
+ * may not be set up yet, and the variables not initialized. So,
+ * free is called.
+ *
+ * CAN_KMALLOC is checked because it would be bad to free a buffer
+ * with kmalloc/vmalloc after they have been turned off during
+ * shutdown.
+ */
+
+ if((addr >= uml_physmem) && (addr < high_physmem)){
+ if(CAN_KMALLOC())
+ kfree(ptr);
+ }
+ else if((addr >= start_vm) && (addr < end_vm)){
+ if(CAN_KMALLOC())
+ vfree(ptr);
+ }
+ else __real_free(ptr);
+}
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only. This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
--- /dev/null
+#include <asm-generic/vmlinux.lds.h>
+
+OUTPUT_FORMAT(ELF_FORMAT)
+OUTPUT_ARCH(ELF_ARCH)
+ENTRY(_start)
+jiffies = jiffies_64;
+
+SECTIONS
+{
+ . = START + SIZEOF_HEADERS;
+
+ __binary_start = .;
+#ifdef MODE_TT
+ .thread_private : {
+ __start_thread_private = .;
+ errno = .;
+ . += 4;
+ arch/um/kernel/tt/unmap_fin.o (.data)
+ __end_thread_private = .;
+ }
+ . = ALIGN(4096);
+ .remap : { arch/um/kernel/tt/unmap_fin.o (.text) }
+#endif
+
+ . = ALIGN(4096); /* Init code and data */
+ _stext = .;
+ __init_begin = .;
+ .init.text : {
+ _sinittext = .;
+ *(.init.text)
+ _einittext = .;
+ }
+ . = ALIGN(4096);
+ .text :
+ {
+ *(.text)
+ SCHED_TEXT
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ }
+
+ #include "asm/common.lds.S"
+
+ init.data : { *(init.data) }
+ .data :
+ {
+ . = ALIGN(KERNEL_STACK_SIZE); /* init_task */
+ *(.data.init_task)
+ *(.data)
+ *(.gnu.linkonce.d*)
+ CONSTRUCTORS
+ }
+ .data1 : { *(.data1) }
+ .ctors :
+ {
+ *(.ctors)
+ }
+ .dtors :
+ {
+ *(.dtors)
+ }
+
+ .got : { *(.got.plt) *(.got) }
+ .dynamic : { *(.dynamic) }
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata : { *(.sdata) }
+ _edata = .;
+ PROVIDE (edata = .);
+ . = ALIGN(0x1000);
+ .sbss :
+ {
+ __bss_start = .;
+ PROVIDE(_bss_start = .);
+ *(.sbss)
+ *(.scommon)
+ }
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+}
--- /dev/null
+#include <stdlib.h>
+#include <sys/time.h>
+
+unsigned long long os_usecs(void)
+{
+ struct timeval tv;
+
+ gettimeofday(&tv, NULL);
+ return((unsigned long long) tv.tv_sec * 1000000 + tv.tv_usec);
+}
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only. This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-file-style: "linux"
+ * End:
+ */
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config NO_KERNEL_MSG
+ bool "Suppress Kernel BUG Messages"
+ help
+ Do not output any debug BUG messages within the kernel.
+
+endmenu
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+# !SMP for now because the context switch early causes GPF in segment reloading
+# and the GS base checking does the wrong thing then, causing a hang.
+config CHECKING
+ bool "Additional run-time checks"
+ depends on DEBUG_KERNEL && !SMP
+ help
+ Enables some internal consistency checks for kernel debugging.
+ You should normally say N.
+
+config INIT_DEBUG
+ bool "Debug __init statements"
+ depends on DEBUG_KERNEL
+ help
+ Fill __init and __initdata at the end of boot. This helps debugging
+ illegal uses of __init and __initdata after initialization.
+
+config SCHEDSTATS
+ bool "Collect scheduler statistics"
+ depends on DEBUG_KERNEL && PROC_FS
+ help
+ If you say Y here, additional code will be inserted into the
+ scheduler and related routines to collect statistics about
+ scheduler behavior and provide them in /proc/schedstat. These
+ stats may be useful for both tuning and debugging the scheduler
+ If you aren't debugging the scheduler or trying to tune a specific
+ application, you can say N to avoid the very slight overhead
+ this adds.
+
+config IOMMU_DEBUG
+ depends on GART_IOMMU && DEBUG_KERNEL
+ bool "Enable IOMMU debugging"
+ help
+ Force the IOMMU to on even when you have less than 4GB of
+ memory and add debugging code. On overflow always panic. And
+ allow to enable IOMMU leak tracing. Can be disabled at boot
+ time with iommu=noforce. This will also enable scatter gather
+ list merging. Currently not recommended for production
+ code. When you use it make sure you have a big enough
+ IOMMU/AGP aperture. Most of the options enabled by this can
+ be set more finegrained using the iommu= command line
+ options. See Documentation/x86_64/boot-options.txt for more
+ details.
+
+config IOMMU_LEAK
+ bool "IOMMU leak tracing"
+ depends on DEBUG_KERNEL
+ depends on IOMMU_DEBUG
+ help
+ Add a simple leak tracer to the IOMMU code. This is useful when you
+ are debugging a buggy device driver that leaks IOMMU mappings.
+
+#config X86_REMOTE_DEBUG
+# bool "kgdb debugging stub"
+
+endmenu
--- /dev/null
+#include <linux/module.h>
+#include <asm/bitops.h>
+
+#undef find_first_zero_bit
+#undef find_next_zero_bit
+#undef find_first_bit
+#undef find_next_bit
+
+/**
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+inline long find_first_zero_bit(const unsigned long * addr, unsigned long size)
+{
+ long d0, d1, d2;
+ long res;
+
+ if (!size)
+ return 0;
+ asm volatile(
+ " repe; scasq\n"
+ " je 1f\n"
+ " xorq -8(%%rdi),%%rax\n"
+ " subq $8,%%rdi\n"
+ " bsfq %%rax,%%rdx\n"
+ "1: subq %[addr],%%rdi\n"
+ " shlq $3,%%rdi\n"
+ " addq %%rdi,%%rdx"
+ :"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2)
+ :"0" (0ULL), "1" ((size + 63) >> 6), "2" (addr), "3" (-1ULL),
+ [addr] "r" (addr) : "memory");
+ return res;
+}
+
+/**
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+long find_next_zero_bit (const unsigned long * addr, long size, long offset)
+{
+ unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
+ unsigned long set = 0;
+ unsigned long res, bit = offset&63;
+
+ if (bit) {
+ /*
+ * Look for zero in first word
+ */
+ asm("bsfq %1,%0\n\t"
+ "cmoveq %2,%0"
+ : "=r" (set)
+ : "r" (~(*p >> bit)), "r"(64L));
+ if (set < (64 - bit))
+ return set + offset;
+ set = 64 - bit;
+ p++;
+ }
+ /*
+ * No zero yet, search remaining full words for a zero
+ */
+ res = find_first_zero_bit ((const unsigned long *)p,
+ size - 64 * (p - (unsigned long *) addr));
+ return (offset + set + res);
+}
+
+static inline long
+__find_first_bit(const unsigned long * addr, unsigned long size)
+{
+ long d0, d1;
+ long res;
+
+ asm volatile(
+ " repe; scasq\n"
+ " jz 1f\n"
+ " subq $8,%%rdi\n"
+ " bsfq (%%rdi),%%rax\n"
+ "1: subq %[addr],%%rdi\n"
+ " shlq $3,%%rdi\n"
+ " addq %%rdi,%%rax"
+ :"=a" (res), "=&c" (d0), "=&D" (d1)
+ :"0" (0ULL),
+ "1" ((size + 63) >> 6), "2" (addr),
+ [addr] "r" (addr) : "memory");
+ return res;
+}
+
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+long find_first_bit(const unsigned long * addr, unsigned long size)
+{
+ return __find_first_bit(addr,size);
+}
+
+/**
+ * find_next_bit - find the first set bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+long find_next_bit(const unsigned long * addr, long size, long offset)
+{
+ const unsigned long * p = addr + (offset >> 6);
+ unsigned long set = 0, bit = offset & 63, res;
+
+ if (bit) {
+ /*
+ * Look for nonzero in the first 64 bits:
+ */
+ asm("bsfq %1,%0\n\t"
+ "cmoveq %2,%0\n\t"
+ : "=r" (set)
+ : "r" (*p >> bit), "r" (64L));
+ if (set < (64 - bit))
+ return set + offset;
+ set = 64 - bit;
+ p++;
+ }
+ /*
+ * No set bit yet, search remaining full words for a bit
+ */
+ res = __find_first_bit (p, size - 64 * (p - addr));
+ return (offset + set + res);
+}
+
+EXPORT_SYMBOL(find_next_bit);
+EXPORT_SYMBOL(find_first_bit);
+EXPORT_SYMBOL(find_first_zero_bit);
+EXPORT_SYMBOL(find_next_zero_bit);
--- /dev/null
+#
+# Makefile for X86_64 specific PCI routines
+#
+# Reuse the i386 PCI subsystem
+#
+CFLAGS += -I arch/i386/pci
+
+obj-y := i386.o
+obj-$(CONFIG_PCI_DIRECT)+= direct.o
+obj-y += fixup.o
+obj-$(CONFIG_ACPI_PCI) += acpi.o
+obj-y += legacy.o irq.o common.o
+# mmconfig has a 64bit special
+obj-$(CONFIG_PCI_MMCONFIG) += mmconfig.o
+
+direct-y += ../../i386/pci/direct.o
+acpi-y += ../../i386/pci/acpi.o
+legacy-y += ../../i386/pci/legacy.o
+irq-y += ../../i386/pci/irq.o
+common-y += ../../i386/pci/common.o
+fixup-y += ../../i386/pci/fixup.o
+i386-y += ../../i386/pci/i386.o
--- /dev/null
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/mpspec.h>
+#include <linux/cpumask.h>
+
+/*
+ * This discovers the pcibus <-> node mapping on AMD K8.
+ *
+ * RED-PEN need to call this again on PCI hotplug
+ * RED-PEN empty cpus get reported wrong
+ */
+
+#define NODE_ID_REGISTER 0x60
+#define NODE_ID(dword) (dword & 0x07)
+#define LDT_BUS_NUMBER_REGISTER_0 0x94
+#define LDT_BUS_NUMBER_REGISTER_1 0xB4
+#define LDT_BUS_NUMBER_REGISTER_2 0xD4
+#define NR_LDT_BUS_NUMBER_REGISTERS 3
+#define SECONDARY_LDT_BUS_NUMBER(dword) ((dword >> 8) & 0xFF)
+#define SUBORDINATE_LDT_BUS_NUMBER(dword) ((dword >> 16) & 0xFF)
+#define PCI_DEVICE_ID_K8HTCONFIG 0x1100
+
+/**
+ * fill_mp_bus_to_cpumask()
+ * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
+ * Registers found in the K8 northbridge
+ */
+__init static int
+fill_mp_bus_to_cpumask(void)
+{
+ struct pci_dev *nb_dev = NULL;
+ int i, j;
+ u32 ldtbus, nid;
+ static int lbnr[3] = {
+ LDT_BUS_NUMBER_REGISTER_0,
+ LDT_BUS_NUMBER_REGISTER_1,
+ LDT_BUS_NUMBER_REGISTER_2
+ };
+
+ while ((nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_K8HTCONFIG, nb_dev))) {
+ pci_read_config_dword(nb_dev, NODE_ID_REGISTER, &nid);
+
+ for (i = 0; i < NR_LDT_BUS_NUMBER_REGISTERS; i++) {
+ pci_read_config_dword(nb_dev, lbnr[i], &ldtbus);
+ /*
+ * if there are no busses hanging off of the current
+ * ldt link then both the secondary and subordinate
+ * bus number fields are set to 0.
+ */
+ if (!(SECONDARY_LDT_BUS_NUMBER(ldtbus) == 0
+ && SUBORDINATE_LDT_BUS_NUMBER(ldtbus) == 0)) {
+ for (j = SECONDARY_LDT_BUS_NUMBER(ldtbus);
+ j <= SUBORDINATE_LDT_BUS_NUMBER(ldtbus);
+ j++)
+ pci_bus_to_cpumask[j] =
+ node_to_cpumask(NODE_ID(nid));
+ }
+ }
+ }
+
+ /* quick sanity check */
+ for (i = 0; i < 256; i++) {
+ if (cpus_empty(pci_bus_to_cpumask[i])) {
+ printk(KERN_ERR
+ "k8-bus.c: bus %i has empty cpu mask\n", i);
+ pci_bus_to_cpumask[i] = CPU_MASK_ALL;
+ }
+ }
+
+ return 0;
+}
+
+fs_initcall(fill_mp_bus_to_cpumask);
--- /dev/null
+/*
+ * Cryptographic API.
+ *
+ * Whirlpool hashing Algorithm
+ *
+ * The Whirlpool algorithm was developed by Paulo S. L. M. Barreto and
+ * Vincent Rijmen. It has been selected as one of cryptographic
+ * primitives by the NESSIE project http://www.cryptonessie.org/
+ *
+ * The original authors have disclaimed all copyright interest in this
+ * code and thus put it in the public domain. The subsequent authors
+ * have put this under the GNU General Public License.
+ *
+ * By Aaron Grothe ajgrothe@yahoo.com, August 23, 2004
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <asm/scatterlist.h>
+#include <linux/crypto.h>
+
+#define WP512_DIGEST_SIZE 64
+#define WP384_DIGEST_SIZE 48
+#define WP256_DIGEST_SIZE 32
+
+#define WP512_BLOCK_SIZE 64
+#define WP512_LENGTHBYTES 32
+
+#define WHIRLPOOL_ROUNDS 10
+
+struct wp512_ctx {
+ u8 bitLength[WP512_LENGTHBYTES];
+ u8 buffer[WP512_BLOCK_SIZE];
+ int bufferBits;
+ int bufferPos;
+ u64 hash[WP512_DIGEST_SIZE/8];
+};
+
+/*
+ * Though Whirlpool is endianness-neutral, the encryption tables are listed
+ * in BIG-ENDIAN format, which is adopted throughout this implementation
+ * (but little-endian notation would be equally suitable if consistently
+ * employed).
+ */
+
+static const u64 C0[256] = {
+ 0x18186018c07830d8ULL, 0x23238c2305af4626ULL, 0xc6c63fc67ef991b8ULL,
+ 0xe8e887e8136fcdfbULL, 0x878726874ca113cbULL, 0xb8b8dab8a9626d11ULL,
+ 0x0101040108050209ULL, 0x4f4f214f426e9e0dULL, 0x3636d836adee6c9bULL,
+ 0xa6a6a2a6590451ffULL, 0xd2d26fd2debdb90cULL, 0xf5f5f3f5fb06f70eULL,
+ 0x7979f979ef80f296ULL, 0x6f6fa16f5fcede30ULL, 0x91917e91fcef3f6dULL,
+ 0x52525552aa07a4f8ULL, 0x60609d6027fdc047ULL, 0xbcbccabc89766535ULL,
+ 0x9b9b569baccd2b37ULL, 0x8e8e028e048c018aULL, 0xa3a3b6a371155bd2ULL,
+ 0x0c0c300c603c186cULL, 0x7b7bf17bff8af684ULL, 0x3535d435b5e16a80ULL,
+ 0x1d1d741de8693af5ULL, 0xe0e0a7e05347ddb3ULL, 0xd7d77bd7f6acb321ULL,
+ 0xc2c22fc25eed999cULL, 0x2e2eb82e6d965c43ULL, 0x4b4b314b627a9629ULL,
+ 0xfefedffea321e15dULL, 0x575741578216aed5ULL, 0x15155415a8412abdULL,
+ 0x7777c1779fb6eee8ULL, 0x3737dc37a5eb6e92ULL, 0xe5e5b3e57b56d79eULL,
+ 0x9f9f469f8cd92313ULL, 0xf0f0e7f0d317fd23ULL, 0x4a4a354a6a7f9420ULL,
+ 0xdada4fda9e95a944ULL, 0x58587d58fa25b0a2ULL, 0xc9c903c906ca8fcfULL,
+ 0x2929a429558d527cULL, 0x0a0a280a5022145aULL, 0xb1b1feb1e14f7f50ULL,
+ 0xa0a0baa0691a5dc9ULL, 0x6b6bb16b7fdad614ULL, 0x85852e855cab17d9ULL,
+ 0xbdbdcebd8173673cULL, 0x5d5d695dd234ba8fULL, 0x1010401080502090ULL,
+ 0xf4f4f7f4f303f507ULL, 0xcbcb0bcb16c08bddULL, 0x3e3ef83eedc67cd3ULL,
+ 0x0505140528110a2dULL, 0x676781671fe6ce78ULL, 0xe4e4b7e47353d597ULL,
+ 0x27279c2725bb4e02ULL, 0x4141194132588273ULL, 0x8b8b168b2c9d0ba7ULL,
+ 0xa7a7a6a7510153f6ULL, 0x7d7de97dcf94fab2ULL, 0x95956e95dcfb3749ULL,
+ 0xd8d847d88e9fad56ULL, 0xfbfbcbfb8b30eb70ULL, 0xeeee9fee2371c1cdULL,
+ 0x7c7ced7cc791f8bbULL, 0x6666856617e3cc71ULL, 0xdddd53dda68ea77bULL,
+ 0x17175c17b84b2eafULL, 0x4747014702468e45ULL, 0x9e9e429e84dc211aULL,
+ 0xcaca0fca1ec589d4ULL, 0x2d2db42d75995a58ULL, 0xbfbfc6bf9179632eULL,
+ 0x07071c07381b0e3fULL, 0xadad8ead012347acULL, 0x5a5a755aea2fb4b0ULL,
+ 0x838336836cb51befULL, 0x3333cc3385ff66b6ULL, 0x636391633ff2c65cULL,
+ 0x02020802100a0412ULL, 0xaaaa92aa39384993ULL, 0x7171d971afa8e2deULL,
+ 0xc8c807c80ecf8dc6ULL, 0x19196419c87d32d1ULL, 0x494939497270923bULL,
+ 0xd9d943d9869aaf5fULL, 0xf2f2eff2c31df931ULL, 0xe3e3abe34b48dba8ULL,
+ 0x5b5b715be22ab6b9ULL, 0x88881a8834920dbcULL, 0x9a9a529aa4c8293eULL,
+ 0x262698262dbe4c0bULL, 0x3232c8328dfa64bfULL, 0xb0b0fab0e94a7d59ULL,
+ 0xe9e983e91b6acff2ULL, 0x0f0f3c0f78331e77ULL, 0xd5d573d5e6a6b733ULL,
+ 0x80803a8074ba1df4ULL, 0xbebec2be997c6127ULL, 0xcdcd13cd26de87ebULL,
+ 0x3434d034bde46889ULL, 0x48483d487a759032ULL, 0xffffdbffab24e354ULL,
+ 0x7a7af57af78ff48dULL, 0x90907a90f4ea3d64ULL, 0x5f5f615fc23ebe9dULL,
+ 0x202080201da0403dULL, 0x6868bd6867d5d00fULL, 0x1a1a681ad07234caULL,
+ 0xaeae82ae192c41b7ULL, 0xb4b4eab4c95e757dULL, 0x54544d549a19a8ceULL,
+ 0x93937693ece53b7fULL, 0x222288220daa442fULL, 0x64648d6407e9c863ULL,
+ 0xf1f1e3f1db12ff2aULL, 0x7373d173bfa2e6ccULL, 0x12124812905a2482ULL,
+ 0x40401d403a5d807aULL, 0x0808200840281048ULL, 0xc3c32bc356e89b95ULL,
+ 0xecec97ec337bc5dfULL, 0xdbdb4bdb9690ab4dULL, 0xa1a1bea1611f5fc0ULL,
+ 0x8d8d0e8d1c830791ULL, 0x3d3df43df5c97ac8ULL, 0x97976697ccf1335bULL,
+ 0x0000000000000000ULL, 0xcfcf1bcf36d483f9ULL, 0x2b2bac2b4587566eULL,
+ 0x7676c57697b3ece1ULL, 0x8282328264b019e6ULL, 0xd6d67fd6fea9b128ULL,
+ 0x1b1b6c1bd87736c3ULL, 0xb5b5eeb5c15b7774ULL, 0xafaf86af112943beULL,
+ 0x6a6ab56a77dfd41dULL, 0x50505d50ba0da0eaULL, 0x45450945124c8a57ULL,
+ 0xf3f3ebf3cb18fb38ULL, 0x3030c0309df060adULL, 0xefef9bef2b74c3c4ULL,
+ 0x3f3ffc3fe5c37edaULL, 0x55554955921caac7ULL, 0xa2a2b2a2791059dbULL,
+ 0xeaea8fea0365c9e9ULL, 0x656589650fecca6aULL, 0xbabad2bab9686903ULL,
+ 0x2f2fbc2f65935e4aULL, 0xc0c027c04ee79d8eULL, 0xdede5fdebe81a160ULL,
+ 0x1c1c701ce06c38fcULL, 0xfdfdd3fdbb2ee746ULL, 0x4d4d294d52649a1fULL,
+ 0x92927292e4e03976ULL, 0x7575c9758fbceafaULL, 0x06061806301e0c36ULL,
+ 0x8a8a128a249809aeULL, 0xb2b2f2b2f940794bULL, 0xe6e6bfe66359d185ULL,
+ 0x0e0e380e70361c7eULL, 0x1f1f7c1ff8633ee7ULL, 0x6262956237f7c455ULL,
+ 0xd4d477d4eea3b53aULL, 0xa8a89aa829324d81ULL, 0x96966296c4f43152ULL,
+ 0xf9f9c3f99b3aef62ULL, 0xc5c533c566f697a3ULL, 0x2525942535b14a10ULL,
+ 0x59597959f220b2abULL, 0x84842a8454ae15d0ULL, 0x7272d572b7a7e4c5ULL,
+ 0x3939e439d5dd72ecULL, 0x4c4c2d4c5a619816ULL, 0x5e5e655eca3bbc94ULL,
+ 0x7878fd78e785f09fULL, 0x3838e038ddd870e5ULL, 0x8c8c0a8c14860598ULL,
+ 0xd1d163d1c6b2bf17ULL, 0xa5a5aea5410b57e4ULL, 0xe2e2afe2434dd9a1ULL,
+ 0x616199612ff8c24eULL, 0xb3b3f6b3f1457b42ULL, 0x2121842115a54234ULL,
+ 0x9c9c4a9c94d62508ULL, 0x1e1e781ef0663ceeULL, 0x4343114322528661ULL,
+ 0xc7c73bc776fc93b1ULL, 0xfcfcd7fcb32be54fULL, 0x0404100420140824ULL,
+ 0x51515951b208a2e3ULL, 0x99995e99bcc72f25ULL, 0x6d6da96d4fc4da22ULL,
+ 0x0d0d340d68391a65ULL, 0xfafacffa8335e979ULL, 0xdfdf5bdfb684a369ULL,
+ 0x7e7ee57ed79bfca9ULL, 0x242490243db44819ULL, 0x3b3bec3bc5d776feULL,
+ 0xabab96ab313d4b9aULL, 0xcece1fce3ed181f0ULL, 0x1111441188552299ULL,
+ 0x8f8f068f0c890383ULL, 0x4e4e254e4a6b9c04ULL, 0xb7b7e6b7d1517366ULL,
+ 0xebeb8beb0b60cbe0ULL, 0x3c3cf03cfdcc78c1ULL, 0x81813e817cbf1ffdULL,
+ 0x94946a94d4fe3540ULL, 0xf7f7fbf7eb0cf31cULL, 0xb9b9deb9a1676f18ULL,
+ 0x13134c13985f268bULL, 0x2c2cb02c7d9c5851ULL, 0xd3d36bd3d6b8bb05ULL,
+ 0xe7e7bbe76b5cd38cULL, 0x6e6ea56e57cbdc39ULL, 0xc4c437c46ef395aaULL,
+ 0x03030c03180f061bULL, 0x565645568a13acdcULL, 0x44440d441a49885eULL,
+ 0x7f7fe17fdf9efea0ULL, 0xa9a99ea921374f88ULL, 0x2a2aa82a4d825467ULL,
+ 0xbbbbd6bbb16d6b0aULL, 0xc1c123c146e29f87ULL, 0x53535153a202a6f1ULL,
+ 0xdcdc57dcae8ba572ULL, 0x0b0b2c0b58271653ULL, 0x9d9d4e9d9cd32701ULL,
+ 0x6c6cad6c47c1d82bULL, 0x3131c43195f562a4ULL, 0x7474cd7487b9e8f3ULL,
+ 0xf6f6fff6e309f115ULL, 0x464605460a438c4cULL, 0xacac8aac092645a5ULL,
+ 0x89891e893c970fb5ULL, 0x14145014a04428b4ULL, 0xe1e1a3e15b42dfbaULL,
+ 0x16165816b04e2ca6ULL, 0x3a3ae83acdd274f7ULL, 0x6969b9696fd0d206ULL,
+ 0x09092409482d1241ULL, 0x7070dd70a7ade0d7ULL, 0xb6b6e2b6d954716fULL,
+ 0xd0d067d0ceb7bd1eULL, 0xeded93ed3b7ec7d6ULL, 0xcccc17cc2edb85e2ULL,
+ 0x424215422a578468ULL, 0x98985a98b4c22d2cULL, 0xa4a4aaa4490e55edULL,
+ 0x2828a0285d885075ULL, 0x5c5c6d5cda31b886ULL, 0xf8f8c7f8933fed6bULL,
+ 0x8686228644a411c2ULL,
+};
+
+static const u64 C1[256] = {
+ 0xd818186018c07830ULL, 0x2623238c2305af46ULL, 0xb8c6c63fc67ef991ULL,
+ 0xfbe8e887e8136fcdULL, 0xcb878726874ca113ULL, 0x11b8b8dab8a9626dULL,
+ 0x0901010401080502ULL, 0x0d4f4f214f426e9eULL, 0x9b3636d836adee6cULL,
+ 0xffa6a6a2a6590451ULL, 0x0cd2d26fd2debdb9ULL, 0x0ef5f5f3f5fb06f7ULL,
+ 0x967979f979ef80f2ULL, 0x306f6fa16f5fcedeULL, 0x6d91917e91fcef3fULL,
+ 0xf852525552aa07a4ULL, 0x4760609d6027fdc0ULL, 0x35bcbccabc897665ULL,
+ 0x379b9b569baccd2bULL, 0x8a8e8e028e048c01ULL, 0xd2a3a3b6a371155bULL,
+ 0x6c0c0c300c603c18ULL, 0x847b7bf17bff8af6ULL, 0x803535d435b5e16aULL,
+ 0xf51d1d741de8693aULL, 0xb3e0e0a7e05347ddULL, 0x21d7d77bd7f6acb3ULL,
+ 0x9cc2c22fc25eed99ULL, 0x432e2eb82e6d965cULL, 0x294b4b314b627a96ULL,
+ 0x5dfefedffea321e1ULL, 0xd5575741578216aeULL, 0xbd15155415a8412aULL,
+ 0xe87777c1779fb6eeULL, 0x923737dc37a5eb6eULL, 0x9ee5e5b3e57b56d7ULL,
+ 0x139f9f469f8cd923ULL, 0x23f0f0e7f0d317fdULL, 0x204a4a354a6a7f94ULL,
+ 0x44dada4fda9e95a9ULL, 0xa258587d58fa25b0ULL, 0xcfc9c903c906ca8fULL,
+ 0x7c2929a429558d52ULL, 0x5a0a0a280a502214ULL, 0x50b1b1feb1e14f7fULL,
+ 0xc9a0a0baa0691a5dULL, 0x146b6bb16b7fdad6ULL, 0xd985852e855cab17ULL,
+ 0x3cbdbdcebd817367ULL, 0x8f5d5d695dd234baULL, 0x9010104010805020ULL,
+ 0x07f4f4f7f4f303f5ULL, 0xddcbcb0bcb16c08bULL, 0xd33e3ef83eedc67cULL,
+ 0x2d0505140528110aULL, 0x78676781671fe6ceULL, 0x97e4e4b7e47353d5ULL,
+ 0x0227279c2725bb4eULL, 0x7341411941325882ULL, 0xa78b8b168b2c9d0bULL,
+ 0xf6a7a7a6a7510153ULL, 0xb27d7de97dcf94faULL, 0x4995956e95dcfb37ULL,
+ 0x56d8d847d88e9fadULL, 0x70fbfbcbfb8b30ebULL, 0xcdeeee9fee2371c1ULL,
+ 0xbb7c7ced7cc791f8ULL, 0x716666856617e3ccULL, 0x7bdddd53dda68ea7ULL,
+ 0xaf17175c17b84b2eULL, 0x454747014702468eULL, 0x1a9e9e429e84dc21ULL,
+ 0xd4caca0fca1ec589ULL, 0x582d2db42d75995aULL, 0x2ebfbfc6bf917963ULL,
+ 0x3f07071c07381b0eULL, 0xacadad8ead012347ULL, 0xb05a5a755aea2fb4ULL,
+ 0xef838336836cb51bULL, 0xb63333cc3385ff66ULL, 0x5c636391633ff2c6ULL,
+ 0x1202020802100a04ULL, 0x93aaaa92aa393849ULL, 0xde7171d971afa8e2ULL,
+ 0xc6c8c807c80ecf8dULL, 0xd119196419c87d32ULL, 0x3b49493949727092ULL,
+ 0x5fd9d943d9869aafULL, 0x31f2f2eff2c31df9ULL, 0xa8e3e3abe34b48dbULL,
+ 0xb95b5b715be22ab6ULL, 0xbc88881a8834920dULL, 0x3e9a9a529aa4c829ULL,
+ 0x0b262698262dbe4cULL, 0xbf3232c8328dfa64ULL, 0x59b0b0fab0e94a7dULL,
+ 0xf2e9e983e91b6acfULL, 0x770f0f3c0f78331eULL, 0x33d5d573d5e6a6b7ULL,
+ 0xf480803a8074ba1dULL, 0x27bebec2be997c61ULL, 0xebcdcd13cd26de87ULL,
+ 0x893434d034bde468ULL, 0x3248483d487a7590ULL, 0x54ffffdbffab24e3ULL,
+ 0x8d7a7af57af78ff4ULL, 0x6490907a90f4ea3dULL, 0x9d5f5f615fc23ebeULL,
+ 0x3d202080201da040ULL, 0x0f6868bd6867d5d0ULL, 0xca1a1a681ad07234ULL,
+ 0xb7aeae82ae192c41ULL, 0x7db4b4eab4c95e75ULL, 0xce54544d549a19a8ULL,
+ 0x7f93937693ece53bULL, 0x2f222288220daa44ULL, 0x6364648d6407e9c8ULL,
+ 0x2af1f1e3f1db12ffULL, 0xcc7373d173bfa2e6ULL, 0x8212124812905a24ULL,
+ 0x7a40401d403a5d80ULL, 0x4808082008402810ULL, 0x95c3c32bc356e89bULL,
+ 0xdfecec97ec337bc5ULL, 0x4ddbdb4bdb9690abULL, 0xc0a1a1bea1611f5fULL,
+ 0x918d8d0e8d1c8307ULL, 0xc83d3df43df5c97aULL, 0x5b97976697ccf133ULL,
+ 0x0000000000000000ULL, 0xf9cfcf1bcf36d483ULL, 0x6e2b2bac2b458756ULL,
+ 0xe17676c57697b3ecULL, 0xe68282328264b019ULL, 0x28d6d67fd6fea9b1ULL,
+ 0xc31b1b6c1bd87736ULL, 0x74b5b5eeb5c15b77ULL, 0xbeafaf86af112943ULL,
+ 0x1d6a6ab56a77dfd4ULL, 0xea50505d50ba0da0ULL, 0x5745450945124c8aULL,
+ 0x38f3f3ebf3cb18fbULL, 0xad3030c0309df060ULL, 0xc4efef9bef2b74c3ULL,
+ 0xda3f3ffc3fe5c37eULL, 0xc755554955921caaULL, 0xdba2a2b2a2791059ULL,
+ 0xe9eaea8fea0365c9ULL, 0x6a656589650feccaULL, 0x03babad2bab96869ULL,
+ 0x4a2f2fbc2f65935eULL, 0x8ec0c027c04ee79dULL, 0x60dede5fdebe81a1ULL,
+ 0xfc1c1c701ce06c38ULL, 0x46fdfdd3fdbb2ee7ULL, 0x1f4d4d294d52649aULL,
+ 0x7692927292e4e039ULL, 0xfa7575c9758fbceaULL, 0x3606061806301e0cULL,
+ 0xae8a8a128a249809ULL, 0x4bb2b2f2b2f94079ULL, 0x85e6e6bfe66359d1ULL,
+ 0x7e0e0e380e70361cULL, 0xe71f1f7c1ff8633eULL, 0x556262956237f7c4ULL,
+ 0x3ad4d477d4eea3b5ULL, 0x81a8a89aa829324dULL, 0x5296966296c4f431ULL,
+ 0x62f9f9c3f99b3aefULL, 0xa3c5c533c566f697ULL, 0x102525942535b14aULL,
+ 0xab59597959f220b2ULL, 0xd084842a8454ae15ULL, 0xc57272d572b7a7e4ULL,
+ 0xec3939e439d5dd72ULL, 0x164c4c2d4c5a6198ULL, 0x945e5e655eca3bbcULL,
+ 0x9f7878fd78e785f0ULL, 0xe53838e038ddd870ULL, 0x988c8c0a8c148605ULL,
+ 0x17d1d163d1c6b2bfULL, 0xe4a5a5aea5410b57ULL, 0xa1e2e2afe2434dd9ULL,
+ 0x4e616199612ff8c2ULL, 0x42b3b3f6b3f1457bULL, 0x342121842115a542ULL,
+ 0x089c9c4a9c94d625ULL, 0xee1e1e781ef0663cULL, 0x6143431143225286ULL,
+ 0xb1c7c73bc776fc93ULL, 0x4ffcfcd7fcb32be5ULL, 0x2404041004201408ULL,
+ 0xe351515951b208a2ULL, 0x2599995e99bcc72fULL, 0x226d6da96d4fc4daULL,
+ 0x650d0d340d68391aULL, 0x79fafacffa8335e9ULL, 0x69dfdf5bdfb684a3ULL,
+ 0xa97e7ee57ed79bfcULL, 0x19242490243db448ULL, 0xfe3b3bec3bc5d776ULL,
+ 0x9aabab96ab313d4bULL, 0xf0cece1fce3ed181ULL, 0x9911114411885522ULL,
+ 0x838f8f068f0c8903ULL, 0x044e4e254e4a6b9cULL, 0x66b7b7e6b7d15173ULL,
+ 0xe0ebeb8beb0b60cbULL, 0xc13c3cf03cfdcc78ULL, 0xfd81813e817cbf1fULL,
+ 0x4094946a94d4fe35ULL, 0x1cf7f7fbf7eb0cf3ULL, 0x18b9b9deb9a1676fULL,
+ 0x8b13134c13985f26ULL, 0x512c2cb02c7d9c58ULL, 0x05d3d36bd3d6b8bbULL,
+ 0x8ce7e7bbe76b5cd3ULL, 0x396e6ea56e57cbdcULL, 0xaac4c437c46ef395ULL,
+ 0x1b03030c03180f06ULL, 0xdc565645568a13acULL, 0x5e44440d441a4988ULL,
+ 0xa07f7fe17fdf9efeULL, 0x88a9a99ea921374fULL, 0x672a2aa82a4d8254ULL,
+ 0x0abbbbd6bbb16d6bULL, 0x87c1c123c146e29fULL, 0xf153535153a202a6ULL,
+ 0x72dcdc57dcae8ba5ULL, 0x530b0b2c0b582716ULL, 0x019d9d4e9d9cd327ULL,
+ 0x2b6c6cad6c47c1d8ULL, 0xa43131c43195f562ULL, 0xf37474cd7487b9e8ULL,
+ 0x15f6f6fff6e309f1ULL, 0x4c464605460a438cULL, 0xa5acac8aac092645ULL,
+ 0xb589891e893c970fULL, 0xb414145014a04428ULL, 0xbae1e1a3e15b42dfULL,
+ 0xa616165816b04e2cULL, 0xf73a3ae83acdd274ULL, 0x066969b9696fd0d2ULL,
+ 0x4109092409482d12ULL, 0xd77070dd70a7ade0ULL, 0x6fb6b6e2b6d95471ULL,
+ 0x1ed0d067d0ceb7bdULL, 0xd6eded93ed3b7ec7ULL, 0xe2cccc17cc2edb85ULL,
+ 0x68424215422a5784ULL, 0x2c98985a98b4c22dULL, 0xeda4a4aaa4490e55ULL,
+ 0x752828a0285d8850ULL, 0x865c5c6d5cda31b8ULL, 0x6bf8f8c7f8933fedULL,
+ 0xc28686228644a411ULL,
+};
+
+static const u64 C2[256] = {
+ 0x30d818186018c078ULL, 0x462623238c2305afULL, 0x91b8c6c63fc67ef9ULL,
+ 0xcdfbe8e887e8136fULL, 0x13cb878726874ca1ULL, 0x6d11b8b8dab8a962ULL,
+ 0x0209010104010805ULL, 0x9e0d4f4f214f426eULL, 0x6c9b3636d836adeeULL,
+ 0x51ffa6a6a2a65904ULL, 0xb90cd2d26fd2debdULL, 0xf70ef5f5f3f5fb06ULL,
+ 0xf2967979f979ef80ULL, 0xde306f6fa16f5fceULL, 0x3f6d91917e91fcefULL,
+ 0xa4f852525552aa07ULL, 0xc04760609d6027fdULL, 0x6535bcbccabc8976ULL,
+ 0x2b379b9b569baccdULL, 0x018a8e8e028e048cULL, 0x5bd2a3a3b6a37115ULL,
+ 0x186c0c0c300c603cULL, 0xf6847b7bf17bff8aULL, 0x6a803535d435b5e1ULL,
+ 0x3af51d1d741de869ULL, 0xddb3e0e0a7e05347ULL, 0xb321d7d77bd7f6acULL,
+ 0x999cc2c22fc25eedULL, 0x5c432e2eb82e6d96ULL, 0x96294b4b314b627aULL,
+ 0xe15dfefedffea321ULL, 0xaed5575741578216ULL, 0x2abd15155415a841ULL,
+ 0xeee87777c1779fb6ULL, 0x6e923737dc37a5ebULL, 0xd79ee5e5b3e57b56ULL,
+ 0x23139f9f469f8cd9ULL, 0xfd23f0f0e7f0d317ULL, 0x94204a4a354a6a7fULL,
+ 0xa944dada4fda9e95ULL, 0xb0a258587d58fa25ULL, 0x8fcfc9c903c906caULL,
+ 0x527c2929a429558dULL, 0x145a0a0a280a5022ULL, 0x7f50b1b1feb1e14fULL,
+ 0x5dc9a0a0baa0691aULL, 0xd6146b6bb16b7fdaULL, 0x17d985852e855cabULL,
+ 0x673cbdbdcebd8173ULL, 0xba8f5d5d695dd234ULL, 0x2090101040108050ULL,
+ 0xf507f4f4f7f4f303ULL, 0x8bddcbcb0bcb16c0ULL, 0x7cd33e3ef83eedc6ULL,
+ 0x0a2d050514052811ULL, 0xce78676781671fe6ULL, 0xd597e4e4b7e47353ULL,
+ 0x4e0227279c2725bbULL, 0x8273414119413258ULL, 0x0ba78b8b168b2c9dULL,
+ 0x53f6a7a7a6a75101ULL, 0xfab27d7de97dcf94ULL, 0x374995956e95dcfbULL,
+ 0xad56d8d847d88e9fULL, 0xeb70fbfbcbfb8b30ULL, 0xc1cdeeee9fee2371ULL,
+ 0xf8bb7c7ced7cc791ULL, 0xcc716666856617e3ULL, 0xa77bdddd53dda68eULL,
+ 0x2eaf17175c17b84bULL, 0x8e45474701470246ULL, 0x211a9e9e429e84dcULL,
+ 0x89d4caca0fca1ec5ULL, 0x5a582d2db42d7599ULL, 0x632ebfbfc6bf9179ULL,
+ 0x0e3f07071c07381bULL, 0x47acadad8ead0123ULL, 0xb4b05a5a755aea2fULL,
+ 0x1bef838336836cb5ULL, 0x66b63333cc3385ffULL, 0xc65c636391633ff2ULL,
+ 0x041202020802100aULL, 0x4993aaaa92aa3938ULL, 0xe2de7171d971afa8ULL,
+ 0x8dc6c8c807c80ecfULL, 0x32d119196419c87dULL, 0x923b494939497270ULL,
+ 0xaf5fd9d943d9869aULL, 0xf931f2f2eff2c31dULL, 0xdba8e3e3abe34b48ULL,
+ 0xb6b95b5b715be22aULL, 0x0dbc88881a883492ULL, 0x293e9a9a529aa4c8ULL,
+ 0x4c0b262698262dbeULL, 0x64bf3232c8328dfaULL, 0x7d59b0b0fab0e94aULL,
+ 0xcff2e9e983e91b6aULL, 0x1e770f0f3c0f7833ULL, 0xb733d5d573d5e6a6ULL,
+ 0x1df480803a8074baULL, 0x6127bebec2be997cULL, 0x87ebcdcd13cd26deULL,
+ 0x68893434d034bde4ULL, 0x903248483d487a75ULL, 0xe354ffffdbffab24ULL,
+ 0xf48d7a7af57af78fULL, 0x3d6490907a90f4eaULL, 0xbe9d5f5f615fc23eULL,
+ 0x403d202080201da0ULL, 0xd00f6868bd6867d5ULL, 0x34ca1a1a681ad072ULL,
+ 0x41b7aeae82ae192cULL, 0x757db4b4eab4c95eULL, 0xa8ce54544d549a19ULL,
+ 0x3b7f93937693ece5ULL, 0x442f222288220daaULL, 0xc86364648d6407e9ULL,
+ 0xff2af1f1e3f1db12ULL, 0xe6cc7373d173bfa2ULL, 0x248212124812905aULL,
+ 0x807a40401d403a5dULL, 0x1048080820084028ULL, 0x9b95c3c32bc356e8ULL,
+ 0xc5dfecec97ec337bULL, 0xab4ddbdb4bdb9690ULL, 0x5fc0a1a1bea1611fULL,
+ 0x07918d8d0e8d1c83ULL, 0x7ac83d3df43df5c9ULL, 0x335b97976697ccf1ULL,
+ 0x0000000000000000ULL, 0x83f9cfcf1bcf36d4ULL, 0x566e2b2bac2b4587ULL,
+ 0xece17676c57697b3ULL, 0x19e68282328264b0ULL, 0xb128d6d67fd6fea9ULL,
+ 0x36c31b1b6c1bd877ULL, 0x7774b5b5eeb5c15bULL, 0x43beafaf86af1129ULL,
+ 0xd41d6a6ab56a77dfULL, 0xa0ea50505d50ba0dULL, 0x8a5745450945124cULL,
+ 0xfb38f3f3ebf3cb18ULL, 0x60ad3030c0309df0ULL, 0xc3c4efef9bef2b74ULL,
+ 0x7eda3f3ffc3fe5c3ULL, 0xaac755554955921cULL, 0x59dba2a2b2a27910ULL,
+ 0xc9e9eaea8fea0365ULL, 0xca6a656589650fecULL, 0x6903babad2bab968ULL,
+ 0x5e4a2f2fbc2f6593ULL, 0x9d8ec0c027c04ee7ULL, 0xa160dede5fdebe81ULL,
+ 0x38fc1c1c701ce06cULL, 0xe746fdfdd3fdbb2eULL, 0x9a1f4d4d294d5264ULL,
+ 0x397692927292e4e0ULL, 0xeafa7575c9758fbcULL, 0x0c3606061806301eULL,
+ 0x09ae8a8a128a2498ULL, 0x794bb2b2f2b2f940ULL, 0xd185e6e6bfe66359ULL,
+ 0x1c7e0e0e380e7036ULL, 0x3ee71f1f7c1ff863ULL, 0xc4556262956237f7ULL,
+ 0xb53ad4d477d4eea3ULL, 0x4d81a8a89aa82932ULL, 0x315296966296c4f4ULL,
+ 0xef62f9f9c3f99b3aULL, 0x97a3c5c533c566f6ULL, 0x4a102525942535b1ULL,
+ 0xb2ab59597959f220ULL, 0x15d084842a8454aeULL, 0xe4c57272d572b7a7ULL,
+ 0x72ec3939e439d5ddULL, 0x98164c4c2d4c5a61ULL, 0xbc945e5e655eca3bULL,
+ 0xf09f7878fd78e785ULL, 0x70e53838e038ddd8ULL, 0x05988c8c0a8c1486ULL,
+ 0xbf17d1d163d1c6b2ULL, 0x57e4a5a5aea5410bULL, 0xd9a1e2e2afe2434dULL,
+ 0xc24e616199612ff8ULL, 0x7b42b3b3f6b3f145ULL, 0x42342121842115a5ULL,
+ 0x25089c9c4a9c94d6ULL, 0x3cee1e1e781ef066ULL, 0x8661434311432252ULL,
+ 0x93b1c7c73bc776fcULL, 0xe54ffcfcd7fcb32bULL, 0x0824040410042014ULL,
+ 0xa2e351515951b208ULL, 0x2f2599995e99bcc7ULL, 0xda226d6da96d4fc4ULL,
+ 0x1a650d0d340d6839ULL, 0xe979fafacffa8335ULL, 0xa369dfdf5bdfb684ULL,
+ 0xfca97e7ee57ed79bULL, 0x4819242490243db4ULL, 0x76fe3b3bec3bc5d7ULL,
+ 0x4b9aabab96ab313dULL, 0x81f0cece1fce3ed1ULL, 0x2299111144118855ULL,
+ 0x03838f8f068f0c89ULL, 0x9c044e4e254e4a6bULL, 0x7366b7b7e6b7d151ULL,
+ 0xcbe0ebeb8beb0b60ULL, 0x78c13c3cf03cfdccULL, 0x1ffd81813e817cbfULL,
+ 0x354094946a94d4feULL, 0xf31cf7f7fbf7eb0cULL, 0x6f18b9b9deb9a167ULL,
+ 0x268b13134c13985fULL, 0x58512c2cb02c7d9cULL, 0xbb05d3d36bd3d6b8ULL,
+ 0xd38ce7e7bbe76b5cULL, 0xdc396e6ea56e57cbULL, 0x95aac4c437c46ef3ULL,
+ 0x061b03030c03180fULL, 0xacdc565645568a13ULL, 0x885e44440d441a49ULL,
+ 0xfea07f7fe17fdf9eULL, 0x4f88a9a99ea92137ULL, 0x54672a2aa82a4d82ULL,
+ 0x6b0abbbbd6bbb16dULL, 0x9f87c1c123c146e2ULL, 0xa6f153535153a202ULL,
+ 0xa572dcdc57dcae8bULL, 0x16530b0b2c0b5827ULL, 0x27019d9d4e9d9cd3ULL,
+ 0xd82b6c6cad6c47c1ULL, 0x62a43131c43195f5ULL, 0xe8f37474cd7487b9ULL,
+ 0xf115f6f6fff6e309ULL, 0x8c4c464605460a43ULL, 0x45a5acac8aac0926ULL,
+ 0x0fb589891e893c97ULL, 0x28b414145014a044ULL, 0xdfbae1e1a3e15b42ULL,
+ 0x2ca616165816b04eULL, 0x74f73a3ae83acdd2ULL, 0xd2066969b9696fd0ULL,
+ 0x124109092409482dULL, 0xe0d77070dd70a7adULL, 0x716fb6b6e2b6d954ULL,
+ 0xbd1ed0d067d0ceb7ULL, 0xc7d6eded93ed3b7eULL, 0x85e2cccc17cc2edbULL,
+ 0x8468424215422a57ULL, 0x2d2c98985a98b4c2ULL, 0x55eda4a4aaa4490eULL,
+ 0x50752828a0285d88ULL, 0xb8865c5c6d5cda31ULL, 0xed6bf8f8c7f8933fULL,
+ 0x11c28686228644a4ULL,
+};
+
+static const u64 C3[256] = {
+ 0x7830d818186018c0ULL, 0xaf462623238c2305ULL, 0xf991b8c6c63fc67eULL,
+ 0x6fcdfbe8e887e813ULL, 0xa113cb878726874cULL, 0x626d11b8b8dab8a9ULL,
+ 0x0502090101040108ULL, 0x6e9e0d4f4f214f42ULL, 0xee6c9b3636d836adULL,
+ 0x0451ffa6a6a2a659ULL, 0xbdb90cd2d26fd2deULL, 0x06f70ef5f5f3f5fbULL,
+ 0x80f2967979f979efULL, 0xcede306f6fa16f5fULL, 0xef3f6d91917e91fcULL,
+ 0x07a4f852525552aaULL, 0xfdc04760609d6027ULL, 0x766535bcbccabc89ULL,
+ 0xcd2b379b9b569bacULL, 0x8c018a8e8e028e04ULL, 0x155bd2a3a3b6a371ULL,
+ 0x3c186c0c0c300c60ULL, 0x8af6847b7bf17bffULL, 0xe16a803535d435b5ULL,
+ 0x693af51d1d741de8ULL, 0x47ddb3e0e0a7e053ULL, 0xacb321d7d77bd7f6ULL,
+ 0xed999cc2c22fc25eULL, 0x965c432e2eb82e6dULL, 0x7a96294b4b314b62ULL,
+ 0x21e15dfefedffea3ULL, 0x16aed55757415782ULL, 0x412abd15155415a8ULL,
+ 0xb6eee87777c1779fULL, 0xeb6e923737dc37a5ULL, 0x56d79ee5e5b3e57bULL,
+ 0xd923139f9f469f8cULL, 0x17fd23f0f0e7f0d3ULL, 0x7f94204a4a354a6aULL,
+ 0x95a944dada4fda9eULL, 0x25b0a258587d58faULL, 0xca8fcfc9c903c906ULL,
+ 0x8d527c2929a42955ULL, 0x22145a0a0a280a50ULL, 0x4f7f50b1b1feb1e1ULL,
+ 0x1a5dc9a0a0baa069ULL, 0xdad6146b6bb16b7fULL, 0xab17d985852e855cULL,
+ 0x73673cbdbdcebd81ULL, 0x34ba8f5d5d695dd2ULL, 0x5020901010401080ULL,
+ 0x03f507f4f4f7f4f3ULL, 0xc08bddcbcb0bcb16ULL, 0xc67cd33e3ef83eedULL,
+ 0x110a2d0505140528ULL, 0xe6ce78676781671fULL, 0x53d597e4e4b7e473ULL,
+ 0xbb4e0227279c2725ULL, 0x5882734141194132ULL, 0x9d0ba78b8b168b2cULL,
+ 0x0153f6a7a7a6a751ULL, 0x94fab27d7de97dcfULL, 0xfb374995956e95dcULL,
+ 0x9fad56d8d847d88eULL, 0x30eb70fbfbcbfb8bULL, 0x71c1cdeeee9fee23ULL,
+ 0x91f8bb7c7ced7cc7ULL, 0xe3cc716666856617ULL, 0x8ea77bdddd53dda6ULL,
+ 0x4b2eaf17175c17b8ULL, 0x468e454747014702ULL, 0xdc211a9e9e429e84ULL,
+ 0xc589d4caca0fca1eULL, 0x995a582d2db42d75ULL, 0x79632ebfbfc6bf91ULL,
+ 0x1b0e3f07071c0738ULL, 0x2347acadad8ead01ULL, 0x2fb4b05a5a755aeaULL,
+ 0xb51bef838336836cULL, 0xff66b63333cc3385ULL, 0xf2c65c636391633fULL,
+ 0x0a04120202080210ULL, 0x384993aaaa92aa39ULL, 0xa8e2de7171d971afULL,
+ 0xcf8dc6c8c807c80eULL, 0x7d32d119196419c8ULL, 0x70923b4949394972ULL,
+ 0x9aaf5fd9d943d986ULL, 0x1df931f2f2eff2c3ULL, 0x48dba8e3e3abe34bULL,
+ 0x2ab6b95b5b715be2ULL, 0x920dbc88881a8834ULL, 0xc8293e9a9a529aa4ULL,
+ 0xbe4c0b262698262dULL, 0xfa64bf3232c8328dULL, 0x4a7d59b0b0fab0e9ULL,
+ 0x6acff2e9e983e91bULL, 0x331e770f0f3c0f78ULL, 0xa6b733d5d573d5e6ULL,
+ 0xba1df480803a8074ULL, 0x7c6127bebec2be99ULL, 0xde87ebcdcd13cd26ULL,
+ 0xe468893434d034bdULL, 0x75903248483d487aULL, 0x24e354ffffdbffabULL,
+ 0x8ff48d7a7af57af7ULL, 0xea3d6490907a90f4ULL, 0x3ebe9d5f5f615fc2ULL,
+ 0xa0403d202080201dULL, 0xd5d00f6868bd6867ULL, 0x7234ca1a1a681ad0ULL,
+ 0x2c41b7aeae82ae19ULL, 0x5e757db4b4eab4c9ULL, 0x19a8ce54544d549aULL,
+ 0xe53b7f93937693ecULL, 0xaa442f222288220dULL, 0xe9c86364648d6407ULL,
+ 0x12ff2af1f1e3f1dbULL, 0xa2e6cc7373d173bfULL, 0x5a24821212481290ULL,
+ 0x5d807a40401d403aULL, 0x2810480808200840ULL, 0xe89b95c3c32bc356ULL,
+ 0x7bc5dfecec97ec33ULL, 0x90ab4ddbdb4bdb96ULL, 0x1f5fc0a1a1bea161ULL,
+ 0x8307918d8d0e8d1cULL, 0xc97ac83d3df43df5ULL, 0xf1335b97976697ccULL,
+ 0x0000000000000000ULL, 0xd483f9cfcf1bcf36ULL, 0x87566e2b2bac2b45ULL,
+ 0xb3ece17676c57697ULL, 0xb019e68282328264ULL, 0xa9b128d6d67fd6feULL,
+ 0x7736c31b1b6c1bd8ULL, 0x5b7774b5b5eeb5c1ULL, 0x2943beafaf86af11ULL,
+ 0xdfd41d6a6ab56a77ULL, 0x0da0ea50505d50baULL, 0x4c8a574545094512ULL,
+ 0x18fb38f3f3ebf3cbULL, 0xf060ad3030c0309dULL, 0x74c3c4efef9bef2bULL,
+ 0xc37eda3f3ffc3fe5ULL, 0x1caac75555495592ULL, 0x1059dba2a2b2a279ULL,
+ 0x65c9e9eaea8fea03ULL, 0xecca6a656589650fULL, 0x686903babad2bab9ULL,
+ 0x935e4a2f2fbc2f65ULL, 0xe79d8ec0c027c04eULL, 0x81a160dede5fdebeULL,
+ 0x6c38fc1c1c701ce0ULL, 0x2ee746fdfdd3fdbbULL, 0x649a1f4d4d294d52ULL,
+ 0xe0397692927292e4ULL, 0xbceafa7575c9758fULL, 0x1e0c360606180630ULL,
+ 0x9809ae8a8a128a24ULL, 0x40794bb2b2f2b2f9ULL, 0x59d185e6e6bfe663ULL,
+ 0x361c7e0e0e380e70ULL, 0x633ee71f1f7c1ff8ULL, 0xf7c4556262956237ULL,
+ 0xa3b53ad4d477d4eeULL, 0x324d81a8a89aa829ULL, 0xf4315296966296c4ULL,
+ 0x3aef62f9f9c3f99bULL, 0xf697a3c5c533c566ULL, 0xb14a102525942535ULL,
+ 0x20b2ab59597959f2ULL, 0xae15d084842a8454ULL, 0xa7e4c57272d572b7ULL,
+ 0xdd72ec3939e439d5ULL, 0x6198164c4c2d4c5aULL, 0x3bbc945e5e655ecaULL,
+ 0x85f09f7878fd78e7ULL, 0xd870e53838e038ddULL, 0x8605988c8c0a8c14ULL,
+ 0xb2bf17d1d163d1c6ULL, 0x0b57e4a5a5aea541ULL, 0x4dd9a1e2e2afe243ULL,
+ 0xf8c24e616199612fULL, 0x457b42b3b3f6b3f1ULL, 0xa542342121842115ULL,
+ 0xd625089c9c4a9c94ULL, 0x663cee1e1e781ef0ULL, 0x5286614343114322ULL,
+ 0xfc93b1c7c73bc776ULL, 0x2be54ffcfcd7fcb3ULL, 0x1408240404100420ULL,
+ 0x08a2e351515951b2ULL, 0xc72f2599995e99bcULL, 0xc4da226d6da96d4fULL,
+ 0x391a650d0d340d68ULL, 0x35e979fafacffa83ULL, 0x84a369dfdf5bdfb6ULL,
+ 0x9bfca97e7ee57ed7ULL, 0xb44819242490243dULL, 0xd776fe3b3bec3bc5ULL,
+ 0x3d4b9aabab96ab31ULL, 0xd181f0cece1fce3eULL, 0x5522991111441188ULL,
+ 0x8903838f8f068f0cULL, 0x6b9c044e4e254e4aULL, 0x517366b7b7e6b7d1ULL,
+ 0x60cbe0ebeb8beb0bULL, 0xcc78c13c3cf03cfdULL, 0xbf1ffd81813e817cULL,
+ 0xfe354094946a94d4ULL, 0x0cf31cf7f7fbf7ebULL, 0x676f18b9b9deb9a1ULL,
+ 0x5f268b13134c1398ULL, 0x9c58512c2cb02c7dULL, 0xb8bb05d3d36bd3d6ULL,
+ 0x5cd38ce7e7bbe76bULL, 0xcbdc396e6ea56e57ULL, 0xf395aac4c437c46eULL,
+ 0x0f061b03030c0318ULL, 0x13acdc565645568aULL, 0x49885e44440d441aULL,
+ 0x9efea07f7fe17fdfULL, 0x374f88a9a99ea921ULL, 0x8254672a2aa82a4dULL,
+ 0x6d6b0abbbbd6bbb1ULL, 0xe29f87c1c123c146ULL, 0x02a6f153535153a2ULL,
+ 0x8ba572dcdc57dcaeULL, 0x2716530b0b2c0b58ULL, 0xd327019d9d4e9d9cULL,
+ 0xc1d82b6c6cad6c47ULL, 0xf562a43131c43195ULL, 0xb9e8f37474cd7487ULL,
+ 0x09f115f6f6fff6e3ULL, 0x438c4c464605460aULL, 0x2645a5acac8aac09ULL,
+ 0x970fb589891e893cULL, 0x4428b414145014a0ULL, 0x42dfbae1e1a3e15bULL,
+ 0x4e2ca616165816b0ULL, 0xd274f73a3ae83acdULL, 0xd0d2066969b9696fULL,
+ 0x2d12410909240948ULL, 0xade0d77070dd70a7ULL, 0x54716fb6b6e2b6d9ULL,
+ 0xb7bd1ed0d067d0ceULL, 0x7ec7d6eded93ed3bULL, 0xdb85e2cccc17cc2eULL,
+ 0x578468424215422aULL, 0xc22d2c98985a98b4ULL, 0x0e55eda4a4aaa449ULL,
+ 0x8850752828a0285dULL, 0x31b8865c5c6d5cdaULL, 0x3fed6bf8f8c7f893ULL,
+ 0xa411c28686228644ULL,
+};
+
+static const u64 C4[256] = {
+ 0xc07830d818186018ULL, 0x05af462623238c23ULL, 0x7ef991b8c6c63fc6ULL,
+ 0x136fcdfbe8e887e8ULL, 0x4ca113cb87872687ULL, 0xa9626d11b8b8dab8ULL,
+ 0x0805020901010401ULL, 0x426e9e0d4f4f214fULL, 0xadee6c9b3636d836ULL,
+ 0x590451ffa6a6a2a6ULL, 0xdebdb90cd2d26fd2ULL, 0xfb06f70ef5f5f3f5ULL,
+ 0xef80f2967979f979ULL, 0x5fcede306f6fa16fULL, 0xfcef3f6d91917e91ULL,
+ 0xaa07a4f852525552ULL, 0x27fdc04760609d60ULL, 0x89766535bcbccabcULL,
+ 0xaccd2b379b9b569bULL, 0x048c018a8e8e028eULL, 0x71155bd2a3a3b6a3ULL,
+ 0x603c186c0c0c300cULL, 0xff8af6847b7bf17bULL, 0xb5e16a803535d435ULL,
+ 0xe8693af51d1d741dULL, 0x5347ddb3e0e0a7e0ULL, 0xf6acb321d7d77bd7ULL,
+ 0x5eed999cc2c22fc2ULL, 0x6d965c432e2eb82eULL, 0x627a96294b4b314bULL,
+ 0xa321e15dfefedffeULL, 0x8216aed557574157ULL, 0xa8412abd15155415ULL,
+ 0x9fb6eee87777c177ULL, 0xa5eb6e923737dc37ULL, 0x7b56d79ee5e5b3e5ULL,
+ 0x8cd923139f9f469fULL, 0xd317fd23f0f0e7f0ULL, 0x6a7f94204a4a354aULL,
+ 0x9e95a944dada4fdaULL, 0xfa25b0a258587d58ULL, 0x06ca8fcfc9c903c9ULL,
+ 0x558d527c2929a429ULL, 0x5022145a0a0a280aULL, 0xe14f7f50b1b1feb1ULL,
+ 0x691a5dc9a0a0baa0ULL, 0x7fdad6146b6bb16bULL, 0x5cab17d985852e85ULL,
+ 0x8173673cbdbdcebdULL, 0xd234ba8f5d5d695dULL, 0x8050209010104010ULL,
+ 0xf303f507f4f4f7f4ULL, 0x16c08bddcbcb0bcbULL, 0xedc67cd33e3ef83eULL,
+ 0x28110a2d05051405ULL, 0x1fe6ce7867678167ULL, 0x7353d597e4e4b7e4ULL,
+ 0x25bb4e0227279c27ULL, 0x3258827341411941ULL, 0x2c9d0ba78b8b168bULL,
+ 0x510153f6a7a7a6a7ULL, 0xcf94fab27d7de97dULL, 0xdcfb374995956e95ULL,
+ 0x8e9fad56d8d847d8ULL, 0x8b30eb70fbfbcbfbULL, 0x2371c1cdeeee9feeULL,
+ 0xc791f8bb7c7ced7cULL, 0x17e3cc7166668566ULL, 0xa68ea77bdddd53ddULL,
+ 0xb84b2eaf17175c17ULL, 0x02468e4547470147ULL, 0x84dc211a9e9e429eULL,
+ 0x1ec589d4caca0fcaULL, 0x75995a582d2db42dULL, 0x9179632ebfbfc6bfULL,
+ 0x381b0e3f07071c07ULL, 0x012347acadad8eadULL, 0xea2fb4b05a5a755aULL,
+ 0x6cb51bef83833683ULL, 0x85ff66b63333cc33ULL, 0x3ff2c65c63639163ULL,
+ 0x100a041202020802ULL, 0x39384993aaaa92aaULL, 0xafa8e2de7171d971ULL,
+ 0x0ecf8dc6c8c807c8ULL, 0xc87d32d119196419ULL, 0x7270923b49493949ULL,
+ 0x869aaf5fd9d943d9ULL, 0xc31df931f2f2eff2ULL, 0x4b48dba8e3e3abe3ULL,
+ 0xe22ab6b95b5b715bULL, 0x34920dbc88881a88ULL, 0xa4c8293e9a9a529aULL,
+ 0x2dbe4c0b26269826ULL, 0x8dfa64bf3232c832ULL, 0xe94a7d59b0b0fab0ULL,
+ 0x1b6acff2e9e983e9ULL, 0x78331e770f0f3c0fULL, 0xe6a6b733d5d573d5ULL,
+ 0x74ba1df480803a80ULL, 0x997c6127bebec2beULL, 0x26de87ebcdcd13cdULL,
+ 0xbde468893434d034ULL, 0x7a75903248483d48ULL, 0xab24e354ffffdbffULL,
+ 0xf78ff48d7a7af57aULL, 0xf4ea3d6490907a90ULL, 0xc23ebe9d5f5f615fULL,
+ 0x1da0403d20208020ULL, 0x67d5d00f6868bd68ULL, 0xd07234ca1a1a681aULL,
+ 0x192c41b7aeae82aeULL, 0xc95e757db4b4eab4ULL, 0x9a19a8ce54544d54ULL,
+ 0xece53b7f93937693ULL, 0x0daa442f22228822ULL, 0x07e9c86364648d64ULL,
+ 0xdb12ff2af1f1e3f1ULL, 0xbfa2e6cc7373d173ULL, 0x905a248212124812ULL,
+ 0x3a5d807a40401d40ULL, 0x4028104808082008ULL, 0x56e89b95c3c32bc3ULL,
+ 0x337bc5dfecec97ecULL, 0x9690ab4ddbdb4bdbULL, 0x611f5fc0a1a1bea1ULL,
+ 0x1c8307918d8d0e8dULL, 0xf5c97ac83d3df43dULL, 0xccf1335b97976697ULL,
+ 0x0000000000000000ULL, 0x36d483f9cfcf1bcfULL, 0x4587566e2b2bac2bULL,
+ 0x97b3ece17676c576ULL, 0x64b019e682823282ULL, 0xfea9b128d6d67fd6ULL,
+ 0xd87736c31b1b6c1bULL, 0xc15b7774b5b5eeb5ULL, 0x112943beafaf86afULL,
+ 0x77dfd41d6a6ab56aULL, 0xba0da0ea50505d50ULL, 0x124c8a5745450945ULL,
+ 0xcb18fb38f3f3ebf3ULL, 0x9df060ad3030c030ULL, 0x2b74c3c4efef9befULL,
+ 0xe5c37eda3f3ffc3fULL, 0x921caac755554955ULL, 0x791059dba2a2b2a2ULL,
+ 0x0365c9e9eaea8feaULL, 0x0fecca6a65658965ULL, 0xb9686903babad2baULL,
+ 0x65935e4a2f2fbc2fULL, 0x4ee79d8ec0c027c0ULL, 0xbe81a160dede5fdeULL,
+ 0xe06c38fc1c1c701cULL, 0xbb2ee746fdfdd3fdULL, 0x52649a1f4d4d294dULL,
+ 0xe4e0397692927292ULL, 0x8fbceafa7575c975ULL, 0x301e0c3606061806ULL,
+ 0x249809ae8a8a128aULL, 0xf940794bb2b2f2b2ULL, 0x6359d185e6e6bfe6ULL,
+ 0x70361c7e0e0e380eULL, 0xf8633ee71f1f7c1fULL, 0x37f7c45562629562ULL,
+ 0xeea3b53ad4d477d4ULL, 0x29324d81a8a89aa8ULL, 0xc4f4315296966296ULL,
+ 0x9b3aef62f9f9c3f9ULL, 0x66f697a3c5c533c5ULL, 0x35b14a1025259425ULL,
+ 0xf220b2ab59597959ULL, 0x54ae15d084842a84ULL, 0xb7a7e4c57272d572ULL,
+ 0xd5dd72ec3939e439ULL, 0x5a6198164c4c2d4cULL, 0xca3bbc945e5e655eULL,
+ 0xe785f09f7878fd78ULL, 0xddd870e53838e038ULL, 0x148605988c8c0a8cULL,
+ 0xc6b2bf17d1d163d1ULL, 0x410b57e4a5a5aea5ULL, 0x434dd9a1e2e2afe2ULL,
+ 0x2ff8c24e61619961ULL, 0xf1457b42b3b3f6b3ULL, 0x15a5423421218421ULL,
+ 0x94d625089c9c4a9cULL, 0xf0663cee1e1e781eULL, 0x2252866143431143ULL,
+ 0x76fc93b1c7c73bc7ULL, 0xb32be54ffcfcd7fcULL, 0x2014082404041004ULL,
+ 0xb208a2e351515951ULL, 0xbcc72f2599995e99ULL, 0x4fc4da226d6da96dULL,
+ 0x68391a650d0d340dULL, 0x8335e979fafacffaULL, 0xb684a369dfdf5bdfULL,
+ 0xd79bfca97e7ee57eULL, 0x3db4481924249024ULL, 0xc5d776fe3b3bec3bULL,
+ 0x313d4b9aabab96abULL, 0x3ed181f0cece1fceULL, 0x8855229911114411ULL,
+ 0x0c8903838f8f068fULL, 0x4a6b9c044e4e254eULL, 0xd1517366b7b7e6b7ULL,
+ 0x0b60cbe0ebeb8bebULL, 0xfdcc78c13c3cf03cULL, 0x7cbf1ffd81813e81ULL,
+ 0xd4fe354094946a94ULL, 0xeb0cf31cf7f7fbf7ULL, 0xa1676f18b9b9deb9ULL,
+ 0x985f268b13134c13ULL, 0x7d9c58512c2cb02cULL, 0xd6b8bb05d3d36bd3ULL,
+ 0x6b5cd38ce7e7bbe7ULL, 0x57cbdc396e6ea56eULL, 0x6ef395aac4c437c4ULL,
+ 0x180f061b03030c03ULL, 0x8a13acdc56564556ULL, 0x1a49885e44440d44ULL,
+ 0xdf9efea07f7fe17fULL, 0x21374f88a9a99ea9ULL, 0x4d8254672a2aa82aULL,
+ 0xb16d6b0abbbbd6bbULL, 0x46e29f87c1c123c1ULL, 0xa202a6f153535153ULL,
+ 0xae8ba572dcdc57dcULL, 0x582716530b0b2c0bULL, 0x9cd327019d9d4e9dULL,
+ 0x47c1d82b6c6cad6cULL, 0x95f562a43131c431ULL, 0x87b9e8f37474cd74ULL,
+ 0xe309f115f6f6fff6ULL, 0x0a438c4c46460546ULL, 0x092645a5acac8aacULL,
+ 0x3c970fb589891e89ULL, 0xa04428b414145014ULL, 0x5b42dfbae1e1a3e1ULL,
+ 0xb04e2ca616165816ULL, 0xcdd274f73a3ae83aULL, 0x6fd0d2066969b969ULL,
+ 0x482d124109092409ULL, 0xa7ade0d77070dd70ULL, 0xd954716fb6b6e2b6ULL,
+ 0xceb7bd1ed0d067d0ULL, 0x3b7ec7d6eded93edULL, 0x2edb85e2cccc17ccULL,
+ 0x2a57846842421542ULL, 0xb4c22d2c98985a98ULL, 0x490e55eda4a4aaa4ULL,
+ 0x5d8850752828a028ULL, 0xda31b8865c5c6d5cULL, 0x933fed6bf8f8c7f8ULL,
+ 0x44a411c286862286ULL,
+};
+
+static const u64 C5[256] = {
+ 0x18c07830d8181860ULL, 0x2305af462623238cULL, 0xc67ef991b8c6c63fULL,
+ 0xe8136fcdfbe8e887ULL, 0x874ca113cb878726ULL, 0xb8a9626d11b8b8daULL,
+ 0x0108050209010104ULL, 0x4f426e9e0d4f4f21ULL, 0x36adee6c9b3636d8ULL,
+ 0xa6590451ffa6a6a2ULL, 0xd2debdb90cd2d26fULL, 0xf5fb06f70ef5f5f3ULL,
+ 0x79ef80f2967979f9ULL, 0x6f5fcede306f6fa1ULL, 0x91fcef3f6d91917eULL,
+ 0x52aa07a4f8525255ULL, 0x6027fdc04760609dULL, 0xbc89766535bcbccaULL,
+ 0x9baccd2b379b9b56ULL, 0x8e048c018a8e8e02ULL, 0xa371155bd2a3a3b6ULL,
+ 0x0c603c186c0c0c30ULL, 0x7bff8af6847b7bf1ULL, 0x35b5e16a803535d4ULL,
+ 0x1de8693af51d1d74ULL, 0xe05347ddb3e0e0a7ULL, 0xd7f6acb321d7d77bULL,
+ 0xc25eed999cc2c22fULL, 0x2e6d965c432e2eb8ULL, 0x4b627a96294b4b31ULL,
+ 0xfea321e15dfefedfULL, 0x578216aed5575741ULL, 0x15a8412abd151554ULL,
+ 0x779fb6eee87777c1ULL, 0x37a5eb6e923737dcULL, 0xe57b56d79ee5e5b3ULL,
+ 0x9f8cd923139f9f46ULL, 0xf0d317fd23f0f0e7ULL, 0x4a6a7f94204a4a35ULL,
+ 0xda9e95a944dada4fULL, 0x58fa25b0a258587dULL, 0xc906ca8fcfc9c903ULL,
+ 0x29558d527c2929a4ULL, 0x0a5022145a0a0a28ULL, 0xb1e14f7f50b1b1feULL,
+ 0xa0691a5dc9a0a0baULL, 0x6b7fdad6146b6bb1ULL, 0x855cab17d985852eULL,
+ 0xbd8173673cbdbdceULL, 0x5dd234ba8f5d5d69ULL, 0x1080502090101040ULL,
+ 0xf4f303f507f4f4f7ULL, 0xcb16c08bddcbcb0bULL, 0x3eedc67cd33e3ef8ULL,
+ 0x0528110a2d050514ULL, 0x671fe6ce78676781ULL, 0xe47353d597e4e4b7ULL,
+ 0x2725bb4e0227279cULL, 0x4132588273414119ULL, 0x8b2c9d0ba78b8b16ULL,
+ 0xa7510153f6a7a7a6ULL, 0x7dcf94fab27d7de9ULL, 0x95dcfb374995956eULL,
+ 0xd88e9fad56d8d847ULL, 0xfb8b30eb70fbfbcbULL, 0xee2371c1cdeeee9fULL,
+ 0x7cc791f8bb7c7cedULL, 0x6617e3cc71666685ULL, 0xdda68ea77bdddd53ULL,
+ 0x17b84b2eaf17175cULL, 0x4702468e45474701ULL, 0x9e84dc211a9e9e42ULL,
+ 0xca1ec589d4caca0fULL, 0x2d75995a582d2db4ULL, 0xbf9179632ebfbfc6ULL,
+ 0x07381b0e3f07071cULL, 0xad012347acadad8eULL, 0x5aea2fb4b05a5a75ULL,
+ 0x836cb51bef838336ULL, 0x3385ff66b63333ccULL, 0x633ff2c65c636391ULL,
+ 0x02100a0412020208ULL, 0xaa39384993aaaa92ULL, 0x71afa8e2de7171d9ULL,
+ 0xc80ecf8dc6c8c807ULL, 0x19c87d32d1191964ULL, 0x497270923b494939ULL,
+ 0xd9869aaf5fd9d943ULL, 0xf2c31df931f2f2efULL, 0xe34b48dba8e3e3abULL,
+ 0x5be22ab6b95b5b71ULL, 0x8834920dbc88881aULL, 0x9aa4c8293e9a9a52ULL,
+ 0x262dbe4c0b262698ULL, 0x328dfa64bf3232c8ULL, 0xb0e94a7d59b0b0faULL,
+ 0xe91b6acff2e9e983ULL, 0x0f78331e770f0f3cULL, 0xd5e6a6b733d5d573ULL,
+ 0x8074ba1df480803aULL, 0xbe997c6127bebec2ULL, 0xcd26de87ebcdcd13ULL,
+ 0x34bde468893434d0ULL, 0x487a75903248483dULL, 0xffab24e354ffffdbULL,
+ 0x7af78ff48d7a7af5ULL, 0x90f4ea3d6490907aULL, 0x5fc23ebe9d5f5f61ULL,
+ 0x201da0403d202080ULL, 0x6867d5d00f6868bdULL, 0x1ad07234ca1a1a68ULL,
+ 0xae192c41b7aeae82ULL, 0xb4c95e757db4b4eaULL, 0x549a19a8ce54544dULL,
+ 0x93ece53b7f939376ULL, 0x220daa442f222288ULL, 0x6407e9c86364648dULL,
+ 0xf1db12ff2af1f1e3ULL, 0x73bfa2e6cc7373d1ULL, 0x12905a2482121248ULL,
+ 0x403a5d807a40401dULL, 0x0840281048080820ULL, 0xc356e89b95c3c32bULL,
+ 0xec337bc5dfecec97ULL, 0xdb9690ab4ddbdb4bULL, 0xa1611f5fc0a1a1beULL,
+ 0x8d1c8307918d8d0eULL, 0x3df5c97ac83d3df4ULL, 0x97ccf1335b979766ULL,
+ 0x0000000000000000ULL, 0xcf36d483f9cfcf1bULL, 0x2b4587566e2b2bacULL,
+ 0x7697b3ece17676c5ULL, 0x8264b019e6828232ULL, 0xd6fea9b128d6d67fULL,
+ 0x1bd87736c31b1b6cULL, 0xb5c15b7774b5b5eeULL, 0xaf112943beafaf86ULL,
+ 0x6a77dfd41d6a6ab5ULL, 0x50ba0da0ea50505dULL, 0x45124c8a57454509ULL,
+ 0xf3cb18fb38f3f3ebULL, 0x309df060ad3030c0ULL, 0xef2b74c3c4efef9bULL,
+ 0x3fe5c37eda3f3ffcULL, 0x55921caac7555549ULL, 0xa2791059dba2a2b2ULL,
+ 0xea0365c9e9eaea8fULL, 0x650fecca6a656589ULL, 0xbab9686903babad2ULL,
+ 0x2f65935e4a2f2fbcULL, 0xc04ee79d8ec0c027ULL, 0xdebe81a160dede5fULL,
+ 0x1ce06c38fc1c1c70ULL, 0xfdbb2ee746fdfdd3ULL, 0x4d52649a1f4d4d29ULL,
+ 0x92e4e03976929272ULL, 0x758fbceafa7575c9ULL, 0x06301e0c36060618ULL,
+ 0x8a249809ae8a8a12ULL, 0xb2f940794bb2b2f2ULL, 0xe66359d185e6e6bfULL,
+ 0x0e70361c7e0e0e38ULL, 0x1ff8633ee71f1f7cULL, 0x6237f7c455626295ULL,
+ 0xd4eea3b53ad4d477ULL, 0xa829324d81a8a89aULL, 0x96c4f43152969662ULL,
+ 0xf99b3aef62f9f9c3ULL, 0xc566f697a3c5c533ULL, 0x2535b14a10252594ULL,
+ 0x59f220b2ab595979ULL, 0x8454ae15d084842aULL, 0x72b7a7e4c57272d5ULL,
+ 0x39d5dd72ec3939e4ULL, 0x4c5a6198164c4c2dULL, 0x5eca3bbc945e5e65ULL,
+ 0x78e785f09f7878fdULL, 0x38ddd870e53838e0ULL, 0x8c148605988c8c0aULL,
+ 0xd1c6b2bf17d1d163ULL, 0xa5410b57e4a5a5aeULL, 0xe2434dd9a1e2e2afULL,
+ 0x612ff8c24e616199ULL, 0xb3f1457b42b3b3f6ULL, 0x2115a54234212184ULL,
+ 0x9c94d625089c9c4aULL, 0x1ef0663cee1e1e78ULL, 0x4322528661434311ULL,
+ 0xc776fc93b1c7c73bULL, 0xfcb32be54ffcfcd7ULL, 0x0420140824040410ULL,
+ 0x51b208a2e3515159ULL, 0x99bcc72f2599995eULL, 0x6d4fc4da226d6da9ULL,
+ 0x0d68391a650d0d34ULL, 0xfa8335e979fafacfULL, 0xdfb684a369dfdf5bULL,
+ 0x7ed79bfca97e7ee5ULL, 0x243db44819242490ULL, 0x3bc5d776fe3b3becULL,
+ 0xab313d4b9aabab96ULL, 0xce3ed181f0cece1fULL, 0x1188552299111144ULL,
+ 0x8f0c8903838f8f06ULL, 0x4e4a6b9c044e4e25ULL, 0xb7d1517366b7b7e6ULL,
+ 0xeb0b60cbe0ebeb8bULL, 0x3cfdcc78c13c3cf0ULL, 0x817cbf1ffd81813eULL,
+ 0x94d4fe354094946aULL, 0xf7eb0cf31cf7f7fbULL, 0xb9a1676f18b9b9deULL,
+ 0x13985f268b13134cULL, 0x2c7d9c58512c2cb0ULL, 0xd3d6b8bb05d3d36bULL,
+ 0xe76b5cd38ce7e7bbULL, 0x6e57cbdc396e6ea5ULL, 0xc46ef395aac4c437ULL,
+ 0x03180f061b03030cULL, 0x568a13acdc565645ULL, 0x441a49885e44440dULL,
+ 0x7fdf9efea07f7fe1ULL, 0xa921374f88a9a99eULL, 0x2a4d8254672a2aa8ULL,
+ 0xbbb16d6b0abbbbd6ULL, 0xc146e29f87c1c123ULL, 0x53a202a6f1535351ULL,
+ 0xdcae8ba572dcdc57ULL, 0x0b582716530b0b2cULL, 0x9d9cd327019d9d4eULL,
+ 0x6c47c1d82b6c6cadULL, 0x3195f562a43131c4ULL, 0x7487b9e8f37474cdULL,
+ 0xf6e309f115f6f6ffULL, 0x460a438c4c464605ULL, 0xac092645a5acac8aULL,
+ 0x893c970fb589891eULL, 0x14a04428b4141450ULL, 0xe15b42dfbae1e1a3ULL,
+ 0x16b04e2ca6161658ULL, 0x3acdd274f73a3ae8ULL, 0x696fd0d2066969b9ULL,
+ 0x09482d1241090924ULL, 0x70a7ade0d77070ddULL, 0xb6d954716fb6b6e2ULL,
+ 0xd0ceb7bd1ed0d067ULL, 0xed3b7ec7d6eded93ULL, 0xcc2edb85e2cccc17ULL,
+ 0x422a578468424215ULL, 0x98b4c22d2c98985aULL, 0xa4490e55eda4a4aaULL,
+ 0x285d8850752828a0ULL, 0x5cda31b8865c5c6dULL, 0xf8933fed6bf8f8c7ULL,
+ 0x8644a411c2868622ULL,
+};
+
+static const u64 C6[256] = {
+ 0x6018c07830d81818ULL, 0x8c2305af46262323ULL, 0x3fc67ef991b8c6c6ULL,
+ 0x87e8136fcdfbe8e8ULL, 0x26874ca113cb8787ULL, 0xdab8a9626d11b8b8ULL,
+ 0x0401080502090101ULL, 0x214f426e9e0d4f4fULL, 0xd836adee6c9b3636ULL,
+ 0xa2a6590451ffa6a6ULL, 0x6fd2debdb90cd2d2ULL, 0xf3f5fb06f70ef5f5ULL,
+ 0xf979ef80f2967979ULL, 0xa16f5fcede306f6fULL, 0x7e91fcef3f6d9191ULL,
+ 0x5552aa07a4f85252ULL, 0x9d6027fdc0476060ULL, 0xcabc89766535bcbcULL,
+ 0x569baccd2b379b9bULL, 0x028e048c018a8e8eULL, 0xb6a371155bd2a3a3ULL,
+ 0x300c603c186c0c0cULL, 0xf17bff8af6847b7bULL, 0xd435b5e16a803535ULL,
+ 0x741de8693af51d1dULL, 0xa7e05347ddb3e0e0ULL, 0x7bd7f6acb321d7d7ULL,
+ 0x2fc25eed999cc2c2ULL, 0xb82e6d965c432e2eULL, 0x314b627a96294b4bULL,
+ 0xdffea321e15dfefeULL, 0x41578216aed55757ULL, 0x5415a8412abd1515ULL,
+ 0xc1779fb6eee87777ULL, 0xdc37a5eb6e923737ULL, 0xb3e57b56d79ee5e5ULL,
+ 0x469f8cd923139f9fULL, 0xe7f0d317fd23f0f0ULL, 0x354a6a7f94204a4aULL,
+ 0x4fda9e95a944dadaULL, 0x7d58fa25b0a25858ULL, 0x03c906ca8fcfc9c9ULL,
+ 0xa429558d527c2929ULL, 0x280a5022145a0a0aULL, 0xfeb1e14f7f50b1b1ULL,
+ 0xbaa0691a5dc9a0a0ULL, 0xb16b7fdad6146b6bULL, 0x2e855cab17d98585ULL,
+ 0xcebd8173673cbdbdULL, 0x695dd234ba8f5d5dULL, 0x4010805020901010ULL,
+ 0xf7f4f303f507f4f4ULL, 0x0bcb16c08bddcbcbULL, 0xf83eedc67cd33e3eULL,
+ 0x140528110a2d0505ULL, 0x81671fe6ce786767ULL, 0xb7e47353d597e4e4ULL,
+ 0x9c2725bb4e022727ULL, 0x1941325882734141ULL, 0x168b2c9d0ba78b8bULL,
+ 0xa6a7510153f6a7a7ULL, 0xe97dcf94fab27d7dULL, 0x6e95dcfb37499595ULL,
+ 0x47d88e9fad56d8d8ULL, 0xcbfb8b30eb70fbfbULL, 0x9fee2371c1cdeeeeULL,
+ 0xed7cc791f8bb7c7cULL, 0x856617e3cc716666ULL, 0x53dda68ea77bddddULL,
+ 0x5c17b84b2eaf1717ULL, 0x014702468e454747ULL, 0x429e84dc211a9e9eULL,
+ 0x0fca1ec589d4cacaULL, 0xb42d75995a582d2dULL, 0xc6bf9179632ebfbfULL,
+ 0x1c07381b0e3f0707ULL, 0x8ead012347acadadULL, 0x755aea2fb4b05a5aULL,
+ 0x36836cb51bef8383ULL, 0xcc3385ff66b63333ULL, 0x91633ff2c65c6363ULL,
+ 0x0802100a04120202ULL, 0x92aa39384993aaaaULL, 0xd971afa8e2de7171ULL,
+ 0x07c80ecf8dc6c8c8ULL, 0x6419c87d32d11919ULL, 0x39497270923b4949ULL,
+ 0x43d9869aaf5fd9d9ULL, 0xeff2c31df931f2f2ULL, 0xabe34b48dba8e3e3ULL,
+ 0x715be22ab6b95b5bULL, 0x1a8834920dbc8888ULL, 0x529aa4c8293e9a9aULL,
+ 0x98262dbe4c0b2626ULL, 0xc8328dfa64bf3232ULL, 0xfab0e94a7d59b0b0ULL,
+ 0x83e91b6acff2e9e9ULL, 0x3c0f78331e770f0fULL, 0x73d5e6a6b733d5d5ULL,
+ 0x3a8074ba1df48080ULL, 0xc2be997c6127bebeULL, 0x13cd26de87ebcdcdULL,
+ 0xd034bde468893434ULL, 0x3d487a7590324848ULL, 0xdbffab24e354ffffULL,
+ 0xf57af78ff48d7a7aULL, 0x7a90f4ea3d649090ULL, 0x615fc23ebe9d5f5fULL,
+ 0x80201da0403d2020ULL, 0xbd6867d5d00f6868ULL, 0x681ad07234ca1a1aULL,
+ 0x82ae192c41b7aeaeULL, 0xeab4c95e757db4b4ULL, 0x4d549a19a8ce5454ULL,
+ 0x7693ece53b7f9393ULL, 0x88220daa442f2222ULL, 0x8d6407e9c8636464ULL,
+ 0xe3f1db12ff2af1f1ULL, 0xd173bfa2e6cc7373ULL, 0x4812905a24821212ULL,
+ 0x1d403a5d807a4040ULL, 0x2008402810480808ULL, 0x2bc356e89b95c3c3ULL,
+ 0x97ec337bc5dfececULL, 0x4bdb9690ab4ddbdbULL, 0xbea1611f5fc0a1a1ULL,
+ 0x0e8d1c8307918d8dULL, 0xf43df5c97ac83d3dULL, 0x6697ccf1335b9797ULL,
+ 0x0000000000000000ULL, 0x1bcf36d483f9cfcfULL, 0xac2b4587566e2b2bULL,
+ 0xc57697b3ece17676ULL, 0x328264b019e68282ULL, 0x7fd6fea9b128d6d6ULL,
+ 0x6c1bd87736c31b1bULL, 0xeeb5c15b7774b5b5ULL, 0x86af112943beafafULL,
+ 0xb56a77dfd41d6a6aULL, 0x5d50ba0da0ea5050ULL, 0x0945124c8a574545ULL,
+ 0xebf3cb18fb38f3f3ULL, 0xc0309df060ad3030ULL, 0x9bef2b74c3c4efefULL,
+ 0xfc3fe5c37eda3f3fULL, 0x4955921caac75555ULL, 0xb2a2791059dba2a2ULL,
+ 0x8fea0365c9e9eaeaULL, 0x89650fecca6a6565ULL, 0xd2bab9686903babaULL,
+ 0xbc2f65935e4a2f2fULL, 0x27c04ee79d8ec0c0ULL, 0x5fdebe81a160dedeULL,
+ 0x701ce06c38fc1c1cULL, 0xd3fdbb2ee746fdfdULL, 0x294d52649a1f4d4dULL,
+ 0x7292e4e039769292ULL, 0xc9758fbceafa7575ULL, 0x1806301e0c360606ULL,
+ 0x128a249809ae8a8aULL, 0xf2b2f940794bb2b2ULL, 0xbfe66359d185e6e6ULL,
+ 0x380e70361c7e0e0eULL, 0x7c1ff8633ee71f1fULL, 0x956237f7c4556262ULL,
+ 0x77d4eea3b53ad4d4ULL, 0x9aa829324d81a8a8ULL, 0x6296c4f431529696ULL,
+ 0xc3f99b3aef62f9f9ULL, 0x33c566f697a3c5c5ULL, 0x942535b14a102525ULL,
+ 0x7959f220b2ab5959ULL, 0x2a8454ae15d08484ULL, 0xd572b7a7e4c57272ULL,
+ 0xe439d5dd72ec3939ULL, 0x2d4c5a6198164c4cULL, 0x655eca3bbc945e5eULL,
+ 0xfd78e785f09f7878ULL, 0xe038ddd870e53838ULL, 0x0a8c148605988c8cULL,
+ 0x63d1c6b2bf17d1d1ULL, 0xaea5410b57e4a5a5ULL, 0xafe2434dd9a1e2e2ULL,
+ 0x99612ff8c24e6161ULL, 0xf6b3f1457b42b3b3ULL, 0x842115a542342121ULL,
+ 0x4a9c94d625089c9cULL, 0x781ef0663cee1e1eULL, 0x1143225286614343ULL,
+ 0x3bc776fc93b1c7c7ULL, 0xd7fcb32be54ffcfcULL, 0x1004201408240404ULL,
+ 0x5951b208a2e35151ULL, 0x5e99bcc72f259999ULL, 0xa96d4fc4da226d6dULL,
+ 0x340d68391a650d0dULL, 0xcffa8335e979fafaULL, 0x5bdfb684a369dfdfULL,
+ 0xe57ed79bfca97e7eULL, 0x90243db448192424ULL, 0xec3bc5d776fe3b3bULL,
+ 0x96ab313d4b9aababULL, 0x1fce3ed181f0ceceULL, 0x4411885522991111ULL,
+ 0x068f0c8903838f8fULL, 0x254e4a6b9c044e4eULL, 0xe6b7d1517366b7b7ULL,
+ 0x8beb0b60cbe0ebebULL, 0xf03cfdcc78c13c3cULL, 0x3e817cbf1ffd8181ULL,
+ 0x6a94d4fe35409494ULL, 0xfbf7eb0cf31cf7f7ULL, 0xdeb9a1676f18b9b9ULL,
+ 0x4c13985f268b1313ULL, 0xb02c7d9c58512c2cULL, 0x6bd3d6b8bb05d3d3ULL,
+ 0xbbe76b5cd38ce7e7ULL, 0xa56e57cbdc396e6eULL, 0x37c46ef395aac4c4ULL,
+ 0x0c03180f061b0303ULL, 0x45568a13acdc5656ULL, 0x0d441a49885e4444ULL,
+ 0xe17fdf9efea07f7fULL, 0x9ea921374f88a9a9ULL, 0xa82a4d8254672a2aULL,
+ 0xd6bbb16d6b0abbbbULL, 0x23c146e29f87c1c1ULL, 0x5153a202a6f15353ULL,
+ 0x57dcae8ba572dcdcULL, 0x2c0b582716530b0bULL, 0x4e9d9cd327019d9dULL,
+ 0xad6c47c1d82b6c6cULL, 0xc43195f562a43131ULL, 0xcd7487b9e8f37474ULL,
+ 0xfff6e309f115f6f6ULL, 0x05460a438c4c4646ULL, 0x8aac092645a5acacULL,
+ 0x1e893c970fb58989ULL, 0x5014a04428b41414ULL, 0xa3e15b42dfbae1e1ULL,
+ 0x5816b04e2ca61616ULL, 0xe83acdd274f73a3aULL, 0xb9696fd0d2066969ULL,
+ 0x2409482d12410909ULL, 0xdd70a7ade0d77070ULL, 0xe2b6d954716fb6b6ULL,
+ 0x67d0ceb7bd1ed0d0ULL, 0x93ed3b7ec7d6ededULL, 0x17cc2edb85e2ccccULL,
+ 0x15422a5784684242ULL, 0x5a98b4c22d2c9898ULL, 0xaaa4490e55eda4a4ULL,
+ 0xa0285d8850752828ULL, 0x6d5cda31b8865c5cULL, 0xc7f8933fed6bf8f8ULL,
+ 0x228644a411c28686ULL,
+};
+
+static const u64 C7[256] = {
+ 0x186018c07830d818ULL, 0x238c2305af462623ULL, 0xc63fc67ef991b8c6ULL,
+ 0xe887e8136fcdfbe8ULL, 0x8726874ca113cb87ULL, 0xb8dab8a9626d11b8ULL,
+ 0x0104010805020901ULL, 0x4f214f426e9e0d4fULL, 0x36d836adee6c9b36ULL,
+ 0xa6a2a6590451ffa6ULL, 0xd26fd2debdb90cd2ULL, 0xf5f3f5fb06f70ef5ULL,
+ 0x79f979ef80f29679ULL, 0x6fa16f5fcede306fULL, 0x917e91fcef3f6d91ULL,
+ 0x525552aa07a4f852ULL, 0x609d6027fdc04760ULL, 0xbccabc89766535bcULL,
+ 0x9b569baccd2b379bULL, 0x8e028e048c018a8eULL, 0xa3b6a371155bd2a3ULL,
+ 0x0c300c603c186c0cULL, 0x7bf17bff8af6847bULL, 0x35d435b5e16a8035ULL,
+ 0x1d741de8693af51dULL, 0xe0a7e05347ddb3e0ULL, 0xd77bd7f6acb321d7ULL,
+ 0xc22fc25eed999cc2ULL, 0x2eb82e6d965c432eULL, 0x4b314b627a96294bULL,
+ 0xfedffea321e15dfeULL, 0x5741578216aed557ULL, 0x155415a8412abd15ULL,
+ 0x77c1779fb6eee877ULL, 0x37dc37a5eb6e9237ULL, 0xe5b3e57b56d79ee5ULL,
+ 0x9f469f8cd923139fULL, 0xf0e7f0d317fd23f0ULL, 0x4a354a6a7f94204aULL,
+ 0xda4fda9e95a944daULL, 0x587d58fa25b0a258ULL, 0xc903c906ca8fcfc9ULL,
+ 0x29a429558d527c29ULL, 0x0a280a5022145a0aULL, 0xb1feb1e14f7f50b1ULL,
+ 0xa0baa0691a5dc9a0ULL, 0x6bb16b7fdad6146bULL, 0x852e855cab17d985ULL,
+ 0xbdcebd8173673cbdULL, 0x5d695dd234ba8f5dULL, 0x1040108050209010ULL,
+ 0xf4f7f4f303f507f4ULL, 0xcb0bcb16c08bddcbULL, 0x3ef83eedc67cd33eULL,
+ 0x05140528110a2d05ULL, 0x6781671fe6ce7867ULL, 0xe4b7e47353d597e4ULL,
+ 0x279c2725bb4e0227ULL, 0x4119413258827341ULL, 0x8b168b2c9d0ba78bULL,
+ 0xa7a6a7510153f6a7ULL, 0x7de97dcf94fab27dULL, 0x956e95dcfb374995ULL,
+ 0xd847d88e9fad56d8ULL, 0xfbcbfb8b30eb70fbULL, 0xee9fee2371c1cdeeULL,
+ 0x7ced7cc791f8bb7cULL, 0x66856617e3cc7166ULL, 0xdd53dda68ea77bddULL,
+ 0x175c17b84b2eaf17ULL, 0x47014702468e4547ULL, 0x9e429e84dc211a9eULL,
+ 0xca0fca1ec589d4caULL, 0x2db42d75995a582dULL, 0xbfc6bf9179632ebfULL,
+ 0x071c07381b0e3f07ULL, 0xad8ead012347acadULL, 0x5a755aea2fb4b05aULL,
+ 0x8336836cb51bef83ULL, 0x33cc3385ff66b633ULL, 0x6391633ff2c65c63ULL,
+ 0x020802100a041202ULL, 0xaa92aa39384993aaULL, 0x71d971afa8e2de71ULL,
+ 0xc807c80ecf8dc6c8ULL, 0x196419c87d32d119ULL, 0x4939497270923b49ULL,
+ 0xd943d9869aaf5fd9ULL, 0xf2eff2c31df931f2ULL, 0xe3abe34b48dba8e3ULL,
+ 0x5b715be22ab6b95bULL, 0x881a8834920dbc88ULL, 0x9a529aa4c8293e9aULL,
+ 0x2698262dbe4c0b26ULL, 0x32c8328dfa64bf32ULL, 0xb0fab0e94a7d59b0ULL,
+ 0xe983e91b6acff2e9ULL, 0x0f3c0f78331e770fULL, 0xd573d5e6a6b733d5ULL,
+ 0x803a8074ba1df480ULL, 0xbec2be997c6127beULL, 0xcd13cd26de87ebcdULL,
+ 0x34d034bde4688934ULL, 0x483d487a75903248ULL, 0xffdbffab24e354ffULL,
+ 0x7af57af78ff48d7aULL, 0x907a90f4ea3d6490ULL, 0x5f615fc23ebe9d5fULL,
+ 0x2080201da0403d20ULL, 0x68bd6867d5d00f68ULL, 0x1a681ad07234ca1aULL,
+ 0xae82ae192c41b7aeULL, 0xb4eab4c95e757db4ULL, 0x544d549a19a8ce54ULL,
+ 0x937693ece53b7f93ULL, 0x2288220daa442f22ULL, 0x648d6407e9c86364ULL,
+ 0xf1e3f1db12ff2af1ULL, 0x73d173bfa2e6cc73ULL, 0x124812905a248212ULL,
+ 0x401d403a5d807a40ULL, 0x0820084028104808ULL, 0xc32bc356e89b95c3ULL,
+ 0xec97ec337bc5dfecULL, 0xdb4bdb9690ab4ddbULL, 0xa1bea1611f5fc0a1ULL,
+ 0x8d0e8d1c8307918dULL, 0x3df43df5c97ac83dULL, 0x976697ccf1335b97ULL,
+ 0x0000000000000000ULL, 0xcf1bcf36d483f9cfULL, 0x2bac2b4587566e2bULL,
+ 0x76c57697b3ece176ULL, 0x82328264b019e682ULL, 0xd67fd6fea9b128d6ULL,
+ 0x1b6c1bd87736c31bULL, 0xb5eeb5c15b7774b5ULL, 0xaf86af112943beafULL,
+ 0x6ab56a77dfd41d6aULL, 0x505d50ba0da0ea50ULL, 0x450945124c8a5745ULL,
+ 0xf3ebf3cb18fb38f3ULL, 0x30c0309df060ad30ULL, 0xef9bef2b74c3c4efULL,
+ 0x3ffc3fe5c37eda3fULL, 0x554955921caac755ULL, 0xa2b2a2791059dba2ULL,
+ 0xea8fea0365c9e9eaULL, 0x6589650fecca6a65ULL, 0xbad2bab9686903baULL,
+ 0x2fbc2f65935e4a2fULL, 0xc027c04ee79d8ec0ULL, 0xde5fdebe81a160deULL,
+ 0x1c701ce06c38fc1cULL, 0xfdd3fdbb2ee746fdULL, 0x4d294d52649a1f4dULL,
+ 0x927292e4e0397692ULL, 0x75c9758fbceafa75ULL, 0x061806301e0c3606ULL,
+ 0x8a128a249809ae8aULL, 0xb2f2b2f940794bb2ULL, 0xe6bfe66359d185e6ULL,
+ 0x0e380e70361c7e0eULL, 0x1f7c1ff8633ee71fULL, 0x62956237f7c45562ULL,
+ 0xd477d4eea3b53ad4ULL, 0xa89aa829324d81a8ULL, 0x966296c4f4315296ULL,
+ 0xf9c3f99b3aef62f9ULL, 0xc533c566f697a3c5ULL, 0x25942535b14a1025ULL,
+ 0x597959f220b2ab59ULL, 0x842a8454ae15d084ULL, 0x72d572b7a7e4c572ULL,
+ 0x39e439d5dd72ec39ULL, 0x4c2d4c5a6198164cULL, 0x5e655eca3bbc945eULL,
+ 0x78fd78e785f09f78ULL, 0x38e038ddd870e538ULL, 0x8c0a8c148605988cULL,
+ 0xd163d1c6b2bf17d1ULL, 0xa5aea5410b57e4a5ULL, 0xe2afe2434dd9a1e2ULL,
+ 0x6199612ff8c24e61ULL, 0xb3f6b3f1457b42b3ULL, 0x21842115a5423421ULL,
+ 0x9c4a9c94d625089cULL, 0x1e781ef0663cee1eULL, 0x4311432252866143ULL,
+ 0xc73bc776fc93b1c7ULL, 0xfcd7fcb32be54ffcULL, 0x0410042014082404ULL,
+ 0x515951b208a2e351ULL, 0x995e99bcc72f2599ULL, 0x6da96d4fc4da226dULL,
+ 0x0d340d68391a650dULL, 0xfacffa8335e979faULL, 0xdf5bdfb684a369dfULL,
+ 0x7ee57ed79bfca97eULL, 0x2490243db4481924ULL, 0x3bec3bc5d776fe3bULL,
+ 0xab96ab313d4b9aabULL, 0xce1fce3ed181f0ceULL, 0x1144118855229911ULL,
+ 0x8f068f0c8903838fULL, 0x4e254e4a6b9c044eULL, 0xb7e6b7d1517366b7ULL,
+ 0xeb8beb0b60cbe0ebULL, 0x3cf03cfdcc78c13cULL, 0x813e817cbf1ffd81ULL,
+ 0x946a94d4fe354094ULL, 0xf7fbf7eb0cf31cf7ULL, 0xb9deb9a1676f18b9ULL,
+ 0x134c13985f268b13ULL, 0x2cb02c7d9c58512cULL, 0xd36bd3d6b8bb05d3ULL,
+ 0xe7bbe76b5cd38ce7ULL, 0x6ea56e57cbdc396eULL, 0xc437c46ef395aac4ULL,
+ 0x030c03180f061b03ULL, 0x5645568a13acdc56ULL, 0x440d441a49885e44ULL,
+ 0x7fe17fdf9efea07fULL, 0xa99ea921374f88a9ULL, 0x2aa82a4d8254672aULL,
+ 0xbbd6bbb16d6b0abbULL, 0xc123c146e29f87c1ULL, 0x535153a202a6f153ULL,
+ 0xdc57dcae8ba572dcULL, 0x0b2c0b582716530bULL, 0x9d4e9d9cd327019dULL,
+ 0x6cad6c47c1d82b6cULL, 0x31c43195f562a431ULL, 0x74cd7487b9e8f374ULL,
+ 0xf6fff6e309f115f6ULL, 0x4605460a438c4c46ULL, 0xac8aac092645a5acULL,
+ 0x891e893c970fb589ULL, 0x145014a04428b414ULL, 0xe1a3e15b42dfbae1ULL,
+ 0x165816b04e2ca616ULL, 0x3ae83acdd274f73aULL, 0x69b9696fd0d20669ULL,
+ 0x092409482d124109ULL, 0x70dd70a7ade0d770ULL, 0xb6e2b6d954716fb6ULL,
+ 0xd067d0ceb7bd1ed0ULL, 0xed93ed3b7ec7d6edULL, 0xcc17cc2edb85e2ccULL,
+ 0x4215422a57846842ULL, 0x985a98b4c22d2c98ULL, 0xa4aaa4490e55eda4ULL,
+ 0x28a0285d88507528ULL, 0x5c6d5cda31b8865cULL, 0xf8c7f8933fed6bf8ULL,
+ 0x86228644a411c286ULL,
+};
+
+static const u64 rc[WHIRLPOOL_ROUNDS + 1] = {
+ 0x0000000000000000ULL, 0x1823c6e887b8014fULL, 0x36a6d2f5796f9152ULL,
+ 0x60bc9b8ea30c7b35ULL, 0x1de0d7c22e4bfe57ULL, 0x157737e59ff04adaULL,
+ 0x58c9290ab1a06b85ULL, 0xbd5d10f4cb3e0567ULL, 0xe427418ba77d95d8ULL,
+ 0xfbee7c66dd17479eULL, 0xca2dbf07ad5a8333ULL,
+};
+
+/**
+ * The core Whirlpool transform.
+ */
+
+static void wp512_process_buffer(struct wp512_ctx *wctx) {
+ int i, r;
+ u64 K[8]; /* the round key */
+ u64 block[8]; /* mu(buffer) */
+ u64 state[8]; /* the cipher state */
+ u64 L[8];
+ u8 *buffer = wctx->buffer;
+
+ for (i = 0; i < 8; i++, buffer += 8) {
+ block[i] =
+ (((u64)buffer[0] ) << 56) ^
+ (((u64)buffer[1] & 0xffL) << 48) ^
+ (((u64)buffer[2] & 0xffL) << 40) ^
+ (((u64)buffer[3] & 0xffL) << 32) ^
+ (((u64)buffer[4] & 0xffL) << 24) ^
+ (((u64)buffer[5] & 0xffL) << 16) ^
+ (((u64)buffer[6] & 0xffL) << 8) ^
+ (((u64)buffer[7] & 0xffL) );
+ }
+
+ state[0] = block[0] ^ (K[0] = wctx->hash[0]);
+ state[1] = block[1] ^ (K[1] = wctx->hash[1]);
+ state[2] = block[2] ^ (K[2] = wctx->hash[2]);
+ state[3] = block[3] ^ (K[3] = wctx->hash[3]);
+ state[4] = block[4] ^ (K[4] = wctx->hash[4]);
+ state[5] = block[5] ^ (K[5] = wctx->hash[5]);
+ state[6] = block[6] ^ (K[6] = wctx->hash[6]);
+ state[7] = block[7] ^ (K[7] = wctx->hash[7]);
+
+ for (r = 1; r <= WHIRLPOOL_ROUNDS; r++) {
+
+ L[0] = C0[(int)(K[0] >> 56) ] ^
+ C1[(int)(K[7] >> 48) & 0xff] ^
+ C2[(int)(K[6] >> 40) & 0xff] ^
+ C3[(int)(K[5] >> 32) & 0xff] ^
+ C4[(int)(K[4] >> 24) & 0xff] ^
+ C5[(int)(K[3] >> 16) & 0xff] ^
+ C6[(int)(K[2] >> 8) & 0xff] ^
+ C7[(int)(K[1] ) & 0xff] ^
+ rc[r];
+
+ L[1] = C0[(int)(K[1] >> 56) ] ^
+ C1[(int)(K[0] >> 48) & 0xff] ^
+ C2[(int)(K[7] >> 40) & 0xff] ^
+ C3[(int)(K[6] >> 32) & 0xff] ^
+ C4[(int)(K[5] >> 24) & 0xff] ^
+ C5[(int)(K[4] >> 16) & 0xff] ^
+ C6[(int)(K[3] >> 8) & 0xff] ^
+ C7[(int)(K[2] ) & 0xff];
+
+ L[2] = C0[(int)(K[2] >> 56) ] ^
+ C1[(int)(K[1] >> 48) & 0xff] ^
+ C2[(int)(K[0] >> 40) & 0xff] ^
+ C3[(int)(K[7] >> 32) & 0xff] ^
+ C4[(int)(K[6] >> 24) & 0xff] ^
+ C5[(int)(K[5] >> 16) & 0xff] ^
+ C6[(int)(K[4] >> 8) & 0xff] ^
+ C7[(int)(K[3] ) & 0xff];
+
+ L[3] = C0[(int)(K[3] >> 56) ] ^
+ C1[(int)(K[2] >> 48) & 0xff] ^
+ C2[(int)(K[1] >> 40) & 0xff] ^
+ C3[(int)(K[0] >> 32) & 0xff] ^
+ C4[(int)(K[7] >> 24) & 0xff] ^
+ C5[(int)(K[6] >> 16) & 0xff] ^
+ C6[(int)(K[5] >> 8) & 0xff] ^
+ C7[(int)(K[4] ) & 0xff];
+
+ L[4] = C0[(int)(K[4] >> 56) ] ^
+ C1[(int)(K[3] >> 48) & 0xff] ^
+ C2[(int)(K[2] >> 40) & 0xff] ^
+ C3[(int)(K[1] >> 32) & 0xff] ^
+ C4[(int)(K[0] >> 24) & 0xff] ^
+ C5[(int)(K[7] >> 16) & 0xff] ^
+ C6[(int)(K[6] >> 8) & 0xff] ^
+ C7[(int)(K[5] ) & 0xff];
+
+ L[5] = C0[(int)(K[5] >> 56) ] ^
+ C1[(int)(K[4] >> 48) & 0xff] ^
+ C2[(int)(K[3] >> 40) & 0xff] ^
+ C3[(int)(K[2] >> 32) & 0xff] ^
+ C4[(int)(K[1] >> 24) & 0xff] ^
+ C5[(int)(K[0] >> 16) & 0xff] ^
+ C6[(int)(K[7] >> 8) & 0xff] ^
+ C7[(int)(K[6] ) & 0xff];
+
+ L[6] = C0[(int)(K[6] >> 56) ] ^
+ C1[(int)(K[5] >> 48) & 0xff] ^
+ C2[(int)(K[4] >> 40) & 0xff] ^
+ C3[(int)(K[3] >> 32) & 0xff] ^
+ C4[(int)(K[2] >> 24) & 0xff] ^
+ C5[(int)(K[1] >> 16) & 0xff] ^
+ C6[(int)(K[0] >> 8) & 0xff] ^
+ C7[(int)(K[7] ) & 0xff];
+
+ L[7] = C0[(int)(K[7] >> 56) ] ^
+ C1[(int)(K[6] >> 48) & 0xff] ^
+ C2[(int)(K[5] >> 40) & 0xff] ^
+ C3[(int)(K[4] >> 32) & 0xff] ^
+ C4[(int)(K[3] >> 24) & 0xff] ^
+ C5[(int)(K[2] >> 16) & 0xff] ^
+ C6[(int)(K[1] >> 8) & 0xff] ^
+ C7[(int)(K[0] ) & 0xff];
+
+ K[0] = L[0];
+ K[1] = L[1];
+ K[2] = L[2];
+ K[3] = L[3];
+ K[4] = L[4];
+ K[5] = L[5];
+ K[6] = L[6];
+ K[7] = L[7];
+
+ L[0] = C0[(int)(state[0] >> 56) ] ^
+ C1[(int)(state[7] >> 48) & 0xff] ^
+ C2[(int)(state[6] >> 40) & 0xff] ^
+ C3[(int)(state[5] >> 32) & 0xff] ^
+ C4[(int)(state[4] >> 24) & 0xff] ^
+ C5[(int)(state[3] >> 16) & 0xff] ^
+ C6[(int)(state[2] >> 8) & 0xff] ^
+ C7[(int)(state[1] ) & 0xff] ^
+ K[0];
+
+ L[1] = C0[(int)(state[1] >> 56) ] ^
+ C1[(int)(state[0] >> 48) & 0xff] ^
+ C2[(int)(state[7] >> 40) & 0xff] ^
+ C3[(int)(state[6] >> 32) & 0xff] ^
+ C4[(int)(state[5] >> 24) & 0xff] ^
+ C5[(int)(state[4] >> 16) & 0xff] ^
+ C6[(int)(state[3] >> 8) & 0xff] ^
+ C7[(int)(state[2] ) & 0xff] ^
+ K[1];
+
+ L[2] = C0[(int)(state[2] >> 56) ] ^
+ C1[(int)(state[1] >> 48) & 0xff] ^
+ C2[(int)(state[0] >> 40) & 0xff] ^
+ C3[(int)(state[7] >> 32) & 0xff] ^
+ C4[(int)(state[6] >> 24) & 0xff] ^
+ C5[(int)(state[5] >> 16) & 0xff] ^
+ C6[(int)(state[4] >> 8) & 0xff] ^
+ C7[(int)(state[3] ) & 0xff] ^
+ K[2];
+
+ L[3] = C0[(int)(state[3] >> 56) ] ^
+ C1[(int)(state[2] >> 48) & 0xff] ^
+ C2[(int)(state[1] >> 40) & 0xff] ^
+ C3[(int)(state[0] >> 32) & 0xff] ^
+ C4[(int)(state[7] >> 24) & 0xff] ^
+ C5[(int)(state[6] >> 16) & 0xff] ^
+ C6[(int)(state[5] >> 8) & 0xff] ^
+ C7[(int)(state[4] ) & 0xff] ^
+ K[3];
+
+ L[4] = C0[(int)(state[4] >> 56) ] ^
+ C1[(int)(state[3] >> 48) & 0xff] ^
+ C2[(int)(state[2] >> 40) & 0xff] ^
+ C3[(int)(state[1] >> 32) & 0xff] ^
+ C4[(int)(state[0] >> 24) & 0xff] ^
+ C5[(int)(state[7] >> 16) & 0xff] ^
+ C6[(int)(state[6] >> 8) & 0xff] ^
+ C7[(int)(state[5] ) & 0xff] ^
+ K[4];
+
+ L[5] = C0[(int)(state[5] >> 56) ] ^
+ C1[(int)(state[4] >> 48) & 0xff] ^
+ C2[(int)(state[3] >> 40) & 0xff] ^
+ C3[(int)(state[2] >> 32) & 0xff] ^
+ C4[(int)(state[1] >> 24) & 0xff] ^
+ C5[(int)(state[0] >> 16) & 0xff] ^
+ C6[(int)(state[7] >> 8) & 0xff] ^
+ C7[(int)(state[6] ) & 0xff] ^
+ K[5];
+
+ L[6] = C0[(int)(state[6] >> 56) ] ^
+ C1[(int)(state[5] >> 48) & 0xff] ^
+ C2[(int)(state[4] >> 40) & 0xff] ^
+ C3[(int)(state[3] >> 32) & 0xff] ^
+ C4[(int)(state[2] >> 24) & 0xff] ^
+ C5[(int)(state[1] >> 16) & 0xff] ^
+ C6[(int)(state[0] >> 8) & 0xff] ^
+ C7[(int)(state[7] ) & 0xff] ^
+ K[6];
+
+ L[7] = C0[(int)(state[7] >> 56) ] ^
+ C1[(int)(state[6] >> 48) & 0xff] ^
+ C2[(int)(state[5] >> 40) & 0xff] ^
+ C3[(int)(state[4] >> 32) & 0xff] ^
+ C4[(int)(state[3] >> 24) & 0xff] ^
+ C5[(int)(state[2] >> 16) & 0xff] ^
+ C6[(int)(state[1] >> 8) & 0xff] ^
+ C7[(int)(state[0] ) & 0xff] ^
+ K[7];
+
+ state[0] = L[0];
+ state[1] = L[1];
+ state[2] = L[2];
+ state[3] = L[3];
+ state[4] = L[4];
+ state[5] = L[5];
+ state[6] = L[6];
+ state[7] = L[7];
+ }
+ /*
+ * apply the Miyaguchi-Preneel compression function:
+ */
+ wctx->hash[0] ^= state[0] ^ block[0];
+ wctx->hash[1] ^= state[1] ^ block[1];
+ wctx->hash[2] ^= state[2] ^ block[2];
+ wctx->hash[3] ^= state[3] ^ block[3];
+ wctx->hash[4] ^= state[4] ^ block[4];
+ wctx->hash[5] ^= state[5] ^ block[5];
+ wctx->hash[6] ^= state[6] ^ block[6];
+ wctx->hash[7] ^= state[7] ^ block[7];
+
+}
+
+static void wp512_init (void *ctx) {
+ int i;
+ struct wp512_ctx *wctx = ctx;
+
+ memset(wctx->bitLength, 0, 32);
+ wctx->bufferBits = wctx->bufferPos = 0;
+ wctx->buffer[0] = 0;
+ for (i = 0; i < 8; i++) {
+ wctx->hash[i] = 0L;
+ }
+}
+
+static void wp512_update(void *ctx, const u8 *source, unsigned int len)
+{
+
+ struct wp512_ctx *wctx = ctx;
+ int sourcePos = 0;
+ unsigned int bits_len = len * 8; // convert to number of bits
+ int sourceGap = (8 - ((int)bits_len & 7)) & 7;
+ int bufferRem = wctx->bufferBits & 7;
+ int i;
+ u32 b, carry;
+ u8 *buffer = wctx->buffer;
+ u8 *bitLength = wctx->bitLength;
+ int bufferBits = wctx->bufferBits;
+ int bufferPos = wctx->bufferPos;
+
+ u64 value = bits_len;
+ for (i = 31, carry = 0; i >= 0 && (carry != 0 || value != 0ULL); i--) {
+ carry += bitLength[i] + ((u32)value & 0xff);
+ bitLength[i] = (u8)carry;
+ carry >>= 8;
+ value >>= 8;
+ }
+ while (bits_len > 8) {
+ b = ((source[sourcePos] << sourceGap) & 0xff) |
+ ((source[sourcePos + 1] & 0xff) >> (8 - sourceGap));
+ buffer[bufferPos++] |= (u8)(b >> bufferRem);
+ bufferBits += 8 - bufferRem;
+ if (bufferBits == WP512_BLOCK_SIZE * 8) {
+ wp512_process_buffer(wctx);
+ bufferBits = bufferPos = 0;
+ }
+ buffer[bufferPos] = b << (8 - bufferRem);
+ bufferBits += bufferRem;
+ bits_len -= 8;
+ sourcePos++;
+ }
+ if (bits_len > 0) {
+ b = (source[sourcePos] << sourceGap) & 0xff;
+ buffer[bufferPos] |= b >> bufferRem;
+ } else {
+ b = 0;
+ }
+ if (bufferRem + bits_len < 8) {
+ bufferBits += bits_len;
+ } else {
+ bufferPos++;
+ bufferBits += 8 - bufferRem;
+ bits_len -= 8 - bufferRem;
+ if (bufferBits == WP512_BLOCK_SIZE * 8) {
+ wp512_process_buffer(wctx);
+ bufferBits = bufferPos = 0;
+ }
+ buffer[bufferPos] = b << (8 - bufferRem);
+ bufferBits += (int)bits_len;
+ }
+
+ wctx->bufferBits = bufferBits;
+ wctx->bufferPos = bufferPos;
+
+}
+
+static void wp512_final(void *ctx, u8 *out)
+{
+ struct wp512_ctx *wctx = ctx;
+ int i;
+ u8 *buffer = wctx->buffer;
+ u8 *bitLength = wctx->bitLength;
+ int bufferBits = wctx->bufferBits;
+ int bufferPos = wctx->bufferPos;
+ u8 *digest = out;
+
+ buffer[bufferPos] |= 0x80U >> (bufferBits & 7);
+ bufferPos++;
+ if (bufferPos > WP512_BLOCK_SIZE - WP512_LENGTHBYTES) {
+ if (bufferPos < WP512_BLOCK_SIZE) {
+ memset(&buffer[bufferPos], 0, WP512_BLOCK_SIZE - bufferPos);
+ }
+ wp512_process_buffer(wctx);
+ bufferPos = 0;
+ }
+ if (bufferPos < WP512_BLOCK_SIZE - WP512_LENGTHBYTES) {
+ memset(&buffer[bufferPos], 0,
+ (WP512_BLOCK_SIZE - WP512_LENGTHBYTES) - bufferPos);
+ }
+ bufferPos = WP512_BLOCK_SIZE - WP512_LENGTHBYTES;
+ memcpy(&buffer[WP512_BLOCK_SIZE - WP512_LENGTHBYTES],
+ bitLength, WP512_LENGTHBYTES);
+ wp512_process_buffer(wctx);
+ for (i = 0; i < WP512_DIGEST_SIZE/8; i++) {
+ digest[0] = (u8)(wctx->hash[i] >> 56);
+ digest[1] = (u8)(wctx->hash[i] >> 48);
+ digest[2] = (u8)(wctx->hash[i] >> 40);
+ digest[3] = (u8)(wctx->hash[i] >> 32);
+ digest[4] = (u8)(wctx->hash[i] >> 24);
+ digest[5] = (u8)(wctx->hash[i] >> 16);
+ digest[6] = (u8)(wctx->hash[i] >> 8);
+ digest[7] = (u8)(wctx->hash[i] );
+ digest += 8;
+ }
+ wctx->bufferBits = bufferBits;
+ wctx->bufferPos = bufferPos;
+}
+
+static void wp384_final(void *ctx, u8 *out)
+{
+ struct wp512_ctx *wctx = ctx;
+ u8 D[64];
+
+ wp512_final (wctx, D);
+ memcpy (out, D, WP384_DIGEST_SIZE);
+ memset (D, 0, WP512_DIGEST_SIZE);
+}
+
+static void wp256_final(void *ctx, u8 *out)
+{
+ struct wp512_ctx *wctx = ctx;
+ u8 D[64];
+
+ wp512_final (wctx, D);
+ memcpy (out, D, WP256_DIGEST_SIZE);
+ memset (D, 0, WP512_DIGEST_SIZE);
+}
+
+static struct crypto_alg wp512 = {
+ .cra_name = "wp512",
+ .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
+ .cra_blocksize = WP512_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct wp512_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_list = LIST_HEAD_INIT(wp512.cra_list),
+ .cra_u = { .digest = {
+ .dia_digestsize = WP512_DIGEST_SIZE,
+ .dia_init = wp512_init,
+ .dia_update = wp512_update,
+ .dia_final = wp512_final } }
+};
+
+static struct crypto_alg wp384 = {
+ .cra_name = "wp384",
+ .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
+ .cra_blocksize = WP512_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct wp512_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_list = LIST_HEAD_INIT(wp384.cra_list),
+ .cra_u = { .digest = {
+ .dia_digestsize = WP384_DIGEST_SIZE,
+ .dia_init = wp512_init,
+ .dia_update = wp512_update,
+ .dia_final = wp384_final } }
+};
+
+static struct crypto_alg wp256 = {
+ .cra_name = "wp256",
+ .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
+ .cra_blocksize = WP512_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct wp512_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_list = LIST_HEAD_INIT(wp256.cra_list),
+ .cra_u = { .digest = {
+ .dia_digestsize = WP256_DIGEST_SIZE,
+ .dia_init = wp512_init,
+ .dia_update = wp512_update,
+ .dia_final = wp256_final } }
+};
+
+static int __init init(void)
+{
+ int ret = 0;
+
+ ret = crypto_register_alg(&wp512);
+
+ if (ret < 0)
+ goto out;
+
+ ret = crypto_register_alg(&wp384);
+ if (ret < 0)
+ {
+ crypto_unregister_alg(&wp512);
+ goto out;
+ }
+
+ ret = crypto_register_alg(&wp256);
+ if (ret < 0)
+ {
+ crypto_unregister_alg(&wp512);
+ crypto_unregister_alg(&wp384);
+ }
+out:
+ return ret;
+}
+
+static void __exit fini(void)
+{
+ crypto_unregister_alg(&wp512);
+ crypto_unregister_alg(&wp384);
+ crypto_unregister_alg(&wp256);
+}
+
+MODULE_ALIAS("wp384");
+MODULE_ALIAS("wp256");
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Whirlpool Message Digest Algorithm");
--- /dev/null
+/*
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+/* Purpose: Prevent PCMCIA cards from using motherboard resources. */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <asm/io.h>
+
+#include <acpi/acpi_bus.h>
+#include <acpi/acpi_drivers.h>
+
+#define _COMPONENT ACPI_SYSTEM_COMPONENT
+ACPI_MODULE_NAME ("acpi_motherboard")
+
+/* Dell use PNP0C01 instead of PNP0C02 */
+#define ACPI_MB_HID1 "PNP0C01"
+#define ACPI_MB_HID2 "PNP0C02"
+
+/**
+ * Doesn't care about legacy IO ports, only IO ports beyond 0x1000 are reserved
+ * Doesn't care about the failure of 'request_region', since other may reserve
+ * the io ports as well
+ */
+#define IS_RESERVED_ADDR(base, len) \
+ (((len) > 0) && ((base) > 0) && ((base) + (len) < IO_SPACE_LIMIT) \
+ && ((base) + (len) > PCIBIOS_MIN_IO))
+
+/*
+ * Clearing the flag (IORESOURCE_BUSY) allows drivers to use
+ * the io ports if they really know they can use it, while
+ * still preventing hotplug PCI devices from using it.
+ */
+
+static acpi_status
+acpi_reserve_io_ranges (struct acpi_resource *res, void *data)
+{
+ struct resource *requested_res = NULL;
+
+ ACPI_FUNCTION_TRACE("acpi_reserve_io_ranges");
+
+ if (res->id == ACPI_RSTYPE_IO) {
+ struct acpi_resource_io *io_res = &res->data.io;
+
+ if (io_res->min_base_address != io_res->max_base_address)
+ return AE_OK;
+ if (IS_RESERVED_ADDR(io_res->min_base_address, io_res->range_length)) {
+ ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Motherboard resources 0x%08x - 0x%08x\n",
+ io_res->min_base_address,
+ io_res->min_base_address + io_res->range_length));
+ requested_res = request_region(io_res->min_base_address,
+ io_res->range_length, "motherboard");
+ }
+ } else if (res->id == ACPI_RSTYPE_FIXED_IO) {
+ struct acpi_resource_fixed_io *fixed_io_res = &res->data.fixed_io;
+
+ if (IS_RESERVED_ADDR(fixed_io_res->base_address, fixed_io_res->range_length)) {
+ ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Motherboard resources 0x%08x - 0x%08x\n",
+ fixed_io_res->base_address,
+ fixed_io_res->base_address + fixed_io_res->range_length));
+ requested_res = request_region(fixed_io_res->base_address,
+ fixed_io_res->range_length, "motherboard");
+ }
+ } else {
+ /* Memory mapped IO? */
+ }
+
+ if (requested_res)
+ requested_res->flags &= ~IORESOURCE_BUSY;
+ return AE_OK;
+}
+
+static int acpi_motherboard_add (struct acpi_device *device)
+{
+ if (!device)
+ return -EINVAL;
+ acpi_walk_resources(device->handle, METHOD_NAME__CRS,
+ acpi_reserve_io_ranges, NULL);
+
+ return 0;
+}
+
+static struct acpi_driver acpi_motherboard_driver1 = {
+ .name = "motherboard",
+ .class = "",
+ .ids = ACPI_MB_HID1,
+ .ops = {
+ .add = acpi_motherboard_add,
+ },
+};
+
+static struct acpi_driver acpi_motherboard_driver2 = {
+ .name = "motherboard",
+ .class = "",
+ .ids = ACPI_MB_HID2,
+ .ops = {
+ .add = acpi_motherboard_add,
+ },
+};
+
+static void __init
+acpi_reserve_resources (void)
+{
+ if (acpi_gbl_FADT->xpm1a_evt_blk.address && acpi_gbl_FADT->pm1_evt_len)
+ request_region(acpi_gbl_FADT->xpm1a_evt_blk.address,
+ acpi_gbl_FADT->pm1_evt_len, "PM1a_EVT_BLK");
+
+ if (acpi_gbl_FADT->xpm1b_evt_blk.address && acpi_gbl_FADT->pm1_evt_len)
+ request_region(acpi_gbl_FADT->xpm1b_evt_blk.address,
+ acpi_gbl_FADT->pm1_evt_len, "PM1b_EVT_BLK");
+
+ if (acpi_gbl_FADT->xpm1a_cnt_blk.address && acpi_gbl_FADT->pm1_cnt_len)
+ request_region(acpi_gbl_FADT->xpm1a_cnt_blk.address,
+ acpi_gbl_FADT->pm1_cnt_len, "PM1a_CNT_BLK");
+
+ if (acpi_gbl_FADT->xpm1b_cnt_blk.address && acpi_gbl_FADT->pm1_cnt_len)
+ request_region(acpi_gbl_FADT->xpm1b_cnt_blk.address,
+ acpi_gbl_FADT->pm1_cnt_len, "PM1b_CNT_BLK");
+
+ if (acpi_gbl_FADT->xpm_tmr_blk.address && acpi_gbl_FADT->pm_tm_len == 4)
+ request_region(acpi_gbl_FADT->xpm_tmr_blk.address,
+ 4, "PM_TMR");
+
+ if (acpi_gbl_FADT->xpm2_cnt_blk.address && acpi_gbl_FADT->pm2_cnt_len)
+ request_region(acpi_gbl_FADT->xpm2_cnt_blk.address,
+ acpi_gbl_FADT->pm2_cnt_len, "PM2_CNT_BLK");
+
+ /* Length of GPE blocks must be a non-negative multiple of 2 */
+
+ if (acpi_gbl_FADT->xgpe0_blk.address && acpi_gbl_FADT->gpe0_blk_len &&
+ !(acpi_gbl_FADT->gpe0_blk_len & 0x1))
+ request_region(acpi_gbl_FADT->xgpe0_blk.address,
+ acpi_gbl_FADT->gpe0_blk_len, "GPE0_BLK");
+
+ if (acpi_gbl_FADT->xgpe1_blk.address && acpi_gbl_FADT->gpe1_blk_len &&
+ !(acpi_gbl_FADT->gpe1_blk_len & 0x1))
+ request_region(acpi_gbl_FADT->xgpe1_blk.address,
+ acpi_gbl_FADT->gpe1_blk_len, "GPE1_BLK");
+}
+
+static int __init acpi_motherboard_init(void)
+{
+ acpi_bus_register_driver(&acpi_motherboard_driver1);
+ acpi_bus_register_driver(&acpi_motherboard_driver2);
+ /*
+ * Guarantee motherboard IO reservation first
+ * This module must run after scan.c
+ */
+ if (!acpi_disabled)
+ acpi_reserve_resources ();
+ return 0;
+}
+
+/**
+ * Reserve motherboard resources after PCI claim BARs,
+ * but before PCI assign resources for uninitialized PCI devices
+ */
+fs_initcall(acpi_motherboard_init);
--- /dev/null
+/*
+ * wakeup.c - support wakeup devices
+ */
+
+#include <linux/init.h>
+#include <linux/acpi.h>
+#include <acpi/acpi_drivers.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <acpi/acevents.h>
+#include "sleep.h"
+
+#define _COMPONENT ACPI_SYSTEM_COMPONENT
+ACPI_MODULE_NAME ("wakeup_devices")
+
+/**
+ * acpi_enable_wakeup_device_prep - prepare wakeup devices
+ * @sleep_state: ACPI state
+ * Enable all wakup devices power if the devices' wakeup level
+ * is higher than requested sleep level
+ */
+extern struct list_head acpi_wakeup_device_list;
+extern spinlock_t acpi_device_lock;
+
+void
+acpi_enable_wakeup_device_prep(
+ u8 sleep_state)
+{
+ struct list_head * node, * next;
+
+ ACPI_FUNCTION_TRACE("acpi_enable_wakeup_device_prep");
+
+ spin_lock(&acpi_device_lock);
+ list_for_each_safe(node, next, &acpi_wakeup_device_list) {
+ struct acpi_device * dev = container_of(node,
+ struct acpi_device, wakeup_list);
+
+ if (!dev->wakeup.flags.valid ||
+ !dev->wakeup.state.enabled ||
+ (sleep_state > (u32) dev->wakeup.sleep_state))
+ continue;
+
+ spin_unlock(&acpi_device_lock);
+ acpi_enable_wakeup_device_power(dev);
+ spin_lock(&acpi_device_lock);
+ }
+ spin_unlock(&acpi_device_lock);
+}
+
+/**
+ * acpi_enable_wakeup_device - enable wakeup devices
+ * @sleep_state: ACPI state
+ * Enable all wakup devices's GPE
+ */
+void
+acpi_enable_wakeup_device(
+ u8 sleep_state)
+{
+ struct list_head * node, * next;
+
+ /*
+ * Caution: this routine must be invoked when interrupt is disabled
+ * Refer ACPI2.0: P212
+ */
+ ACPI_FUNCTION_TRACE("acpi_enable_wakeup_device");
+ spin_lock(&acpi_device_lock);
+ list_for_each_safe(node, next, &acpi_wakeup_device_list) {
+ struct acpi_device * dev = container_of(node,
+ struct acpi_device, wakeup_list);
+
+ /* If users want to disable run-wake GPE,
+ * we only disable it for wake and leave it for runtime
+ */
+ if (dev->wakeup.flags.run_wake && !dev->wakeup.state.enabled) {
+ spin_unlock(&acpi_device_lock);
+ acpi_set_gpe_type(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_GPE_TYPE_RUNTIME);
+ /* Re-enable it, since set_gpe_type will disable it */
+ acpi_enable_gpe(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_ISR);
+ spin_lock(&acpi_device_lock);
+ continue;
+ }
+
+ if (!dev->wakeup.flags.valid ||
+ !dev->wakeup.state.enabled ||
+ (sleep_state > (u32) dev->wakeup.sleep_state))
+ continue;
+
+ spin_unlock(&acpi_device_lock);
+ /* run-wake GPE has been enabled */
+ if (!dev->wakeup.flags.run_wake)
+ acpi_enable_gpe(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_ISR);
+ dev->wakeup.state.active = 1;
+ spin_lock(&acpi_device_lock);
+ }
+ spin_unlock(&acpi_device_lock);
+}
+
+/**
+ * acpi_disable_wakeup_device - disable devices' wakeup capability
+ * @sleep_state: ACPI state
+ * Disable all wakup devices's GPE and wakeup capability
+ */
+void
+acpi_disable_wakeup_device (
+ u8 sleep_state)
+{
+ struct list_head * node, * next;
+
+ ACPI_FUNCTION_TRACE("acpi_disable_wakeup_device");
+
+ spin_lock(&acpi_device_lock);
+ list_for_each_safe(node, next, &acpi_wakeup_device_list) {
+ struct acpi_device * dev = container_of(node,
+ struct acpi_device, wakeup_list);
+
+ if (dev->wakeup.flags.run_wake && !dev->wakeup.state.enabled) {
+ spin_unlock(&acpi_device_lock);
+ acpi_set_gpe_type(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_GPE_TYPE_WAKE_RUN);
+ /* Re-enable it, since set_gpe_type will disable it */
+ acpi_enable_gpe(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_NOT_ISR);
+ spin_lock(&acpi_device_lock);
+ continue;
+ }
+
+ if (!dev->wakeup.flags.valid ||
+ !dev->wakeup.state.active ||
+ (sleep_state > (u32) dev->wakeup.sleep_state))
+ continue;
+
+ spin_unlock(&acpi_device_lock);
+ acpi_disable_wakeup_device_power(dev);
+ /* Never disable run-wake GPE */
+ if (!dev->wakeup.flags.run_wake) {
+ acpi_disable_gpe(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_NOT_ISR);
+ acpi_clear_gpe(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_NOT_ISR);
+ }
+ dev->wakeup.state.active = 0;
+ spin_lock(&acpi_device_lock);
+ }
+ spin_unlock(&acpi_device_lock);
+}
+
+static int __init acpi_wakeup_device_init(void)
+{
+ struct list_head * node, * next;
+
+ if (acpi_disabled)
+ return 0;
+ printk("ACPI wakeup devices: \n");
+
+ spin_lock(&acpi_device_lock);
+ list_for_each_safe(node, next, &acpi_wakeup_device_list) {
+ struct acpi_device * dev = container_of(node,
+ struct acpi_device, wakeup_list);
+
+ /* In case user doesn't load button driver */
+ if (dev->wakeup.flags.run_wake && !dev->wakeup.state.enabled) {
+ spin_unlock(&acpi_device_lock);
+ acpi_set_gpe_type(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_GPE_TYPE_WAKE_RUN);
+ acpi_enable_gpe(dev->wakeup.gpe_device,
+ dev->wakeup.gpe_number, ACPI_NOT_ISR);
+ dev->wakeup.state.enabled = 1;
+ spin_lock(&acpi_device_lock);
+ }
+ printk("%4s ", dev->pnp.bus_id);
+ }
+ spin_unlock(&acpi_device_lock);
+ printk("\n");
+
+ return 0;
+}
+
+late_initcall(acpi_wakeup_device_init);
--- /dev/null
+/*
+ * The low performance USB storage driver (ub).
+ *
+ * Copyright (c) 1999, 2000 Matthew Dharm (mdharm-usb@one-eyed-alien.net)
+ * Copyright (C) 2004 Pete Zaitcev (zaitcev@yahoo.com)
+ *
+ * This work is a part of Linux kernel, is derived from it,
+ * and is not licensed separately. See file COPYING for details.
+ *
+ * TODO (sorted by decreasing priority)
+ * -- ZIP does "ub: resid 18 len 0 act 0" and whole transport quits (toggles?)
+ * -- set readonly flag for CDs, set removable flag for CF readers
+ * -- do inquiry and verify we got a disk and not a tape (for LUN mismatch)
+ * -- support pphaneuf's SDDR-75 with two LUNs (also broken capacity...)
+ * -- special case some senses, e.g. 3a/0 -> no media present, reduce retries
+ * -- do something about spin-down devices, they are extremely dangerous
+ * (ZIP is one. Needs spin-up command as well.)
+ * -- verify the 13 conditions and do bulk resets
+ * -- normal pool of commands instead of cmdv[]?
+ * -- kill last_pipe and simply do two-state clearing on both pipes
+ * -- verify protocol (bulk) from USB descriptors (maybe...)
+ * -- highmem and sg
+ * -- move top_sense and work_bcs into separate allocations (if they survive)
+ * for cache purists and esoteric architectures.
+ * -- prune comments, they are too volumnous
+ * -- Exterminate P3 printks
+ * -- Resove XXX's
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/usb.h>
+#include <linux/blkdev.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/timer.h>
+#include <scsi/scsi.h>
+
+#define DRV_NAME "ub"
+#define DEVFS_NAME DRV_NAME
+
+#define UB_MAJOR 125 /* Stolen from Experimental range for a week - XXX */
+
+/*
+ * Definitions which have to be scattered once we understand the layout better.
+ */
+
+/* Transport (despite PR in the name) */
+#define US_PR_BULK 0x50 /* bulk only */
+
+/* Protocol */
+#define US_SC_SCSI 0x06 /* Transparent */
+
+/*
+ */
+#define UB_MINORS_PER_MAJOR 8
+
+#define UB_MAX_CDB_SIZE 16 /* Corresponds to Bulk */
+
+#define UB_SENSE_SIZE 18
+
+/*
+ */
+
+/* command block wrapper */
+struct bulk_cb_wrap {
+ u32 Signature; /* contains 'USBC' */
+ u32 Tag; /* unique per command id */
+ u32 DataTransferLength; /* size of data */
+ u8 Flags; /* direction in bit 0 */
+ u8 Lun; /* LUN normally 0 */
+ u8 Length; /* of of the CDB */
+ u8 CDB[UB_MAX_CDB_SIZE]; /* max command */
+};
+
+#define US_BULK_CB_WRAP_LEN 31
+#define US_BULK_CB_SIGN 0x43425355 /*spells out USBC */
+#define US_BULK_FLAG_IN 1
+#define US_BULK_FLAG_OUT 0
+
+/* command status wrapper */
+struct bulk_cs_wrap {
+ u32 Signature; /* should = 'USBS' */
+ u32 Tag; /* same as original command */
+ u32 Residue; /* amount not transferred */
+ u8 Status; /* see below */
+};
+
+#define US_BULK_CS_WRAP_LEN 13
+#define US_BULK_CS_SIGN 0x53425355 /* spells out 'USBS' */
+/* This is for Olympus Camedia digital cameras */
+#define US_BULK_CS_OLYMPUS_SIGN 0x55425355 /* spells out 'USBU' */
+#define US_BULK_STAT_OK 0
+#define US_BULK_STAT_FAIL 1
+#define US_BULK_STAT_PHASE 2
+
+/* bulk-only class specific requests */
+#define US_BULK_RESET_REQUEST 0xff
+#define US_BULK_GET_MAX_LUN 0xfe
+
+/*
+ */
+struct ub_dev;
+
+#define UB_MAX_REQ_SG 1
+#define UB_MAX_SECTORS 64
+
+/*
+ * A second ought to be enough for a 32K transfer (UB_MAX_SECTORS)
+ * even if a webcam hogs the bus (famous last words).
+ * Some CDs need a second to spin up though.
+ * ZIP drive rejects commands when it's not spinning,
+ * so it does not need long timeouts either.
+ */
+#define UB_URB_TIMEOUT (HZ*2)
+#define UB_CTRL_TIMEOUT (HZ/2) /* 500ms ought to be enough to clear a stall */
+
+/*
+ * An instance of a SCSI command in transit.
+ */
+#define UB_DIR_NONE 0
+#define UB_DIR_READ 1
+#define UB_DIR_ILLEGAL2 2
+#define UB_DIR_WRITE 3
+
+#define UB_DIR_CHAR(c) (((c)==UB_DIR_WRITE)? 'w': \
+ (((c)==UB_DIR_READ)? 'r': 'n'))
+
+enum ub_scsi_cmd_state {
+ UB_CMDST_INIT, /* Initial state */
+ UB_CMDST_CMD, /* Command submitted */
+ UB_CMDST_DATA, /* Data phase */
+ UB_CMDST_CLR2STS, /* Clearing before requesting status */
+ UB_CMDST_STAT, /* Status phase */
+ UB_CMDST_CLEAR, /* Clearing a stall (halt, actually) */
+ UB_CMDST_SENSE, /* Sending Request Sense */
+ UB_CMDST_DONE /* Final state */
+};
+
+static char *ub_scsi_cmd_stname[] = {
+ ". ",
+ "Cmd",
+ "dat",
+ "c2s",
+ "sts",
+ "clr",
+ "Sen",
+ "fin"
+};
+
+struct ub_scsi_cmd {
+ unsigned char cdb[UB_MAX_CDB_SIZE];
+ unsigned char cdb_len;
+
+ unsigned char dir; /* 0 - none, 1 - read, 3 - write. */
+ unsigned char trace_index;
+ enum ub_scsi_cmd_state state;
+ unsigned int tag;
+ struct ub_scsi_cmd *next;
+
+ int error; /* Return code - valid upon done */
+ int act_len; /* Return size */
+
+ int stat_count; /* Retries getting status. */
+
+ /*
+ * We do not support transfers from highmem pages
+ * because the underlying USB framework does not do what we need.
+ */
+ char *data; /* Requested buffer */
+ unsigned int len; /* Requested length */
+ // struct scatterlist sgv[UB_MAX_REQ_SG];
+
+ void (*done)(struct ub_dev *, struct ub_scsi_cmd *);
+ void *back;
+};
+
+/*
+ */
+struct ub_capacity {
+ unsigned long nsec; /* Linux size - 512 byte sectors */
+ unsigned int bsize; /* Linux hardsect_size */
+ unsigned int bshift; /* Shift between 512 and hard sects */
+};
+
+/*
+ * The SCSI command tracing structure.
+ */
+
+#define SCMD_ST_HIST_SZ 8
+#define SCMD_TRACE_SZ 15 /* No more than 256 (trace_index) */
+
+struct ub_scsi_cmd_trace {
+ int hcur;
+ unsigned int tag;
+ unsigned int req_size, act_size;
+ unsigned char op;
+ unsigned char dir;
+ unsigned char key, asc, ascq;
+ char st_hst[SCMD_ST_HIST_SZ];
+};
+
+struct ub_scsi_trace {
+ int cur;
+ struct ub_scsi_cmd_trace vec[SCMD_TRACE_SZ];
+};
+
+/*
+ * This is a direct take-off from linux/include/completion.h
+ * The difference is that I do not wait on this thing, just poll.
+ * When I want to wait (ub_probe), I just use the stock completion.
+ *
+ * Note that INIT_COMPLETION takes no lock. It is correct. But why
+ * in the bloody hell that thing takes struct instead of pointer to struct
+ * is quite beyond me. I just copied it from the stock completion.
+ */
+struct ub_completion {
+ unsigned int done;
+ spinlock_t lock;
+};
+
+static inline void ub_init_completion(struct ub_completion *x)
+{
+ x->done = 0;
+ spin_lock_init(&x->lock);
+}
+
+#define UB_INIT_COMPLETION(x) ((x).done = 0)
+
+static void ub_complete(struct ub_completion *x)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&x->lock, flags);
+ x->done++;
+ spin_unlock_irqrestore(&x->lock, flags);
+}
+
+static int ub_is_completed(struct ub_completion *x)
+{
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&x->lock, flags);
+ ret = x->done;
+ spin_unlock_irqrestore(&x->lock, flags);
+ return ret;
+}
+
+/*
+ */
+struct ub_scsi_cmd_queue {
+ int qlen, qmax;
+ struct ub_scsi_cmd *head, *tail;
+};
+
+/*
+ * The UB device instance.
+ */
+struct ub_dev {
+ spinlock_t lock;
+ int id; /* Number among ub's */
+ atomic_t poison; /* The USB device is disconnected */
+ int openc; /* protected by ub_lock! */
+ /* kref is too implicit for our taste */
+ unsigned int tagcnt;
+ int changed; /* Media was changed */
+ int removable;
+ int readonly;
+ char name[8];
+ struct usb_device *dev;
+ struct usb_interface *intf;
+
+ struct ub_capacity capacity;
+ struct gendisk *disk;
+
+ unsigned int send_bulk_pipe; /* cached pipe values */
+ unsigned int recv_bulk_pipe;
+ unsigned int send_ctrl_pipe;
+ unsigned int recv_ctrl_pipe;
+
+ struct tasklet_struct tasklet;
+
+ /* XXX Use Ingo's mempool (once we have more than one) */
+ int cmda[1];
+ struct ub_scsi_cmd cmdv[1];
+
+ struct ub_scsi_cmd_queue cmd_queue;
+ struct ub_scsi_cmd top_rqs_cmd; /* REQUEST SENSE */
+ unsigned char top_sense[UB_SENSE_SIZE];
+
+ struct ub_completion work_done;
+ struct urb work_urb;
+ struct timer_list work_timer;
+ int last_pipe; /* What might need clearing */
+ struct bulk_cb_wrap work_bcb;
+ struct bulk_cs_wrap work_bcs;
+ struct usb_ctrlrequest work_cr;
+
+ struct ub_scsi_trace tr;
+};
+
+/*
+ */
+static void ub_rw_cmd_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static void ub_end_rq(struct request *rq, int uptodate);
+static int ub_submit_scsi(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static void ub_urb_complete(struct urb *urb, struct pt_regs *pt);
+static void ub_scsi_action(unsigned long _dev);
+static void ub_scsi_dispatch(struct ub_dev *sc);
+static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static void ub_state_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int rc);
+static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static void ub_state_sense(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static int ub_submit_clear_stall(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
+ int stalled_pipe);
+static void ub_top_sense_done(struct ub_dev *sc, struct ub_scsi_cmd *scmd);
+static int ub_sync_tur(struct ub_dev *sc);
+static int ub_sync_read_cap(struct ub_dev *sc, struct ub_capacity *ret);
+
+/*
+ */
+static struct usb_device_id ub_usb_ids[] = {
+ // { USB_DEVICE_VER(0x0781, 0x0002, 0x0009, 0x0009) }, /* SDDR-31 */
+ { USB_INTERFACE_INFO(USB_CLASS_MASS_STORAGE, US_SC_SCSI, US_PR_BULK) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(usb, ub_usb_ids);
+
+/*
+ * Find me a way to identify "next free minor" for add_disk(),
+ * and the array disappears the next day. However, the number of
+ * hosts has something to do with the naming and /proc/partitions.
+ * This has to be thought out in detail before changing.
+ * If UB_MAX_HOST was 1000, we'd use a bitmap. Or a better data structure.
+ */
+#define UB_MAX_HOSTS 26
+static char ub_hostv[UB_MAX_HOSTS];
+static spinlock_t ub_lock = SPIN_LOCK_UNLOCKED; /* Locks globals and ->openc */
+
+/*
+ * The SCSI command tracing procedures.
+ */
+
+static void ub_cmdtr_new(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ int n;
+ struct ub_scsi_cmd_trace *t;
+
+ if ((n = sc->tr.cur + 1) == SCMD_TRACE_SZ) n = 0;
+ t = &sc->tr.vec[n];
+
+ memset(t, 0, sizeof(struct ub_scsi_cmd_trace));
+ t->tag = cmd->tag;
+ t->op = cmd->cdb[0];
+ t->dir = cmd->dir;
+ t->req_size = cmd->len;
+ t->st_hst[0] = cmd->state;
+
+ sc->tr.cur = n;
+ cmd->trace_index = n;
+}
+
+static void ub_cmdtr_state(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ int n;
+ struct ub_scsi_cmd_trace *t;
+
+ t = &sc->tr.vec[cmd->trace_index];
+ if (t->tag == cmd->tag) {
+ if ((n = t->hcur + 1) == SCMD_ST_HIST_SZ) n = 0;
+ t->st_hst[n] = cmd->state;
+ t->hcur = n;
+ }
+}
+
+static void ub_cmdtr_act_len(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct ub_scsi_cmd_trace *t;
+
+ t = &sc->tr.vec[cmd->trace_index];
+ if (t->tag == cmd->tag)
+ t->act_size = cmd->act_len;
+}
+
+static void ub_cmdtr_sense(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
+ unsigned char *sense)
+{
+ struct ub_scsi_cmd_trace *t;
+
+ t = &sc->tr.vec[cmd->trace_index];
+ if (t->tag == cmd->tag) {
+ t->key = sense[2] & 0x0F;
+ t->asc = sense[12];
+ t->ascq = sense[13];
+ }
+}
+
+static ssize_t ub_diag_show(struct device *dev, char *page)
+{
+ struct usb_interface *intf;
+ struct ub_dev *sc;
+ int cnt;
+ unsigned long flags;
+ int nc, nh;
+ int i, j;
+ struct ub_scsi_cmd_trace *t;
+
+ intf = to_usb_interface(dev);
+ sc = usb_get_intfdata(intf);
+ if (sc == NULL)
+ return 0;
+
+ cnt = 0;
+ spin_lock_irqsave(&sc->lock, flags);
+
+ cnt += sprintf(page + cnt,
+ "qlen %d qmax %d changed %d removable %d readonly %d\n",
+ sc->cmd_queue.qlen, sc->cmd_queue.qmax,
+ sc->changed, sc->removable, sc->readonly);
+
+ if ((nc = sc->tr.cur + 1) == SCMD_TRACE_SZ) nc = 0;
+ for (j = 0; j < SCMD_TRACE_SZ; j++) {
+ t = &sc->tr.vec[nc];
+
+ cnt += sprintf(page + cnt, "%08x %02x", t->tag, t->op);
+ if (t->op == REQUEST_SENSE) {
+ cnt += sprintf(page + cnt, " [sense %x %02x %02x]",
+ t->key, t->asc, t->ascq);
+ } else {
+ cnt += sprintf(page + cnt, " %c", UB_DIR_CHAR(t->dir));
+ cnt += sprintf(page + cnt, " [%5d %5d]",
+ t->req_size, t->act_size);
+ }
+ if ((nh = t->hcur + 1) == SCMD_ST_HIST_SZ) nh = 0;
+ for (i = 0; i < SCMD_ST_HIST_SZ; i++) {
+ cnt += sprintf(page + cnt, " %s",
+ ub_scsi_cmd_stname[(int)t->st_hst[nh]]);
+ if (++nh == SCMD_ST_HIST_SZ) nh = 0;
+ }
+ cnt += sprintf(page + cnt, "\n");
+
+ if (++nc == SCMD_TRACE_SZ) nc = 0;
+ }
+
+ spin_unlock_irqrestore(&sc->lock, flags);
+ return cnt;
+}
+
+static DEVICE_ATTR(diag, S_IRUGO, ub_diag_show, NULL); /* N.B. World readable */
+
+/*
+ * The id allocator.
+ *
+ * This also stores the host for indexing by minor, which is somewhat dirty.
+ */
+static int ub_id_get(void)
+{
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&ub_lock, flags);
+ for (i = 0; i < UB_MAX_HOSTS; i++) {
+ if (ub_hostv[i] == 0) {
+ ub_hostv[i] = 1;
+ spin_unlock_irqrestore(&ub_lock, flags);
+ return i;
+ }
+ }
+ spin_unlock_irqrestore(&ub_lock, flags);
+ return -1;
+}
+
+static void ub_id_put(int id)
+{
+
+ if (id < 0 || id >= UB_MAX_HOSTS) {
+ printk(KERN_ERR DRV_NAME ": bad host ID %d\n", id);
+ return;
+ }
+ if (ub_hostv[id] == 0) {
+ printk(KERN_ERR DRV_NAME ": freeing free host ID %d\n", id);
+ return;
+ }
+ ub_hostv[id] = 0;
+}
+
+/*
+ * Final cleanup and deallocation.
+ * This must be called with ub_lock taken.
+ */
+static void ub_cleanup(struct ub_dev *sc)
+{
+ ub_id_put(sc->id);
+ kfree(sc);
+}
+
+/*
+ * The "command allocator".
+ */
+static struct ub_scsi_cmd *ub_get_cmd(struct ub_dev *sc)
+{
+ struct ub_scsi_cmd *ret;
+
+ if (sc->cmda[0])
+ return NULL;
+ ret = &sc->cmdv[0];
+ sc->cmda[0] = 1;
+ return ret;
+}
+
+static void ub_put_cmd(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ if (cmd != &sc->cmdv[0]) {
+ printk(KERN_WARNING "%s: releasing a foreign cmd %p\n",
+ sc->name, cmd);
+ return;
+ }
+ if (!sc->cmda[0]) {
+ printk(KERN_WARNING "%s: releasing a free cmd\n", sc->name);
+ return;
+ }
+ sc->cmda[0] = 0;
+}
+
+/*
+ * The command queue.
+ */
+static void ub_cmdq_add(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct ub_scsi_cmd_queue *t = &sc->cmd_queue;
+
+ if (t->qlen++ == 0) {
+ t->head = cmd;
+ t->tail = cmd;
+ } else {
+ t->tail->next = cmd;
+ t->tail = cmd;
+ }
+
+ if (t->qlen > t->qmax)
+ t->qmax = t->qlen;
+}
+
+static void ub_cmdq_insert(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct ub_scsi_cmd_queue *t = &sc->cmd_queue;
+
+ if (t->qlen++ == 0) {
+ t->head = cmd;
+ t->tail = cmd;
+ } else {
+ cmd->next = t->head;
+ t->head = cmd;
+ }
+
+ if (t->qlen > t->qmax)
+ t->qmax = t->qlen;
+}
+
+static struct ub_scsi_cmd *ub_cmdq_pop(struct ub_dev *sc)
+{
+ struct ub_scsi_cmd_queue *t = &sc->cmd_queue;
+ struct ub_scsi_cmd *cmd;
+
+ if (t->qlen == 0)
+ return NULL;
+ if (--t->qlen == 0)
+ t->tail = NULL;
+ cmd = t->head;
+ t->head = cmd->next;
+ cmd->next = NULL;
+ return cmd;
+}
+
+#define ub_cmdq_peek(sc) ((sc)->cmd_queue.head)
+
+/*
+ * The request function is our main entry point
+ */
+
+static inline int ub_bd_rq_fn_1(request_queue_t *q)
+{
+#if 0
+ int writing = 0, pci_dir, i, n_elem;
+ u32 tmp;
+ unsigned int msg_size;
+#endif
+ struct ub_dev *sc = q->queuedata;
+ struct request *rq;
+#if 0 /* We use rq->buffer for now */
+ struct scatterlist *sg;
+ int n_elem;
+#endif
+ struct ub_scsi_cmd *cmd;
+ int ub_dir;
+ unsigned int block, nblks;
+ int rc;
+
+ if ((rq = elv_next_request(q)) == NULL)
+ return 1;
+
+ if (atomic_read(&sc->poison) || sc->changed) {
+ blkdev_dequeue_request(rq);
+ ub_end_rq(rq, 0);
+ return 0;
+ }
+
+ if ((cmd = ub_get_cmd(sc)) == NULL) {
+ blk_stop_queue(q);
+ return 1;
+ }
+
+ blkdev_dequeue_request(rq);
+
+ if (rq_data_dir(rq) == WRITE)
+ ub_dir = UB_DIR_WRITE;
+ else
+ ub_dir = UB_DIR_READ;
+
+ /*
+ * get scatterlist from block layer
+ */
+#if 0 /* We use rq->buffer for now */
+ sg = &cmd->sgv[0];
+ n_elem = blk_rq_map_sg(q, rq, sg);
+ if (n_elem <= 0) {
+ ub_put_cmd(sc, cmd);
+ ub_end_rq(rq, 0);
+ blk_start_queue(q);
+ return 0; /* request with no s/g entries? */
+ }
+
+ if (n_elem != 1) { /* Paranoia */
+ printk(KERN_WARNING "%s: request with %d segments\n",
+ sc->name, n_elem);
+ ub_put_cmd(sc, cmd);
+ ub_end_rq(rq, 0);
+ blk_start_queue(q);
+ return 0;
+ }
+#endif
+ /*
+ * XXX Unfortunately, this check does not work. It is quite possible
+ * to get bogus non-null rq->buffer if you allow sg by mistake.
+ */
+ if (rq->buffer == NULL) {
+ /*
+ * This must not happen if we set the queue right.
+ * The block level must create bounce buffers for us.
+ */
+ static int do_print = 1;
+ if (do_print) {
+ printk(KERN_WARNING "%s: unmapped request\n", sc->name);
+ do_print = 0;
+ }
+ ub_put_cmd(sc, cmd);
+ ub_end_rq(rq, 0);
+ blk_start_queue(q);
+ return 0;
+ }
+
+ /*
+ * build the command
+ */
+ block = rq->sector;
+ nblks = rq->nr_sectors;
+
+ memset(cmd, 0, sizeof(struct ub_scsi_cmd));
+ cmd->cdb[0] = (ub_dir == UB_DIR_READ)? READ_10: WRITE_10;
+ /* 10-byte uses 4 bytes of LBA: 2147483648KB, 2097152MB, 2048GB */
+ cmd->cdb[2] = block >> 24;
+ cmd->cdb[3] = block >> 16;
+ cmd->cdb[4] = block >> 8;
+ cmd->cdb[5] = block;
+ cmd->cdb[7] = nblks >> 8;
+ cmd->cdb[8] = nblks;
+ cmd->cdb_len = 10;
+ cmd->dir = ub_dir;
+ cmd->state = UB_CMDST_INIT;
+ cmd->data = rq->buffer;
+ cmd->len = nblks * 512;
+ cmd->done = ub_rw_cmd_done;
+ cmd->back = rq;
+
+ cmd->tag = sc->tagcnt++;
+ if ((rc = ub_submit_scsi(sc, cmd)) != 0) {
+ ub_put_cmd(sc, cmd);
+ ub_end_rq(rq, 0);
+ blk_start_queue(q);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void ub_bd_rq_fn(request_queue_t *q)
+{
+ do { } while (ub_bd_rq_fn_1(q) == 0);
+}
+
+static void ub_rw_cmd_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct request *rq = cmd->back;
+ struct gendisk *disk = sc->disk;
+ request_queue_t *q = disk->queue;
+ int uptodate;
+
+ if (cmd->error == 0)
+ uptodate = 1;
+ else
+ uptodate = 0;
+
+ ub_put_cmd(sc, cmd);
+ ub_end_rq(rq, uptodate);
+ blk_start_queue(q);
+}
+
+static void ub_end_rq(struct request *rq, int uptodate)
+{
+ int rc;
+
+ rc = end_that_request_first(rq, uptodate, rq->hard_nr_sectors);
+ // assert(rc == 0);
+ end_that_request_last(rq);
+}
+
+/*
+ * Submit a regular SCSI operation (not an auto-sense).
+ *
+ * The Iron Law of Good Submit Routine is:
+ * Zero return - callback is done, Nonzero return - callback is not done.
+ * No exceptions.
+ *
+ * Host is assumed locked.
+ *
+ * XXX We only support Bulk for the moment.
+ */
+static int ub_submit_scsi(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+
+ if (cmd->state != UB_CMDST_INIT ||
+ (cmd->dir != UB_DIR_NONE && cmd->len == 0)) {
+ return -EINVAL;
+ }
+
+ ub_cmdq_add(sc, cmd);
+ /*
+ * We can call ub_scsi_dispatch(sc) right away here, but it's a little
+ * safer to jump to a tasklet, in case upper layers do something silly.
+ */
+ tasklet_schedule(&sc->tasklet);
+ return 0;
+}
+
+/*
+ * Submit the first URB for the queued command.
+ * This function does not deal with queueing in any way.
+ */
+static int ub_scsi_cmd_start(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct bulk_cb_wrap *bcb;
+ int rc;
+
+ bcb = &sc->work_bcb;
+
+ /* set up the command wrapper */
+ bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
+ bcb->Tag = cmd->tag; /* Endianness is not important */
+ bcb->DataTransferLength = cpu_to_le32(cmd->len);
+ bcb->Flags = (cmd->dir == UB_DIR_READ) ? 0x80 : 0;
+ bcb->Lun = 0; /* No multi-LUN yet */
+ bcb->Length = cmd->cdb_len;
+
+ /* copy the command payload */
+ memcpy(bcb->CDB, cmd->cdb, UB_MAX_CDB_SIZE);
+
+ UB_INIT_COMPLETION(sc->work_done);
+
+ sc->last_pipe = sc->send_bulk_pipe;
+ usb_fill_bulk_urb(&sc->work_urb, sc->dev, sc->send_bulk_pipe,
+ bcb, US_BULK_CB_WRAP_LEN, ub_urb_complete, sc);
+ sc->work_urb.transfer_flags = URB_ASYNC_UNLINK;
+
+ /* Fill what we shouldn't be filling, because usb-storage did so. */
+ sc->work_urb.actual_length = 0;
+ sc->work_urb.error_count = 0;
+ sc->work_urb.status = 0;
+
+ sc->work_timer.expires = jiffies + UB_URB_TIMEOUT;
+ add_timer(&sc->work_timer);
+
+ if ((rc = usb_submit_urb(&sc->work_urb, GFP_ATOMIC)) != 0) {
+ /* XXX Clear stalls */
+ printk("ub: cmd #%d start failed (%d)\n", cmd->tag, rc); /* P3 */
+ del_timer(&sc->work_timer);
+ ub_complete(&sc->work_done);
+ return rc;
+ }
+
+ cmd->state = UB_CMDST_CMD;
+ ub_cmdtr_state(sc, cmd);
+ return 0;
+}
+
+/*
+ * Timeout handler.
+ */
+static void ub_urb_timeout(unsigned long arg)
+{
+ struct ub_dev *sc = (struct ub_dev *) arg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sc->lock, flags);
+ usb_unlink_urb(&sc->work_urb);
+ spin_unlock_irqrestore(&sc->lock, flags);
+}
+
+/*
+ * Completion routine for the work URB.
+ *
+ * This can be called directly from usb_submit_urb (while we have
+ * the sc->lock taken) and from an interrupt (while we do NOT have
+ * the sc->lock taken). Therefore, bounce this off to a tasklet.
+ */
+static void ub_urb_complete(struct urb *urb, struct pt_regs *pt)
+{
+ struct ub_dev *sc = urb->context;
+
+ ub_complete(&sc->work_done);
+ tasklet_schedule(&sc->tasklet);
+}
+
+static void ub_scsi_action(unsigned long _dev)
+{
+ struct ub_dev *sc = (struct ub_dev *) _dev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sc->lock, flags);
+ ub_scsi_dispatch(sc);
+ spin_unlock_irqrestore(&sc->lock, flags);
+}
+
+static void ub_scsi_dispatch(struct ub_dev *sc)
+{
+ struct ub_scsi_cmd *cmd;
+ int rc;
+
+ while ((cmd = ub_cmdq_peek(sc)) != NULL) {
+ if (cmd->state == UB_CMDST_DONE) {
+ ub_cmdq_pop(sc);
+ (*cmd->done)(sc, cmd);
+ } else if (cmd->state == UB_CMDST_INIT) {
+ ub_cmdtr_new(sc, cmd);
+ if ((rc = ub_scsi_cmd_start(sc, cmd)) == 0)
+ break;
+ cmd->error = rc;
+ cmd->state = UB_CMDST_DONE;
+ ub_cmdtr_state(sc, cmd);
+ } else {
+ if (!ub_is_completed(&sc->work_done))
+ break;
+ ub_scsi_urb_compl(sc, cmd);
+ }
+ }
+}
+
+static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct urb *urb = &sc->work_urb;
+ struct bulk_cs_wrap *bcs;
+ int pipe;
+ int rc;
+
+/* P3 */ /** printk("ub: urb status %d pipe 0x%08x len %d act %d\n",
+ urb->status, urb->pipe, urb->transfer_buffer_length, urb->actual_length); **/
+
+ if (atomic_read(&sc->poison)) {
+ /* A little too simplistic, I feel... */
+ goto Bad_End;
+ }
+
+ if (cmd->state == UB_CMDST_CLEAR) {
+ if (urb->status == -EPIPE) {
+ /*
+ * STALL while clearning STALL.
+ * A STALL is illegal on a control pipe!
+ * XXX Might try to reset the device here and retry.
+ */
+ printk(KERN_NOTICE "%s: "
+ "stall on control pipe for device %u\n",
+ sc->name, sc->dev->devnum);
+ goto Bad_End;
+ }
+
+ /*
+ * We ignore the result for the halt clear.
+ */
+
+ /* reset the endpoint toggle */
+ usb_settoggle(sc->dev, usb_pipeendpoint(sc->last_pipe),
+ usb_pipeout(sc->last_pipe), 0);
+
+ ub_state_sense(sc, cmd);
+
+ } else if (cmd->state == UB_CMDST_CLR2STS) {
+ if (urb->status == -EPIPE) {
+ /*
+ * STALL while clearning STALL.
+ * A STALL is illegal on a control pipe!
+ * XXX Might try to reset the device here and retry.
+ */
+ printk(KERN_NOTICE "%s: "
+ "stall on control pipe for device %u\n",
+ sc->name, sc->dev->devnum);
+ goto Bad_End;
+ }
+
+ /*
+ * We ignore the result for the halt clear.
+ */
+
+ /* reset the endpoint toggle */
+ usb_settoggle(sc->dev, usb_pipeendpoint(sc->last_pipe),
+ usb_pipeout(sc->last_pipe), 0);
+
+ ub_state_stat(sc, cmd);
+
+ } else if (cmd->state == UB_CMDST_CMD) {
+ if (urb->status == -EPIPE) {
+ rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
+ if (rc != 0) {
+ printk(KERN_NOTICE "%s: "
+ "unable to submit clear for device %u (%d)\n",
+ sc->name, sc->dev->devnum, rc);
+ /*
+ * This is typically ENOMEM or some other such shit.
+ * Retrying is pointless. Just do Bad End on it...
+ */
+ goto Bad_End;
+ }
+ cmd->state = UB_CMDST_CLEAR;
+ ub_cmdtr_state(sc, cmd);
+ return;
+ }
+ if (urb->status != 0)
+ goto Bad_End;
+ if (urb->actual_length != US_BULK_CB_WRAP_LEN) {
+ /* XXX Must do reset here to unconfuse the device */
+ goto Bad_End;
+ }
+
+ if (cmd->dir == UB_DIR_NONE) {
+ ub_state_stat(sc, cmd);
+ return;
+ }
+
+ UB_INIT_COMPLETION(sc->work_done);
+
+ if (cmd->dir == UB_DIR_READ)
+ pipe = sc->recv_bulk_pipe;
+ else
+ pipe = sc->send_bulk_pipe;
+ sc->last_pipe = pipe;
+ usb_fill_bulk_urb(&sc->work_urb, sc->dev, pipe,
+ cmd->data, cmd->len, ub_urb_complete, sc);
+ sc->work_urb.transfer_flags = URB_ASYNC_UNLINK;
+ sc->work_urb.actual_length = 0;
+ sc->work_urb.error_count = 0;
+ sc->work_urb.status = 0;
+
+ sc->work_timer.expires = jiffies + UB_URB_TIMEOUT;
+ add_timer(&sc->work_timer);
+
+ if ((rc = usb_submit_urb(&sc->work_urb, GFP_ATOMIC)) != 0) {
+ /* XXX Clear stalls */
+ printk("ub: data #%d submit failed (%d)\n", cmd->tag, rc); /* P3 */
+ del_timer(&sc->work_timer);
+ ub_complete(&sc->work_done);
+ ub_state_done(sc, cmd, rc);
+ return;
+ }
+
+ cmd->state = UB_CMDST_DATA;
+ ub_cmdtr_state(sc, cmd);
+
+ } else if (cmd->state == UB_CMDST_DATA) {
+ if (urb->status == -EPIPE) {
+ rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
+ if (rc != 0) {
+ printk(KERN_NOTICE "%s: "
+ "unable to submit clear for device %u (%d)\n",
+ sc->name, sc->dev->devnum, rc);
+ /*
+ * This is typically ENOMEM or some other such shit.
+ * Retrying is pointless. Just do Bad End on it...
+ */
+ goto Bad_End;
+ }
+ cmd->state = UB_CMDST_CLR2STS;
+ ub_cmdtr_state(sc, cmd);
+ return;
+ }
+ if (urb->status == -EOVERFLOW) {
+ /*
+ * A babble? Failure, but we must transfer CSW now.
+ */
+ cmd->error = -EOVERFLOW; /* A cheap trick... */
+ } else {
+ if (urb->status != 0)
+ goto Bad_End;
+ }
+
+ cmd->act_len = urb->actual_length;
+ ub_cmdtr_act_len(sc, cmd);
+
+ ub_state_stat(sc, cmd);
+
+ } else if (cmd->state == UB_CMDST_STAT) {
+ if (urb->status == -EPIPE) {
+ rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
+ if (rc != 0) {
+ printk(KERN_NOTICE "%s: "
+ "unable to submit clear for device %u (%d)\n",
+ sc->name, sc->dev->devnum, rc);
+ /*
+ * This is typically ENOMEM or some other such shit.
+ * Retrying is pointless. Just do Bad End on it...
+ */
+ goto Bad_End;
+ }
+ cmd->state = UB_CMDST_CLEAR;
+ ub_cmdtr_state(sc, cmd);
+ return;
+ }
+ if (urb->status != 0)
+ goto Bad_End;
+
+ if (urb->actual_length == 0) {
+ /*
+ * Some broken devices add unnecessary zero-length
+ * packets to the end of their data transfers.
+ * Such packets show up as 0-length CSWs. If we
+ * encounter such a thing, try to read the CSW again.
+ */
+ if (++cmd->stat_count >= 4) {
+ printk(KERN_NOTICE "%s: "
+ "unable to get CSW on device %u\n",
+ sc->name, sc->dev->devnum);
+ goto Bad_End;
+ }
+
+ /*
+ * ub_state_stat only not dropping the count...
+ */
+ UB_INIT_COMPLETION(sc->work_done);
+
+ sc->last_pipe = sc->recv_bulk_pipe;
+ usb_fill_bulk_urb(&sc->work_urb, sc->dev,
+ sc->recv_bulk_pipe, &sc->work_bcs,
+ US_BULK_CS_WRAP_LEN, ub_urb_complete, sc);
+ sc->work_urb.transfer_flags = URB_ASYNC_UNLINK;
+ sc->work_urb.actual_length = 0;
+ sc->work_urb.error_count = 0;
+ sc->work_urb.status = 0;
+
+ sc->work_timer.expires = jiffies + UB_URB_TIMEOUT;
+ add_timer(&sc->work_timer);
+
+ rc = usb_submit_urb(&sc->work_urb, GFP_ATOMIC);
+ if (rc != 0) {
+ /* XXX Clear stalls */
+ printk("%s: CSW #%d submit failed (%d)\n",
+ sc->name, cmd->tag, rc); /* P3 */
+ del_timer(&sc->work_timer);
+ ub_complete(&sc->work_done);
+ ub_state_done(sc, cmd, rc);
+ return;
+ }
+ return;
+ }
+
+ /*
+ * Check the returned Bulk protocol status.
+ */
+
+ bcs = &sc->work_bcs;
+ rc = le32_to_cpu(bcs->Residue);
+ if (rc != cmd->len - cmd->act_len) {
+ /*
+ * It is all right to transfer less, the caller has
+ * to check. But it's not all right if the device
+ * counts disagree with our counts.
+ */
+ /* P3 */ printk("%s: resid %d len %d act %d\n",
+ sc->name, rc, cmd->len, cmd->act_len);
+ goto Bad_End;
+ }
+
+ if (bcs->Signature != cpu_to_le32(US_BULK_CS_SIGN) &&
+ bcs->Signature != cpu_to_le32(US_BULK_CS_OLYMPUS_SIGN)) {
+ /* XXX Rate-limit, even for P3 tagged */
+ /* P3 */ printk("ub: signature 0x%x\n", bcs->Signature);
+ /* Windows ignores signatures, so do we. */
+ }
+
+ if (bcs->Tag != cmd->tag) {
+ /* P3 */ printk("%s: tag orig 0x%x reply 0x%x\n",
+ sc->name, cmd->tag, bcs->Tag);
+ goto Bad_End;
+ }
+
+ switch (bcs->Status) {
+ case US_BULK_STAT_OK:
+ break;
+ case US_BULK_STAT_FAIL:
+ ub_state_sense(sc, cmd);
+ return;
+ case US_BULK_STAT_PHASE:
+ /* XXX We must reset the transport here */
+ /* P3 */ printk("%s: status PHASE\n", sc->name);
+ goto Bad_End;
+ default:
+ printk(KERN_INFO "%s: unknown CSW status 0x%x\n",
+ sc->name, bcs->Status);
+ goto Bad_End;
+ }
+
+ /* Not zeroing error to preserve a babble indicator */
+ cmd->state = UB_CMDST_DONE;
+ ub_cmdtr_state(sc, cmd);
+ ub_cmdq_pop(sc);
+ (*cmd->done)(sc, cmd);
+
+ } else if (cmd->state == UB_CMDST_SENSE) {
+ /*
+ * We do not look at sense, because even if there was no sense,
+ * we get into UB_CMDST_SENSE from a STALL or CSW FAIL only.
+ * We request sense because we want to clear CHECK CONDITION
+ * on devices with delusions of SCSI, and not because we
+ * are curious in any way about the sense itself.
+ */
+ /* if ((cmd->top_sense[2] & 0x0F) == NO_SENSE) { foo } */
+
+ ub_state_done(sc, cmd, -EIO);
+ } else {
+ printk(KERN_WARNING "%s: "
+ "wrong command state %d on device %u\n",
+ sc->name, cmd->state, sc->dev->devnum);
+ goto Bad_End;
+ }
+ return;
+
+Bad_End: /* Little Excel is dead */
+ ub_state_done(sc, cmd, -EIO);
+}
+
+/*
+ * Factorization helper for the command state machine:
+ * Finish the command.
+ */
+static void ub_state_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int rc)
+{
+
+ cmd->error = rc;
+ cmd->state = UB_CMDST_DONE;
+ ub_cmdtr_state(sc, cmd);
+ ub_cmdq_pop(sc);
+ (*cmd->done)(sc, cmd);
+}
+
+/*
+ * Factorization helper for the command state machine:
+ * Submit a CSW read and go to STAT state.
+ */
+static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ int rc;
+
+ UB_INIT_COMPLETION(sc->work_done);
+
+ sc->last_pipe = sc->recv_bulk_pipe;
+ usb_fill_bulk_urb(&sc->work_urb, sc->dev, sc->recv_bulk_pipe,
+ &sc->work_bcs, US_BULK_CS_WRAP_LEN, ub_urb_complete, sc);
+ sc->work_urb.transfer_flags = URB_ASYNC_UNLINK;
+ sc->work_urb.actual_length = 0;
+ sc->work_urb.error_count = 0;
+ sc->work_urb.status = 0;
+
+ sc->work_timer.expires = jiffies + UB_URB_TIMEOUT;
+ add_timer(&sc->work_timer);
+
+ if ((rc = usb_submit_urb(&sc->work_urb, GFP_ATOMIC)) != 0) {
+ /* XXX Clear stalls */
+ printk("ub: CSW #%d submit failed (%d)\n", cmd->tag, rc); /* P3 */
+ del_timer(&sc->work_timer);
+ ub_complete(&sc->work_done);
+ ub_state_done(sc, cmd, rc);
+ return;
+ }
+
+ cmd->stat_count = 0;
+ cmd->state = UB_CMDST_STAT;
+ ub_cmdtr_state(sc, cmd);
+}
+
+/*
+ * Factorization helper for the command state machine:
+ * Submit a REQUEST SENSE and go to SENSE state.
+ */
+static void ub_state_sense(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct ub_scsi_cmd *scmd;
+ int rc;
+
+ if (cmd->cdb[0] == REQUEST_SENSE) {
+ rc = -EPIPE;
+ goto error;
+ }
+
+ memset(&sc->top_sense, 0, UB_SENSE_SIZE);
+ scmd = &sc->top_rqs_cmd;
+ scmd->cdb[0] = REQUEST_SENSE;
+ scmd->cdb_len = 6;
+ scmd->dir = UB_DIR_READ;
+ scmd->state = UB_CMDST_INIT;
+ scmd->data = sc->top_sense;
+ scmd->len = UB_SENSE_SIZE;
+ scmd->done = ub_top_sense_done;
+ scmd->back = cmd;
+
+ scmd->tag = sc->tagcnt++;
+
+ cmd->state = UB_CMDST_SENSE;
+ ub_cmdtr_state(sc, cmd);
+
+ ub_cmdq_insert(sc, scmd);
+ return;
+
+error:
+ ub_state_done(sc, cmd, rc);
+}
+
+/*
+ * A helper for the command's state machine:
+ * Submit a stall clear.
+ */
+static int ub_submit_clear_stall(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
+ int stalled_pipe)
+{
+ int endp;
+ struct usb_ctrlrequest *cr;
+ int rc;
+
+ endp = usb_pipeendpoint(stalled_pipe);
+ if (usb_pipein (stalled_pipe))
+ endp |= USB_DIR_IN;
+
+ cr = &sc->work_cr;
+ cr->bRequestType = USB_RECIP_ENDPOINT;
+ cr->bRequest = USB_REQ_CLEAR_FEATURE;
+ cr->wValue = cpu_to_le16(USB_ENDPOINT_HALT);
+ cr->wIndex = cpu_to_le16(endp);
+ cr->wLength = cpu_to_le16(0);
+
+ UB_INIT_COMPLETION(sc->work_done);
+
+ usb_fill_control_urb(&sc->work_urb, sc->dev, sc->send_ctrl_pipe,
+ (unsigned char*) cr, NULL, 0, ub_urb_complete, sc);
+ sc->work_urb.transfer_flags = URB_ASYNC_UNLINK;
+ sc->work_urb.actual_length = 0;
+ sc->work_urb.error_count = 0;
+ sc->work_urb.status = 0;
+
+ sc->work_timer.expires = jiffies + UB_CTRL_TIMEOUT;
+ add_timer(&sc->work_timer);
+
+ if ((rc = usb_submit_urb(&sc->work_urb, GFP_ATOMIC)) != 0) {
+ del_timer(&sc->work_timer);
+ ub_complete(&sc->work_done);
+ return rc;
+ }
+ return 0;
+}
+
+/*
+ */
+static void ub_top_sense_done(struct ub_dev *sc, struct ub_scsi_cmd *scmd)
+{
+ unsigned char *sense = scmd->data;
+ struct ub_scsi_cmd *cmd;
+
+ ub_cmdtr_sense(sc, scmd, sense);
+
+ if ((cmd = ub_cmdq_peek(sc)) == NULL) {
+ printk(KERN_WARNING "%s: sense done while idle\n", sc->name);
+ return;
+ }
+ if (cmd != scmd->back) {
+ printk(KERN_WARNING "%s: "
+ "sense done for wrong command 0x%x on device %u\n",
+ sc->name, cmd->tag, sc->dev->devnum);
+ return;
+ }
+ if (cmd->state != UB_CMDST_SENSE) {
+ printk(KERN_WARNING "%s: "
+ "sense done with bad cmd state %d on device %u\n",
+ sc->name, cmd->state, sc->dev->devnum);
+ return;
+ }
+
+ ub_scsi_urb_compl(sc, cmd);
+}
+
+#if 0
+/* Determine what the maximum LUN supported is */
+int usb_stor_Bulk_max_lun(struct us_data *us)
+{
+ int result;
+
+ /* issue the command */
+ result = usb_stor_control_msg(us, us->recv_ctrl_pipe,
+ US_BULK_GET_MAX_LUN,
+ USB_DIR_IN | USB_TYPE_CLASS |
+ USB_RECIP_INTERFACE,
+ 0, us->ifnum, us->iobuf, 1, HZ);
+
+ /*
+ * Some devices (i.e. Iomega Zip100) need this -- apparently
+ * the bulk pipes get STALLed when the GetMaxLUN request is
+ * processed. This is, in theory, harmless to all other devices
+ * (regardless of if they stall or not).
+ */
+ if (result < 0) {
+ usb_stor_clear_halt(us, us->recv_bulk_pipe);
+ usb_stor_clear_halt(us, us->send_bulk_pipe);
+ }
+
+ US_DEBUGP("GetMaxLUN command result is %d, data is %d\n",
+ result, us->iobuf[0]);
+
+ /* if we have a successful request, return the result */
+ if (result == 1)
+ return us->iobuf[0];
+
+ /* return the default -- no LUNs */
+ return 0;
+}
+#endif
+
+/*
+ * This is called from a process context.
+ */
+static void ub_revalidate(struct ub_dev *sc)
+{
+
+ sc->readonly = 0; /* XXX Query this from the device */
+
+ /*
+ * XXX sd.c sets capacity to zero in such case. However, it doesn't
+ * work for us. In case of zero capacity, block layer refuses to
+ * have the /dev/uba opened (why?) Set capacity to some random value.
+ */
+ sc->capacity.nsec = 50;
+ sc->capacity.bsize = 512;
+ sc->capacity.bshift = 0;
+
+ if (ub_sync_tur(sc) != 0)
+ return; /* Not ready */
+ sc->changed = 0;
+
+ if (ub_sync_read_cap(sc, &sc->capacity) != 0) {
+ /*
+ * The retry here means something is wrong, either with the
+ * device, with the transport, or with our code.
+ * We keep this because sd.c has retries for capacity.
+ */
+ if (ub_sync_read_cap(sc, &sc->capacity) != 0) {
+ sc->capacity.nsec = 100;
+ sc->capacity.bsize = 512;
+ sc->capacity.bshift = 0;
+ }
+ }
+}
+
+/*
+ * The open funcion.
+ * This is mostly needed to keep refcounting, but also to support
+ * media checks on removable media drives.
+ */
+static int ub_bd_open(struct inode *inode, struct file *filp)
+{
+ struct gendisk *disk = inode->i_bdev->bd_disk;
+ struct ub_dev *sc;
+ unsigned long flags;
+ int rc;
+
+ if ((sc = disk->private_data) == NULL)
+ return -ENXIO;
+ spin_lock_irqsave(&ub_lock, flags);
+ if (atomic_read(&sc->poison)) {
+ spin_unlock_irqrestore(&ub_lock, flags);
+ return -ENXIO;
+ }
+ sc->openc++;
+ spin_unlock_irqrestore(&ub_lock, flags);
+
+ if (sc->removable || sc->readonly)
+ check_disk_change(inode->i_bdev);
+
+ /* XXX sd.c and floppy.c bail on open if media is not present. */
+
+ if (sc->readonly && (filp->f_mode & FMODE_WRITE)) {
+ rc = -EROFS;
+ goto err_open;
+ }
+
+ return 0;
+
+err_open:
+ spin_lock_irqsave(&ub_lock, flags);
+ --sc->openc;
+ if (sc->openc == 0 && atomic_read(&sc->poison))
+ ub_cleanup(sc);
+ spin_unlock_irqrestore(&ub_lock, flags);
+ return rc;
+}
+
+/*
+ */
+static int ub_bd_release(struct inode *inode, struct file *filp)
+{
+ struct gendisk *disk = inode->i_bdev->bd_disk;
+ struct ub_dev *sc = disk->private_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ub_lock, flags);
+ --sc->openc;
+ if (sc->openc == 0 && atomic_read(&sc->poison))
+ ub_cleanup(sc);
+ spin_unlock_irqrestore(&ub_lock, flags);
+ return 0;
+}
+
+/*
+ * The ioctl interface.
+ */
+static int ub_bd_ioctl(struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+// void __user *usermem = (void *) arg;
+// struct carm_port *port = ino->i_bdev->bd_disk->private_data;
+// struct hd_geometry geom;
+
+#if 0
+ switch (cmd) {
+ case HDIO_GETGEO:
+ if (usermem == NULL) // XXX Bizzare. Why?
+ return -EINVAL;
+
+ geom.heads = (u8) port->dev_geom_head;
+ geom.sectors = (u8) port->dev_geom_sect;
+ geom.cylinders = port->dev_geom_cyl;
+ geom.start = get_start_sect(ino->i_bdev);
+
+ if (copy_to_user(usermem, &geom, sizeof(geom)))
+ return -EFAULT;
+ return 0;
+
+ default: ;
+ }
+#endif
+
+ return -ENOTTY;
+}
+
+/*
+ * This is called once a new disk was seen by the block layer or by ub_probe().
+ * The main onjective here is to discover the features of the media such as
+ * the capacity, read-only status, etc. USB storage generally does not
+ * need to be spun up, but if we needed it, this would be the place.
+ *
+ * This call can sleep.
+ *
+ * The return code is not used.
+ */
+static int ub_bd_revalidate(struct gendisk *disk)
+{
+ struct ub_dev *sc = disk->private_data;
+
+ ub_revalidate(sc);
+ /* This is pretty much a long term P3 */
+ printk(KERN_INFO "%s: device %u capacity nsec %ld bsize %u\n",
+ sc->name, sc->dev->devnum, sc->capacity.nsec, sc->capacity.bsize);
+
+ set_capacity(disk, sc->capacity.nsec);
+ // set_disk_ro(sdkp->disk, sc->readonly);
+ return 0;
+}
+
+/*
+ * The check is called by the block layer to verify if the media
+ * is still available. It is supposed to be harmless, lightweight and
+ * non-intrusive in case the media was not changed.
+ *
+ * This call can sleep.
+ *
+ * The return code is bool!
+ */
+static int ub_bd_media_changed(struct gendisk *disk)
+{
+ struct ub_dev *sc = disk->private_data;
+
+ if (!sc->removable)
+ return 0;
+
+ /*
+ * We clean checks always after every command, so this is not
+ * as dangerous as it looks. If the TEST_UNIT_READY fails here,
+ * the device is actually not ready with operator or software
+ * intervention required. One dangerous item might be a drive which
+ * spins itself down, and come the time to write dirty pages, this
+ * will fail, then block layer discards the data. Since we never
+ * spin drives up, such devices simply cannot be used with ub anyway.
+ */
+ if (ub_sync_tur(sc) != 0) {
+ sc->changed = 1;
+ /* P3 */ printk("%s: made changed\n", sc->name);
+ return 1;
+ }
+
+ /* The sd.c clears this before returning (one-shot flag). Why? */
+ /* P3 */ printk("%s: %s changed\n", sc->name,
+ sc->changed? "is": "was not");
+ return sc->changed;
+}
+
+static struct block_device_operations ub_bd_fops = {
+ .owner = THIS_MODULE,
+ .open = ub_bd_open,
+ .release = ub_bd_release,
+ .ioctl = ub_bd_ioctl,
+ .media_changed = ub_bd_media_changed,
+ .revalidate_disk = ub_bd_revalidate,
+};
+
+/*
+ * Common ->done routine for commands executed synchronously.
+ */
+static void ub_probe_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+ struct completion *cop = cmd->back;
+ complete(cop);
+}
+
+/*
+ * Test if the device has a check condition on it, synchronously.
+ */
+static int ub_sync_tur(struct ub_dev *sc)
+{
+ struct ub_scsi_cmd *cmd;
+ enum { ALLOC_SIZE = sizeof(struct ub_scsi_cmd) };
+ unsigned long flags;
+ struct completion compl;
+ int rc;
+
+ init_completion(&compl);
+
+ rc = -ENOMEM;
+ if ((cmd = kmalloc(ALLOC_SIZE, GFP_KERNEL)) == NULL)
+ goto err_alloc;
+ memset(cmd, 0, ALLOC_SIZE);
+
+ cmd->cdb[0] = TEST_UNIT_READY;
+ cmd->cdb_len = 6;
+ cmd->dir = UB_DIR_NONE;
+ cmd->state = UB_CMDST_INIT;
+ cmd->done = ub_probe_done;
+ cmd->back = &compl;
+
+ spin_lock_irqsave(&sc->lock, flags);
+ cmd->tag = sc->tagcnt++;
+
+ rc = ub_submit_scsi(sc, cmd);
+ spin_unlock_irqrestore(&sc->lock, flags);
+
+ if (rc != 0) {
+ printk("ub: testing ready: submit error (%d)\n", rc); /* P3 */
+ goto err_submit;
+ }
+
+ wait_for_completion(&compl);
+
+ rc = cmd->error;
+
+err_submit:
+ kfree(cmd);
+err_alloc:
+ return rc;
+}
+
+/*
+ * Read the SCSI capacity synchronously (for probing).
+ */
+static int ub_sync_read_cap(struct ub_dev *sc, struct ub_capacity *ret)
+{
+ struct ub_scsi_cmd *cmd;
+ char *p;
+ enum { ALLOC_SIZE = sizeof(struct ub_scsi_cmd) + 8 };
+ unsigned long flags;
+ unsigned int bsize, shift;
+ unsigned long nsec;
+ struct completion compl;
+ int rc;
+
+ init_completion(&compl);
+
+ rc = -ENOMEM;
+ if ((cmd = kmalloc(ALLOC_SIZE, GFP_KERNEL)) == NULL)
+ goto err_alloc;
+ memset(cmd, 0, ALLOC_SIZE);
+ p = (char *)cmd + sizeof(struct ub_scsi_cmd);
+
+ cmd->cdb[0] = 0x25;
+ cmd->cdb_len = 10;
+ cmd->dir = UB_DIR_READ;
+ cmd->state = UB_CMDST_INIT;
+ cmd->data = p;
+ cmd->len = 8;
+ cmd->done = ub_probe_done;
+ cmd->back = &compl;
+
+ spin_lock_irqsave(&sc->lock, flags);
+ cmd->tag = sc->tagcnt++;
+
+ rc = ub_submit_scsi(sc, cmd);
+ spin_unlock_irqrestore(&sc->lock, flags);
+
+ if (rc != 0) {
+ printk("ub: reading capacity: submit error (%d)\n", rc); /* P3 */
+ goto err_submit;
+ }
+
+ wait_for_completion(&compl);
+
+ if (cmd->error != 0) {
+ printk("ub: reading capacity: error %d\n", cmd->error); /* P3 */
+ rc = -EIO;
+ goto err_read;
+ }
+ if (cmd->act_len != 8) {
+ printk("ub: reading capacity: size %d\n", cmd->act_len); /* P3 */
+ rc = -EIO;
+ goto err_read;
+ }
+
+ /* sd.c special-cases sector size of 0 to mean 512. Needed? Safe? */
+ nsec = be32_to_cpu(*(u32 *)p) + 1;
+ bsize = be32_to_cpu(*(u32 *)(p + 4));
+ switch (bsize) {
+ case 512: shift = 0; break;
+ case 1024: shift = 1; break;
+ case 2048: shift = 2; break;
+ case 4096: shift = 3; break;
+ default:
+ printk("ub: Bad sector size %u\n", bsize); /* P3 */
+ rc = -EDOM;
+ goto err_inv_bsize;
+ }
+
+ ret->bsize = bsize;
+ ret->bshift = shift;
+ ret->nsec = nsec << shift;
+ rc = 0;
+
+err_inv_bsize:
+err_read:
+err_submit:
+ kfree(cmd);
+err_alloc:
+ return rc;
+}
+
+/*
+ */
+static void ub_probe_urb_complete(struct urb *urb, struct pt_regs *pt)
+{
+ struct completion *cop = urb->context;
+ complete(cop);
+}
+
+static void ub_probe_timeout(unsigned long arg)
+{
+ struct completion *cop = (struct completion *) arg;
+ complete(cop);
+}
+
+/*
+ * Clear initial stalls.
+ */
+static int ub_probe_clear_stall(struct ub_dev *sc, int stalled_pipe)
+{
+ int endp;
+ struct usb_ctrlrequest *cr;
+ struct completion compl;
+ struct timer_list timer;
+ int rc;
+
+ init_completion(&compl);
+
+ endp = usb_pipeendpoint(stalled_pipe);
+ if (usb_pipein (stalled_pipe))
+ endp |= USB_DIR_IN;
+
+ cr = &sc->work_cr;
+ cr->bRequestType = USB_RECIP_ENDPOINT;
+ cr->bRequest = USB_REQ_CLEAR_FEATURE;
+ cr->wValue = cpu_to_le16(USB_ENDPOINT_HALT);
+ cr->wIndex = cpu_to_le16(endp);
+ cr->wLength = cpu_to_le16(0);
+
+ usb_fill_control_urb(&sc->work_urb, sc->dev, sc->send_ctrl_pipe,
+ (unsigned char*) cr, NULL, 0, ub_probe_urb_complete, &compl);
+ sc->work_urb.transfer_flags = 0;
+ sc->work_urb.actual_length = 0;
+ sc->work_urb.error_count = 0;
+ sc->work_urb.status = 0;
+
+ init_timer(&timer);
+ timer.function = ub_probe_timeout;
+ timer.data = (unsigned long) &compl;
+ timer.expires = jiffies + UB_CTRL_TIMEOUT;
+ add_timer(&timer);
+
+ if ((rc = usb_submit_urb(&sc->work_urb, GFP_KERNEL)) != 0) {
+ printk(KERN_WARNING
+ "%s: Unable to submit a probe clear (%d)\n", sc->name, rc);
+ del_timer_sync(&timer);
+ return rc;
+ }
+
+ wait_for_completion(&compl);
+
+ del_timer_sync(&timer);
+ /*
+ * Most of the time, URB was done and dev set to NULL, and so
+ * the unlink bounces out with ENODEV. We do not call usb_kill_urb
+ * because we still think about a backport to 2.4.
+ */
+ usb_unlink_urb(&sc->work_urb);
+
+ /* reset the endpoint toggle */
+ usb_settoggle(sc->dev, endp, usb_pipeout(sc->last_pipe), 0);
+
+ return 0;
+}
+
+/*
+ * Get the pipe settings.
+ */
+static int ub_get_pipes(struct ub_dev *sc, struct usb_device *dev,
+ struct usb_interface *intf)
+{
+ struct usb_host_interface *altsetting = intf->cur_altsetting;
+ struct usb_endpoint_descriptor *ep_in = NULL;
+ struct usb_endpoint_descriptor *ep_out = NULL;
+ struct usb_endpoint_descriptor *ep;
+ int i;
+
+ /*
+ * Find the endpoints we need.
+ * We are expecting a minimum of 2 endpoints - in and out (bulk).
+ * We will ignore any others.
+ */
+ for (i = 0; i < altsetting->desc.bNumEndpoints; i++) {
+ ep = &altsetting->endpoint[i].desc;
+
+ /* Is it a BULK endpoint? */
+ if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
+ == USB_ENDPOINT_XFER_BULK) {
+ /* BULK in or out? */
+ if (ep->bEndpointAddress & USB_DIR_IN)
+ ep_in = ep;
+ else
+ ep_out = ep;
+ }
+ }
+
+ if (ep_in == NULL || ep_out == NULL) {
+ printk(KERN_NOTICE "%s: device %u failed endpoint check\n",
+ sc->name, sc->dev->devnum);
+ return -EIO;
+ }
+
+ /* Calculate and store the pipe values */
+ sc->send_ctrl_pipe = usb_sndctrlpipe(dev, 0);
+ sc->recv_ctrl_pipe = usb_rcvctrlpipe(dev, 0);
+ sc->send_bulk_pipe = usb_sndbulkpipe(dev,
+ ep_out->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
+ sc->recv_bulk_pipe = usb_rcvbulkpipe(dev,
+ ep_in->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
+
+ return 0;
+}
+
+/*
+ * Probing is done in the process context, which allows us to cheat
+ * and not to build a state machine for the discovery.
+ */
+static int ub_probe(struct usb_interface *intf,
+ const struct usb_device_id *dev_id)
+{
+ struct ub_dev *sc;
+ request_queue_t *q;
+ struct gendisk *disk;
+ int rc;
+
+ rc = -ENOMEM;
+ if ((sc = kmalloc(sizeof(struct ub_dev), GFP_KERNEL)) == NULL)
+ goto err_core;
+ memset(sc, 0, sizeof(struct ub_dev));
+ spin_lock_init(&sc->lock);
+ usb_init_urb(&sc->work_urb);
+ tasklet_init(&sc->tasklet, ub_scsi_action, (unsigned long)sc);
+ atomic_set(&sc->poison, 0);
+
+ init_timer(&sc->work_timer);
+ sc->work_timer.data = (unsigned long) sc;
+ sc->work_timer.function = ub_urb_timeout;
+
+ ub_init_completion(&sc->work_done);
+ sc->work_done.done = 1; /* A little yuk, but oh well... */
+
+ rc = -ENOSR;
+ if ((sc->id = ub_id_get()) == -1)
+ goto err_id;
+ snprintf(sc->name, 8, DRV_NAME "%c", sc->id + 'a');
+
+ sc->dev = interface_to_usbdev(intf);
+ sc->intf = intf;
+ // sc->ifnum = intf->cur_altsetting->desc.bInterfaceNumber;
+
+ usb_set_intfdata(intf, sc);
+ usb_get_dev(sc->dev);
+ // usb_get_intf(sc->intf); /* Do we need this? */
+
+ /* XXX Verify that we can handle the device (from descriptors) */
+
+ ub_get_pipes(sc, sc->dev, intf);
+
+ if (device_create_file(&sc->intf->dev, &dev_attr_diag) != 0)
+ goto err_diag;
+
+ /*
+ * At this point, all USB initialization is done, do upper layer.
+ * We really hate halfway initialized structures, so from the
+ * invariants perspective, this ub_dev is fully constructed at
+ * this point.
+ */
+
+ /*
+ * This is needed to clear toggles. It is a problem only if we do
+ * `rmmod ub && modprobe ub` without disconnects, but we like that.
+ */
+ ub_probe_clear_stall(sc, sc->recv_bulk_pipe);
+ ub_probe_clear_stall(sc, sc->send_bulk_pipe);
+
+ /*
+ * The way this is used by the startup code is a little specific.
+ * A SCSI check causes a USB stall. Our common case code sees it
+ * and clears the check, after which the device is ready for use.
+ * But if a check was not present, any command other than
+ * TEST_UNIT_READY ends with a lockup (including REQUEST_SENSE).
+ *
+ * If we neglect to clear the SCSI check, the first real command fails
+ * (which is the capacity readout). We clear that and retry, but why
+ * causing spurious retries for no reason.
+ *
+ * Revalidation may start with its own TEST_UNIT_READY, but that one
+ * has to succeed, so we clear checks with an additional one here.
+ * In any case it's not our business how revaliadation is implemented.
+ */
+ ub_sync_tur(sc);
+
+ sc->removable = 1; /* XXX Query this from the device */
+
+ ub_revalidate(sc);
+ /* This is pretty much a long term P3 */
+ printk(KERN_INFO "%s: device %u capacity nsec %ld bsize %u\n",
+ sc->name, sc->dev->devnum, sc->capacity.nsec, sc->capacity.bsize);
+
+ /*
+ * Just one disk per sc currently, but maybe more.
+ */
+ rc = -ENOMEM;
+ if ((disk = alloc_disk(UB_MINORS_PER_MAJOR)) == NULL)
+ goto err_diskalloc;
+
+ sc->disk = disk;
+ sprintf(disk->disk_name, DRV_NAME "%c", sc->id + 'a');
+ sprintf(disk->devfs_name, DEVFS_NAME "/%c", sc->id + 'a');
+ disk->major = UB_MAJOR;
+ disk->first_minor = sc->id * UB_MINORS_PER_MAJOR;
+ disk->fops = &ub_bd_fops;
+ disk->private_data = sc;
+ disk->driverfs_dev = &intf->dev;
+
+ rc = -ENOMEM;
+ if ((q = blk_init_queue(ub_bd_rq_fn, &sc->lock)) == NULL)
+ goto err_blkqinit;
+
+ disk->queue = q;
+
+ // blk_queue_bounce_limit(q, hba[i]->pdev->dma_mask);
+ blk_queue_max_hw_segments(q, UB_MAX_REQ_SG);
+ blk_queue_max_phys_segments(q, UB_MAX_REQ_SG);
+ // blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
+ blk_queue_max_sectors(q, UB_MAX_SECTORS);
+ // blk_queue_hardsect_size(q, xxxxx);
+
+ /*
+ * This is a serious infraction, caused by a deficiency in the
+ * USB sg interface (usb_sg_wait()). We plan to remove this once
+ * we get mileage on the driver and can justify a change to USB API.
+ * See blk_queue_bounce_limit() to understand this part.
+ *
+ * XXX And I still need to be aware of the DMA mask in the HC.
+ */
+ q->bounce_pfn = blk_max_low_pfn;
+ q->bounce_gfp = GFP_NOIO;
+
+ q->queuedata = sc;
+
+ set_capacity(disk, sc->capacity.nsec);
+ if (sc->removable)
+ disk->flags |= GENHD_FL_REMOVABLE;
+
+ add_disk(disk);
+
+ return 0;
+
+err_blkqinit:
+ put_disk(disk);
+err_diskalloc:
+ device_remove_file(&sc->intf->dev, &dev_attr_diag);
+err_diag:
+ usb_set_intfdata(intf, NULL);
+ // usb_put_intf(sc->intf);
+ usb_put_dev(sc->dev);
+ spin_lock_irq(&ub_lock);
+ ub_id_put(sc->id);
+ spin_unlock_irq(&ub_lock);
+err_id:
+ kfree(sc);
+err_core:
+ return rc;
+}
+
+static void ub_disconnect(struct usb_interface *intf)
+{
+ struct ub_dev *sc = usb_get_intfdata(intf);
+ struct gendisk *disk = sc->disk;
+ request_queue_t *q = disk->queue;
+ unsigned long flags;
+
+ /*
+ * Fence stall clearnings, operations triggered by unlinkings and so on.
+ * We do not attempt to unlink any URBs, because we do not trust the
+ * unlink paths in HC drivers. Also, we get -84 upon disconnect anyway.
+ */
+ atomic_set(&sc->poison, 1);
+
+ /*
+ * Blow away queued commands.
+ *
+ * Actually, this never works, because before we get here
+ * the HCD terminates outstanding URB(s). It causes our
+ * SCSI command queue to advance, commands fail to submit,
+ * and the whole queue drains. So, we just use this code to
+ * print warnings.
+ */
+ spin_lock_irqsave(&sc->lock, flags);
+ {
+ struct ub_scsi_cmd *cmd;
+ int cnt = 0;
+ while ((cmd = ub_cmdq_pop(sc)) != NULL) {
+ cmd->error = -ENOTCONN;
+ cmd->state = UB_CMDST_DONE;
+ ub_cmdtr_state(sc, cmd);
+ ub_cmdq_pop(sc);
+ (*cmd->done)(sc, cmd);
+ cnt++;
+ }
+ if (cnt != 0) {
+ printk(KERN_WARNING "%s: "
+ "%d was queued after shutdown\n", sc->name, cnt);
+ }
+ }
+ spin_unlock_irqrestore(&sc->lock, flags);
+
+ /*
+ * Unregister the upper layer, this waits for all commands to end.
+ */
+ if (disk->flags & GENHD_FL_UP)
+ del_gendisk(disk);
+ if (q)
+ blk_cleanup_queue(q);
+
+ /*
+ * If we zero disk->private_data BEFORE put_disk, we have to check
+ * for NULL all over the place in open, release, check_media and
+ * revalidate, because the block level semaphore is well inside the
+ * put_disk. But we cannot zero after the call, because *disk is gone.
+ * The sd.c is blatantly racy in this area.
+ */
+ /* disk->private_data = NULL; */
+ put_disk(disk);
+ sc->disk = NULL;
+
+ /*
+ * We really expect blk_cleanup_queue() to wait, so no amount
+ * of paranoya is too much.
+ *
+ * Taking a lock on a structure which is about to be freed
+ * is very nonsensual. Here it is largely a way to do a debug freeze,
+ * and a bracket which shows where the nonsensual code segment ends.
+ *
+ * Testing for -EINPROGRESS is always a bug, so we are bending
+ * the rules a little.
+ */
+ spin_lock_irqsave(&sc->lock, flags);
+ if (sc->work_urb.status == -EINPROGRESS) { /* janitors: ignore */
+ printk(KERN_WARNING "%s: "
+ "URB is active after disconnect\n", sc->name);
+ }
+ spin_unlock_irqrestore(&sc->lock, flags);
+
+ /*
+ * At this point there must be no commands coming from anyone
+ * and no URBs left in transit.
+ */
+
+ device_remove_file(&sc->intf->dev, &dev_attr_diag);
+ usb_set_intfdata(intf, NULL);
+ // usb_put_intf(sc->intf);
+ sc->intf = NULL;
+ usb_put_dev(sc->dev);
+ sc->dev = NULL;
+
+ spin_lock_irqsave(&ub_lock, flags);
+ if (sc->openc == 0)
+ ub_cleanup(sc);
+ spin_unlock_irqrestore(&ub_lock, flags);
+}
+
+struct usb_driver ub_driver = {
+ .owner = THIS_MODULE,
+ .name = "ub",
+ .probe = ub_probe,
+ .disconnect = ub_disconnect,
+ .id_table = ub_usb_ids,
+};
+
+static int __init ub_init(void)
+{
+ int rc;
+
+ /* P3 */ printk("ub: sizeof ub_scsi_cmd %zu ub_dev %zu\n",
+ sizeof(struct ub_scsi_cmd), sizeof(struct ub_dev));
+
+ if ((rc = register_blkdev(UB_MAJOR, DRV_NAME)) != 0)
+ goto err_regblkdev;
+ devfs_mk_dir(DEVFS_NAME);
+
+ if ((rc = usb_register(&ub_driver)) != 0)
+ goto err_register;
+
+ return 0;
+
+err_register:
+ devfs_remove(DEVFS_NAME);
+ unregister_blkdev(UB_MAJOR, DRV_NAME);
+err_regblkdev:
+ return rc;
+}
+
+static void __exit ub_exit(void)
+{
+ usb_deregister(&ub_driver);
+
+ devfs_remove(DEVFS_NAME);
+ unregister_blkdev(UB_MAJOR, DRV_NAME);
+}
+
+module_init(ub_init);
+module_exit(ub_exit);
+
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright 2004 Jon Smirl <jonsmirl@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "drm_auth.h"
+#include "drm_agpsupport.h"
+#include "drm_bufs.h"
+#include "drm_context.h"
+#include "drm_dma.h"
+#include "drm_irq.h"
+#include "drm_drawable.h"
+#include "drm_drv.h"
+#include "drm_fops.h"
+#include "drm_init.h"
+#include "drm_ioctl.h"
+#include "drm_lock.h"
+#include "drm_memory.h"
+#include "drm_proc.h"
+#include "drm_vm.h"
+#include "drm_stub.h"
+#include "drm_scatter.h"
--- /dev/null
+/* i915.h -- Intel I915 DRM template customization -*- linux-c -*-
+ */
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+
+#ifndef __I915_H__
+#define __I915_H__
+
+/* This remains constant for all DRM template files.
+ */
+#define DRM(x) i915_##x
+
+/* General customization:
+ */
+
+#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
+
+#define DRIVER_NAME "i915"
+#define DRIVER_DESC "Intel Graphics"
+#define DRIVER_DATE "20040405"
+
+/* Interface history:
+ *
+ * 1.1: Original.
+ */
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 1
+#define DRIVER_PATCHLEVEL 0
+
+#define DRIVER_IOCTLS \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_INIT)] = { i915_dma_init, 1, 1 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_FLUSH)] = { i915_flush_ioctl, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_FLIP)] = { i915_flip_bufs, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_BATCHBUFFER)] = { i915_batchbuffer, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_IRQ_EMIT)] = { i915_irq_emit, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_IRQ_WAIT)] = { i915_irq_wait, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_GETPARAM)] = { i915_getparam, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_SETPARAM)] = { i915_setparam, 1, 1 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_ALLOC)] = { i915_mem_alloc, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_FREE)] = { i915_mem_free, 1, 0 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_INIT_HEAP)] = { i915_mem_init_heap, 1, 1 }, \
+ [DRM_IOCTL_NR(DRM_IOCTL_I915_CMDBUFFER)] = { i915_cmdbuffer, 1, 0 }
+
+/* We use our own dma mechanisms, not the drm template code. However,
+ * the shared IRQ code is useful to us:
+ */
+#define __HAVE_PM 1
+
+#endif
--- /dev/null
+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
+ */
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+static inline void i915_print_status_page(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ u32 *temp = dev_priv->hw_status_page;
+
+ if (!temp) {
+ DRM_DEBUG("no status page\n");
+ return;
+ }
+
+ DRM_DEBUG("hw_status: Interrupt Status : %x\n", temp[0]);
+ DRM_DEBUG("hw_status: LpRing Head ptr : %x\n", temp[1]);
+ DRM_DEBUG("hw_status: IRing Head ptr : %x\n", temp[2]);
+ DRM_DEBUG("hw_status: Reserved : %x\n", temp[3]);
+ DRM_DEBUG("hw_status: Driver Counter : %d\n", temp[5]);
+
+}
+
+/* Really want an OS-independent resettable timer. Would like to have
+ * this loop run for (eg) 3 sec, but have the timer reset every time
+ * the head pointer changes, so that EBUSY only happens if the ring
+ * actually stalls for (eg) 3 seconds.
+ */
+int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
+ u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+ int i;
+
+ for (i = 0; i < 10000; i++) {
+ ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+ ring->space = ring->head - (ring->tail + 8);
+ if (ring->space < 0)
+ ring->space += ring->Size;
+ if (ring->space >= n)
+ return 0;
+
+ dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
+ if (ring->head != last_head)
+ i = 0;
+
+ last_head = ring->head;
+ }
+
+ return DRM_ERR(EBUSY);
+}
+
+void i915_kernel_lost_context(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
+
+ ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+ ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
+ ring->space = ring->head - (ring->tail + 8);
+ if (ring->space < 0)
+ ring->space += ring->Size;
+
+ if (ring->head == ring->tail)
+ dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
+}
+
+int i915_dma_cleanup(drm_device_t * dev)
+{
+ /* Make sure interrupts are disabled here because the uninstall ioctl
+ * may not have been called from userspace and after dev_private
+ * is freed, it's too late.
+ */
+ if (dev->irq)
+ DRM(irq_uninstall) (dev);
+
+ if (dev->dev_private) {
+ drm_i915_private_t *dev_priv =
+ (drm_i915_private_t *) dev->dev_private;
+
+ if (dev_priv->ring.virtual_start) {
+ drm_core_ioremapfree( &dev_priv->ring.map, dev);
+ }
+
+ if (dev_priv->hw_status_page) {
+ pci_free_consistent(dev->pdev, PAGE_SIZE,
+ dev_priv->hw_status_page,
+ dev_priv->dma_status_page);
+ /* Need to rewrite hardware status page */
+ I915_WRITE(0x02080, 0x1ffff000);
+ }
+
+ DRM(free) (dev->dev_private, sizeof(drm_i915_private_t),
+ DRM_MEM_DRIVER);
+
+ dev->dev_private = NULL;
+ }
+
+ return 0;
+}
+
+static int i915_initialize(drm_device_t * dev,
+ drm_i915_private_t * dev_priv,
+ drm_i915_init_t * init)
+{
+ memset(dev_priv, 0, sizeof(drm_i915_private_t));
+
+ DRM_GETSAREA();
+ if (!dev_priv->sarea) {
+ DRM_ERROR("can not find sarea!\n");
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ return DRM_ERR(EINVAL);
+ }
+
+ dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
+ if (!dev_priv->mmio_map) {
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ DRM_ERROR("can not find mmio map!\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ dev_priv->sarea_priv = (drm_i915_sarea_t *)
+ ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
+
+ dev_priv->ring.Start = init->ring_start;
+ dev_priv->ring.End = init->ring_end;
+ dev_priv->ring.Size = init->ring_size;
+ dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+
+ dev_priv->ring.map.offset = init->ring_start;
+ dev_priv->ring.map.size = init->ring_size;
+ dev_priv->ring.map.type = 0;
+ dev_priv->ring.map.flags = 0;
+ dev_priv->ring.map.mtrr = 0;
+
+ drm_core_ioremap( &dev_priv->ring.map, dev );
+
+ if (dev_priv->ring.map.handle == NULL) {
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ DRM_ERROR("can not ioremap virtual address for"
+ " ring buffer\n");
+ return DRM_ERR(ENOMEM);
+ }
+
+ dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
+
+ dev_priv->back_offset = init->back_offset;
+ dev_priv->front_offset = init->front_offset;
+ dev_priv->current_page = 0;
+ dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+
+ /* We are using separate values as placeholders for mechanisms for
+ * private backbuffer/depthbuffer usage.
+ */
+ dev_priv->use_mi_batchbuffer_start = 0;
+
+ /* Allow hardware batchbuffers unless told otherwise.
+ */
+ dev_priv->allow_batchbuffer = 1;
+
+ /* Program Hardware Status Page */
+ dev_priv->hw_status_page =
+ pci_alloc_consistent(dev->pdev, PAGE_SIZE,
+ &dev_priv->dma_status_page);
+
+ if (!dev_priv->hw_status_page) {
+ dev->dev_private = (void *)dev_priv;
+ i915_dma_cleanup(dev);
+ DRM_ERROR("Can not allocate hardware status page\n");
+ return DRM_ERR(ENOMEM);
+ }
+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+ DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+
+ I915_WRITE(0x02080, dev_priv->dma_status_page);
+ DRM_DEBUG("Enabled hardware status page\n");
+
+ dev->dev_private = (void *)dev_priv;
+
+ return 0;
+}
+
+static int i915_resume(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
+ if (!dev_priv->sarea) {
+ DRM_ERROR("can not find sarea!\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ if (!dev_priv->mmio_map) {
+ DRM_ERROR("can not find mmio map!\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ if (dev_priv->ring.map.handle == NULL) {
+ DRM_ERROR("can not ioremap virtual address for"
+ " ring buffer\n");
+ return DRM_ERR(ENOMEM);
+ }
+
+ /* Program Hardware Status Page */
+ if (!dev_priv->hw_status_page) {
+ DRM_ERROR("Can not find hardware status page\n");
+ return DRM_ERR(EINVAL);
+ }
+ DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
+
+ I915_WRITE(0x02080, dev_priv->dma_status_page);
+ DRM_DEBUG("Enabled hardware status page\n");
+
+ return 0;
+}
+
+int i915_dma_init(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv;
+ drm_i915_init_t init;
+ int retcode = 0;
+
+ DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
+ sizeof(init));
+
+ switch (init.func) {
+ case I915_INIT_DMA:
+ dev_priv = DRM(alloc) (sizeof(drm_i915_private_t),
+ DRM_MEM_DRIVER);
+ if (dev_priv == NULL)
+ return DRM_ERR(ENOMEM);
+ retcode = i915_initialize(dev, dev_priv, &init);
+ break;
+ case I915_CLEANUP_DMA:
+ retcode = i915_dma_cleanup(dev);
+ break;
+ case I915_RESUME_DMA:
+ retcode = i915_resume(dev);
+ break;
+ default:
+ retcode = -EINVAL;
+ break;
+ }
+
+ return retcode;
+}
+
+/* Implement basically the same security restrictions as hardware does
+ * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
+ *
+ * Most of the calculations below involve calculating the size of a
+ * particular instruction. It's important to get the size right as
+ * that tells us where the next instruction to check is. Any illegal
+ * instruction detected will be given a size of zero, which is a
+ * signal to abort the rest of the buffer.
+ */
+static int do_validate_cmd(int cmd)
+{
+ switch (((cmd >> 29) & 0x7)) {
+ case 0x0:
+ switch ((cmd >> 23) & 0x3f) {
+ case 0x0:
+ return 1; /* MI_NOOP */
+ case 0x4:
+ return 1; /* MI_FLUSH */
+ default:
+ return 0; /* disallow everything else */
+ }
+ break;
+ case 0x1:
+ return 0; /* reserved */
+ case 0x2:
+ return (cmd & 0xff) + 2; /* 2d commands */
+ case 0x3:
+ if (((cmd >> 24) & 0x1f) <= 0x18)
+ return 1;
+
+ switch ((cmd >> 24) & 0x1f) {
+ case 0x1c:
+ return 1;
+ case 0x1d:
+ switch ((cmd>>16)&0xff) {
+ case 0x3:
+ return (cmd & 0x1f) + 2;
+ case 0x4:
+ return (cmd & 0xf) + 2;
+ default:
+ return (cmd & 0xffff) + 2;
+ }
+ case 0x1e:
+ if (cmd & (1 << 23))
+ return (cmd & 0xffff) + 1;
+ else
+ return 1;
+ case 0x1f:
+ if ((cmd & (1 << 23)) == 0) /* inline vertices */
+ return (cmd & 0x1ffff) + 2;
+ else if (cmd & (1 << 17)) /* indirect random */
+ if ((cmd & 0xffff) == 0)
+ return 0; /* unknown length, too hard */
+ else
+ return (((cmd & 0xffff) + 1) / 2) + 1;
+ else
+ return 2; /* indirect sequential */
+ default:
+ return 0;
+ }
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int validate_cmd(int cmd)
+{
+ int ret = do_validate_cmd(cmd);
+
+/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
+
+ return ret;
+}
+
+static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ int i;
+ RING_LOCALS;
+
+ for (i = 0; i < dwords;) {
+ int cmd, sz;
+
+ if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
+ return DRM_ERR(EINVAL);
+
+/* printk("%d/%d ", i, dwords); */
+
+ if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
+ return DRM_ERR(EINVAL);
+
+ BEGIN_LP_RING(sz);
+ OUT_RING(cmd);
+
+ while (++i, --sz) {
+ if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
+ sizeof(cmd))) {
+ return DRM_ERR(EINVAL);
+ }
+ OUT_RING(cmd);
+ }
+ ADVANCE_LP_RING();
+ }
+
+ return 0;
+}
+
+static int i915_emit_box(drm_device_t * dev,
+ drm_clip_rect_t __user * boxes,
+ int i, int DR1, int DR4)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_clip_rect_t box;
+ RING_LOCALS;
+
+ if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
+ return EFAULT;
+ }
+
+ if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
+ DRM_ERROR("Bad box %d,%d..%d,%d\n",
+ box.x1, box.y1, box.x2, box.y2);
+ return DRM_ERR(EINVAL);
+ }
+
+ BEGIN_LP_RING(6);
+ OUT_RING(GFX_OP_DRAWRECT_INFO);
+ OUT_RING(DR1);
+ OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
+ OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
+ OUT_RING(DR4);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+
+ return 0;
+}
+
+static int i915_dispatch_cmdbuffer(drm_device_t * dev,
+ drm_i915_cmdbuffer_t * cmd)
+{
+ int nbox = cmd->num_cliprects;
+ int i = 0, count, ret;
+
+ if (cmd->sz & 0x3) {
+ DRM_ERROR("alignment");
+ return DRM_ERR(EINVAL);
+ }
+
+ i915_kernel_lost_context(dev);
+
+ count = nbox ? nbox : 1;
+
+ for (i = 0; i < count; i++) {
+ if (i < nbox) {
+ ret = i915_emit_box(dev, cmd->cliprects, i,
+ cmd->DR1, cmd->DR4);
+ if (ret)
+ return ret;
+ }
+
+ ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int i915_dispatch_batchbuffer(drm_device_t * dev,
+ drm_i915_batchbuffer_t * batch)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_clip_rect_t __user *boxes = batch->cliprects;
+ int nbox = batch->num_cliprects;
+ int i = 0, count;
+ RING_LOCALS;
+
+ if ((batch->start | batch->used) & 0x7) {
+ DRM_ERROR("alignment");
+ return DRM_ERR(EINVAL);
+ }
+
+ i915_kernel_lost_context(dev);
+
+ count = nbox ? nbox : 1;
+
+ for (i = 0; i < count; i++) {
+ if (i < nbox) {
+ int ret = i915_emit_box(dev, boxes, i,
+ batch->DR1, batch->DR4);
+ if (ret)
+ return ret;
+ }
+
+ if (dev_priv->use_mi_batchbuffer_start) {
+ BEGIN_LP_RING(2);
+ OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
+ OUT_RING(batch->start | MI_BATCH_NON_SECURE);
+ ADVANCE_LP_RING();
+ } else {
+ BEGIN_LP_RING(4);
+ OUT_RING(MI_BATCH_BUFFER);
+ OUT_RING(batch->start | MI_BATCH_NON_SECURE);
+ OUT_RING(batch->start + batch->used - 4);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+ }
+ }
+
+ dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
+
+ BEGIN_LP_RING(4);
+ OUT_RING(CMD_STORE_DWORD_IDX);
+ OUT_RING(20);
+ OUT_RING(dev_priv->counter);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+
+ return 0;
+}
+
+static int i915_dispatch_flip(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ RING_LOCALS;
+
+ DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
+ __FUNCTION__,
+ dev_priv->current_page,
+ dev_priv->sarea_priv->pf_current_page);
+
+ i915_kernel_lost_context(dev);
+
+ BEGIN_LP_RING(2);
+ OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+
+ BEGIN_LP_RING(6);
+ OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
+ OUT_RING(0);
+ if (dev_priv->current_page == 0) {
+ OUT_RING(dev_priv->back_offset);
+ dev_priv->current_page = 1;
+ } else {
+ OUT_RING(dev_priv->front_offset);
+ dev_priv->current_page = 0;
+ }
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+
+ BEGIN_LP_RING(2);
+ OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+
+ dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
+
+ BEGIN_LP_RING(4);
+ OUT_RING(CMD_STORE_DWORD_IDX);
+ OUT_RING(20);
+ OUT_RING(dev_priv->counter);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+
+ dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+ return 0;
+}
+
+static int i915_quiescent(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ i915_kernel_lost_context(dev);
+ return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
+}
+
+int i915_flush_ioctl(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+
+ if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+ DRM_ERROR("i915_flush_ioctl called without lock held\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ return i915_quiescent(dev);
+}
+
+int i915_batchbuffer(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ u32 *hw_status = dev_priv->hw_status_page;
+ drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
+ dev_priv->sarea_priv;
+ drm_i915_batchbuffer_t batch;
+ int ret;
+
+ if (!dev_priv->allow_batchbuffer) {
+ DRM_ERROR("Batchbuffer ioctl disabled\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
+ sizeof(batch));
+
+ DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
+ batch.start, batch.used, batch.num_cliprects);
+
+ if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+ DRM_ERROR("i915_batchbuffer called without lock held\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
+ batch.num_cliprects *
+ sizeof(drm_clip_rect_t)))
+ return DRM_ERR(EFAULT);
+
+ ret = i915_dispatch_batchbuffer(dev, &batch);
+
+ sarea_priv->last_dispatch = (int)hw_status[5];
+ return ret;
+}
+
+int i915_cmdbuffer(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ u32 *hw_status = dev_priv->hw_status_page;
+ drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
+ dev_priv->sarea_priv;
+ drm_i915_cmdbuffer_t cmdbuf;
+ int ret;
+
+ DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
+ sizeof(cmdbuf));
+
+ DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
+ cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
+
+ if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+ DRM_ERROR("i915_cmdbuffer called without lock held\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ if (cmdbuf.num_cliprects &&
+ DRM_VERIFYAREA_READ(cmdbuf.cliprects,
+ cmdbuf.num_cliprects *
+ sizeof(drm_clip_rect_t))) {
+ DRM_ERROR("Fault accessing cliprects\n");
+ return DRM_ERR(EFAULT);
+ }
+
+ ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
+ if (ret) {
+ DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
+ return ret;
+ }
+
+ sarea_priv->last_dispatch = (int)hw_status[5];
+ return 0;
+}
+
+int i915_do_cleanup_pageflip(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ DRM_DEBUG("%s\n", __FUNCTION__);
+ if (dev_priv->current_page != 0)
+ i915_dispatch_flip(dev);
+
+ return 0;
+}
+
+int i915_flip_bufs(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+
+ DRM_DEBUG("%s\n", __FUNCTION__);
+ if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+ DRM_ERROR("i915_flip_buf called without lock held\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ return i915_dispatch_flip(dev);
+}
+
+int i915_getparam(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_getparam_t param;
+ int value;
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
+ sizeof(param));
+
+ switch (param.param) {
+ case I915_PARAM_IRQ_ACTIVE:
+ value = dev->irq ? 1 : 0;
+ break;
+ case I915_PARAM_ALLOW_BATCHBUFFER:
+ value = dev_priv->allow_batchbuffer ? 1 : 0;
+ break;
+ default:
+ DRM_ERROR("Unkown parameter %d\n", param.param);
+ return DRM_ERR(EINVAL);
+ }
+
+ if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
+ DRM_ERROR("DRM_COPY_TO_USER failed\n");
+ return DRM_ERR(EFAULT);
+ }
+
+ return 0;
+}
+
+int i915_setparam(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_setparam_t param;
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
+ sizeof(param));
+
+ switch (param.param) {
+ case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
+ dev_priv->use_mi_batchbuffer_start = param.value;
+ break;
+ case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
+ dev_priv->tex_lru_log_granularity = param.value;
+ break;
+ case I915_SETPARAM_ALLOW_BATCHBUFFER:
+ dev_priv->allow_batchbuffer = param.value;
+ break;
+ default:
+ DRM_ERROR("unknown parameter %d\n", param.param);
+ return DRM_ERR(EINVAL);
+ }
+
+ return 0;
+}
+
+static void i915_driver_pretakedown(drm_device_t *dev)
+{
+ if ( dev->dev_private ) {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ i915_mem_takedown( &(dev_priv->agp_heap) );
+ }
+ i915_dma_cleanup( dev );
+}
+
+static void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp)
+{
+ if ( dev->dev_private ) {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ i915_mem_release( dev, filp, dev_priv->agp_heap );
+ }
+}
+
+void i915_driver_register_fns(drm_device_t *dev)
+{
+ dev->driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED;
+ dev->fn_tbl.pretakedown = i915_driver_pretakedown;
+ dev->fn_tbl.prerelease = i915_driver_prerelease;
+ dev->fn_tbl.irq_preinstall = i915_driver_irq_preinstall;
+ dev->fn_tbl.irq_postinstall = i915_driver_irq_postinstall;
+ dev->fn_tbl.irq_uninstall = i915_driver_irq_uninstall;
+ dev->fn_tbl.irq_handler = i915_driver_irq_handler;
+
+ dev->counters += 4;
+ dev->types[6] = _DRM_STAT_IRQ;
+ dev->types[7] = _DRM_STAT_PRIMARY;
+ dev->types[8] = _DRM_STAT_SECONDARY;
+ dev->types[9] = _DRM_STAT_DMA;
+}
--- /dev/null
+#ifndef _I915_DRM_H_
+#define _I915_DRM_H_
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ */
+
+#include "drm.h"
+
+/* Each region is a minimum of 16k, and there are at most 255 of them.
+ */
+#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
+ * of chars for next/prev indices */
+#define I915_LOG_MIN_TEX_REGION_SIZE 14
+
+typedef struct _drm_i915_init {
+ enum {
+ I915_INIT_DMA = 0x01,
+ I915_CLEANUP_DMA = 0x02,
+ I915_RESUME_DMA = 0x03
+ } func;
+ unsigned int mmio_offset;
+ int sarea_priv_offset;
+ unsigned int ring_start;
+ unsigned int ring_end;
+ unsigned int ring_size;
+ unsigned int front_offset;
+ unsigned int back_offset;
+ unsigned int depth_offset;
+ unsigned int w;
+ unsigned int h;
+ unsigned int pitch;
+ unsigned int pitch_bits;
+ unsigned int back_pitch;
+ unsigned int depth_pitch;
+ unsigned int cpp;
+ unsigned int chipset;
+} drm_i915_init_t;
+
+typedef struct _drm_i915_sarea {
+ drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
+ int last_upload; /* last time texture was uploaded */
+ int last_enqueue; /* last time a buffer was enqueued */
+ int last_dispatch; /* age of the most recently dispatched buffer */
+ int ctxOwner; /* last context to upload state */
+ int texAge;
+ int pf_enabled; /* is pageflipping allowed? */
+ int pf_active;
+ int pf_current_page; /* which buffer is being displayed? */
+ int perf_boxes; /* performance boxes to be displayed */
+} drm_i915_sarea_t;
+
+/* Flags for perf_boxes
+ */
+#define I915_BOX_RING_EMPTY 0x1
+#define I915_BOX_FLIP 0x2
+#define I915_BOX_WAIT 0x4
+#define I915_BOX_TEXTURE_LOAD 0x8
+#define I915_BOX_LOST_CONTEXT 0x10
+
+/* I915 specific ioctls
+ * The device specific ioctl range is 0x40 to 0x79.
+ */
+#define DRM_IOCTL_I915_INIT DRM_IOW( 0x40, drm_i915_init_t)
+#define DRM_IOCTL_I915_FLUSH DRM_IO ( 0x41)
+#define DRM_IOCTL_I915_FLIP DRM_IO ( 0x42)
+#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( 0x43, drm_i915_batchbuffer_t)
+#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(0x44, drm_i915_irq_emit_t)
+#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( 0x45, drm_i915_irq_wait_t)
+#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(0x46, drm_i915_getparam_t)
+#define DRM_IOCTL_I915_SETPARAM DRM_IOW( 0x47, drm_i915_setparam_t)
+#define DRM_IOCTL_I915_ALLOC DRM_IOWR(0x48, drm_i915_mem_alloc_t)
+#define DRM_IOCTL_I915_FREE DRM_IOW( 0x49, drm_i915_mem_free_t)
+#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( 0x4a, drm_i915_mem_init_heap_t)
+#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( 0x4b, drm_i915_cmdbuffer_t)
+
+/* Allow drivers to submit batchbuffers directly to hardware, relying
+ * on the security mechanisms provided by hardware.
+ */
+typedef struct _drm_i915_batchbuffer {
+ int start; /* agp offset */
+ int used; /* nr bytes in use */
+ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
+ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
+ int num_cliprects; /* mulitpass with multiple cliprects? */
+ drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
+} drm_i915_batchbuffer_t;
+
+/* As above, but pass a pointer to userspace buffer which can be
+ * validated by the kernel prior to sending to hardware.
+ */
+typedef struct _drm_i915_cmdbuffer {
+ char __user *buf; /* pointer to userspace command buffer */
+ int sz; /* nr bytes in buf */
+ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
+ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
+ int num_cliprects; /* mulitpass with multiple cliprects? */
+ drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
+} drm_i915_cmdbuffer_t;
+
+/* Userspace can request & wait on irq's:
+ */
+typedef struct drm_i915_irq_emit {
+ int __user *irq_seq;
+} drm_i915_irq_emit_t;
+
+typedef struct drm_i915_irq_wait {
+ int irq_seq;
+} drm_i915_irq_wait_t;
+
+/* Ioctl to query kernel params:
+ */
+#define I915_PARAM_IRQ_ACTIVE 1
+#define I915_PARAM_ALLOW_BATCHBUFFER 2
+
+typedef struct drm_i915_getparam {
+ int param;
+ int __user *value;
+} drm_i915_getparam_t;
+
+/* Ioctl to set kernel params:
+ */
+#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
+#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
+#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
+
+typedef struct drm_i915_setparam {
+ int param;
+ int value;
+} drm_i915_setparam_t;
+
+/* A memory manager for regions of shared memory:
+ */
+#define I915_MEM_REGION_AGP 1
+
+typedef struct drm_i915_mem_alloc {
+ int region;
+ int alignment;
+ int size;
+ int __user *region_offset; /* offset from start of fb or agp */
+} drm_i915_mem_alloc_t;
+
+typedef struct drm_i915_mem_free {
+ int region;
+ int region_offset;
+} drm_i915_mem_free_t;
+
+typedef struct drm_i915_mem_init_heap {
+ int region;
+ int size;
+ int start;
+} drm_i915_mem_init_heap_t;
+
+#endif /* _I915_DRM_H_ */
--- /dev/null
+/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
+ */
+
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+#include "drm_core.h"
--- /dev/null
+/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
+ */
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+
+#ifndef _I915_DRV_H_
+#define _I915_DRV_H_
+
+typedef struct _drm_i915_ring_buffer {
+ int tail_mask;
+ unsigned long Start;
+ unsigned long End;
+ unsigned long Size;
+ u8 *virtual_start;
+ int head;
+ int tail;
+ int space;
+ drm_local_map_t map;
+} drm_i915_ring_buffer_t;
+
+struct mem_block {
+ struct mem_block *next;
+ struct mem_block *prev;
+ int start;
+ int size;
+ DRMFILE filp; /* 0: free, -1: heap, other: real files */
+};
+
+typedef struct drm_i915_private {
+ drm_local_map_t *sarea;
+ drm_local_map_t *mmio_map;
+
+ drm_i915_sarea_t *sarea_priv;
+ drm_i915_ring_buffer_t ring;
+
+ void *hw_status_page;
+ unsigned long counter;
+ dma_addr_t dma_status_page;
+
+ int back_offset;
+ int front_offset;
+ int current_page;
+ int page_flipping;
+ int use_mi_batchbuffer_start;
+
+ wait_queue_head_t irq_queue;
+ atomic_t irq_received;
+ atomic_t irq_emitted;
+
+ int tex_lru_log_granularity;
+ int allow_batchbuffer;
+ struct mem_block *agp_heap;
+} drm_i915_private_t;
+
+ /* i915_dma.c */
+extern int i915_dma_init(DRM_IOCTL_ARGS);
+extern int i915_dma_cleanup(drm_device_t * dev);
+extern int i915_flush_ioctl(DRM_IOCTL_ARGS);
+extern int i915_batchbuffer(DRM_IOCTL_ARGS);
+extern int i915_flip_bufs(DRM_IOCTL_ARGS);
+extern int i915_getparam(DRM_IOCTL_ARGS);
+extern int i915_setparam(DRM_IOCTL_ARGS);
+extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
+extern void i915_kernel_lost_context(drm_device_t * dev);
+
+/* i915_irq.c */
+extern int i915_irq_emit(DRM_IOCTL_ARGS);
+extern int i915_irq_wait(DRM_IOCTL_ARGS);
+extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
+extern int i915_emit_irq(drm_device_t * dev);
+
+extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
+extern void i915_driver_irq_preinstall(drm_device_t *dev);
+extern void i915_driver_irq_postinstall(drm_device_t *dev);
+extern void i915_driver_irq_uninstall(drm_device_t *dev);
+
+/* i915_mem.c */
+extern int i915_mem_alloc(DRM_IOCTL_ARGS);
+extern int i915_mem_free(DRM_IOCTL_ARGS);
+extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
+extern void i915_mem_takedown(struct mem_block **heap);
+extern void i915_mem_release(drm_device_t * dev,
+ DRMFILE filp, struct mem_block *heap);
+
+#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
+#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
+#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
+#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
+
+#define I915_VERBOSE 0
+
+#define RING_LOCALS unsigned int outring, ringmask, outcount; \
+ volatile char *virt;
+
+#define BEGIN_LP_RING(n) do { \
+ if (I915_VERBOSE) \
+ DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
+ n, __FUNCTION__); \
+ if (dev_priv->ring.space < n*4) \
+ i915_wait_ring(dev, n*4, __FUNCTION__); \
+ outcount = 0; \
+ outring = dev_priv->ring.tail; \
+ ringmask = dev_priv->ring.tail_mask; \
+ virt = dev_priv->ring.virtual_start; \
+} while (0)
+
+#define OUT_RING(n) do { \
+ if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
+ *(volatile unsigned int *)(virt + outring) = n; \
+ outcount++; \
+ outring += 4; \
+ outring &= ringmask; \
+} while (0)
+
+#define ADVANCE_LP_RING() do { \
+ if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
+ dev_priv->ring.tail = outring; \
+ dev_priv->ring.space -= outcount * 4; \
+ I915_WRITE(LP_RING + RING_TAIL, outring); \
+} while(0)
+
+extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
+
+#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
+#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
+#define CMD_REPORT_HEAD (7<<23)
+#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
+#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
+
+#define INST_PARSER_CLIENT 0x00000000
+#define INST_OP_FLUSH 0x02000000
+#define INST_FLUSH_MAP_CACHE 0x00000001
+
+#define BB1_START_ADDR_MASK (~0x7)
+#define BB1_PROTECTED (1<<0)
+#define BB1_UNPROTECTED (0<<0)
+#define BB2_END_ADDR_MASK (~0x7)
+
+#define I915REG_HWSTAM 0x02098
+#define I915REG_INT_IDENTITY_R 0x020a4
+#define I915REG_INT_MASK_R 0x020a8
+#define I915REG_INT_ENABLE_R 0x020a0
+
+#define SRX_INDEX 0x3c4
+#define SRX_DATA 0x3c5
+#define SR01 1
+#define SR01_SCREEN_OFF (1<<5)
+
+#define PPCR 0x61204
+#define PPCR_ON (1<<0)
+
+#define ADPA 0x61100
+#define ADPA_DPMS_MASK (~(3<<10))
+#define ADPA_DPMS_ON (0<<10)
+#define ADPA_DPMS_SUSPEND (1<<10)
+#define ADPA_DPMS_STANDBY (2<<10)
+#define ADPA_DPMS_OFF (3<<10)
+
+#define NOPID 0x2094
+#define LP_RING 0x2030
+#define HP_RING 0x2040
+#define RING_TAIL 0x00
+#define TAIL_ADDR 0x001FFFF8
+#define RING_HEAD 0x04
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START 0x08
+#define START_ADDR 0x0xFFFFF000
+#define RING_LEN 0x0C
+#define RING_NR_PAGES 0x001FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
+
+#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define SC_UPDATE_SCISSOR (0x1<<1)
+#define SC_ENABLE_MASK (0x1<<0)
+#define SC_ENABLE (0x1<<0)
+
+#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define SCI_YMIN_MASK (0xffff<<16)
+#define SCI_XMIN_MASK (0xffff<<0)
+#define SCI_YMAX_MASK (0xffff<<16)
+#define SCI_XMAX_MASK (0xffff<<0)
+
+#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
+#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
+#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+
+#define MI_BATCH_BUFFER ((0x30<<23)|1)
+#define MI_BATCH_BUFFER_START (0x31<<23)
+#define MI_BATCH_BUFFER_END (0xA<<23)
+#define MI_BATCH_NON_SECURE (1)
+
+#define MI_WAIT_FOR_EVENT ((0x3<<23))
+#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
+
+#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
+
+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
+#define ASYNC_FLIP (1<<22)
+
+#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
+
+#endif
--- /dev/null
+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
+ */
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+#define USER_INT_FLAG 0x2
+#define MAX_NOPID ((u32)~0)
+#define READ_BREADCRUMB(dev_priv) (((u32*)(dev_priv->hw_status_page))[5])
+
+irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
+{
+ drm_device_t *dev = (drm_device_t *) arg;
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ u16 temp;
+
+ temp = I915_READ16(I915REG_INT_IDENTITY_R);
+ temp &= USER_INT_FLAG;
+
+ DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
+
+ if (temp == 0)
+ return IRQ_NONE;
+
+ I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
+ DRM_WAKEUP(&dev_priv->irq_queue);
+
+ return IRQ_HANDLED;
+}
+
+int i915_emit_irq(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ u32 ret;
+ RING_LOCALS;
+
+ i915_kernel_lost_context(dev);
+
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
+ ret = dev_priv->counter;
+
+ BEGIN_LP_RING(2);
+ OUT_RING(0);
+ OUT_RING(GFX_OP_USER_INTERRUPT);
+ ADVANCE_LP_RING();
+
+ return ret;
+}
+
+int i915_wait_irq(drm_device_t * dev, int irq_nr)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ int ret = 0;
+
+ DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr,
+ READ_BREADCRUMB(dev_priv));
+
+ if (READ_BREADCRUMB(dev_priv) >= irq_nr)
+ return 0;
+
+ dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
+ DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
+ READ_BREADCRUMB(dev_priv) >= irq_nr);
+
+ if (ret == DRM_ERR(EBUSY)) {
+ DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n",
+ __FUNCTION__,
+ READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
+ }
+
+ dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+ return ret;
+}
+
+/* Needs the lock as it touches the ring.
+ */
+int i915_irq_emit(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_irq_emit_t emit;
+ int result;
+
+ if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+ DRM_ERROR("i915_irq_emit called without lock held\n");
+ return DRM_ERR(EINVAL);
+ }
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(emit, (drm_i915_irq_emit_t __user *) data,
+ sizeof(emit));
+
+ result = i915_emit_irq(dev);
+
+ if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
+ DRM_ERROR("copy_to_user\n");
+ return DRM_ERR(EFAULT);
+ }
+
+ return 0;
+}
+
+/* Doesn't need the hardware lock.
+ */
+int i915_irq_wait(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_irq_wait_t irqwait;
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_i915_irq_wait_t __user *) data,
+ sizeof(irqwait));
+
+ return i915_wait_irq(dev, irqwait.irq_seq);
+}
+
+/* drm_dma.h hooks
+*/
+void i915_driver_irq_preinstall(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ I915_WRITE16(I915REG_HWSTAM, 0xfffe);
+ I915_WRITE16(I915REG_INT_MASK_R, 0x0);
+ I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+}
+
+void i915_driver_irq_postinstall(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG);
+ DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+}
+
+void i915_driver_irq_uninstall(drm_device_t * dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ if (!dev_priv)
+ return;
+
+ I915_WRITE16(I915REG_HWSTAM, 0xffff);
+ I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
+ I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+}
--- /dev/null
+/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*-
+ */
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ **************************************************************************/
+
+#include "i915.h"
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+/* This memory manager is integrated into the global/local lru
+ * mechanisms used by the clients. Specifically, it operates by
+ * setting the 'in_use' fields of the global LRU to indicate whether
+ * this region is privately allocated to a client.
+ *
+ * This does require the client to actually respect that field.
+ *
+ * Currently no effort is made to allocate 'private' memory in any
+ * clever way - the LRU information isn't used to determine which
+ * block to allocate, and the ring is drained prior to allocations --
+ * in other words allocation is expensive.
+ */
+static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ drm_tex_region_t *list;
+ unsigned shift, nr;
+ unsigned start;
+ unsigned end;
+ unsigned i;
+ int age;
+
+ shift = dev_priv->tex_lru_log_granularity;
+ nr = I915_NR_TEX_REGIONS;
+
+ start = p->start >> shift;
+ end = (p->start + p->size - 1) >> shift;
+
+ age = ++sarea_priv->texAge;
+ list = sarea_priv->texList;
+
+ /* Mark the regions with the new flag and update their age. Move
+ * them to head of list to preserve LRU semantics.
+ */
+ for (i = start; i <= end; i++) {
+ list[i].in_use = in_use;
+ list[i].age = age;
+
+ /* remove_from_list(i)
+ */
+ list[(unsigned)list[i].next].prev = list[i].prev;
+ list[(unsigned)list[i].prev].next = list[i].next;
+
+ /* insert_at_head(list, i)
+ */
+ list[i].prev = nr;
+ list[i].next = list[nr].next;
+ list[(unsigned)list[nr].next].prev = i;
+ list[nr].next = i;
+ }
+}
+
+/* Very simple allocator for agp memory, working on a static range
+ * already mapped into each client's address space.
+ */
+
+static struct mem_block *split_block(struct mem_block *p, int start, int size,
+ DRMFILE filp)
+{
+ /* Maybe cut off the start of an existing block */
+ if (start > p->start) {
+ struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock));
+ if (!newblock)
+ goto out;
+ newblock->start = start;
+ newblock->size = p->size - (start - p->start);
+ newblock->filp = NULL;
+ newblock->next = p->next;
+ newblock->prev = p;
+ p->next->prev = newblock;
+ p->next = newblock;
+ p->size -= newblock->size;
+ p = newblock;
+ }
+
+ /* Maybe cut off the end of an existing block */
+ if (size < p->size) {
+ struct mem_block *newblock = DRM_MALLOC(sizeof(*newblock));
+ if (!newblock)
+ goto out;
+ newblock->start = start + size;
+ newblock->size = p->size - size;
+ newblock->filp = NULL;
+ newblock->next = p->next;
+ newblock->prev = p;
+ p->next->prev = newblock;
+ p->next = newblock;
+ p->size = size;
+ }
+
+ out:
+ /* Our block is in the middle */
+ p->filp = filp;
+ return p;
+}
+
+static struct mem_block *alloc_block(struct mem_block *heap, int size,
+ int align2, DRMFILE filp)
+{
+ struct mem_block *p;
+ int mask = (1 << align2) - 1;
+
+ for (p = heap->next; p != heap; p = p->next) {
+ int start = (p->start + mask) & ~mask;
+ if (p->filp == NULL && start + size <= p->start + p->size)
+ return split_block(p, start, size, filp);
+ }
+
+ return NULL;
+}
+
+static struct mem_block *find_block(struct mem_block *heap, int start)
+{
+ struct mem_block *p;
+
+ for (p = heap->next; p != heap; p = p->next)
+ if (p->start == start)
+ return p;
+
+ return NULL;
+}
+
+static void free_block(struct mem_block *p)
+{
+ p->filp = NULL;
+
+ /* Assumes a single contiguous range. Needs a special filp in
+ * 'heap' to stop it being subsumed.
+ */
+ if (p->next->filp == NULL) {
+ struct mem_block *q = p->next;
+ p->size += q->size;
+ p->next = q->next;
+ p->next->prev = p;
+ DRM_FREE(q, sizeof(*q));
+ }
+
+ if (p->prev->filp == NULL) {
+ struct mem_block *q = p->prev;
+ q->size += p->size;
+ q->next = p->next;
+ q->next->prev = q;
+ DRM_FREE(p, sizeof(*q));
+ }
+}
+
+/* Initialize. How to check for an uninitialized heap?
+ */
+static int init_heap(struct mem_block **heap, int start, int size)
+{
+ struct mem_block *blocks = DRM_MALLOC(sizeof(*blocks));
+
+ if (!blocks)
+ return -ENOMEM;
+
+ *heap = DRM_MALLOC(sizeof(**heap));
+ if (!*heap) {
+ DRM_FREE(blocks, sizeof(*blocks));
+ return -ENOMEM;
+ }
+
+ blocks->start = start;
+ blocks->size = size;
+ blocks->filp = NULL;
+ blocks->next = blocks->prev = *heap;
+
+ memset(*heap, 0, sizeof(**heap));
+ (*heap)->filp = (DRMFILE) - 1;
+ (*heap)->next = (*heap)->prev = blocks;
+ return 0;
+}
+
+/* Free all blocks associated with the releasing file.
+ */
+void i915_mem_release(drm_device_t * dev, DRMFILE filp, struct mem_block *heap)
+{
+ struct mem_block *p;
+
+ if (!heap || !heap->next)
+ return;
+
+ for (p = heap->next; p != heap; p = p->next) {
+ if (p->filp == filp) {
+ p->filp = NULL;
+ mark_block(dev, p, 0);
+ }
+ }
+
+ /* Assumes a single contiguous range. Needs a special filp in
+ * 'heap' to stop it being subsumed.
+ */
+ for (p = heap->next; p != heap; p = p->next) {
+ while (p->filp == NULL && p->next->filp == NULL) {
+ struct mem_block *q = p->next;
+ p->size += q->size;
+ p->next = q->next;
+ p->next->prev = p;
+ DRM_FREE(q, sizeof(*q));
+ }
+ }
+}
+
+/* Shutdown.
+ */
+void i915_mem_takedown(struct mem_block **heap)
+{
+ struct mem_block *p;
+
+ if (!*heap)
+ return;
+
+ for (p = (*heap)->next; p != *heap;) {
+ struct mem_block *q = p;
+ p = p->next;
+ DRM_FREE(q, sizeof(*q));
+ }
+
+ DRM_FREE(*heap, sizeof(**heap));
+ *heap = NULL;
+}
+
+static struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region)
+{
+ switch (region) {
+ case I915_MEM_REGION_AGP:
+ return &dev_priv->agp_heap;
+ default:
+ return NULL;
+ }
+}
+
+/* IOCTL HANDLERS */
+
+int i915_mem_alloc(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_mem_alloc_t alloc;
+ struct mem_block *block, **heap;
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(alloc, (drm_i915_mem_alloc_t __user *) data,
+ sizeof(alloc));
+
+ heap = get_heap(dev_priv, alloc.region);
+ if (!heap || !*heap)
+ return DRM_ERR(EFAULT);
+
+ /* Make things easier on ourselves: all allocations at least
+ * 4k aligned.
+ */
+ if (alloc.alignment < 12)
+ alloc.alignment = 12;
+
+ block = alloc_block(*heap, alloc.size, alloc.alignment, filp);
+
+ if (!block)
+ return DRM_ERR(ENOMEM);
+
+ mark_block(dev, block, 1);
+
+ if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) {
+ DRM_ERROR("copy_to_user\n");
+ return DRM_ERR(EFAULT);
+ }
+
+ return 0;
+}
+
+int i915_mem_free(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_mem_free_t memfree;
+ struct mem_block *block, **heap;
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(memfree, (drm_i915_mem_free_t __user *) data,
+ sizeof(memfree));
+
+ heap = get_heap(dev_priv, memfree.region);
+ if (!heap || !*heap)
+ return DRM_ERR(EFAULT);
+
+ block = find_block(*heap, memfree.region_offset);
+ if (!block)
+ return DRM_ERR(EFAULT);
+
+ if (block->filp != filp)
+ return DRM_ERR(EPERM);
+
+ mark_block(dev, block, 0);
+ free_block(block);
+ return 0;
+}
+
+int i915_mem_init_heap(DRM_IOCTL_ARGS)
+{
+ DRM_DEVICE;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ drm_i915_mem_init_heap_t initheap;
+ struct mem_block **heap;
+
+ if (!dev_priv) {
+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+ return DRM_ERR(EINVAL);
+ }
+
+ DRM_COPY_FROM_USER_IOCTL(initheap,
+ (drm_i915_mem_init_heap_t __user *) data,
+ sizeof(initheap));
+
+ heap = get_heap(dev_priv, initheap.region);
+ if (!heap)
+ return DRM_ERR(EFAULT);
+
+ if (*heap) {
+ DRM_ERROR("heap already initialized?");
+ return DRM_ERR(EFAULT);
+ }
+
+ return init_heap(heap, initheap.start, initheap.size);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004 Hollis Blanchard <hollisb@us.ibm.com>, IBM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/* Host Virtual Serial Interface (HVSI) is a protocol between the hosted OS
+ * and the service processor on IBM pSeries servers. On these servers, there
+ * are no serial ports under the OS's control, and sometimes there is no other
+ * console available either. However, the service processor has two standard
+ * serial ports, so this over-complicated protocol allows the OS to control
+ * those ports by proxy.
+ *
+ * Besides data, the procotol supports the reading/writing of the serial
+ * port's DTR line, and the reading of the CD line. This is to allow the OS to
+ * control a modem attached to the service processor's serial port. Note that
+ * the OS cannot change the speed of the port through this protocol.
+ */
+
+/* TODO:
+ * test FSP reset
+ * add udbg support for xmon/kdb
+ */
+
+#undef DEBUG
+
+#include <linux/console.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/major.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/sysrq.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <asm/hvcall.h>
+#include <asm/hvconsole.h>
+#include <asm/prom.h>
+#include <asm/uaccess.h>
+#include <asm/vio.h>
+
+#define HVSI_MAJOR 229
+#define HVSI_MINOR 128
+#define MAX_NR_HVSI_CONSOLES 4
+
+#define HVSI_TIMEOUT (5*HZ)
+#define HVSI_VERSION 1
+#define HVSI_MAX_PACKET 256
+#define HVSI_MAX_READ 16
+#define HVSI_MAX_OUTGOING_DATA 12
+#define N_OUTBUF 12
+
+/*
+ * we pass data via two 8-byte registers, so we would like our char arrays
+ * properly aligned for those loads.
+ */
+#define __ALIGNED__ __attribute__((__aligned__(sizeof(long))))
+
+struct hvsi_struct {
+ struct work_struct writer;
+ wait_queue_head_t emptyq; /* woken when outbuf is emptied */
+ wait_queue_head_t stateq; /* woken when HVSI state changes */
+ spinlock_t lock;
+ int index;
+ struct tty_struct *tty;
+ unsigned int count;
+ uint8_t throttle_buf[128];
+ uint8_t outbuf[N_OUTBUF]; /* to implement write_room and chars_in_buffer */
+ /* inbuf is for packet reassembly. leave a little room for leftovers. */
+ uint8_t inbuf[HVSI_MAX_PACKET + HVSI_MAX_READ];
+ uint8_t *inbuf_end;
+ int n_throttle;
+ int n_outbuf;
+ uint32_t vtermno;
+ uint32_t virq;
+ atomic_t seqno; /* HVSI packet sequence number */
+ uint16_t mctrl;
+ uint8_t state; /* HVSI protocol state */
+ uint8_t flags;
+#ifdef CONFIG_MAGIC_SYSRQ
+ uint8_t sysrq;
+#endif /* CONFIG_MAGIC_SYSRQ */
+};
+static struct hvsi_struct hvsi_ports[MAX_NR_HVSI_CONSOLES];
+
+static struct tty_driver *hvsi_driver;
+static int hvsi_count;
+static int (*hvsi_wait)(struct hvsi_struct *hp, int state);
+
+enum HVSI_PROTOCOL_STATE {
+ HVSI_CLOSED,
+ HVSI_WAIT_FOR_VER_RESPONSE,
+ HVSI_WAIT_FOR_VER_QUERY,
+ HVSI_OPEN,
+ HVSI_WAIT_FOR_MCTRL_RESPONSE,
+};
+#define HVSI_CONSOLE 0x1
+
+#define VS_DATA_PACKET_HEADER 0xff
+#define VS_CONTROL_PACKET_HEADER 0xfe
+#define VS_QUERY_PACKET_HEADER 0xfd
+#define VS_QUERY_RESPONSE_PACKET_HEADER 0xfc
+
+/* control verbs */
+#define VSV_SET_MODEM_CTL 1 /* to service processor only */
+#define VSV_MODEM_CTL_UPDATE 2 /* from service processor only */
+#define VSV_CLOSE_PROTOCOL 3
+
+/* query verbs */
+#define VSV_SEND_VERSION_NUMBER 1
+#define VSV_SEND_MODEM_CTL_STATUS 2
+
+/* yes, these masks are not consecutive. */
+#define HVSI_TSDTR 0x01
+#define HVSI_TSCD 0x20
+
+struct hvsi_header {
+ uint8_t type;
+ uint8_t len;
+ uint16_t seqno;
+} __attribute__((packed));
+
+struct hvsi_data {
+ uint8_t type;
+ uint8_t len;
+ uint16_t seqno;
+ uint8_t data[HVSI_MAX_OUTGOING_DATA];
+} __attribute__((packed));
+
+struct hvsi_control {
+ uint8_t type;
+ uint8_t len;
+ uint16_t seqno;
+ uint16_t verb;
+ /* optional depending on verb: */
+ uint32_t word;
+ uint32_t mask;
+} __attribute__((packed));
+
+struct hvsi_query {
+ uint8_t type;
+ uint8_t len;
+ uint16_t seqno;
+ uint16_t verb;
+} __attribute__((packed));
+
+struct hvsi_query_response {
+ uint8_t type;
+ uint8_t len;
+ uint16_t seqno;
+ uint16_t verb;
+ uint16_t query_seqno;
+ union {
+ uint8_t version;
+ uint32_t mctrl_word;
+ } u;
+} __attribute__((packed));
+
+static inline int is_open(struct hvsi_struct *hp)
+{
+ /* if we're waiting for an mctrl then we're already open */
+ return (hp->state == HVSI_OPEN)
+ || (hp->state == HVSI_WAIT_FOR_MCTRL_RESPONSE);
+}
+
+static inline void print_state(struct hvsi_struct *hp)
+{
+#ifdef DEBUG
+ static const char *state_names[] = {
+ "HVSI_CLOSED",
+ "HVSI_WAIT_FOR_VER_RESPONSE",
+ "HVSI_WAIT_FOR_VER_QUERY",
+ "HVSI_OPEN",
+ "HVSI_WAIT_FOR_MCTRL_RESPONSE",
+ };
+ const char *name = state_names[hp->state];
+
+ if (hp->state > (sizeof(state_names)/sizeof(char*)))
+ name = "UNKNOWN";
+
+ pr_debug("hvsi%i: state = %s\n", hp->index, name);
+#endif /* DEBUG */
+}
+
+static inline void __set_state(struct hvsi_struct *hp, int state)
+{
+ hp->state = state;
+ print_state(hp);
+ wake_up_all(&hp->stateq);
+}
+
+static inline void set_state(struct hvsi_struct *hp, int state)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&hp->lock, flags);
+ __set_state(hp, state);
+ spin_unlock_irqrestore(&hp->lock, flags);
+}
+
+static inline int len_packet(const uint8_t *packet)
+{
+ return (int)((struct hvsi_header *)packet)->len;
+}
+
+static inline int is_header(const uint8_t *packet)
+{
+ struct hvsi_header *header = (struct hvsi_header *)packet;
+ return header->type >= VS_QUERY_RESPONSE_PACKET_HEADER;
+}
+
+static inline int got_packet(const struct hvsi_struct *hp, uint8_t *packet)
+{
+ if (hp->inbuf_end < packet + sizeof(struct hvsi_header))
+ return 0; /* don't even have the packet header */
+
+ if (hp->inbuf_end < (packet + len_packet(packet)))
+ return 0; /* don't have the rest of the packet */
+
+ return 1;
+}
+
+/* shift remaining bytes in packetbuf down */
+static void compact_inbuf(struct hvsi_struct *hp, uint8_t *read_to)
+{
+ int remaining = (int)(hp->inbuf_end - read_to);
+
+ pr_debug("%s: %i chars remain\n", __FUNCTION__, remaining);
+
+ if (read_to != hp->inbuf)
+ memmove(hp->inbuf, read_to, remaining);
+
+ hp->inbuf_end = hp->inbuf + remaining;
+}
+
+#ifdef DEBUG
+#define dbg_dump_packet(packet) dump_packet(packet)
+#define dbg_dump_hex(data, len) dump_hex(data, len)
+#else
+#define dbg_dump_packet(packet) do { } while (0)
+#define dbg_dump_hex(data, len) do { } while (0)
+#endif
+
+static void dump_hex(const uint8_t *data, int len)
+{
+ int i;
+
+ printk(" ");
+ for (i=0; i < len; i++)
+ printk("%.2x", data[i]);
+
+ printk("\n ");
+ for (i=0; i < len; i++) {
+ if (isprint(data[i]))
+ printk("%c", data[i]);
+ else
+ printk(".");
+ }
+ printk("\n");
+}
+
+static void dump_packet(uint8_t *packet)
+{
+ struct hvsi_header *header = (struct hvsi_header *)packet;
+
+ printk("type 0x%x, len %i, seqno %i:\n", header->type, header->len,
+ header->seqno);
+
+ dump_hex(packet, header->len);
+}
+
+/* can't use hvc_get_chars because that strips CRs */
+static int hvsi_read(struct hvsi_struct *hp, char *buf, int count)
+{
+ unsigned long got;
+
+ if (plpar_hcall(H_GET_TERM_CHAR, hp->vtermno, 0, 0, 0, &got,
+ (unsigned long *)buf, (unsigned long *)buf+1) == H_Success)
+ return got;
+ return 0;
+}
+
+/*
+ * we can't call tty_hangup() directly here because we need to call that
+ * outside of our lock
+ */
+static struct tty_struct *hvsi_recv_control(struct hvsi_struct *hp,
+ uint8_t *packet)
+{
+ struct tty_struct *to_hangup = NULL;
+ struct hvsi_control *header = (struct hvsi_control *)packet;
+
+ switch (header->verb) {
+ case VSV_MODEM_CTL_UPDATE:
+ if ((header->word & HVSI_TSCD) == 0) {
+ /* CD went away; no more connection */
+ pr_debug("hvsi%i: CD dropped\n", hp->index);
+ hp->mctrl &= TIOCM_CD;
+ if (!(hp->tty->flags & CLOCAL))
+ to_hangup = hp->tty;
+ }
+ break;
+ case VSV_CLOSE_PROTOCOL:
+ printk(KERN_DEBUG
+ "hvsi%i: service processor closed connection!\n", hp->index);
+ __set_state(hp, HVSI_CLOSED);
+ to_hangup = hp->tty;
+ hp->tty = NULL;
+ break;
+ default:
+ printk(KERN_WARNING "hvsi%i: unknown HVSI control packet: ",
+ hp->index);
+ dump_packet(packet);
+ break;
+ }
+
+ return to_hangup;
+}
+
+static void hvsi_recv_response(struct hvsi_struct *hp, uint8_t *packet)
+{
+ struct hvsi_query_response *resp = (struct hvsi_query_response *)packet;
+
+ switch (hp->state) {
+ case HVSI_WAIT_FOR_VER_RESPONSE:
+ __set_state(hp, HVSI_WAIT_FOR_VER_QUERY);
+ break;
+ case HVSI_WAIT_FOR_MCTRL_RESPONSE:
+ hp->mctrl = 0;
+ if (resp->u.mctrl_word & HVSI_TSDTR)
+ hp->mctrl |= TIOCM_DTR;
+ if (resp->u.mctrl_word & HVSI_TSCD)
+ hp->mctrl |= TIOCM_CD;
+ __set_state(hp, HVSI_OPEN);
+ break;
+ default:
+ printk(KERN_ERR "hvsi%i: unexpected query response: ", hp->index);
+ dump_packet(packet);
+ break;
+ }
+}
+
+/* respond to service processor's version query */
+static int hvsi_version_respond(struct hvsi_struct *hp, uint16_t query_seqno)
+{
+ struct hvsi_query_response packet __ALIGNED__;
+ int wrote;
+
+ packet.type = VS_QUERY_RESPONSE_PACKET_HEADER;
+ packet.len = sizeof(struct hvsi_query_response);
+ packet.seqno = atomic_inc_return(&hp->seqno);
+ packet.verb = VSV_SEND_VERSION_NUMBER;
+ packet.u.version = HVSI_VERSION;
+ packet.query_seqno = query_seqno+1;
+
+ pr_debug("%s: sending %i bytes\n", __FUNCTION__, packet.len);
+ dbg_dump_hex((uint8_t*)&packet, packet.len);
+
+ wrote = hvc_put_chars(hp->vtermno, (char *)&packet, packet.len);
+ if (wrote != packet.len) {
+ printk(KERN_ERR "hvsi%i: couldn't send query response!\n",
+ hp->index);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void hvsi_recv_query(struct hvsi_struct *hp, uint8_t *packet)
+{
+ struct hvsi_query *query = (struct hvsi_query *)packet;
+
+ switch (hp->state) {
+ case HVSI_WAIT_FOR_VER_QUERY:
+ __set_state(hp, HVSI_OPEN);
+ hvsi_version_respond(hp, query->seqno);
+ break;
+ default:
+ printk(KERN_ERR "hvsi%i: unexpected query: ", hp->index);
+ dump_packet(packet);
+ break;
+ }
+}
+
+static void hvsi_insert_chars(struct hvsi_struct *hp, const char *buf, int len)
+{
+ int i;
+
+ for (i=0; i < len; i++) {
+ char c = buf[i];
+#ifdef CONFIG_MAGIC_SYSRQ
+ if (c == '\0') {
+ hp->sysrq = 1;
+ continue;
+ } else if (hp->sysrq) {
+ handle_sysrq(c, NULL, hp->tty);
+ hp->sysrq = 0;
+ continue;
+ }
+#endif /* CONFIG_MAGIC_SYSRQ */
+ tty_insert_flip_char(hp->tty, c, 0);
+ }
+}
+
+/*
+ * We could get 252 bytes of data at once here. But the tty layer only
+ * throttles us at TTY_THRESHOLD_THROTTLE (128) bytes, so we could overflow
+ * it. Accordingly we won't send more than 128 bytes at a time to the flip
+ * buffer, which will give the tty buffer a chance to throttle us. Should the
+ * value of TTY_THRESHOLD_THROTTLE change in n_tty.c, this code should be
+ * revisited.
+ */
+#define TTY_THRESHOLD_THROTTLE 128
+static struct tty_struct *hvsi_recv_data(struct hvsi_struct *hp,
+ const uint8_t *packet)
+{
+ const struct hvsi_header *header = (const struct hvsi_header *)packet;
+ const uint8_t *data = packet + sizeof(struct hvsi_header);
+ int datalen = header->len - sizeof(struct hvsi_header);
+ int overflow = datalen - TTY_THRESHOLD_THROTTLE;
+
+ pr_debug("queueing %i chars '%.*s'\n", datalen, datalen, data);
+
+ if (datalen == 0)
+ return NULL;
+
+ if (overflow > 0) {
+ pr_debug("%s: got >TTY_THRESHOLD_THROTTLE bytes\n", __FUNCTION__);
+ datalen = TTY_THRESHOLD_THROTTLE;
+ }
+
+ hvsi_insert_chars(hp, data, datalen);
+
+ if (overflow > 0) {
+ /*
+ * we still have more data to deliver, so we need to save off the
+ * overflow and send it later
+ */
+ pr_debug("%s: deferring overflow\n", __FUNCTION__);
+ memcpy(hp->throttle_buf, data + TTY_THRESHOLD_THROTTLE, overflow);
+ hp->n_throttle = overflow;
+ }
+
+ return hp->tty;
+}
+
+/*
+ * Returns true/false indicating data successfully read from hypervisor.
+ * Used both to get packets for tty connections and to advance the state
+ * machine during console handshaking (in which case tty = NULL and we ignore
+ * incoming data).
+ */
+static int hvsi_load_chunk(struct hvsi_struct *hp, struct tty_struct **flip,
+ struct tty_struct **hangup)
+{
+ uint8_t *packet = hp->inbuf;
+ int chunklen;
+
+ *flip = NULL;
+ *hangup = NULL;
+
+ chunklen = hvsi_read(hp, hp->inbuf_end, HVSI_MAX_READ);
+ if (chunklen == 0)
+ return 0;
+
+ pr_debug("%s: got %i bytes\n", __FUNCTION__, chunklen);
+ dbg_dump_hex(hp->inbuf_end, chunklen);
+
+ hp->inbuf_end += chunklen;
+
+ /* handle all completed packets */
+ while ((packet < hp->inbuf_end) && got_packet(hp, packet)) {
+ struct hvsi_header *header = (struct hvsi_header *)packet;
+
+ if (!is_header(packet)) {
+ printk(KERN_ERR "hvsi%i: got malformed packet\n", hp->index);
+ /* skip bytes until we find a header or run out of data */
+ while ((packet < hp->inbuf_end) && (!is_header(packet)))
+ packet++;
+ continue;
+ }
+
+ pr_debug("%s: handling %i-byte packet\n", __FUNCTION__,
+ len_packet(packet));
+ dbg_dump_packet(packet);
+
+ switch (header->type) {
+ case VS_DATA_PACKET_HEADER:
+ if (!is_open(hp))
+ break;
+ if (hp->tty == NULL)
+ break; /* no tty buffer to put data in */
+ *flip = hvsi_recv_data(hp, packet);
+ break;
+ case VS_CONTROL_PACKET_HEADER:
+ *hangup = hvsi_recv_control(hp, packet);
+ break;
+ case VS_QUERY_RESPONSE_PACKET_HEADER:
+ hvsi_recv_response(hp, packet);
+ break;
+ case VS_QUERY_PACKET_HEADER:
+ hvsi_recv_query(hp, packet);
+ break;
+ default:
+ printk(KERN_ERR "hvsi%i: unknown HVSI packet type 0x%x\n",
+ hp->index, header->type);
+ dump_packet(packet);
+ break;
+ }
+
+ packet += len_packet(packet);
+
+ if (*hangup) {
+ pr_debug("%s: hangup\n", __FUNCTION__);
+ /*
+ * we need to send the hangup now before receiving any more data.
+ * If we get "data, hangup, data", we can't deliver the second
+ * data before the hangup.
+ */
+ break;
+ }
+ }
+
+ compact_inbuf(hp, packet);
+
+ return 1;
+}
+
+static void hvsi_send_overflow(struct hvsi_struct *hp)
+{
+ pr_debug("%s: delivering %i bytes overflow\n", __FUNCTION__,
+ hp->n_throttle);
+
+ hvsi_insert_chars(hp, hp->throttle_buf, hp->n_throttle);
+ hp->n_throttle = 0;
+}
+
+/*
+ * must get all pending data because we only get an irq on empty->non-empty
+ * transition
+ */
+static irqreturn_t hvsi_interrupt(int irq, void *arg, struct pt_regs *regs)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)arg;
+ struct tty_struct *flip;
+ struct tty_struct *hangup;
+ unsigned long flags;
+ irqreturn_t handled = IRQ_NONE;
+ int again = 1;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ while (again) {
+ spin_lock_irqsave(&hp->lock, flags);
+ again = hvsi_load_chunk(hp, &flip, &hangup);
+ handled = IRQ_HANDLED;
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ /*
+ * we have to call tty_flip_buffer_push() and tty_hangup() outside our
+ * spinlock. But we also have to keep going until we've read all the
+ * available data.
+ */
+
+ if (flip) {
+ /* there was data put in the tty flip buffer */
+ tty_flip_buffer_push(flip);
+ flip = NULL;
+ }
+
+ if (hangup) {
+ tty_hangup(hangup);
+ }
+ }
+
+ spin_lock_irqsave(&hp->lock, flags);
+ if (hp->tty && hp->n_throttle
+ && (!test_bit(TTY_THROTTLED, &hp->tty->flags))) {
+ /* we weren't hung up and we weren't throttled, so we can deliver the
+ * rest now */
+ flip = hp->tty;
+ hvsi_send_overflow(hp);
+ }
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ if (flip) {
+ tty_flip_buffer_push(flip);
+ }
+
+ return handled;
+}
+
+/* for boot console, before the irq handler is running */
+static int __init poll_for_state(struct hvsi_struct *hp, int state)
+{
+ unsigned long end_jiffies = jiffies + HVSI_TIMEOUT;
+
+ for (;;) {
+ hvsi_interrupt(hp->virq, (void *)hp, NULL); /* get pending data */
+
+ if (hp->state == state)
+ return 0;
+
+ mdelay(5);
+ if (time_after(jiffies, end_jiffies))
+ return -EIO;
+ }
+}
+
+/* wait for irq handler to change our state */
+static int wait_for_state(struct hvsi_struct *hp, int state)
+{
+ unsigned long end_jiffies = jiffies + HVSI_TIMEOUT;
+ unsigned long timeout;
+ int ret = 0;
+
+ DECLARE_WAITQUEUE(myself, current);
+ set_current_state(TASK_INTERRUPTIBLE);
+ add_wait_queue(&hp->stateq, &myself);
+
+ for (;;) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (hp->state == state)
+ break;
+ timeout = end_jiffies - jiffies;
+ if (time_after(jiffies, end_jiffies)) {
+ ret = -EIO;
+ break;
+ }
+ schedule_timeout(timeout);
+ }
+ remove_wait_queue(&hp->stateq, &myself);
+ set_current_state(TASK_RUNNING);
+
+ return ret;
+}
+
+static int hvsi_query(struct hvsi_struct *hp, uint16_t verb)
+{
+ struct hvsi_query packet __ALIGNED__;
+ int wrote;
+
+ packet.type = VS_QUERY_PACKET_HEADER;
+ packet.len = sizeof(struct hvsi_query);
+ packet.seqno = atomic_inc_return(&hp->seqno);
+ packet.verb = verb;
+
+ pr_debug("%s: sending %i bytes\n", __FUNCTION__, packet.len);
+ dbg_dump_hex((uint8_t*)&packet, packet.len);
+
+ wrote = hvc_put_chars(hp->vtermno, (char *)&packet, packet.len);
+ if (wrote != packet.len) {
+ printk(KERN_ERR "hvsi%i: couldn't send query (%i)!\n", hp->index,
+ wrote);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int hvsi_get_mctrl(struct hvsi_struct *hp)
+{
+ int ret;
+
+ set_state(hp, HVSI_WAIT_FOR_MCTRL_RESPONSE);
+ hvsi_query(hp, VSV_SEND_MODEM_CTL_STATUS);
+
+ ret = hvsi_wait(hp, HVSI_OPEN);
+ if (ret < 0) {
+ printk(KERN_ERR "hvsi%i: didn't get modem flags\n", hp->index);
+ set_state(hp, HVSI_OPEN);
+ return ret;
+ }
+
+ pr_debug("%s: mctrl 0x%x\n", __FUNCTION__, hp->mctrl);
+
+ return 0;
+}
+
+/* note that we can only set DTR */
+static int hvsi_set_mctrl(struct hvsi_struct *hp, uint16_t mctrl)
+{
+ struct hvsi_control packet __ALIGNED__;
+ int wrote;
+
+ packet.type = VS_CONTROL_PACKET_HEADER,
+ packet.seqno = atomic_inc_return(&hp->seqno);
+ packet.len = sizeof(struct hvsi_control);
+ packet.verb = VSV_SET_MODEM_CTL;
+ packet.mask = HVSI_TSDTR;
+
+ if (mctrl & TIOCM_DTR)
+ packet.word = HVSI_TSDTR;
+
+ pr_debug("%s: sending %i bytes\n", __FUNCTION__, packet.len);
+ dbg_dump_hex((uint8_t*)&packet, packet.len);
+
+ wrote = hvc_put_chars(hp->vtermno, (char *)&packet, packet.len);
+ if (wrote != packet.len) {
+ printk(KERN_ERR "hvsi%i: couldn't set DTR!\n", hp->index);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void hvsi_drain_input(struct hvsi_struct *hp)
+{
+ uint8_t buf[HVSI_MAX_READ] __ALIGNED__;
+ unsigned long end_jiffies = jiffies + HVSI_TIMEOUT;
+
+ while (time_before(end_jiffies, jiffies))
+ if (0 == hvsi_read(hp, buf, HVSI_MAX_READ))
+ break;
+}
+
+static int hvsi_handshake(struct hvsi_struct *hp)
+{
+ int ret;
+
+ /*
+ * We could have a CLOSE or other data waiting for us before we even try
+ * to open; try to throw it all away so we don't get confused. (CLOSE
+ * is the first message sent up the pipe when the FSP comes online. We
+ * need to distinguish between "it came up a while ago and we're the first
+ * user" and "it was just reset before it saw our handshake packet".)
+ */
+ hvsi_drain_input(hp);
+
+ set_state(hp, HVSI_WAIT_FOR_VER_RESPONSE);
+ ret = hvsi_query(hp, VSV_SEND_VERSION_NUMBER);
+ if (ret < 0) {
+ printk(KERN_ERR "hvsi%i: couldn't send version query\n", hp->index);
+ return ret;
+ }
+
+ ret = hvsi_wait(hp, HVSI_OPEN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int hvsi_put_chars(struct hvsi_struct *hp, const char *buf, int count)
+{
+ struct hvsi_data packet __ALIGNED__;
+ int ret;
+
+ BUG_ON(count > HVSI_MAX_OUTGOING_DATA);
+
+ packet.type = VS_DATA_PACKET_HEADER;
+ packet.seqno = atomic_inc_return(&hp->seqno);
+ packet.len = count + sizeof(struct hvsi_header);
+ memcpy(&packet.data, buf, count);
+
+ ret = hvc_put_chars(hp->vtermno, (char *)&packet, packet.len);
+ if (ret == packet.len) {
+ /* return the number of chars written, not the packet length */
+ return count;
+ }
+ return ret; /* return any errors */
+}
+
+static void hvsi_close_protocol(struct hvsi_struct *hp)
+{
+ struct hvsi_control packet __ALIGNED__;
+
+ packet.type = VS_CONTROL_PACKET_HEADER;
+ packet.seqno = atomic_inc_return(&hp->seqno);
+ packet.len = 6;
+ packet.verb = VSV_CLOSE_PROTOCOL;
+
+ pr_debug("%s: sending %i bytes\n", __FUNCTION__, packet.len);
+ dbg_dump_hex((uint8_t*)&packet, packet.len);
+
+ hvc_put_chars(hp->vtermno, (char *)&packet, packet.len);
+}
+
+static int hvsi_open(struct tty_struct *tty, struct file *filp)
+{
+ struct hvsi_struct *hp;
+ unsigned long flags;
+ int line = tty->index;
+ int ret;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ if (line < 0 || line >= hvsi_count)
+ return -ENODEV;
+ hp = &hvsi_ports[line];
+
+ tty->driver_data = hp;
+ tty->low_latency = 1; /* avoid throttle/tty_flip_buffer_push race */
+
+ spin_lock_irqsave(&hp->lock, flags);
+ hp->tty = tty;
+ hp->count++;
+ atomic_set(&hp->seqno, 0);
+ h_vio_signal(hp->vtermno, VIO_IRQ_ENABLE);
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ if (hp->flags & HVSI_CONSOLE)
+ return 0; /* this has already been handshaked as the console */
+
+ ret = hvsi_handshake(hp);
+ if (ret < 0) {
+ printk(KERN_ERR "%s: HVSI handshaking failed\n", tty->name);
+ return ret;
+ }
+
+ ret = hvsi_get_mctrl(hp);
+ if (ret < 0) {
+ printk(KERN_ERR "%s: couldn't get initial modem flags\n", tty->name);
+ return ret;
+ }
+
+ ret = hvsi_set_mctrl(hp, hp->mctrl | TIOCM_DTR);
+ if (ret < 0) {
+ printk(KERN_ERR "%s: couldn't set DTR\n", tty->name);
+ return ret;
+ }
+
+ return 0;
+}
+
+/* wait for hvsi_write_worker to empty hp->outbuf */
+static void hvsi_flush_output(struct hvsi_struct *hp)
+{
+ unsigned long end_jiffies = jiffies + HVSI_TIMEOUT;
+ unsigned long timeout;
+
+ DECLARE_WAITQUEUE(myself, current);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ add_wait_queue(&hp->emptyq, &myself);
+
+ for (;;) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ if (hp->n_outbuf <= 0)
+ break;
+ timeout = end_jiffies - jiffies;
+ if (time_after(jiffies, end_jiffies))
+ break;
+ schedule_timeout(timeout);
+ }
+ remove_wait_queue(&hp->emptyq, &myself);
+ set_current_state(TASK_RUNNING);
+
+ /* 'writer' could still be pending if it didn't see n_outbuf = 0 yet */
+ cancel_delayed_work(&hp->writer);
+ flush_scheduled_work();
+
+ /*
+ * it's also possible that our timeout expired and hvsi_write_worker
+ * didn't manage to push outbuf. poof.
+ */
+ hp->n_outbuf = 0;
+}
+
+static void hvsi_close(struct tty_struct *tty, struct file *filp)
+{
+ struct hvsi_struct *hp = tty->driver_data;
+ unsigned long flags;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ if (tty_hung_up_p(filp))
+ return;
+
+ spin_lock_irqsave(&hp->lock, flags);
+
+ if (--hp->count == 0) {
+ hp->tty = NULL;
+ hp->inbuf_end = hp->inbuf; /* discard remaining partial packets */
+
+ /* only close down connection if it is not the console */
+ if (!(hp->flags & HVSI_CONSOLE)) {
+ h_vio_signal(hp->vtermno, VIO_IRQ_DISABLE); /* no more irqs */
+ __set_state(hp, HVSI_CLOSED);
+ /*
+ * any data delivered to the tty layer after this will be
+ * discarded (except for XON/XOFF)
+ */
+ tty->closing = 1;
+
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ /* let any existing irq handlers finish. no more will start. */
+ synchronize_irq(hp->virq);
+
+ /* hvsi_write_worker will re-schedule until outbuf is empty. */
+ hvsi_flush_output(hp);
+
+ /* tell FSP to stop sending data */
+ hvsi_close_protocol(hp);
+
+ /*
+ * drain anything FSP is still in the middle of sending, and let
+ * hvsi_handshake drain the rest on the next open.
+ */
+ hvsi_drain_input(hp);
+
+ spin_lock_irqsave(&hp->lock, flags);
+ }
+ } else if (hp->count < 0)
+ printk(KERN_ERR "hvsi_close %lu: oops, count is %d\n",
+ hp - hvsi_ports, hp->count);
+
+ spin_unlock_irqrestore(&hp->lock, flags);
+}
+
+static void hvsi_hangup(struct tty_struct *tty)
+{
+ struct hvsi_struct *hp = tty->driver_data;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ hp->count = 0;
+ hp->tty = NULL;
+}
+
+/* called with hp->lock held */
+static void hvsi_push(struct hvsi_struct *hp)
+{
+ int n;
+
+ if (hp->n_outbuf <= 0)
+ return;
+
+ n = hvsi_put_chars(hp, hp->outbuf, hp->n_outbuf);
+ if (n != 0) {
+ /*
+ * either all data was sent or there was an error, and we throw away
+ * data on error.
+ */
+ hp->n_outbuf = 0;
+ }
+}
+
+/* hvsi_write_worker will keep rescheduling itself until outbuf is empty */
+static void hvsi_write_worker(void *arg)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)arg;
+ unsigned long flags;
+#ifdef DEBUG
+ static long start_j = 0;
+
+ if (start_j == 0)
+ start_j = jiffies;
+#endif /* DEBUG */
+
+ spin_lock_irqsave(&hp->lock, flags);
+
+ hvsi_push(hp);
+ if (hp->n_outbuf > 0)
+ schedule_delayed_work(&hp->writer, 10);
+ else {
+#ifdef DEBUG
+ pr_debug("%s: outbuf emptied after %li jiffies\n", __FUNCTION__,
+ jiffies - start_j);
+ start_j = 0;
+#endif /* DEBUG */
+ wake_up_all(&hp->emptyq);
+ if (test_bit(TTY_DO_WRITE_WAKEUP, &hp->tty->flags)
+ && hp->tty->ldisc.write_wakeup)
+ hp->tty->ldisc.write_wakeup(hp->tty);
+ wake_up_interruptible(&hp->tty->write_wait);
+ }
+
+ spin_unlock_irqrestore(&hp->lock, flags);
+}
+
+static int hvsi_write_room(struct tty_struct *tty)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)tty->driver_data;
+
+ return N_OUTBUF - hp->n_outbuf;
+}
+
+static int hvsi_chars_in_buffer(struct tty_struct *tty)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)tty->driver_data;
+
+ return hp->n_outbuf;
+}
+
+static int hvsi_write(struct tty_struct *tty, int from_user,
+ const unsigned char *buf, int count)
+{
+ struct hvsi_struct *hp = tty->driver_data;
+ const char *source = buf;
+ char *kbuf = NULL;
+ unsigned long flags;
+ int total = 0;
+ int origcount = count;
+
+ if (from_user) {
+ kbuf = kmalloc(count, GFP_KERNEL);
+ if (kbuf == NULL)
+ return -ENOMEM;
+ if (copy_from_user(kbuf, buf, count)) {
+ kfree(kbuf);
+ return -EFAULT;
+ }
+ source = kbuf;
+ }
+
+ spin_lock_irqsave(&hp->lock, flags);
+
+ if (!is_open(hp)) {
+ /* we're either closing or not yet open; don't accept data */
+ pr_debug("%s: not open\n", __FUNCTION__);
+ goto out;
+ }
+
+ /*
+ * when the hypervisor buffer (16K) fills, data will stay in hp->outbuf
+ * and hvsi_write_worker will be scheduled. subsequent hvsi_write() calls
+ * will see there is no room in outbuf and return.
+ */
+ while ((count > 0) && (hvsi_write_room(hp->tty) > 0)) {
+ int chunksize = min(count, hvsi_write_room(hp->tty));
+
+ BUG_ON(hp->n_outbuf < 0);
+ memcpy(hp->outbuf + hp->n_outbuf, source, chunksize);
+ hp->n_outbuf += chunksize;
+
+ total += chunksize;
+ source += chunksize;
+ count -= chunksize;
+ hvsi_push(hp);
+ }
+
+ if (hp->n_outbuf > 0) {
+ /*
+ * we weren't able to write it all to the hypervisor.
+ * schedule another push attempt.
+ */
+ schedule_delayed_work(&hp->writer, 10);
+ }
+
+out:
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ if (from_user)
+ kfree(kbuf);
+
+ if (total != origcount)
+ pr_debug("%s: wanted %i, only wrote %i\n", __FUNCTION__, origcount,
+ total);
+
+ return total;
+}
+
+/*
+ * I have never seen throttle or unthrottle called, so this little throttle
+ * buffering scheme may or may not work.
+ */
+static void hvsi_throttle(struct tty_struct *tty)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)tty->driver_data;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ h_vio_signal(hp->vtermno, VIO_IRQ_DISABLE);
+}
+
+static void hvsi_unthrottle(struct tty_struct *tty)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)tty->driver_data;
+ unsigned long flags;
+ int shouldflip = 0;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ spin_lock_irqsave(&hp->lock, flags);
+ if (hp->n_throttle) {
+ hvsi_send_overflow(hp);
+ shouldflip = 1;
+ }
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ if (shouldflip)
+ tty_flip_buffer_push(hp->tty);
+
+ h_vio_signal(hp->vtermno, VIO_IRQ_ENABLE);
+}
+
+static int hvsi_tiocmget(struct tty_struct *tty, struct file *file)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)tty->driver_data;
+
+ hvsi_get_mctrl(hp);
+ return hp->mctrl;
+}
+
+static int hvsi_tiocmset(struct tty_struct *tty, struct file *file,
+ unsigned int set, unsigned int clear)
+{
+ struct hvsi_struct *hp = (struct hvsi_struct *)tty->driver_data;
+ unsigned long flags;
+ uint16_t new_mctrl;
+
+ /* we can only alter DTR */
+ clear &= TIOCM_DTR;
+ set &= TIOCM_DTR;
+
+ spin_lock_irqsave(&hp->lock, flags);
+
+ new_mctrl = (hp->mctrl & ~clear) | set;
+
+ if (hp->mctrl != new_mctrl) {
+ hvsi_set_mctrl(hp, new_mctrl);
+ hp->mctrl = new_mctrl;
+ }
+ spin_unlock_irqrestore(&hp->lock, flags);
+
+ return 0;
+}
+
+
+static struct tty_operations hvsi_ops = {
+ .open = hvsi_open,
+ .close = hvsi_close,
+ .write = hvsi_write,
+ .hangup = hvsi_hangup,
+ .write_room = hvsi_write_room,
+ .chars_in_buffer = hvsi_chars_in_buffer,
+ .throttle = hvsi_throttle,
+ .unthrottle = hvsi_unthrottle,
+ .tiocmget = hvsi_tiocmget,
+ .tiocmset = hvsi_tiocmset,
+};
+
+static int __init hvsi_init(void)
+{
+ int i;
+
+ hvsi_driver = alloc_tty_driver(hvsi_count);
+ if (!hvsi_driver)
+ return -ENOMEM;
+
+ hvsi_driver->owner = THIS_MODULE;
+ hvsi_driver->devfs_name = "hvsi/";
+ hvsi_driver->driver_name = "hvsi";
+ hvsi_driver->name = "hvsi";
+ hvsi_driver->major = HVSI_MAJOR;
+ hvsi_driver->minor_start = HVSI_MINOR;
+ hvsi_driver->type = TTY_DRIVER_TYPE_SYSTEM;
+ hvsi_driver->init_termios = tty_std_termios;
+ hvsi_driver->init_termios.c_cflag = B9600 | CS8 | CREAD | HUPCL;
+ hvsi_driver->flags = TTY_DRIVER_REAL_RAW;
+ tty_set_operations(hvsi_driver, &hvsi_ops);
+
+ for (i=0; i < hvsi_count; i++) {
+ struct hvsi_struct *hp = &hvsi_ports[i];
+ int ret = 1;
+
+ ret = request_irq(hp->virq, hvsi_interrupt, SA_INTERRUPT, "hvsi", hp);
+ if (ret)
+ printk(KERN_ERR "HVSI: couldn't reserve irq 0x%x (error %i)\n",
+ hp->virq, ret);
+ }
+ hvsi_wait = wait_for_state; /* irqs active now */
+
+ if (tty_register_driver(hvsi_driver))
+ panic("Couldn't register hvsi console driver\n");
+
+ printk(KERN_INFO "HVSI: registered %i devices\n", hvsi_count);
+
+ return 0;
+}
+device_initcall(hvsi_init);
+
+/***** console (not tty) code: *****/
+
+static void hvsi_console_print(struct console *console, const char *buf,
+ unsigned int count)
+{
+ struct hvsi_struct *hp = &hvsi_ports[console->index];
+ char c[HVSI_MAX_OUTGOING_DATA] __ALIGNED__;
+ unsigned int i = 0, n = 0;
+ int ret, donecr = 0;
+
+ mb();
+ if (!is_open(hp))
+ return;
+
+ /*
+ * ugh, we have to translate LF -> CRLF ourselves, in place.
+ * copied from hvc_console.c:
+ */
+ while (count > 0 || i > 0) {
+ if (count > 0 && i < sizeof(c)) {
+ if (buf[n] == '\n' && !donecr) {
+ c[i++] = '\r';
+ donecr = 1;
+ } else {
+ c[i++] = buf[n++];
+ donecr = 0;
+ --count;
+ }
+ } else {
+ ret = hvsi_put_chars(hp, c, i);
+ if (ret < 0)
+ i = 0;
+ i -= ret;
+ }
+ }
+}
+
+static struct tty_driver *hvsi_console_device(struct console *console,
+ int *index)
+{
+ *index = console->index;
+ return hvsi_driver;
+}
+
+static int __init hvsi_console_setup(struct console *console, char *options)
+{
+ struct hvsi_struct *hp = &hvsi_ports[console->index];
+ int ret;
+
+ if (console->index < 0 || console->index >= hvsi_count)
+ return -1;
+
+ /* give the FSP a chance to change the baud rate when we re-open */
+ hvsi_close_protocol(hp);
+
+ ret = hvsi_handshake(hp);
+ if (ret < 0)
+ return ret;
+
+ ret = hvsi_get_mctrl(hp);
+ if (ret < 0)
+ return ret;
+
+ ret = hvsi_set_mctrl(hp, hp->mctrl | TIOCM_DTR);
+ if (ret < 0)
+ return ret;
+
+ hp->flags |= HVSI_CONSOLE;
+
+ return 0;
+}
+
+static struct console hvsi_con_driver = {
+ .name = "hvsi",
+ .write = hvsi_console_print,
+ .device = hvsi_console_device,
+ .setup = hvsi_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+};
+
+static int __init hvsi_console_init(void)
+{
+ struct device_node *vty;
+
+ hvsi_wait = poll_for_state; /* no irqs yet; must poll */
+
+ /* search device tree for vty nodes */
+ for (vty = of_find_compatible_node(NULL, "serial", "hvterm-protocol");
+ vty != NULL;
+ vty = of_find_compatible_node(vty, "serial", "hvterm-protocol")) {
+ struct hvsi_struct *hp;
+ uint32_t *vtermno;
+ uint32_t *irq;
+
+ vtermno = (uint32_t *)get_property(vty, "reg", NULL);
+ irq = (uint32_t *)get_property(vty, "interrupts", NULL);
+ if (!vtermno || !irq)
+ continue;
+
+ if (hvsi_count >= MAX_NR_HVSI_CONSOLES) {
+ of_node_put(vty);
+ break;
+ }
+
+ hp = &hvsi_ports[hvsi_count];
+ INIT_WORK(&hp->writer, hvsi_write_worker, hp);
+ init_waitqueue_head(&hp->emptyq);
+ init_waitqueue_head(&hp->stateq);
+ hp->lock = SPIN_LOCK_UNLOCKED;
+ hp->index = hvsi_count;
+ hp->inbuf_end = hp->inbuf;
+ hp->state = HVSI_CLOSED;
+ hp->vtermno = *vtermno;
+ hp->virq = virt_irq_create_mapping(irq[0]);
+ if (hp->virq == NO_IRQ) {
+ printk(KERN_ERR "%s: couldn't create irq mapping for 0x%x\n",
+ __FUNCTION__, hp->virq);
+ continue;
+ } else
+ hp->virq = irq_offset_up(hp->virq);
+
+ hvsi_count++;
+ }
+
+ if (hvsi_count)
+ register_console(&hvsi_con_driver);
+ return 0;
+}
+console_initcall(hvsi_console_init);
--- /dev/null
+/*
+ * ipmi_poweroff.c
+ *
+ * MontaVista IPMI Poweroff extension to sys_reboot
+ *
+ * Author: MontaVista Software, Inc.
+ * Steven Dake <sdake@mvista.com>
+ * Corey Minyard <cminyard@mvista.com>
+ * source@mvista.com
+ *
+ * Copyright 2002,2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <asm/semaphore.h>
+#include <linux/kdev_t.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/ipmi.h>
+#include <linux/ipmi_smi.h>
+
+#define PFX "IPMI poweroff: "
+#define IPMI_POWEROFF_VERSION "v33"
+
+/* Where to we insert our poweroff function? */
+extern void (*pm_power_off)(void);
+
+/* Stuff from the get device id command. */
+unsigned int mfg_id;
+unsigned int prod_id;
+unsigned char capabilities;
+
+/* We use our own messages for this operation, we don't let the system
+ allocate them, since we may be in a panic situation. The whole
+ thing is single-threaded, anyway, so multiple messages are not
+ required. */
+static void dummy_smi_free(struct ipmi_smi_msg *msg)
+{
+}
+static void dummy_recv_free(struct ipmi_recv_msg *msg)
+{
+}
+static struct ipmi_smi_msg halt_smi_msg =
+{
+ .done = dummy_smi_free
+};
+static struct ipmi_recv_msg halt_recv_msg =
+{
+ .done = dummy_recv_free
+};
+
+
+/*
+ * Code to send a message and wait for the reponse.
+ */
+
+static void receive_handler(struct ipmi_recv_msg *recv_msg, void *handler_data)
+{
+ struct semaphore *sem = recv_msg->user_msg_data;
+
+ if (sem)
+ up(sem);
+}
+
+static struct ipmi_user_hndl ipmi_poweroff_handler =
+{
+ .ipmi_recv_hndl = receive_handler
+};
+
+
+static int ipmi_request_wait_for_response(ipmi_user_t user,
+ struct ipmi_addr *addr,
+ struct kernel_ipmi_msg *send_msg)
+{
+ int rv;
+ struct semaphore sem;
+
+ sema_init (&sem, 0);
+
+ rv = ipmi_request_supply_msgs(user, addr, 0, send_msg, &sem,
+ &halt_smi_msg, &halt_recv_msg, 0);
+ if (rv)
+ return rv;
+
+ down (&sem);
+
+ return halt_recv_msg.msg.data[0];
+}
+
+/* We are in run-to-completion mode, no semaphore is desired. */
+static int ipmi_request_in_rc_mode(ipmi_user_t user,
+ struct ipmi_addr *addr,
+ struct kernel_ipmi_msg *send_msg)
+{
+ int rv;
+
+ rv = ipmi_request_supply_msgs(user, addr, 0, send_msg, NULL,
+ &halt_smi_msg, &halt_recv_msg, 0);
+ if (rv)
+ return rv;
+
+ return halt_recv_msg.msg.data[0];
+}
+
+/*
+ * ATCA Support
+ */
+
+#define IPMI_NETFN_ATCA 0x2c
+#define IPMI_ATCA_SET_POWER_CMD 0x11
+#define IPMI_ATCA_GET_ADDR_INFO_CMD 0x01
+#define IPMI_PICMG_ID 0
+
+static int ipmi_atca_detect (ipmi_user_t user)
+{
+ struct ipmi_system_interface_addr smi_addr;
+ struct kernel_ipmi_msg send_msg;
+ int rv;
+ unsigned char data[1];
+
+ /*
+ * Configure IPMI address for local access
+ */
+ smi_addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
+ smi_addr.channel = IPMI_BMC_CHANNEL;
+ smi_addr.lun = 0;
+
+ /*
+ * Use get address info to check and see if we are ATCA
+ */
+ send_msg.netfn = IPMI_NETFN_ATCA;
+ send_msg.cmd = IPMI_ATCA_GET_ADDR_INFO_CMD;
+ data[0] = IPMI_PICMG_ID;
+ send_msg.data = data;
+ send_msg.data_len = sizeof(data);
+ rv = ipmi_request_wait_for_response(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ return !rv;
+}
+
+static void ipmi_poweroff_atca (ipmi_user_t user)
+{
+ struct ipmi_system_interface_addr smi_addr;
+ struct kernel_ipmi_msg send_msg;
+ int rv;
+ unsigned char data[4];
+
+ /*
+ * Configure IPMI address for local access
+ */
+ smi_addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
+ smi_addr.channel = IPMI_BMC_CHANNEL;
+ smi_addr.lun = 0;
+
+ printk(KERN_INFO PFX "Powering down via ATCA power command\n");
+
+ /*
+ * Power down
+ */
+ send_msg.netfn = IPMI_NETFN_ATCA;
+ send_msg.cmd = IPMI_ATCA_SET_POWER_CMD;
+ data[0] = IPMI_PICMG_ID;
+ data[1] = 0; /* FRU id */
+ data[2] = 0; /* Power Level */
+ data[3] = 0; /* Don't change saved presets */
+ send_msg.data = data;
+ send_msg.data_len = sizeof (data);
+ rv = ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv) {
+ printk(KERN_ERR PFX "Unable to send ATCA powerdown message,"
+ " IPMI error 0x%x\n", rv);
+ goto out;
+ }
+
+ out:
+ return;
+}
+
+/*
+ * CPI1 Support
+ */
+
+#define IPMI_NETFN_OEM_1 0xf8
+#define OEM_GRP_CMD_SET_RESET_STATE 0x84
+#define OEM_GRP_CMD_SET_POWER_STATE 0x82
+#define IPMI_NETFN_OEM_8 0xf8
+#define OEM_GRP_CMD_REQUEST_HOTSWAP_CTRL 0x80
+#define OEM_GRP_CMD_GET_SLOT_GA 0xa3
+#define IPMI_NETFN_SENSOR_EVT 0x10
+#define IPMI_CMD_GET_EVENT_RECEIVER 0x01
+
+#define IPMI_CPI1_PRODUCT_ID 0x000157
+#define IPMI_CPI1_MANUFACTURER_ID 0x0108
+
+static int ipmi_cpi1_detect (ipmi_user_t user)
+{
+ return ((mfg_id == IPMI_CPI1_MANUFACTURER_ID)
+ && (prod_id == IPMI_CPI1_PRODUCT_ID));
+}
+
+static void ipmi_poweroff_cpi1 (ipmi_user_t user)
+{
+ struct ipmi_system_interface_addr smi_addr;
+ struct ipmi_ipmb_addr ipmb_addr;
+ struct kernel_ipmi_msg send_msg;
+ int rv;
+ unsigned char data[1];
+ int slot;
+ unsigned char hotswap_ipmb;
+ unsigned char aer_addr;
+ unsigned char aer_lun;
+
+ /*
+ * Configure IPMI address for local access
+ */
+ smi_addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
+ smi_addr.channel = IPMI_BMC_CHANNEL;
+ smi_addr.lun = 0;
+
+ printk(KERN_INFO PFX "Powering down via CPI1 power command\n");
+
+ /*
+ * Get IPMI ipmb address
+ */
+ send_msg.netfn = IPMI_NETFN_OEM_8 >> 2;
+ send_msg.cmd = OEM_GRP_CMD_GET_SLOT_GA;
+ send_msg.data = NULL;
+ send_msg.data_len = 0;
+ rv = ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv)
+ goto out;
+ slot = halt_recv_msg.msg.data[1];
+ hotswap_ipmb = (slot > 9) ? (0xb0 + 2 * slot) : (0xae + 2 * slot);
+
+ /*
+ * Get active event receiver
+ */
+ send_msg.netfn = IPMI_NETFN_SENSOR_EVT >> 2;
+ send_msg.cmd = IPMI_CMD_GET_EVENT_RECEIVER;
+ send_msg.data = NULL;
+ send_msg.data_len = 0;
+ rv = ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv)
+ goto out;
+ aer_addr = halt_recv_msg.msg.data[1];
+ aer_lun = halt_recv_msg.msg.data[2];
+
+ /*
+ * Setup IPMB address target instead of local target
+ */
+ ipmb_addr.addr_type = IPMI_IPMB_ADDR_TYPE;
+ ipmb_addr.channel = 0;
+ ipmb_addr.slave_addr = aer_addr;
+ ipmb_addr.lun = aer_lun;
+
+ /*
+ * Send request hotswap control to remove blade from dpv
+ */
+ send_msg.netfn = IPMI_NETFN_OEM_8 >> 2;
+ send_msg.cmd = OEM_GRP_CMD_REQUEST_HOTSWAP_CTRL;
+ send_msg.data = &hotswap_ipmb;
+ send_msg.data_len = 1;
+ ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &ipmb_addr,
+ &send_msg);
+
+ /*
+ * Set reset asserted
+ */
+ send_msg.netfn = IPMI_NETFN_OEM_1 >> 2;
+ send_msg.cmd = OEM_GRP_CMD_SET_RESET_STATE;
+ send_msg.data = data;
+ data[0] = 1; /* Reset asserted state */
+ send_msg.data_len = 1;
+ rv = ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv)
+ goto out;
+
+ /*
+ * Power down
+ */
+ send_msg.netfn = IPMI_NETFN_OEM_1 >> 2;
+ send_msg.cmd = OEM_GRP_CMD_SET_POWER_STATE;
+ send_msg.data = data;
+ data[0] = 1; /* Power down state */
+ send_msg.data_len = 1;
+ rv = ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv)
+ goto out;
+
+ out:
+ return;
+}
+
+/*
+ * Standard chassis support
+ */
+
+#define IPMI_NETFN_CHASSIS_REQUEST 0
+#define IPMI_CHASSIS_CONTROL_CMD 0x02
+
+static int ipmi_chassis_detect (ipmi_user_t user)
+{
+ /* Chassis support, use it. */
+ return (capabilities & 0x80);
+}
+
+static void ipmi_poweroff_chassis (ipmi_user_t user)
+{
+ struct ipmi_system_interface_addr smi_addr;
+ struct kernel_ipmi_msg send_msg;
+ int rv;
+ unsigned char data[1];
+
+ /*
+ * Configure IPMI address for local access
+ */
+ smi_addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
+ smi_addr.channel = IPMI_BMC_CHANNEL;
+ smi_addr.lun = 0;
+
+ printk(KERN_INFO PFX "Powering down via IPMI chassis control command\n");
+
+ /*
+ * Power down
+ */
+ send_msg.netfn = IPMI_NETFN_CHASSIS_REQUEST;
+ send_msg.cmd = IPMI_CHASSIS_CONTROL_CMD;
+ data[0] = 0; /* Power down */
+ send_msg.data = data;
+ send_msg.data_len = sizeof(data);
+ rv = ipmi_request_in_rc_mode(user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv) {
+ printk(KERN_ERR PFX "Unable to send chassis powerdown message,"
+ " IPMI error 0x%x\n", rv);
+ goto out;
+ }
+
+ out:
+ return;
+}
+
+
+/* Table of possible power off functions. */
+struct poweroff_function {
+ char *platform_type;
+ int (*detect)(ipmi_user_t user);
+ void (*poweroff_func)(ipmi_user_t user);
+};
+
+static struct poweroff_function poweroff_functions[] = {
+ { "ATCA", ipmi_atca_detect, ipmi_poweroff_atca },
+ { "CPI1", ipmi_cpi1_detect, ipmi_poweroff_cpi1 },
+ /* Chassis should generally be last, other things should override
+ it. */
+ { "chassis", ipmi_chassis_detect, ipmi_poweroff_chassis },
+};
+#define NUM_PO_FUNCS (sizeof(poweroff_functions) \
+ / sizeof(struct poweroff_function))
+
+
+/* Our local state. */
+static int ready = 0;
+static ipmi_user_t ipmi_user;
+static void (*specific_poweroff_func)(ipmi_user_t user) = NULL;
+
+/* Holds the old poweroff function so we can restore it on removal. */
+static void (*old_poweroff_func)(void);
+
+
+/* Called on a powerdown request. */
+static void ipmi_poweroff_function (void)
+{
+ if (!ready)
+ return;
+
+ /* Use run-to-completion mode, since interrupts may be off. */
+ ipmi_user_set_run_to_completion(ipmi_user, 1);
+ specific_poweroff_func(ipmi_user);
+ ipmi_user_set_run_to_completion(ipmi_user, 0);
+}
+
+/* Wait for an IPMI interface to be installed, the first one installed
+ will be grabbed by this code and used to perform the powerdown. */
+static void ipmi_po_new_smi(int if_num)
+{
+ struct ipmi_system_interface_addr smi_addr;
+ struct kernel_ipmi_msg send_msg;
+ int rv;
+ int i;
+
+ if (ready)
+ return;
+
+ rv = ipmi_create_user(if_num, &ipmi_poweroff_handler, NULL, &ipmi_user);
+ if (rv) {
+ printk(KERN_ERR PFX "could not create IPMI user, error %d\n",
+ rv);
+ return;
+ }
+
+ /*
+ * Do a get device ide and store some results, since this is
+ * used by several functions.
+ */
+ smi_addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
+ smi_addr.channel = IPMI_BMC_CHANNEL;
+ smi_addr.lun = 0;
+
+ send_msg.netfn = IPMI_NETFN_APP_REQUEST;
+ send_msg.cmd = IPMI_GET_DEVICE_ID_CMD;
+ send_msg.data = NULL;
+ send_msg.data_len = 0;
+ rv = ipmi_request_wait_for_response(ipmi_user,
+ (struct ipmi_addr *) &smi_addr,
+ &send_msg);
+ if (rv) {
+ printk(KERN_ERR PFX "Unable to send IPMI get device id info,"
+ " IPMI error 0x%x\n", rv);
+ goto out_err;
+ }
+
+ if (halt_recv_msg.msg.data_len < 12) {
+ printk(KERN_ERR PFX "(chassis) IPMI get device id info too,"
+ " short, was %d bytes, needed %d bytes\n",
+ halt_recv_msg.msg.data_len, 12);
+ goto out_err;
+ }
+
+ mfg_id = (halt_recv_msg.msg.data[7]
+ | (halt_recv_msg.msg.data[8] << 8)
+ | (halt_recv_msg.msg.data[9] << 16));
+ prod_id = (halt_recv_msg.msg.data[10]
+ | (halt_recv_msg.msg.data[11] << 8));
+ capabilities = halt_recv_msg.msg.data[6];
+
+
+ /* Scan for a poweroff method */
+ for (i=0; i<NUM_PO_FUNCS; i++) {
+ if (poweroff_functions[i].detect(ipmi_user))
+ goto found;
+ }
+
+ out_err:
+ printk(KERN_ERR PFX "Unable to find a poweroff function that"
+ " will work, giving up\n");
+ ipmi_destroy_user(ipmi_user);
+ return;
+
+ found:
+ printk(KERN_INFO PFX "Found a %s style poweroff function\n",
+ poweroff_functions[i].platform_type);
+ specific_poweroff_func = poweroff_functions[i].poweroff_func;
+ old_poweroff_func = pm_power_off;
+ pm_power_off = ipmi_poweroff_function;
+ ready = 1;
+}
+
+static void ipmi_po_smi_gone(int if_num)
+{
+ /* This can never be called, because once poweroff driver is
+ registered, the interface can't go away until the power
+ driver is unregistered. */
+}
+
+static struct ipmi_smi_watcher smi_watcher =
+{
+ .owner = THIS_MODULE,
+ .new_smi = ipmi_po_new_smi,
+ .smi_gone = ipmi_po_smi_gone
+};
+
+
+/*
+ * Startup and shutdown functions.
+ */
+static int ipmi_poweroff_init (void)
+{
+ int rv;
+
+ printk ("Copyright (C) 2004 MontaVista Software -"
+ " IPMI Powerdown via sys_reboot version "
+ IPMI_POWEROFF_VERSION ".\n");
+
+ rv = ipmi_smi_watcher_register(&smi_watcher);
+ if (rv)
+ printk(KERN_ERR PFX "Unable to register SMI watcher: %d\n", rv);
+
+ return rv;
+}
+
+#ifdef MODULE
+static __exit void ipmi_poweroff_cleanup(void)
+{
+ int rv;
+
+ ipmi_smi_watcher_unregister(&smi_watcher);
+
+ if (ready) {
+ rv = ipmi_destroy_user(ipmi_user);
+ if (rv)
+ printk(KERN_ERR PFX "could not cleanup the IPMI"
+ " user: 0x%x\n", rv);
+ pm_power_off = old_poweroff_func;
+ }
+}
+module_exit(ipmi_poweroff_cleanup);
+#endif
+
+module_init(ipmi_poweroff_init);
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Intel Multimedia Timer device implementation for SGI SN platforms.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * This driver exports an API that should be supportable by any HPET or IA-PC
+ * multimedia timer. The code below is currently specific to the SGI Altix
+ * SHub RTC, however.
+ *
+ * 11/01/01 - jbarnes - initial revision
+ * 9/10/04 - Christoph Lameter - remove interrupt support for kernel inclusion
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/ioctl.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/mmtimer.h>
+#include <linux/miscdevice.h>
+#include <asm/uaccess.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/clksupport.h>
+
+MODULE_AUTHOR("Jesse Barnes <jbarnes@sgi.com>");
+MODULE_DESCRIPTION("Multimedia timer support");
+MODULE_LICENSE("GPL");
+
+/* name of the device, usually in /dev */
+#define MMTIMER_NAME "mmtimer"
+#define MMTIMER_DESC "IA-PC Multimedia Timer"
+#define MMTIMER_VERSION "1.0"
+
+#define RTC_BITS 55 /* 55 bits for this implementation */
+
+static int mmtimer_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+static int mmtimer_mmap(struct file *file, struct vm_area_struct *vma);
+
+/*
+ * Period in femtoseconds (10^-15 s)
+ */
+static unsigned long mmtimer_femtoperiod = 0;
+
+static struct file_operations mmtimer_fops = {
+ .owner = THIS_MODULE,
+ .mmap = mmtimer_mmap,
+ .ioctl = mmtimer_ioctl,
+};
+
+/**
+ * mmtimer_ioctl - ioctl interface for /dev/mmtimer
+ * @inode: inode of the device
+ * @file: file structure for the device
+ * @cmd: command to execute
+ * @arg: optional argument to command
+ *
+ * Executes the command specified by @cmd. Returns 0 for success, < 0 for
+ * failure.
+ *
+ * Valid commands:
+ *
+ * %MMTIMER_GETOFFSET - Should return the offset (relative to the start
+ * of the page where the registers are mapped) for the counter in question.
+ *
+ * %MMTIMER_GETRES - Returns the resolution of the clock in femto (10^-15)
+ * seconds
+ *
+ * %MMTIMER_GETFREQ - Copies the frequency of the clock in Hz to the address
+ * specified by @arg
+ *
+ * %MMTIMER_GETBITS - Returns the number of bits in the clock's counter
+ *
+ * %MMTIMER_MMAPAVAIL - Returns 1 if the registers can be mmap'd into userspace
+ *
+ * %MMTIMER_GETCOUNTER - Gets the current value in the counter and places it
+ * in the address specified by @arg.
+ */
+static int mmtimer_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ case MMTIMER_GETOFFSET: /* offset of the counter */
+ /*
+ * SN RTC registers are on their own 64k page
+ */
+ if(PAGE_SIZE <= (1 << 16))
+ ret = (((long)RTC_COUNTER_ADDR) & (PAGE_SIZE-1)) / 8;
+ else
+ ret = -ENOSYS;
+ break;
+
+ case MMTIMER_GETRES: /* resolution of the clock in 10^-15 s */
+ if(copy_to_user((unsigned long *)arg, &mmtimer_femtoperiod,
+ sizeof(unsigned long)))
+ return -EFAULT;
+ break;
+
+ case MMTIMER_GETFREQ: /* frequency in Hz */
+ if(copy_to_user((unsigned long *)arg,
+ &sn_rtc_cycles_per_second,
+ sizeof(unsigned long)))
+ return -EFAULT;
+ ret = 0;
+ break;
+
+ case MMTIMER_GETBITS: /* number of bits in the clock */
+ ret = RTC_BITS;
+ break;
+
+ case MMTIMER_MMAPAVAIL: /* can we mmap the clock into userspace? */
+ ret = (PAGE_SIZE <= (1 << 16)) ? 1 : 0;
+ break;
+
+ case MMTIMER_GETCOUNTER:
+ if(copy_to_user((unsigned long *)arg, RTC_COUNTER_ADDR,
+ sizeof(unsigned long)))
+ return -EFAULT;
+ break;
+ default:
+ ret = -ENOSYS;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * mmtimer_mmap - maps the clock's registers into userspace
+ * @file: file structure for the device
+ * @vma: VMA to map the registers into
+ *
+ * Calls remap_page_range() to map the clock's registers into
+ * the calling process' address space.
+ */
+static int mmtimer_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ unsigned long mmtimer_addr;
+
+ if (vma->vm_end - vma->vm_start != PAGE_SIZE)
+ return -EINVAL;
+
+ if (vma->vm_flags & VM_WRITE)
+ return -EPERM;
+
+ if (PAGE_SIZE > (1 << 16))
+ return -ENOSYS;
+
+ vma->vm_flags |= (VM_IO | VM_SHM | VM_LOCKED );
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ mmtimer_addr = __pa(RTC_COUNTER_ADDR);
+ mmtimer_addr &= ~(PAGE_SIZE - 1);
+ mmtimer_addr &= 0xfffffffffffffffUL;
+
+ if (remap_page_range(vma, vma->vm_start, mmtimer_addr, PAGE_SIZE,
+ vma->vm_page_prot)) {
+ printk(KERN_ERR "remap_page_range failed in mmtimer.c\n");
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static struct miscdevice mmtimer_miscdev = {
+ SGI_MMTIMER,
+ MMTIMER_NAME,
+ &mmtimer_fops
+};
+
+/**
+ * mmtimer_init - device initialization routine
+ *
+ * Does initial setup for the mmtimer device.
+ */
+static int __init mmtimer_init(void)
+{
+ if (!ia64_platform_is("sn2"))
+ return -1;
+
+ /*
+ * Sanity check the cycles/sec variable
+ */
+ if (sn_rtc_cycles_per_second < 100000) {
+ printk(KERN_ERR "%s: unable to determine clock frequency\n",
+ MMTIMER_NAME);
+ return -1;
+ }
+
+ mmtimer_femtoperiod = ((unsigned long)1E15 + sn_rtc_cycles_per_second /
+ 2) / sn_rtc_cycles_per_second;
+
+ strcpy(mmtimer_miscdev.devfs_name, MMTIMER_NAME);
+ if (misc_register(&mmtimer_miscdev)) {
+ printk(KERN_ERR "%s: failed to register device\n",
+ MMTIMER_NAME);
+ return -1;
+ }
+
+ printk(KERN_INFO "%s: v%s, %ld MHz\n", MMTIMER_DESC, MMTIMER_VERSION,
+ sn_rtc_cycles_per_second/(unsigned long)1E6);
+
+ return 0;
+}
+
+module_init(mmtimer_init);
+
--- /dev/null
+/*
+ * SN Platform system controller communication support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * System controller communication driver
+ *
+ * This driver allows a user process to communicate with the system
+ * controller (a.k.a. "IRouter") network in an SGI SN system.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/device.h>
+#include <linux/poll.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/nodepda.h>
+#include "snsc.h"
+
+#define SYSCTL_BASENAME "snsc"
+
+#define SCDRV_BUFSZ 2048
+#define SCDRV_TIMEOUT 1000
+
+static irqreturn_t
+scdrv_interrupt(int irq, void *subch_data, struct pt_regs *regs)
+{
+ struct subch_data_s *sd = subch_data;
+ unsigned long flags;
+ int status;
+
+ spin_lock_irqsave(&sd->sd_rlock, flags);
+ spin_lock(&sd->sd_wlock);
+ status = ia64_sn_irtr_intr(sd->sd_nasid, sd->sd_subch);
+
+ if (status > 0) {
+ if (status & SAL_IROUTER_INTR_RECV) {
+ wake_up(&sd->sd_rq);
+ }
+ if (status & SAL_IROUTER_INTR_XMIT) {
+ ia64_sn_irtr_intr_disable
+ (sd->sd_nasid, sd->sd_subch,
+ SAL_IROUTER_INTR_XMIT);
+ wake_up(&sd->sd_wq);
+ }
+ }
+ spin_unlock(&sd->sd_wlock);
+ spin_unlock_irqrestore(&sd->sd_rlock, flags);
+ return IRQ_HANDLED;
+}
+
+/*
+ * scdrv_open
+ *
+ * Reserve a subchannel for system controller communication.
+ */
+
+static int
+scdrv_open(struct inode *inode, struct file *file)
+{
+ struct sysctl_data_s *scd;
+ struct subch_data_s *sd;
+ int rv;
+
+ /* look up device info for this device file */
+ scd = container_of(inode->i_cdev, struct sysctl_data_s, scd_cdev);
+
+ /* allocate memory for subchannel data */
+ sd = kmalloc(sizeof (struct subch_data_s), GFP_KERNEL);
+ if (sd == NULL) {
+ printk("%s: couldn't allocate subchannel data\n",
+ __FUNCTION__);
+ return -ENOMEM;
+ }
+
+ /* initialize subch_data_s fields */
+ memset(sd, 0, sizeof (struct subch_data_s));
+ sd->sd_nasid = scd->scd_nasid;
+ sd->sd_subch = ia64_sn_irtr_open(scd->scd_nasid);
+
+ if (sd->sd_subch < 0) {
+ kfree(sd);
+ printk("%s: couldn't allocate subchannel\n", __FUNCTION__);
+ return -EBUSY;
+ }
+
+ spin_lock_init(&sd->sd_rlock);
+ spin_lock_init(&sd->sd_wlock);
+ init_waitqueue_head(&sd->sd_rq);
+ init_waitqueue_head(&sd->sd_wq);
+ sema_init(&sd->sd_rbs, 1);
+ sema_init(&sd->sd_wbs, 1);
+
+ file->private_data = sd;
+
+ /* hook this subchannel up to the system controller interrupt */
+ rv = request_irq(SGI_UART_VECTOR, scdrv_interrupt,
+ SA_SHIRQ | SA_INTERRUPT,
+ SYSCTL_BASENAME, sd);
+ if (rv) {
+ ia64_sn_irtr_close(sd->sd_nasid, sd->sd_subch);
+ kfree(sd);
+ printk("%s: irq request failed (%d)\n", __FUNCTION__, rv);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+/*
+ * scdrv_release
+ *
+ * Release a previously-reserved subchannel.
+ */
+
+static int
+scdrv_release(struct inode *inode, struct file *file)
+{
+ struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
+ int rv;
+
+ /* free the interrupt */
+ free_irq(SGI_UART_VECTOR, sd);
+
+ /* ask SAL to close the subchannel */
+ rv = ia64_sn_irtr_close(sd->sd_nasid, sd->sd_subch);
+
+ kfree(sd);
+ return rv;
+}
+
+/*
+ * scdrv_read
+ *
+ * Called to read bytes from the open IRouter pipe.
+ *
+ */
+
+static inline int
+read_status_check(struct subch_data_s *sd, int *len)
+{
+ return ia64_sn_irtr_recv(sd->sd_nasid, sd->sd_subch, sd->sd_rb, len);
+}
+
+static ssize_t
+scdrv_read(struct file *file, char __user *buf, size_t count, loff_t *f_pos)
+{
+ int status;
+ int len;
+ unsigned long flags;
+ struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
+
+ /* try to get control of the read buffer */
+ if (down_trylock(&sd->sd_rbs)) {
+ /* somebody else has it now;
+ * if we're non-blocking, then exit...
+ */
+ if (file->f_flags & O_NONBLOCK) {
+ return -EAGAIN;
+ }
+ /* ...or if we want to block, then do so here */
+ if (down_interruptible(&sd->sd_rbs)) {
+ /* something went wrong with wait */
+ return -ERESTARTSYS;
+ }
+ }
+
+ /* anything to read? */
+ len = CHUNKSIZE;
+ spin_lock_irqsave(&sd->sd_rlock, flags);
+ status = read_status_check(sd, &len);
+
+ /* if not, and we're blocking I/O, loop */
+ while (status < 0) {
+ DECLARE_WAITQUEUE(wait, current);
+
+ if (file->f_flags & O_NONBLOCK) {
+ spin_unlock_irqrestore(&sd->sd_rlock, flags);
+ up(&sd->sd_rbs);
+ return -EAGAIN;
+ }
+
+ len = CHUNKSIZE;
+ add_wait_queue(&sd->sd_rq, &wait);
+ set_current_state(TASK_INTERRUPTIBLE);
+ spin_unlock_irqrestore(&sd->sd_rlock, flags);
+
+ schedule_timeout(SCDRV_TIMEOUT);
+
+ remove_wait_queue(&sd->sd_rq, &wait);
+ if (signal_pending(current)) {
+ /* wait was interrupted */
+ up(&sd->sd_rbs);
+ return -ERESTARTSYS;
+ }
+
+ spin_lock_irqsave(&sd->sd_rlock, flags);
+ status = read_status_check(sd, &len);
+ }
+ spin_unlock_irqrestore(&sd->sd_rlock, flags);
+
+ if (len > 0) {
+ /* we read something in the last read_status_check(); copy
+ * it out to user space
+ */
+ if (count < len) {
+ pr_debug("%s: only accepting %d of %d bytes\n",
+ __FUNCTION__, (int) count, len);
+ }
+ len = min((int) count, len);
+ if (copy_to_user(buf, sd->sd_rb, len))
+ len = -EFAULT;
+ }
+
+ /* release the read buffer and wake anyone who might be
+ * waiting for it
+ */
+ up(&sd->sd_rbs);
+
+ /* return the number of characters read in */
+ return len;
+}
+
+/*
+ * scdrv_write
+ *
+ * Writes a chunk of an IRouter packet (or other system controller data)
+ * to the system controller.
+ *
+ */
+static inline int
+write_status_check(struct subch_data_s *sd, int count)
+{
+ return ia64_sn_irtr_send(sd->sd_nasid, sd->sd_subch, sd->sd_wb, count);
+}
+
+static ssize_t
+scdrv_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *f_pos)
+{
+ unsigned long flags;
+ int status;
+ struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
+
+ /* try to get control of the write buffer */
+ if (down_trylock(&sd->sd_wbs)) {
+ /* somebody else has it now;
+ * if we're non-blocking, then exit...
+ */
+ if (file->f_flags & O_NONBLOCK) {
+ return -EAGAIN;
+ }
+ /* ...or if we want to block, then do so here */
+ if (down_interruptible(&sd->sd_wbs)) {
+ /* something went wrong with wait */
+ return -ERESTARTSYS;
+ }
+ }
+
+ count = min((int) count, CHUNKSIZE);
+ if (copy_from_user(sd->sd_wb, buf, count)) {
+ up(&sd->sd_wbs);
+ return -EFAULT;
+ }
+
+ /* try to send the buffer */
+ spin_lock_irqsave(&sd->sd_wlock, flags);
+ status = write_status_check(sd, count);
+
+ /* if we failed, and we want to block, then loop */
+ while (status <= 0) {
+ DECLARE_WAITQUEUE(wait, current);
+
+ if (file->f_flags & O_NONBLOCK) {
+ spin_unlock(&sd->sd_wlock);
+ up(&sd->sd_wbs);
+ return -EAGAIN;
+ }
+
+ add_wait_queue(&sd->sd_wq, &wait);
+ set_current_state(TASK_INTERRUPTIBLE);
+ spin_unlock_irqrestore(&sd->sd_wlock, flags);
+
+ schedule_timeout(SCDRV_TIMEOUT);
+
+ remove_wait_queue(&sd->sd_wq, &wait);
+ if (signal_pending(current)) {
+ /* wait was interrupted */
+ up(&sd->sd_wbs);
+ return -ERESTARTSYS;
+ }
+
+ spin_lock_irqsave(&sd->sd_wlock, flags);
+ status = write_status_check(sd, count);
+ }
+ spin_unlock_irqrestore(&sd->sd_wlock, flags);
+
+ /* release the write buffer and wake anyone who's waiting for it */
+ up(&sd->sd_wbs);
+
+ /* return the number of characters accepted (should be the complete
+ * "chunk" as requested)
+ */
+ if ((status >= 0) && (status < count)) {
+ pr_debug("Didn't accept the full chunk; %d of %d\n",
+ status, (int) count);
+ }
+ return status;
+}
+
+static unsigned int
+scdrv_poll(struct file *file, struct poll_table_struct *wait)
+{
+ unsigned int mask = 0;
+ int status = 0;
+ struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
+ unsigned long flags;
+
+ poll_wait(file, &sd->sd_rq, wait);
+ poll_wait(file, &sd->sd_wq, wait);
+
+ spin_lock_irqsave(&sd->sd_rlock, flags);
+ spin_lock(&sd->sd_wlock);
+ status = ia64_sn_irtr_intr(sd->sd_nasid, sd->sd_subch);
+ spin_unlock(&sd->sd_wlock);
+ spin_unlock_irqrestore(&sd->sd_rlock, flags);
+
+ if (status > 0) {
+ if (status & SAL_IROUTER_INTR_RECV) {
+ mask |= POLLIN | POLLRDNORM;
+ }
+ if (status & SAL_IROUTER_INTR_XMIT) {
+ mask |= POLLOUT | POLLWRNORM;
+ }
+ }
+
+ return mask;
+}
+
+static struct file_operations scdrv_fops = {
+ .owner = THIS_MODULE,
+ .read = scdrv_read,
+ .write = scdrv_write,
+ .poll = scdrv_poll,
+ .open = scdrv_open,
+ .release = scdrv_release,
+};
+
+/*
+ * scdrv_init
+ *
+ * Called at boot time to initialize the system controller communication
+ * facility.
+ */
+int __init
+scdrv_init(void)
+{
+ geoid_t geoid;
+ cmoduleid_t cmod;
+ int i;
+ char devname[32];
+ char *devnamep;
+ module_t *m;
+ struct sysctl_data_s *scd;
+ void *salbuf;
+ struct class_simple *snsc_class;
+ dev_t first_dev, dev;
+
+ if (alloc_chrdev_region(&first_dev, 0, (MAX_SLABS*nummodules),
+ SYSCTL_BASENAME) < 0) {
+ printk("%s: failed to register SN system controller device\n",
+ __FUNCTION__);
+ return -ENODEV;
+ }
+ snsc_class = class_simple_create(THIS_MODULE, SYSCTL_BASENAME);
+
+ for (cmod = 0; cmod < nummodules; cmod++) {
+ m = sn_modules[cmod];
+ for (i = 0; i <= MAX_SLABS; i++) {
+
+ if (m->nodes[i] == -1) {
+ /* node is not alive in module */
+ continue;
+ }
+
+ geoid = m->geoid[i];
+ devnamep = devname;
+ format_module_id(devnamep, geo_module(geoid),
+ MODULE_FORMAT_BRIEF);
+ devnamep = devname + strlen(devname);
+ sprintf(devnamep, "#%d", geo_slab(geoid));
+
+ /* allocate sysctl device data */
+ scd = kmalloc(sizeof (struct sysctl_data_s),
+ GFP_KERNEL);
+ if (!scd) {
+ printk("%s: failed to allocate device info"
+ "for %s/%s\n", __FUNCTION__,
+ SYSCTL_BASENAME, devname);
+ continue;
+ }
+ memset(scd, 0, sizeof (struct sysctl_data_s));
+
+ /* initialize sysctl device data fields */
+ scd->scd_nasid = cnodeid_to_nasid(m->nodes[i]);
+ if (!(salbuf = kmalloc(SCDRV_BUFSZ, GFP_KERNEL))) {
+ printk("%s: failed to allocate driver buffer"
+ "(%s%s)\n", __FUNCTION__,
+ SYSCTL_BASENAME, devname);
+ kfree(scd);
+ continue;
+ }
+
+ if (ia64_sn_irtr_init(scd->scd_nasid, salbuf,
+ SCDRV_BUFSZ) < 0) {
+ printk
+ ("%s: failed to initialize SAL for"
+ " system controller communication"
+ " (%s/%s): outdated PROM?\n",
+ __FUNCTION__, SYSCTL_BASENAME, devname);
+ kfree(scd);
+ kfree(salbuf);
+ continue;
+ }
+
+ dev = first_dev + m->nodes[i];
+ cdev_init(&scd->scd_cdev, &scdrv_fops);
+ if (cdev_add(&scd->scd_cdev, dev, 1)) {
+ printk("%s: failed to register system"
+ " controller device (%s%s)\n",
+ __FUNCTION__, SYSCTL_BASENAME, devname);
+ kfree(scd);
+ kfree(salbuf);
+ continue;
+ }
+
+ class_simple_device_add(snsc_class, dev, NULL,
+ "%s", devname);
+
+ ia64_sn_irtr_intr_enable(scd->scd_nasid,
+ 0 /*ignored */ ,
+ SAL_IROUTER_INTR_RECV);
+ }
+ }
+ return 0;
+}
+
+module_init(scdrv_init);
--- /dev/null
+/*
+ * SN Platform system controller communication support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * This file contains macros and data types for communication with the
+ * system controllers in SGI SN systems.
+ */
+
+#ifndef _SN_SYSCTL_H_
+#define _SN_SYSCTL_H_
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/kobject.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <asm/sn/types.h>
+#include <asm/semaphore.h>
+
+#define CHUNKSIZE 127
+
+/* This structure is used to track an open subchannel. */
+struct subch_data_s {
+ nasid_t sd_nasid; /* node on which the subchannel was opened */
+ int sd_subch; /* subchannel number */
+ spinlock_t sd_rlock; /* monitor lock for rsv */
+ spinlock_t sd_wlock; /* monitor lock for wsv */
+ wait_queue_head_t sd_rq; /* wait queue for readers */
+ wait_queue_head_t sd_wq; /* wait queue for writers */
+ struct semaphore sd_rbs; /* semaphore for read buffer */
+ struct semaphore sd_wbs; /* semaphore for write buffer */
+
+ char sd_rb[CHUNKSIZE]; /* read buffer */
+ char sd_wb[CHUNKSIZE]; /* write buffer */
+};
+
+struct sysctl_data_s {
+ struct cdev scd_cdev; /* Character device info */
+ nasid_t scd_nasid; /* Node on which subchannels are opened. */
+};
+
+#endif /* _SN_SYSCTL_H_ */
--- /dev/null
+/*
+ * mpc8xx_wdt.c - MPC8xx watchdog userspace interface
+ *
+ * Author: Florian Schirmer <jolt@tuxbox.org>
+ *
+ * 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/watchdog.h>
+#include <asm/8xx_immap.h>
+#include <asm/uaccess.h>
+#include <syslib/m8xx_wdt.h>
+
+static unsigned long wdt_opened;
+static int wdt_status;
+
+static void mpc8xx_wdt_handler_disable(void)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+
+ imap->im_sit.sit_piscr &= ~(PISCR_PIE | PISCR_PTE);
+
+ printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler deactivated\n");
+}
+
+static void mpc8xx_wdt_handler_enable(void)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+
+ imap->im_sit.sit_piscr |= PISCR_PIE | PISCR_PTE;
+
+ printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler activated\n");
+}
+
+static int mpc8xx_wdt_open(struct inode *inode, struct file *file)
+{
+ if (test_and_set_bit(0, &wdt_opened))
+ return -EBUSY;
+
+ m8xx_wdt_reset();
+ mpc8xx_wdt_handler_disable();
+
+ return 0;
+}
+
+static int mpc8xx_wdt_release(struct inode *inode, struct file *file)
+{
+ m8xx_wdt_reset();
+
+#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
+ mpc8xx_wdt_handler_enable();
+#endif
+
+ clear_bit(0, &wdt_opened);
+
+ return 0;
+}
+
+static ssize_t mpc8xx_wdt_write(struct file *file, const char *data, size_t len,
+ loff_t * ppos)
+{
+ if (ppos != &file->f_pos)
+ return -ESPIPE;
+
+ if (len)
+ m8xx_wdt_reset();
+
+ return len;
+}
+
+static int mpc8xx_wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int timeout;
+ static struct watchdog_info info = {
+ .options = WDIOF_KEEPALIVEPING,
+ .firmware_version = 0,
+ .identity = "MPC8xx watchdog",
+ };
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ if (copy_to_user((void *)arg, &info, sizeof(info)))
+ return -EFAULT;
+ break;
+
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ if (put_user(wdt_status, (int *)arg))
+ return -EFAULT;
+ wdt_status &= ~WDIOF_KEEPALIVEPING;
+ break;
+
+ case WDIOC_GETTEMP:
+ return -EOPNOTSUPP;
+
+ case WDIOC_SETOPTIONS:
+ return -EOPNOTSUPP;
+
+ case WDIOC_KEEPALIVE:
+ m8xx_wdt_reset();
+ wdt_status |= WDIOF_KEEPALIVEPING;
+ break;
+
+ case WDIOC_SETTIMEOUT:
+ return -EOPNOTSUPP;
+
+ case WDIOC_GETTIMEOUT:
+ timeout = m8xx_wdt_get_timeout();
+ if (put_user(timeout, (int *)arg))
+ return -EFAULT;
+ break;
+
+ default:
+ return -ENOIOCTLCMD;
+ }
+
+ return 0;
+}
+
+static struct file_operations mpc8xx_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = mpc8xx_wdt_write,
+ .ioctl = mpc8xx_wdt_ioctl,
+ .open = mpc8xx_wdt_open,
+ .release = mpc8xx_wdt_release,
+};
+
+static struct miscdevice mpc8xx_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &mpc8xx_wdt_fops,
+};
+
+static int __init mpc8xx_wdt_init(void)
+{
+ return misc_register(&mpc8xx_wdt_miscdev);
+}
+
+static void __exit mpc8xx_wdt_exit(void)
+{
+ misc_deregister(&mpc8xx_wdt_miscdev);
+
+ m8xx_wdt_reset();
+ mpc8xx_wdt_handler_enable();
+}
+
+module_init(mpc8xx_wdt_init);
+module_exit(mpc8xx_wdt_exit);
+
+MODULE_AUTHOR("Florian Schirmer <jolt@tuxbox.org>");
+MODULE_DESCRIPTION("MPC8xx watchdog driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
--- /dev/null
+/*
+ * drivers/cpufreq/cpufreq_ondemand.c
+ *
+ * Copyright (C) 2001 Russell King
+ * (C) 2003 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>.
+ * Jun Nakajima <jun.nakajima@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/smp.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ctype.h>
+#include <linux/cpufreq.h>
+#include <linux/sysctl.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/sysfs.h>
+#include <linux/sched.h>
+#include <linux/kmod.h>
+#include <linux/workqueue.h>
+#include <linux/jiffies.h>
+#include <linux/config.h>
+#include <linux/kernel_stat.h>
+#include <linux/percpu.h>
+
+/*
+ * dbs is used in this file as a shortform for demandbased switching
+ * It helps to keep variable names smaller, simpler
+ */
+
+#define DEF_FREQUENCY_UP_THRESHOLD (80)
+#define MIN_FREQUENCY_UP_THRESHOLD (0)
+#define MAX_FREQUENCY_UP_THRESHOLD (100)
+
+#define DEF_FREQUENCY_DOWN_THRESHOLD (20)
+#define MIN_FREQUENCY_DOWN_THRESHOLD (0)
+#define MAX_FREQUENCY_DOWN_THRESHOLD (100)
+
+/*
+ * The polling frequency of this governor depends on the capability of
+ * the processor. Default polling frequency is 1000 times the transition
+ * latency of the processor. The governor will work on any processor with
+ * transition latency <= 10mS, using appropriate sampling
+ * rate.
+ * For CPUs with transition latency > 10mS (mostly drivers with CPUFREQ_ETERNAL)
+ * this governor will not work.
+ * All times here are in uS.
+ */
+static unsigned int def_sampling_rate;
+#define MIN_SAMPLING_RATE (def_sampling_rate / 2)
+#define MAX_SAMPLING_RATE (500 * def_sampling_rate)
+#define DEF_SAMPLING_RATE_LATENCY_MULTIPLIER (1000)
+#define DEF_SAMPLING_DOWN_FACTOR (10)
+#define TRANSITION_LATENCY_LIMIT (10 * 1000)
+#define sampling_rate_in_HZ(x) (((x * HZ) < (1000 * 1000))?1:((x * HZ) / (1000 * 1000)))
+
+static void do_dbs_timer(void *data);
+
+struct cpu_dbs_info_s {
+ struct cpufreq_policy *cur_policy;
+ unsigned int prev_cpu_idle_up;
+ unsigned int prev_cpu_idle_down;
+ unsigned int enable;
+};
+static DEFINE_PER_CPU(struct cpu_dbs_info_s, cpu_dbs_info);
+
+static unsigned int dbs_enable; /* number of CPUs using this policy */
+
+static DECLARE_MUTEX (dbs_sem);
+static DECLARE_WORK (dbs_work, do_dbs_timer, NULL);
+
+struct dbs_tuners {
+ unsigned int sampling_rate;
+ unsigned int sampling_down_factor;
+ unsigned int up_threshold;
+ unsigned int down_threshold;
+};
+
+struct dbs_tuners dbs_tuners_ins = {
+ .up_threshold = DEF_FREQUENCY_UP_THRESHOLD,
+ .down_threshold = DEF_FREQUENCY_DOWN_THRESHOLD,
+ .sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR,
+};
+
+/************************** sysfs interface ************************/
+static ssize_t show_sampling_rate_max(struct cpufreq_policy *policy, char *buf)
+{
+ return sprintf (buf, "%u\n", MAX_SAMPLING_RATE);
+}
+
+static ssize_t show_sampling_rate_min(struct cpufreq_policy *policy, char *buf)
+{
+ return sprintf (buf, "%u\n", MIN_SAMPLING_RATE);
+}
+
+#define define_one_ro(_name) \
+static struct freq_attr _name = { \
+ .attr = { .name = __stringify(_name), .mode = 0444 }, \
+ .show = show_##_name, \
+}
+
+define_one_ro(sampling_rate_max);
+define_one_ro(sampling_rate_min);
+
+/* cpufreq_ondemand Governor Tunables */
+#define show_one(file_name, object) \
+static ssize_t show_##file_name \
+(struct cpufreq_policy *unused, char *buf) \
+{ \
+ return sprintf(buf, "%u\n", dbs_tuners_ins.object); \
+}
+show_one(sampling_rate, sampling_rate);
+show_one(sampling_down_factor, sampling_down_factor);
+show_one(up_threshold, up_threshold);
+show_one(down_threshold, down_threshold);
+
+static ssize_t store_sampling_down_factor(struct cpufreq_policy *unused,
+ const char *buf, size_t count)
+{
+ unsigned int input;
+ int ret;
+ ret = sscanf (buf, "%u", &input);
+ down(&dbs_sem);
+ if (ret != 1 )
+ goto out;
+
+ dbs_tuners_ins.sampling_down_factor = input;
+out:
+ up(&dbs_sem);
+ return count;
+}
+
+static ssize_t store_sampling_rate(struct cpufreq_policy *unused,
+ const char *buf, size_t count)
+{
+ unsigned int input;
+ int ret;
+ ret = sscanf (buf, "%u", &input);
+ down(&dbs_sem);
+ if (ret != 1 || input > MAX_SAMPLING_RATE || input < MIN_SAMPLING_RATE)
+ goto out;
+
+ dbs_tuners_ins.sampling_rate = input;
+out:
+ up(&dbs_sem);
+ return count;
+}
+
+static ssize_t store_up_threshold(struct cpufreq_policy *unused,
+ const char *buf, size_t count)
+{
+ unsigned int input;
+ int ret;
+ ret = sscanf (buf, "%u", &input);
+ down(&dbs_sem);
+ if (ret != 1 || input > MAX_FREQUENCY_UP_THRESHOLD ||
+ input < MIN_FREQUENCY_UP_THRESHOLD ||
+ input <= dbs_tuners_ins.down_threshold)
+ goto out;
+
+ dbs_tuners_ins.up_threshold = input;
+out:
+ up(&dbs_sem);
+ return count;
+}
+
+static ssize_t store_down_threshold(struct cpufreq_policy *unused,
+ const char *buf, size_t count)
+{
+ unsigned int input;
+ int ret;
+ ret = sscanf (buf, "%u", &input);
+ down(&dbs_sem);
+ if (ret != 1 || input > MAX_FREQUENCY_DOWN_THRESHOLD ||
+ input < MIN_FREQUENCY_DOWN_THRESHOLD ||
+ input >= dbs_tuners_ins.up_threshold)
+ goto out;
+
+ dbs_tuners_ins.down_threshold = input;
+out:
+ up(&dbs_sem);
+ return count;
+}
+
+#define define_one_rw(_name) \
+static struct freq_attr _name = { \
+ .attr = { .name = __stringify(_name), .mode = 0644 }, \
+ .show = show_##_name, \
+ .store = store_##_name, \
+}
+
+define_one_rw(sampling_rate);
+define_one_rw(sampling_down_factor);
+define_one_rw(up_threshold);
+define_one_rw(down_threshold);
+
+static struct attribute * dbs_attributes[] = {
+ &sampling_rate_max.attr,
+ &sampling_rate_min.attr,
+ &sampling_rate.attr,
+ &sampling_down_factor.attr,
+ &up_threshold.attr,
+ &down_threshold.attr,
+ NULL
+};
+
+static struct attribute_group dbs_attr_group = {
+ .attrs = dbs_attributes,
+ .name = "ondemand",
+};
+
+/************************** sysfs end ************************/
+
+static void dbs_check_cpu(int cpu)
+{
+ unsigned int idle_ticks, up_idle_ticks, down_idle_ticks;
+ unsigned int total_idle_ticks;
+ unsigned int freq_down_step;
+ unsigned int freq_down_sampling_rate;
+ static int down_skip[NR_CPUS];
+ struct cpu_dbs_info_s *this_dbs_info;
+
+ this_dbs_info = &per_cpu(cpu_dbs_info, cpu);
+ if (!this_dbs_info->enable)
+ return;
+
+ /*
+ * The default safe range is 20% to 80%
+ * Every sampling_rate, we check
+ * - If current idle time is less than 20%, then we try to
+ * increase frequency
+ * Every sampling_rate*sampling_down_factor, we check
+ * - If current idle time is more than 80%, then we try to
+ * decrease frequency
+ *
+ * Any frequency increase takes it to the maximum frequency.
+ * Frequency reduction happens at minimum steps of
+ * 5% of max_frequency
+ */
+ /* Check for frequency increase */
+ total_idle_ticks = kstat_cpu(cpu).cpustat.idle +
+ kstat_cpu(cpu).cpustat.iowait;
+ idle_ticks = total_idle_ticks -
+ this_dbs_info->prev_cpu_idle_up;
+ this_dbs_info->prev_cpu_idle_up = total_idle_ticks;
+
+ /* Scale idle ticks by 100 and compare with up and down ticks */
+ idle_ticks *= 100;
+ up_idle_ticks = (100 - dbs_tuners_ins.up_threshold) *
+ sampling_rate_in_HZ(dbs_tuners_ins.sampling_rate);
+
+ if (idle_ticks < up_idle_ticks) {
+ __cpufreq_driver_target(this_dbs_info->cur_policy,
+ this_dbs_info->cur_policy->max,
+ CPUFREQ_RELATION_H);
+ down_skip[cpu] = 0;
+ this_dbs_info->prev_cpu_idle_down = total_idle_ticks;
+ return;
+ }
+
+ /* Check for frequency decrease */
+ down_skip[cpu]++;
+ if (down_skip[cpu] < dbs_tuners_ins.sampling_down_factor)
+ return;
+
+ idle_ticks = total_idle_ticks -
+ this_dbs_info->prev_cpu_idle_down;
+ /* Scale idle ticks by 100 and compare with up and down ticks */
+ idle_ticks *= 100;
+ down_skip[cpu] = 0;
+ this_dbs_info->prev_cpu_idle_down = total_idle_ticks;
+
+ freq_down_sampling_rate = dbs_tuners_ins.sampling_rate *
+ dbs_tuners_ins.sampling_down_factor;
+ down_idle_ticks = (100 - dbs_tuners_ins.down_threshold) *
+ sampling_rate_in_HZ(freq_down_sampling_rate);
+
+ if (idle_ticks > down_idle_ticks ) {
+ freq_down_step = (5 * this_dbs_info->cur_policy->max) / 100;
+
+ /* max freq cannot be less than 100. But who knows.... */
+ if (unlikely(freq_down_step == 0))
+ freq_down_step = 5;
+
+ __cpufreq_driver_target(this_dbs_info->cur_policy,
+ this_dbs_info->cur_policy->cur - freq_down_step,
+ CPUFREQ_RELATION_H);
+ return;
+ }
+}
+
+static void do_dbs_timer(void *data)
+{
+ int i;
+ down(&dbs_sem);
+ for (i = 0; i < NR_CPUS; i++)
+ if (cpu_online(i))
+ dbs_check_cpu(i);
+ schedule_delayed_work(&dbs_work,
+ sampling_rate_in_HZ(dbs_tuners_ins.sampling_rate));
+ up(&dbs_sem);
+}
+
+static inline void dbs_timer_init(void)
+{
+ INIT_WORK(&dbs_work, do_dbs_timer, NULL);
+ schedule_work(&dbs_work);
+ return;
+}
+
+static inline void dbs_timer_exit(void)
+{
+ cancel_delayed_work(&dbs_work);
+ return;
+}
+
+static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
+ unsigned int event)
+{
+ unsigned int cpu = policy->cpu;
+ struct cpu_dbs_info_s *this_dbs_info;
+
+ this_dbs_info = &per_cpu(cpu_dbs_info, cpu);
+
+ switch (event) {
+ case CPUFREQ_GOV_START:
+ if ((!cpu_online(cpu)) ||
+ (!policy->cur))
+ return -EINVAL;
+
+ if (policy->cpuinfo.transition_latency >
+ (TRANSITION_LATENCY_LIMIT * 1000))
+ return -EINVAL;
+ if (this_dbs_info->enable) /* Already enabled */
+ break;
+
+ down(&dbs_sem);
+ this_dbs_info->cur_policy = policy;
+
+ this_dbs_info->prev_cpu_idle_up =
+ kstat_cpu(cpu).cpustat.idle +
+ kstat_cpu(cpu).cpustat.iowait;
+ this_dbs_info->prev_cpu_idle_down =
+ kstat_cpu(cpu).cpustat.idle +
+ kstat_cpu(cpu).cpustat.iowait;
+ this_dbs_info->enable = 1;
+ sysfs_create_group(&policy->kobj, &dbs_attr_group);
+ dbs_enable++;
+ /*
+ * Start the timerschedule work, when this governor
+ * is used for first time
+ */
+ if (dbs_enable == 1) {
+ unsigned int latency;
+ /* policy latency is in nS. Convert it to uS first */
+
+ latency = policy->cpuinfo.transition_latency;
+ if (latency < 1000)
+ latency = 1000;
+
+ def_sampling_rate = (latency / 1000) *
+ DEF_SAMPLING_RATE_LATENCY_MULTIPLIER;
+ dbs_tuners_ins.sampling_rate = def_sampling_rate;
+
+ dbs_timer_init();
+ }
+
+ up(&dbs_sem);
+ break;
+
+ case CPUFREQ_GOV_STOP:
+ down(&dbs_sem);
+ this_dbs_info->enable = 0;
+ sysfs_remove_group(&policy->kobj, &dbs_attr_group);
+ dbs_enable--;
+ /*
+ * Stop the timerschedule work, when this governor
+ * is used for first time
+ */
+ if (dbs_enable == 0)
+ dbs_timer_exit();
+
+ up(&dbs_sem);
+
+ break;
+
+ case CPUFREQ_GOV_LIMITS:
+ down(&dbs_sem);
+ if (policy->max < this_dbs_info->cur_policy->cur)
+ __cpufreq_driver_target(
+ this_dbs_info->cur_policy,
+ policy->max, CPUFREQ_RELATION_H);
+ else if (policy->min > this_dbs_info->cur_policy->cur)
+ __cpufreq_driver_target(
+ this_dbs_info->cur_policy,
+ policy->min, CPUFREQ_RELATION_L);
+ up(&dbs_sem);
+ break;
+ }
+ return 0;
+}
+
+struct cpufreq_governor cpufreq_gov_dbs = {
+ .name = "ondemand",
+ .governor = cpufreq_governor_dbs,
+ .owner = THIS_MODULE,
+};
+EXPORT_SYMBOL(cpufreq_gov_dbs);
+
+static int __init cpufreq_gov_dbs_init(void)
+{
+ return cpufreq_register_governor(&cpufreq_gov_dbs);
+}
+
+static void __exit cpufreq_gov_dbs_exit(void)
+{
+ /* Make sure that the scheduled work is indeed not running */
+ flush_scheduled_work();
+
+ cpufreq_unregister_governor(&cpufreq_gov_dbs);
+}
+
+
+MODULE_AUTHOR ("Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>");
+MODULE_DESCRIPTION ("'cpufreq_ondemand' - A dynamic cpufreq governor for "
+ "Low Latency Frequency Transition capable processors");
+MODULE_LICENSE ("GPL");
+
+module_init(cpufreq_gov_dbs_init);
+module_exit(cpufreq_gov_dbs_exit);
--- /dev/null
+/*
+ * i2c-algo-pca.c i2c driver algorithms for PCA9564 adapters
+ * Copyright (C) 2004 Arcom Control Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-pca.h>
+#include "i2c-algo-pca.h"
+
+#define DRIVER "i2c-algo-pca"
+
+#define DEB1(fmt, args...) do { if (i2c_debug>=1) printk(fmt, ## args); } while(0)
+#define DEB2(fmt, args...) do { if (i2c_debug>=2) printk(fmt, ## args); } while(0)
+#define DEB3(fmt, args...) do { if (i2c_debug>=3) printk(fmt, ## args); } while(0)
+
+static int i2c_debug=0;
+
+#define pca_outw(adap, reg, val) adap->write_byte(adap, reg, val)
+#define pca_inw(adap, reg) adap->read_byte(adap, reg)
+
+#define pca_status(adap) pca_inw(adap, I2C_PCA_STA)
+#define pca_clock(adap) adap->get_clock(adap)
+#define pca_own(adap) adap->get_own(adap)
+#define pca_set_con(adap, val) pca_outw(adap, I2C_PCA_CON, val)
+#define pca_get_con(adap) pca_inw(adap, I2C_PCA_CON)
+#define pca_wait(adap) adap->wait_for_interrupt(adap)
+
+/*
+ * Generate a start condition on the i2c bus.
+ *
+ * returns after the start condition has occured
+ */
+static void pca_start(struct i2c_algo_pca_data *adap)
+{
+ int sta = pca_get_con(adap);
+ DEB2("=== START\n");
+ sta |= I2C_PCA_CON_STA;
+ sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_SI);
+ pca_set_con(adap, sta);
+ pca_wait(adap);
+}
+
+/*
+ * Generate a repeated start condition on the i2c bus
+ *
+ * return after the repeated start condition has occured
+ */
+static void pca_repeated_start(struct i2c_algo_pca_data *adap)
+{
+ int sta = pca_get_con(adap);
+ DEB2("=== REPEATED START\n");
+ sta |= I2C_PCA_CON_STA;
+ sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_SI);
+ pca_set_con(adap, sta);
+ pca_wait(adap);
+}
+
+/*
+ * Generate a stop condition on the i2c bus
+ *
+ * returns after the stop condition has been generated
+ *
+ * STOPs do not generate an interrupt or set the SI flag, since the
+ * part returns the the idle state (0xf8). Hence we don't need to
+ * pca_wait here.
+ */
+static void pca_stop(struct i2c_algo_pca_data *adap)
+{
+ int sta = pca_get_con(adap);
+ DEB2("=== STOP\n");
+ sta |= I2C_PCA_CON_STO;
+ sta &= ~(I2C_PCA_CON_STA|I2C_PCA_CON_SI);
+ pca_set_con(adap, sta);
+}
+
+/*
+ * Send the slave address and R/W bit
+ *
+ * returns after the address has been sent
+ */
+static void pca_address(struct i2c_algo_pca_data *adap,
+ struct i2c_msg *msg)
+{
+ int sta = pca_get_con(adap);
+ int addr;
+
+ addr = ( (0x7f & msg->addr) << 1 );
+ if (msg->flags & I2C_M_RD )
+ addr |= 1;
+ DEB2("=== SLAVE ADDRESS %#04x+%c=%#04x\n",
+ msg->addr, msg->flags & I2C_M_RD ? 'R' : 'W', addr);
+
+ pca_outw(adap, I2C_PCA_DAT, addr);
+
+ sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI);
+ pca_set_con(adap, sta);
+
+ pca_wait(adap);
+}
+
+/*
+ * Transmit a byte.
+ *
+ * Returns after the byte has been transmitted
+ */
+static void pca_tx_byte(struct i2c_algo_pca_data *adap,
+ __u8 b)
+{
+ int sta = pca_get_con(adap);
+ DEB2("=== WRITE %#04x\n", b);
+ pca_outw(adap, I2C_PCA_DAT, b);
+
+ sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI);
+ pca_set_con(adap, sta);
+
+ pca_wait(adap);
+}
+
+/*
+ * Receive a byte
+ *
+ * returns immediately.
+ */
+static void pca_rx_byte(struct i2c_algo_pca_data *adap,
+ __u8 *b, int ack)
+{
+ *b = pca_inw(adap, I2C_PCA_DAT);
+ DEB2("=== READ %#04x %s\n", *b, ack ? "ACK" : "NACK");
+}
+
+/*
+ * Setup ACK or NACK for next received byte and wait for it to arrive.
+ *
+ * Returns after next byte has arrived.
+ */
+static void pca_rx_ack(struct i2c_algo_pca_data *adap,
+ int ack)
+{
+ int sta = pca_get_con(adap);
+
+ sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI|I2C_PCA_CON_AA);
+
+ if ( ack )
+ sta |= I2C_PCA_CON_AA;
+
+ pca_set_con(adap, sta);
+ pca_wait(adap);
+}
+
+/*
+ * Reset the i2c bus / SIO
+ */
+static void pca_reset(struct i2c_algo_pca_data *adap)
+{
+ /* apparently only an external reset will do it. not a lot can be done */
+ printk(KERN_ERR DRIVER ": Haven't figured out how to do a reset yet\n");
+}
+
+static int pca_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg msgs[],
+ int num)
+{
+ struct i2c_algo_pca_data *adap = i2c_adap->algo_data;
+ struct i2c_msg *msg = NULL;
+ int curmsg;
+ int numbytes = 0;
+ int state;
+
+ state = pca_status(adap);
+ if ( state != 0xF8 ) {
+ printk(KERN_ERR DRIVER ": bus is not idle. status is %#04x\n", state );
+ /* FIXME: what to do. Force stop ? */
+ return -EREMOTEIO;
+ }
+
+ DEB1("{{{ XFER %d messages\n", num);
+
+ if (i2c_debug>=2) {
+ for (curmsg = 0; curmsg < num; curmsg++) {
+ int addr, i;
+ msg = &msgs[curmsg];
+
+ addr = (0x7f & msg->addr) ;
+
+ if (msg->flags & I2C_M_RD )
+ printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
+ curmsg, msg->len, addr, (addr<<1) | 1);
+ else {
+ printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
+ curmsg, msg->len, addr, addr<<1,
+ msg->len == 0 ? "" : ", ");
+ for(i=0; i < msg->len; i++)
+ printk("%#04x%s", msg->buf[i], i == msg->len - 1 ? "" : ", ");
+ printk("]\n");
+ }
+ }
+ }
+
+ curmsg = 0;
+ while (curmsg < num) {
+ state = pca_status(adap);
+
+ DEB3("STATE is 0x%02x\n", state);
+ msg = &msgs[curmsg];
+
+ switch (state) {
+ case 0xf8: /* On reset or stop the bus is idle */
+ pca_start(adap);
+ break;
+
+ case 0x08: /* A START condition has been transmitted */
+ case 0x10: /* A repeated start condition has been transmitted */
+ pca_address(adap, msg);
+ break;
+
+ case 0x18: /* SLA+W has been transmitted; ACK has been received */
+ case 0x28: /* Data byte in I2CDAT has been transmitted; ACK has been received */
+ if (numbytes < msg->len) {
+ pca_tx_byte(adap, msg->buf[numbytes]);
+ numbytes++;
+ break;
+ }
+ curmsg++; numbytes = 0;
+ if (curmsg == num)
+ pca_stop(adap);
+ else
+ pca_repeated_start(adap);
+ break;
+
+ case 0x20: /* SLA+W has been transmitted; NOT ACK has been received */
+ DEB2("NOT ACK recieved after SLA+W\n");
+ pca_stop(adap);
+ return -EREMOTEIO;
+
+ case 0x40: /* SLA+R has been transmitted; ACK has been received */
+ pca_rx_ack(adap, msg->len > 1);
+ break;
+
+ case 0x50: /* Data bytes has been received; ACK has been returned */
+ if (numbytes < msg->len) {
+ pca_rx_byte(adap, &msg->buf[numbytes], 1);
+ numbytes++;
+ pca_rx_ack(adap, numbytes < msg->len - 1);
+ break;
+ }
+ curmsg++; numbytes = 0;
+ if (curmsg == num)
+ pca_stop(adap);
+ else
+ pca_repeated_start(adap);
+ break;
+
+ case 0x48: /* SLA+R has been transmitted; NOT ACK has been received */
+ DEB2("NOT ACK received after SLA+R\n");
+ pca_stop(adap);
+ return -EREMOTEIO;
+
+ case 0x30: /* Data byte in I2CDAT has been transmitted; NOT ACK has been received */
+ DEB2("NOT ACK recieved after data byte\n");
+ return -EREMOTEIO;
+
+ case 0x38: /* Arbitration lost during SLA+W, SLA+R or data bytes */
+ DEB2("Arbitration lost\n");
+ return -EREMOTEIO;
+
+ case 0x58: /* Data byte has been received; NOT ACK has been returned */
+ if ( numbytes == msg->len - 1 ) {
+ pca_rx_byte(adap, &msg->buf[numbytes], 0);
+ curmsg++; numbytes = 0;
+ if (curmsg == num)
+ pca_stop(adap);
+ else
+ pca_repeated_start(adap);
+ } else {
+ DEB2("NOT ACK sent after data byte received. "
+ "Not final byte. numbytes %d. len %d\n",
+ numbytes, msg->len);
+ pca_stop(adap);
+ return -EREMOTEIO;
+ }
+ break;
+ case 0x70: /* Bus error - SDA stuck low */
+ DEB2("BUS ERROR - SDA Stuck low\n");
+ pca_reset(adap);
+ return -EREMOTEIO;
+ case 0x90: /* Bus error - SCL stuck low */
+ DEB2("BUS ERROR - SCL Stuck low\n");
+ pca_reset(adap);
+ return -EREMOTEIO;
+ case 0x00: /* Bus error during master or slave mode due to illegal START or STOP condition */
+ DEB2("BUS ERROR - Illegal START or STOP\n");
+ pca_reset(adap);
+ return -EREMOTEIO;
+ default:
+ printk(KERN_ERR DRIVER ": unhandled SIO state 0x%02x\n", state);
+ break;
+ }
+
+ }
+
+ DEB1(KERN_CRIT "}}} transfered %d messages. "
+ "status is %#04x. control is %#04x\n",
+ num, pca_status(adap),
+ pca_get_con(adap));
+ return curmsg;
+}
+
+static u32 pca_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_SMBUS_EMUL;
+}
+
+static int pca_init(struct i2c_algo_pca_data *adap)
+{
+ static int freqs[] = {330,288,217,146,88,59,44,36};
+ int own, clock;
+
+ own = pca_own(adap);
+ clock = pca_clock(adap);
+ DEB1(KERN_INFO DRIVER ": own address is %#04x\n", own);
+ DEB1(KERN_INFO DRIVER ": clock freqeuncy is %dkHz\n", freqs[clock]);
+
+ pca_outw(adap, I2C_PCA_ADR, own << 1);
+
+ pca_set_con(adap, I2C_PCA_CON_ENSIO | clock);
+ udelay(500); /* 500 µs for oscilator to stabilise */
+
+ return 0;
+}
+
+static struct i2c_algorithm pca_algo = {
+ .name = "PCA9564 algorithm",
+ .id = I2C_ALGO_PCA,
+ .master_xfer = pca_xfer,
+ .functionality = pca_func,
+};
+
+/*
+ * registering functions to load algorithms at runtime
+ */
+int i2c_pca_add_bus(struct i2c_adapter *adap)
+{
+ struct i2c_algo_pca_data *pca_adap = adap->algo_data;
+ int rval;
+
+ /* register new adapter to i2c module... */
+
+ adap->id |= pca_algo.id;
+ adap->algo = &pca_algo;
+
+ adap->timeout = 100; /* default values, should */
+ adap->retries = 3; /* be replaced by defines */
+
+ rval = pca_init(pca_adap);
+
+ if (!rval)
+ i2c_add_adapter(adap);
+
+ return rval;
+}
+
+int i2c_pca_del_bus(struct i2c_adapter *adap)
+{
+ return i2c_del_adapter(adap);
+}
+
+EXPORT_SYMBOL(i2c_pca_add_bus);
+EXPORT_SYMBOL(i2c_pca_del_bus);
+
+MODULE_AUTHOR("Ian Campbell <icampbell@arcom.com>");
+MODULE_DESCRIPTION("I2C-Bus PCA9564 algorithm");
+MODULE_LICENSE("GPL");
+
+module_param(i2c_debug, int, 0);
--- /dev/null
+#ifndef I2C_PCA9564_H
+#define I2C_PCA9564_H 1
+
+#define I2C_PCA_STA 0x00 /* STATUS Read Only */
+#define I2C_PCA_TO 0x00 /* TIMEOUT Write Only */
+#define I2C_PCA_DAT 0x01 /* DATA Read/Write */
+#define I2C_PCA_ADR 0x02 /* OWN ADR Read/Write */
+#define I2C_PCA_CON 0x03 /* CONTROL Read/Write */
+
+#define I2C_PCA_CON_AA 0x80 /* Assert Acknowledge */
+#define I2C_PCA_CON_ENSIO 0x40 /* Enable */
+#define I2C_PCA_CON_STA 0x20 /* Start */
+#define I2C_PCA_CON_STO 0x10 /* Stop */
+#define I2C_PCA_CON_SI 0x08 /* Serial Interrupt */
+#define I2C_PCA_CON_CR 0x07 /* Clock Rate (MASK) */
+
+#define I2C_PCA_CON_330kHz 0x00
+#define I2C_PCA_CON_288kHz 0x01
+#define I2C_PCA_CON_217kHz 0x02
+#define I2C_PCA_CON_146kHz 0x03
+#define I2C_PCA_CON_88kHz 0x04
+#define I2C_PCA_CON_59kHz 0x05
+#define I2C_PCA_CON_44kHz 0x06
+#define I2C_PCA_CON_36kHz 0x07
+
+#endif /* I2C_PCA9564_H */
--- /dev/null
+/*
+ * drivers/i2c/busses/i2c-ixp2000.c
+ *
+ * I2C adapter for IXP2000 systems using GPIOs for I2C bus
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ * Based on IXDP2400 code by: Naeem M. Afzal <naeem.m.afzal@intel.com>
+ * Made generic by: Jeff Daly <jeffrey.daly@intel.com>
+ *
+ * Copyright (c) 2003-2004 MontaVista Software Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * From Jeff Daly:
+ *
+ * I2C adapter driver for Intel IXDP2xxx platforms. This should work for any
+ * IXP2000 platform if it uses the HW GPIO in the same manner. Basically,
+ * SDA and SCL GPIOs have external pullups. Setting the respective GPIO to
+ * an input will make the signal a '1' via the pullup. Setting them to
+ * outputs will pull them down.
+ *
+ * The GPIOs are open drain signals and are used as configuration strap inputs
+ * during power-up so there's generally a buffer on the board that needs to be
+ * 'enabled' to drive the GPIOs.
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_I2C_DEBUG_BUS
+#define DEBUG 1
+#endif
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+
+#include <asm/hardware.h> /* Pick up IXP42000-specific bits */
+
+static inline int ixp2000_scl_pin(void *data)
+{
+ return ((struct ixp2000_i2c_pins*)data)->scl_pin;
+}
+
+static inline int ixp2000_sda_pin(void *data)
+{
+ return ((struct ixp2000_i2c_pins*)data)->sda_pin;
+}
+
+
+static void ixp2000_bit_setscl(void *data, int val)
+{
+ int i = 5000;
+
+ if (val) {
+ gpio_line_config(ixp2000_scl_pin(data), GPIO_IN);
+ while(!gpio_line_get(ixp2000_scl_pin(data)) && i--);
+ } else {
+ gpio_line_config(ixp2000_scl_pin(data), GPIO_OUT);
+ }
+}
+
+static void ixp2000_bit_setsda(void *data, int val)
+{
+ if (val) {
+ gpio_line_config(ixp2000_sda_pin(data), GPIO_IN);
+ } else {
+ gpio_line_config(ixp2000_sda_pin(data), GPIO_OUT);
+ }
+}
+
+static int ixp2000_bit_getscl(void *data)
+{
+ return gpio_line_get(ixp2000_scl_pin(data));
+}
+
+static int ixp2000_bit_getsda(void *data)
+{
+ return gpio_line_get(ixp2000_sda_pin(data));
+}
+
+struct ixp2000_i2c_data {
+ struct ixp2000_i2c_pins *gpio_pins;
+ struct i2c_adapter adapter;
+ struct i2c_algo_bit_data algo_data;
+};
+
+static int ixp2000_i2c_remove(struct device *dev)
+{
+ struct platform_device *plat_dev = to_platform_device(dev);
+ struct ixp2000_i2c_data *drv_data = dev_get_drvdata(&plat_dev->dev);
+
+ dev_set_drvdata(&plat_dev->dev, NULL);
+
+ i2c_bit_del_bus(&drv_data->adapter);
+
+ kfree(drv_data);
+
+ return 0;
+}
+
+static int ixp2000_i2c_probe(struct device *dev)
+{
+ int err;
+ struct platform_device *plat_dev = to_platform_device(dev);
+ struct ixp2000_i2c_pins *gpio = plat_dev->dev.platform_data;
+ struct ixp2000_i2c_data *drv_data =
+ kmalloc(sizeof(struct ixp2000_i2c_data), GFP_KERNEL);
+
+ if (!drv_data)
+ return -ENOMEM;
+ memzero(drv_data, sizeof(*drv_data));
+ drv_data->gpio_pins = gpio;
+
+ drv_data->algo_data.data = gpio;
+ drv_data->algo_data.setsda = ixp2000_bit_setsda;
+ drv_data->algo_data.setscl = ixp2000_bit_setscl;
+ drv_data->algo_data.getsda = ixp2000_bit_getsda;
+ drv_data->algo_data.getscl = ixp2000_bit_getscl;
+ drv_data->algo_data.udelay = 6;
+ drv_data->algo_data.mdelay = 6;
+ drv_data->algo_data.timeout = 100;
+
+ drv_data->adapter.id = I2C_HW_B_IXP2000,
+ drv_data->adapter.algo_data = &drv_data->algo_data,
+
+ drv_data->adapter.dev.parent = &plat_dev->dev;
+
+ gpio_line_config(gpio->sda_pin, GPIO_IN);
+ gpio_line_config(gpio->scl_pin, GPIO_IN);
+ gpio_line_set(gpio->scl_pin, 0);
+ gpio_line_set(gpio->sda_pin, 0);
+
+ if ((err = i2c_bit_add_bus(&drv_data->adapter)) != 0) {
+ dev_err(dev, "Could not install, error %d\n", err);
+ kfree(drv_data);
+ return err;
+ }
+
+ dev_set_drvdata(&plat_dev->dev, drv_data);
+
+ return 0;
+}
+
+static struct device_driver ixp2000_i2c_driver = {
+ .name = "IXP2000-I2C",
+ .bus = &platform_bus_type,
+ .probe = ixp2000_i2c_probe,
+ .remove = ixp2000_i2c_remove,
+};
+
+static int __init ixp2000_i2c_init(void)
+{
+ return driver_register(&ixp2000_i2c_driver);
+}
+
+static void __exit ixp2000_i2c_exit(void)
+{
+ driver_unregister(&ixp2000_i2c_driver);
+}
+
+module_init(ixp2000_i2c_init);
+module_exit(ixp2000_i2c_exit);
+
+MODULE_AUTHOR ("Deepak Saxena <dsaxena@plexity.net>");
+MODULE_DESCRIPTION("IXP2000 GPIO-based I2C bus driver");
+MODULE_LICENSE("GPL");
+
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
+
+ * This is a combined i2c adapter and algorithm driver for the
+ * MPC107/Tsi107 PowerPC northbridge and processors that include
+ * the same I2C unit (8240, 8245, 85xx).
+ *
+ * Release 0.6
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <asm/ocp.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+
+#define MPC_I2C_ADDR 0x00
+#define MPC_I2C_FDR 0x04
+#define MPC_I2C_CR 0x08
+#define MPC_I2C_SR 0x0c
+#define MPC_I2C_DR 0x10
+#define MPC_I2C_DFSRR 0x14
+#define MPC_I2C_REGION 0x20
+
+#define CCR_MEN 0x80
+#define CCR_MIEN 0x40
+#define CCR_MSTA 0x20
+#define CCR_MTX 0x10
+#define CCR_TXAK 0x08
+#define CCR_RSTA 0x04
+
+#define CSR_MCF 0x80
+#define CSR_MAAS 0x40
+#define CSR_MBB 0x20
+#define CSR_MAL 0x10
+#define CSR_SRW 0x04
+#define CSR_MIF 0x02
+#define CSR_RXAK 0x01
+
+struct mpc_i2c {
+ char *base;
+ struct ocp_def *ocpdef;
+ u32 interrupt;
+ wait_queue_head_t queue;
+ struct i2c_adapter adap;
+};
+
+static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
+{
+ writeb(x, i2c->base + MPC_I2C_CR);
+}
+
+static irqreturn_t mpc_i2c_isr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct mpc_i2c *i2c = dev_id;
+ if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
+ /* Read again to allow register to stabilise */
+ i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
+ writeb(0, i2c->base + MPC_I2C_SR);
+ wake_up_interruptible(&i2c->queue);
+ }
+ return IRQ_HANDLED;
+}
+
+static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ unsigned long orig_jiffies = jiffies;
+ u32 x;
+ int result = 0;
+
+ if (i2c->ocpdef->irq == OCP_IRQ_NA) {
+ while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
+ schedule();
+ if (time_after(jiffies, orig_jiffies + timeout)) {
+ pr_debug("I2C: timeout\n");
+ result = -EIO;
+ break;
+ }
+ }
+ x = readb(i2c->base + MPC_I2C_SR);
+ writeb(0, i2c->base + MPC_I2C_SR);
+ } else {
+ add_wait_queue(&i2c->queue, &wait);
+ while (!(i2c->interrupt & CSR_MIF)) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (signal_pending(current)) {
+ pr_debug("I2C: Interrupted\n");
+ result = -EINTR;
+ break;
+ }
+ if (time_after(jiffies, orig_jiffies + timeout)) {
+ pr_debug("I2C: timeout\n");
+ result = -EIO;
+ break;
+ }
+ schedule_timeout(timeout);
+ }
+ current->state = TASK_RUNNING;
+ remove_wait_queue(&i2c->queue, &wait);
+ x = i2c->interrupt;
+ i2c->interrupt = 0;
+ }
+
+ if (result < -0)
+ return result;
+
+ if (!(x & CSR_MCF)) {
+ pr_debug("I2C: unfinished\n");
+ return -EIO;
+ }
+
+ if (x & CSR_MAL) {
+ pr_debug("I2C: MAL\n");
+ return -EIO;
+ }
+
+ if (writing && (x & CSR_RXAK)) {
+ pr_debug("I2C: No RXAK\n");
+ /* generate stop */
+ writeccr(i2c, CCR_MEN);
+ return -EIO;
+ }
+ return 0;
+}
+
+static void mpc_i2c_setclock(struct mpc_i2c *i2c)
+{
+ struct ocp_fs_i2c_data *i2c_data = i2c->ocpdef->additions;
+ /* Set clock and filters */
+ if (i2c_data && (i2c_data->flags & FS_I2C_SEPARATE_DFSRR)) {
+ writeb(0x31, i2c->base + MPC_I2C_FDR);
+ writeb(0x10, i2c->base + MPC_I2C_DFSRR);
+ } else if (i2c_data && (i2c_data->flags & FS_I2C_CLOCK_5200))
+ writeb(0x3f, i2c->base + MPC_I2C_FDR);
+ else
+ writel(0x1031, i2c->base + MPC_I2C_FDR);
+}
+
+static void mpc_i2c_start(struct mpc_i2c *i2c)
+{
+ /* Clear arbitration */
+ writeb(0, i2c->base + MPC_I2C_SR);
+ /* Start with MEN */
+ writeccr(i2c, CCR_MEN);
+}
+
+static void mpc_i2c_stop(struct mpc_i2c *i2c)
+{
+ writeccr(i2c, CCR_MEN);
+}
+
+static int mpc_write(struct mpc_i2c *i2c, int target,
+ const u8 * data, int length, int restart)
+{
+ int i;
+ unsigned timeout = HZ;
+ u32 flags = restart ? CCR_RSTA : 0;
+
+ /* Start with MEN */
+ if (!restart)
+ writeccr(i2c, CCR_MEN);
+ /* Start as master */
+ writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
+ /* Write target byte */
+ writeb((target << 1), i2c->base + MPC_I2C_DR);
+
+ if (i2c_wait(i2c, timeout, 1) < 0)
+ return -1;
+
+ for (i = 0; i < length; i++) {
+ /* Write data byte */
+ writeb(data[i], i2c->base + MPC_I2C_DR);
+
+ if (i2c_wait(i2c, timeout, 1) < 0)
+ return -1;
+ }
+
+ return 0;
+}
+
+static int mpc_read(struct mpc_i2c *i2c, int target,
+ u8 * data, int length, int restart)
+{
+ unsigned timeout = HZ;
+ int i;
+ u32 flags = restart ? CCR_RSTA : 0;
+
+ /* Start with MEN */
+ if (!restart)
+ writeccr(i2c, CCR_MEN);
+ /* Switch to read - restart */
+ writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
+ /* Write target address byte - this time with the read flag set */
+ writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
+
+ if (i2c_wait(i2c, timeout, 1) < 0)
+ return -1;
+
+ if (length) {
+ if (length == 1)
+ writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
+ else
+ writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
+ /* Dummy read */
+ readb(i2c->base + MPC_I2C_DR);
+ }
+
+ for (i = 0; i < length; i++) {
+ if (i2c_wait(i2c, timeout, 0) < 0)
+ return -1;
+
+ /* Generate txack on next to last byte */
+ if (i == length - 2)
+ writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
+ /* Generate stop on last byte */
+ if (i == length - 1)
+ writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
+ data[i] = readb(i2c->base + MPC_I2C_DR);
+ }
+
+ return length;
+}
+
+static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+ struct i2c_msg *pmsg;
+ int i;
+ int ret = 0;
+ unsigned long orig_jiffies = jiffies;
+ struct mpc_i2c *i2c = i2c_get_adapdata(adap);
+
+ mpc_i2c_start(i2c);
+
+ /* Allow bus up to 1s to become not busy */
+ while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
+ if (signal_pending(current)) {
+ pr_debug("I2C: Interrupted\n");
+ return -EINTR;
+ }
+ if (time_after(jiffies, orig_jiffies + HZ)) {
+ pr_debug("I2C: timeout\n");
+ return -EIO;
+ }
+ schedule();
+ }
+
+ for (i = 0; ret >= 0 && i < num; i++) {
+ pmsg = &msgs[i];
+ pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
+ pmsg->flags & I2C_M_RD ? "read" : "write",
+ pmsg->len, pmsg->addr, i + 1, num);
+ if (pmsg->flags & I2C_M_RD)
+ ret =
+ mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
+ else
+ ret =
+ mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
+ }
+ mpc_i2c_stop(i2c);
+ return (ret < 0) ? ret : num;
+}
+
+static u32 mpc_functionality(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static struct i2c_algorithm mpc_algo = {
+ .name = "MPC algorithm",
+ .id = I2C_ALGO_MPC107,
+ .master_xfer = mpc_xfer,
+ .functionality = mpc_functionality,
+};
+
+static struct i2c_adapter mpc_ops = {
+ .owner = THIS_MODULE,
+ .name = "MPC adapter",
+ .id = I2C_ALGO_MPC107 | I2C_HW_MPC107,
+ .algo = &mpc_algo,
+ .class = I2C_CLASS_HWMON,
+ .timeout = 1,
+ .retries = 1
+};
+
+static int __devinit mpc_i2c_probe(struct ocp_device *ocp)
+{
+ int result = 0;
+ struct mpc_i2c *i2c;
+
+ if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
+ return -ENOMEM;
+ }
+ i2c->ocpdef = ocp->def;
+ init_waitqueue_head(&i2c->queue);
+
+ if (!request_mem_region(ocp->def->paddr, MPC_I2C_REGION, "i2c-mpc")) {
+ printk(KERN_ERR "i2c-mpc - resource unavailable\n");
+ return -ENODEV;
+ }
+
+ i2c->base = ioremap(ocp->def->paddr, MPC_I2C_REGION);
+
+ if (!i2c->base) {
+ printk(KERN_ERR "i2c-mpc - failed to map controller\n");
+ result = -ENOMEM;
+ goto fail_map;
+ }
+
+ if (ocp->def->irq != OCP_IRQ_NA)
+ if ((result = request_irq(ocp->def->irq, mpc_i2c_isr,
+ 0, "i2c-mpc", i2c)) < 0) {
+ printk(KERN_ERR
+ "i2c-mpc - failed to attach interrupt\n");
+ goto fail_irq;
+ }
+
+ i2c->adap = mpc_ops;
+ i2c_set_adapdata(&i2c->adap, i2c);
+ if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
+ printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
+ goto fail_add;
+ }
+
+ mpc_i2c_setclock(i2c);
+ ocp_set_drvdata(ocp, i2c);
+ return result;
+
+ fail_add:
+ if (ocp->def->irq != OCP_IRQ_NA)
+ free_irq(ocp->def->irq, 0);
+ fail_irq:
+ iounmap(i2c->base);
+ fail_map:
+ release_mem_region(ocp->def->paddr, MPC_I2C_REGION);
+ kfree(i2c);
+ return result;
+}
+static void __devexit mpc_i2c_remove(struct ocp_device *ocp)
+{
+ struct mpc_i2c *i2c = ocp_get_drvdata(ocp);
+ ocp_set_drvdata(ocp, NULL);
+ i2c_del_adapter(&i2c->adap);
+
+ if (ocp->def->irq != OCP_IRQ_NA)
+ free_irq(i2c->ocpdef->irq, i2c);
+ iounmap(i2c->base);
+ release_mem_region(i2c->ocpdef->paddr, MPC_I2C_REGION);
+ kfree(i2c);
+}
+
+static struct ocp_device_id mpc_iic_ids[] __devinitdata = {
+ {.vendor = OCP_VENDOR_FREESCALE,.function = OCP_FUNC_IIC},
+ {.vendor = OCP_VENDOR_INVALID}
+};
+
+MODULE_DEVICE_TABLE(ocp, mpc_iic_ids);
+
+static struct ocp_driver mpc_iic_driver = {
+ .name = "iic",
+ .id_table = mpc_iic_ids,
+ .probe = mpc_i2c_probe,
+ .remove = __devexit_p(mpc_i2c_remove)
+};
+
+static int __init iic_init(void)
+{
+ return ocp_register_driver(&mpc_iic_driver);
+}
+
+static void __exit iic_exit(void)
+{
+ ocp_unregister_driver(&mpc_iic_driver);
+}
+
+module_init(iic_init);
+module_exit(iic_exit);
+
+MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
+MODULE_DESCRIPTION
+ ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * i2c-pca-isa.c driver for PCA9564 on ISA boards
+ * Copyright (C) 2004 Arcom Control Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/wait.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-pca.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "../algos/i2c-algo-pca.h"
+
+#define IO_SIZE 4
+
+#undef DEBUG_IO
+//#define DEBUG_IO
+
+static unsigned long base = 0x330;
+static int irq = 10;
+
+/* Data sheet recommends 59kHz for 100kHz operation due to variation
+ * in the actual clock rate */
+static int clock = I2C_PCA_CON_59kHz;
+
+static int own = 0x55;
+
+static wait_queue_head_t pca_wait;
+
+static int pca_isa_getown(struct i2c_algo_pca_data *adap)
+{
+ return (own);
+}
+
+static int pca_isa_getclock(struct i2c_algo_pca_data *adap)
+{
+ return (clock);
+}
+
+static void
+pca_isa_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
+{
+#ifdef DEBUG_IO
+ static char *names[] = { "T/O", "DAT", "ADR", "CON" };
+ printk("*** write %s at %#lx <= %#04x\n", names[reg], base+reg, val);
+#endif
+ outb(val, base+reg);
+}
+
+static int
+pca_isa_readbyte(struct i2c_algo_pca_data *adap, int reg)
+{
+ int res = inb(base+reg);
+#ifdef DEBUG_IO
+ {
+ static char *names[] = { "STA", "DAT", "ADR", "CON" };
+ printk("*** read %s => %#04x\n", names[reg], res);
+ }
+#endif
+ return res;
+}
+
+static int pca_isa_waitforinterrupt(struct i2c_algo_pca_data *adap)
+{
+ int ret = 0;
+
+ if (irq > -1) {
+ ret = wait_event_interruptible(pca_wait,
+ pca_isa_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
+ } else {
+ while ((pca_isa_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
+ udelay(100);
+ }
+ return ret;
+}
+
+static irqreturn_t pca_handler(int this_irq, void *dev_id, struct pt_regs *regs) {
+ wake_up_interruptible(&pca_wait);
+ return IRQ_HANDLED;
+}
+
+static struct i2c_algo_pca_data pca_isa_data = {
+ .get_own = pca_isa_getown,
+ .get_clock = pca_isa_getclock,
+ .write_byte = pca_isa_writebyte,
+ .read_byte = pca_isa_readbyte,
+ .wait_for_interrupt = pca_isa_waitforinterrupt,
+};
+
+static struct i2c_adapter pca_isa_ops = {
+ .owner = THIS_MODULE,
+ .id = I2C_HW_A_ISA,
+ .algo_data = &pca_isa_data,
+ .name = "PCA9564 ISA Adapter",
+};
+
+static int __init pca_isa_init(void)
+{
+
+ init_waitqueue_head(&pca_wait);
+
+ printk(KERN_INFO "i2c-pca-isa: i/o base %#08lx. irq %d\n", base, irq);
+
+ if (!request_region(base, IO_SIZE, "i2c-pca-isa")) {
+ printk(KERN_ERR "i2c-pca-isa: I/O address %#08lx is in use.\n", base);
+ goto out;
+ }
+
+ if (irq > -1) {
+ if (request_irq(irq, pca_handler, 0, "i2c-pca-isa", &pca_isa_ops) < 0) {
+ printk(KERN_ERR "i2c-pca-isa: Request irq%d failed\n", irq);
+ goto out_region;
+ }
+ }
+
+ if (i2c_pca_add_bus(&pca_isa_ops) < 0) {
+ printk(KERN_ERR "i2c-pca-isa: Failed to add i2c bus\n");
+ goto out_irq;
+ }
+
+ return 0;
+
+ out_irq:
+ if (irq > -1)
+ free_irq(irq, &pca_isa_ops);
+ out_region:
+ release_region(base, IO_SIZE);
+ out:
+ return -ENODEV;
+}
+
+static void pca_isa_exit(void)
+{
+ i2c_pca_del_bus(&pca_isa_ops);
+
+ if (irq > 0) {
+ disable_irq(irq);
+ free_irq(irq, &pca_isa_ops);
+ }
+ release_region(base, IO_SIZE);
+}
+
+MODULE_AUTHOR("Ian Campbell <icampbell@arcom.com>");
+MODULE_DESCRIPTION("ISA base PCA9564 driver");
+MODULE_LICENSE("GPL");
+
+module_param(base, ulong, 0);
+MODULE_PARM_DESC(base, "I/O base address");
+
+module_param(irq, int, 0);
+MODULE_PARM_DESC(irq, "IRQ");
+module_param(clock, int, 0);
+MODULE_PARM_DESC(clock, "Clock rate as described in table 1 of PCA9564 datasheet");
+
+module_param(own, int, 0); /* the driver can't do slave mode, so there's no real point in this */
+
+module_init(pca_isa_init);
+module_exit(pca_isa_exit);
--- /dev/null
+/*
+ * isp1301_omap - ISP 1301 USB transceiver, talking to OMAP OTG controller
+ *
+ * Copyright (C) 2004 Texas Instruments
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#undef DEBUG
+#undef VERBOSE
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/usb_ch9.h>
+#include <linux/usb_gadget.h>
+#include <linux/usb.h>
+#include <linux/usb_otg.h>
+#include <linux/i2c.h>
+#include <linux/workqueue.h>
+
+#include <asm/irq.h>
+#include <asm/arch/usb.h>
+
+
+#ifndef DEBUG
+#undef VERBOSE
+#endif
+
+
+#define DRIVER_VERSION "24 August 2004"
+#define DRIVER_NAME (isp1301_driver.name)
+
+MODULE_DESCRIPTION("ISP1301 USB OTG Transceiver Driver");
+MODULE_LICENSE("GPL");
+
+struct isp1301 {
+ struct otg_transceiver otg;
+ struct i2c_client client;
+ void (*i2c_release)(struct device *dev);
+
+ int irq;
+
+ u32 last_otg_ctrl;
+ unsigned working:1;
+
+ struct timer_list timer;
+
+ /* use keventd context to change the state for us */
+ struct work_struct work;
+
+ unsigned long todo;
+# define WORK_UPDATE_ISP 0 /* update ISP from OTG */
+# define WORK_UPDATE_OTG 1 /* update OTG from ISP */
+# define WORK_HOST_RESUME 4 /* resume host */
+# define WORK_TIMER 6 /* timer fired */
+# define WORK_STOP 7 /* don't resubmit */
+};
+
+
+/* bits in OTG_CTRL_REG */
+
+#define OTG_XCEIV_OUTPUTS \
+ (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
+#define OTG_XCEIV_INPUTS \
+ (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
+#define OTG_CTRL_BITS \
+ (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|OTG_B_HNPEN|OTG_BUSDROP)
+ /* and OTG_PULLUP is sometimes written */
+
+#define OTG_CTRL_MASK (OTG_DRIVER_SEL| \
+ OTG_XCEIV_OUTPUTS|OTG_XCEIV_INPUTS| \
+ OTG_CTRL_BITS)
+
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_MACH_OMAP_H2
+
+/* board-specific PM hooks */
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/mach-types.h>
+
+
+#if defined(CONFIG_TPS65010) || defined(CONFIG_TPS65010_MODULE)
+
+#include <asm/arch/tps65010.h>
+
+#else
+
+static inline int tps65010_set_vbus_draw(unsigned mA)
+{
+ pr_debug("tps65010: draw %d mA (STUB)\n", mA);
+ return 0;
+}
+
+#endif
+
+static void enable_vbus_draw(struct isp1301 *isp, unsigned mA)
+{
+ int status = tps65010_set_vbus_draw(mA);
+ if (status < 0)
+ pr_debug(" VBUS %d mA error %d\n", mA, status);
+}
+
+static void enable_vbus_source(struct isp1301 *isp)
+{
+ /* this board won't supply more than 8mA vbus power.
+ * some boards can switch a 100ma "unit load" (or more).
+ */
+}
+
+
+/* products will deliver OTG messages with LEDs, GUI, etc */
+static inline void notresponding(struct isp1301 *isp)
+{
+ printk(KERN_NOTICE "OTG device not responding.\n");
+}
+
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/* only two addresses possible */
+#define ISP_BASE 0x2c
+static unsigned short normal_i2c[] = {
+ ISP_BASE, ISP_BASE + 1,
+ I2C_CLIENT_END };
+static unsigned short normal_i2c_range[] = { I2C_CLIENT_END };
+
+I2C_CLIENT_INSMOD;
+
+static struct i2c_driver isp1301_driver;
+
+/* smbus apis are used for portability */
+
+static inline u8
+isp1301_get_u8(struct isp1301 *isp, u8 reg)
+{
+ return i2c_smbus_read_byte_data(&isp->client, reg + 0);
+}
+
+static inline int
+isp1301_get_u16(struct isp1301 *isp, u8 reg)
+{
+ return i2c_smbus_read_word_data(&isp->client, reg);
+}
+
+static inline int
+isp1301_set_bits(struct isp1301 *isp, u8 reg, u8 bits)
+{
+ return i2c_smbus_write_byte_data(&isp->client, reg + 0, bits);
+}
+
+static inline int
+isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits)
+{
+ return i2c_smbus_write_byte_data(&isp->client, reg + 1, bits);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* identification */
+#define ISP1301_VENDOR_ID 0x00 /* u16 read */
+#define ISP1301_PRODUCT_ID 0x02 /* u16 read */
+#define ISP1301_BCD_DEVICE 0x14 /* u16 read */
+
+#define I2C_VENDOR_ID_PHILIPS 0x04cc
+#define I2C_PRODUCT_ID_PHILIPS_1301 0x1301
+
+/* operational registers */
+#define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */
+# define MC1_SPEED_REG (1 << 0)
+# define MC1_SUSPEND_REG (1 << 1)
+# define MC1_DAT_SE0 (1 << 2)
+# define MC1_TRANSPARENT (1 << 3)
+# define MC1_BDIS_ACON_EN (1 << 4)
+# define MC1_OE_INT_EN (1 << 5)
+# define MC1_UART_EN (1 << 6)
+# define MC1_MASK 0x7f
+#define ISP1301_MODE_CONTROL_2 0x12 /* u8 read, set, +1 clear */
+# define MC2_GLOBAL_PWR_DN (1 << 0)
+# define MC2_SPD_SUSP_CTRL (1 << 1)
+# define MC2_BI_DI (1 << 2)
+# define MC2_TRANSP_BDIR0 (1 << 3)
+# define MC2_TRANSP_BDIR1 (1 << 4)
+# define MC2_AUDIO_EN (1 << 5)
+# define MC2_PSW_EN (1 << 6)
+# define MC2_EN2V7 (1 << 7)
+#define ISP1301_OTG_CONTROL_1 0x06 /* u8 read, set, +1 clear */
+# define OTG1_DP_PULLUP (1 << 0)
+# define OTG1_DM_PULLUP (1 << 1)
+# define OTG1_DP_PULLDOWN (1 << 2)
+# define OTG1_DM_PULLDOWN (1 << 3)
+# define OTG1_ID_PULLDOWN (1 << 4)
+# define OTG1_VBUS_DRV (1 << 5)
+# define OTG1_VBUS_DISCHRG (1 << 6)
+# define OTG1_VBUS_CHRG (1 << 7)
+#define ISP1301_OTG_STATUS 0x10 /* u8 readonly */
+# define OTG_B_SESS_END (1 << 6)
+# define OTG_B_SESS_VLD (1 << 7)
+
+#define ISP1301_INTERRUPT_SOURCE 0x08 /* u8 read */
+#define ISP1301_INTERRUPT_LATCH 0x0A /* u8 read, set, +1 clear */
+
+#define ISP1301_INTERRUPT_FALLING 0x0C /* u8 read, set, +1 clear */
+#define ISP1301_INTERRUPT_RISING 0x0E /* u8 read, set, +1 clear */
+
+/* same bitfields in all interrupt registers */
+# define INTR_VBUS_VLD (1 << 0)
+# define INTR_SESS_VLD (1 << 1)
+# define INTR_DP_HI (1 << 2)
+# define INTR_ID_GND (1 << 3)
+# define INTR_DM_HI (1 << 4)
+# define INTR_ID_FLOAT (1 << 5)
+# define INTR_BDIS_ACON (1 << 6)
+# define INTR_CR_INT (1 << 7)
+
+/*-------------------------------------------------------------------------*/
+
+static const char *state_string(enum usb_otg_state state)
+{
+ switch (state) {
+ case OTG_STATE_A_IDLE: return "a_idle";
+ case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
+ case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
+ case OTG_STATE_A_HOST: return "a_host";
+ case OTG_STATE_A_SUSPEND: return "a_suspend";
+ case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
+ case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
+ case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
+ case OTG_STATE_B_IDLE: return "b_idle";
+ case OTG_STATE_B_SRP_INIT: return "b_srp_init";
+ case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
+ case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
+ case OTG_STATE_B_HOST: return "b_host";
+ default: return "UNDEFINED";
+ }
+}
+
+static inline const char *state_name(struct isp1301 *isp)
+{
+ return state_string(isp->otg.state);
+}
+
+#ifdef VERBOSE
+#define dev_vdbg dev_dbg
+#else
+#define dev_vdbg(dev, fmt, arg...) do{}while(0)
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/* NOTE: some of this ISP1301 setup is specific to H2 boards;
+ * not everything is guarded by board-specific checks, or even using
+ * omap_usb_config data to deduce MC1_DAT_SE0 and MC2_BI_DI.
+ *
+ * ALSO: this currently doesn't use ISP1301 low-power modes
+ * while OTG is running.
+ */
+
+static void power_down(struct isp1301 *isp)
+{
+ isp->otg.state = OTG_STATE_UNDEFINED;
+
+ // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG);
+
+ isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN);
+ isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
+}
+
+static void power_up(struct isp1301 *isp)
+{
+ // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
+ isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG);
+
+ /* do this only when cpu is driving transceiver,
+ * so host won't see a low speed device...
+ */
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
+}
+
+#define NO_HOST_SUSPEND
+
+static int host_suspend(struct isp1301 *isp)
+{
+#ifdef NO_HOST_SUSPEND
+ return 0;
+#else
+ struct device *dev;
+
+ if (!isp->otg.host)
+ return -ENODEV;
+
+ /* Currently ASSUMES only the OTG port matters;
+ * other ports could be active...
+ */
+ dev = isp->otg.host->controller;
+ return dev->driver->suspend(dev, 3, 0);
+#endif
+}
+
+static int host_resume(struct isp1301 *isp)
+{
+#ifdef NO_HOST_SUSPEND
+ return 0;
+#else
+ struct device *dev;
+
+ if (!isp->otg.host)
+ return -ENODEV;
+
+ dev = isp->otg.host->controller;
+ return dev->driver->resume(dev, 0);
+#endif
+}
+
+static int gadget_suspend(struct isp1301 *isp)
+{
+ isp->otg.gadget->b_hnp_enable = 0;
+ isp->otg.gadget->a_hnp_support = 0;
+ isp->otg.gadget->a_alt_hnp_support = 0;
+ return usb_gadget_vbus_disconnect(isp->otg.gadget);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define TIMER_MINUTES 10
+#define TIMER_JIFFIES (TIMER_MINUTES * 60 * HZ)
+
+/* Almost all our I2C messaging comes from a work queue's task context.
+ * NOTE: guaranteeing certain response times might mean we shouldn't
+ * share keventd's work queue; a realtime task might be safest.
+ */
+void
+isp1301_defer_work(struct isp1301 *isp, int work)
+{
+ int status;
+
+ if (isp && !test_and_set_bit(work, &isp->todo)) {
+ (void) get_device(&isp->client.dev);
+ status = schedule_work(&isp->work);
+ if (!status && !isp->working)
+ dev_vdbg(&isp->client.dev,
+ "work item %d may be lost\n", work);
+ }
+}
+
+/* called from irq handlers */
+static void a_idle(struct isp1301 *isp, const char *tag)
+{
+ if (isp->otg.state == OTG_STATE_A_IDLE)
+ return;
+
+ isp->otg.default_a = 1;
+ if (isp->otg.host) {
+ isp->otg.host->is_b_host = 0;
+ host_suspend(isp);
+ }
+ if (isp->otg.gadget) {
+ isp->otg.gadget->is_a_peripheral = 1;
+ gadget_suspend(isp);
+ }
+ isp->otg.state = OTG_STATE_A_IDLE;
+ isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+ pr_debug(" --> %s/%s\n", state_name(isp), tag);
+}
+
+/* called from irq handlers */
+static void b_idle(struct isp1301 *isp, const char *tag)
+{
+ if (isp->otg.state == OTG_STATE_B_IDLE)
+ return;
+
+ isp->otg.default_a = 0;
+ if (isp->otg.host) {
+ isp->otg.host->is_b_host = 1;
+ host_suspend(isp);
+ }
+ if (isp->otg.gadget) {
+ isp->otg.gadget->is_a_peripheral = 0;
+ gadget_suspend(isp);
+ }
+ isp->otg.state = OTG_STATE_B_IDLE;
+ isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+ pr_debug(" --> %s/%s\n", state_name(isp), tag);
+}
+
+static void
+dump_regs(struct isp1301 *isp, const char *label)
+{
+#ifdef DEBUG
+ u8 ctrl = isp1301_get_u8(isp, ISP1301_OTG_CONTROL_1);
+ u8 status = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
+ u8 src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
+
+ pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n",
+ OTG_CTRL_REG, label, state_name(isp),
+ ctrl, status, src);
+ /* mode control and irq enables don't change much */
+#endif
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USB_OTG
+
+/*
+ * The OMAP OTG controller handles most of the OTG state transitions.
+ *
+ * We translate isp1301 outputs (mostly voltage comparator status) into
+ * OTG inputs; OTG outputs (mostly pullup/pulldown controls) and HNP state
+ * flags into isp1301 inputs ... and infer state transitions.
+ */
+
+#ifdef VERBOSE
+
+static void check_state(struct isp1301 *isp, const char *tag)
+{
+ enum usb_otg_state state = OTG_STATE_UNDEFINED;
+ u8 fsm = OTG_TEST_REG & 0x0ff;
+ unsigned extra = 0;
+
+ switch (fsm) {
+
+ /* default-b */
+ case 0x0:
+ state = OTG_STATE_B_IDLE;
+ break;
+ case 0x3:
+ case 0x7:
+ extra = 1;
+ case 0x1:
+ state = OTG_STATE_B_PERIPHERAL;
+ break;
+ case 0x11:
+ state = OTG_STATE_B_SRP_INIT;
+ break;
+
+ /* extra dual-role default-b states */
+ case 0x12:
+ case 0x13:
+ case 0x16:
+ extra = 1;
+ case 0x17:
+ state = OTG_STATE_B_WAIT_ACON;
+ break;
+ case 0x34:
+ state = OTG_STATE_B_HOST;
+ break;
+
+ /* default-a */
+ case 0x36:
+ state = OTG_STATE_A_IDLE;
+ break;
+ case 0x3c:
+ state = OTG_STATE_A_WAIT_VFALL;
+ break;
+ case 0x7d:
+ state = OTG_STATE_A_VBUS_ERR;
+ break;
+ case 0x9e:
+ case 0x9f:
+ extra = 1;
+ case 0x89:
+ state = OTG_STATE_A_PERIPHERAL;
+ break;
+ case 0xb7:
+ state = OTG_STATE_A_WAIT_VRISE;
+ break;
+ case 0xb8:
+ state = OTG_STATE_A_WAIT_BCON;
+ break;
+ case 0xb9:
+ state = OTG_STATE_A_HOST;
+ break;
+ case 0xba:
+ state = OTG_STATE_A_SUSPEND;
+ break;
+ default:
+ break;
+ }
+ if (isp->otg.state == state && !extra)
+ return;
+ pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
+ state_string(state), fsm, state_name(isp), OTG_CTRL_REG);
+}
+
+#else
+
+static inline void check_state(struct isp1301 *isp, const char *tag) { }
+
+#endif
+
+/* outputs from ISP1301_INTERRUPT_SOURCE */
+static void update_otg1(struct isp1301 *isp, u8 int_src)
+{
+ u32 otg_ctrl;
+
+ otg_ctrl = OTG_CTRL_REG
+ & OTG_CTRL_MASK
+ & ~OTG_XCEIV_INPUTS
+ & ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
+ if (int_src & INTR_SESS_VLD)
+ otg_ctrl |= OTG_ASESSVLD;
+ else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) {
+ a_idle(isp, "vfall");
+ otg_ctrl &= ~OTG_CTRL_BITS;
+ }
+ if (int_src & INTR_VBUS_VLD)
+ otg_ctrl |= OTG_VBUSVLD;
+ if (int_src & INTR_ID_GND) { /* default-A */
+ if (isp->otg.state == OTG_STATE_B_IDLE
+ || isp->otg.state == OTG_STATE_UNDEFINED) {
+ a_idle(isp, "init");
+ return;
+ }
+ } else { /* default-B */
+ otg_ctrl |= OTG_ID;
+ if (isp->otg.state == OTG_STATE_A_IDLE
+ || isp->otg.state == OTG_STATE_UNDEFINED) {
+ b_idle(isp, "init");
+ return;
+ }
+ }
+ OTG_CTRL_REG = otg_ctrl;
+}
+
+/* outputs from ISP1301_OTG_STATUS */
+static void update_otg2(struct isp1301 *isp, u8 otg_status)
+{
+ u32 otg_ctrl;
+
+ otg_ctrl = OTG_CTRL_REG
+ & OTG_CTRL_MASK
+ & ~OTG_XCEIV_INPUTS
+ & ~(OTG_BSESSVLD|OTG_BSESSEND);
+ if (otg_status & OTG_B_SESS_VLD)
+ otg_ctrl |= OTG_BSESSVLD;
+ else if (otg_status & OTG_B_SESS_END)
+ otg_ctrl |= OTG_BSESSEND;
+ OTG_CTRL_REG = otg_ctrl;
+}
+
+/* inputs going to ISP1301 */
+static void otg_update_isp(struct isp1301 *isp)
+{
+ u32 otg_ctrl, otg_change;
+ u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP;
+
+ otg_ctrl = OTG_CTRL_REG;
+ otg_change = otg_ctrl ^ isp->last_otg_ctrl;
+ isp->last_otg_ctrl = otg_ctrl;
+ otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS;
+
+ switch (isp->otg.state) {
+ case OTG_STATE_B_IDLE:
+ case OTG_STATE_B_PERIPHERAL:
+ case OTG_STATE_B_SRP_INIT:
+ if (!(otg_ctrl & OTG_PULLUP)) {
+ // if (otg_ctrl & OTG_B_HNPEN) {
+ if (isp->otg.gadget->b_hnp_enable) {
+ isp->otg.state = OTG_STATE_B_WAIT_ACON;
+ pr_debug(" --> b_wait_acon\n");
+ }
+ goto pulldown;
+ }
+pullup:
+ set |= OTG1_DP_PULLUP;
+ clr |= OTG1_DP_PULLDOWN;
+ break;
+ case OTG_STATE_A_SUSPEND:
+ case OTG_STATE_A_PERIPHERAL:
+ if (otg_ctrl & OTG_PULLUP)
+ goto pullup;
+ /* FALLTHROUGH */
+ // case OTG_STATE_B_WAIT_ACON:
+ default:
+pulldown:
+ set |= OTG1_DP_PULLDOWN;
+ clr |= OTG1_DP_PULLUP;
+ break;
+ }
+
+# define toggle(OTG,ISP) do { \
+ if (otg_ctrl & OTG) set |= ISP; \
+ else clr |= ISP; \
+ } while (0)
+
+ if (!(isp->otg.host))
+ otg_ctrl &= ~OTG_DRV_VBUS;
+
+ switch (isp->otg.state) {
+ case OTG_STATE_A_SUSPEND:
+ if (otg_ctrl & OTG_DRV_VBUS) {
+ set |= OTG1_VBUS_DRV;
+ break;
+ }
+ /* HNP failed for some reason (A_AIDL_BDIS timeout) */
+ notresponding(isp);
+
+ /* FALLTHROUGH */
+ case OTG_STATE_A_VBUS_ERR:
+ isp->otg.state = OTG_STATE_A_WAIT_VFALL;
+ pr_debug(" --> a_wait_vfall\n");
+ /* FALLTHROUGH */
+ case OTG_STATE_A_WAIT_VFALL:
+ /* FIXME usbcore thinks port power is still on ... */
+ clr |= OTG1_VBUS_DRV;
+ break;
+ case OTG_STATE_A_IDLE:
+ if (otg_ctrl & OTG_DRV_VBUS) {
+ isp->otg.state = OTG_STATE_A_WAIT_VRISE;
+ pr_debug(" --> a_wait_vrise\n");
+ }
+ /* FALLTHROUGH */
+ default:
+ toggle(OTG_DRV_VBUS, OTG1_VBUS_DRV);
+ }
+
+ toggle(OTG_PU_VBUS, OTG1_VBUS_CHRG);
+ toggle(OTG_PD_VBUS, OTG1_VBUS_DISCHRG);
+
+# undef toggle
+
+ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, set);
+ isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, clr);
+
+ /* HNP switch to host or peripheral; and SRP */
+ if (otg_change & OTG_PULLUP) {
+ switch (isp->otg.state) {
+ case OTG_STATE_B_IDLE:
+ if (clr & OTG1_DP_PULLUP)
+ break;
+ isp->otg.state = OTG_STATE_B_PERIPHERAL;
+ pr_debug(" --> b_peripheral\n");
+ break;
+ case OTG_STATE_A_SUSPEND:
+ if (clr & OTG1_DP_PULLUP)
+ break;
+ isp->otg.state = OTG_STATE_A_PERIPHERAL;
+ pr_debug(" --> a_peripheral\n");
+ break;
+ default:
+ break;
+ }
+ OTG_CTRL_REG |= OTG_PULLUP;
+ }
+
+ check_state(isp, __FUNCTION__);
+ dump_regs(isp, "otg->isp1301");
+}
+
+static irqreturn_t omap_otg_irq(int irq, void *_isp, struct pt_regs *regs)
+{
+ u16 otg_irq = OTG_IRQ_SRC_REG;
+ u32 otg_ctrl;
+ int ret = IRQ_NONE;
+ struct isp1301 *isp = _isp;
+
+ /* update ISP1301 transciever from OTG controller */
+ if (otg_irq & OPRT_CHG) {
+ OTG_IRQ_SRC_REG = OPRT_CHG;
+ isp1301_defer_work(isp, WORK_UPDATE_ISP);
+ ret = IRQ_HANDLED;
+
+ /* SRP to become b_peripheral failed */
+ } else if (otg_irq & B_SRP_TMROUT) {
+ pr_debug("otg: B_SRP_TIMEOUT, %06x\n", OTG_CTRL_REG);
+ notresponding(isp);
+
+ /* gadget drivers that care should monitor all kinds of
+ * remote wakeup (SRP, normal) using their own timer
+ * to give "check cable and A-device" messages.
+ */
+ if (isp->otg.state == OTG_STATE_B_SRP_INIT)
+ b_idle(isp, "srp_timeout");
+
+ OTG_IRQ_SRC_REG = B_SRP_TMROUT;
+ ret = IRQ_HANDLED;
+
+ /* HNP to become b_host failed */
+ } else if (otg_irq & B_HNP_FAIL) {
+ pr_debug("otg: %s B_HNP_FAIL, %06x\n",
+ state_name(isp), OTG_CTRL_REG);
+ notresponding(isp);
+
+ otg_ctrl = OTG_CTRL_REG;
+ otg_ctrl |= OTG_BUSDROP;
+ otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
+ OTG_CTRL_REG = otg_ctrl;
+
+ /* subset of b_peripheral()... */
+ isp->otg.state = OTG_STATE_B_PERIPHERAL;
+ pr_debug(" --> b_peripheral\n");
+
+ OTG_IRQ_SRC_REG = B_HNP_FAIL;
+ ret = IRQ_HANDLED;
+
+ /* detect SRP from B-device ... */
+ } else if (otg_irq & A_SRP_DETECT) {
+ pr_debug("otg: %s SRP_DETECT, %06x\n",
+ state_name(isp), OTG_CTRL_REG);
+
+ isp1301_defer_work(isp, WORK_UPDATE_OTG);
+ switch (isp->otg.state) {
+ case OTG_STATE_A_IDLE:
+ if (!isp->otg.host)
+ break;
+ isp1301_defer_work(isp, WORK_HOST_RESUME);
+ otg_ctrl = OTG_CTRL_REG;
+ otg_ctrl |= OTG_A_BUSREQ;
+ otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
+ & ~OTG_XCEIV_INPUTS
+ & OTG_CTRL_MASK;
+ OTG_CTRL_REG = otg_ctrl;
+ break;
+ default:
+ break;
+ }
+
+ OTG_IRQ_SRC_REG = A_SRP_DETECT;
+ ret = IRQ_HANDLED;
+
+ /* timer expired: T(a_wait_bcon) and maybe T(a_wait_vrise)
+ * we don't track them separately
+ */
+ } else if (otg_irq & A_REQ_TMROUT) {
+ otg_ctrl = OTG_CTRL_REG;
+ pr_info("otg: BCON_TMOUT from %s, %06x\n",
+ state_name(isp), otg_ctrl);
+ notresponding(isp);
+
+ otg_ctrl |= OTG_BUSDROP;
+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
+ OTG_CTRL_REG = otg_ctrl;
+ isp->otg.state = OTG_STATE_A_WAIT_VFALL;
+
+ OTG_IRQ_SRC_REG = A_REQ_TMROUT;
+ ret = IRQ_HANDLED;
+
+ /* A-supplied voltage fell too low; overcurrent */
+ } else if (otg_irq & A_VBUS_ERR) {
+ otg_ctrl = OTG_CTRL_REG;
+ printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n",
+ state_name(isp), otg_irq, otg_ctrl);
+
+ otg_ctrl |= OTG_BUSDROP;
+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
+ OTG_CTRL_REG = otg_ctrl;
+ isp->otg.state = OTG_STATE_A_VBUS_ERR;
+
+ OTG_IRQ_SRC_REG = A_VBUS_ERR;
+ ret = IRQ_HANDLED;
+
+ /* switch driver; the transciever code activates it,
+ * ungating the udc clock or resuming OHCI.
+ */
+ } else if (otg_irq & DRIVER_SWITCH) {
+ int kick = 0;
+
+ otg_ctrl = OTG_CTRL_REG;
+ printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n",
+ state_name(isp),
+ (otg_ctrl & OTG_DRIVER_SEL)
+ ? "gadget" : "host",
+ otg_ctrl);
+ isp1301_defer_work(isp, WORK_UPDATE_ISP);
+
+ /* role is peripheral */
+ if (otg_ctrl & OTG_DRIVER_SEL) {
+ switch (isp->otg.state) {
+ case OTG_STATE_A_IDLE:
+ b_idle(isp, __FUNCTION__);
+ break;
+ default:
+ break;
+ }
+ isp1301_defer_work(isp, WORK_UPDATE_ISP);
+
+ /* role is host */
+ } else {
+ if (!(otg_ctrl & OTG_ID)) {
+ otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
+ OTG_CTRL_REG = otg_ctrl | OTG_A_BUSREQ;
+ }
+
+ if (isp->otg.host) {
+ switch (isp->otg.state) {
+ case OTG_STATE_B_WAIT_ACON:
+ isp->otg.state = OTG_STATE_B_HOST;
+ pr_debug(" --> b_host\n");
+ kick = 1;
+ break;
+ case OTG_STATE_A_WAIT_BCON:
+ isp->otg.state = OTG_STATE_A_HOST;
+ pr_debug(" --> a_host\n");
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+ isp->otg.state = OTG_STATE_A_WAIT_BCON;
+ pr_debug(" --> a_wait_bcon\n");
+ break;
+ default:
+ break;
+ }
+ isp1301_defer_work(isp, WORK_HOST_RESUME);
+ }
+ }
+
+ OTG_IRQ_SRC_REG = DRIVER_SWITCH;
+ ret = IRQ_HANDLED;
+
+ if (kick)
+ usb_bus_start_enum(isp->otg.host,
+ isp->otg.host->otg_port);
+ }
+
+ check_state(isp, __FUNCTION__);
+ return ret;
+}
+
+static struct platform_device *otg_dev;
+
+static int otg_init(struct isp1301 *isp)
+{
+ if (!otg_dev)
+ return -ENODEV;
+
+ dump_regs(isp, __FUNCTION__);
+ /* some of these values are board-specific... */
+ OTG_SYSCON_2_REG |= OTG_EN
+ /* for B-device: */
+ | SRP_GPDATA /* 9msec Bdev D+ pulse */
+ | SRP_GPDVBUS /* discharge after VBUS pulse */
+ // | (3 << 24) /* 2msec VBUS pulse */
+ /* for A-device: */
+ | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */
+ | SRP_DPW /* detect 167+ns SRP pulses */
+ | SRP_DATA | SRP_VBUS /* accept both kinds of SRP pulse */
+ ;
+
+ update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
+ update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
+
+ check_state(isp, __FUNCTION__);
+ pr_debug("otg: %s, %s %06x\n",
+ state_name(isp), __FUNCTION__, OTG_CTRL_REG);
+
+ OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG
+ | B_SRP_TMROUT | B_HNP_FAIL
+ | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT;
+ OTG_SYSCON_2_REG |= OTG_EN;
+
+ return 0;
+}
+
+static int otg_probe(struct device *dev)
+{
+ // struct omap_usb_config *config = dev->platform_data;
+
+ otg_dev = to_platform_device(dev);
+ return 0;
+}
+
+static int otg_remove(struct device *dev)
+{
+ otg_dev = 0;
+ return 0;
+}
+
+struct device_driver omap_otg_driver = {
+ .name = "omap_otg",
+ .bus = &platform_bus_type,
+ .probe = otg_probe,
+ .remove = otg_remove,
+};
+
+static int otg_bind(struct isp1301 *isp)
+{
+ int status;
+
+ if (otg_dev)
+ return -EBUSY;
+
+ status = driver_register(&omap_otg_driver);
+ if (status < 0)
+ return status;
+
+ if (otg_dev)
+ status = request_irq(otg_dev->resource[1].start, omap_otg_irq,
+ SA_INTERRUPT, DRIVER_NAME, isp);
+ else
+ status = -ENODEV;
+
+ if (status < 0)
+ driver_unregister(&omap_otg_driver);
+ return status;
+}
+
+static void otg_unbind(struct isp1301 *isp)
+{
+ if (!otg_dev)
+ return;
+ free_irq(otg_dev->resource[1].start, isp);
+}
+
+#else
+
+/* OTG controller isn't clocked */
+
+#endif /* CONFIG_USB_OTG */
+
+/*-------------------------------------------------------------------------*/
+
+static void b_peripheral(struct isp1301 *isp)
+{
+ enable_vbus_draw(isp, 8);
+ OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+ usb_gadget_vbus_connect(isp->otg.gadget);
+
+#ifdef CONFIG_USB_OTG
+ otg_update_isp(isp);
+#else
+ /* UDC driver just set OTG_BSESSVLD */
+ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLUP);
+ isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLDOWN);
+ isp->otg.state = OTG_STATE_B_PERIPHERAL;
+ pr_debug(" --> b_peripheral\n");
+ dump_regs(isp, "2periph");
+#endif
+}
+
+static int isp_update_otg(struct isp1301 *isp, u8 stat)
+{
+ u8 isp_stat, isp_bstat;
+ enum usb_otg_state state = isp->otg.state;
+
+ if (stat & INTR_BDIS_ACON)
+ pr_debug("OTG: BDIS_ACON, %s\n", state_name(isp));
+
+ /* start certain state transitions right away */
+ isp_stat = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
+ if (isp_stat & INTR_ID_GND) {
+ if (isp->otg.default_a) {
+ switch (state) {
+ case OTG_STATE_B_IDLE:
+ a_idle(isp, "idle");
+ /* FALLTHROUGH */
+ case OTG_STATE_A_IDLE:
+ enable_vbus_source(isp);
+ /* FALLTHROUGH */
+ case OTG_STATE_A_WAIT_VRISE:
+ /* we skip over OTG_STATE_A_WAIT_BCON, since
+ * the HC will transition to A_HOST (or
+ * A_SUSPEND!) without our noticing except
+ * when HNP is used.
+ */
+ if (isp_stat & INTR_VBUS_VLD)
+ isp->otg.state = OTG_STATE_A_HOST;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ if (!(isp_stat & INTR_SESS_VLD))
+ a_idle(isp, "vfell");
+ break;
+ default:
+ if (!(isp_stat & INTR_VBUS_VLD))
+ isp->otg.state = OTG_STATE_A_VBUS_ERR;
+ break;
+ }
+ isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
+ } else {
+ switch (state) {
+ case OTG_STATE_B_PERIPHERAL:
+ case OTG_STATE_B_HOST:
+ case OTG_STATE_B_WAIT_ACON:
+ usb_gadget_vbus_disconnect(isp->otg.gadget);
+ break;
+ default:
+ break;
+ }
+ if (state != OTG_STATE_A_IDLE)
+ a_idle(isp, "id");
+ if (isp->otg.host && state == OTG_STATE_A_IDLE)
+ isp1301_defer_work(isp, WORK_HOST_RESUME);
+ isp_bstat = 0;
+ }
+ } else {
+ /* if user unplugged mini-A end of cable,
+ * don't bypass A_WAIT_VFALL.
+ */
+ if (isp->otg.default_a) {
+ switch (state) {
+ default:
+ isp->otg.state = OTG_STATE_A_WAIT_VFALL;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ state = OTG_STATE_A_IDLE;
+ /* khubd may take a while to notice and
+ * handle this disconnect, so don't go
+ * to B_IDLE quite yet.
+ */
+ break;
+ case OTG_STATE_A_IDLE:
+ host_suspend(isp);
+ isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
+ MC1_BDIS_ACON_EN);
+ isp->otg.state = OTG_STATE_B_IDLE;
+ OTG_CTRL_REG &= OTG_CTRL_REG & OTG_CTRL_MASK
+ & ~OTG_CTRL_BITS;
+ break;
+ case OTG_STATE_B_IDLE:
+ break;
+ }
+ }
+ isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
+
+ switch (isp->otg.state) {
+ case OTG_STATE_B_PERIPHERAL:
+ case OTG_STATE_B_WAIT_ACON:
+ case OTG_STATE_B_HOST:
+ if (likely(isp_bstat & OTG_B_SESS_VLD))
+ break;
+ enable_vbus_draw(isp, 0);
+#ifndef CONFIG_USB_OTG
+ /* UDC driver will clear OTG_BSESSVLD */
+ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
+ OTG1_DP_PULLDOWN);
+ isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
+ OTG1_DP_PULLUP);
+ dump_regs(isp, __FUNCTION__);
+#endif
+ /* FALLTHROUGH */
+ case OTG_STATE_B_SRP_INIT:
+ b_idle(isp, __FUNCTION__);
+ OTG_CTRL_REG &= OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+ /* FALLTHROUGH */
+ case OTG_STATE_B_IDLE:
+ if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) {
+#ifdef CONFIG_USB_OTG
+ update_otg1(isp, isp_stat);
+ update_otg2(isp, isp_bstat);
+#endif
+ b_peripheral(isp);
+ } else if (!(isp_stat & (INTR_VBUS_VLD|INTR_SESS_VLD)))
+ isp_bstat |= OTG_B_SESS_END;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ break;
+ default:
+ pr_debug("otg: unsupported b-device %s\n",
+ state_name(isp));
+ break;
+ }
+ }
+
+ if (state != isp->otg.state)
+ pr_debug(" isp, %s -> %s\n",
+ state_string(state), state_name(isp));
+
+#ifdef CONFIG_USB_OTG
+ /* update the OTG controller state to match the isp1301; may
+ * trigger OPRT_CHG irqs for changes going to the isp1301.
+ */
+ update_otg1(isp, isp_stat);
+ update_otg2(isp, isp_bstat);
+ check_state(isp, __FUNCTION__);
+#endif
+
+ dump_regs(isp, "isp1301->otg");
+}
+
+/*-------------------------------------------------------------------------*/
+
+static u8 isp1301_clear_latch(struct isp1301 *isp)
+{
+ u8 latch = isp1301_get_u8(isp, ISP1301_INTERRUPT_LATCH);
+ isp1301_clear_bits(isp, ISP1301_INTERRUPT_LATCH, latch);
+ return latch;
+}
+
+static void
+isp1301_work(void *data)
+{
+ struct isp1301 *isp = data;
+ int stop;
+
+ /* implicit lock: we're the only task using this device */
+ isp->working = 1;
+ do {
+ stop = test_bit(WORK_STOP, &isp->todo);
+
+#ifdef CONFIG_USB_OTG
+ /* transfer state from otg engine to isp1301 */
+ if (test_and_clear_bit(WORK_UPDATE_ISP, &isp->todo)) {
+ otg_update_isp(isp);
+ put_device(&isp->client.dev);
+ }
+#endif
+ /* transfer state from isp1301 to otg engine */
+ if (test_and_clear_bit(WORK_UPDATE_OTG, &isp->todo)) {
+ u8 stat = isp1301_clear_latch(isp);
+
+ isp_update_otg(isp, stat);
+ put_device(&isp->client.dev);
+ }
+
+ if (test_and_clear_bit(WORK_HOST_RESUME, &isp->todo)) {
+ u32 otg_ctrl;
+
+ /*
+ * skip A_WAIT_VRISE; hc transitions invisibly
+ * skip A_WAIT_BCON; same.
+ */
+ switch (isp->otg.state) {
+ case OTG_STATE_A_WAIT_BCON:
+ case OTG_STATE_A_WAIT_VRISE:
+ isp->otg.state = OTG_STATE_A_HOST;
+ pr_debug(" --> a_host\n");
+ otg_ctrl = OTG_CTRL_REG;
+ otg_ctrl |= OTG_A_BUSREQ;
+ otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
+ & OTG_CTRL_MASK;
+ OTG_CTRL_REG = otg_ctrl;
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+ isp->otg.state = OTG_STATE_B_HOST;
+ pr_debug(" --> b_host (acon)\n");
+ break;
+ case OTG_STATE_B_HOST:
+ case OTG_STATE_B_IDLE:
+ case OTG_STATE_A_IDLE:
+ break;
+ default:
+ pr_debug(" host resume in %s\n",
+ state_name(isp));
+ }
+ host_resume(isp);
+ // mdelay(10);
+ put_device(&isp->client.dev);
+ }
+
+ if (test_and_clear_bit(WORK_TIMER, &isp->todo)) {
+#ifdef VERBOSE
+ dump_regs(isp, "timer");
+ if (!stop)
+ mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
+#endif
+ put_device(&isp->client.dev);
+ }
+
+ if (isp->todo)
+ dev_vdbg(&isp->client.dev,
+ "work done, todo = 0x%lx\n",
+ isp->todo);
+ if (stop) {
+ dev_dbg(&isp->client.dev, "stop\n");
+ break;
+ }
+ } while (isp->todo);
+ isp->working = 0;
+}
+
+static irqreturn_t isp1301_irq(int irq, void *isp, struct pt_regs *regs)
+{
+ isp1301_defer_work(isp, WORK_UPDATE_OTG);
+ return IRQ_HANDLED;
+}
+
+static void isp1301_timer(unsigned long _isp)
+{
+ isp1301_defer_work((void *)_isp, WORK_TIMER);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void isp1301_release(struct device *dev)
+{
+ struct isp1301 *isp;
+
+ isp = container_of(dev, struct isp1301, client.dev);
+
+ /* ugly -- i2c hijacks our memory hook to wait_for_completion() */
+ if (isp->i2c_release)
+ isp->i2c_release(dev);
+ kfree (isp);
+}
+
+static struct isp1301 *the_transceiver;
+
+static int isp1301_detach_client(struct i2c_client *i2c)
+{
+ struct isp1301 *isp;
+
+ isp = container_of(i2c, struct isp1301, client);
+
+ isp1301_clear_bits(isp, ISP1301_INTERRUPT_FALLING, ~0);
+ isp1301_clear_bits(isp, ISP1301_INTERRUPT_RISING, ~0);
+ free_irq(isp->irq, isp);
+#ifdef CONFIG_USB_OTG
+ otg_unbind(isp);
+#endif
+ if (machine_is_omap_h2())
+ omap_free_gpio(2);
+
+ isp->timer.data = 0;
+ set_bit(WORK_STOP, &isp->todo);
+ del_timer_sync(&isp->timer);
+ flush_scheduled_work();
+
+ put_device(&i2c->dev);
+ the_transceiver = 0;
+
+ return i2c_detach_client(i2c);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* NOTE: three modes are possible here, only one of which
+ * will be standards-conformant on any given system:
+ *
+ * - OTG mode (dual-role), required if there's a Mini-AB connector
+ * - HOST mode, for when there's one or more A (host) connectors
+ * - DEVICE mode, for when there's a B/Mini-B (device) connector
+ *
+ * As a rule, you won't have an isp1301 chip unless it's there to
+ * support the OTG mode. Other modes help testing USB controllers
+ * in isolation from (full) OTG support, or maybe so later board
+ * revisions can help to support those feature.
+ */
+
+#ifdef CONFIG_USB_OTG
+
+static int isp1301_otg_enable(struct isp1301 *isp)
+{
+ power_up(isp);
+ otg_init(isp);
+
+ /* NOTE: since we don't change this, this provides
+ * a few more interrupts than are strictly needed.
+ */
+ isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
+ INTR_VBUS_VLD | INTR_SESS_VLD | INTR_ID_GND);
+ isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
+ INTR_VBUS_VLD | INTR_SESS_VLD | INTR_ID_GND);
+
+ dev_info(&isp->client.dev, "ready for dual-role USB ...\n");
+
+ return 0;
+}
+
+#endif
+
+/* add or disable the host device+driver */
+static int
+isp1301_set_host(struct otg_transceiver *otg, struct usb_bus *host)
+{
+ struct isp1301 *isp = container_of(otg, struct isp1301, otg);
+
+ if (!otg || isp != the_transceiver)
+ return -ENODEV;
+
+ if (!host) {
+ OTG_IRQ_EN_REG = 0;
+ power_down(isp);
+ isp->otg.host = 0;
+ return 0;
+ }
+
+#ifdef CONFIG_USB_OTG
+ isp->otg.host = host;
+ dev_dbg(&isp->client.dev, "registered host\n");
+ host_suspend(isp);
+ if (isp->otg.gadget)
+ return isp1301_otg_enable(isp);
+ return 0;
+
+#elif !defined(CONFIG_USB_GADGET_OMAP)
+ // FIXME update its refcount
+ isp->otg.host = host;
+
+ power_up(isp);
+
+ if (machine_is_omap_h2())
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
+
+ dev_info(&isp->client.dev, "A-Host sessions ok\n");
+ isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
+ INTR_ID_GND);
+ isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
+ INTR_ID_GND);
+
+ /* If this has a Mini-AB connector, this mode is highly
+ * nonstandard ... but can be handy for testing, especially with
+ * the Mini-A end of an OTG cable. (Or something nonstandard
+ * like MiniB-to-StandardB, maybe built with a gender mender.)
+ */
+ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_VBUS_DRV);
+
+ dump_regs(isp, __FUNCTION__);
+
+ return 0;
+
+#else
+ dev_dbg(&isp->client.dev, "host sessions not allowed\n");
+ return -EINVAL;
+#endif
+
+}
+
+static int
+isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
+{
+ struct isp1301 *isp = container_of(otg, struct isp1301, otg);
+
+ if (!otg || isp != the_transceiver)
+ return -ENODEV;
+
+ if (!gadget) {
+ OTG_IRQ_EN_REG = 0;
+ if (!isp->otg.default_a)
+ enable_vbus_draw(isp, 0);
+ usb_gadget_vbus_disconnect(isp->otg.gadget);
+ isp->otg.gadget = 0;
+ power_down(isp);
+ return 0;
+ }
+
+#ifdef CONFIG_USB_OTG
+ isp->otg.gadget = gadget;
+ dev_dbg(&isp->client.dev, "registered gadget\n");
+ /* gadget driver may be suspended until vbus_connect () */
+ if (isp->otg.host)
+ return isp1301_otg_enable(isp);
+ return 0;
+
+#elif !defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OHCI_HCD_MODULE)
+ isp->otg.gadget = gadget;
+ // FIXME update its refcount
+
+ OTG_CTRL_REG = (OTG_CTRL_REG & OTG_CTRL_MASK
+ & ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS))
+ | OTG_ID;
+ power_up(isp);
+ isp->otg.state = OTG_STATE_B_IDLE;
+
+ if (machine_is_omap_h2())
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
+
+ isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
+ INTR_SESS_VLD);
+ isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
+ INTR_VBUS_VLD);
+ dev_info(&isp->client.dev, "B-Peripheral sessions ok\n");
+ dump_regs(isp, __FUNCTION__);
+
+ /* If this has a Mini-AB connector, this mode is highly
+ * nonstandard ... but can be handy for testing, so long
+ * as you don't plug a Mini-A cable into the jack.
+ */
+ if (isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE) & INTR_VBUS_VLD)
+ b_peripheral(isp);
+
+ return 0;
+
+#else
+ dev_dbg(&isp->client.dev, "peripheral sessions not allowed\n");
+ return -EINVAL;
+#endif
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int
+isp1301_set_power(struct otg_transceiver *dev, unsigned mA)
+{
+ if (!the_transceiver)
+ return -ENODEV;
+ if (dev->state == OTG_STATE_B_PERIPHERAL)
+ enable_vbus_draw(the_transceiver, mA);
+ return 0;
+}
+
+static int
+isp1301_start_srp(struct otg_transceiver *dev)
+{
+ struct isp1301 *isp = container_of(dev, struct isp1301, otg);
+ u32 otg_ctrl;
+
+ if (!dev || isp != the_transceiver
+ || isp->otg.state != OTG_STATE_B_IDLE)
+ return -ENODEV;
+
+ otg_ctrl = OTG_CTRL_REG;
+ if (!(otg_ctrl & OTG_BSESSEND))
+ return -EINVAL;
+
+ otg_ctrl |= OTG_B_BUSREQ;
+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK;
+ OTG_CTRL_REG = otg_ctrl;
+ isp->otg.state = OTG_STATE_B_SRP_INIT;
+
+ pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), OTG_CTRL_REG);
+#ifdef CONFIG_USB_OTG
+ check_state(isp, __FUNCTION__);
+#endif
+ return 0;
+}
+
+static int
+isp1301_start_hnp(struct otg_transceiver *dev)
+{
+#ifdef CONFIG_USB_OTG
+ struct isp1301 *isp = container_of(dev, struct isp1301, otg);
+
+ if (!dev || isp != the_transceiver)
+ return -ENODEV;
+ if (isp->otg.default_a && (isp->otg.host == NULL
+ || !isp->otg.host->b_hnp_enable))
+ return -ENOTCONN;
+ if (!isp->otg.default_a && (isp->otg.gadget == NULL
+ || !isp->otg.gadget->b_hnp_enable))
+ return -ENOTCONN;
+
+ /* We want hardware to manage most HNP protocol timings.
+ * So do this part as early as possible...
+ */
+ switch (isp->otg.state) {
+ case OTG_STATE_B_HOST:
+ isp->otg.state = OTG_STATE_B_PERIPHERAL;
+ /* caller will suspend next */
+ break;
+ case OTG_STATE_A_HOST:
+#if 0
+ /* autoconnect mode avoids irq latency bugs */
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
+ MC1_BDIS_ACON_EN);
+#endif
+ /* caller must suspend then clear A_BUSREQ */
+ usb_gadget_vbus_connect(isp->otg.gadget);
+ OTG_CTRL_REG |= OTG_A_SETB_HNPEN;
+
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+ /* initiated by B-Host suspend */
+ break;
+ default:
+ return -EILSEQ;
+ }
+ pr_debug("otg: HNP %s, %06x ...\n",
+ state_name(isp), OTG_CTRL_REG);
+ check_state(isp, __FUNCTION__);
+ return 0;
+#else
+ /* srp-only */
+ return -EINVAL;
+#endif
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* no error returns, they'd just make bus scanning stop */
+static int isp1301_probe(struct i2c_adapter *bus, int address, int kind)
+{
+ int status;
+ struct isp1301 *isp;
+ struct i2c_client *i2c;
+
+ if (the_transceiver)
+ return 0;
+
+ isp = kmalloc(sizeof *isp, GFP_KERNEL);
+ if (!isp)
+ return 0;
+
+ memset(isp, 0, sizeof *isp);
+
+ INIT_WORK(&isp->work, isp1301_work, isp);
+ init_timer(&isp->timer);
+ isp->timer.function = isp1301_timer;
+ isp->timer.data = (unsigned long) isp;
+
+ isp->irq = -1;
+ isp->client.addr = address;
+ i2c_set_clientdata(&isp->client, isp);
+ isp->client.adapter = bus;
+ isp->client.id = 1301;
+ isp->client.driver = &isp1301_driver;
+ strlcpy(isp->client.name, DRIVER_NAME, I2C_NAME_SIZE);
+ i2c = &isp->client;
+
+ /* if this is a true probe, verify the chip ... */
+ if (kind < 0) {
+ status = isp1301_get_u16(isp, ISP1301_VENDOR_ID);
+ if (status != I2C_VENDOR_ID_PHILIPS) {
+ dev_dbg(&bus->dev, "addr %d not philips id: %d\n",
+ address, status);
+ goto fail1;
+ }
+ status = isp1301_get_u16(isp, ISP1301_PRODUCT_ID);
+ if (status != I2C_PRODUCT_ID_PHILIPS_1301) {
+ dev_dbg(&bus->dev, "%d not isp1301, %d\n",
+ address, status);
+ goto fail1;
+ }
+ }
+
+ status = i2c_attach_client(i2c);
+ if (status < 0) {
+ dev_dbg(&bus->dev, "can't attach %s to device %d, err %d\n",
+ DRIVER_NAME, address, status);
+fail1:
+ kfree(isp);
+ return 0;
+ }
+ isp->i2c_release = i2c->dev.release;
+ i2c->dev.release = isp1301_release;
+
+ /* initial development used chiprev 2.00 */
+ status = i2c_smbus_read_word_data(i2c, ISP1301_BCD_DEVICE);
+ dev_info(&i2c->dev, "chiprev %x.%02x, driver " DRIVER_VERSION "\n",
+ status >> 8, status & 0xff);
+
+ /* make like power-on reset */
+ isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_MASK);
+
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_BI_DI);
+ isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, ~MC2_BI_DI);
+
+ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
+ OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
+ isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
+ ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
+
+ isp1301_clear_bits(isp, ISP1301_INTERRUPT_LATCH, ~0);
+ isp1301_clear_bits(isp, ISP1301_INTERRUPT_FALLING, ~0);
+ isp1301_clear_bits(isp, ISP1301_INTERRUPT_RISING, ~0);
+
+#ifdef CONFIG_USB_OTG
+ status = otg_bind(isp);
+ if (status < 0) {
+ dev_dbg(&i2c->dev, "can't bind OTG\n");
+ goto fail2;
+ }
+#endif
+
+ if (machine_is_omap_h2()) {
+ /* full speed signaling by default */
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
+ MC1_SPEED_REG);
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2,
+ MC2_SPD_SUSP_CTRL);
+
+ /* IRQ wired at M14 */
+ omap_cfg_reg(M14_1510_GPIO2);
+ isp->irq = OMAP_GPIO_IRQ(2);
+ omap_request_gpio(2);
+ omap_set_gpio_direction(2, 1);
+ omap_set_gpio_edge_ctrl(2, OMAP_GPIO_FALLING_EDGE);
+ }
+
+ status = request_irq(isp->irq, isp1301_irq,
+ SA_SAMPLE_RANDOM, DRIVER_NAME, isp);
+ if (status < 0) {
+ dev_dbg(&i2c->dev, "can't get IRQ %d, err %d\n",
+ isp->irq, status);
+#ifdef CONFIG_USB_OTG
+fail2:
+#endif
+ i2c_detach_client(i2c);
+ goto fail1;
+ }
+
+ isp->otg.dev = &isp->client.dev;
+ isp->otg.label = DRIVER_NAME;
+
+ isp->otg.set_host = isp1301_set_host,
+ isp->otg.set_peripheral = isp1301_set_peripheral,
+ isp->otg.set_power = isp1301_set_power,
+ isp->otg.start_srp = isp1301_start_srp,
+ isp->otg.start_hnp = isp1301_start_hnp,
+
+ enable_vbus_draw(isp, 0);
+ power_down(isp);
+ the_transceiver = isp;
+
+#ifdef CONFIG_USB_OTG
+ update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
+ update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
+#endif
+
+ dump_regs(isp, __FUNCTION__);
+
+#ifdef VERBOSE
+ mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
+ dev_dbg(&i2c->dev, "scheduled timer, %d min\n", TIMER_MINUTES);
+#endif
+
+ status = otg_set_transceiver(&isp->otg);
+ if (status < 0)
+ dev_err(&i2c->dev, "can't register transceiver, %d\n",
+ status);
+
+ return 0;
+}
+
+static int isp1301_scan_bus(struct i2c_adapter *bus)
+{
+ if (!i2c_check_functionality(bus, I2C_FUNC_SMBUS_BYTE_DATA
+ | I2C_FUNC_SMBUS_READ_WORD_DATA))
+ return -EINVAL;
+ return i2c_probe(bus, &addr_data, isp1301_probe);
+}
+
+static struct i2c_driver isp1301_driver = {
+ .owner = THIS_MODULE,
+ .name = "isp1301_omap",
+ .id = 1301, /* FIXME "official", i2c-ids.h */
+ .class = I2C_CLASS_HWMON,
+ .flags = I2C_DF_NOTIFY,
+ .attach_adapter = isp1301_scan_bus,
+ .detach_client = isp1301_detach_client,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int __init isp_init(void)
+{
+ return i2c_add_driver(&isp1301_driver);
+}
+module_init(isp_init);
+
+static void __exit isp_exit(void)
+{
+ if (the_transceiver)
+ otg_set_transceiver(0);
+ i2c_del_driver(&isp1301_driver);
+}
+module_exit(isp_exit);
+
--- /dev/null
+/*
+ smsc47m1.c - Part of lm_sensors, Linux kernel modules
+ for hardware monitoring
+
+ Supports the SMSC LPC47B27x, LPC47M10x, LPC47M13x and LPC47M14x
+ Super-I/O chips.
+
+ Copyright (C) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
+ Copyright (C) 2004 Jean Delvare <khali@linux-fr.org>
+ Ported to Linux 2.6 by Gabriele Gorla <gorlik@yahoo.com>
+ and Jean Delvare
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/i2c-sensor.h>
+#include <linux/init.h>
+#include <asm/io.h>
+
+static unsigned short normal_i2c[] = { I2C_CLIENT_END };
+static unsigned short normal_i2c_range[] = { I2C_CLIENT_END };
+/* Address is autodetected, there is no default value */
+static unsigned int normal_isa[] = { 0x0000, I2C_CLIENT_ISA_END };
+static unsigned int normal_isa_range[] = { I2C_CLIENT_ISA_END };
+static struct i2c_force_data forces[] = {{NULL}};
+
+enum chips { any_chip, smsc47m1 };
+static struct i2c_address_data addr_data = {
+ .normal_i2c = normal_i2c,
+ .normal_i2c_range = normal_i2c_range,
+ .normal_isa = normal_isa,
+ .normal_isa_range = normal_isa_range,
+ .probe = normal_i2c, /* cheat */
+ .probe_range = normal_i2c_range, /* cheat */
+ .ignore = normal_i2c, /* cheat */
+ .ignore_range = normal_i2c_range, /* cheat */
+ .forces = forces,
+};
+
+/* Super-I/0 registers and commands */
+
+#define REG 0x2e /* The register to read/write */
+#define VAL 0x2f /* The value to read/write */
+
+static inline void
+superio_outb(int reg, int val)
+{
+ outb(reg, REG);
+ outb(val, VAL);
+}
+
+static inline int
+superio_inb(int reg)
+{
+ outb(reg, REG);
+ return inb(VAL);
+}
+
+/* logical device for fans is 0x0A */
+#define superio_select() superio_outb(0x07, 0x0A)
+
+static inline void
+superio_enter(void)
+{
+ outb(0x55, REG);
+}
+
+static inline void
+superio_exit(void)
+{
+ outb(0xAA, REG);
+}
+
+#define SUPERIO_REG_ACT 0x30
+#define SUPERIO_REG_BASE 0x60
+#define SUPERIO_REG_DEVID 0x20
+
+/* Logical device registers */
+
+#define SMSC_EXTENT 0x80
+
+/* nr is 0 or 1 in the macros below */
+#define SMSC47M1_REG_ALARM 0x04
+#define SMSC47M1_REG_TPIN(nr) (0x34 - (nr))
+#define SMSC47M1_REG_PPIN(nr) (0x36 - (nr))
+#define SMSC47M1_REG_PWM(nr) (0x56 + (nr))
+#define SMSC47M1_REG_FANDIV 0x58
+#define SMSC47M1_REG_FAN(nr) (0x59 + (nr))
+#define SMSC47M1_REG_FAN_PRELOAD(nr) (0x5B + (nr))
+
+#define MIN_FROM_REG(reg,div) ((reg)>=192 ? 0 : \
+ 983040/((192-(reg))*(div)))
+#define FAN_FROM_REG(reg,div,preload) ((reg)<=(preload) || (reg)==255 ? 0 : \
+ 983040/(((reg)-(preload))*(div)))
+#define DIV_FROM_REG(reg) (1 << (reg))
+#define PWM_FROM_REG(reg) (((reg) & 0x7E) << 1)
+#define PWM_EN_FROM_REG(reg) ((~(reg)) & 0x01)
+#define PWM_TO_REG(reg) (((reg) >> 1) & 0x7E)
+
+struct smsc47m1_data {
+ struct i2c_client client;
+ struct semaphore lock;
+ int sysctl_id;
+
+ struct semaphore update_lock;
+ unsigned long last_updated; /* In jiffies */
+
+ u8 fan[2]; /* Register value */
+ u8 fan_preload[2]; /* Register value */
+ u8 fan_div[2]; /* Register encoding, shifted right */
+ u8 alarms; /* Register encoding */
+ u8 pwm[2]; /* Register value (bit 7 is enable) */
+};
+
+
+static int smsc47m1_attach_adapter(struct i2c_adapter *adapter);
+static int smsc47m1_find(int *address);
+static int smsc47m1_detect(struct i2c_adapter *adapter, int address, int kind);
+static int smsc47m1_detach_client(struct i2c_client *client);
+
+static int smsc47m1_read_value(struct i2c_client *client, u8 reg);
+static void smsc47m1_write_value(struct i2c_client *client, u8 reg, u8 value);
+
+static struct smsc47m1_data *smsc47m1_update_device(struct device *dev,
+ int init);
+
+
+static int smsc47m1_id;
+
+static struct i2c_driver smsc47m1_driver = {
+ .owner = THIS_MODULE,
+ .name = "smsc47m1",
+ .id = I2C_DRIVERID_SMSC47M1,
+ .flags = I2C_DF_NOTIFY,
+ .attach_adapter = smsc47m1_attach_adapter,
+ .detach_client = smsc47m1_detach_client,
+};
+
+/* nr is 0 or 1 in the callback functions below */
+
+static ssize_t get_fan(struct device *dev, char *buf, int nr)
+{
+ struct smsc47m1_data *data = smsc47m1_update_device(dev, 0);
+ /* This chip (stupidly) stops monitoring fan speed if PWM is
+ enabled and duty cycle is 0%. This is fine if the monitoring
+ and control concern the same fan, but troublesome if they are
+ not (which could as well happen). */
+ int rpm = (data->pwm[nr] & 0x7F) == 0x00 ? 0 :
+ FAN_FROM_REG(data->fan[nr],
+ DIV_FROM_REG(data->fan_div[nr]),
+ data->fan_preload[nr]);
+ return sprintf(buf, "%d\n", rpm);
+}
+
+static ssize_t get_fan_min(struct device *dev, char *buf, int nr)
+{
+ struct smsc47m1_data *data = smsc47m1_update_device(dev, 0);
+ int rpm = MIN_FROM_REG(data->fan_preload[nr],
+ DIV_FROM_REG(data->fan_div[nr]));
+ return sprintf(buf, "%d\n", rpm);
+}
+
+static ssize_t get_fan_div(struct device *dev, char *buf, int nr)
+{
+ struct smsc47m1_data *data = smsc47m1_update_device(dev, 0);
+ return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
+}
+
+static ssize_t get_fan_pwm(struct device *dev, char *buf, int nr)
+{
+ struct smsc47m1_data *data = smsc47m1_update_device(dev, 0);
+ return sprintf(buf, "%d\n", PWM_FROM_REG(data->pwm[nr]));
+}
+
+static ssize_t get_fan_pwm_en(struct device *dev, char *buf, int nr)
+{
+ struct smsc47m1_data *data = smsc47m1_update_device(dev, 0);
+ return sprintf(buf, "%d\n", PWM_EN_FROM_REG(data->pwm[nr]));
+}
+
+static ssize_t get_alarms(struct device *dev, char *buf)
+{
+ struct smsc47m1_data *data = smsc47m1_update_device(dev, 0);
+ return sprintf(buf, "%d\n", data->alarms);
+}
+
+static ssize_t set_fan_min(struct device *dev, const char *buf,
+ size_t count, int nr)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct smsc47m1_data *data = i2c_get_clientdata(client);
+
+ long rpmdiv = simple_strtol(buf, NULL, 10)
+ * DIV_FROM_REG(data->fan_div[nr]);
+
+ if (983040 > 192 * rpmdiv || 2 * rpmdiv > 983040)
+ return -EINVAL;
+
+ data->fan_preload[nr] = 192 - ((983040 + rpmdiv / 2) / rpmdiv);
+ smsc47m1_write_value(client, SMSC47M1_REG_FAN_PRELOAD(nr),
+ data->fan_preload[nr]);
+
+ return count;
+}
+
+/* Note: we save and restore the fan minimum here, because its value is
+ determined in part by the fan clock divider. This follows the principle
+ of least suprise; the user doesn't expect the fan minimum to change just
+ because the divider changed. */
+static ssize_t set_fan_div(struct device *dev, const char *buf,
+ size_t count, int nr)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct smsc47m1_data *data = i2c_get_clientdata(client);
+
+ long new_div = simple_strtol(buf, NULL, 10), tmp;
+ u8 old_div = DIV_FROM_REG(data->fan_div[nr]);
+
+ if (new_div == old_div) /* No change */
+ return count;
+ switch (new_div) {
+ case 1: data->fan_div[nr] = 0; break;
+ case 2: data->fan_div[nr] = 1; break;
+ case 4: data->fan_div[nr] = 2; break;
+ case 8: data->fan_div[nr] = 3; break;
+ default: return -EINVAL;
+ }
+
+ tmp = smsc47m1_read_value(client, SMSC47M1_REG_FANDIV) & 0x0F;
+ tmp |= (data->fan_div[0] << 4) | (data->fan_div[1] << 6);
+ smsc47m1_write_value(client, SMSC47M1_REG_FANDIV, tmp);
+
+ /* Preserve fan min */
+ tmp = 192 - (old_div * (192 - data->fan_preload[nr])
+ + new_div / 2) / new_div;
+ data->fan_preload[nr] = SENSORS_LIMIT(tmp, 0, 191);
+ smsc47m1_write_value(client, SMSC47M1_REG_FAN_PRELOAD(nr),
+ data->fan_preload[nr]);
+
+ return count;
+}
+
+static ssize_t set_fan_pwm(struct device *dev, const char *buf,
+ size_t count, int nr)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct smsc47m1_data *data = i2c_get_clientdata(client);
+
+ long val = simple_strtol(buf, NULL, 10);
+
+ if (val < 0 || val > 255)
+ return -EINVAL;
+
+ data->pwm[nr] &= 0x81; /* Preserve additional bits */
+ data->pwm[nr] |= PWM_TO_REG(val);
+
+ smsc47m1_write_value(client, SMSC47M1_REG_PWM(nr),
+ data->pwm[nr]);
+ return count;
+}
+
+static ssize_t set_fan_pwm_en(struct device *dev, const char *buf,
+ size_t count, int nr)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct smsc47m1_data *data = i2c_get_clientdata(client);
+
+ long val = simple_strtol(buf, NULL, 10);
+
+ if (val != 0 && val != 1)
+ return -EINVAL;
+
+ data->pwm[nr] &= 0xFE; /* preserve the other bits */
+ data->pwm[nr] |= !val;
+
+ smsc47m1_write_value(client, SMSC47M1_REG_PWM(nr),
+ data->pwm[nr]);
+
+ return count;
+}
+
+#define fan_present(offset) \
+static ssize_t get_fan##offset (struct device *dev, char *buf) \
+{ \
+ return get_fan(dev, buf, 0x##offset - 1); \
+} \
+static ssize_t get_fan##offset##_min (struct device *dev, char *buf) \
+{ \
+ return get_fan_min(dev, buf, 0x##offset - 1); \
+} \
+static ssize_t set_fan##offset##_min (struct device *dev, \
+ const char *buf, size_t count) \
+{ \
+ return set_fan_min(dev, buf, count, 0x##offset - 1); \
+} \
+static ssize_t get_fan##offset##_div (struct device *dev, char *buf) \
+{ \
+ return get_fan_div(dev, buf, 0x##offset - 1); \
+} \
+static ssize_t set_fan##offset##_div (struct device *dev, \
+ const char *buf, size_t count) \
+{ \
+ return set_fan_div(dev, buf, count, 0x##offset - 1); \
+} \
+static ssize_t get_fan##offset##_pwm (struct device *dev, char *buf) \
+{ \
+ return get_fan_pwm(dev, buf, 0x##offset - 1); \
+} \
+static ssize_t set_fan##offset##_pwm (struct device *dev, \
+ const char *buf, size_t count) \
+{ \
+ return set_fan_pwm(dev, buf, count, 0x##offset - 1); \
+} \
+static ssize_t get_fan##offset##_pwm_en (struct device *dev, char *buf) \
+{ \
+ return get_fan_pwm_en(dev, buf, 0x##offset - 1); \
+} \
+static ssize_t set_fan##offset##_pwm_en (struct device *dev, \
+ const char *buf, size_t count) \
+{ \
+ return set_fan_pwm_en(dev, buf, count, 0x##offset - 1); \
+} \
+static DEVICE_ATTR(fan##offset##_input, S_IRUGO, get_fan##offset, \
+ NULL); \
+static DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
+ get_fan##offset##_min, set_fan##offset##_min); \
+static DEVICE_ATTR(fan##offset##_div, S_IRUGO | S_IWUSR, \
+ get_fan##offset##_div, set_fan##offset##_div); \
+static DEVICE_ATTR(fan##offset##_pwm, S_IRUGO | S_IWUSR, \
+ get_fan##offset##_pwm, set_fan##offset##_pwm); \
+static DEVICE_ATTR(fan##offset##_pwm_enable, S_IRUGO | S_IWUSR, \
+ get_fan##offset##_pwm_en, set_fan##offset##_pwm_en);
+
+fan_present(1);
+fan_present(2);
+
+static DEVICE_ATTR(alarms, S_IRUGO, get_alarms, NULL);
+
+static int smsc47m1_attach_adapter(struct i2c_adapter *adapter)
+{
+ if (!(adapter->class & I2C_CLASS_HWMON))
+ return 0;
+ return i2c_detect(adapter, &addr_data, smsc47m1_detect);
+}
+
+static int smsc47m1_find(int *address)
+{
+ u8 val;
+
+ superio_enter();
+ val = superio_inb(SUPERIO_REG_DEVID);
+
+ /*
+ * SMSC LPC47M10x/LPC47M13x (device id 0x59), LPC47M14x (device id
+ * 0x5F) and LPC47B27x (device id 0x51) have fan control.
+ * The LPC47M15x and LPC47M192 chips "with hardware monitoring block"
+ * can do much more besides (device id 0x60, unsupported).
+ */
+ if (val == 0x51)
+ printk(KERN_INFO "smsc47m1: Found SMSC47B27x\n");
+ else if (val == 0x59)
+ printk(KERN_INFO "smsc47m1: Found SMSC47M10x/SMSC47M13x\n");
+ else if (val == 0x5F)
+ printk(KERN_INFO "smsc47m1: Found SMSC47M14x\n");
+ else {
+ superio_exit();
+ return -ENODEV;
+ }
+
+ superio_select();
+ *address = (superio_inb(SUPERIO_REG_BASE) << 8)
+ | superio_inb(SUPERIO_REG_BASE + 1);
+ val = superio_inb(SUPERIO_REG_ACT);
+ if (*address == 0 || (val & 0x01) == 0) {
+ printk(KERN_INFO "smsc47m1: Device is disabled, will not use\n");
+ superio_exit();
+ return -ENODEV;
+ }
+
+ superio_exit();
+ return 0;
+}
+
+static int smsc47m1_detect(struct i2c_adapter *adapter, int address, int kind)
+{
+ struct i2c_client *new_client;
+ struct smsc47m1_data *data;
+ int err = 0;
+
+ if (!i2c_is_isa_adapter(adapter)) {
+ return 0;
+ }
+
+ if (!request_region(address, SMSC_EXTENT, "smsc47m1")) {
+ dev_err(&adapter->dev, "Region 0x%x already in use!\n", address);
+ return -EBUSY;
+ }
+
+ if (!(data = kmalloc(sizeof(struct smsc47m1_data), GFP_KERNEL))) {
+ err = -ENOMEM;
+ goto error_release;
+ }
+ memset(data, 0x00, sizeof(struct smsc47m1_data));
+
+ new_client = &data->client;
+ i2c_set_clientdata(new_client, data);
+ new_client->addr = address;
+ init_MUTEX(&data->lock);
+ new_client->adapter = adapter;
+ new_client->driver = &smsc47m1_driver;
+ new_client->flags = 0;
+
+ strlcpy(new_client->name, "smsc47m1", I2C_NAME_SIZE);
+
+ new_client->id = smsc47m1_id++;
+ init_MUTEX(&data->update_lock);
+
+ if ((err = i2c_attach_client(new_client)))
+ goto error_free;
+
+ /* Some values (fan min, clock dividers, pwm registers) may be
+ needed before any update is triggered, so we better read them
+ at least once here. We don't usually do it that way, but in
+ this particular case, manually reading 5 registers out of 8
+ doesn't make much sense and we're better using the existing
+ function. */
+ smsc47m1_update_device(&new_client->dev, 1);
+
+ if ((smsc47m1_read_value(new_client, SMSC47M1_REG_TPIN(0)) & 0x05)
+ == 0x05) {
+ device_create_file(&new_client->dev, &dev_attr_fan1_input);
+ device_create_file(&new_client->dev, &dev_attr_fan1_min);
+ device_create_file(&new_client->dev, &dev_attr_fan1_div);
+ } else
+ dev_dbg(&new_client->dev, "Fan 1 not enabled by hardware, "
+ "skipping\n");
+
+ if ((smsc47m1_read_value(new_client, SMSC47M1_REG_TPIN(1)) & 0x05)
+ == 0x05) {
+ device_create_file(&new_client->dev, &dev_attr_fan2_input);
+ device_create_file(&new_client->dev, &dev_attr_fan2_min);
+ device_create_file(&new_client->dev, &dev_attr_fan2_div);
+ } else
+ dev_dbg(&new_client->dev, "Fan 2 not enabled by hardware, "
+ "skipping\n");
+
+ if ((smsc47m1_read_value(new_client, SMSC47M1_REG_PPIN(0)) & 0x05)
+ == 0x04) {
+ device_create_file(&new_client->dev, &dev_attr_fan1_pwm);
+ device_create_file(&new_client->dev, &dev_attr_fan1_pwm_enable);
+ } else
+ dev_dbg(&new_client->dev, "PWM 1 not enabled by hardware, "
+ "skipping\n");
+ if ((smsc47m1_read_value(new_client, SMSC47M1_REG_PPIN(1)) & 0x05)
+ == 0x04) {
+ device_create_file(&new_client->dev, &dev_attr_fan2_pwm);
+ device_create_file(&new_client->dev, &dev_attr_fan2_pwm_enable);
+ } else
+ dev_dbg(&new_client->dev, "PWM 2 not enabled by hardware, "
+ "skipping\n");
+
+ device_create_file(&new_client->dev, &dev_attr_alarms);
+
+ return 0;
+
+error_free:
+ kfree(new_client);
+error_release:
+ release_region(address, SMSC_EXTENT);
+ return err;
+}
+
+static int smsc47m1_detach_client(struct i2c_client *client)
+{
+ int err;
+
+ if ((err = i2c_detach_client(client))) {
+ dev_err(&client->dev, "Client deregistration failed, "
+ "client not detached.\n");
+ return err;
+ }
+
+ release_region(client->addr, SMSC_EXTENT);
+ kfree(i2c_get_clientdata(client));
+
+ return 0;
+}
+
+static int smsc47m1_read_value(struct i2c_client *client, u8 reg)
+{
+ int res;
+
+ down(&((struct smsc47m1_data *) i2c_get_clientdata(client))->lock);
+ res = inb_p(client->addr + reg);
+ up(&((struct smsc47m1_data *) i2c_get_clientdata(client))->lock);
+ return res;
+}
+
+static void smsc47m1_write_value(struct i2c_client *client, u8 reg, u8 value)
+{
+ down(&((struct smsc47m1_data *) i2c_get_clientdata(client))->lock);
+ outb_p(value, client->addr + reg);
+ up(&((struct smsc47m1_data *) i2c_get_clientdata(client))->lock);
+}
+
+static struct smsc47m1_data *smsc47m1_update_device(struct device *dev,
+ int init)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct smsc47m1_data *data = i2c_get_clientdata(client);
+
+ down(&data->update_lock);
+
+ if ((jiffies - data->last_updated > HZ + HZ / 2) ||
+ (jiffies < data->last_updated) || init) {
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ data->fan[i] = smsc47m1_read_value(client,
+ SMSC47M1_REG_FAN(i));
+ data->fan_preload[i] = smsc47m1_read_value(client,
+ SMSC47M1_REG_FAN_PRELOAD(i));
+ data->pwm[i] = smsc47m1_read_value(client,
+ SMSC47M1_REG_PWM(i));
+ }
+
+ i = smsc47m1_read_value(client, SMSC47M1_REG_FANDIV);
+ data->fan_div[0] = (i >> 4) & 0x03;
+ data->fan_div[1] = i >> 6;
+
+ data->alarms = smsc47m1_read_value(client,
+ SMSC47M1_REG_ALARM) >> 6;
+ /* Clear alarms if needed */
+ if (data->alarms)
+ smsc47m1_write_value(client, SMSC47M1_REG_ALARM, 0xC0);
+
+ data->last_updated = jiffies;
+ }
+
+ up(&data->update_lock);
+ return data;
+}
+
+static int __init sm_smsc47m1_init(void)
+{
+ if (smsc47m1_find(normal_isa)) {
+ return -ENODEV;
+ }
+
+ return i2c_add_driver(&smsc47m1_driver);
+}
+
+static void __exit sm_smsc47m1_exit(void)
+{
+ i2c_del_driver(&smsc47m1_driver);
+}
+
+MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
+MODULE_DESCRIPTION("SMSC LPC47M1xx fan sensors driver");
+MODULE_LICENSE("GPL");
+
+module_init(sm_smsc47m1_init);
+module_exit(sm_smsc47m1_exit);
--- /dev/null
+/*
+ i2c-sensor-detect.c - Part of lm_sensors, Linux kernel modules for hardware
+ monitoring
+ Copyright (c) 1998 - 2001 Frodo Looijaard <frodol@dds.nl> and
+ Mark D. Studebaker <mdsxyz123@yahoo.com>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/sysctl.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/i2c-sensor.h>
+#include <asm/uaccess.h>
+
+
+/* Very inefficient for ISA detects, and won't work for 10-bit addresses! */
+int i2c_detect(struct i2c_adapter *adapter,
+ struct i2c_address_data *address_data,
+ int (*found_proc) (struct i2c_adapter *, int, int))
+{
+ int addr, i, found, j, err;
+ struct i2c_force_data *this_force;
+ int is_isa = i2c_is_isa_adapter(adapter);
+ int adapter_id =
+ is_isa ? ANY_I2C_ISA_BUS : i2c_adapter_id(adapter);
+
+ /* Forget it if we can't probe using SMBUS_QUICK */
+ if ((!is_isa) &&
+ !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_QUICK))
+ return -1;
+
+ for (addr = 0x00; addr <= (is_isa ? 0xffff : 0x7f); addr++) {
+ if (!is_isa && i2c_check_addr(adapter, addr))
+ continue;
+
+ /* If it is in one of the force entries, we don't do any
+ detection at all */
+ found = 0;
+ for (i = 0; !found && (this_force = address_data->forces + i, this_force->force); i++) {
+ for (j = 0; !found && (this_force->force[j] != I2C_CLIENT_END); j += 2) {
+ if ( ((adapter_id == this_force->force[j]) ||
+ ((this_force->force[j] == ANY_I2C_BUS) && !is_isa)) &&
+ (addr == this_force->force[j + 1]) ) {
+ dev_dbg(&adapter->dev, "found force parameter for adapter %d, addr %04x\n", adapter_id, addr);
+ if ((err = found_proc(adapter, addr, this_force->kind)))
+ return err;
+ found = 1;
+ }
+ }
+ }
+ if (found)
+ continue;
+
+ /* If this address is in one of the ignores, we can forget about it
+ right now */
+ for (i = 0; !found && (address_data->ignore[i] != I2C_CLIENT_END); i += 2) {
+ if ( ((adapter_id == address_data->ignore[i]) ||
+ ((address_data->ignore[i] == ANY_I2C_BUS) &&
+ !is_isa)) &&
+ (addr == address_data->ignore[i + 1])) {
+ dev_dbg(&adapter->dev, "found ignore parameter for adapter %d, addr %04x\n", adapter_id, addr);
+ found = 1;
+ }
+ }
+ for (i = 0; !found && (address_data->ignore_range[i] != I2C_CLIENT_END); i += 3) {
+ if ( ((adapter_id == address_data->ignore_range[i]) ||
+ ((address_data-> ignore_range[i] == ANY_I2C_BUS) &
+ !is_isa)) &&
+ (addr >= address_data->ignore_range[i + 1]) &&
+ (addr <= address_data->ignore_range[i + 2])) {
+ dev_dbg(&adapter->dev, "found ignore_range parameter for adapter %d, addr %04x\n", adapter_id, addr);
+ found = 1;
+ }
+ }
+ if (found)
+ continue;
+
+ /* Now, we will do a detection, but only if it is in the normal or
+ probe entries */
+ if (is_isa) {
+ for (i = 0; !found && (address_data->normal_isa[i] != I2C_CLIENT_ISA_END); i += 1) {
+ if (addr == address_data->normal_isa[i]) {
+ dev_dbg(&adapter->dev, "found normal isa entry for adapter %d, addr %04x\n", adapter_id, addr);
+ found = 1;
+ }
+ }
+ for (i = 0; !found && (address_data->normal_isa_range[i] != I2C_CLIENT_ISA_END); i += 3) {
+ if ((addr >= address_data->normal_isa_range[i]) &&
+ (addr <= address_data->normal_isa_range[i + 1]) &&
+ ((addr - address_data->normal_isa_range[i]) % address_data->normal_isa_range[i + 2] == 0)) {
+ dev_dbg(&adapter->dev, "found normal isa_range entry for adapter %d, addr %04x", adapter_id, addr);
+ found = 1;
+ }
+ }
+ } else {
+ for (i = 0; !found && (address_data->normal_i2c[i] != I2C_CLIENT_END); i += 1) {
+ if (addr == address_data->normal_i2c[i]) {
+ found = 1;
+ dev_dbg(&adapter->dev, "found normal i2c entry for adapter %d, addr %02x", adapter_id, addr);
+ }
+ }
+ for (i = 0; !found && (address_data->normal_i2c_range[i] != I2C_CLIENT_END); i += 2) {
+ if ((addr >= address_data->normal_i2c_range[i]) &&
+ (addr <= address_data->normal_i2c_range[i + 1])) {
+ dev_dbg(&adapter->dev, "found normal i2c_range entry for adapter %d, addr %04x\n", adapter_id, addr);
+ found = 1;
+ }
+ }
+ }
+
+ for (i = 0;
+ !found && (address_data->probe[i] != I2C_CLIENT_END);
+ i += 2) {
+ if (((adapter_id == address_data->probe[i]) ||
+ ((address_data->
+ probe[i] == ANY_I2C_BUS) && !is_isa))
+ && (addr == address_data->probe[i + 1])) {
+ dev_dbg(&adapter->dev, "found probe parameter for adapter %d, addr %04x\n", adapter_id, addr);
+ found = 1;
+ }
+ }
+ for (i = 0; !found && (address_data->probe_range[i] != I2C_CLIENT_END); i += 3) {
+ if ( ((adapter_id == address_data->probe_range[i]) ||
+ ((address_data->probe_range[i] == ANY_I2C_BUS) && !is_isa)) &&
+ (addr >= address_data->probe_range[i + 1]) &&
+ (addr <= address_data->probe_range[i + 2])) {
+ found = 1;
+ dev_dbg(&adapter->dev, "found probe_range parameter for adapter %d, addr %04x\n", adapter_id, addr);
+ }
+ }
+ if (!found)
+ continue;
+
+ /* OK, so we really should examine this address. First check
+ whether there is some client here at all! */
+ if (is_isa ||
+ (i2c_smbus_xfer (adapter, addr, 0, 0, 0, I2C_SMBUS_QUICK, NULL) >= 0))
+ if ((err = found_proc(adapter, addr, -1)))
+ return err;
+ }
+ return 0;
+}
+
+EXPORT_SYMBOL(i2c_detect);
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
+ "Rudolf Marek <r.marek@sh.cvut.cz>");
+
+MODULE_DESCRIPTION("i2c-sensor driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ i2c-sensor-vid.c - Part of lm_sensors, Linux kernel modules for hardware
+ monitoring
+
+ Copyright (c) 2004 Rudolf Marek <r.marek@sh.cvut.cz>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+
+struct vrm_model {
+ u8 vendor;
+ u8 eff_family;
+ u8 eff_model;
+ int vrm_type;
+};
+
+#define ANY 0xFF
+
+#ifdef CONFIG_X86
+
+static struct vrm_model vrm_models[] = {
+ {X86_VENDOR_AMD, 0x6, ANY, 90}, /* Athlon Duron etc */
+ {X86_VENDOR_AMD, 0xF, 0x4, 90}, /* Athlon 64 */
+ {X86_VENDOR_AMD, 0xF, 0x5, 24}, /* Opteron */
+ {X86_VENDOR_INTEL, 0x6, 0x9, 85}, /* 0.13um too */
+ {X86_VENDOR_INTEL, 0x6, 0xB, 85}, /* 0xB Tualatin */
+ {X86_VENDOR_INTEL, 0x6, ANY, 82}, /* any P6 */
+ {X86_VENDOR_INTEL, 0x7, ANY, 0}, /* Itanium */
+ {X86_VENDOR_INTEL, 0xF, 0x3, 100}, /* P4 Prescott */
+ {X86_VENDOR_INTEL, 0xF, ANY, 90}, /* P4 before Prescott */
+ {X86_VENDOR_INTEL, 0x10,ANY, 0}, /* Itanium 2 */
+ {X86_VENDOR_UNKNOWN, ANY, ANY, 0} /* stop here */
+ };
+
+static int find_vrm(u8 eff_family, u8 eff_model, u8 vendor)
+{
+ int i = 0;
+
+ while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
+ if (vrm_models[i].vendor==vendor)
+ if ((vrm_models[i].eff_family==eff_family)&& \
+ ((vrm_models[i].eff_model==eff_model)|| \
+ (vrm_models[i].eff_model==ANY)))
+ return vrm_models[i].vrm_type;
+ i++;
+ }
+
+ return 0;
+}
+
+int i2c_which_vrm(void)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+ u32 eax;
+ u8 eff_family, eff_model;
+ int vrm_ret;
+
+ if (c->x86 < 6) return 0; /* any CPU with familly lower than 6
+ dont have VID and/or CPUID */
+ eax = cpuid_eax(1);
+ eff_family = ((eax & 0x00000F00)>>8);
+ eff_model = ((eax & 0x000000F0)>>4);
+ if (eff_family == 0xF) { /* use extended model & family */
+ eff_family += ((eax & 0x00F00000)>>20);
+ eff_model += ((eax & 0x000F0000)>>16)<<4;
+ }
+ vrm_ret = find_vrm(eff_family,eff_model,c->x86_vendor);
+ if (vrm_ret == 0)
+ printk(KERN_INFO "i2c-sensor.o: Unknown VRM version of your"
+ " x86 CPU\n");
+ return vrm_ret;
+}
+
+/* and now something completely different for Non-x86 world*/
+#else
+int i2c_which_vrm(void)
+{
+ printk(KERN_INFO "i2c-sensor.o: Unknown VRM version of your CPU\n");
+ return 0;
+}
+#endif
+
+EXPORT_SYMBOL(i2c_which_vrm);
--- /dev/null
+/* linux/drivers/ide/arm/bast-ide.c
+ *
+ * Copyright (c) 2003-2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/ide.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/arch/map.h>
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-irq.h>
+
+/* list of registered interfaces */
+static ide_hwif_t *ifs[2];
+
+static int __init
+bastide_register(unsigned int base, unsigned int aux, int irq,
+ ide_hwif_t **hwif)
+{
+ hw_regs_t hw;
+ int i;
+
+ memset(&hw, 0, sizeof(hw));
+
+ base += BAST_IDE_CS;
+ aux += BAST_IDE_CS;
+
+ for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+ hw.io_ports[i] = (unsigned long)base;
+ base += 0x20;
+ }
+
+ hw.io_ports[IDE_CONTROL_OFFSET] = aux + (6 * 0x20);
+ hw.irq = irq;
+
+ ide_register_hw(&hw, hwif);
+
+ return 0;
+}
+
+static int __init bastide_init(void)
+{
+ /* we can treat the VR1000 and the BAST the same */
+
+ if (!(machine_is_bast() || machine_is_vr1000()))
+ return 0;
+
+ printk("BAST: IDE driver, (c) 2003-2004 Simtec Electronics\n");
+
+ bastide_register(BAST_VA_IDEPRI, BAST_VA_IDEPRIAUX, IRQ_IDE0, &ifs[0]);
+ bastide_register(BAST_VA_IDESEC, BAST_VA_IDESECAUX, IRQ_IDE1, &ifs[1]);
+ return 0;
+}
+
+module_init(bastide_init);
+
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Simtec BAST / Thorcom VR1000 IDE driver");
--- /dev/null
+/*
+ * Raw serio device providing access to a raw byte stream from underlying
+ * serio port. Closely emulates behavior of pre-2.6 /dev/psaux device
+ *
+ * Copyright (c) 2004 Dmitry Torokhov
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/module.h>
+#include <linux/serio.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/device.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/miscdevice.h>
+#include <linux/wait.h>
+
+#define DRIVER_DESC "Raw serio driver"
+
+MODULE_AUTHOR("Dmitry Torokhov <dtor@mail.ru>");
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
+
+#define SERIO_RAW_QUEUE_LEN 64
+struct serio_raw {
+ unsigned char queue[SERIO_RAW_QUEUE_LEN];
+ unsigned int tail, head;
+
+ char name[16];
+ unsigned int refcnt;
+ struct serio *serio;
+ struct miscdevice dev;
+ wait_queue_head_t wait;
+ struct list_head list;
+ struct list_head node;
+};
+
+struct serio_raw_list {
+ struct fasync_struct *fasync;
+ struct serio_raw *serio_raw;
+ struct list_head node;
+};
+
+static DECLARE_MUTEX(serio_raw_sem);
+static LIST_HEAD(serio_raw_list);
+static unsigned int serio_raw_no;
+
+/*********************************************************************
+ * Interface with userspace (file operations) *
+ *********************************************************************/
+
+static int serio_raw_fasync(int fd, struct file *file, int on)
+{
+ struct serio_raw_list *list = file->private_data;
+ int retval;
+
+ retval = fasync_helper(fd, file, on, &list->fasync);
+ return retval < 0 ? retval : 0;
+}
+
+static struct serio_raw *serio_raw_locate(int minor)
+{
+ struct serio_raw *serio_raw;
+
+ list_for_each_entry(serio_raw, &serio_raw_list, node) {
+ if (serio_raw->dev.minor == minor)
+ return serio_raw;
+ }
+
+ return NULL;
+}
+
+static int serio_raw_open(struct inode *inode, struct file *file)
+{
+ struct serio_raw *serio_raw;
+ struct serio_raw_list *list;
+ int retval = 0;
+
+ retval = down_interruptible(&serio_raw_sem);
+ if (retval)
+ return retval;
+
+ if (!(serio_raw = serio_raw_locate(iminor(inode)))) {
+ retval = -ENODEV;
+ goto out;
+ }
+
+ if (!serio_raw->serio) {
+ retval = -ENODEV;
+ goto out;
+ }
+
+ if (!(list = kmalloc(sizeof(struct serio_raw_list), GFP_KERNEL))) {
+ retval = -ENOMEM;
+ goto out;
+ }
+
+ memset(list, 0, sizeof(struct serio_raw_list));
+ list->serio_raw = serio_raw;
+ file->private_data = list;
+
+ serio_raw->refcnt++;
+ list_add_tail(&list->node, &serio_raw->list);
+
+out:
+ up(&serio_raw_sem);
+ return retval;
+}
+
+static int serio_raw_cleanup(struct serio_raw *serio_raw)
+{
+ if (--serio_raw->refcnt == 0) {
+ misc_deregister(&serio_raw->dev);
+ list_del_init(&serio_raw->node);
+ kfree(serio_raw);
+
+ return 1;
+ }
+
+ return 0;
+}
+
+static int serio_raw_release(struct inode *inode, struct file *file)
+{
+ struct serio_raw_list *list = file->private_data;
+ struct serio_raw *serio_raw = list->serio_raw;
+
+ down(&serio_raw_sem);
+
+ serio_raw_fasync(-1, file, 0);
+ serio_raw_cleanup(serio_raw);
+
+ up(&serio_raw_sem);
+ return 0;
+}
+
+static int serio_raw_fetch_byte(struct serio_raw *serio_raw, char *c)
+{
+ unsigned long flags;
+ int empty;
+
+ spin_lock_irqsave(&serio_raw->serio->lock, flags);
+
+ empty = serio_raw->head == serio_raw->tail;
+ if (!empty) {
+ *c = serio_raw->queue[serio_raw->tail];
+ serio_raw->tail = (serio_raw->tail + 1) % SERIO_RAW_QUEUE_LEN;
+ }
+
+ spin_unlock_irqrestore(&serio_raw->serio->lock, flags);
+
+ return !empty;
+}
+
+static ssize_t serio_raw_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
+{
+ struct serio_raw_list *list = file->private_data;
+ struct serio_raw *serio_raw = list->serio_raw;
+ char c;
+ ssize_t retval = 0;
+
+ if (!serio_raw->serio)
+ return -ENODEV;
+
+ if (serio_raw->head == serio_raw->tail && (file->f_flags & O_NONBLOCK))
+ return -EAGAIN;
+
+ retval = wait_event_interruptible(list->serio_raw->wait,
+ serio_raw->head != serio_raw->tail || !serio_raw->serio);
+ if (retval)
+ return retval;
+
+ if (!serio_raw->serio)
+ return -ENODEV;
+
+ while (retval < count && serio_raw_fetch_byte(serio_raw, &c)) {
+ if (put_user(c, buffer++))
+ return -EFAULT;
+ retval++;
+ }
+
+ return retval;
+}
+
+static ssize_t serio_raw_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
+{
+ struct serio_raw_list *list = file->private_data;
+ ssize_t written = 0;
+ int retval;
+ unsigned char c;
+
+ retval = down_interruptible(&serio_raw_sem);
+ if (retval)
+ return retval;
+
+ if (!list->serio_raw->serio) {
+ retval = -ENODEV;
+ goto out;
+ }
+
+ if (count > 32)
+ count = 32;
+
+ while (count--) {
+ if (get_user(c, buffer++)) {
+ retval = -EFAULT;
+ goto out;
+ }
+ if (serio_write(list->serio_raw->serio, c)) {
+ retval = -EIO;
+ goto out;
+ }
+ written++;
+ };
+
+out:
+ up(&serio_raw_sem);
+ return written;
+}
+
+static unsigned int serio_raw_poll(struct file *file, poll_table *wait)
+{
+ struct serio_raw_list *list = file->private_data;
+
+ poll_wait(file, &list->serio_raw->wait, wait);
+
+ if (list->serio_raw->head != list->serio_raw->tail)
+ return POLLIN | POLLRDNORM;
+
+ return 0;
+}
+
+struct file_operations serio_raw_fops = {
+ .owner = THIS_MODULE,
+ .open = serio_raw_open,
+ .release = serio_raw_release,
+ .read = serio_raw_read,
+ .write = serio_raw_write,
+ .poll = serio_raw_poll,
+ .fasync = serio_raw_fasync,
+};
+
+
+/*********************************************************************
+ * Interface with serio port *
+ *********************************************************************/
+
+static irqreturn_t serio_raw_interrupt(struct serio *serio, unsigned char data,
+ unsigned int dfl, struct pt_regs *regs)
+{
+ struct serio_raw *serio_raw = serio->private;
+ struct serio_raw_list *list;
+ unsigned int head = serio_raw->head;
+
+ /* we are holding serio->lock here so we are prootected */
+ serio_raw->queue[head] = data;
+ head = (head + 1) % SERIO_RAW_QUEUE_LEN;
+ if (likely(head != serio_raw->tail)) {
+ serio_raw->head = head;
+ list_for_each_entry(list, &serio_raw->list, node)
+ kill_fasync(&list->fasync, SIGIO, POLL_IN);
+ wake_up_interruptible(&serio_raw->wait);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void serio_raw_connect(struct serio *serio, struct serio_driver *drv)
+{
+ struct serio_raw *serio_raw;
+ int err;
+
+ if ((serio->type & SERIO_TYPE) != SERIO_8042)
+ return;
+
+ if (!(serio_raw = kmalloc(sizeof(struct serio_raw), GFP_KERNEL))) {
+ printk(KERN_ERR "serio_raw.c: can't allocate memory for a device\n");
+ return;
+ }
+
+ down(&serio_raw_sem);
+
+ memset(serio_raw, 0, sizeof(struct serio_raw));
+ snprintf(serio_raw->name, sizeof(serio_raw->name), "serio_raw%d", serio_raw_no++);
+ serio_raw->refcnt = 1;
+ serio_raw->serio = serio;
+ INIT_LIST_HEAD(&serio_raw->list);
+ init_waitqueue_head(&serio_raw->wait);
+
+ serio->private = serio_raw;
+ if (serio_open(serio, drv))
+ goto out_free;
+
+ list_add_tail(&serio_raw->node, &serio_raw_list);
+
+ serio_raw->dev.minor = PSMOUSE_MINOR;
+ serio_raw->dev.name = serio_raw->name;
+ serio_raw->dev.fops = &serio_raw_fops;
+
+ err = misc_register(&serio_raw->dev);
+ if (err) {
+ serio_raw->dev.minor = MISC_DYNAMIC_MINOR;
+ err = misc_register(&serio_raw->dev);
+ }
+
+ if (err) {
+ printk(KERN_INFO "serio_raw: failed to register raw access device for %s\n",
+ serio->phys);
+ goto out_close;
+ }
+
+ printk(KERN_INFO "serio_raw: raw access enabled on %s (%s, minor %d)\n",
+ serio->phys, serio_raw->name, serio_raw->dev.minor);
+ goto out;
+
+out_close:
+ serio_close(serio);
+ list_del_init(&serio_raw->node);
+out_free:
+ serio->private = NULL;
+ kfree(serio_raw);
+out:
+ up(&serio_raw_sem);
+}
+
+static int serio_raw_reconnect(struct serio *serio)
+{
+ struct serio_raw *serio_raw = serio->private;
+ struct serio_driver *drv = serio->drv;
+
+ if (!drv || !serio_raw) {
+ printk(KERN_DEBUG "serio_raw: reconnect request, but serio is disconnected, ignoring...\n");
+ return -1;
+ }
+
+ /*
+ * Nothing needs to be done here, we just need this method to
+ * keep the same device.
+ */
+ return 0;
+}
+
+static void serio_raw_disconnect(struct serio *serio)
+{
+ struct serio_raw *serio_raw;
+
+ down(&serio_raw_sem);
+
+ serio_raw = serio->private;
+
+ serio_close(serio);
+ serio->private = NULL;
+
+ serio_raw->serio = NULL;
+ if (!serio_raw_cleanup(serio_raw))
+ wake_up_interruptible(&serio_raw->wait);
+
+ up(&serio_raw_sem);
+}
+
+static struct serio_driver serio_raw_drv = {
+ .driver = {
+ .name = "serio_raw",
+ },
+ .description = DRIVER_DESC,
+ .interrupt = serio_raw_interrupt,
+ .connect = serio_raw_connect,
+ .reconnect = serio_raw_reconnect,
+ .disconnect = serio_raw_disconnect,
+ .manual_bind = 1,
+};
+
+int __init serio_raw_init(void)
+{
+ serio_register_driver(&serio_raw_drv);
+ return 0;
+}
+
+void __exit serio_raw_exit(void)
+{
+ serio_unregister_driver(&serio_raw_drv);
+}
+
+module_init(serio_raw_init);
+module_exit(serio_raw_exit);
--- /dev/null
+/*
+ * raid10.c : Multiple Devices driver for Linux
+ *
+ * Copyright (C) 2000-2004 Neil Brown
+ *
+ * RAID-10 support for md.
+ *
+ * Base on code in raid1.c. See raid1.c for futher copyright information.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/raid/raid10.h>
+
+/*
+ * RAID10 provides a combination of RAID0 and RAID1 functionality.
+ * The layout of data is defined by
+ * chunk_size
+ * raid_disks
+ * near_copies (stored in low byte of layout)
+ * far_copies (stored in second byte of layout)
+ *
+ * The data to be stored is divided into chunks using chunksize.
+ * Each device is divided into far_copies sections.
+ * In each section, chunks are laid out in a style similar to raid0, but
+ * near_copies copies of each chunk is stored (each on a different drive).
+ * The starting device for each section is offset near_copies from the starting
+ * device of the previous section.
+ * Thus there are (near_copies*far_copies) of each chunk, and each is on a different
+ * drive.
+ * near_copies and far_copies must be at least one, and there product is at most
+ * raid_disks.
+ */
+
+/*
+ * Number of guaranteed r10bios in case of extreme VM load:
+ */
+#define NR_RAID10_BIOS 256
+
+static void unplug_slaves(mddev_t *mddev);
+
+static void * r10bio_pool_alloc(int gfp_flags, void *data)
+{
+ conf_t *conf = data;
+ r10bio_t *r10_bio;
+ int size = offsetof(struct r10bio_s, devs[conf->copies]);
+
+ /* allocate a r10bio with room for raid_disks entries in the bios array */
+ r10_bio = kmalloc(size, gfp_flags);
+ if (r10_bio)
+ memset(r10_bio, 0, size);
+ else
+ unplug_slaves(conf->mddev);
+
+ return r10_bio;
+}
+
+static void r10bio_pool_free(void *r10_bio, void *data)
+{
+ kfree(r10_bio);
+}
+
+#define RESYNC_BLOCK_SIZE (64*1024)
+//#define RESYNC_BLOCK_SIZE PAGE_SIZE
+#define RESYNC_SECTORS (RESYNC_BLOCK_SIZE >> 9)
+#define RESYNC_PAGES ((RESYNC_BLOCK_SIZE + PAGE_SIZE-1) / PAGE_SIZE)
+#define RESYNC_WINDOW (2048*1024)
+
+/*
+ * When performing a resync, we need to read and compare, so
+ * we need as many pages are there are copies.
+ * When performing a recovery, we need 2 bios, one for read,
+ * one for write (we recover only one drive per r10buf)
+ *
+ */
+static void * r10buf_pool_alloc(int gfp_flags, void *data)
+{
+ conf_t *conf = data;
+ struct page *page;
+ r10bio_t *r10_bio;
+ struct bio *bio;
+ int i, j;
+ int nalloc;
+
+ r10_bio = r10bio_pool_alloc(gfp_flags, conf);
+ if (!r10_bio) {
+ unplug_slaves(conf->mddev);
+ return NULL;
+ }
+
+ if (test_bit(MD_RECOVERY_SYNC, &conf->mddev->recovery))
+ nalloc = conf->copies; /* resync */
+ else
+ nalloc = 2; /* recovery */
+
+ /*
+ * Allocate bios.
+ */
+ for (j = nalloc ; j-- ; ) {
+ bio = bio_alloc(gfp_flags, RESYNC_PAGES);
+ if (!bio)
+ goto out_free_bio;
+ r10_bio->devs[j].bio = bio;
+ }
+ /*
+ * Allocate RESYNC_PAGES data pages and attach them
+ * where needed.
+ */
+ for (j = 0 ; j < nalloc; j++) {
+ bio = r10_bio->devs[j].bio;
+ for (i = 0; i < RESYNC_PAGES; i++) {
+ page = alloc_page(gfp_flags);
+ if (unlikely(!page))
+ goto out_free_pages;
+
+ bio->bi_io_vec[i].bv_page = page;
+ }
+ }
+
+ return r10_bio;
+
+out_free_pages:
+ for ( ; i > 0 ; i--)
+ __free_page(bio->bi_io_vec[i-1].bv_page);
+ while (j--)
+ for (i = 0; i < RESYNC_PAGES ; i++)
+ __free_page(r10_bio->devs[j].bio->bi_io_vec[i].bv_page);
+ j = -1;
+out_free_bio:
+ while ( ++j < nalloc )
+ bio_put(r10_bio->devs[j].bio);
+ r10bio_pool_free(r10_bio, conf);
+ return NULL;
+}
+
+static void r10buf_pool_free(void *__r10_bio, void *data)
+{
+ int i;
+ conf_t *conf = data;
+ r10bio_t *r10bio = __r10_bio;
+ int j;
+
+ for (j=0; j < conf->copies; j++) {
+ struct bio *bio = r10bio->devs[j].bio;
+ if (bio) {
+ for (i = 0; i < RESYNC_PAGES; i++) {
+ __free_page(bio->bi_io_vec[i].bv_page);
+ bio->bi_io_vec[i].bv_page = NULL;
+ }
+ bio_put(bio);
+ }
+ }
+ r10bio_pool_free(r10bio, conf);
+}
+
+static void put_all_bios(conf_t *conf, r10bio_t *r10_bio)
+{
+ int i;
+
+ for (i = 0; i < conf->copies; i++) {
+ struct bio **bio = & r10_bio->devs[i].bio;
+ if (*bio)
+ bio_put(*bio);
+ *bio = NULL;
+ }
+}
+
+static inline void free_r10bio(r10bio_t *r10_bio)
+{
+ unsigned long flags;
+
+ conf_t *conf = mddev_to_conf(r10_bio->mddev);
+
+ /*
+ * Wake up any possible resync thread that waits for the device
+ * to go idle.
+ */
+ spin_lock_irqsave(&conf->resync_lock, flags);
+ if (!--conf->nr_pending) {
+ wake_up(&conf->wait_idle);
+ wake_up(&conf->wait_resume);
+ }
+ spin_unlock_irqrestore(&conf->resync_lock, flags);
+
+ put_all_bios(conf, r10_bio);
+ mempool_free(r10_bio, conf->r10bio_pool);
+}
+
+static inline void put_buf(r10bio_t *r10_bio)
+{
+ conf_t *conf = mddev_to_conf(r10_bio->mddev);
+ unsigned long flags;
+
+ mempool_free(r10_bio, conf->r10buf_pool);
+
+ spin_lock_irqsave(&conf->resync_lock, flags);
+ if (!conf->barrier)
+ BUG();
+ --conf->barrier;
+ wake_up(&conf->wait_resume);
+ wake_up(&conf->wait_idle);
+
+ if (!--conf->nr_pending) {
+ wake_up(&conf->wait_idle);
+ wake_up(&conf->wait_resume);
+ }
+ spin_unlock_irqrestore(&conf->resync_lock, flags);
+}
+
+static void reschedule_retry(r10bio_t *r10_bio)
+{
+ unsigned long flags;
+ mddev_t *mddev = r10_bio->mddev;
+ conf_t *conf = mddev_to_conf(mddev);
+
+ spin_lock_irqsave(&conf->device_lock, flags);
+ list_add(&r10_bio->retry_list, &conf->retry_list);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+
+ md_wakeup_thread(mddev->thread);
+}
+
+/*
+ * raid_end_bio_io() is called when we have finished servicing a mirrored
+ * operation and are ready to return a success/failure code to the buffer
+ * cache layer.
+ */
+static void raid_end_bio_io(r10bio_t *r10_bio)
+{
+ struct bio *bio = r10_bio->master_bio;
+
+ bio_endio(bio, bio->bi_size,
+ test_bit(R10BIO_Uptodate, &r10_bio->state) ? 0 : -EIO);
+ free_r10bio(r10_bio);
+}
+
+/*
+ * Update disk head position estimator based on IRQ completion info.
+ */
+static inline void update_head_pos(int slot, r10bio_t *r10_bio)
+{
+ conf_t *conf = mddev_to_conf(r10_bio->mddev);
+
+ conf->mirrors[r10_bio->devs[slot].devnum].head_position =
+ r10_bio->devs[slot].addr + (r10_bio->sectors);
+}
+
+static int raid10_end_read_request(struct bio *bio, unsigned int bytes_done, int error)
+{
+ int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
+ r10bio_t * r10_bio = (r10bio_t *)(bio->bi_private);
+ int slot, dev;
+ conf_t *conf = mddev_to_conf(r10_bio->mddev);
+
+ if (bio->bi_size)
+ return 1;
+
+ slot = r10_bio->read_slot;
+ dev = r10_bio->devs[slot].devnum;
+ /*
+ * this branch is our 'one mirror IO has finished' event handler:
+ */
+ if (!uptodate)
+ md_error(r10_bio->mddev, conf->mirrors[dev].rdev);
+ else
+ /*
+ * Set R10BIO_Uptodate in our master bio, so that
+ * we will return a good error code to the higher
+ * levels even if IO on some other mirrored buffer fails.
+ *
+ * The 'master' represents the composite IO operation to
+ * user-side. So if something waits for IO, then it will
+ * wait for the 'master' bio.
+ */
+ set_bit(R10BIO_Uptodate, &r10_bio->state);
+
+ update_head_pos(slot, r10_bio);
+
+ /*
+ * we have only one bio on the read side
+ */
+ if (uptodate)
+ raid_end_bio_io(r10_bio);
+ else {
+ /*
+ * oops, read error:
+ */
+ char b[BDEVNAME_SIZE];
+ if (printk_ratelimit())
+ printk(KERN_ERR "raid10: %s: rescheduling sector %llu\n",
+ bdevname(conf->mirrors[dev].rdev->bdev,b), (unsigned long long)r10_bio->sector);
+ reschedule_retry(r10_bio);
+ }
+
+ rdev_dec_pending(conf->mirrors[dev].rdev, conf->mddev);
+ return 0;
+}
+
+static int raid10_end_write_request(struct bio *bio, unsigned int bytes_done, int error)
+{
+ int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
+ r10bio_t * r10_bio = (r10bio_t *)(bio->bi_private);
+ int slot, dev;
+ conf_t *conf = mddev_to_conf(r10_bio->mddev);
+
+ if (bio->bi_size)
+ return 1;
+
+ for (slot = 0; slot < conf->copies; slot++)
+ if (r10_bio->devs[slot].bio == bio)
+ break;
+ dev = r10_bio->devs[slot].devnum;
+
+ /*
+ * this branch is our 'one mirror IO has finished' event handler:
+ */
+ if (!uptodate)
+ md_error(r10_bio->mddev, conf->mirrors[dev].rdev);
+ else
+ /*
+ * Set R10BIO_Uptodate in our master bio, so that
+ * we will return a good error code for to the higher
+ * levels even if IO on some other mirrored buffer fails.
+ *
+ * The 'master' represents the composite IO operation to
+ * user-side. So if something waits for IO, then it will
+ * wait for the 'master' bio.
+ */
+ set_bit(R10BIO_Uptodate, &r10_bio->state);
+
+ update_head_pos(slot, r10_bio);
+
+ /*
+ *
+ * Let's see if all mirrored write operations have finished
+ * already.
+ */
+ if (atomic_dec_and_test(&r10_bio->remaining)) {
+ md_write_end(r10_bio->mddev);
+ raid_end_bio_io(r10_bio);
+ }
+
+ rdev_dec_pending(conf->mirrors[dev].rdev, conf->mddev);
+ return 0;
+}
+
+
+/*
+ * RAID10 layout manager
+ * Aswell as the chunksize and raid_disks count, there are two
+ * parameters: near_copies and far_copies.
+ * near_copies * far_copies must be <= raid_disks.
+ * Normally one of these will be 1.
+ * If both are 1, we get raid0.
+ * If near_copies == raid_disks, we get raid1.
+ *
+ * Chunks are layed out in raid0 style with near_copies copies of the
+ * first chunk, followed by near_copies copies of the next chunk and
+ * so on.
+ * If far_copies > 1, then after 1/far_copies of the array has been assigned
+ * as described above, we start again with a device offset of near_copies.
+ * So we effectively have another copy of the whole array further down all
+ * the drives, but with blocks on different drives.
+ * With this layout, and block is never stored twice on the one device.
+ *
+ * raid10_find_phys finds the sector offset of a given virtual sector
+ * on each device that it is on. If a block isn't on a device,
+ * that entry in the array is set to MaxSector.
+ *
+ * raid10_find_virt does the reverse mapping, from a device and a
+ * sector offset to a virtual address
+ */
+
+static void raid10_find_phys(conf_t *conf, r10bio_t *r10bio)
+{
+ int n,f;
+ sector_t sector;
+ sector_t chunk;
+ sector_t stripe;
+ int dev;
+
+ int slot = 0;
+
+ /* now calculate first sector/dev */
+ chunk = r10bio->sector >> conf->chunk_shift;
+ sector = r10bio->sector & conf->chunk_mask;
+
+ chunk *= conf->near_copies;
+ stripe = chunk;
+ dev = sector_div(stripe, conf->raid_disks);
+
+ sector += stripe << conf->chunk_shift;
+
+ /* and calculate all the others */
+ for (n=0; n < conf->near_copies; n++) {
+ int d = dev;
+ sector_t s = sector;
+ r10bio->devs[slot].addr = sector;
+ r10bio->devs[slot].devnum = d;
+ slot++;
+
+ for (f = 1; f < conf->far_copies; f++) {
+ d += conf->near_copies;
+ if (d >= conf->raid_disks)
+ d -= conf->raid_disks;
+ s += conf->stride;
+ r10bio->devs[slot].devnum = d;
+ r10bio->devs[slot].addr = s;
+ slot++;
+ }
+ dev++;
+ if (dev >= conf->raid_disks) {
+ dev = 0;
+ sector += (conf->chunk_mask + 1);
+ }
+ }
+ BUG_ON(slot != conf->copies);
+}
+
+static sector_t raid10_find_virt(conf_t *conf, sector_t sector, int dev)
+{
+ sector_t offset, chunk, vchunk;
+
+ while (sector > conf->stride) {
+ sector -= conf->stride;
+ if (dev < conf->near_copies)
+ dev += conf->raid_disks - conf->near_copies;
+ else
+ dev -= conf->near_copies;
+ }
+
+ offset = sector & conf->chunk_mask;
+ chunk = sector >> conf->chunk_shift;
+ vchunk = chunk * conf->raid_disks + dev;
+ sector_div(vchunk, conf->near_copies);
+ return (vchunk << conf->chunk_shift) + offset;
+}
+
+/**
+ * raid10_mergeable_bvec -- tell bio layer if a two requests can be merged
+ * @q: request queue
+ * @bio: the buffer head that's been built up so far
+ * @biovec: the request that could be merged to it.
+ *
+ * Return amount of bytes we can accept at this offset
+ * If near_copies == raid_disk, there are no striping issues,
+ * but in that case, the function isn't called at all.
+ */
+static int raid10_mergeable_bvec(request_queue_t *q, struct bio *bio,
+ struct bio_vec *bio_vec)
+{
+ mddev_t *mddev = q->queuedata;
+ sector_t sector = bio->bi_sector + get_start_sect(bio->bi_bdev);
+ int max;
+ unsigned int chunk_sectors = mddev->chunk_size >> 9;
+ unsigned int bio_sectors = bio->bi_size >> 9;
+
+ max = (chunk_sectors - ((sector & (chunk_sectors - 1)) + bio_sectors)) << 9;
+ if (max < 0) max = 0; /* bio_add cannot handle a negative return */
+ if (max <= bio_vec->bv_len && bio_sectors == 0)
+ return bio_vec->bv_len;
+ else
+ return max;
+}
+
+/*
+ * This routine returns the disk from which the requested read should
+ * be done. There is a per-array 'next expected sequential IO' sector
+ * number - if this matches on the next IO then we use the last disk.
+ * There is also a per-disk 'last know head position' sector that is
+ * maintained from IRQ contexts, both the normal and the resync IO
+ * completion handlers update this position correctly. If there is no
+ * perfect sequential match then we pick the disk whose head is closest.
+ *
+ * If there are 2 mirrors in the same 2 devices, performance degrades
+ * because position is mirror, not device based.
+ *
+ * The rdev for the device selected will have nr_pending incremented.
+ */
+
+/*
+ * FIXME: possibly should rethink readbalancing and do it differently
+ * depending on near_copies / far_copies geometry.
+ */
+static int read_balance(conf_t *conf, r10bio_t *r10_bio)
+{
+ const unsigned long this_sector = r10_bio->sector;
+ int disk, slot, nslot;
+ const int sectors = r10_bio->sectors;
+ sector_t new_distance, current_distance;
+
+ raid10_find_phys(conf, r10_bio);
+ spin_lock_irq(&conf->device_lock);
+ /*
+ * Check if we can balance. We can balance on the whole
+ * device if no resync is going on, or below the resync window.
+ * We take the first readable disk when above the resync window.
+ */
+ if (conf->mddev->recovery_cp < MaxSector
+ && (this_sector + sectors >= conf->next_resync)) {
+ /* make sure that disk is operational */
+ slot = 0;
+ disk = r10_bio->devs[slot].devnum;
+
+ while (!conf->mirrors[disk].rdev ||
+ !conf->mirrors[disk].rdev->in_sync) {
+ slot++;
+ if (slot == conf->copies) {
+ slot = 0;
+ disk = -1;
+ break;
+ }
+ disk = r10_bio->devs[slot].devnum;
+ }
+ goto rb_out;
+ }
+
+
+ /* make sure the disk is operational */
+ slot = 0;
+ disk = r10_bio->devs[slot].devnum;
+ while (!conf->mirrors[disk].rdev ||
+ !conf->mirrors[disk].rdev->in_sync) {
+ slot ++;
+ if (slot == conf->copies) {
+ disk = -1;
+ goto rb_out;
+ }
+ disk = r10_bio->devs[slot].devnum;
+ }
+
+
+ current_distance = abs(this_sector - conf->mirrors[disk].head_position);
+
+ /* Find the disk whose head is closest */
+
+ for (nslot = slot; nslot < conf->copies; nslot++) {
+ int ndisk = r10_bio->devs[nslot].devnum;
+
+
+ if (!conf->mirrors[ndisk].rdev ||
+ !conf->mirrors[ndisk].rdev->in_sync)
+ continue;
+
+ if (!atomic_read(&conf->mirrors[ndisk].rdev->nr_pending)) {
+ disk = ndisk;
+ slot = nslot;
+ break;
+ }
+ new_distance = abs(r10_bio->devs[nslot].addr -
+ conf->mirrors[ndisk].head_position);
+ if (new_distance < current_distance) {
+ current_distance = new_distance;
+ disk = ndisk;
+ slot = nslot;
+ }
+ }
+
+rb_out:
+ r10_bio->read_slot = slot;
+/* conf->next_seq_sect = this_sector + sectors;*/
+
+ if (disk >= 0 && conf->mirrors[disk].rdev)
+ atomic_inc(&conf->mirrors[disk].rdev->nr_pending);
+ spin_unlock_irq(&conf->device_lock);
+
+ return disk;
+}
+
+static void unplug_slaves(mddev_t *mddev)
+{
+ conf_t *conf = mddev_to_conf(mddev);
+ int i;
+ unsigned long flags;
+
+ spin_lock_irqsave(&conf->device_lock, flags);
+ for (i=0; i<mddev->raid_disks; i++) {
+ mdk_rdev_t *rdev = conf->mirrors[i].rdev;
+ if (rdev && atomic_read(&rdev->nr_pending)) {
+ request_queue_t *r_queue = bdev_get_queue(rdev->bdev);
+
+ atomic_inc(&rdev->nr_pending);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+
+ if (r_queue->unplug_fn)
+ r_queue->unplug_fn(r_queue);
+
+ spin_lock_irqsave(&conf->device_lock, flags);
+ atomic_dec(&rdev->nr_pending);
+ }
+ }
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+}
+static void raid10_unplug(request_queue_t *q)
+{
+ unplug_slaves(q->queuedata);
+}
+
+static int raid10_issue_flush(request_queue_t *q, struct gendisk *disk,
+ sector_t *error_sector)
+{
+ mddev_t *mddev = q->queuedata;
+ conf_t *conf = mddev_to_conf(mddev);
+ unsigned long flags;
+ int i, ret = 0;
+
+ spin_lock_irqsave(&conf->device_lock, flags);
+ for (i=0; i<mddev->raid_disks; i++) {
+ mdk_rdev_t *rdev = conf->mirrors[i].rdev;
+ if (rdev && !rdev->faulty) {
+ struct block_device *bdev = rdev->bdev;
+ request_queue_t *r_queue = bdev_get_queue(bdev);
+
+ if (r_queue->issue_flush_fn) {
+ ret = r_queue->issue_flush_fn(r_queue, bdev->bd_disk, error_sector);
+ if (ret)
+ break;
+ }
+ }
+ }
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+ return ret;
+}
+
+/*
+ * Throttle resync depth, so that we can both get proper overlapping of
+ * requests, but are still able to handle normal requests quickly.
+ */
+#define RESYNC_DEPTH 32
+
+static void device_barrier(conf_t *conf, sector_t sect)
+{
+ spin_lock_irq(&conf->resync_lock);
+ wait_event_lock_irq(conf->wait_idle, !waitqueue_active(&conf->wait_resume),
+ conf->resync_lock, unplug_slaves(conf->mddev));
+
+ if (!conf->barrier++) {
+ wait_event_lock_irq(conf->wait_idle, !conf->nr_pending,
+ conf->resync_lock, unplug_slaves(conf->mddev));
+ if (conf->nr_pending)
+ BUG();
+ }
+ wait_event_lock_irq(conf->wait_resume, conf->barrier < RESYNC_DEPTH,
+ conf->resync_lock, unplug_slaves(conf->mddev));
+ conf->next_resync = sect;
+ spin_unlock_irq(&conf->resync_lock);
+}
+
+static int make_request(request_queue_t *q, struct bio * bio)
+{
+ mddev_t *mddev = q->queuedata;
+ conf_t *conf = mddev_to_conf(mddev);
+ mirror_info_t *mirror;
+ r10bio_t *r10_bio;
+ struct bio *read_bio;
+ int i;
+ int chunk_sects = conf->chunk_mask + 1;
+
+ /* If this request crosses a chunk boundary, we need to
+ * split it. This will only happen for 1 PAGE (or less) requests.
+ */
+ if (unlikely( (bio->bi_sector & conf->chunk_mask) + (bio->bi_size >> 9)
+ > chunk_sects &&
+ conf->near_copies < conf->raid_disks)) {
+ struct bio_pair *bp;
+ /* Sanity check -- queue functions should prevent this happening */
+ if (bio->bi_vcnt != 1 ||
+ bio->bi_idx != 0)
+ goto bad_map;
+ /* This is a one page bio that upper layers
+ * refuse to split for us, so we need to split it.
+ */
+ bp = bio_split(bio, bio_split_pool,
+ chunk_sects - (bio->bi_sector & (chunk_sects - 1)) );
+ if (make_request(q, &bp->bio1))
+ generic_make_request(&bp->bio1);
+ if (make_request(q, &bp->bio2))
+ generic_make_request(&bp->bio2);
+
+ bio_pair_release(bp);
+ return 0;
+ bad_map:
+ printk("raid10_make_request bug: can't convert block across chunks"
+ " or bigger than %dk %llu %d\n", chunk_sects/2,
+ (unsigned long long)bio->bi_sector, bio->bi_size >> 10);
+
+ bio_io_error(bio, bio->bi_size);
+ return 0;
+ }
+
+ /*
+ * Register the new request and wait if the reconstruction
+ * thread has put up a bar for new requests.
+ * Continue immediately if no resync is active currently.
+ */
+ spin_lock_irq(&conf->resync_lock);
+ wait_event_lock_irq(conf->wait_resume, !conf->barrier, conf->resync_lock, );
+ conf->nr_pending++;
+ spin_unlock_irq(&conf->resync_lock);
+
+ if (bio_data_dir(bio)==WRITE) {
+ disk_stat_inc(mddev->gendisk, writes);
+ disk_stat_add(mddev->gendisk, write_sectors, bio_sectors(bio));
+ } else {
+ disk_stat_inc(mddev->gendisk, reads);
+ disk_stat_add(mddev->gendisk, read_sectors, bio_sectors(bio));
+ }
+
+ r10_bio = mempool_alloc(conf->r10bio_pool, GFP_NOIO);
+
+ r10_bio->master_bio = bio;
+ r10_bio->sectors = bio->bi_size >> 9;
+
+ r10_bio->mddev = mddev;
+ r10_bio->sector = bio->bi_sector;
+
+ if (bio_data_dir(bio) == READ) {
+ /*
+ * read balancing logic:
+ */
+ int disk = read_balance(conf, r10_bio);
+ int slot = r10_bio->read_slot;
+ if (disk < 0) {
+ raid_end_bio_io(r10_bio);
+ return 0;
+ }
+ mirror = conf->mirrors + disk;
+
+ read_bio = bio_clone(bio, GFP_NOIO);
+
+ r10_bio->devs[slot].bio = read_bio;
+
+ read_bio->bi_sector = r10_bio->devs[slot].addr +
+ mirror->rdev->data_offset;
+ read_bio->bi_bdev = mirror->rdev->bdev;
+ read_bio->bi_end_io = raid10_end_read_request;
+ read_bio->bi_rw = READ;
+ read_bio->bi_private = r10_bio;
+
+ generic_make_request(read_bio);
+ return 0;
+ }
+
+ /*
+ * WRITE:
+ */
+ /* first select target devices under spinlock and
+ * inc refcount on their rdev. Record them by setting
+ * bios[x] to bio
+ */
+ raid10_find_phys(conf, r10_bio);
+ spin_lock_irq(&conf->device_lock);
+ for (i = 0; i < conf->copies; i++) {
+ int d = r10_bio->devs[i].devnum;
+ if (conf->mirrors[d].rdev &&
+ !conf->mirrors[d].rdev->faulty) {
+ atomic_inc(&conf->mirrors[d].rdev->nr_pending);
+ r10_bio->devs[i].bio = bio;
+ } else
+ r10_bio->devs[i].bio = NULL;
+ }
+ spin_unlock_irq(&conf->device_lock);
+
+ atomic_set(&r10_bio->remaining, 1);
+ md_write_start(mddev);
+ for (i = 0; i < conf->copies; i++) {
+ struct bio *mbio;
+ int d = r10_bio->devs[i].devnum;
+ if (!r10_bio->devs[i].bio)
+ continue;
+
+ mbio = bio_clone(bio, GFP_NOIO);
+ r10_bio->devs[i].bio = mbio;
+
+ mbio->bi_sector = r10_bio->devs[i].addr+
+ conf->mirrors[d].rdev->data_offset;
+ mbio->bi_bdev = conf->mirrors[d].rdev->bdev;
+ mbio->bi_end_io = raid10_end_write_request;
+ mbio->bi_rw = WRITE;
+ mbio->bi_private = r10_bio;
+
+ atomic_inc(&r10_bio->remaining);
+ generic_make_request(mbio);
+ }
+
+ if (atomic_dec_and_test(&r10_bio->remaining)) {
+ md_write_end(mddev);
+ raid_end_bio_io(r10_bio);
+ }
+
+ return 0;
+}
+
+static void status(struct seq_file *seq, mddev_t *mddev)
+{
+ conf_t *conf = mddev_to_conf(mddev);
+ int i;
+
+ if (conf->near_copies < conf->raid_disks)
+ seq_printf(seq, " %dK chunks", mddev->chunk_size/1024);
+ if (conf->near_copies > 1)
+ seq_printf(seq, " %d near-copies", conf->near_copies);
+ if (conf->far_copies > 1)
+ seq_printf(seq, " %d far-copies", conf->far_copies);
+
+ seq_printf(seq, " [%d/%d] [", conf->raid_disks,
+ conf->working_disks);
+ for (i = 0; i < conf->raid_disks; i++)
+ seq_printf(seq, "%s",
+ conf->mirrors[i].rdev &&
+ conf->mirrors[i].rdev->in_sync ? "U" : "_");
+ seq_printf(seq, "]");
+}
+
+static void error(mddev_t *mddev, mdk_rdev_t *rdev)
+{
+ char b[BDEVNAME_SIZE];
+ conf_t *conf = mddev_to_conf(mddev);
+
+ /*
+ * If it is not operational, then we have already marked it as dead
+ * else if it is the last working disks, ignore the error, let the
+ * next level up know.
+ * else mark the drive as failed
+ */
+ if (rdev->in_sync
+ && conf->working_disks == 1)
+ /*
+ * Don't fail the drive, just return an IO error.
+ * The test should really be more sophisticated than
+ * "working_disks == 1", but it isn't critical, and
+ * can wait until we do more sophisticated "is the drive
+ * really dead" tests...
+ */
+ return;
+ if (rdev->in_sync) {
+ mddev->degraded++;
+ conf->working_disks--;
+ /*
+ * if recovery is running, make sure it aborts.
+ */
+ set_bit(MD_RECOVERY_ERR, &mddev->recovery);
+ }
+ rdev->in_sync = 0;
+ rdev->faulty = 1;
+ mddev->sb_dirty = 1;
+ printk(KERN_ALERT "raid10: Disk failure on %s, disabling device. \n"
+ " Operation continuing on %d devices\n",
+ bdevname(rdev->bdev,b), conf->working_disks);
+}
+
+static void print_conf(conf_t *conf)
+{
+ int i;
+ mirror_info_t *tmp;
+
+ printk("RAID10 conf printout:\n");
+ if (!conf) {
+ printk("(!conf)\n");
+ return;
+ }
+ printk(" --- wd:%d rd:%d\n", conf->working_disks,
+ conf->raid_disks);
+
+ for (i = 0; i < conf->raid_disks; i++) {
+ char b[BDEVNAME_SIZE];
+ tmp = conf->mirrors + i;
+ if (tmp->rdev)
+ printk(" disk %d, wo:%d, o:%d, dev:%s\n",
+ i, !tmp->rdev->in_sync, !tmp->rdev->faulty,
+ bdevname(tmp->rdev->bdev,b));
+ }
+}
+
+static void close_sync(conf_t *conf)
+{
+ spin_lock_irq(&conf->resync_lock);
+ wait_event_lock_irq(conf->wait_resume, !conf->barrier,
+ conf->resync_lock, unplug_slaves(conf->mddev));
+ spin_unlock_irq(&conf->resync_lock);
+
+ if (conf->barrier) BUG();
+ if (waitqueue_active(&conf->wait_idle)) BUG();
+
+ mempool_destroy(conf->r10buf_pool);
+ conf->r10buf_pool = NULL;
+}
+
+static int raid10_spare_active(mddev_t *mddev)
+{
+ int i;
+ conf_t *conf = mddev->private;
+ mirror_info_t *tmp;
+
+ spin_lock_irq(&conf->device_lock);
+ /*
+ * Find all non-in_sync disks within the RAID10 configuration
+ * and mark them in_sync
+ */
+ for (i = 0; i < conf->raid_disks; i++) {
+ tmp = conf->mirrors + i;
+ if (tmp->rdev
+ && !tmp->rdev->faulty
+ && !tmp->rdev->in_sync) {
+ conf->working_disks++;
+ mddev->degraded--;
+ tmp->rdev->in_sync = 1;
+ }
+ }
+ spin_unlock_irq(&conf->device_lock);
+
+ print_conf(conf);
+ return 0;
+}
+
+
+static int raid10_add_disk(mddev_t *mddev, mdk_rdev_t *rdev)
+{
+ conf_t *conf = mddev->private;
+ int found = 0;
+ int mirror;
+ mirror_info_t *p;
+
+ if (mddev->recovery_cp < MaxSector)
+ /* only hot-add to in-sync arrays, as recovery is
+ * very different from resync
+ */
+ return 0;
+ spin_lock_irq(&conf->device_lock);
+ for (mirror=0; mirror < mddev->raid_disks; mirror++)
+ if ( !(p=conf->mirrors+mirror)->rdev) {
+ p->rdev = rdev;
+
+ blk_queue_stack_limits(mddev->queue,
+ rdev->bdev->bd_disk->queue);
+ /* as we don't honour merge_bvec_fn, we must never risk
+ * violating it, so limit ->max_sector to one PAGE, as
+ * a one page request is never in violation.
+ */
+ if (rdev->bdev->bd_disk->queue->merge_bvec_fn &&
+ mddev->queue->max_sectors > (PAGE_SIZE>>9))
+ mddev->queue->max_sectors = (PAGE_SIZE>>9);
+
+ p->head_position = 0;
+ rdev->raid_disk = mirror;
+ found = 1;
+ break;
+ }
+ spin_unlock_irq(&conf->device_lock);
+
+ print_conf(conf);
+ return found;
+}
+
+static int raid10_remove_disk(mddev_t *mddev, int number)
+{
+ conf_t *conf = mddev->private;
+ int err = 1;
+ mirror_info_t *p = conf->mirrors+ number;
+
+ print_conf(conf);
+ spin_lock_irq(&conf->device_lock);
+ if (p->rdev) {
+ if (p->rdev->in_sync ||
+ atomic_read(&p->rdev->nr_pending)) {
+ err = -EBUSY;
+ goto abort;
+ }
+ p->rdev = NULL;
+ err = 0;
+ }
+ if (err)
+ MD_BUG();
+abort:
+ spin_unlock_irq(&conf->device_lock);
+
+ print_conf(conf);
+ return err;
+}
+
+
+static int end_sync_read(struct bio *bio, unsigned int bytes_done, int error)
+{
+ int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
+ r10bio_t * r10_bio = (r10bio_t *)(bio->bi_private);
+ conf_t *conf = mddev_to_conf(r10_bio->mddev);
+ int i,d;
+
+ if (bio->bi_size)
+ return 1;
+
+ for (i=0; i<conf->copies; i++)
+ if (r10_bio->devs[i].bio == bio)
+ break;
+ if (i == conf->copies)
+ BUG();
+ update_head_pos(i, r10_bio);
+ d = r10_bio->devs[i].devnum;
+ if (!uptodate)
+ md_error(r10_bio->mddev,
+ conf->mirrors[d].rdev);
+
+ /* for reconstruct, we always reschedule after a read.
+ * for resync, only after all reads
+ */
+ if (test_bit(R10BIO_IsRecover, &r10_bio->state) ||
+ atomic_dec_and_test(&r10_bio->remaining)) {
+ /* we have read all the blocks,
+ * do the comparison in process context in raid10d
+ */
+ reschedule_retry(r10_bio);
+ }
+ rdev_dec_pending(conf->mirrors[d].rdev, conf->mddev);
+ return 0;
+}
+
+static int end_sync_write(struct bio *bio, unsigned int bytes_done, int error)
+{
+ int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
+ r10bio_t * r10_bio = (r10bio_t *)(bio->bi_private);
+ mddev_t *mddev = r10_bio->mddev;
+ conf_t *conf = mddev_to_conf(mddev);
+ int i,d;
+
+ if (bio->bi_size)
+ return 1;
+
+ for (i = 0; i < conf->copies; i++)
+ if (r10_bio->devs[i].bio == bio)
+ break;
+ d = r10_bio->devs[i].devnum;
+
+ if (!uptodate)
+ md_error(mddev, conf->mirrors[d].rdev);
+ update_head_pos(i, r10_bio);
+
+ while (atomic_dec_and_test(&r10_bio->remaining)) {
+ if (r10_bio->master_bio == NULL) {
+ /* the primary of several recovery bios */
+ md_done_sync(mddev, r10_bio->sectors, 1);
+ put_buf(r10_bio);
+ break;
+ } else {
+ r10bio_t *r10_bio2 = (r10bio_t *)r10_bio->master_bio;
+ put_buf(r10_bio);
+ r10_bio = r10_bio2;
+ }
+ }
+ rdev_dec_pending(conf->mirrors[d].rdev, mddev);
+ return 0;
+}
+
+/*
+ * Note: sync and recover and handled very differently for raid10
+ * This code is for resync.
+ * For resync, we read through virtual addresses and read all blocks.
+ * If there is any error, we schedule a write. The lowest numbered
+ * drive is authoritative.
+ * However requests come for physical address, so we need to map.
+ * For every physical address there are raid_disks/copies virtual addresses,
+ * which is always are least one, but is not necessarly an integer.
+ * This means that a physical address can span multiple chunks, so we may
+ * have to submit multiple io requests for a single sync request.
+ */
+/*
+ * We check if all blocks are in-sync and only write to blocks that
+ * aren't in sync
+ */
+static void sync_request_write(mddev_t *mddev, r10bio_t *r10_bio)
+{
+ conf_t *conf = mddev_to_conf(mddev);
+ int i, first;
+ struct bio *tbio, *fbio;
+
+ atomic_set(&r10_bio->remaining, 1);
+
+ /* find the first device with a block */
+ for (i=0; i<conf->copies; i++)
+ if (test_bit(BIO_UPTODATE, &r10_bio->devs[i].bio->bi_flags))
+ break;
+
+ if (i == conf->copies)
+ goto done;
+
+ first = i;
+ fbio = r10_bio->devs[i].bio;
+
+ /* now find blocks with errors */
+ for (i=first+1 ; i < conf->copies ; i++) {
+ int vcnt, j, d;
+
+ if (!test_bit(BIO_UPTODATE, &r10_bio->devs[i].bio->bi_flags))
+ continue;
+ /* We know that the bi_io_vec layout is the same for
+ * both 'first' and 'i', so we just compare them.
+ * All vec entries are PAGE_SIZE;
+ */
+ tbio = r10_bio->devs[i].bio;
+ vcnt = r10_bio->sectors >> (PAGE_SHIFT-9);
+ for (j = 0; j < vcnt; j++)
+ if (memcmp(page_address(fbio->bi_io_vec[j].bv_page),
+ page_address(tbio->bi_io_vec[j].bv_page),
+ PAGE_SIZE))
+ break;
+ if (j == vcnt)
+ continue;
+ /* Ok, we need to write this bio
+ * First we need to fixup bv_offset, bv_len and
+ * bi_vecs, as the read request might have corrupted these
+ */
+ tbio->bi_vcnt = vcnt;
+ tbio->bi_size = r10_bio->sectors << 9;
+ tbio->bi_idx = 0;
+ tbio->bi_phys_segments = 0;
+ tbio->bi_hw_segments = 0;
+ tbio->bi_hw_front_size = 0;
+ tbio->bi_hw_back_size = 0;
+ tbio->bi_flags &= ~(BIO_POOL_MASK - 1);
+ tbio->bi_flags |= 1 << BIO_UPTODATE;
+ tbio->bi_next = NULL;
+ tbio->bi_rw = WRITE;
+ tbio->bi_private = r10_bio;
+ tbio->bi_sector = r10_bio->devs[i].addr;
+
+ for (j=0; j < vcnt ; j++) {
+ tbio->bi_io_vec[j].bv_offset = 0;
+ tbio->bi_io_vec[j].bv_len = PAGE_SIZE;
+
+ memcpy(page_address(tbio->bi_io_vec[j].bv_page),
+ page_address(fbio->bi_io_vec[j].bv_page),
+ PAGE_SIZE);
+ }
+ tbio->bi_end_io = end_sync_write;
+
+ d = r10_bio->devs[i].devnum;
+ atomic_inc(&conf->mirrors[d].rdev->nr_pending);
+ atomic_inc(&r10_bio->remaining);
+ md_sync_acct(conf->mirrors[d].rdev->bdev, tbio->bi_size >> 9);
+
+ generic_make_request(tbio);
+ }
+
+done:
+ if (atomic_dec_and_test(&r10_bio->remaining)) {
+ md_done_sync(mddev, r10_bio->sectors, 1);
+ put_buf(r10_bio);
+ }
+}
+
+/*
+ * Now for the recovery code.
+ * Recovery happens across physical sectors.
+ * We recover all non-is_sync drives by finding the virtual address of
+ * each, and then choose a working drive that also has that virt address.
+ * There is a separate r10_bio for each non-in_sync drive.
+ * Only the first two slots are in use. The first for reading,
+ * The second for writing.
+ *
+ */
+
+static void recovery_request_write(mddev_t *mddev, r10bio_t *r10_bio)
+{
+ conf_t *conf = mddev_to_conf(mddev);
+ int i, d;
+ struct bio *bio, *wbio;
+
+
+ /* move the pages across to the second bio
+ * and submit the write request
+ */
+ bio = r10_bio->devs[0].bio;
+ wbio = r10_bio->devs[1].bio;
+ for (i=0; i < wbio->bi_vcnt; i++) {
+ struct page *p = bio->bi_io_vec[i].bv_page;
+ bio->bi_io_vec[i].bv_page = wbio->bi_io_vec[i].bv_page;
+ wbio->bi_io_vec[i].bv_page = p;
+ }
+ d = r10_bio->devs[1].devnum;
+
+ atomic_inc(&conf->mirrors[d].rdev->nr_pending);
+ md_sync_acct(conf->mirrors[d].rdev->bdev, wbio->bi_size >> 9);
+ generic_make_request(wbio);
+}
+
+
+/*
+ * This is a kernel thread which:
+ *
+ * 1. Retries failed read operations on working mirrors.
+ * 2. Updates the raid superblock when problems encounter.
+ * 3. Performs writes following reads for array syncronising.
+ */
+
+static void raid10d(mddev_t *mddev)
+{
+ r10bio_t *r10_bio;
+ struct bio *bio;
+ unsigned long flags;
+ conf_t *conf = mddev_to_conf(mddev);
+ struct list_head *head = &conf->retry_list;
+ int unplug=0;
+ mdk_rdev_t *rdev;
+
+ md_check_recovery(mddev);
+ md_handle_safemode(mddev);
+
+ for (;;) {
+ char b[BDEVNAME_SIZE];
+ spin_lock_irqsave(&conf->device_lock, flags);
+ if (list_empty(head))
+ break;
+ r10_bio = list_entry(head->prev, r10bio_t, retry_list);
+ list_del(head->prev);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+
+ mddev = r10_bio->mddev;
+ conf = mddev_to_conf(mddev);
+ if (test_bit(R10BIO_IsSync, &r10_bio->state)) {
+ sync_request_write(mddev, r10_bio);
+ unplug = 1;
+ } else if (test_bit(R10BIO_IsRecover, &r10_bio->state)) {
+ recovery_request_write(mddev, r10_bio);
+ unplug = 1;
+ } else {
+ int mirror;
+ bio = r10_bio->devs[r10_bio->read_slot].bio;
+ r10_bio->devs[r10_bio->read_slot].bio = NULL;
+ mirror = read_balance(conf, r10_bio);
+ r10_bio->devs[r10_bio->read_slot].bio = bio;
+ if (mirror == -1) {
+ printk(KERN_ALERT "raid10: %s: unrecoverable I/O"
+ " read error for block %llu\n",
+ bdevname(bio->bi_bdev,b),
+ (unsigned long long)r10_bio->sector);
+ raid_end_bio_io(r10_bio);
+ } else {
+ rdev = conf->mirrors[mirror].rdev;
+ if (printk_ratelimit())
+ printk(KERN_ERR "raid10: %s: redirecting sector %llu to"
+ " another mirror\n",
+ bdevname(rdev->bdev,b),
+ (unsigned long long)r10_bio->sector);
+ bio->bi_bdev = rdev->bdev;
+ bio->bi_sector = r10_bio->devs[r10_bio->read_slot].addr
+ + rdev->data_offset;
+ bio->bi_next = NULL;
+ bio->bi_flags &= (1<<BIO_CLONED);
+ bio->bi_flags |= 1 << BIO_UPTODATE;
+ bio->bi_idx = 0;
+ bio->bi_size = r10_bio->sectors << 9;
+ bio->bi_rw = READ;
+ unplug = 1;
+ generic_make_request(bio);
+ }
+ }
+ }
+ spin_unlock_irqrestore(&conf->device_lock, flags);
+ if (unplug)
+ unplug_slaves(mddev);
+}
+
+
+static int init_resync(conf_t *conf)
+{
+ int buffs;
+
+ buffs = RESYNC_WINDOW / RESYNC_BLOCK_SIZE;
+ if (conf->r10buf_pool)
+ BUG();
+ conf->r10buf_pool = mempool_create(buffs, r10buf_pool_alloc, r10buf_pool_free, conf);
+ if (!conf->r10buf_pool)
+ return -ENOMEM;
+ conf->next_resync = 0;
+ return 0;
+}
+
+/*
+ * perform a "sync" on one "block"
+ *
+ * We need to make sure that no normal I/O request - particularly write
+ * requests - conflict with active sync requests.
+ *
+ * This is achieved by tracking pending requests and a 'barrier' concept
+ * that can be installed to exclude normal IO requests.
+ *
+ * Resync and recovery are handled very differently.
+ * We differentiate by looking at MD_RECOVERY_SYNC in mddev->recovery.
+ *
+ * For resync, we iterate over virtual addresses, read all copies,
+ * and update if there are differences. If only one copy is live,
+ * skip it.
+ * For recovery, we iterate over physical addresses, read a good
+ * value for each non-in_sync drive, and over-write.
+ *
+ * So, for recovery we may have several outstanding complex requests for a
+ * given address, one for each out-of-sync device. We model this by allocating
+ * a number of r10_bio structures, one for each out-of-sync device.
+ * As we setup these structures, we collect all bio's together into a list
+ * which we then process collectively to add pages, and then process again
+ * to pass to generic_make_request.
+ *
+ * The r10_bio structures are linked using a borrowed master_bio pointer.
+ * This link is counted in ->remaining. When the r10_bio that points to NULL
+ * has its remaining count decremented to 0, the whole complex operation
+ * is complete.
+ *
+ */
+
+static int sync_request(mddev_t *mddev, sector_t sector_nr, int go_faster)
+{
+ conf_t *conf = mddev_to_conf(mddev);
+ r10bio_t *r10_bio;
+ struct bio *biolist = NULL, *bio;
+ sector_t max_sector, nr_sectors;
+ int disk;
+ int i;
+
+ sector_t sectors_skipped = 0;
+ int chunks_skipped = 0;
+
+ if (!conf->r10buf_pool)
+ if (init_resync(conf))
+ return -ENOMEM;
+
+ skipped:
+ max_sector = mddev->size << 1;
+ if (test_bit(MD_RECOVERY_SYNC, &mddev->recovery))
+ max_sector = mddev->resync_max_sectors;
+ if (sector_nr >= max_sector) {
+ close_sync(conf);
+ return sectors_skipped;
+ }
+ if (chunks_skipped >= conf->raid_disks) {
+ /* if there has been nothing to do on any drive,
+ * then there is nothing to do at all..
+ */
+ sector_t sec = max_sector - sector_nr;
+ md_done_sync(mddev, sec, 1);
+ return sec + sectors_skipped;
+ }
+
+ /* make sure whole request will fit in a chunk - if chunks
+ * are meaningful
+ */
+ if (conf->near_copies < conf->raid_disks &&
+ max_sector > (sector_nr | conf->chunk_mask))
+ max_sector = (sector_nr | conf->chunk_mask) + 1;
+ /*
+ * If there is non-resync activity waiting for us then
+ * put in a delay to throttle resync.
+ */
+ if (!go_faster && waitqueue_active(&conf->wait_resume))
+ schedule_timeout(HZ);
+ device_barrier(conf, sector_nr + RESYNC_SECTORS);
+
+ /* Again, very different code for resync and recovery.
+ * Both must result in an r10bio with a list of bios that
+ * have bi_end_io, bi_sector, bi_bdev set,
+ * and bi_private set to the r10bio.
+ * For recovery, we may actually create several r10bios
+ * with 2 bios in each, that correspond to the bios in the main one.
+ * In this case, the subordinate r10bios link back through a
+ * borrowed master_bio pointer, and the counter in the master
+ * includes a ref from each subordinate.
+ */
+ /* First, we decide what to do and set ->bi_end_io
+ * To end_sync_read if we want to read, and
+ * end_sync_write if we will want to write.
+ */
+
+ if (!test_bit(MD_RECOVERY_SYNC, &mddev->recovery)) {
+ /* recovery... the complicated one */
+ int i, j, k;
+ r10_bio = NULL;
+
+ for (i=0 ; i<conf->raid_disks; i++)
+ if (conf->mirrors[i].rdev &&
+ !conf->mirrors[i].rdev->in_sync) {
+ /* want to reconstruct this device */
+ r10bio_t *rb2 = r10_bio;
+
+ r10_bio = mempool_alloc(conf->r10buf_pool, GFP_NOIO);
+ spin_lock_irq(&conf->resync_lock);
+ conf->nr_pending++;
+ if (rb2) conf->barrier++;
+ spin_unlock_irq(&conf->resync_lock);
+ atomic_set(&r10_bio->remaining, 0);
+
+ r10_bio->master_bio = (struct bio*)rb2;
+ if (rb2)
+ atomic_inc(&rb2->remaining);
+ r10_bio->mddev = mddev;
+ set_bit(R10BIO_IsRecover, &r10_bio->state);
+ r10_bio->sector = raid10_find_virt(conf, sector_nr, i);
+ raid10_find_phys(conf, r10_bio);
+ for (j=0; j<conf->copies;j++) {
+ int d = r10_bio->devs[j].devnum;
+ if (conf->mirrors[d].rdev &&
+ conf->mirrors[d].rdev->in_sync) {
+ /* This is where we read from */
+ bio = r10_bio->devs[0].bio;
+ bio->bi_next = biolist;
+ biolist = bio;
+ bio->bi_private = r10_bio;
+ bio->bi_end_io = end_sync_read;
+ bio->bi_rw = 0;
+ bio->bi_sector = r10_bio->devs[j].addr +
+ conf->mirrors[d].rdev->data_offset;
+ bio->bi_bdev = conf->mirrors[d].rdev->bdev;
+ atomic_inc(&conf->mirrors[d].rdev->nr_pending);
+ atomic_inc(&r10_bio->remaining);
+ /* and we write to 'i' */
+
+ for (k=0; k<conf->copies; k++)
+ if (r10_bio->devs[k].devnum == i)
+ break;
+ bio = r10_bio->devs[1].bio;
+ bio->bi_next = biolist;
+ biolist = bio;
+ bio->bi_private = r10_bio;
+ bio->bi_end_io = end_sync_write;
+ bio->bi_rw = 1;
+ bio->bi_sector = r10_bio->devs[k].addr +
+ conf->mirrors[i].rdev->data_offset;
+ bio->bi_bdev = conf->mirrors[i].rdev->bdev;
+
+ r10_bio->devs[0].devnum = d;
+ r10_bio->devs[1].devnum = i;
+
+ break;
+ }
+ }
+ if (j == conf->copies) {
+ BUG();
+ }
+ }
+ if (biolist == NULL) {
+ while (r10_bio) {
+ r10bio_t *rb2 = r10_bio;
+ r10_bio = (r10bio_t*) rb2->master_bio;
+ rb2->master_bio = NULL;
+ put_buf(rb2);
+ }
+ goto giveup;
+ }
+ } else {
+ /* resync. Schedule a read for every block at this virt offset */
+ int count = 0;
+ r10_bio = mempool_alloc(conf->r10buf_pool, GFP_NOIO);
+
+ spin_lock_irq(&conf->resync_lock);
+ conf->nr_pending++;
+ spin_unlock_irq(&conf->resync_lock);
+
+ r10_bio->mddev = mddev;
+ atomic_set(&r10_bio->remaining, 0);
+
+ r10_bio->master_bio = NULL;
+ r10_bio->sector = sector_nr;
+ set_bit(R10BIO_IsSync, &r10_bio->state);
+ raid10_find_phys(conf, r10_bio);
+ r10_bio->sectors = (sector_nr | conf->chunk_mask) - sector_nr +1;
+ spin_lock_irq(&conf->device_lock);
+ for (i=0; i<conf->copies; i++) {
+ int d = r10_bio->devs[i].devnum;
+ bio = r10_bio->devs[i].bio;
+ bio->bi_end_io = NULL;
+ if (conf->mirrors[d].rdev == NULL ||
+ conf->mirrors[d].rdev->faulty)
+ continue;
+ atomic_inc(&conf->mirrors[d].rdev->nr_pending);
+ atomic_inc(&r10_bio->remaining);
+ bio->bi_next = biolist;
+ biolist = bio;
+ bio->bi_private = r10_bio;
+ bio->bi_end_io = end_sync_read;
+ bio->bi_rw = 0;
+ bio->bi_sector = r10_bio->devs[i].addr +
+ conf->mirrors[d].rdev->data_offset;
+ bio->bi_bdev = conf->mirrors[d].rdev->bdev;
+ count++;
+ }
+ spin_unlock_irq(&conf->device_lock);
+ if (count < 2) {
+ for (i=0; i<conf->copies; i++) {
+ int d = r10_bio->devs[i].devnum;
+ if (r10_bio->devs[i].bio->bi_end_io)
+ atomic_dec(&conf->mirrors[d].rdev->nr_pending);
+ }
+ put_buf(r10_bio);
+ goto giveup;
+ }
+ }
+
+ for (bio = biolist; bio ; bio=bio->bi_next) {
+
+ bio->bi_flags &= ~(BIO_POOL_MASK - 1);
+ if (bio->bi_end_io)
+ bio->bi_flags |= 1 << BIO_UPTODATE;
+ bio->bi_vcnt = 0;
+ bio->bi_idx = 0;
+ bio->bi_phys_segments = 0;
+ bio->bi_hw_segments = 0;
+ bio->bi_size = 0;
+ }
+
+ nr_sectors = 0;
+ do {
+ struct page *page;
+ int len = PAGE_SIZE;
+ disk = 0;
+ if (sector_nr + (len>>9) > max_sector)
+ len = (max_sector - sector_nr) << 9;
+ if (len == 0)
+ break;
+ for (bio= biolist ; bio ; bio=bio->bi_next) {
+ page = bio->bi_io_vec[bio->bi_vcnt].bv_page;
+ if (bio_add_page(bio, page, len, 0) == 0) {
+ /* stop here */
+ struct bio *bio2;
+ bio->bi_io_vec[bio->bi_vcnt].bv_page = page;
+ for (bio2 = biolist; bio2 && bio2 != bio; bio2 = bio2->bi_next) {
+ /* remove last page from this bio */
+ bio2->bi_vcnt--;
+ bio2->bi_size -= len;
+ bio2->bi_flags &= ~(1<< BIO_SEG_VALID);
+ }
+ goto bio_full;
+ }
+ disk = i;
+ }
+ nr_sectors += len>>9;
+ sector_nr += len>>9;
+ } while (biolist->bi_vcnt < RESYNC_PAGES);
+ bio_full:
+ r10_bio->sectors = nr_sectors;
+
+ while (biolist) {
+ bio = biolist;
+ biolist = biolist->bi_next;
+
+ bio->bi_next = NULL;
+ r10_bio = bio->bi_private;
+ r10_bio->sectors = nr_sectors;
+
+ if (bio->bi_end_io == end_sync_read) {
+ md_sync_acct(bio->bi_bdev, nr_sectors);
+ generic_make_request(bio);
+ }
+ }
+
+ return nr_sectors;
+ giveup:
+ /* There is nowhere to write, so all non-sync
+ * drives must be failed, so try the next chunk...
+ */
+ {
+ int sec = max_sector - sector_nr;
+ sectors_skipped += sec;
+ chunks_skipped ++;
+ sector_nr = max_sector;
+ md_done_sync(mddev, sec, 1);
+ goto skipped;
+ }
+}
+
+static int run(mddev_t *mddev)
+{
+ conf_t *conf;
+ int i, disk_idx;
+ mirror_info_t *disk;
+ mdk_rdev_t *rdev;
+ struct list_head *tmp;
+ int nc, fc;
+ sector_t stride, size;
+
+ if (mddev->level != 10) {
+ printk(KERN_ERR "raid10: %s: raid level not set correctly... (%d)\n",
+ mdname(mddev), mddev->level);
+ goto out;
+ }
+ nc = mddev->layout & 255;
+ fc = (mddev->layout >> 8) & 255;
+ if ((nc*fc) <2 || (nc*fc) > mddev->raid_disks ||
+ (mddev->layout >> 16)) {
+ printk(KERN_ERR "raid10: %s: unsupported raid10 layout: 0x%8x\n",
+ mdname(mddev), mddev->layout);
+ goto out;
+ }
+ /*
+ * copy the already verified devices into our private RAID10
+ * bookkeeping area. [whatever we allocate in run(),
+ * should be freed in stop()]
+ */
+ conf = kmalloc(sizeof(conf_t), GFP_KERNEL);
+ mddev->private = conf;
+ if (!conf) {
+ printk(KERN_ERR "raid10: couldn't allocate memory for %s\n",
+ mdname(mddev));
+ goto out;
+ }
+ memset(conf, 0, sizeof(*conf));
+ conf->mirrors = kmalloc(sizeof(struct mirror_info)*mddev->raid_disks,
+ GFP_KERNEL);
+ if (!conf->mirrors) {
+ printk(KERN_ERR "raid10: couldn't allocate memory for %s\n",
+ mdname(mddev));
+ goto out_free_conf;
+ }
+ memset(conf->mirrors, 0, sizeof(struct mirror_info)*mddev->raid_disks);
+
+ conf->near_copies = nc;
+ conf->far_copies = fc;
+ conf->copies = nc*fc;
+ conf->chunk_mask = (sector_t)(mddev->chunk_size>>9)-1;
+ conf->chunk_shift = ffz(~mddev->chunk_size) - 9;
+ stride = mddev->size >> (conf->chunk_shift-1);
+ sector_div(stride, fc);
+ conf->stride = stride << conf->chunk_shift;
+
+ conf->r10bio_pool = mempool_create(NR_RAID10_BIOS, r10bio_pool_alloc,
+ r10bio_pool_free, conf);
+ if (!conf->r10bio_pool) {
+ printk(KERN_ERR "raid10: couldn't allocate memory for %s\n",
+ mdname(mddev));
+ goto out_free_conf;
+ }
+ mddev->queue->unplug_fn = raid10_unplug;
+
+ mddev->queue->issue_flush_fn = raid10_issue_flush;
+
+ ITERATE_RDEV(mddev, rdev, tmp) {
+ disk_idx = rdev->raid_disk;
+ if (disk_idx >= mddev->raid_disks
+ || disk_idx < 0)
+ continue;
+ disk = conf->mirrors + disk_idx;
+
+ disk->rdev = rdev;
+
+ blk_queue_stack_limits(mddev->queue,
+ rdev->bdev->bd_disk->queue);
+ /* as we don't honour merge_bvec_fn, we must never risk
+ * violating it, so limit ->max_sector to one PAGE, as
+ * a one page request is never in violation.
+ */
+ if (rdev->bdev->bd_disk->queue->merge_bvec_fn &&
+ mddev->queue->max_sectors > (PAGE_SIZE>>9))
+ mddev->queue->max_sectors = (PAGE_SIZE>>9);
+
+ disk->head_position = 0;
+ if (!rdev->faulty && rdev->in_sync)
+ conf->working_disks++;
+ }
+ conf->raid_disks = mddev->raid_disks;
+ conf->mddev = mddev;
+ conf->device_lock = SPIN_LOCK_UNLOCKED;
+ INIT_LIST_HEAD(&conf->retry_list);
+
+ conf->resync_lock = SPIN_LOCK_UNLOCKED;
+ init_waitqueue_head(&conf->wait_idle);
+ init_waitqueue_head(&conf->wait_resume);
+
+ if (!conf->working_disks) {
+ printk(KERN_ERR "raid10: no operational mirrors for %s\n",
+ mdname(mddev));
+ goto out_free_conf;
+ }
+
+ mddev->degraded = 0;
+ for (i = 0; i < conf->raid_disks; i++) {
+
+ disk = conf->mirrors + i;
+
+ if (!disk->rdev) {
+ disk->head_position = 0;
+ mddev->degraded++;
+ }
+ }
+
+
+ mddev->thread = md_register_thread(raid10d, mddev, "%s_raid10");
+ if (!mddev->thread) {
+ printk(KERN_ERR
+ "raid10: couldn't allocate thread for %s\n",
+ mdname(mddev));
+ goto out_free_conf;
+ }
+
+ printk(KERN_INFO
+ "raid10: raid set %s active with %d out of %d devices\n",
+ mdname(mddev), mddev->raid_disks - mddev->degraded,
+ mddev->raid_disks);
+ /*
+ * Ok, everything is just fine now
+ */
+ size = conf->stride * conf->raid_disks;
+ sector_div(size, conf->near_copies);
+ mddev->array_size = size/2;
+ mddev->resync_max_sectors = size;
+
+ /* Calculate max read-ahead size.
+ * We need to readahead at least twice a whole stripe....
+ * maybe...
+ */
+ {
+ int stripe = conf->raid_disks * mddev->chunk_size / PAGE_CACHE_SIZE;
+ stripe /= conf->near_copies;
+ if (mddev->queue->backing_dev_info.ra_pages < 2* stripe)
+ mddev->queue->backing_dev_info.ra_pages = 2* stripe;
+ }
+
+ if (conf->near_copies < mddev->raid_disks)
+ blk_queue_merge_bvec(mddev->queue, raid10_mergeable_bvec);
+ return 0;
+
+out_free_conf:
+ if (conf->r10bio_pool)
+ mempool_destroy(conf->r10bio_pool);
+ if (conf->mirrors)
+ kfree(conf->mirrors);
+ kfree(conf);
+ mddev->private = NULL;
+out:
+ return -EIO;
+}
+
+static int stop(mddev_t *mddev)
+{
+ conf_t *conf = mddev_to_conf(mddev);
+
+ md_unregister_thread(mddev->thread);
+ mddev->thread = NULL;
+ if (conf->r10bio_pool)
+ mempool_destroy(conf->r10bio_pool);
+ if (conf->mirrors)
+ kfree(conf->mirrors);
+ kfree(conf);
+ mddev->private = NULL;
+ return 0;
+}
+
+
+static mdk_personality_t raid10_personality =
+{
+ .name = "raid10",
+ .owner = THIS_MODULE,
+ .make_request = make_request,
+ .run = run,
+ .stop = stop,
+ .status = status,
+ .error_handler = error,
+ .hot_add_disk = raid10_add_disk,
+ .hot_remove_disk= raid10_remove_disk,
+ .spare_active = raid10_spare_active,
+ .sync_request = sync_request,
+};
+
+static int __init raid_init(void)
+{
+ return register_md_personality(RAID10, &raid10_personality);
+}
+
+static void raid_exit(void)
+{
+ unregister_md_personality(RAID10);
+}
+
+module_init(raid_init);
+module_exit(raid_exit);
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("md-personality-9"); /* RAID10 */
--- /dev/null
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/i2o.h>
+
+static int verbose;
+extern struct i2o_driver **i2o_drivers;
+extern unsigned int i2o_max_drivers;
+static void i2o_report_util_cmd(u8 cmd);
+static void i2o_report_exec_cmd(u8 cmd);
+void i2o_report_fail_status(u8 req_status, u32 * msg);
+void i2o_report_common_status(u8 req_status);
+static void i2o_report_common_dsc(u16 detailed_status);
+
+void i2o_dump_status_block(i2o_status_block * sb)
+{
+ pr_debug("Organization ID: %d\n", sb->org_id);
+ pr_debug("IOP ID: %d\n", sb->iop_id);
+ pr_debug("Host Unit ID: %d\n", sb->host_unit_id);
+ pr_debug("Segment Number: %d\n", sb->segment_number);
+ pr_debug("I2O Version: %d\n", sb->i2o_version);
+ pr_debug("IOP State: %d\n", sb->iop_state);
+ pr_debug("Messanger Type: %d\n", sb->msg_type);
+ pr_debug("Inbound Frame Size: %d\n", sb->inbound_frame_size);
+ pr_debug("Init Code: %d\n", sb->init_code);
+ pr_debug("Max Inbound MFrames: %d\n", sb->max_inbound_frames);
+ pr_debug("Current Inbound MFrames: %d\n", sb->cur_inbound_frames);
+ pr_debug("Max Outbound MFrames: %d\n", sb->max_outbound_frames);
+ pr_debug("Product ID String: %s\n", sb->product_id);
+ pr_debug("Expected LCT Size: %d\n", sb->expected_lct_size);
+ pr_debug("IOP Capabilities: %d\n", sb->iop_capabilities);
+ pr_debug("Desired Private MemSize: %d\n", sb->desired_mem_size);
+ pr_debug("Current Private MemSize: %d\n", sb->current_mem_size);
+ pr_debug("Current Private MemBase: %d\n", sb->current_mem_base);
+ pr_debug("Desired Private IO Size: %d\n", sb->desired_io_size);
+ pr_debug("Current Private IO Size: %d\n", sb->current_io_size);
+ pr_debug("Current Private IO Base: %d\n", sb->current_io_base);
+};
+
+/*
+ * Used for error reporting/debugging purposes.
+ * Report Cmd name, Request status, Detailed Status.
+ */
+void i2o_report_status(const char *severity, const char *str,
+ struct i2o_message *m)
+{
+ u32 *msg = (u32 *) m;
+ u8 cmd = (msg[1] >> 24) & 0xFF;
+ u8 req_status = (msg[4] >> 24) & 0xFF;
+ u16 detailed_status = msg[4] & 0xFFFF;
+ //struct i2o_driver *h = i2o_drivers[msg[2] & (i2o_max_drivers-1)];
+
+ if (cmd == I2O_CMD_UTIL_EVT_REGISTER)
+ return; // No status in this reply
+
+ printk("%s%s: ", severity, str);
+
+ if (cmd < 0x1F) // Utility cmd
+ i2o_report_util_cmd(cmd);
+
+ else if (cmd >= 0xA0 && cmd <= 0xEF) // Executive cmd
+ i2o_report_exec_cmd(cmd);
+ else
+ printk("Cmd = %0#2x, ", cmd); // Other cmds
+
+ if (msg[0] & MSG_FAIL) {
+ i2o_report_fail_status(req_status, msg);
+ return;
+ }
+
+ i2o_report_common_status(req_status);
+
+ if (cmd < 0x1F || (cmd >= 0xA0 && cmd <= 0xEF))
+ i2o_report_common_dsc(detailed_status);
+ else
+ printk(" / DetailedStatus = %0#4x.\n", detailed_status);
+}
+
+/* Used to dump a message to syslog during debugging */
+void i2o_dump_message(struct i2o_message *m)
+{
+#ifdef DEBUG
+ u32 *msg = (u32 *) m;
+ int i;
+ printk(KERN_INFO "Dumping I2O message size %d @ %p\n",
+ msg[0] >> 16 & 0xffff, msg);
+ for (i = 0; i < ((msg[0] >> 16) & 0xffff); i++)
+ printk(KERN_INFO " msg[%d] = %0#10x\n", i, msg[i]);
+#endif
+}
+
+/**
+ * i2o_report_controller_unit - print information about a tid
+ * @c: controller
+ * @d: device
+ *
+ * Dump an information block associated with a given unit (TID). The
+ * tables are read and a block of text is output to printk that is
+ * formatted intended for the user.
+ */
+
+void i2o_report_controller_unit(struct i2o_controller *c, struct i2o_device *d)
+{
+ char buf[64];
+ char str[22];
+ int ret;
+
+ if (verbose == 0)
+ return;
+
+ printk(KERN_INFO "Target ID %03x.\n", d->lct_data.tid);
+ if ((ret = i2o_parm_field_get(d, 0xF100, 3, buf, 16)) >= 0) {
+ buf[16] = 0;
+ printk(KERN_INFO " Vendor: %s\n", buf);
+ }
+ if ((ret = i2o_parm_field_get(d, 0xF100, 4, buf, 16)) >= 0) {
+ buf[16] = 0;
+ printk(KERN_INFO " Device: %s\n", buf);
+ }
+ if (i2o_parm_field_get(d, 0xF100, 5, buf, 16) >= 0) {
+ buf[16] = 0;
+ printk(KERN_INFO " Description: %s\n", buf);
+ }
+ if ((ret = i2o_parm_field_get(d, 0xF100, 6, buf, 8)) >= 0) {
+ buf[8] = 0;
+ printk(KERN_INFO " Rev: %s\n", buf);
+ }
+
+ printk(KERN_INFO " Class: ");
+ //sprintf(str, "%-21s", i2o_get_class_name(d->lct_data.class_id));
+ printk("%s\n", str);
+
+ printk(KERN_INFO " Subclass: 0x%04X\n", d->lct_data.sub_class);
+ printk(KERN_INFO " Flags: ");
+
+ if (d->lct_data.device_flags & (1 << 0))
+ printk("C"); // ConfigDialog requested
+ if (d->lct_data.device_flags & (1 << 1))
+ printk("U"); // Multi-user capable
+ if (!(d->lct_data.device_flags & (1 << 4)))
+ printk("P"); // Peer service enabled!
+ if (!(d->lct_data.device_flags & (1 << 5)))
+ printk("M"); // Mgmt service enabled!
+ printk("\n");
+}
+
+/*
+MODULE_PARM(verbose, "i");
+MODULE_PARM_DESC(verbose, "Verbose diagnostics");
+*/
+/*
+ * Used for error reporting/debugging purposes.
+ * Following fail status are common to all classes.
+ * The preserved message must be handled in the reply handler.
+ */
+void i2o_report_fail_status(u8 req_status, u32 * msg)
+{
+ static char *FAIL_STATUS[] = {
+ "0x80", /* not used */
+ "SERVICE_SUSPENDED", /* 0x81 */
+ "SERVICE_TERMINATED", /* 0x82 */
+ "CONGESTION",
+ "FAILURE",
+ "STATE_ERROR",
+ "TIME_OUT",
+ "ROUTING_FAILURE",
+ "INVALID_VERSION",
+ "INVALID_OFFSET",
+ "INVALID_MSG_FLAGS",
+ "FRAME_TOO_SMALL",
+ "FRAME_TOO_LARGE",
+ "INVALID_TARGET_ID",
+ "INVALID_INITIATOR_ID",
+ "INVALID_INITIATOR_CONTEX", /* 0x8F */
+ "UNKNOWN_FAILURE" /* 0xFF */
+ };
+
+ if (req_status == I2O_FSC_TRANSPORT_UNKNOWN_FAILURE)
+ printk("TRANSPORT_UNKNOWN_FAILURE (%0#2x)\n.", req_status);
+ else
+ printk("TRANSPORT_%s.\n", FAIL_STATUS[req_status & 0x0F]);
+
+ /* Dump some details */
+
+ printk(KERN_ERR " InitiatorId = %d, TargetId = %d\n",
+ (msg[1] >> 12) & 0xFFF, msg[1] & 0xFFF);
+ printk(KERN_ERR " LowestVersion = 0x%02X, HighestVersion = 0x%02X\n",
+ (msg[4] >> 8) & 0xFF, msg[4] & 0xFF);
+ printk(KERN_ERR " FailingHostUnit = 0x%04X, FailingIOP = 0x%03X\n",
+ msg[5] >> 16, msg[5] & 0xFFF);
+
+ printk(KERN_ERR " Severity: 0x%02X ", (msg[4] >> 16) & 0xFF);
+ if (msg[4] & (1 << 16))
+ printk("(FormatError), "
+ "this msg can never be delivered/processed.\n");
+ if (msg[4] & (1 << 17))
+ printk("(PathError), "
+ "this msg can no longer be delivered/processed.\n");
+ if (msg[4] & (1 << 18))
+ printk("(PathState), "
+ "the system state does not allow delivery.\n");
+ if (msg[4] & (1 << 19))
+ printk("(Congestion), resources temporarily not available;"
+ "do not retry immediately.\n");
+}
+
+/*
+ * Used for error reporting/debugging purposes.
+ * Following reply status are common to all classes.
+ */
+void i2o_report_common_status(u8 req_status)
+{
+ static char *REPLY_STATUS[] = {
+ "SUCCESS",
+ "ABORT_DIRTY",
+ "ABORT_NO_DATA_TRANSFER",
+ "ABORT_PARTIAL_TRANSFER",
+ "ERROR_DIRTY",
+ "ERROR_NO_DATA_TRANSFER",
+ "ERROR_PARTIAL_TRANSFER",
+ "PROCESS_ABORT_DIRTY",
+ "PROCESS_ABORT_NO_DATA_TRANSFER",
+ "PROCESS_ABORT_PARTIAL_TRANSFER",
+ "TRANSACTION_ERROR",
+ "PROGRESS_REPORT"
+ };
+
+ if (req_status >= ARRAY_SIZE(REPLY_STATUS))
+ printk("RequestStatus = %0#2x", req_status);
+ else
+ printk("%s", REPLY_STATUS[req_status]);
+}
+
+/*
+ * Used for error reporting/debugging purposes.
+ * Following detailed status are valid for executive class,
+ * utility class, DDM class and for transaction error replies.
+ */
+static void i2o_report_common_dsc(u16 detailed_status)
+{
+ static char *COMMON_DSC[] = {
+ "SUCCESS",
+ "0x01", // not used
+ "BAD_KEY",
+ "TCL_ERROR",
+ "REPLY_BUFFER_FULL",
+ "NO_SUCH_PAGE",
+ "INSUFFICIENT_RESOURCE_SOFT",
+ "INSUFFICIENT_RESOURCE_HARD",
+ "0x08", // not used
+ "CHAIN_BUFFER_TOO_LARGE",
+ "UNSUPPORTED_FUNCTION",
+ "DEVICE_LOCKED",
+ "DEVICE_RESET",
+ "INAPPROPRIATE_FUNCTION",
+ "INVALID_INITIATOR_ADDRESS",
+ "INVALID_MESSAGE_FLAGS",
+ "INVALID_OFFSET",
+ "INVALID_PARAMETER",
+ "INVALID_REQUEST",
+ "INVALID_TARGET_ADDRESS",
+ "MESSAGE_TOO_LARGE",
+ "MESSAGE_TOO_SMALL",
+ "MISSING_PARAMETER",
+ "TIMEOUT",
+ "UNKNOWN_ERROR",
+ "UNKNOWN_FUNCTION",
+ "UNSUPPORTED_VERSION",
+ "DEVICE_BUSY",
+ "DEVICE_NOT_AVAILABLE"
+ };
+
+ if (detailed_status > I2O_DSC_DEVICE_NOT_AVAILABLE)
+ printk(" / DetailedStatus = %0#4x.\n", detailed_status);
+ else
+ printk(" / %s.\n", COMMON_DSC[detailed_status]);
+}
+
+/*
+ * Used for error reporting/debugging purposes
+ */
+static void i2o_report_util_cmd(u8 cmd)
+{
+ switch (cmd) {
+ case I2O_CMD_UTIL_NOP:
+ printk("UTIL_NOP, ");
+ break;
+ case I2O_CMD_UTIL_ABORT:
+ printk("UTIL_ABORT, ");
+ break;
+ case I2O_CMD_UTIL_CLAIM:
+ printk("UTIL_CLAIM, ");
+ break;
+ case I2O_CMD_UTIL_RELEASE:
+ printk("UTIL_CLAIM_RELEASE, ");
+ break;
+ case I2O_CMD_UTIL_CONFIG_DIALOG:
+ printk("UTIL_CONFIG_DIALOG, ");
+ break;
+ case I2O_CMD_UTIL_DEVICE_RESERVE:
+ printk("UTIL_DEVICE_RESERVE, ");
+ break;
+ case I2O_CMD_UTIL_DEVICE_RELEASE:
+ printk("UTIL_DEVICE_RELEASE, ");
+ break;
+ case I2O_CMD_UTIL_EVT_ACK:
+ printk("UTIL_EVENT_ACKNOWLEDGE, ");
+ break;
+ case I2O_CMD_UTIL_EVT_REGISTER:
+ printk("UTIL_EVENT_REGISTER, ");
+ break;
+ case I2O_CMD_UTIL_LOCK:
+ printk("UTIL_LOCK, ");
+ break;
+ case I2O_CMD_UTIL_LOCK_RELEASE:
+ printk("UTIL_LOCK_RELEASE, ");
+ break;
+ case I2O_CMD_UTIL_PARAMS_GET:
+ printk("UTIL_PARAMS_GET, ");
+ break;
+ case I2O_CMD_UTIL_PARAMS_SET:
+ printk("UTIL_PARAMS_SET, ");
+ break;
+ case I2O_CMD_UTIL_REPLY_FAULT_NOTIFY:
+ printk("UTIL_REPLY_FAULT_NOTIFY, ");
+ break;
+ default:
+ printk("Cmd = %0#2x, ", cmd);
+ }
+}
+
+/*
+ * Used for error reporting/debugging purposes
+ */
+static void i2o_report_exec_cmd(u8 cmd)
+{
+ switch (cmd) {
+ case I2O_CMD_ADAPTER_ASSIGN:
+ printk("EXEC_ADAPTER_ASSIGN, ");
+ break;
+ case I2O_CMD_ADAPTER_READ:
+ printk("EXEC_ADAPTER_READ, ");
+ break;
+ case I2O_CMD_ADAPTER_RELEASE:
+ printk("EXEC_ADAPTER_RELEASE, ");
+ break;
+ case I2O_CMD_BIOS_INFO_SET:
+ printk("EXEC_BIOS_INFO_SET, ");
+ break;
+ case I2O_CMD_BOOT_DEVICE_SET:
+ printk("EXEC_BOOT_DEVICE_SET, ");
+ break;
+ case I2O_CMD_CONFIG_VALIDATE:
+ printk("EXEC_CONFIG_VALIDATE, ");
+ break;
+ case I2O_CMD_CONN_SETUP:
+ printk("EXEC_CONN_SETUP, ");
+ break;
+ case I2O_CMD_DDM_DESTROY:
+ printk("EXEC_DDM_DESTROY, ");
+ break;
+ case I2O_CMD_DDM_ENABLE:
+ printk("EXEC_DDM_ENABLE, ");
+ break;
+ case I2O_CMD_DDM_QUIESCE:
+ printk("EXEC_DDM_QUIESCE, ");
+ break;
+ case I2O_CMD_DDM_RESET:
+ printk("EXEC_DDM_RESET, ");
+ break;
+ case I2O_CMD_DDM_SUSPEND:
+ printk("EXEC_DDM_SUSPEND, ");
+ break;
+ case I2O_CMD_DEVICE_ASSIGN:
+ printk("EXEC_DEVICE_ASSIGN, ");
+ break;
+ case I2O_CMD_DEVICE_RELEASE:
+ printk("EXEC_DEVICE_RELEASE, ");
+ break;
+ case I2O_CMD_HRT_GET:
+ printk("EXEC_HRT_GET, ");
+ break;
+ case I2O_CMD_ADAPTER_CLEAR:
+ printk("EXEC_IOP_CLEAR, ");
+ break;
+ case I2O_CMD_ADAPTER_CONNECT:
+ printk("EXEC_IOP_CONNECT, ");
+ break;
+ case I2O_CMD_ADAPTER_RESET:
+ printk("EXEC_IOP_RESET, ");
+ break;
+ case I2O_CMD_LCT_NOTIFY:
+ printk("EXEC_LCT_NOTIFY, ");
+ break;
+ case I2O_CMD_OUTBOUND_INIT:
+ printk("EXEC_OUTBOUND_INIT, ");
+ break;
+ case I2O_CMD_PATH_ENABLE:
+ printk("EXEC_PATH_ENABLE, ");
+ break;
+ case I2O_CMD_PATH_QUIESCE:
+ printk("EXEC_PATH_QUIESCE, ");
+ break;
+ case I2O_CMD_PATH_RESET:
+ printk("EXEC_PATH_RESET, ");
+ break;
+ case I2O_CMD_STATIC_MF_CREATE:
+ printk("EXEC_STATIC_MF_CREATE, ");
+ break;
+ case I2O_CMD_STATIC_MF_RELEASE:
+ printk("EXEC_STATIC_MF_RELEASE, ");
+ break;
+ case I2O_CMD_STATUS_GET:
+ printk("EXEC_STATUS_GET, ");
+ break;
+ case I2O_CMD_SW_DOWNLOAD:
+ printk("EXEC_SW_DOWNLOAD, ");
+ break;
+ case I2O_CMD_SW_UPLOAD:
+ printk("EXEC_SW_UPLOAD, ");
+ break;
+ case I2O_CMD_SW_REMOVE:
+ printk("EXEC_SW_REMOVE, ");
+ break;
+ case I2O_CMD_SYS_ENABLE:
+ printk("EXEC_SYS_ENABLE, ");
+ break;
+ case I2O_CMD_SYS_MODIFY:
+ printk("EXEC_SYS_MODIFY, ");
+ break;
+ case I2O_CMD_SYS_QUIESCE:
+ printk("EXEC_SYS_QUIESCE, ");
+ break;
+ case I2O_CMD_SYS_TAB_SET:
+ printk("EXEC_SYS_TAB_SET, ");
+ break;
+ default:
+ printk("Cmd = %#02x, ", cmd);
+ }
+}
+
+void i2o_debug_state(struct i2o_controller *c)
+{
+ printk(KERN_INFO "%s: State = ", c->name);
+ switch (((i2o_status_block *) c->status_block.virt)->iop_state) {
+ case 0x01:
+ printk("INIT\n");
+ break;
+ case 0x02:
+ printk("RESET\n");
+ break;
+ case 0x04:
+ printk("HOLD\n");
+ break;
+ case 0x05:
+ printk("READY\n");
+ break;
+ case 0x08:
+ printk("OPERATIONAL\n");
+ break;
+ case 0x10:
+ printk("FAILED\n");
+ break;
+ case 0x11:
+ printk("FAULTED\n");
+ break;
+ default:
+ printk("%x (unknown !!)\n",
+ ((i2o_status_block *) c->status_block.virt)->iop_state);
+ }
+};
+
+void i2o_systab_debug(struct i2o_sys_tbl *sys_tbl)
+{
+ u32 *table;
+ int count;
+ u32 size;
+
+ table = (u32 *) sys_tbl;
+ size = sizeof(struct i2o_sys_tbl) + sys_tbl->num_entries
+ * sizeof(struct i2o_sys_tbl_entry);
+
+ for (count = 0; count < (size >> 2); count++)
+ printk(KERN_INFO "sys_tbl[%d] = %0#10x\n", count, table[count]);
+}
+
+void i2o_dump_hrt(struct i2o_controller *c)
+{
+ u32 *rows = (u32 *) c->hrt.virt;
+ u8 *p = (u8 *) c->hrt.virt;
+ u8 *d;
+ int count;
+ int length;
+ int i;
+ int state;
+
+ if (p[3] != 0) {
+ printk(KERN_ERR
+ "%s: HRT table for controller is too new a version.\n",
+ c->name);
+ return;
+ }
+
+ count = p[0] | (p[1] << 8);
+ length = p[2];
+
+ printk(KERN_INFO "%s: HRT has %d entries of %d bytes each.\n",
+ c->name, count, length << 2);
+
+ rows += 2;
+
+ for (i = 0; i < count; i++) {
+ printk(KERN_INFO "Adapter %08X: ", rows[0]);
+ p = (u8 *) (rows + 1);
+ d = (u8 *) (rows + 2);
+ state = p[1] << 8 | p[0];
+
+ printk("TID %04X:[", state & 0xFFF);
+ state >>= 12;
+ if (state & (1 << 0))
+ printk("H"); /* Hidden */
+ if (state & (1 << 2)) {
+ printk("P"); /* Present */
+ if (state & (1 << 1))
+ printk("C"); /* Controlled */
+ }
+ if (state > 9)
+ printk("*"); /* Hard */
+
+ printk("]:");
+
+ switch (p[3] & 0xFFFF) {
+ case 0:
+ /* Adapter private bus - easy */
+ printk("Local bus %d: I/O at 0x%04X Mem 0x%08X",
+ p[2], d[1] << 8 | d[0], *(u32 *) (d + 4));
+ break;
+ case 1:
+ /* ISA bus */
+ printk("ISA %d: CSN %d I/O at 0x%04X Mem 0x%08X",
+ p[2], d[2], d[1] << 8 | d[0], *(u32 *) (d + 4));
+ break;
+
+ case 2: /* EISA bus */
+ printk("EISA %d: Slot %d I/O at 0x%04X Mem 0x%08X",
+ p[2], d[3], d[1] << 8 | d[0], *(u32 *) (d + 4));
+ break;
+
+ case 3: /* MCA bus */
+ printk("MCA %d: Slot %d I/O at 0x%04X Mem 0x%08X",
+ p[2], d[3], d[1] << 8 | d[0], *(u32 *) (d + 4));
+ break;
+
+ case 4: /* PCI bus */
+ printk("PCI %d: Bus %d Device %d Function %d",
+ p[2], d[2], d[1], d[0]);
+ break;
+
+ case 0x80: /* Other */
+ default:
+ printk("Unsupported bus type.");
+ break;
+ }
+ printk("\n");
+ rows += length;
+ }
+}
+
+EXPORT_SYMBOL(i2o_dump_status_block);
+EXPORT_SYMBOL(i2o_dump_message);
--- /dev/null
+/*
+ * Functions to handle I2O devices
+ *
+ * Copyright (C) 2004 Markus Lidel <Markus.Lidel@shadowconnect.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Fixes/additions:
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>
+ * initial version.
+ */
+
+#include <linux/module.h>
+#include <linux/i2o.h>
+
+/* Exec OSM functions */
+extern struct bus_type i2o_bus_type;
+
+/**
+ * i2o_device_issue_claim - claim or release a device
+ * @dev: I2O device to claim or release
+ * @cmd: claim or release command
+ * @type: type of claim
+ *
+ * Issue I2O UTIL_CLAIM or UTIL_RELEASE messages. The message to be sent
+ * is set by cmd. dev is the I2O device which should be claim or
+ * released and the type is the claim type (see the I2O spec).
+ *
+ * Returs 0 on success or negative error code on failure.
+ */
+static inline int i2o_device_issue_claim(struct i2o_device *dev, u32 cmd,
+ u32 type)
+{
+ struct i2o_message *msg;
+ u32 m;
+
+ m = i2o_msg_get_wait(dev->iop, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(FIVE_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(cmd << 24 | HOST_TID << 12 | dev->lct_data.tid, &msg->u.head[1]);
+ writel(type, &msg->body[0]);
+
+ return i2o_msg_post_wait(dev->iop, m, 60);
+};
+
+/**
+ * i2o_device_claim - claim a device for use by an OSM
+ * @dev: I2O device to claim
+ * @drv: I2O driver which wants to claim the device
+ *
+ * Do the leg work to assign a device to a given OSM. If the claim succeed
+ * the owner of the rimary. If the attempt fails a negative errno code
+ * is returned. On success zero is returned.
+ */
+int i2o_device_claim(struct i2o_device *dev)
+{
+ int rc = 0;
+
+ down(&dev->lock);
+
+ rc = i2o_device_issue_claim(dev, I2O_CMD_UTIL_CLAIM, I2O_CLAIM_PRIMARY);
+ if (!rc)
+ pr_debug("claim of device %d succeded\n", dev->lct_data.tid);
+ else
+ pr_debug("claim of device %d failed %d\n", dev->lct_data.tid,
+ rc);
+
+ up(&dev->lock);
+
+ return rc;
+};
+
+/**
+ * i2o_device_claim_release - release a device that the OSM is using
+ * @dev: device to release
+ * @drv: driver which claimed the device
+ *
+ * Drop a claim by an OSM on a given I2O device.
+ *
+ * AC - some devices seem to want to refuse an unclaim until they have
+ * finished internal processing. It makes sense since you don't want a
+ * new device to go reconfiguring the entire system until you are done.
+ * Thus we are prepared to wait briefly.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_device_claim_release(struct i2o_device *dev)
+{
+ int tries;
+ int rc = 0;
+
+ down(&dev->lock);
+
+ /*
+ * If the controller takes a nonblocking approach to
+ * releases we have to sleep/poll for a few times.
+ */
+ for (tries = 0; tries < 10; tries++) {
+ rc = i2o_device_issue_claim(dev, I2O_CMD_UTIL_RELEASE,
+ I2O_CLAIM_PRIMARY);
+ if (!rc)
+ break;
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ);
+ }
+
+ if (!rc)
+ pr_debug("claim release of device %d succeded\n",
+ dev->lct_data.tid);
+ else
+ pr_debug("claim release of device %d failed %d\n",
+ dev->lct_data.tid, rc);
+
+ up(&dev->lock);
+
+ return rc;
+};
+
+/**
+ * i2o_device_release - release the memory for a I2O device
+ * @dev: I2O device which should be released
+ *
+ * Release the allocated memory. This function is called if refcount of
+ * device reaches 0 automatically.
+ */
+static void i2o_device_release(struct device *dev)
+{
+ struct i2o_device *i2o_dev = to_i2o_device(dev);
+
+ pr_debug("Release I2O device %s\n", dev->bus_id);
+
+ kfree(i2o_dev);
+};
+
+/**
+ * i2o_device_class_release - Remove I2O device attributes
+ * @cd: I2O class device which is added to the I2O device class
+ *
+ * Removes attributes from the I2O device again. Also search each device
+ * on the controller for I2O devices which refert to this device as parent
+ * or user and remove this links also.
+ */
+static void i2o_device_class_release(struct class_device *cd)
+{
+ struct i2o_device *i2o_dev, *tmp;
+ struct i2o_controller *c;
+
+ i2o_dev = to_i2o_device(cd->dev);
+ c = i2o_dev->iop;
+
+ sysfs_remove_link(&i2o_dev->device.kobj, "parent");
+ sysfs_remove_link(&i2o_dev->device.kobj, "user");
+
+ list_for_each_entry(tmp, &c->devices, list) {
+ if (tmp->lct_data.parent_tid == i2o_dev->lct_data.tid)
+ sysfs_remove_link(&tmp->device.kobj, "parent");
+ if (tmp->lct_data.user_tid == i2o_dev->lct_data.tid)
+ sysfs_remove_link(&tmp->device.kobj, "user");
+ }
+};
+
+/* I2O device class */
+static struct class i2o_device_class = {
+ .name = "i2o_device",
+ .release = i2o_device_class_release
+};
+
+/**
+ * i2o_device_alloc - Allocate a I2O device and initialize it
+ *
+ * Allocate the memory for a I2O device and initialize locks and lists
+ *
+ * Returns the allocated I2O device or a negative error code if the device
+ * could not be allocated.
+ */
+static struct i2o_device *i2o_device_alloc(void)
+{
+ struct i2o_device *dev;
+
+ dev = kmalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ memset(dev, 0, sizeof(*dev));
+
+ INIT_LIST_HEAD(&dev->list);
+ init_MUTEX(&dev->lock);
+
+ dev->device.bus = &i2o_bus_type;
+ dev->device.release = &i2o_device_release;
+ dev->classdev.class = &i2o_device_class;
+ dev->classdev.dev = &dev->device;
+
+ return dev;
+};
+
+/**
+ * i2o_device_add - allocate a new I2O device and add it to the IOP
+ * @iop: I2O controller where the device is on
+ * @entry: LCT entry of the I2O device
+ *
+ * Allocate a new I2O device and initialize it with the LCT entry. The
+ * device is appended to the device list of the controller.
+ *
+ * Returns a pointer to the I2O device on success or negative error code
+ * on failure.
+ */
+struct i2o_device *i2o_device_add(struct i2o_controller *c,
+ i2o_lct_entry * entry)
+{
+ struct i2o_device *dev;
+
+ dev = i2o_device_alloc();
+ if (IS_ERR(dev)) {
+ printk(KERN_ERR "i2o: unable to allocate i2o device\n");
+ return dev;
+ }
+
+ dev->lct_data = *entry;
+
+ snprintf(dev->device.bus_id, BUS_ID_SIZE, "%d:%03x", c->unit,
+ dev->lct_data.tid);
+
+ snprintf(dev->classdev.class_id, BUS_ID_SIZE, "%d:%03x", c->unit,
+ dev->lct_data.tid);
+
+ dev->iop = c;
+ dev->device.parent = &c->device;
+
+ device_register(&dev->device);
+
+ list_add_tail(&dev->list, &c->devices);
+
+ class_device_register(&dev->classdev);
+
+ i2o_driver_notify_device_add_all(dev);
+
+ pr_debug("I2O device %s added\n", dev->device.bus_id);
+
+ return dev;
+};
+
+/**
+ * i2o_device_remove - remove an I2O device from the I2O core
+ * @dev: I2O device which should be released
+ *
+ * Is used on I2O controller removal or LCT modification, when the device
+ * is removed from the system. Note that the device could still hang
+ * around until the refcount reaches 0.
+ */
+void i2o_device_remove(struct i2o_device *i2o_dev)
+{
+ i2o_driver_notify_device_remove_all(i2o_dev);
+ class_device_unregister(&i2o_dev->classdev);
+ list_del(&i2o_dev->list);
+ device_unregister(&i2o_dev->device);
+};
+
+/**
+ * i2o_device_parse_lct - Parse a previously fetched LCT and create devices
+ * @c: I2O controller from which the LCT should be parsed.
+ *
+ * The Logical Configuration Table tells us what we can talk to on the
+ * board. For every entry we create an I2O device, which is registered in
+ * the I2O core.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_device_parse_lct(struct i2o_controller *c)
+{
+ struct i2o_device *dev, *tmp;
+ i2o_lct *lct;
+ int i;
+ int max;
+
+ down(&c->lct_lock);
+
+ if (c->lct)
+ kfree(c->lct);
+
+ lct = c->dlct.virt;
+
+ c->lct = kmalloc(lct->table_size * 4, GFP_KERNEL);
+ if (!c->lct) {
+ up(&c->lct_lock);
+ return -ENOMEM;
+ }
+
+ if (lct->table_size * 4 > c->dlct.len) {
+ memcpy_fromio(c->lct, c->dlct.virt, c->dlct.len);
+ up(&c->lct_lock);
+ return -EAGAIN;
+ }
+
+ memcpy_fromio(c->lct, c->dlct.virt, lct->table_size * 4);
+
+ lct = c->lct;
+
+ max = (lct->table_size - 3) / 9;
+
+ pr_debug("LCT has %d entries (LCT size: %d)\n", max, lct->table_size);
+
+ /* remove devices, which are not in the LCT anymore */
+ list_for_each_entry_safe(dev, tmp, &c->devices, list) {
+ int found = 0;
+
+ for (i = 0; i < max; i++) {
+ if (lct->lct_entry[i].tid == dev->lct_data.tid) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ i2o_device_remove(dev);
+ }
+
+ /* add new devices, which are new in the LCT */
+ for (i = 0; i < max; i++) {
+ int found = 0;
+
+ list_for_each_entry_safe(dev, tmp, &c->devices, list) {
+ if (lct->lct_entry[i].tid == dev->lct_data.tid) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ i2o_device_add(c, &lct->lct_entry[i]);
+ }
+ up(&c->lct_lock);
+
+ return 0;
+};
+
+/**
+ * i2o_device_class_show_class_id - Displays class id of I2O device
+ * @cd: class device of which the class id should be displayed
+ * @buf: buffer into which the class id should be printed
+ *
+ * Returns the number of bytes which are printed into the buffer.
+ */
+static ssize_t i2o_device_class_show_class_id(struct class_device *cd,
+ char *buf)
+{
+ struct i2o_device *dev = to_i2o_device(cd->dev);
+
+ sprintf(buf, "%03x\n", dev->lct_data.class_id);
+ return strlen(buf) + 1;
+};
+
+/**
+ * i2o_device_class_show_tid - Displays TID of I2O device
+ * @cd: class device of which the TID should be displayed
+ * @buf: buffer into which the class id should be printed
+ *
+ * Returns the number of bytes which are printed into the buffer.
+ */
+static ssize_t i2o_device_class_show_tid(struct class_device *cd, char *buf)
+{
+ struct i2o_device *dev = to_i2o_device(cd->dev);
+
+ sprintf(buf, "%03x\n", dev->lct_data.tid);
+ return strlen(buf) + 1;
+};
+
+/* I2O device class attributes */
+static CLASS_DEVICE_ATTR(class_id, S_IRUGO, i2o_device_class_show_class_id,
+ NULL);
+static CLASS_DEVICE_ATTR(tid, S_IRUGO, i2o_device_class_show_tid, NULL);
+
+/**
+ * i2o_device_class_add - Adds attributes to the I2O device
+ * @cd: I2O class device which is added to the I2O device class
+ *
+ * This function get called when a I2O device is added to the class. It
+ * creates the attributes for each device and creates user/parent symlink
+ * if necessary.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_device_class_add(struct class_device *cd)
+{
+ struct i2o_device *i2o_dev, *tmp;
+ struct i2o_controller *c;
+
+ i2o_dev = to_i2o_device(cd->dev);
+ c = i2o_dev->iop;
+
+ class_device_create_file(cd, &class_device_attr_class_id);
+ class_device_create_file(cd, &class_device_attr_tid);
+
+ /* create user entries for this device */
+ tmp = i2o_iop_find_device(i2o_dev->iop, i2o_dev->lct_data.user_tid);
+ if (tmp)
+ sysfs_create_link(&i2o_dev->device.kobj, &tmp->device.kobj,
+ "user");
+
+ /* create user entries refering to this device */
+ list_for_each_entry(tmp, &c->devices, list)
+ if (tmp->lct_data.user_tid == i2o_dev->lct_data.tid)
+ sysfs_create_link(&tmp->device.kobj,
+ &i2o_dev->device.kobj, "user");
+
+ /* create parent entries for this device */
+ tmp = i2o_iop_find_device(i2o_dev->iop, i2o_dev->lct_data.parent_tid);
+ if (tmp)
+ sysfs_create_link(&i2o_dev->device.kobj, &tmp->device.kobj,
+ "parent");
+
+ /* create parent entries refering to this device */
+ list_for_each_entry(tmp, &c->devices, list)
+ if (tmp->lct_data.parent_tid == i2o_dev->lct_data.tid)
+ sysfs_create_link(&tmp->device.kobj,
+ &i2o_dev->device.kobj, "parent");
+
+ return 0;
+};
+
+/* I2O device class interface */
+static struct class_interface i2o_device_class_interface = {
+ .class = &i2o_device_class,
+ .add = i2o_device_class_add
+};
+
+/*
+ * Run time support routines
+ */
+
+/* Issue UTIL_PARAMS_GET or UTIL_PARAMS_SET
+ *
+ * This function can be used for all UtilParamsGet/Set operations.
+ * The OperationList is given in oplist-buffer,
+ * and results are returned in reslist-buffer.
+ * Note that the minimum sized reslist is 8 bytes and contains
+ * ResultCount, ErrorInfoSize, BlockStatus and BlockSize.
+ */
+
+int i2o_parm_issue(struct i2o_device *i2o_dev, int cmd, void *oplist,
+ int oplen, void *reslist, int reslen)
+{
+ struct i2o_message *msg;
+ u32 m;
+ u32 *res32 = (u32 *) reslist;
+ u32 *restmp = (u32 *) reslist;
+ int len = 0;
+ int i = 0;
+ int rc;
+ struct i2o_dma res;
+ struct i2o_controller *c = i2o_dev->iop;
+ struct device *dev = &c->pdev->dev;
+
+ res.virt = NULL;
+
+ if (i2o_dma_alloc(dev, &res, reslen, GFP_KERNEL))
+ return -ENOMEM;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY) {
+ i2o_dma_free(dev, &res);
+ return -ETIMEDOUT;
+ }
+
+ i = 0;
+ writel(cmd << 24 | HOST_TID << 12 | i2o_dev->lct_data.tid,
+ &msg->u.head[1]);
+ writel(0, &msg->body[i++]);
+ writel(0x4C000000 | oplen, &msg->body[i++]); /* OperationList */
+ memcpy_toio(&msg->body[i], oplist, oplen);
+ i += (oplen / 4 + (oplen % 4 ? 1 : 0));
+ writel(0xD0000000 | res.len, &msg->body[i++]); /* ResultList */
+ writel(res.phys, &msg->body[i++]);
+
+ writel(I2O_MESSAGE_SIZE(i + sizeof(struct i2o_message) / 4) |
+ SGL_OFFSET_5, &msg->u.head[0]);
+
+ rc = i2o_msg_post_wait_mem(c, m, 10, &res);
+
+ /* This only looks like a memory leak - don't "fix" it. */
+ if (rc == -ETIMEDOUT)
+ return rc;
+
+ memcpy_fromio(reslist, res.virt, res.len);
+ i2o_dma_free(dev, &res);
+
+ /* Query failed */
+ if (rc)
+ return rc;
+ /*
+ * Calculate number of bytes of Result LIST
+ * We need to loop through each Result BLOCK and grab the length
+ */
+ restmp = res32 + 1;
+ len = 1;
+ for (i = 0; i < (res32[0] & 0X0000FFFF); i++) {
+ if (restmp[0] & 0x00FF0000) { /* BlockStatus != SUCCESS */
+ printk(KERN_WARNING
+ "%s - Error:\n ErrorInfoSize = 0x%02x, "
+ "BlockStatus = 0x%02x, BlockSize = 0x%04x\n",
+ (cmd ==
+ I2O_CMD_UTIL_PARAMS_SET) ? "PARAMS_SET" :
+ "PARAMS_GET", res32[1] >> 24,
+ (res32[1] >> 16) & 0xFF, res32[1] & 0xFFFF);
+
+ /*
+ * If this is the only request,than we return an error
+ */
+ if ((res32[0] & 0x0000FFFF) == 1) {
+ return -((res32[1] >> 16) & 0xFF); /* -BlockStatus */
+ }
+ }
+ len += restmp[0] & 0x0000FFFF; /* Length of res BLOCK */
+ restmp += restmp[0] & 0x0000FFFF; /* Skip to next BLOCK */
+ }
+ return (len << 2); /* bytes used by result list */
+}
+
+/*
+ * Query one field group value or a whole scalar group.
+ */
+int i2o_parm_field_get(struct i2o_device *i2o_dev, int group, int field,
+ void *buf, int buflen)
+{
+ u16 opblk[] = { 1, 0, I2O_PARAMS_FIELD_GET, group, 1, field };
+ u8 resblk[8 + buflen]; /* 8 bytes for header */
+ int size;
+
+ if (field == -1) /* whole group */
+ opblk[4] = -1;
+
+ size = i2o_parm_issue(i2o_dev, I2O_CMD_UTIL_PARAMS_GET, opblk,
+ sizeof(opblk), resblk, sizeof(resblk));
+
+ memcpy(buf, resblk + 8, buflen); /* cut off header */
+
+ if (size > buflen)
+ return buflen;
+
+ return size;
+}
+
+/*
+ * Set a scalar group value or a whole group.
+ */
+int i2o_parm_field_set(struct i2o_device *i2o_dev, int group, int field,
+ void *buf, int buflen)
+{
+ u16 *opblk;
+ u8 resblk[8 + buflen]; /* 8 bytes for header */
+ int size;
+
+ opblk = kmalloc(buflen + 64, GFP_KERNEL);
+ if (opblk == NULL) {
+ printk(KERN_ERR "i2o: no memory for operation buffer.\n");
+ return -ENOMEM;
+ }
+
+ opblk[0] = 1; /* operation count */
+ opblk[1] = 0; /* pad */
+ opblk[2] = I2O_PARAMS_FIELD_SET;
+ opblk[3] = group;
+
+ if (field == -1) { /* whole group */
+ opblk[4] = -1;
+ memcpy(opblk + 5, buf, buflen);
+ } else { /* single field */
+
+ opblk[4] = 1;
+ opblk[5] = field;
+ memcpy(opblk + 6, buf, buflen);
+ }
+
+ size = i2o_parm_issue(i2o_dev, I2O_CMD_UTIL_PARAMS_SET, opblk,
+ 12 + buflen, resblk, sizeof(resblk));
+
+ kfree(opblk);
+ if (size > buflen)
+ return buflen;
+
+ return size;
+}
+
+/*
+ * if oper == I2O_PARAMS_TABLE_GET, get from all rows
+ * if fieldcount == -1 return all fields
+ * ibuf and ibuflen are unused (use NULL, 0)
+ * else return specific fields
+ * ibuf contains fieldindexes
+ *
+ * if oper == I2O_PARAMS_LIST_GET, get from specific rows
+ * if fieldcount == -1 return all fields
+ * ibuf contains rowcount, keyvalues
+ * else return specific fields
+ * fieldcount is # of fieldindexes
+ * ibuf contains fieldindexes, rowcount, keyvalues
+ *
+ * You could also use directly function i2o_issue_params().
+ */
+int i2o_parm_table_get(struct i2o_device *dev, int oper, int group,
+ int fieldcount, void *ibuf, int ibuflen, void *resblk,
+ int reslen)
+{
+ u16 *opblk;
+ int size;
+
+ size = 10 + ibuflen;
+ if (size % 4)
+ size += 4 - size % 4;
+
+ opblk = kmalloc(size, GFP_KERNEL);
+ if (opblk == NULL) {
+ printk(KERN_ERR "i2o: no memory for query buffer.\n");
+ return -ENOMEM;
+ }
+
+ opblk[0] = 1; /* operation count */
+ opblk[1] = 0; /* pad */
+ opblk[2] = oper;
+ opblk[3] = group;
+ opblk[4] = fieldcount;
+ memcpy(opblk + 5, ibuf, ibuflen); /* other params */
+
+ size = i2o_parm_issue(dev, I2O_CMD_UTIL_PARAMS_GET, opblk,
+ size, resblk, reslen);
+
+ kfree(opblk);
+ if (size > reslen)
+ return reslen;
+
+ return size;
+}
+
+/**
+ * i2o_device_init - Initialize I2O devices
+ *
+ * Registers the I2O device class.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_device_init(void)
+{
+ int rc;
+
+ rc = class_register(&i2o_device_class);
+ if (rc)
+ return rc;
+
+ return class_interface_register(&i2o_device_class_interface);
+};
+
+/**
+ * i2o_device_exit - I2O devices exit function
+ *
+ * Unregisters the I2O device class.
+ */
+void i2o_device_exit(void)
+{
+ class_interface_register(&i2o_device_class_interface);
+ class_unregister(&i2o_device_class);
+};
+
+EXPORT_SYMBOL(i2o_device_claim);
+EXPORT_SYMBOL(i2o_device_claim_release);
+EXPORT_SYMBOL(i2o_parm_field_get);
+EXPORT_SYMBOL(i2o_parm_field_set);
+EXPORT_SYMBOL(i2o_parm_table_get);
+EXPORT_SYMBOL(i2o_parm_issue);
--- /dev/null
+/*
+ * Functions to handle I2O drivers (OSMs) and I2O bus type for sysfs
+ *
+ * Copyright (C) 2004 Markus Lidel <Markus.Lidel@shadowconnect.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Fixes/additions:
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>
+ * initial version.
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/rwsem.h>
+#include <linux/i2o.h>
+
+
+/* max_drivers - Maximum I2O drivers (OSMs) which could be registered */
+unsigned int i2o_max_drivers = I2O_MAX_DRIVERS;
+module_param_named(max_drivers, i2o_max_drivers, uint, 0);
+MODULE_PARM_DESC(max_drivers, "maximum number of OSM's to support");
+
+/* I2O drivers lock and array */
+static spinlock_t i2o_drivers_lock = SPIN_LOCK_UNLOCKED;
+static struct i2o_driver **i2o_drivers;
+
+/**
+ * i2o_bus_match - Tell if a I2O device class id match the class ids of
+ * the I2O driver (OSM)
+ *
+ * @dev: device which should be verified
+ * @drv: the driver to match against
+ *
+ * Used by the bus to check if the driver wants to handle the device.
+ *
+ * Returns 1 if the class ids of the driver match the class id of the
+ * device, otherwise 0.
+ */
+static int i2o_bus_match(struct device *dev, struct device_driver *drv)
+{
+ struct i2o_device *i2o_dev = to_i2o_device(dev);
+ struct i2o_driver *i2o_drv = to_i2o_driver(drv);
+ struct i2o_class_id *ids = i2o_drv->classes;
+
+ if (ids)
+ while (ids->class_id != I2O_CLASS_END) {
+ if (ids->class_id == i2o_dev->lct_data.class_id)
+ return 1;
+ ids++;
+ }
+ return 0;
+};
+
+/* I2O bus type */
+struct bus_type i2o_bus_type = {
+ .name = "i2o",
+ .match = i2o_bus_match,
+};
+
+/**
+ * i2o_driver_register - Register a I2O driver (OSM) in the I2O core
+ * @drv: I2O driver which should be registered
+ *
+ * Registers the OSM drv in the I2O core and creates an event queues if
+ * necessary.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_driver_register(struct i2o_driver *drv)
+{
+ struct i2o_controller *c;
+ int i;
+ int rc = 0;
+ unsigned long flags;
+
+ pr_debug("Register driver %s\n", drv->name);
+
+ if (drv->event) {
+ drv->event_queue = create_workqueue(drv->name);
+ if (!drv->event_queue) {
+ printk(KERN_ERR "i2o: Could not initialize event queue "
+ "for driver %s\n", drv->name);
+ return -EFAULT;
+ }
+ pr_debug("Event queue initialized for driver %s\n", drv->name);
+ } else
+ drv->event_queue = NULL;
+
+ drv->driver.name = drv->name;
+ drv->driver.bus = &i2o_bus_type;
+
+ spin_lock_irqsave(&i2o_drivers_lock, flags);
+
+ for (i = 0; i2o_drivers[i]; i++)
+ if (i >= i2o_max_drivers) {
+ printk(KERN_ERR "i2o: too many drivers registered, "
+ "increase max_drivers\n");
+ spin_unlock_irqrestore(&i2o_drivers_lock, flags);
+ return -EFAULT;
+ }
+
+ drv->context = i;
+ i2o_drivers[i] = drv;
+
+ spin_unlock_irqrestore(&i2o_drivers_lock, flags);
+
+ pr_debug("driver %s gets context id %d\n", drv->name, drv->context);
+
+ list_for_each_entry(c, &i2o_controllers, list) {
+ struct i2o_device *i2o_dev;
+
+ i2o_driver_notify_controller_add(drv, c);
+ list_for_each_entry(i2o_dev, &c->devices, list)
+ i2o_driver_notify_device_add(drv, i2o_dev);
+ }
+
+
+ rc = driver_register(&drv->driver);
+ if (rc)
+ destroy_workqueue(drv->event_queue);
+
+ return rc;
+};
+
+/**
+ * i2o_driver_unregister - Unregister a I2O driver (OSM) from the I2O core
+ * @drv: I2O driver which should be unregistered
+ *
+ * Unregisters the OSM drv from the I2O core and cleanup event queues if
+ * necessary.
+ */
+void i2o_driver_unregister(struct i2o_driver *drv)
+{
+ struct i2o_controller *c;
+ unsigned long flags;
+
+ pr_debug("unregister driver %s\n", drv->name);
+
+ driver_unregister(&drv->driver);
+
+ list_for_each_entry(c, &i2o_controllers, list) {
+ struct i2o_device *i2o_dev;
+
+ list_for_each_entry(i2o_dev, &c->devices, list)
+ i2o_driver_notify_device_remove(drv, i2o_dev);
+
+ i2o_driver_notify_controller_remove(drv, c);
+ }
+
+ spin_lock_irqsave(&i2o_drivers_lock, flags);
+ i2o_drivers[drv->context] = NULL;
+ spin_unlock_irqrestore(&i2o_drivers_lock, flags);
+
+ if (drv->event_queue) {
+ destroy_workqueue(drv->event_queue);
+ drv->event_queue = NULL;
+ pr_debug("event queue removed for %s\n", drv->name);
+ }
+};
+
+/**
+ * i2o_driver_dispatch - dispatch an I2O reply message
+ * @c: I2O controller of the message
+ * @m: I2O message number
+ * @msg: I2O message to be delivered
+ *
+ * The reply is delivered to the driver from which the original message
+ * was. This function is only called from interrupt context.
+ *
+ * Returns 0 on success and the message should not be flushed. Returns > 0
+ * on success and if the message should be flushed afterwords. Returns
+ * negative error code on failure (the message will be flushed too).
+ */
+int i2o_driver_dispatch(struct i2o_controller *c, u32 m,
+ struct i2o_message *msg)
+{
+ struct i2o_driver *drv;
+ u32 context = readl(&msg->u.s.icntxt);
+
+ if (likely(context < i2o_max_drivers)) {
+ spin_lock(&i2o_drivers_lock);
+ drv = i2o_drivers[context];
+ spin_unlock(&i2o_drivers_lock);
+
+ if (unlikely(!drv)) {
+ printk(KERN_WARNING "i2o: Spurious reply to unknown "
+ "driver %d\n", context);
+ return -EIO;
+ }
+
+ if ((readl(&msg->u.head[1]) >> 24) == I2O_CMD_UTIL_EVT_REGISTER) {
+ struct i2o_device *dev, *tmp;
+ struct i2o_event *evt;
+ u16 size;
+ u16 tid;
+
+ tid = readl(&msg->u.head[1]) & 0x1fff;
+
+ pr_debug("%s: event received from device %d\n", c->name,
+ tid);
+
+ /* cut of header from message size (in 32-bit words) */
+ size = (readl(&msg->u.head[0]) >> 16) - 5;
+
+ evt = kmalloc(size * 4 + sizeof(*evt), GFP_ATOMIC);
+ if (!evt)
+ return -ENOMEM;
+ memset(evt, 0, size * 4 + sizeof(*evt));
+
+ evt->size = size;
+ memcpy_fromio(&evt->tcntxt, &msg->u.s.tcntxt,
+ (size + 2) * 4);
+
+ list_for_each_entry_safe(dev, tmp, &c->devices, list)
+ if (dev->lct_data.tid == tid) {
+ evt->i2o_dev = dev;
+ break;
+ }
+
+ INIT_WORK(&evt->work, (void (*)(void *))drv->event,
+ evt);
+ queue_work(drv->event_queue, &evt->work);
+ return 1;
+ }
+
+ if (likely(drv->reply))
+ return drv->reply(c, m, msg);
+ else
+ pr_debug("%s: Reply to driver %s, but no reply function"
+ " defined!\n", c->name, drv->name);
+ return -EIO;
+ } else
+ printk(KERN_WARNING "i2o: Spurious reply to unknown driver "
+ "%d\n", readl(&msg->u.s.icntxt));
+ return -EIO;
+}
+
+/**
+ * i2o_driver_notify_controller_add_all - Send notify of added controller
+ * to all I2O drivers
+ *
+ * Send notifications to all registered drivers that a new controller was
+ * added.
+ */
+void i2o_driver_notify_controller_add_all(struct i2o_controller *c) {
+ int i;
+ struct i2o_driver *drv;
+
+ for(i = 0; i < I2O_MAX_DRIVERS; i ++) {
+ drv = i2o_drivers[i];
+
+ if(drv)
+ i2o_driver_notify_controller_add(drv, c);
+ }
+}
+
+/**
+ * i2o_driver_notify_controller_remove_all - Send notify of removed
+ * controller to all I2O drivers
+ *
+ * Send notifications to all registered drivers that a controller was
+ * removed.
+ */
+void i2o_driver_notify_controller_remove_all(struct i2o_controller *c) {
+ int i;
+ struct i2o_driver *drv;
+
+ for(i = 0; i < I2O_MAX_DRIVERS; i ++) {
+ drv = i2o_drivers[i];
+
+ if(drv)
+ i2o_driver_notify_controller_remove(drv, c);
+ }
+}
+
+/**
+ * i2o_driver_notify_device_add_all - Send notify of added device to all
+ * I2O drivers
+ *
+ * Send notifications to all registered drivers that a device was added.
+ */
+void i2o_driver_notify_device_add_all(struct i2o_device *i2o_dev) {
+ int i;
+ struct i2o_driver *drv;
+
+ for(i = 0; i < I2O_MAX_DRIVERS; i ++) {
+ drv = i2o_drivers[i];
+
+ if(drv)
+ i2o_driver_notify_device_add(drv, i2o_dev);
+ }
+}
+
+/**
+ * i2o_driver_notify_device_remove_all - Send notify of removed device to
+ * all I2O drivers
+ *
+ * Send notifications to all registered drivers that a device was removed.
+ */
+void i2o_driver_notify_device_remove_all(struct i2o_device *i2o_dev) {
+ int i;
+ struct i2o_driver *drv;
+
+ for(i = 0; i < I2O_MAX_DRIVERS; i ++) {
+ drv = i2o_drivers[i];
+
+ if(drv)
+ i2o_driver_notify_device_remove(drv, i2o_dev);
+ }
+}
+
+/**
+ * i2o_driver_init - initialize I2O drivers (OSMs)
+ *
+ * Registers the I2O bus and allocate memory for the array of OSMs.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int __init i2o_driver_init(void)
+{
+ int rc = 0;
+
+ if ((i2o_max_drivers < 2) || (i2o_max_drivers > 64) ||
+ ((i2o_max_drivers ^ (i2o_max_drivers - 1)) !=
+ (2 * i2o_max_drivers - 1))) {
+ printk(KERN_WARNING "i2o: max_drivers set to %d, but must be "
+ ">=2 and <= 64 and a power of 2\n", i2o_max_drivers);
+ i2o_max_drivers = I2O_MAX_DRIVERS;
+ }
+ printk(KERN_INFO "i2o: max_drivers=%d\n", i2o_max_drivers);
+
+ i2o_drivers =
+ kmalloc(i2o_max_drivers * sizeof(*i2o_drivers), GFP_KERNEL);
+ if (!i2o_drivers)
+ return -ENOMEM;
+
+ memset(i2o_drivers, 0, i2o_max_drivers * sizeof(*i2o_drivers));
+
+ rc = bus_register(&i2o_bus_type);
+
+ if (rc < 0)
+ kfree(i2o_drivers);
+
+ return rc;
+};
+
+/**
+ * i2o_driver_exit - clean up I2O drivers (OSMs)
+ *
+ * Unregisters the I2O bus and free driver array.
+ */
+void __exit i2o_driver_exit(void)
+{
+ bus_unregister(&i2o_bus_type);
+ kfree(i2o_drivers);
+};
+
+EXPORT_SYMBOL(i2o_driver_register);
+EXPORT_SYMBOL(i2o_driver_unregister);
+EXPORT_SYMBOL(i2o_driver_notify_controller_add_all);
+EXPORT_SYMBOL(i2o_driver_notify_controller_remove_all);
+EXPORT_SYMBOL(i2o_driver_notify_device_add_all);
+EXPORT_SYMBOL(i2o_driver_notify_device_remove_all);
--- /dev/null
+/*
+ * Executive OSM
+ *
+ * Copyright (C) 1999-2002 Red Hat Software
+ *
+ * Written by Alan Cox, Building Number Three Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * A lot of the I2O message side code from this is taken from the Red
+ * Creek RCPCI45 adapter driver by Red Creek Communications
+ *
+ * Fixes/additions:
+ * Philipp Rumpf
+ * Juha Sievänen <Juha.Sievanen@cs.Helsinki.FI>
+ * Auvo Häkkinen <Auvo.Hakkinen@cs.Helsinki.FI>
+ * Deepak Saxena <deepak@plexity.net>
+ * Boji T Kannanthanam <boji.t.kannanthanam@intel.com>
+ * Alan Cox <alan@redhat.com>:
+ * Ported to Linux 2.5.
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>:
+ * Minor fixes for 2.6.
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>:
+ * Support for sysfs included.
+ */
+
+#include <linux/module.h>
+#include <linux/i2o.h>
+
+struct i2o_driver i2o_exec_driver;
+
+/* Module internal functions from other sources */
+extern int i2o_device_parse_lct(struct i2o_controller *);
+
+/* global wait list for POST WAIT */
+static LIST_HEAD(i2o_exec_wait_list);
+
+/* Wait struct needed for POST WAIT */
+struct i2o_exec_wait {
+ wait_queue_head_t *wq; /* Pointer to Wait queue */
+ struct i2o_dma dma; /* DMA buffers to free on failure */
+ u32 tcntxt; /* transaction context from reply */
+ int complete; /* 1 if reply received otherwise 0 */
+ u32 m; /* message id */
+ struct i2o_message *msg; /* pointer to the reply message */
+ struct list_head list; /* node in global wait list */
+};
+
+/* Exec OSM class handling definition */
+static struct i2o_class_id i2o_exec_class_id[] = {
+ {I2O_CLASS_EXECUTIVE},
+ {I2O_CLASS_END}
+};
+
+/**
+ * i2o_exec_wait_alloc - Allocate a i2o_exec_wait struct an initialize it
+ *
+ * Allocate the i2o_exec_wait struct and initialize the wait.
+ *
+ * Returns i2o_exec_wait pointer on success or negative error code on
+ * failure.
+ */
+static struct i2o_exec_wait *i2o_exec_wait_alloc(void)
+{
+ struct i2o_exec_wait *wait;
+
+ wait = kmalloc(sizeof(*wait), GFP_KERNEL);
+ if (!wait)
+ return ERR_PTR(-ENOMEM);
+
+ memset(wait, 0, sizeof(*wait));
+
+ INIT_LIST_HEAD(&wait->list);
+
+ return wait;
+};
+
+/**
+ * i2o_exec_wait_free - Free a i2o_exec_wait struct
+ * @i2o_exec_wait: I2O wait data which should be cleaned up
+ */
+static void i2o_exec_wait_free(struct i2o_exec_wait *wait)
+{
+ kfree(wait);
+};
+
+/**
+ * i2o_msg_post_wait_mem - Post and wait a message with DMA buffers
+ * @c: controller
+ * @m: message to post
+ * @timeout: time in seconds to wait
+ * @dma: i2o_dma struct of the DMA buffer to free on failure
+ *
+ * This API allows an OSM to post a message and then be told whether or
+ * not the system received a successful reply. If the message times out
+ * then the value '-ETIMEDOUT' is returned. This is a special case. In
+ * this situation the message may (should) complete at an indefinite time
+ * in the future. When it completes it will use the memory buffer
+ * attached to the request. If -ETIMEDOUT is returned then the memory
+ * buffer must not be freed. Instead the event completion will free them
+ * for you. In all other cases the buffer are your problem.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_msg_post_wait_mem(struct i2o_controller *c, u32 m, unsigned long
+ timeout, struct i2o_dma *dma)
+{
+ DECLARE_WAIT_QUEUE_HEAD(wq);
+ DEFINE_WAIT(wait);
+ struct i2o_exec_wait *iwait;
+ static u32 tcntxt = 0x80000000;
+ struct i2o_message *msg = c->in_queue.virt + m;
+ int rc = 0;
+
+ iwait = i2o_exec_wait_alloc();
+ if (!iwait)
+ return -ENOMEM;
+
+ if (tcntxt == 0xffffffff)
+ tcntxt = 0x80000000;
+
+ if (dma)
+ iwait->dma = *dma;
+
+ /*
+ * Fill in the message initiator context and transaction context.
+ * We will only use transaction contexts >= 0x80000000 for POST WAIT,
+ * so we could find a POST WAIT reply easier in the reply handler.
+ */
+ writel(i2o_exec_driver.context, &msg->u.s.icntxt);
+ iwait->tcntxt = tcntxt++;
+ writel(iwait->tcntxt, &msg->u.s.tcntxt);
+
+ /*
+ * Post the message to the controller. At some point later it will
+ * return. If we time out before it returns then complete will be zero.
+ */
+ i2o_msg_post(c, m);
+
+ if (!iwait->complete) {
+ iwait->wq = &wq;
+ /*
+ * we add elements add the head, because if a entry in the list
+ * will never be removed, we have to iterate over it every time
+ */
+ list_add(&iwait->list, &i2o_exec_wait_list);
+
+ prepare_to_wait(&wq, &wait, TASK_INTERRUPTIBLE);
+
+ if (!iwait->complete)
+ schedule_timeout(timeout * HZ);
+
+ finish_wait(&wq, &wait);
+
+ iwait->wq = NULL;
+ }
+
+ barrier();
+
+ if (iwait->complete) {
+ if (readl(&iwait->msg->body[0]) >> 24)
+ rc = readl(&iwait->msg->body[0]) & 0xff;
+ i2o_flush_reply(c, iwait->m);
+ i2o_exec_wait_free(iwait);
+ } else {
+ /*
+ * We cannot remove it now. This is important. When it does
+ * terminate (which it must do if the controller has not
+ * died...) then it will otherwise scribble on stuff.
+ *
+ * FIXME: try abort message
+ */
+ if (dma)
+ dma->virt = NULL;
+
+ rc = -ETIMEDOUT;
+ }
+
+ return rc;
+};
+
+/**
+ * i2o_msg_post_wait_complete - Reply to a i2o_msg_post request from IOP
+ * @c: I2O controller which answers
+ * @m: message id
+ * @msg: pointer to the I2O reply message
+ *
+ * This function is called in interrupt context only. If the reply reached
+ * before the timeout, the i2o_exec_wait struct is filled with the message
+ * and the task will be waked up. The task is now responsible for returning
+ * the message m back to the controller! If the message reaches us after
+ * the timeout clean up the i2o_exec_wait struct (including allocated
+ * DMA buffer).
+ *
+ * Return 0 on success and if the message m should not be given back to the
+ * I2O controller, or >0 on success and if the message should be given back
+ * afterwords. Returns negative error code on failure. In this case the
+ * message must also be given back to the controller.
+ */
+static int i2o_msg_post_wait_complete(struct i2o_controller *c, u32 m,
+ struct i2o_message *msg)
+{
+ struct i2o_exec_wait *wait, *tmp;
+ static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+ int rc = 1;
+ u32 context;
+
+ context = readl(&msg->u.s.tcntxt);
+
+ /*
+ * We need to search through the i2o_exec_wait_list to see if the given
+ * message is still outstanding. If not, it means that the IOP took
+ * longer to respond to the message than we had allowed and timer has
+ * already expired. Not much we can do about that except log it for
+ * debug purposes, increase timeout, and recompile.
+ */
+ spin_lock(&lock);
+ list_for_each_entry_safe(wait, tmp, &i2o_exec_wait_list, list) {
+ if (wait->tcntxt == context) {
+ list_del(&wait->list);
+
+ wait->m = m;
+ wait->msg = msg;
+ wait->complete = 1;
+
+ barrier();
+
+ if (wait->wq) {
+ wake_up_interruptible(wait->wq);
+ rc = 0;
+ } else {
+ struct device *dev;
+
+ dev = &c->pdev->dev;
+
+ pr_debug("timedout reply received!\n");
+ i2o_dma_free(dev, &wait->dma);
+ i2o_exec_wait_free(wait);
+ rc = -1;
+ }
+
+ spin_unlock(&lock);
+
+ return rc;
+ }
+ }
+
+ spin_unlock(&lock);
+
+ pr_debug("i2o: Bogus reply in POST WAIT (tr-context: %08x)!\n",
+ context);
+
+ return -1;
+};
+
+/**
+ * i2o_exec_probe - Called if a new I2O device (executive class) appears
+ * @dev: I2O device which should be probed
+ *
+ * Registers event notification for every event from Executive device. The
+ * return is always 0, because we want all devices of class Executive.
+ *
+ * Returns 0 on success.
+ */
+static int i2o_exec_probe(struct device *dev)
+{
+ struct i2o_device *i2o_dev = to_i2o_device(dev);
+
+ i2o_event_register(i2o_dev, &i2o_exec_driver, 0, 0xffffffff);
+
+ i2o_dev->iop->exec = i2o_dev;
+
+ return 0;
+};
+
+/**
+ * i2o_exec_remove - Called on I2O device removal
+ * @dev: I2O device which was removed
+ *
+ * Unregisters event notification from Executive I2O device.
+ *
+ * Returns 0 on success.
+ */
+static int i2o_exec_remove(struct device *dev)
+{
+ i2o_event_register(to_i2o_device(dev), &i2o_exec_driver, 0, 0);
+
+ return 0;
+};
+
+/**
+ * i2o_exec_lct_modified - Called on LCT NOTIFY reply
+ * @c: I2O controller on which the LCT has modified
+ *
+ * This function handles asynchronus LCT NOTIFY replies. It parses the
+ * new LCT and if the buffer for the LCT was to small sends a LCT NOTIFY
+ * again.
+ */
+static void i2o_exec_lct_modified(struct i2o_controller *c)
+{
+ if (i2o_device_parse_lct(c) == -EAGAIN)
+ i2o_exec_lct_notify(c, 0);
+};
+
+/**
+ * i2o_exec_reply - I2O Executive reply handler
+ * @c: I2O controller from which the reply comes
+ * @m: message id
+ * @msg: pointer to the I2O reply message
+ *
+ * This function is always called from interrupt context. If a POST WAIT
+ * reply was received, pass it to the complete function. If a LCT NOTIFY
+ * reply was received, a new event is created to handle the update.
+ *
+ * Returns 0 on success and if the reply should not be flushed or > 0
+ * on success and if the reply should be flushed. Returns negative error
+ * code on failure and if the reply should be flushed.
+ */
+static int i2o_exec_reply(struct i2o_controller *c, u32 m,
+ struct i2o_message *msg)
+{
+ if (readl(&msg->u.head[0]) & MSG_FAIL) { // Fail bit is set
+ struct i2o_message *pmsg; /* preserved message */
+ u32 pm;
+
+ pm = readl(&msg->body[3]);
+
+ pmsg = c->in_queue.virt + pm;
+
+ i2o_report_status(KERN_INFO, "i2o_core", msg);
+
+ /* Release the preserved msg by resubmitting it as a NOP */
+ i2o_msg_nop(c, pm);
+
+ /* If reply to i2o_post_wait failed, return causes a timeout */
+ return -1;
+ }
+
+ if (readl(&msg->u.s.tcntxt) & 0x80000000)
+ return i2o_msg_post_wait_complete(c, m, msg);
+
+ if ((readl(&msg->u.head[1]) >> 24) == I2O_CMD_LCT_NOTIFY) {
+ struct work_struct *work;
+
+ pr_debug("%s: LCT notify received\n", c->name);
+
+ work = kmalloc(sizeof(*work), GFP_ATOMIC);
+ if (!work)
+ return -ENOMEM;
+
+ INIT_WORK(work, (void (*)(void *))i2o_exec_lct_modified, c);
+ queue_work(i2o_exec_driver.event_queue, work);
+ return 1;
+ }
+
+ /*
+ * If this happens, we want to dump the message to the syslog so
+ * it can be sent back to the card manufacturer by the end user
+ * to aid in debugging.
+ *
+ */
+ printk(KERN_WARNING "%s: Unsolicited message reply sent to core!"
+ "Message dumped to syslog\n", c->name);
+ i2o_dump_message(msg);
+
+ return -EFAULT;
+}
+
+/**
+ * i2o_exec_event - Event handling function
+ * @evt: Event which occurs
+ *
+ * Handles events send by the Executive device. At the moment does not do
+ * anything useful.
+ */
+static void i2o_exec_event(struct i2o_event *evt)
+{
+ printk(KERN_INFO "Event received from device: %d\n",
+ evt->i2o_dev->lct_data.tid);
+ kfree(evt);
+};
+
+/**
+ * i2o_exec_lct_get - Get the IOP's Logical Configuration Table
+ * @c: I2O controller from which the LCT should be fetched
+ *
+ * Send a LCT NOTIFY request to the controller, and wait
+ * I2O_TIMEOUT_LCT_GET seconds until arrival of response. If the LCT is
+ * to large, retry it.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_exec_lct_get(struct i2o_controller *c)
+{
+ struct i2o_message *msg;
+ u32 m;
+ int i = 0;
+ int rc = -EAGAIN;
+
+ for (i = 1; i <= I2O_LCT_GET_TRIES; i++) {
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(EIGHT_WORD_MSG_SIZE | SGL_OFFSET_6, &msg->u.head[0]);
+ writel(I2O_CMD_LCT_NOTIFY << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(0xffffffff, &msg->body[0]);
+ writel(0x00000000, &msg->body[1]);
+ writel(0xd0000000 | c->dlct.len, &msg->body[2]);
+ writel(c->dlct.phys, &msg->body[3]);
+
+ rc = i2o_msg_post_wait(c, m, I2O_TIMEOUT_LCT_GET);
+ if (rc < 0)
+ break;
+
+ rc = i2o_device_parse_lct(c);
+ if (rc != -EAGAIN)
+ break;
+ }
+
+ return rc;
+}
+
+/**
+ * i2o_exec_lct_notify - Send a asynchronus LCT NOTIFY request
+ * @c: I2O controller to which the request should be send
+ * @change_ind: change indicator
+ *
+ * This function sends a LCT NOTIFY request to the I2O controller with
+ * the change indicator change_ind. If the change_ind == 0 the controller
+ * replies immediately after the request. If change_ind > 0 the reply is
+ * send after change indicator of the LCT is > change_ind.
+ */
+int i2o_exec_lct_notify(struct i2o_controller *c, u32 change_ind)
+{
+ i2o_status_block *sb = c->status_block.virt;
+ struct device *dev;
+ struct i2o_message *msg;
+ u32 m;
+
+ dev = &c->pdev->dev;
+
+ if (i2o_dma_realloc(dev, &c->dlct, sb->expected_lct_size, GFP_KERNEL))
+ return -ENOMEM;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(EIGHT_WORD_MSG_SIZE | SGL_OFFSET_6, &msg->u.head[0]);
+ writel(I2O_CMD_LCT_NOTIFY << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(i2o_exec_driver.context, &msg->u.s.icntxt);
+ writel(0, &msg->u.s.tcntxt); /* FIXME */
+ writel(0xffffffff, &msg->body[0]);
+ writel(change_ind, &msg->body[1]);
+ writel(0xd0000000 | c->dlct.len, &msg->body[2]);
+ writel(c->dlct.phys, &msg->body[3]);
+
+ i2o_msg_post(c, m);
+
+ return 0;
+};
+
+/* Exec OSM driver struct */
+struct i2o_driver i2o_exec_driver = {
+ .name = "exec-osm",
+ .reply = i2o_exec_reply,
+ .event = i2o_exec_event,
+ .classes = i2o_exec_class_id,
+ .driver = {
+ .probe = i2o_exec_probe,
+ .remove = i2o_exec_remove,
+ },
+};
+
+/**
+ * i2o_exec_init - Registers the Exec OSM
+ *
+ * Registers the Exec OSM in the I2O core.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int __init i2o_exec_init(void)
+{
+ return i2o_driver_register(&i2o_exec_driver);
+};
+
+/**
+ * i2o_exec_exit - Removes the Exec OSM
+ *
+ * Unregisters the Exec OSM from the I2O core.
+ */
+void __exit i2o_exec_exit(void)
+{
+ i2o_driver_unregister(&i2o_exec_driver);
+};
+
+EXPORT_SYMBOL(i2o_msg_post_wait_mem);
+EXPORT_SYMBOL(i2o_exec_lct_get);
+EXPORT_SYMBOL(i2o_exec_lct_notify);
--- /dev/null
+/*
+ * Block OSM structures/API
+ *
+ * Copyright (C) 1999-2002 Red Hat Software
+ *
+ * Written by Alan Cox, Building Number Three Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * For the purpose of avoiding doubt the preferred form of the work
+ * for making modifications shall be a standards compliant form such
+ * gzipped tar and not one requiring a proprietary or patent encumbered
+ * tool to unpack.
+ *
+ * Fixes/additions:
+ * Steve Ralston:
+ * Multiple device handling error fixes,
+ * Added a queue depth.
+ * Alan Cox:
+ * FC920 has an rmw bug. Dont or in the end marker.
+ * Removed queue walk, fixed for 64bitness.
+ * Rewrote much of the code over time
+ * Added indirect block lists
+ * Handle 64K limits on many controllers
+ * Don't use indirects on the Promise (breaks)
+ * Heavily chop down the queue depths
+ * Deepak Saxena:
+ * Independent queues per IOP
+ * Support for dynamic device creation/deletion
+ * Code cleanup
+ * Support for larger I/Os through merge* functions
+ * (taken from DAC960 driver)
+ * Boji T Kannanthanam:
+ * Set the I2O Block devices to be detected in increasing
+ * order of TIDs during boot.
+ * Search and set the I2O block device that we boot off
+ * from as the first device to be claimed (as /dev/i2o/hda)
+ * Properly attach/detach I2O gendisk structure from the
+ * system gendisk list. The I2O block devices now appear in
+ * /proc/partitions.
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>:
+ * Minor bugfixes for 2.6.
+ */
+
+#ifndef I2O_BLOCK_OSM_H
+#define I2O_BLOCK_OSM_H
+
+#define I2O_BLOCK_RETRY_TIME HZ/4
+#define I2O_BLOCK_MAX_OPEN_REQUESTS 50
+
+/* I2O Block OSM mempool struct */
+struct i2o_block_mempool {
+ kmem_cache_t *slab;
+ mempool_t *pool;
+};
+
+/* I2O Block device descriptor */
+struct i2o_block_device {
+ struct i2o_device *i2o_dev; /* pointer to I2O device */
+ struct gendisk *gd;
+ spinlock_t lock; /* queue lock */
+ struct list_head open_queue; /* list of transfered, but unfinished
+ requests */
+ unsigned int open_queue_depth; /* number of requests in the queue */
+
+ int rcache; /* read cache flags */
+ int wcache; /* write cache flags */
+ int flags;
+ int power; /* power state */
+ int media_change_flag; /* media changed flag */
+};
+
+/* I2O Block device request */
+struct i2o_block_request
+{
+ struct list_head queue;
+ struct request *req; /* corresponding request */
+ struct i2o_block_device *i2o_blk_dev; /* I2O block device */
+ int sg_dma_direction; /* direction of DMA buffer read/write */
+ int sg_nents; /* number of SG elements */
+ struct scatterlist sg_table[I2O_MAX_SEGMENTS]; /* SG table */
+};
+
+/* I2O Block device delayed request */
+struct i2o_block_delayed_request
+{
+ struct work_struct work;
+ struct request_queue *queue;
+};
+
+#endif
--- /dev/null
+/*
+ * Functions to handle I2O controllers and I2O message handling
+ *
+ * Copyright (C) 1999-2002 Red Hat Software
+ *
+ * Written by Alan Cox, Building Number Three Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * A lot of the I2O message side code from this is taken from the
+ * Red Creek RCPCI45 adapter driver by Red Creek Communications
+ *
+ * Fixes/additions:
+ * Philipp Rumpf
+ * Juha Sievänen <Juha.Sievanen@cs.Helsinki.FI>
+ * Auvo Häkkinen <Auvo.Hakkinen@cs.Helsinki.FI>
+ * Deepak Saxena <deepak@plexity.net>
+ * Boji T Kannanthanam <boji.t.kannanthanam@intel.com>
+ * Alan Cox <alan@redhat.com>:
+ * Ported to Linux 2.5.
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>:
+ * Minor fixes for 2.6.
+ */
+
+#include <linux/module.h>
+#include <linux/i2o.h>
+
+/* global I2O controller list */
+LIST_HEAD(i2o_controllers);
+
+/*
+ * global I2O System Table. Contains information about all the IOPs in the
+ * system. Used to inform IOPs about each others existence.
+ */
+static struct i2o_dma i2o_systab;
+
+/* Module internal functions from other sources */
+extern struct i2o_driver i2o_exec_driver;
+extern int i2o_exec_lct_get(struct i2o_controller *);
+extern void i2o_device_remove(struct i2o_device *);
+
+extern int __init i2o_driver_init(void);
+extern void __exit i2o_driver_exit(void);
+extern int __init i2o_exec_init(void);
+extern void __exit i2o_exec_exit(void);
+extern int __init i2o_pci_init(void);
+extern void __exit i2o_pci_exit(void);
+extern int i2o_device_init(void);
+extern void i2o_device_exit(void);
+
+/**
+ * i2o_msg_nop - Returns a message which is not used
+ * @c: I2O controller from which the message was created
+ * @m: message which should be returned
+ *
+ * If you fetch a message via i2o_msg_get, and can't use it, you must
+ * return the message with this function. Otherwise the message frame
+ * is lost.
+ */
+void i2o_msg_nop(struct i2o_controller *c, u32 m)
+{
+ struct i2o_message *msg = c->in_queue.virt + m;
+
+ writel(THREE_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_UTIL_NOP << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(0, &msg->u.head[2]);
+ writel(0, &msg->u.head[3]);
+ i2o_msg_post(c, m);
+};
+
+/**
+ * i2o_msg_get_wait - obtain an I2O message from the IOP
+ * @c: I2O controller
+ * @msg: pointer to a I2O message pointer
+ * @wait: how long to wait until timeout
+ *
+ * This function waits up to wait seconds for a message slot to be
+ * available.
+ *
+ * On a success the message is returned and the pointer to the message is
+ * set in msg. The returned message is the physical page frame offset
+ * address from the read port (see the i2o spec). If no message is
+ * available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
+ */
+u32 i2o_msg_get_wait(struct i2o_controller *c, struct i2o_message **msg,
+ int wait)
+{
+ unsigned long timeout = jiffies + wait * HZ;
+ u32 m;
+
+ while ((m = i2o_msg_get(c, msg)) == I2O_QUEUE_EMPTY) {
+ if (time_after(jiffies, timeout)) {
+ pr_debug("%s: Timeout waiting for message frame.\n",
+ c->name);
+ return I2O_QUEUE_EMPTY;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+ }
+
+ return m;
+};
+
+#if BITS_PER_LONG == 64
+/**
+ * i2o_cntxt_list_add - Append a pointer to context list and return a id
+ * @c: controller to which the context list belong
+ * @ptr: pointer to add to the context list
+ *
+ * Because the context field in I2O is only 32-bit large, on 64-bit the
+ * pointer is to large to fit in the context field. The i2o_cntxt_list
+ * functions therefore map pointers to context fields.
+ *
+ * Returns context id > 0 on success or 0 on failure.
+ */
+u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
+{
+ struct i2o_context_list_element *entry;
+ unsigned long flags;
+
+ if (!ptr)
+ printk(KERN_ERR "NULL pointer found!\n");
+
+ entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
+ if (!entry) {
+ printk(KERN_ERR "i2o: Could not allocate memory for context "
+ "list element\n");
+ return 0;
+ }
+
+ entry->ptr = ptr;
+ entry->timestamp = jiffies;
+ INIT_LIST_HEAD(&entry->list);
+
+ spin_lock_irqsave(&c->context_list_lock, flags);
+
+ if (unlikely(atomic_inc_and_test(&c->context_list_counter)))
+ atomic_inc(&c->context_list_counter);
+
+ entry->context = atomic_read(&c->context_list_counter);
+
+ list_add(&entry->list, &c->context_list);
+
+ spin_unlock_irqrestore(&c->context_list_lock, flags);
+
+ pr_debug("Add context to list %p -> %d\n", ptr, context);
+
+ return entry->context;
+};
+
+/**
+ * i2o_cntxt_list_remove - Remove a pointer from the context list
+ * @c: controller to which the context list belong
+ * @ptr: pointer which should be removed from the context list
+ *
+ * Removes a previously added pointer from the context list and returns
+ * the matching context id.
+ *
+ * Returns context id on succes or 0 on failure.
+ */
+u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
+{
+ struct i2o_context_list_element *entry;
+ u32 context = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->context_list_lock, flags);
+ list_for_each_entry(entry, &c->context_list, list)
+ if (entry->ptr == ptr) {
+ list_del(&entry->list);
+ context = entry->context;
+ kfree(entry);
+ break;
+ }
+ spin_unlock_irqrestore(&c->context_list_lock, flags);
+
+ if (!context)
+ printk(KERN_WARNING "i2o: Could not remove nonexistent ptr "
+ "%p\n", ptr);
+
+ pr_debug("remove ptr from context list %d -> %p\n", context, ptr);
+
+ return context;
+};
+
+/**
+ * i2o_cntxt_list_get - Get a pointer from the context list and remove it
+ * @c: controller to which the context list belong
+ * @context: context id to which the pointer belong
+ *
+ * Returns pointer to the matching context id on success or NULL on
+ * failure.
+ */
+void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
+{
+ struct i2o_context_list_element *entry;
+ unsigned long flags;
+ void *ptr = NULL;
+
+ spin_lock_irqsave(&c->context_list_lock, flags);
+ list_for_each_entry(entry, &c->context_list, list)
+ if (entry->context == context) {
+ list_del(&entry->list);
+ ptr = entry->ptr;
+ kfree(entry);
+ break;
+ }
+ spin_unlock_irqrestore(&c->context_list_lock, flags);
+
+ if (!ptr)
+ printk(KERN_WARNING "i2o: context id %d not found\n", context);
+
+ pr_debug("get ptr from context list %d -> %p\n", context, ptr);
+
+ return ptr;
+};
+
+/**
+ * i2o_cntxt_list_get_ptr - Get a context id from the context list
+ * @c: controller to which the context list belong
+ * @ptr: pointer to which the context id should be fetched
+ *
+ * Returns context id which matches to the pointer on succes or 0 on
+ * failure.
+ */
+u32 i2o_cntxt_list_get_ptr(struct i2o_controller * c, void *ptr)
+{
+ struct i2o_context_list_element *entry;
+ u32 context = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->context_list_lock, flags);
+ list_for_each_entry(entry, &c->context_list, list)
+ if (entry->ptr == ptr) {
+ context = entry->context;
+ break;
+ }
+ spin_unlock_irqrestore(&c->context_list_lock, flags);
+
+ if (!context)
+ printk(KERN_WARNING "i2o: Could not find nonexistent ptr "
+ "%p\n", ptr);
+
+ pr_debug("get context id from context list %p -> %d\n", ptr, context);
+
+ return context;
+};
+#endif
+
+/**
+ * i2o_iop_find - Find an I2O controller by id
+ * @unit: unit number of the I2O controller to search for
+ *
+ * Lookup the I2O controller on the controller list.
+ *
+ * Returns pointer to the I2O controller on success or NULL if not found.
+ */
+struct i2o_controller *i2o_find_iop(int unit)
+{
+ struct i2o_controller *c;
+
+ list_for_each_entry(c, &i2o_controllers, list) {
+ if (c->unit == unit)
+ return c;
+ }
+
+ return NULL;
+};
+
+/**
+ * i2o_iop_find_device - Find a I2O device on an I2O controller
+ * @c: I2O controller where the I2O device hangs on
+ * @tid: TID of the I2O device to search for
+ *
+ * Searches the devices of the I2O controller for a device with TID tid and
+ * returns it.
+ *
+ * Returns a pointer to the I2O device if found, otherwise NULL.
+ */
+struct i2o_device *i2o_iop_find_device(struct i2o_controller *c, u16 tid)
+{
+ struct i2o_device *dev;
+
+ list_for_each_entry(dev, &c->devices, list)
+ if (dev->lct_data.tid == tid)
+ return dev;
+
+ return NULL;
+};
+
+/**
+ * i2o_quiesce_controller - quiesce controller
+ * @c: controller
+ *
+ * Quiesce an IOP. Causes IOP to make external operation quiescent
+ * (i2o 'READY' state). Internal operation of the IOP continues normally.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_iop_quiesce(struct i2o_controller *c)
+{
+ struct i2o_message *msg;
+ u32 m;
+ i2o_status_block *sb = c->status_block.virt;
+ int rc;
+
+ i2o_status_get(c);
+
+ /* SysQuiesce discarded if IOP not in READY or OPERATIONAL state */
+ if ((sb->iop_state != ADAPTER_STATE_READY) &&
+ (sb->iop_state != ADAPTER_STATE_OPERATIONAL))
+ return 0;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(FOUR_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_SYS_QUIESCE << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+
+ /* Long timeout needed for quiesce if lots of devices */
+ if ((rc = i2o_msg_post_wait(c, m, 240)))
+ printk(KERN_INFO "%s: Unable to quiesce (status=%#x).\n",
+ c->name, -rc);
+ else
+ pr_debug("%s: Quiesced.\n", c->name);
+
+ i2o_status_get(c); // Entered READY state
+
+ return rc;
+};
+
+/**
+ * i2o_iop_enable - move controller from ready to OPERATIONAL
+ * @c: I2O controller
+ *
+ * Enable IOP. This allows the IOP to resume external operations and
+ * reverses the effect of a quiesce. Returns zero or an error code if
+ * an error occurs.
+ */
+static int i2o_iop_enable(struct i2o_controller *c)
+{
+ struct i2o_message *msg;
+ u32 m;
+ i2o_status_block *sb = c->status_block.virt;
+ int rc;
+
+ i2o_status_get(c);
+
+ /* Enable only allowed on READY state */
+ if (sb->iop_state != ADAPTER_STATE_READY)
+ return -EINVAL;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(FOUR_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_SYS_ENABLE << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+
+ /* How long of a timeout do we need? */
+ if ((rc = i2o_msg_post_wait(c, m, 240)))
+ printk(KERN_ERR "%s: Could not enable (status=%#x).\n",
+ c->name, -rc);
+ else
+ pr_debug("%s: Enabled.\n", c->name);
+
+ i2o_status_get(c); // entered OPERATIONAL state
+
+ return rc;
+};
+
+/**
+ * i2o_iop_quiesce_all - Quiesce all I2O controllers on the system
+ *
+ * Quiesce all I2O controllers which are connected to the system.
+ */
+static inline void i2o_iop_quiesce_all(void)
+{
+ struct i2o_controller *c, *tmp;
+
+ list_for_each_entry_safe(c, tmp, &i2o_controllers, list) {
+ if (!c->no_quiesce)
+ i2o_iop_quiesce(c);
+ }
+};
+
+/**
+ * i2o_iop_enable_all - Enables all controllers on the system
+ *
+ * Enables all I2O controllers which are connected to the system.
+ */
+static inline void i2o_iop_enable_all(void)
+{
+ struct i2o_controller *c, *tmp;
+
+ list_for_each_entry_safe(c, tmp, &i2o_controllers, list)
+ i2o_iop_enable(c);
+};
+
+/**
+ * i2o_clear_controller - Bring I2O controller into HOLD state
+ * @c: controller
+ *
+ * Clear an IOP to HOLD state, ie. terminate external operations, clear all
+ * input queues and prepare for a system restart. IOP's internal operation
+ * continues normally and the outbound queue is alive. The IOP is not
+ * expected to rebuild its LCT.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_iop_clear(struct i2o_controller *c)
+{
+ struct i2o_message *msg;
+ u32 m;
+ int rc;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ /* Quiesce all IOPs first */
+ i2o_iop_quiesce_all();
+
+ writel(FOUR_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_ADAPTER_CLEAR << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+
+ if ((rc = i2o_msg_post_wait(c, m, 30)))
+ printk(KERN_INFO "%s: Unable to clear (status=%#x).\n",
+ c->name, -rc);
+ else
+ pr_debug("%s: Cleared.\n", c->name);
+
+ /* Enable all IOPs */
+ i2o_iop_enable_all();
+
+ i2o_status_get(c);
+
+ return rc;
+}
+
+/**
+ * i2o_iop_reset - reset an I2O controller
+ * @c: controller to reset
+ *
+ * Reset the IOP into INIT state and wait until IOP gets into RESET state.
+ * Terminate all external operations, clear IOP's inbound and outbound
+ * queues, terminate all DDMs, and reload the IOP's operating environment
+ * and all local DDMs. The IOP rebuilds its LCT.
+ */
+static int i2o_iop_reset(struct i2o_controller *c)
+{
+ u8 *status = c->status.virt;
+ struct i2o_message *msg;
+ u32 m;
+ unsigned long timeout;
+ i2o_status_block *sb = c->status_block.virt;
+ int rc = 0;
+
+ pr_debug("Resetting controller\n");
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ memset(status, 0, 4);
+
+ /* Quiesce all IOPs first */
+ i2o_iop_quiesce_all();
+
+ writel(EIGHT_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_ADAPTER_RESET << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(i2o_exec_driver.context, &msg->u.s.icntxt);
+ writel(0, &msg->u.s.tcntxt); //FIXME: use reasonable transaction context
+ writel(0, &msg->body[0]);
+ writel(0, &msg->body[1]);
+ writel(i2o_ptr_low((void *)c->status.phys), &msg->body[2]);
+ writel(i2o_ptr_high((void *)c->status.phys), &msg->body[3]);
+
+ i2o_msg_post(c, m);
+
+ /* Wait for a reply */
+ timeout = jiffies + I2O_TIMEOUT_RESET * HZ;
+ while (!*status) {
+ if (time_after(jiffies, timeout)) {
+ printk(KERN_ERR "IOP reset timeout.\n");
+ rc = -ETIMEDOUT;
+ goto exit;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+
+ rmb();
+ }
+
+ if (*status == I2O_CMD_IN_PROGRESS) {
+ /*
+ * Once the reset is sent, the IOP goes into the INIT state
+ * which is indeterminate. We need to wait until the IOP
+ * has rebooted before we can let the system talk to
+ * it. We read the inbound Free_List until a message is
+ * available. If we can't read one in the given ammount of
+ * time, we assume the IOP could not reboot properly.
+ */
+ pr_debug("%s: Reset in progress, waiting for reboot...\n",
+ c->name);
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_RESET);
+ while (m == I2O_QUEUE_EMPTY) {
+ if (time_after(jiffies, timeout)) {
+ printk(KERN_ERR "IOP reset timeout.\n");
+ rc = -ETIMEDOUT;
+ goto exit;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_RESET);
+ }
+ i2o_msg_nop(c, m);
+ }
+
+ /* from here all quiesce commands are safe */
+ c->no_quiesce = 0;
+
+ /* If IopReset was rejected or didn't perform reset, try IopClear */
+ i2o_status_get(c);
+ if (*status == I2O_CMD_REJECTED || sb->iop_state != ADAPTER_STATE_RESET) {
+ printk(KERN_WARNING "%s: Reset rejected, trying to clear\n",
+ c->name);
+ i2o_iop_clear(c);
+ } else
+ pr_debug("%s: Reset completed.\n", c->name);
+
+ exit:
+ /* Enable all IOPs */
+ i2o_iop_enable_all();
+
+ return rc;
+};
+
+/**
+ * i2o_iop_init_outbound_queue - setup the outbound message queue
+ * @c: I2O controller
+ *
+ * Clear and (re)initialize IOP's outbound queue and post the message
+ * frames to the IOP.
+ *
+ * Returns 0 on success or a negative errno code on failure.
+ */
+int i2o_iop_init_outbound_queue(struct i2o_controller *c)
+{
+ u8 *status = c->status.virt;
+ u32 m;
+ struct i2o_message *msg;
+ ulong timeout;
+ int i;
+
+ pr_debug("%s: Initializing Outbound Queue...\n", c->name);
+
+ memset(status, 0, 4);
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(EIGHT_WORD_MSG_SIZE | TRL_OFFSET_6, &msg->u.head[0]);
+ writel(I2O_CMD_OUTBOUND_INIT << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(i2o_exec_driver.context, &msg->u.s.icntxt);
+ writel(0x0106, &msg->u.s.tcntxt); /* FIXME: why 0x0106, maybe in
+ Spec? */
+ writel(PAGE_SIZE, &msg->body[0]);
+ writel(MSG_FRAME_SIZE << 16 | 0x80, &msg->body[1]); /* Outbound msg frame
+ size in words and Initcode */
+ writel(0xd0000004, &msg->body[2]);
+ writel(i2o_ptr_low((void *)c->status.phys), &msg->body[3]);
+ writel(i2o_ptr_high((void *)c->status.phys), &msg->body[4]);
+
+ i2o_msg_post(c, m);
+
+ timeout = jiffies + I2O_TIMEOUT_INIT_OUTBOUND_QUEUE * HZ;
+ while (*status <= I2O_CMD_IN_PROGRESS) {
+ if (time_after(jiffies, timeout)) {
+ printk(KERN_WARNING "%s: Timeout Initializing\n",
+ c->name);
+ return -ETIMEDOUT;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+
+ rmb();
+ }
+
+ m = c->out_queue.phys;
+
+ /* Post frames */
+ for (i = 0; i < NMBR_MSG_FRAMES; i++) {
+ i2o_flush_reply(c, m);
+ m += MSG_FRAME_SIZE * 4;
+ }
+
+ return 0;
+}
+
+/**
+ * i2o_iop_activate - Bring controller up to HOLD
+ * @c: controller
+ *
+ * This function brings an I2O controller into HOLD state. The adapter
+ * is reset if necessary and then the queues and resource table are read.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_iop_activate(struct i2o_controller *c)
+{
+ i2o_status_block *sb = c->status_block.virt;
+ int rc;
+ /* In INIT state, Wait Inbound Q to initialize (in i2o_status_get) */
+ /* In READY state, Get status */
+
+ rc = i2o_status_get(c);
+ if (rc) {
+ printk(KERN_INFO "Unable to obtain status of %s, "
+ "attempting a reset.\n", c->name);
+ if (i2o_iop_reset(c))
+ return rc;
+ }
+
+ if (sb->i2o_version > I2OVER15) {
+ printk(KERN_ERR "%s: Not running vrs. 1.5. of the I2O "
+ "Specification.\n", c->name);
+ return -ENODEV;
+ }
+
+ switch (sb->iop_state) {
+ case ADAPTER_STATE_FAULTED:
+ printk(KERN_CRIT "%s: hardware fault\n", c->name);
+ return -ENODEV;
+
+ case ADAPTER_STATE_READY:
+ case ADAPTER_STATE_OPERATIONAL:
+ case ADAPTER_STATE_HOLD:
+ case ADAPTER_STATE_FAILED:
+ pr_debug("already running, trying to reset...\n");
+ if (i2o_iop_reset(c))
+ return -ENODEV;
+ }
+
+ rc = i2o_iop_init_outbound_queue(c);
+ if (rc)
+ return rc;
+
+ /* In HOLD state */
+
+ rc = i2o_hrt_get(c);
+ if (rc)
+ return rc;
+
+ return 0;
+};
+
+/**
+ * i2o_iop_systab_set - Set the I2O System Table of the specified IOP
+ * @c: I2O controller to which the system table should be send
+ *
+ * Before the systab could be set i2o_systab_build() must be called.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_iop_systab_set(struct i2o_controller *c)
+{
+ struct i2o_message *msg;
+ u32 m;
+ i2o_status_block *sb = c->status_block.virt;
+ struct device *dev = &c->pdev->dev;
+ struct resource *root;
+ int rc;
+
+ if (sb->current_mem_size < sb->desired_mem_size) {
+ struct resource *res = &c->mem_resource;
+ res->name = c->pdev->bus->name;
+ res->flags = IORESOURCE_MEM;
+ res->start = 0;
+ res->end = 0;
+ printk("%s: requires private memory resources.\n", c->name);
+ root = pci_find_parent_resource(c->pdev, res);
+ if (root == NULL)
+ printk("Can't find parent resource!\n");
+ if (root && allocate_resource(root, res, sb->desired_mem_size, sb->desired_mem_size, sb->desired_mem_size, 1 << 20, /* Unspecified, so use 1Mb and play safe */
+ NULL, NULL) >= 0) {
+ c->mem_alloc = 1;
+ sb->current_mem_size = 1 + res->end - res->start;
+ sb->current_mem_base = res->start;
+ printk(KERN_INFO
+ "%s: allocated %ld bytes of PCI memory at 0x%08lX.\n",
+ c->name, 1 + res->end - res->start, res->start);
+ }
+ }
+
+ if (sb->current_io_size < sb->desired_io_size) {
+ struct resource *res = &c->io_resource;
+ res->name = c->pdev->bus->name;
+ res->flags = IORESOURCE_IO;
+ res->start = 0;
+ res->end = 0;
+ printk("%s: requires private memory resources.\n", c->name);
+ root = pci_find_parent_resource(c->pdev, res);
+ if (root == NULL)
+ printk("Can't find parent resource!\n");
+ if (root && allocate_resource(root, res, sb->desired_io_size, sb->desired_io_size, sb->desired_io_size, 1 << 20, /* Unspecified, so use 1Mb and play safe */
+ NULL, NULL) >= 0) {
+ c->io_alloc = 1;
+ sb->current_io_size = 1 + res->end - res->start;
+ sb->current_mem_base = res->start;
+ printk(KERN_INFO
+ "%s: allocated %ld bytes of PCI I/O at 0x%08lX.\n",
+ c->name, 1 + res->end - res->start, res->start);
+ }
+ }
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ i2o_systab.phys = dma_map_single(dev, i2o_systab.virt, i2o_systab.len,
+ PCI_DMA_TODEVICE);
+ if (!i2o_systab.phys) {
+ i2o_msg_nop(c, m);
+ return -ENOMEM;
+ }
+
+ writel(I2O_MESSAGE_SIZE(12) | SGL_OFFSET_6, &msg->u.head[0]);
+ writel(I2O_CMD_SYS_TAB_SET << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+
+ /*
+ * Provide three SGL-elements:
+ * System table (SysTab), Private memory space declaration and
+ * Private i/o space declaration
+ *
+ * FIXME: is this still true?
+ * Nasty one here. We can't use dma_alloc_coherent to send the
+ * same table to everyone. We have to go remap it for them all
+ */
+
+ writel(c->unit + 2, &msg->body[0]);
+ writel(0, &msg->body[1]);
+ writel(0x54000000 | i2o_systab.phys, &msg->body[2]);
+ writel(i2o_systab.phys, &msg->body[3]);
+ writel(0x54000000 | sb->current_mem_size, &msg->body[4]);
+ writel(sb->current_mem_base, &msg->body[5]);
+ writel(0xd4000000 | sb->current_io_size, &msg->body[6]);
+ writel(sb->current_io_base, &msg->body[6]);
+
+ rc = i2o_msg_post_wait(c, m, 120);
+
+ dma_unmap_single(dev, i2o_systab.phys, i2o_systab.len,
+ PCI_DMA_TODEVICE);
+
+ if (rc < 0)
+ printk(KERN_ERR "%s: Unable to set SysTab (status=%#x).\n",
+ c->name, -rc);
+ else
+ pr_debug("%s: SysTab set.\n", c->name);
+
+ i2o_status_get(c); // Entered READY state
+
+ return rc;
+}
+
+/**
+ * i2o_iop_online - Bring a controller online into OPERATIONAL state.
+ * @c: I2O controller
+ *
+ * Send the system table and enable the I2O controller.
+ *
+ * Returns 0 on success or negativer error code on failure.
+ */
+static int i2o_iop_online(struct i2o_controller *c)
+{
+ int rc;
+
+ rc = i2o_iop_systab_set(c);
+ if (rc)
+ return rc;
+
+ /* In READY state */
+ pr_debug("%s: Attempting to enable...\n", c->name);
+ rc = i2o_iop_enable(c);
+ if (rc)
+ return rc;
+
+ return 0;
+};
+
+/**
+ * i2o_iop_remove - Remove the I2O controller from the I2O core
+ * @c: I2O controller
+ *
+ * Remove the I2O controller from the I2O core. If devices are attached to
+ * the controller remove these also and finally reset the controller.
+ */
+void i2o_iop_remove(struct i2o_controller *c)
+{
+ struct i2o_device *dev, *tmp;
+
+ pr_debug("Deleting controller %s\n", c->name);
+
+ i2o_driver_notify_controller_remove_all(c);
+
+ list_del(&c->list);
+
+ list_for_each_entry_safe(dev, tmp, &c->devices, list)
+ i2o_device_remove(dev);
+
+ /* Ask the IOP to switch to RESET state */
+ i2o_iop_reset(c);
+}
+
+/**
+ * i2o_systab_build - Build system table
+ *
+ * The system table contains information about all the IOPs in the system
+ * (duh) and is used by the Executives on the IOPs to establish peer2peer
+ * connections. We're not supporting peer2peer at the moment, but this
+ * will be needed down the road for things like lan2lan forwarding.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_systab_build(void)
+{
+ struct i2o_controller *c, *tmp;
+ int num_controllers = 0;
+ u32 change_ind = 0;
+ int count = 0;
+ struct i2o_sys_tbl *systab = i2o_systab.virt;
+
+ list_for_each_entry_safe(c, tmp, &i2o_controllers, list)
+ num_controllers++;
+
+ if (systab) {
+ change_ind = systab->change_ind;
+ kfree(i2o_systab.virt);
+ }
+
+ /* Header + IOPs */
+ i2o_systab.len = sizeof(struct i2o_sys_tbl) + num_controllers *
+ sizeof(struct i2o_sys_tbl_entry);
+
+ systab = i2o_systab.virt = kmalloc(i2o_systab.len, GFP_KERNEL);
+ if (!systab) {
+ printk(KERN_ERR "i2o: unable to allocate memory for System "
+ "Table\n");
+ return -ENOMEM;
+ }
+ memset(systab, 0, i2o_systab.len);
+
+ systab->version = I2OVERSION;
+ systab->change_ind = change_ind + 1;
+
+ list_for_each_entry_safe(c, tmp, &i2o_controllers, list) {
+ i2o_status_block *sb;
+
+ if (count >= num_controllers) {
+ printk(KERN_ERR "i2o: controller added while building "
+ "system table\n");
+ break;
+ }
+
+ sb = c->status_block.virt;
+
+ /*
+ * Get updated IOP state so we have the latest information
+ *
+ * We should delete the controller at this point if it
+ * doesn't respond since if it's not on the system table
+ * it is techninically not part of the I2O subsystem...
+ */
+ if (unlikely(i2o_status_get(c))) {
+ printk(KERN_ERR "%s: Deleting b/c could not get status"
+ " while attempting to build system table\n",
+ c->name);
+ i2o_iop_remove(c);
+ continue; // try the next one
+ }
+
+ systab->iops[count].org_id = sb->org_id;
+ systab->iops[count].iop_id = c->unit + 2;
+ systab->iops[count].seg_num = 0;
+ systab->iops[count].i2o_version = sb->i2o_version;
+ systab->iops[count].iop_state = sb->iop_state;
+ systab->iops[count].msg_type = sb->msg_type;
+ systab->iops[count].frame_size = sb->inbound_frame_size;
+ systab->iops[count].last_changed = change_ind;
+ systab->iops[count].iop_capabilities = sb->iop_capabilities;
+ systab->iops[count].inbound_low = i2o_ptr_low(c->post_port);
+ systab->iops[count].inbound_high = i2o_ptr_high(c->post_port);
+
+ count++;
+ }
+
+ systab->num_entries = count;
+
+ return 0;
+};
+
+/**
+ * i2o_parse_hrt - Parse the hardware resource table.
+ * @c: I2O controller
+ *
+ * We don't do anything with it except dumping it (in debug mode).
+ *
+ * Returns 0.
+ */
+static int i2o_parse_hrt(struct i2o_controller *c)
+{
+ i2o_dump_hrt(c);
+ return 0;
+};
+
+/**
+ * i2o_status_get - Get the status block from the I2O controller
+ * @c: I2O controller
+ *
+ * Issue a status query on the controller. This updates the attached
+ * status block. The status block could then be accessed through
+ * c->status_block.
+ *
+ * Returns 0 on sucess or negative error code on failure.
+ */
+int i2o_status_get(struct i2o_controller *c)
+{
+ struct i2o_message *msg;
+ u32 m;
+ u8 *status_block;
+ unsigned long timeout;
+
+ status_block = (u8 *) c->status_block.virt;
+ memset(status_block, 0, sizeof(i2o_status_block));
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(NINE_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_STATUS_GET << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(i2o_exec_driver.context, &msg->u.s.icntxt);
+ writel(0, &msg->u.s.tcntxt); // FIXME: use resonable transaction context
+ writel(0, &msg->body[0]);
+ writel(0, &msg->body[1]);
+ writel(i2o_ptr_low((void *)c->status_block.phys), &msg->body[2]);
+ writel(i2o_ptr_high((void *)c->status_block.phys), &msg->body[3]);
+ writel(sizeof(i2o_status_block), &msg->body[4]); /* always 88 bytes */
+
+ i2o_msg_post(c, m);
+
+ /* Wait for a reply */
+ timeout = jiffies + I2O_TIMEOUT_STATUS_GET * HZ;
+ while (status_block[87] != 0xFF) {
+ if (time_after(jiffies, timeout)) {
+ printk(KERN_ERR "%s: Get status timeout.\n", c->name);
+ return -ETIMEDOUT;
+ }
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+
+ rmb();
+ }
+
+#ifdef DEBUG
+ i2o_debug_state(c);
+#endif
+
+ return 0;
+}
+
+/*
+ * i2o_hrt_get - Get the Hardware Resource Table from the I2O controller
+ * @c: I2O controller from which the HRT should be fetched
+ *
+ * The HRT contains information about possible hidden devices but is
+ * mostly useless to us.
+ *
+ * Returns 0 on success or negativer error code on failure.
+ */
+int i2o_hrt_get(struct i2o_controller *c)
+{
+ int rc;
+ int i;
+ i2o_hrt *hrt = c->hrt.virt;
+ u32 size = sizeof(i2o_hrt);
+ struct device *dev = &c->pdev->dev;
+
+ for (i = 0; i < I2O_HRT_GET_TRIES; i++) {
+ struct i2o_message *msg;
+ u32 m;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(SIX_WORD_MSG_SIZE | SGL_OFFSET_4, &msg->u.head[0]);
+ writel(I2O_CMD_HRT_GET << 24 | HOST_TID << 12 | ADAPTER_TID,
+ &msg->u.head[1]);
+ writel(0xd0000000 | c->hrt.len, &msg->body[0]);
+ writel(c->hrt.phys, &msg->body[1]);
+
+ rc = i2o_msg_post_wait_mem(c, m, 20, &c->hrt);
+
+ if (rc < 0) {
+ printk(KERN_ERR "%s: Unable to get HRT (status=%#x)\n",
+ c->name, -rc);
+ return rc;
+ }
+
+ size = hrt->num_entries * hrt->entry_len << 2;
+ if (size > c->hrt.len) {
+ if (i2o_dma_realloc(dev, &c->hrt, size, GFP_KERNEL))
+ return -ENOMEM;
+ else
+ hrt = c->hrt.virt;
+ } else
+ return i2o_parse_hrt(c);
+ }
+
+ printk(KERN_ERR "%s: Unable to get HRT after %d tries, giving up\n",
+ c->name, I2O_HRT_GET_TRIES);
+
+ return -EBUSY;
+}
+
+/**
+ * i2o_iop_alloc - Allocate and initialize a i2o_controller struct
+ *
+ * Allocate the necessary memory for a i2o_controller struct and
+ * initialize the lists.
+ *
+ * Returns a pointer to the I2O controller or a negative error code on
+ * failure.
+ */
+struct i2o_controller *i2o_iop_alloc(void)
+{
+ static int unit = 0; /* 0 and 1 are NULL IOP and Local Host */
+ struct i2o_controller *c;
+
+ c = kmalloc(sizeof(*c), GFP_KERNEL);
+ if (!c) {
+ printk(KERN_ERR "i2o: Insufficient memory to allocate the "
+ "controller.\n");
+ return ERR_PTR(-ENOMEM);
+ }
+ memset(c, 0, sizeof(*c));
+
+ INIT_LIST_HEAD(&c->devices);
+ c->lock = SPIN_LOCK_UNLOCKED;
+ init_MUTEX(&c->lct_lock);
+ c->unit = unit++;
+ sprintf(c->name, "iop%d", c->unit);
+
+#if BITS_PER_LONG == 64
+ c->context_list_lock = SPIN_LOCK_UNLOCKED;
+ atomic_set(&c->context_list_counter, 0);
+ INIT_LIST_HEAD(&c->context_list);
+#endif
+
+ return c;
+};
+
+/**
+ * i2o_iop_free - Free the i2o_controller struct
+ * @c: I2O controller to free
+ */
+void i2o_iop_free(struct i2o_controller *c)
+{
+ kfree(c);
+};
+
+/**
+ * i2o_iop_add - Initialize the I2O controller and add him to the I2O core
+ * @c: controller
+ *
+ * Initialize the I2O controller and if no error occurs add him to the I2O
+ * core.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+int i2o_iop_add(struct i2o_controller *c)
+{
+ int rc;
+
+ printk(KERN_INFO "%s: Activating I2O controller...\n", c->name);
+ printk(KERN_INFO "%s: This may take a few minutes if there are many "
+ "devices\n", c->name);
+
+ if ((rc = i2o_iop_activate(c))) {
+ printk(KERN_ERR "%s: controller could not activated\n",
+ c->name);
+ i2o_iop_reset(c);
+ return rc;
+ }
+
+ pr_debug("building sys table %s...\n", c->name);
+
+ if ((rc = i2o_systab_build())) {
+ i2o_iop_reset(c);
+ return rc;
+ }
+
+ pr_debug("online controller %s...\n", c->name);
+
+ if ((rc = i2o_iop_online(c))) {
+ i2o_iop_reset(c);
+ return rc;
+ }
+
+ pr_debug("getting LCT %s...\n", c->name);
+
+ if ((rc = i2o_exec_lct_get(c))) {
+ i2o_iop_reset(c);
+ return rc;
+ }
+
+ list_add(&c->list, &i2o_controllers);
+
+ i2o_driver_notify_controller_add_all(c);
+
+ printk(KERN_INFO "%s: Controller added\n", c->name);
+
+ return 0;
+};
+
+/**
+ * i2o_event_register - Turn on/off event notification for a I2O device
+ * @dev: I2O device which should receive the event registration request
+ * @drv: driver which want to get notified
+ * @tcntxt: transaction context to use with this notifier
+ * @evt_mask: mask of events
+ *
+ * Create and posts an event registration message to the task. No reply
+ * is waited for, or expected. If you do not want further notifications,
+ * call the i2o_event_register again with a evt_mask of 0.
+ *
+ * Returns 0 on success or -ETIMEDOUT if no message could be fetched for
+ * sending the request.
+ */
+int i2o_event_register(struct i2o_device *dev, struct i2o_driver *drv,
+ int tcntxt, u32 evt_mask)
+{
+ struct i2o_controller *c = dev->iop;
+ struct i2o_message *msg;
+ u32 m;
+
+ m = i2o_msg_get_wait(c, &msg, I2O_TIMEOUT_MESSAGE_GET);
+ if (m == I2O_QUEUE_EMPTY)
+ return -ETIMEDOUT;
+
+ writel(FIVE_WORD_MSG_SIZE | SGL_OFFSET_0, &msg->u.head[0]);
+ writel(I2O_CMD_UTIL_EVT_REGISTER << 24 | HOST_TID << 12 | dev->lct_data.
+ tid, &msg->u.head[1]);
+ writel(drv->context, &msg->u.s.icntxt);
+ writel(tcntxt, &msg->u.s.tcntxt);
+ writel(evt_mask, &msg->body[0]);
+
+ i2o_msg_post(c, m);
+
+ return 0;
+};
+
+/**
+ * i2o_iop_init - I2O main initialization function
+ *
+ * Initialize the I2O drivers (OSM) functions, register the Executive OSM,
+ * initialize the I2O PCI part and finally initialize I2O device stuff.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int __init i2o_iop_init(void)
+{
+ int rc = 0;
+
+ printk(KERN_INFO "I2O Core - (C) Copyright 1999 Red Hat Software\n");
+
+ rc = i2o_device_init();
+ if (rc)
+ goto exit;
+
+ rc = i2o_driver_init();
+ if (rc)
+ goto device_exit;
+
+ rc = i2o_exec_init();
+ if (rc)
+ goto driver_exit;
+
+ rc = i2o_pci_init();
+ if (rc < 0)
+ goto exec_exit;
+
+ return 0;
+
+ exec_exit:
+ i2o_exec_exit();
+
+ driver_exit:
+ i2o_driver_exit();
+
+ device_exit:
+ i2o_device_exit();
+
+ exit:
+ return rc;
+}
+
+/**
+ * i2o_iop_exit - I2O main exit function
+ *
+ * Removes I2O controllers from PCI subsystem and shut down OSMs.
+ */
+static void __exit i2o_iop_exit(void)
+{
+ i2o_pci_exit();
+ i2o_exec_exit();
+ i2o_driver_exit();
+ i2o_device_exit();
+};
+
+module_init(i2o_iop_init);
+module_exit(i2o_iop_exit);
+
+MODULE_AUTHOR("Red Hat Software");
+MODULE_DESCRIPTION("I2O Core");
+MODULE_LICENSE("GPL");
+
+#if BITS_PER_LONG == 64
+EXPORT_SYMBOL(i2o_cntxt_list_add);
+EXPORT_SYMBOL(i2o_cntxt_list_get);
+EXPORT_SYMBOL(i2o_cntxt_list_remove);
+EXPORT_SYMBOL(i2o_cntxt_list_get_ptr);
+#endif
+EXPORT_SYMBOL(i2o_msg_get_wait);
+EXPORT_SYMBOL(i2o_msg_nop);
+EXPORT_SYMBOL(i2o_find_iop);
+EXPORT_SYMBOL(i2o_iop_find_device);
+EXPORT_SYMBOL(i2o_event_register);
+EXPORT_SYMBOL(i2o_status_get);
+EXPORT_SYMBOL(i2o_hrt_get);
+EXPORT_SYMBOL(i2o_controllers);
--- /dev/null
+/*
+ * PCI handling of I2O controller
+ *
+ * Copyright (C) 1999-2002 Red Hat Software
+ *
+ * Written by Alan Cox, Building Number Three Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * A lot of the I2O message side code from this is taken from the Red
+ * Creek RCPCI45 adapter driver by Red Creek Communications
+ *
+ * Fixes/additions:
+ * Philipp Rumpf
+ * Juha Sievänen <Juha.Sievanen@cs.Helsinki.FI>
+ * Auvo Häkkinen <Auvo.Hakkinen@cs.Helsinki.FI>
+ * Deepak Saxena <deepak@plexity.net>
+ * Boji T Kannanthanam <boji.t.kannanthanam@intel.com>
+ * Alan Cox <alan@redhat.com>:
+ * Ported to Linux 2.5.
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>:
+ * Minor fixes for 2.6.
+ * Markus Lidel <Markus.Lidel@shadowconnect.com>:
+ * Support for sysfs included.
+ */
+
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/i2o.h>
+
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif // CONFIG_MTRR
+
+/* Module internal functions from other sources */
+extern struct i2o_controller *i2o_iop_alloc(void);
+extern void i2o_iop_free(struct i2o_controller *);
+
+extern int i2o_iop_add(struct i2o_controller *);
+extern void i2o_iop_remove(struct i2o_controller *);
+
+extern int i2o_driver_dispatch(struct i2o_controller *, u32,
+ struct i2o_message *);
+
+/* PCI device id table for all I2O controllers */
+static struct pci_device_id __devinitdata i2o_pci_ids[] = {
+ {PCI_DEVICE_CLASS(PCI_CLASS_INTELLIGENT_I2O << 8, 0xffff00)},
+ {PCI_DEVICE(PCI_VENDOR_ID_DPT, 0xa511)},
+ {0}
+};
+
+/**
+ * i2o_dma_realloc - Realloc DMA memory
+ * @dev: struct device pointer to the PCI device of the I2O controller
+ * @addr: pointer to a i2o_dma struct DMA buffer
+ * @len: new length of memory
+ * @gfp_mask: GFP mask
+ *
+ * If there was something allocated in the addr, free it first. If len > 0
+ * than try to allocate it and write the addresses back to the addr
+ * structure. If len == 0 set the virtual address to NULL.
+ *
+ * Returns the 0 on success or negative error code on failure.
+ */
+int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr, size_t len,
+ unsigned int gfp_mask)
+{
+ i2o_dma_free(dev, addr);
+
+ if (len)
+ return i2o_dma_alloc(dev, addr, len, gfp_mask);
+
+ return 0;
+};
+
+/**
+ * i2o_pci_free - Frees the DMA memory for the I2O controller
+ * @c: I2O controller to free
+ *
+ * Remove all allocated DMA memory and unmap memory IO regions. If MTRR
+ * is enabled, also remove it again.
+ */
+static void __devexit i2o_pci_free(struct i2o_controller *c)
+{
+ struct device *dev;
+
+ dev = &c->pdev->dev;
+
+ i2o_dma_free(dev, &c->out_queue);
+ i2o_dma_free(dev, &c->status_block);
+ if (c->lct)
+ kfree(c->lct);
+ i2o_dma_free(dev, &c->dlct);
+ i2o_dma_free(dev, &c->hrt);
+ i2o_dma_free(dev, &c->status);
+
+#ifdef CONFIG_MTRR
+ if (c->mtrr_reg0 >= 0)
+ mtrr_del(c->mtrr_reg0, 0, 0);
+ if (c->mtrr_reg1 >= 0)
+ mtrr_del(c->mtrr_reg1, 0, 0);
+#endif
+
+ if (c->raptor && c->in_queue.virt)
+ iounmap(c->in_queue.virt);
+
+ if (c->base.virt)
+ iounmap(c->base.virt);
+}
+
+/**
+ * i2o_pci_alloc - Allocate DMA memory, map IO memory for I2O controller
+ * @c: I2O controller
+ *
+ * Allocate DMA memory for a PCI (or in theory AGP) I2O controller. All
+ * IO mappings are also done here. If MTRR is enabled, also do add memory
+ * regions here.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int __devinit i2o_pci_alloc(struct i2o_controller *c)
+{
+ struct pci_dev *pdev = c->pdev;
+ struct device *dev = &pdev->dev;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ /* Skip I/O spaces */
+ if (!(pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
+ if (!c->base.phys) {
+ c->base.phys = pci_resource_start(pdev, i);
+ c->base.len = pci_resource_len(pdev, i);
+
+ /*
+ * If we know what card it is, set the size
+ * correctly. Code is taken from dpt_i2o.c
+ */
+ if(pdev->device == 0xa501) {
+ if(pdev->subsystem_device >= 0xc032 &&
+ pdev->subsystem_device <= 0xc03b) {
+ if(c->base.len > 0x400000)
+ c->base.len = 0x400000;
+ } else {
+ if(c->base.len > 0x100000)
+ c->base.len = 0x100000;
+ }
+ }
+ if (!c->raptor)
+ break;
+ } else {
+ c->in_queue.phys = pci_resource_start(pdev, i);
+ c->in_queue.len = pci_resource_len(pdev, i);
+ break;
+ }
+ }
+ }
+
+ if (i == 6) {
+ printk(KERN_ERR "i2o: I2O controller has no memory regions"
+ " defined.\n");
+ i2o_pci_free(c);
+ return -EINVAL;
+ }
+
+ /* Map the I2O controller */
+ if (c->raptor) {
+ printk(KERN_INFO "i2o: PCI I2O controller\n");
+ printk(KERN_INFO " BAR0 at 0x%08lX size=%ld\n",
+ (unsigned long)c->base.phys, (unsigned long)c->base.len);
+ printk(KERN_INFO " BAR1 at 0x%08lX size=%ld\n",
+ (unsigned long)c->in_queue.phys,
+ (unsigned long)c->in_queue.len);
+ } else
+ printk(KERN_INFO "i2o: PCI I2O controller at %08lX size=%ld\n",
+ (unsigned long)c->base.phys, (unsigned long)c->base.len);
+
+ c->base.virt = ioremap(c->base.phys, c->base.len);
+ if (!c->base.virt) {
+ printk(KERN_ERR "i2o: Unable to map controller.\n");
+ return -ENOMEM;
+ }
+
+ if (c->raptor) {
+ c->in_queue.virt = ioremap(c->in_queue.phys, c->in_queue.len);
+ if (!c->in_queue.virt) {
+ printk(KERN_ERR "i2o: Unable to map controller.\n");
+ i2o_pci_free(c);
+ return -ENOMEM;
+ }
+ } else
+ c->in_queue = c->base;
+
+ c->irq_mask = c->base.virt + 0x34;
+ c->post_port = c->base.virt + 0x40;
+ c->reply_port = c->base.virt + 0x44;
+
+#ifdef CONFIG_MTRR
+ /* Enable Write Combining MTRR for IOP's memory region */
+ c->mtrr_reg0 = mtrr_add(c->in_queue.phys, c->in_queue.len,
+ MTRR_TYPE_WRCOMB, 1);
+ c->mtrr_reg1 = -1;
+
+ if (c->mtrr_reg0 < 0)
+ printk(KERN_WARNING "i2o: could not enable write combining "
+ "MTRR\n");
+ else
+ printk(KERN_INFO "i2o: using write combining MTRR\n");
+
+ /*
+ * If it is an INTEL i960 I/O processor then set the first 64K to
+ * Uncacheable since the region contains the messaging unit which
+ * shouldn't be cached.
+ */
+ if ((pdev->vendor == PCI_VENDOR_ID_INTEL ||
+ pdev->vendor == PCI_VENDOR_ID_DPT) && !c->raptor) {
+ printk(KERN_INFO "i2o: MTRR workaround for Intel i960 processor"
+ "\n");
+ c->mtrr_reg1 = mtrr_add(c->base.phys, 0x10000,
+ MTRR_TYPE_UNCACHABLE, 1);
+
+ if (c->mtrr_reg1 < 0) {
+ printk(KERN_WARNING "i2o_pci: Error in setting "
+ "MTRR_TYPE_UNCACHABLE\n");
+ mtrr_del(c->mtrr_reg0, c->in_queue.phys,
+ c->in_queue.len);
+ c->mtrr_reg0 = -1;
+ }
+ }
+#endif
+
+ if (i2o_dma_alloc(dev, &c->status, 4, GFP_KERNEL)) {
+ i2o_pci_free(c);
+ return -ENOMEM;
+ }
+
+ if (i2o_dma_alloc(dev, &c->hrt, sizeof(i2o_hrt), GFP_KERNEL)) {
+ i2o_pci_free(c);
+ return -ENOMEM;
+ }
+
+ if (i2o_dma_alloc(dev, &c->dlct, 8192, GFP_KERNEL)) {
+ i2o_pci_free(c);
+ return -ENOMEM;
+ }
+
+ if (i2o_dma_alloc(dev, &c->status_block, sizeof(i2o_status_block),
+ GFP_KERNEL)) {
+ i2o_pci_free(c);
+ return -ENOMEM;
+ }
+
+ if (i2o_dma_alloc(dev, &c->out_queue, MSG_POOL_SIZE, GFP_KERNEL)) {
+ i2o_pci_free(c);
+ return -ENOMEM;
+ }
+
+ pci_set_drvdata(pdev, c);
+
+ return 0;
+}
+
+/**
+ * i2o_pci_interrupt - Interrupt handler for I2O controller
+ * @irq: interrupt line
+ * @dev_id: pointer to the I2O controller
+ * @r: pointer to registers
+ *
+ * Handle an interrupt from a PCI based I2O controller. This turns out
+ * to be rather simple. We keep the controller pointer in the cookie.
+ */
+static irqreturn_t i2o_pci_interrupt(int irq, void *dev_id, struct pt_regs *r)
+{
+ struct i2o_controller *c = dev_id;
+ struct device *dev = &c->pdev->dev;
+ struct i2o_message *m;
+ u32 mv;
+ u32 *msg;
+
+ /*
+ * Old 960 steppings had a bug in the I2O unit that caused
+ * the queue to appear empty when it wasn't.
+ */
+ mv = I2O_REPLY_READ32(c);
+ if (mv == I2O_QUEUE_EMPTY) {
+ mv = I2O_REPLY_READ32(c);
+ if (unlikely(mv == I2O_QUEUE_EMPTY)) {
+ return IRQ_NONE;
+ } else
+ pr_debug("960 bug detected\n");
+ }
+
+ while (mv != I2O_QUEUE_EMPTY) {
+ /*
+ * Map the message from the page frame map to kernel virtual.
+ * Because bus_to_virt is deprecated, we have calculate the
+ * location by ourself!
+ */
+ m = (struct i2o_message *)(mv -
+ (unsigned long)c->out_queue.phys +
+ (unsigned long)c->out_queue.virt);
+
+ msg = (u32 *) m;
+
+ /*
+ * Ensure this message is seen coherently but cachably by
+ * the processor
+ */
+ dma_sync_single_for_cpu(dev, c->out_queue.phys, MSG_FRAME_SIZE,
+ PCI_DMA_FROMDEVICE);
+
+ /* dispatch it */
+ if (i2o_driver_dispatch(c, mv, m))
+ /* flush it if result != 0 */
+ i2o_flush_reply(c, mv);
+
+ /*
+ * That 960 bug again...
+ */
+ mv = I2O_REPLY_READ32(c);
+ if (mv == I2O_QUEUE_EMPTY)
+ mv = I2O_REPLY_READ32(c);
+ }
+ return IRQ_HANDLED;
+}
+
+/**
+ * i2o_pci_irq_enable - Allocate interrupt for I2O controller
+ *
+ * Allocate an interrupt for the I2O controller, and activate interrupts
+ * on the I2O controller.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int i2o_pci_irq_enable(struct i2o_controller *c)
+{
+ struct pci_dev *pdev = c->pdev;
+ int rc;
+
+ I2O_IRQ_WRITE32(c, 0xffffffff);
+
+ if (pdev->irq) {
+ rc = request_irq(pdev->irq, i2o_pci_interrupt, SA_SHIRQ,
+ c->name, c);
+ if (rc < 0) {
+ printk(KERN_ERR "%s: unable to allocate interrupt %d."
+ "\n", c->name, pdev->irq);
+ return rc;
+ }
+ }
+
+ I2O_IRQ_WRITE32(c, 0x00000000);
+
+ printk(KERN_INFO "%s: Installed at IRQ %d\n", c->name, pdev->irq);
+
+ return 0;
+}
+
+/**
+ * i2o_pci_irq_disable - Free interrupt for I2O controller
+ * @c: I2O controller
+ *
+ * Disable interrupts in I2O controller and then free interrupt.
+ */
+static void i2o_pci_irq_disable(struct i2o_controller *c)
+{
+ I2O_IRQ_WRITE32(c, 0xffffffff);
+
+ if (c->pdev->irq > 0)
+ free_irq(c->pdev->irq, c);
+}
+
+/**
+ * i2o_pci_probe - Probe the PCI device for an I2O controller
+ * @dev: PCI device to test
+ * @id: id which matched with the PCI device id table
+ *
+ * Probe the PCI device for any device which is a memory of the
+ * Intelligent, I2O class or an Adaptec Zero Channel Controller. We
+ * attempt to set up each such device and register it with the core.
+ *
+ * Returns 0 on success or negative error code on failure.
+ */
+static int __devinit i2o_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct i2o_controller *c;
+ int rc;
+
+ printk(KERN_INFO "i2o: Checking for PCI I2O controllers...\n");
+
+ if ((pdev->class & 0xff) > 1) {
+ printk(KERN_WARNING "i2o: I2O controller found but does not "
+ "support I2O 1.5 (skipping).\n");
+ return -ENODEV;
+ }
+
+ if ((rc = pci_enable_device(pdev))) {
+ printk(KERN_WARNING "i2o: I2O controller found but could not be"
+ " enabled.\n");
+ return rc;
+ }
+
+ printk(KERN_INFO "i2o: I2O controller found on bus %d at %d.\n",
+ pdev->bus->number, pdev->devfn);
+
+ if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
+ printk(KERN_WARNING "i2o: I2O controller on bus %d at %d: No "
+ "suitable DMA available!\n", pdev->bus->number,
+ pdev->devfn);
+ rc = -ENODEV;
+ goto disable;
+ }
+
+ pci_set_master(pdev);
+
+ c = i2o_iop_alloc();
+ if (IS_ERR(c)) {
+ printk(KERN_ERR "i2o: memory for I2O controller could not be "
+ "allocated\n");
+ rc = PTR_ERR(c);
+ goto disable;
+ }
+
+ c->pdev = pdev;
+ c->device = pdev->dev;
+
+ /* Cards that fall apart if you hit them with large I/O loads... */
+ if (pdev->vendor == PCI_VENDOR_ID_NCR && pdev->device == 0x0630) {
+ c->short_req = 1;
+ printk(KERN_INFO "i2o: Symbios FC920 workarounds activated.\n");
+ }
+
+ if (pdev->subsystem_vendor == PCI_VENDOR_ID_PROMISE) {
+ c->promise = 1;
+ printk(KERN_INFO "i2o: Promise workarounds activated.\n");
+ }
+
+ /* Cards that go bananas if you quiesce them before you reset them. */
+ if (pdev->vendor == PCI_VENDOR_ID_DPT) {
+ c->no_quiesce = 1;
+ if (pdev->device == 0xa511)
+ c->raptor = 1;
+ }
+
+ if ((rc = i2o_pci_alloc(c))) {
+ printk(KERN_ERR "i2o: DMA / IO allocation for I2O controller "
+ " failed\n");
+ goto free_controller;
+ }
+
+ if (i2o_pci_irq_enable(c)) {
+ printk(KERN_ERR "i2o: unable to enable interrupts for I2O "
+ "controller\n");
+ goto free_pci;
+ }
+
+ if ((rc = i2o_iop_add(c)))
+ goto uninstall;
+
+ return 0;
+
+ uninstall:
+ i2o_pci_irq_disable(c);
+
+ free_pci:
+ i2o_pci_free(c);
+
+ free_controller:
+ i2o_iop_free(c);
+
+ disable:
+ pci_disable_device(pdev);
+
+ return rc;
+}
+
+/**
+ * i2o_pci_remove - Removes a I2O controller from the system
+ * pdev: I2O controller which should be removed
+ *
+ * Reset the I2O controller, disable interrupts and remove all allocated
+ * resources.
+ */
+static void __devexit i2o_pci_remove(struct pci_dev *pdev)
+{
+ struct i2o_controller *c;
+ c = pci_get_drvdata(pdev);
+
+ i2o_iop_remove(c);
+ i2o_pci_irq_disable(c);
+ i2o_pci_free(c);
+
+ printk(KERN_INFO "%s: Controller removed.\n", c->name);
+
+ i2o_iop_free(c);
+ pci_disable_device(pdev);
+};
+
+/* PCI driver for I2O controller */
+static struct pci_driver i2o_pci_driver = {
+ .name = "I2O controller",
+ .id_table = i2o_pci_ids,
+ .probe = i2o_pci_probe,
+ .remove = __devexit_p(i2o_pci_remove),
+};
+
+/**
+ * i2o_pci_init - registers I2O PCI driver in PCI subsystem
+ *
+ * Returns > 0 on success or negative error code on failure.
+ */
+int __init i2o_pci_init(void)
+{
+ return pci_register_driver(&i2o_pci_driver);
+};
+
+/**
+ * i2o_pci_exit - unregisters I2O PCI driver from PCI subsystem
+ */
+void __exit i2o_pci_exit(void)
+{
+ pci_unregister_driver(&i2o_pci_driver);
+};
+
+EXPORT_SYMBOL(i2o_dma_realloc);
--- /dev/null
+#
+# MMC subsystem configuration
+#
+
+menu "MMC/SD Card support"
+
+config MMC
+ tristate "MMC support"
+ help
+ MMC is the "multi-media card" bus protocol.
+
+ If you want MMC support, you should say Y here and also
+ to the specific driver for your MMC interface.
+
+config MMC_DEBUG
+ bool "MMC debugging"
+ depends on MMC != n
+ help
+ This is an option for use by developers; most people should
+ say N here. This enables MMC core and driver debugging.
+
+config MMC_BLOCK
+ tristate "MMC block device driver"
+ depends on MMC
+ default y
+ help
+ Say Y here to enable the MMC block device driver support.
+ This provides a block device driver, which you can use to
+ mount the filesystem. Almost everyone wishing MMC support
+ should say Y or M here.
+
+config MMC_ARMMMCI
+ tristate "ARM AMBA Multimedia Card Interface support"
+ depends on ARM_AMBA && MMC
+ help
+ This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
+ Interface (PL180 and PL181) support. If you have an ARM(R)
+ platform with a Multimedia Card slot, say Y or M here.
+
+ If unsure, say N.
+
+config MMC_PXA
+ tristate "Intel PXA255 Multimedia Card Interface support"
+ depends on ARCH_PXA && MMC
+ help
+ This selects the Intel(R) PXA(R) Multimedia card Interface.
+ If you have a PXA(R) platform with a Multimedia Card slot,
+ say Y or M here.
+
+ If unsure, say N.
+
+endmenu
--- /dev/null
+#
+# Makefile for the kernel mmc device drivers.
+#
+
+#
+# Core
+#
+obj-$(CONFIG_MMC) += mmc_core.o
+
+#
+# Media drivers
+#
+obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
+
+#
+# Host drivers
+#
+obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
+obj-$(CONFIG_MMC_PXA) += pxamci.o
+
+mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o
--- /dev/null
+/*
+ * linux/drivers/mmc/mmc.c
+ *
+ * Copyright (C) 2003-2004 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+
+#include "mmc.h"
+
+#ifdef CONFIG_MMC_DEBUG
+#define DBG(x...) printk(KERN_DEBUG x)
+#else
+#define DBG(x...) do { } while (0)
+#endif
+
+#define CMD_RETRIES 3
+
+/*
+ * OCR Bit positions to 10s of Vdd mV.
+ */
+static const unsigned short mmc_ocr_bit_to_vdd[] = {
+ 150, 155, 160, 165, 170, 180, 190, 200,
+ 210, 220, 230, 240, 250, 260, 270, 280,
+ 290, 300, 310, 320, 330, 340, 350, 360
+};
+
+static const unsigned int tran_exp[] = {
+ 10000, 100000, 1000000, 10000000,
+ 0, 0, 0, 0
+};
+
+static const unsigned char tran_mant[] = {
+ 0, 10, 12, 13, 15, 20, 25, 30,
+ 35, 40, 45, 50, 55, 60, 70, 80,
+};
+
+static const unsigned int tacc_exp[] = {
+ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
+};
+
+static const unsigned int tacc_mant[] = {
+ 0, 10, 12, 13, 15, 20, 25, 30,
+ 35, 40, 45, 50, 55, 60, 70, 80,
+};
+
+
+/**
+ * mmc_request_done - finish processing an MMC command
+ * @host: MMC host which completed command
+ * @mrq: MMC request which completed
+ *
+ * MMC drivers should call this function when they have completed
+ * their processing of a command. This should be called before the
+ * data part of the command has completed.
+ */
+void mmc_request_done(struct mmc_host *host, struct mmc_request *mrq)
+{
+ struct mmc_command *cmd = mrq->cmd;
+ int err = mrq->cmd->error;
+ DBG("MMC: req done (%02x): %d: %08x %08x %08x %08x\n", cmd->opcode,
+ err, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
+ if (err && cmd->retries) {
+ cmd->retries--;
+ cmd->error = 0;
+ host->ops->request(host, mrq);
+ } else if (mrq->done) {
+ mrq->done(mrq);
+ }
+}
+
+EXPORT_SYMBOL(mmc_request_done);
+
+/**
+ * mmc_start_request - start a command on a host
+ * @host: MMC host to start command on
+ * @mrq: MMC request to start
+ *
+ * Queue a command on the specified host. We expect the
+ * caller to be holding the host lock with interrupts disabled.
+ */
+void
+mmc_start_request(struct mmc_host *host, struct mmc_request *mrq)
+{
+ DBG("MMC: starting cmd %02x arg %08x flags %08x\n",
+ mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags);
+
+ WARN_ON(host->card_busy == NULL);
+
+ mrq->cmd->error = 0;
+ mrq->cmd->mrq = mrq;
+ if (mrq->data) {
+ mrq->cmd->data = mrq->data;
+ mrq->data->error = 0;
+ mrq->data->mrq = mrq;
+ if (mrq->stop) {
+ mrq->data->stop = mrq->stop;
+ mrq->stop->error = 0;
+ mrq->stop->mrq = mrq;
+ }
+ }
+ host->ops->request(host, mrq);
+}
+
+EXPORT_SYMBOL(mmc_start_request);
+
+static void mmc_wait_done(struct mmc_request *mrq)
+{
+ complete(mrq->done_data);
+}
+
+int mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq)
+{
+ DECLARE_COMPLETION(complete);
+
+ mrq->done_data = &complete;
+ mrq->done = mmc_wait_done;
+
+ mmc_start_request(host, mrq);
+
+ wait_for_completion(&complete);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(mmc_wait_for_req);
+
+/**
+ * mmc_wait_for_cmd - start a command and wait for completion
+ * @host: MMC host to start command
+ * @cmd: MMC command to start
+ * @retries: maximum number of retries
+ *
+ * Start a new MMC command for a host, and wait for the command
+ * to complete. Return any error that occurred while the command
+ * was executing. Do not attempt to parse the response.
+ */
+int mmc_wait_for_cmd(struct mmc_host *host, struct mmc_command *cmd, int retries)
+{
+ struct mmc_request mrq;
+
+ BUG_ON(host->card_busy == NULL);
+
+ memset(&mrq, 0, sizeof(struct mmc_request));
+
+ memset(cmd->resp, 0, sizeof(cmd->resp));
+ cmd->retries = retries;
+
+ mrq.cmd = cmd;
+ cmd->data = NULL;
+
+ mmc_wait_for_req(host, &mrq);
+
+ return cmd->error;
+}
+
+EXPORT_SYMBOL(mmc_wait_for_cmd);
+
+
+
+/**
+ * __mmc_claim_host - exclusively claim a host
+ * @host: mmc host to claim
+ * @card: mmc card to claim host for
+ *
+ * Claim a host for a set of operations. If a valid card
+ * is passed and this wasn't the last card selected, select
+ * the card before returning.
+ *
+ * Note: you should use mmc_card_claim_host or mmc_claim_host.
+ */
+int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ unsigned long flags;
+ int err = 0;
+
+ add_wait_queue(&host->wq, &wait);
+ spin_lock_irqsave(&host->lock, flags);
+ while (1) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ if (host->card_busy == NULL)
+ break;
+ spin_unlock_irqrestore(&host->lock, flags);
+ schedule();
+ spin_lock_irqsave(&host->lock, flags);
+ }
+ set_current_state(TASK_RUNNING);
+ host->card_busy = card;
+ spin_unlock_irqrestore(&host->lock, flags);
+ remove_wait_queue(&host->wq, &wait);
+
+ if (card != (void *)-1 && host->card_selected != card) {
+ struct mmc_command cmd;
+
+ host->card_selected = card;
+
+ cmd.opcode = MMC_SELECT_CARD;
+ cmd.arg = card->rca << 16;
+ cmd.flags = MMC_RSP_R1;
+
+ err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
+ }
+
+ return err;
+}
+
+EXPORT_SYMBOL(__mmc_claim_host);
+
+/**
+ * mmc_release_host - release a host
+ * @host: mmc host to release
+ *
+ * Release a MMC host, allowing others to claim the host
+ * for their operations.
+ */
+void mmc_release_host(struct mmc_host *host)
+{
+ unsigned long flags;
+
+ BUG_ON(host->card_busy == NULL);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->card_busy = NULL;
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ wake_up(&host->wq);
+}
+
+EXPORT_SYMBOL(mmc_release_host);
+
+/*
+ * Ensure that no card is selected.
+ */
+static void mmc_deselect_cards(struct mmc_host *host)
+{
+ struct mmc_command cmd;
+
+ if (host->card_selected) {
+ host->card_selected = NULL;
+
+ cmd.opcode = MMC_SELECT_CARD;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_NONE;
+
+ mmc_wait_for_cmd(host, &cmd, 0);
+ }
+}
+
+
+static inline void mmc_delay(unsigned int ms)
+{
+ if (ms < HZ / 1000) {
+ yield();
+ mdelay(ms);
+ } else {
+ msleep_interruptible (ms);
+ }
+}
+
+/*
+ * Mask off any voltages we don't support and select
+ * the lowest voltage
+ */
+static u32 mmc_select_voltage(struct mmc_host *host, u32 ocr)
+{
+ int bit;
+
+ ocr &= host->ocr_avail;
+
+ bit = ffs(ocr);
+ if (bit) {
+ bit -= 1;
+
+ ocr = 3 << bit;
+
+ host->ios.vdd = bit;
+ host->ops->set_ios(host, &host->ios);
+ } else {
+ ocr = 0;
+ }
+
+ return ocr;
+}
+
+#define UNSTUFF_BITS(resp,start,size) \
+ ({ \
+ const u32 __mask = (1 << (size)) - 1; \
+ const int __off = 3 - ((start) / 32); \
+ const int __shft = (start) & 31; \
+ u32 __res; \
+ \
+ __res = resp[__off] >> __shft; \
+ if ((size) + __shft >= 32) \
+ __res |= resp[__off-1] << (32 - __shft); \
+ __res & __mask; \
+ })
+
+/*
+ * Given the decoded CSD structure, decode the raw CID to our CID structure.
+ */
+static void mmc_decode_cid(struct mmc_card *card)
+{
+ u32 *resp = card->raw_cid;
+
+ memset(&card->cid, 0, sizeof(struct mmc_cid));
+
+ /*
+ * The selection of the format here is guesswork based upon
+ * information people have sent to date.
+ */
+ switch (card->csd.mmca_vsn) {
+ case 0: /* MMC v1.? */
+ case 1: /* MMC v1.4 */
+ card->cid.manfid = UNSTUFF_BITS(resp, 104, 24);
+ card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8);
+ card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8);
+ card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8);
+ card->cid.prod_name[3] = UNSTUFF_BITS(resp, 72, 8);
+ card->cid.prod_name[4] = UNSTUFF_BITS(resp, 64, 8);
+ card->cid.prod_name[5] = UNSTUFF_BITS(resp, 56, 8);
+ card->cid.prod_name[6] = UNSTUFF_BITS(resp, 48, 8);
+ card->cid.hwrev = UNSTUFF_BITS(resp, 44, 4);
+ card->cid.fwrev = UNSTUFF_BITS(resp, 40, 4);
+ card->cid.serial = UNSTUFF_BITS(resp, 16, 24);
+ card->cid.month = UNSTUFF_BITS(resp, 12, 4);
+ card->cid.year = UNSTUFF_BITS(resp, 8, 4) + 1997;
+ break;
+
+ case 2: /* MMC v2.x ? */
+ case 3: /* MMC v3.x ? */
+ card->cid.manfid = UNSTUFF_BITS(resp, 120, 8);
+ card->cid.oemid = UNSTUFF_BITS(resp, 104, 16);
+ card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8);
+ card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8);
+ card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8);
+ card->cid.prod_name[3] = UNSTUFF_BITS(resp, 72, 8);
+ card->cid.prod_name[4] = UNSTUFF_BITS(resp, 64, 8);
+ card->cid.prod_name[5] = UNSTUFF_BITS(resp, 56, 8);
+ card->cid.serial = UNSTUFF_BITS(resp, 16, 32);
+ card->cid.month = UNSTUFF_BITS(resp, 12, 4);
+ card->cid.year = UNSTUFF_BITS(resp, 8, 4) + 1997;
+ break;
+
+ default:
+ printk("%s: card has unknown MMCA version %d\n",
+ card->host->host_name, card->csd.mmca_vsn);
+ mmc_card_set_bad(card);
+ break;
+ }
+}
+
+/*
+ * Given a 128-bit response, decode to our card CSD structure.
+ */
+static void mmc_decode_csd(struct mmc_card *card)
+{
+ struct mmc_csd *csd = &card->csd;
+ unsigned int e, m, csd_struct;
+ u32 *resp = card->raw_csd;
+
+ /*
+ * We only understand CSD structure v1.1 and v2.
+ * v2 has extra information in bits 15, 11 and 10.
+ */
+ csd_struct = UNSTUFF_BITS(resp, 126, 2);
+ if (csd_struct != 1 && csd_struct != 2) {
+ printk("%s: unrecognised CSD structure version %d\n",
+ card->host->host_name, csd_struct);
+ mmc_card_set_bad(card);
+ return;
+ }
+
+ csd->mmca_vsn = UNSTUFF_BITS(resp, 122, 4);
+ m = UNSTUFF_BITS(resp, 115, 4);
+ e = UNSTUFF_BITS(resp, 112, 3);
+ csd->tacc_ns = (tacc_exp[e] * tacc_mant[m] + 9) / 10;
+ csd->tacc_clks = UNSTUFF_BITS(resp, 104, 8) * 100;
+
+ m = UNSTUFF_BITS(resp, 99, 4);
+ e = UNSTUFF_BITS(resp, 96, 3);
+ csd->max_dtr = tran_exp[e] * tran_mant[m];
+ csd->cmdclass = UNSTUFF_BITS(resp, 84, 12);
+
+ e = UNSTUFF_BITS(resp, 47, 3);
+ m = UNSTUFF_BITS(resp, 62, 12);
+ csd->capacity = (1 + m) << (e + 2);
+
+ csd->read_blkbits = UNSTUFF_BITS(resp, 80, 4);
+}
+
+/*
+ * Locate a MMC card on this MMC host given a raw CID.
+ */
+static struct mmc_card *mmc_find_card(struct mmc_host *host, u32 *raw_cid)
+{
+ struct mmc_card *card;
+
+ list_for_each_entry(card, &host->cards, node) {
+ if (memcmp(card->raw_cid, raw_cid, sizeof(card->raw_cid)) == 0)
+ return card;
+ }
+ return NULL;
+}
+
+/*
+ * Allocate a new MMC card, and assign a unique RCA.
+ */
+static struct mmc_card *
+mmc_alloc_card(struct mmc_host *host, u32 *raw_cid, unsigned int *frca)
+{
+ struct mmc_card *card, *c;
+ unsigned int rca = *frca;
+
+ card = kmalloc(sizeof(struct mmc_card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ mmc_init_card(card, host);
+ memcpy(card->raw_cid, raw_cid, sizeof(card->raw_cid));
+
+ again:
+ list_for_each_entry(c, &host->cards, node)
+ if (c->rca == rca) {
+ rca++;
+ goto again;
+ }
+
+ card->rca = rca;
+
+ *frca = rca;
+
+ return card;
+}
+
+/*
+ * Tell attached cards to go to IDLE state
+ */
+static void mmc_idle_cards(struct mmc_host *host)
+{
+ struct mmc_command cmd;
+
+ cmd.opcode = MMC_GO_IDLE_STATE;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_NONE;
+
+ mmc_wait_for_cmd(host, &cmd, 0);
+
+ mmc_delay(1);
+}
+
+/*
+ * Apply power to the MMC stack.
+ */
+static void mmc_power_up(struct mmc_host *host)
+{
+ int bit = fls(host->ocr_avail) - 1;
+
+ host->ios.vdd = bit;
+ host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN;
+ host->ios.power_mode = MMC_POWER_UP;
+ host->ops->set_ios(host, &host->ios);
+
+ mmc_delay(1);
+
+ host->ios.clock = host->f_min;
+ host->ios.power_mode = MMC_POWER_ON;
+ host->ops->set_ios(host, &host->ios);
+
+ mmc_delay(2);
+}
+
+static void mmc_power_off(struct mmc_host *host)
+{
+ host->ios.clock = 0;
+ host->ios.vdd = 0;
+ host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN;
+ host->ios.power_mode = MMC_POWER_OFF;
+ host->ops->set_ios(host, &host->ios);
+}
+
+static int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
+{
+ struct mmc_command cmd;
+ int i, err = 0;
+
+ cmd.opcode = MMC_SEND_OP_COND;
+ cmd.arg = ocr;
+ cmd.flags = MMC_RSP_R3;
+
+ for (i = 100; i; i--) {
+ err = mmc_wait_for_cmd(host, &cmd, 0);
+ if (err != MMC_ERR_NONE)
+ break;
+
+ if (cmd.resp[0] & MMC_CARD_BUSY || ocr == 0)
+ break;
+
+ err = MMC_ERR_TIMEOUT;
+
+ mmc_delay(10);
+ }
+
+ if (rocr)
+ *rocr = cmd.resp[0];
+
+ return err;
+}
+
+/*
+ * Discover cards by requesting their CID. If this command
+ * times out, it is not an error; there are no further cards
+ * to be discovered. Add new cards to the list.
+ *
+ * Create a mmc_card entry for each discovered card, assigning
+ * it an RCA, and save the raw CID for decoding later.
+ */
+static void mmc_discover_cards(struct mmc_host *host)
+{
+ struct mmc_card *card;
+ unsigned int first_rca = 1, err;
+
+ while (1) {
+ struct mmc_command cmd;
+
+ cmd.opcode = MMC_ALL_SEND_CID;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_R2;
+
+ err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
+ if (err == MMC_ERR_TIMEOUT) {
+ err = MMC_ERR_NONE;
+ break;
+ }
+ if (err != MMC_ERR_NONE) {
+ printk(KERN_ERR "%s: error requesting CID: %d\n",
+ host->host_name, err);
+ break;
+ }
+
+ card = mmc_find_card(host, cmd.resp);
+ if (!card) {
+ card = mmc_alloc_card(host, cmd.resp, &first_rca);
+ if (IS_ERR(card)) {
+ err = PTR_ERR(card);
+ break;
+ }
+ list_add(&card->node, &host->cards);
+ }
+
+ card->state &= ~MMC_STATE_DEAD;
+
+ cmd.opcode = MMC_SET_RELATIVE_ADDR;
+ cmd.arg = card->rca << 16;
+ cmd.flags = MMC_RSP_R1;
+
+ err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
+ if (err != MMC_ERR_NONE)
+ mmc_card_set_dead(card);
+ }
+}
+
+static void mmc_read_csds(struct mmc_host *host)
+{
+ struct mmc_card *card;
+
+ list_for_each_entry(card, &host->cards, node) {
+ struct mmc_command cmd;
+ int err;
+
+ if (card->state & (MMC_STATE_DEAD|MMC_STATE_PRESENT))
+ continue;
+
+ cmd.opcode = MMC_SEND_CSD;
+ cmd.arg = card->rca << 16;
+ cmd.flags = MMC_RSP_R2;
+
+ err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
+ if (err != MMC_ERR_NONE) {
+ mmc_card_set_dead(card);
+ continue;
+ }
+
+ memcpy(card->raw_csd, cmd.resp, sizeof(card->raw_csd));
+
+ mmc_decode_csd(card);
+ mmc_decode_cid(card);
+ }
+}
+
+static unsigned int mmc_calculate_clock(struct mmc_host *host)
+{
+ struct mmc_card *card;
+ unsigned int max_dtr = host->f_max;
+
+ list_for_each_entry(card, &host->cards, node)
+ if (!mmc_card_dead(card) && max_dtr > card->csd.max_dtr)
+ max_dtr = card->csd.max_dtr;
+
+ DBG("MMC: selected %d.%03dMHz transfer rate\n",
+ max_dtr / 1000000, (max_dtr / 1000) % 1000);
+
+ return max_dtr;
+}
+
+/*
+ * Check whether cards we already know about are still present.
+ * We do this by requesting status, and checking whether a card
+ * responds.
+ *
+ * A request for status does not cause a state change in data
+ * transfer mode.
+ */
+static void mmc_check_cards(struct mmc_host *host)
+{
+ struct list_head *l, *n;
+
+ mmc_deselect_cards(host);
+
+ list_for_each_safe(l, n, &host->cards) {
+ struct mmc_card *card = mmc_list_to_card(l);
+ struct mmc_command cmd;
+ int err;
+
+ cmd.opcode = MMC_SEND_STATUS;
+ cmd.arg = card->rca << 16;
+ cmd.flags = MMC_RSP_R1;
+
+ err = mmc_wait_for_cmd(host, &cmd, CMD_RETRIES);
+ if (err == MMC_ERR_NONE)
+ continue;
+
+ mmc_card_set_dead(card);
+ }
+}
+
+static void mmc_setup(struct mmc_host *host)
+{
+ if (host->ios.power_mode != MMC_POWER_ON) {
+ int err;
+ u32 ocr;
+
+ mmc_power_up(host);
+ mmc_idle_cards(host);
+
+ err = mmc_send_op_cond(host, 0, &ocr);
+ if (err != MMC_ERR_NONE)
+ return;
+
+ host->ocr = mmc_select_voltage(host, ocr);
+
+ /*
+ * Since we're changing the OCR value, we seem to
+ * need to tell some cards to go back to the idle
+ * state. We wait 1ms to give cards time to
+ * respond.
+ */
+ if (host->ocr)
+ mmc_idle_cards(host);
+ } else {
+ host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN;
+ host->ios.clock = host->f_min;
+ host->ops->set_ios(host, &host->ios);
+
+ /*
+ * We should remember the OCR mask from the existing
+ * cards, and detect the new cards OCR mask, combine
+ * the two and re-select the VDD. However, if we do
+ * change VDD, we should do an idle, and then do a
+ * full re-initialisation. We would need to notify
+ * drivers so that they can re-setup the cards as
+ * well, while keeping their queues at bay.
+ *
+ * For the moment, we take the easy way out - if the
+ * new cards don't like our currently selected VDD,
+ * they drop off the bus.
+ */
+ }
+
+ if (host->ocr == 0)
+ return;
+
+ /*
+ * Send the selected OCR multiple times... until the cards
+ * all get the idea that they should be ready for CMD2.
+ * (My SanDisk card seems to need this.)
+ */
+ mmc_send_op_cond(host, host->ocr, NULL);
+
+ mmc_discover_cards(host);
+
+ /*
+ * Ok, now switch to push-pull mode.
+ */
+ host->ios.bus_mode = MMC_BUSMODE_PUSHPULL;
+ host->ops->set_ios(host, &host->ios);
+
+ mmc_read_csds(host);
+}
+
+
+/**
+ * mmc_detect_change - process change of state on a MMC socket
+ * @host: host which changed state.
+ *
+ * All we know is that card(s) have been inserted or removed
+ * from the socket(s). We don't know which socket or cards.
+ */
+void mmc_detect_change(struct mmc_host *host)
+{
+ schedule_work(&host->detect);
+}
+
+EXPORT_SYMBOL(mmc_detect_change);
+
+
+static void mmc_rescan(void *data)
+{
+ struct mmc_host *host = data;
+ struct list_head *l, *n;
+
+ mmc_claim_host(host);
+
+ if (host->ios.power_mode == MMC_POWER_ON)
+ mmc_check_cards(host);
+
+ mmc_setup(host);
+
+ if (!list_empty(&host->cards)) {
+ /*
+ * (Re-)calculate the fastest clock rate which the
+ * attached cards and the host support.
+ */
+ host->ios.clock = mmc_calculate_clock(host);
+ host->ops->set_ios(host, &host->ios);
+ }
+
+ mmc_release_host(host);
+
+ list_for_each_safe(l, n, &host->cards) {
+ struct mmc_card *card = mmc_list_to_card(l);
+
+ /*
+ * If this is a new and good card, register it.
+ */
+ if (!mmc_card_present(card) && !mmc_card_dead(card)) {
+ if (mmc_register_card(card))
+ mmc_card_set_dead(card);
+ else
+ mmc_card_set_present(card);
+ }
+
+ /*
+ * If this card is dead, destroy it.
+ */
+ if (mmc_card_dead(card)) {
+ list_del(&card->node);
+ mmc_remove_card(card);
+ }
+ }
+
+ /*
+ * If we discover that there are no cards on the
+ * bus, turn off the clock and power down.
+ */
+ if (list_empty(&host->cards))
+ mmc_power_off(host);
+}
+
+
+/**
+ * mmc_alloc_host - initialise the per-host structure.
+ * @extra: sizeof private data structure
+ * @dev: pointer to host device model structure
+ *
+ * Initialise the per-host structure.
+ */
+struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
+{
+ struct mmc_host *host;
+
+ host = kmalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL);
+ if (host) {
+ memset(host, 0, sizeof(struct mmc_host) + extra);
+
+ spin_lock_init(&host->lock);
+ init_waitqueue_head(&host->wq);
+ INIT_LIST_HEAD(&host->cards);
+ INIT_WORK(&host->detect, mmc_rescan, host);
+
+ host->dev = dev;
+
+ /*
+ * By default, hosts do not support SGIO or large requests.
+ * They have to set these according to their abilities.
+ */
+ host->max_hw_segs = 1;
+ host->max_phys_segs = 1;
+ host->max_sectors = 1 << (PAGE_CACHE_SHIFT - 9);
+ host->max_seg_size = PAGE_CACHE_SIZE;
+ }
+
+ return host;
+}
+
+EXPORT_SYMBOL(mmc_alloc_host);
+
+/**
+ * mmc_add_host - initialise host hardware
+ * @host: mmc host
+ */
+int mmc_add_host(struct mmc_host *host)
+{
+ static unsigned int host_num;
+
+ snprintf(host->host_name, sizeof(host->host_name),
+ "mmc%d", host_num++);
+
+ mmc_power_off(host);
+ mmc_detect_change(host);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(mmc_add_host);
+
+/**
+ * mmc_remove_host - remove host hardware
+ * @host: mmc host
+ *
+ * Unregister and remove all cards associated with this host,
+ * and power down the MMC bus.
+ */
+void mmc_remove_host(struct mmc_host *host)
+{
+ struct list_head *l, *n;
+
+ list_for_each_safe(l, n, &host->cards) {
+ struct mmc_card *card = mmc_list_to_card(l);
+
+ mmc_remove_card(card);
+ }
+
+ mmc_power_off(host);
+}
+
+EXPORT_SYMBOL(mmc_remove_host);
+
+/**
+ * mmc_free_host - free the host structure
+ * @host: mmc host
+ *
+ * Free the host once all references to it have been dropped.
+ */
+void mmc_free_host(struct mmc_host *host)
+{
+ flush_scheduled_work();
+ kfree(host);
+}
+
+EXPORT_SYMBOL(mmc_free_host);
+
+#ifdef CONFIG_PM
+
+/**
+ * mmc_suspend_host - suspend a host
+ * @host: mmc host
+ * @state: suspend mode (PM_SUSPEND_xxx)
+ */
+int mmc_suspend_host(struct mmc_host *host, u32 state)
+{
+ mmc_claim_host(host);
+ mmc_deselect_cards(host);
+ mmc_power_off(host);
+ mmc_release_host(host);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(mmc_suspend_host);
+
+/**
+ * mmc_resume_host - resume a previously suspended host
+ * @host: mmc host
+ */
+int mmc_resume_host(struct mmc_host *host)
+{
+ mmc_detect_change(host);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(mmc_resume_host);
+
+#endif
+
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * linux/drivers/mmc/mmc.h
+ *
+ * Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _MMC_H
+#define _MMC_H
+/* core-internal functions */
+void mmc_init_card(struct mmc_card *card, struct mmc_host *host);
+int mmc_register_card(struct mmc_card *card);
+void mmc_remove_card(struct mmc_card *card);
+#endif
--- /dev/null
+/*
+ * Block driver for media (i.e., flash cards)
+ *
+ * Copyright 2002 Hewlett-Packard Company
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Many thanks to Alessandro Rubini and Jonathan Corbet!
+ *
+ * Author: Andrew Christian
+ * 28 May 2002
+ */
+#include <linux/moduleparam.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/hdreg.h>
+#include <linux/kdev_t.h>
+#include <linux/blkdev.h>
+#include <linux/devfs_fs_kernel.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/protocol.h>
+
+#include <asm/system.h>
+#include <asm/uaccess.h>
+
+#include "mmc_queue.h"
+
+/*
+ * max 8 partitions per card
+ */
+#define MMC_SHIFT 3
+
+static int major;
+
+/*
+ * There is one mmc_blk_data per slot.
+ */
+struct mmc_blk_data {
+ spinlock_t lock;
+ struct gendisk *disk;
+ struct mmc_queue queue;
+
+ unsigned int usage;
+ unsigned int block_bits;
+};
+
+static DECLARE_MUTEX(open_lock);
+
+static struct mmc_blk_data *mmc_blk_get(struct gendisk *disk)
+{
+ struct mmc_blk_data *md;
+
+ down(&open_lock);
+ md = disk->private_data;
+ if (md && md->usage == 0)
+ md = NULL;
+ if (md)
+ md->usage++;
+ up(&open_lock);
+
+ return md;
+}
+
+static void mmc_blk_put(struct mmc_blk_data *md)
+{
+ down(&open_lock);
+ md->usage--;
+ if (md->usage == 0) {
+ put_disk(md->disk);
+ mmc_cleanup_queue(&md->queue);
+ kfree(md);
+ }
+ up(&open_lock);
+}
+
+static int mmc_blk_open(struct inode *inode, struct file *filp)
+{
+ struct mmc_blk_data *md;
+ int ret = -ENXIO;
+
+ md = mmc_blk_get(inode->i_bdev->bd_disk);
+ if (md) {
+ if (md->usage == 2)
+ check_disk_change(inode->i_bdev);
+ ret = 0;
+ }
+
+ return ret;
+}
+
+static int mmc_blk_release(struct inode *inode, struct file *filp)
+{
+ struct mmc_blk_data *md = inode->i_bdev->bd_disk->private_data;
+
+ mmc_blk_put(md);
+ return 0;
+}
+
+static int
+mmc_blk_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct block_device *bdev = inode->i_bdev;
+
+ if (cmd == HDIO_GETGEO) {
+ struct hd_geometry geo;
+
+ memset(&geo, 0, sizeof(struct hd_geometry));
+
+ geo.cylinders = get_capacity(bdev->bd_disk) / (4 * 16);
+ geo.heads = 4;
+ geo.sectors = 16;
+ geo.start = get_start_sect(bdev);
+
+ return copy_to_user((void __user *)arg, &geo, sizeof(geo))
+ ? -EFAULT : 0;
+ }
+
+ return -ENOTTY;
+}
+
+static struct block_device_operations mmc_bdops = {
+ .open = mmc_blk_open,
+ .release = mmc_blk_release,
+ .ioctl = mmc_blk_ioctl,
+ .owner = THIS_MODULE,
+};
+
+struct mmc_blk_request {
+ struct mmc_request mrq;
+ struct mmc_command cmd;
+ struct mmc_command stop;
+ struct mmc_data data;
+};
+
+static int mmc_blk_prep_rq(struct mmc_queue *mq, struct request *req)
+{
+ struct mmc_blk_data *md = mq->data;
+ int stat = BLKPREP_OK;
+
+ /*
+ * If we have no device, we haven't finished initialising.
+ */
+ if (!md || !mq->card) {
+ printk(KERN_ERR "%s: killing request - no device/host\n",
+ req->rq_disk->disk_name);
+ stat = BLKPREP_KILL;
+ }
+
+ return stat;
+}
+
+static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
+{
+ struct mmc_blk_data *md = mq->data;
+ struct mmc_card *card = md->queue.card;
+ int ret;
+
+ if (mmc_card_claim_host(card))
+ goto cmd_err;
+
+ do {
+ struct mmc_blk_request brq;
+ struct mmc_command cmd;
+
+ memset(&brq, 0, sizeof(struct mmc_blk_request));
+ brq.mrq.cmd = &brq.cmd;
+ brq.mrq.data = &brq.data;
+
+ brq.cmd.arg = req->sector << 9;
+ brq.cmd.flags = MMC_RSP_R1;
+ brq.data.req = req;
+ brq.data.timeout_ns = card->csd.tacc_ns * 10;
+ brq.data.timeout_clks = card->csd.tacc_clks * 10;
+ brq.data.blksz_bits = md->block_bits;
+ brq.data.blocks = req->nr_sectors >> (md->block_bits - 9);
+ brq.stop.opcode = MMC_STOP_TRANSMISSION;
+ brq.stop.arg = 0;
+ brq.stop.flags = MMC_RSP_R1B;
+
+ if (rq_data_dir(req) == READ) {
+ brq.cmd.opcode = brq.data.blocks > 1 ? MMC_READ_MULTIPLE_BLOCK : MMC_READ_SINGLE_BLOCK;
+ brq.data.flags |= MMC_DATA_READ;
+ } else {
+ brq.cmd.opcode = MMC_WRITE_BLOCK;
+ brq.cmd.flags = MMC_RSP_R1B;
+ brq.data.flags |= MMC_DATA_WRITE;
+ brq.data.blocks = 1;
+ }
+ brq.mrq.stop = brq.data.blocks > 1 ? &brq.stop : NULL;
+
+ mmc_wait_for_req(card->host, &brq.mrq);
+ if (brq.cmd.error) {
+ printk(KERN_ERR "%s: error %d sending read/write command\n",
+ req->rq_disk->disk_name, brq.cmd.error);
+ goto cmd_err;
+ }
+
+ if (brq.data.error) {
+ printk(KERN_ERR "%s: error %d transferring data\n",
+ req->rq_disk->disk_name, brq.data.error);
+ goto cmd_err;
+ }
+
+ if (brq.stop.error) {
+ printk(KERN_ERR "%s: error %d sending stop command\n",
+ req->rq_disk->disk_name, brq.stop.error);
+ goto cmd_err;
+ }
+
+ do {
+ int err;
+
+ cmd.opcode = MMC_SEND_STATUS;
+ cmd.arg = card->rca << 16;
+ cmd.flags = MMC_RSP_R1;
+ err = mmc_wait_for_cmd(card->host, &cmd, 5);
+ if (err) {
+ printk(KERN_ERR "%s: error %d requesting status\n",
+ req->rq_disk->disk_name, err);
+ goto cmd_err;
+ }
+ } while (!(cmd.resp[0] & R1_READY_FOR_DATA));
+
+#if 0
+ if (cmd.resp[0] & ~0x00000900)
+ printk(KERN_ERR "%s: status = %08x\n",
+ req->rq_disk->disk_name, cmd.resp[0]);
+ if (mmc_decode_status(cmd.resp))
+ goto cmd_err;
+#endif
+
+ /*
+ * A block was successfully transferred.
+ */
+ spin_lock_irq(&md->lock);
+ ret = end_that_request_chunk(req, 1, brq.data.bytes_xfered);
+ if (!ret) {
+ /*
+ * The whole request completed successfully.
+ */
+ add_disk_randomness(req->rq_disk);
+ blkdev_dequeue_request(req);
+ end_that_request_last(req);
+ }
+ spin_unlock_irq(&md->lock);
+ } while (ret);
+
+ mmc_card_release_host(card);
+
+ return 1;
+
+ cmd_err:
+ mmc_card_release_host(card);
+
+ /*
+ * This is a little draconian, but until we get proper
+ * error handling sorted out here, its the best we can
+ * do - especially as some hosts have no idea how much
+ * data was transferred before the error occurred.
+ */
+ spin_lock_irq(&md->lock);
+ do {
+ ret = end_that_request_chunk(req, 0,
+ req->current_nr_sectors << 9);
+ } while (ret);
+
+ add_disk_randomness(req->rq_disk);
+ blkdev_dequeue_request(req);
+ end_that_request_last(req);
+ spin_unlock_irq(&md->lock);
+
+ return 0;
+}
+
+#define MMC_NUM_MINORS (256 >> MMC_SHIFT)
+
+static unsigned long dev_use[MMC_NUM_MINORS/(8*sizeof(unsigned long))];
+
+static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+{
+ struct mmc_blk_data *md;
+ int devidx, ret;
+
+ devidx = find_first_zero_bit(dev_use, MMC_NUM_MINORS);
+ if (devidx >= MMC_NUM_MINORS)
+ return ERR_PTR(-ENOSPC);
+ __set_bit(devidx, dev_use);
+
+ md = kmalloc(sizeof(struct mmc_blk_data), GFP_KERNEL);
+ if (md) {
+ memset(md, 0, sizeof(struct mmc_blk_data));
+
+ md->disk = alloc_disk(1 << MMC_SHIFT);
+ if (md->disk == NULL) {
+ kfree(md);
+ md = ERR_PTR(-ENOMEM);
+ goto out;
+ }
+
+ spin_lock_init(&md->lock);
+ md->usage = 1;
+
+ ret = mmc_init_queue(&md->queue, card, &md->lock);
+ if (ret) {
+ put_disk(md->disk);
+ kfree(md);
+ md = ERR_PTR(ret);
+ goto out;
+ }
+ md->queue.prep_fn = mmc_blk_prep_rq;
+ md->queue.issue_fn = mmc_blk_issue_rq;
+ md->queue.data = md;
+
+ md->disk->major = major;
+ md->disk->first_minor = devidx << MMC_SHIFT;
+ md->disk->fops = &mmc_bdops;
+ md->disk->private_data = md;
+ md->disk->queue = md->queue.queue;
+ md->disk->driverfs_dev = &card->dev;
+
+ sprintf(md->disk->disk_name, "mmcblk%d", devidx);
+ sprintf(md->disk->devfs_name, "mmc/blk%d", devidx);
+
+ md->block_bits = card->csd.read_blkbits;
+
+ blk_queue_hardsect_size(md->queue.queue, 1 << md->block_bits);
+ set_capacity(md->disk, card->csd.capacity);
+ }
+ out:
+ return md;
+}
+
+static int
+mmc_blk_set_blksize(struct mmc_blk_data *md, struct mmc_card *card)
+{
+ struct mmc_command cmd;
+ int err;
+
+ mmc_card_claim_host(card);
+ cmd.opcode = MMC_SET_BLOCKLEN;
+ cmd.arg = 1 << card->csd.read_blkbits;
+ cmd.flags = MMC_RSP_R1;
+ err = mmc_wait_for_cmd(card->host, &cmd, 5);
+ mmc_card_release_host(card);
+
+ if (err) {
+ printk(KERN_ERR "%s: unable to set block size to %d: %d\n",
+ md->disk->disk_name, cmd.arg, err);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mmc_blk_probe(struct mmc_card *card)
+{
+ struct mmc_blk_data *md;
+ int err;
+
+ if (card->csd.cmdclass & ~0x1ff)
+ return -ENODEV;
+
+ if (card->csd.read_blkbits < 9) {
+ printk(KERN_WARNING "%s: read blocksize too small (%u)\n",
+ mmc_card_id(card), 1 << card->csd.read_blkbits);
+ return -ENODEV;
+ }
+
+ md = mmc_blk_alloc(card);
+ if (IS_ERR(md))
+ return PTR_ERR(md);
+
+ err = mmc_blk_set_blksize(md, card);
+ if (err)
+ goto out;
+
+ printk(KERN_INFO "%s: %s %s %dKiB\n",
+ md->disk->disk_name, mmc_card_id(card), mmc_card_name(card),
+ (card->csd.capacity << card->csd.read_blkbits) / 1024);
+
+ mmc_set_drvdata(card, md);
+ add_disk(md->disk);
+ return 0;
+
+ out:
+ mmc_blk_put(md);
+
+ return err;
+}
+
+static void mmc_blk_remove(struct mmc_card *card)
+{
+ struct mmc_blk_data *md = mmc_get_drvdata(card);
+
+ if (md) {
+ int devidx;
+
+ del_gendisk(md->disk);
+
+ /*
+ * I think this is needed.
+ */
+ md->disk->queue = NULL;
+
+ devidx = md->disk->first_minor >> MMC_SHIFT;
+ __clear_bit(devidx, dev_use);
+
+ mmc_blk_put(md);
+ }
+ mmc_set_drvdata(card, NULL);
+}
+
+#ifdef CONFIG_PM
+static int mmc_blk_suspend(struct mmc_card *card, u32 state)
+{
+ struct mmc_blk_data *md = mmc_get_drvdata(card);
+
+ if (md) {
+ mmc_queue_suspend(&md->queue);
+ }
+ return 0;
+}
+
+static int mmc_blk_resume(struct mmc_card *card)
+{
+ struct mmc_blk_data *md = mmc_get_drvdata(card);
+
+ if (md) {
+ mmc_blk_set_blksize(md, card);
+ mmc_queue_resume(&md->queue);
+ }
+ return 0;
+}
+#else
+#define mmc_blk_suspend NULL
+#define mmc_blk_resume NULL
+#endif
+
+static struct mmc_driver mmc_driver = {
+ .drv = {
+ .name = "mmcblk",
+ },
+ .probe = mmc_blk_probe,
+ .remove = mmc_blk_remove,
+ .suspend = mmc_blk_suspend,
+ .resume = mmc_blk_resume,
+};
+
+static int __init mmc_blk_init(void)
+{
+ int res = -ENOMEM;
+
+ res = register_blkdev(major, "mmc");
+ if (res < 0) {
+ printk(KERN_WARNING "Unable to get major %d for MMC media: %d\n",
+ major, res);
+ goto out;
+ }
+ if (major == 0)
+ major = res;
+
+ devfs_mk_dir("mmc");
+ return mmc_register_driver(&mmc_driver);
+
+ out:
+ return res;
+}
+
+static void __exit mmc_blk_exit(void)
+{
+ mmc_unregister_driver(&mmc_driver);
+ devfs_remove("mmc");
+ unregister_blkdev(major, "mmc");
+}
+
+module_init(mmc_blk_init);
+module_exit(mmc_blk_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver");
+
+module_param(major, int, 0444);
+MODULE_PARM_DESC(major, "specify the major device number for MMC block driver");
--- /dev/null
+/*
+ * linux/drivers/mmc/mmc_queue.c
+ *
+ * Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <linux/blkdev.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include "mmc_queue.h"
+
+#define MMC_QUEUE_EXIT (1 << 0)
+#define MMC_QUEUE_SUSPENDED (1 << 1)
+
+/*
+ * Prepare a MMC request. Essentially, this means passing the
+ * preparation off to the media driver. The media driver will
+ * create a mmc_io_request in req->special.
+ */
+static int mmc_prep_request(struct request_queue *q, struct request *req)
+{
+ struct mmc_queue *mq = q->queuedata;
+ int ret = BLKPREP_KILL;
+
+ if (req->flags & REQ_SPECIAL) {
+ /*
+ * Special commands already have the command
+ * blocks already setup in req->special.
+ */
+ BUG_ON(!req->special);
+
+ ret = BLKPREP_OK;
+ } else if (req->flags & (REQ_CMD | REQ_BLOCK_PC)) {
+ /*
+ * Block I/O requests need translating according
+ * to the protocol.
+ */
+ ret = mq->prep_fn(mq, req);
+ } else {
+ /*
+ * Everything else is invalid.
+ */
+ blk_dump_rq_flags(req, "MMC bad request");
+ }
+
+ if (ret == BLKPREP_OK)
+ req->flags |= REQ_DONTPREP;
+
+ return ret;
+}
+
+static int mmc_queue_thread(void *d)
+{
+ struct mmc_queue *mq = d;
+ struct request_queue *q = mq->queue;
+ DECLARE_WAITQUEUE(wait, current);
+
+ /*
+ * Set iothread to ensure that we aren't put to sleep by
+ * the process freezing. We handle suspension ourselves.
+ */
+ current->flags |= PF_MEMALLOC|PF_NOFREEZE;
+
+ daemonize("mmcqd");
+
+ complete(&mq->thread_complete);
+
+ down(&mq->thread_sem);
+ add_wait_queue(&mq->thread_wq, &wait);
+ do {
+ struct request *req = NULL;
+
+ spin_lock_irq(q->queue_lock);
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (!blk_queue_plugged(q))
+ mq->req = req = elv_next_request(q);
+ spin_unlock(q->queue_lock);
+
+ if (!req) {
+ if (mq->flags & MMC_QUEUE_EXIT)
+ break;
+ up(&mq->thread_sem);
+ schedule();
+ down(&mq->thread_sem);
+ continue;
+ }
+ set_current_state(TASK_RUNNING);
+
+ mq->issue_fn(mq, req);
+ } while (1);
+ remove_wait_queue(&mq->thread_wq, &wait);
+ up(&mq->thread_sem);
+
+ complete_and_exit(&mq->thread_complete, 0);
+ return 0;
+}
+
+/*
+ * Generic MMC request handler. This is called for any queue on a
+ * particular host. When the host is not busy, we look for a request
+ * on any queue on this host, and attempt to issue it. This may
+ * not be the queue we were asked to process.
+ */
+static void mmc_request(request_queue_t *q)
+{
+ struct mmc_queue *mq = q->queuedata;
+
+ if (!mq->req)
+ wake_up(&mq->thread_wq);
+}
+
+/**
+ * mmc_init_queue - initialise a queue structure.
+ * @mq: mmc queue
+ * @card: mmc card to attach this queue
+ * @lock: queue lock
+ *
+ * Initialise a MMC card request queue.
+ */
+int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, spinlock_t *lock)
+{
+ struct mmc_host *host = card->host;
+ u64 limit = BLK_BOUNCE_HIGH;
+ int ret;
+
+ if (host->dev->dma_mask && *host->dev->dma_mask)
+ limit = *host->dev->dma_mask;
+
+ mq->card = card;
+ mq->queue = blk_init_queue(mmc_request, lock);
+ if (!mq->queue)
+ return -ENOMEM;
+
+ blk_queue_prep_rq(mq->queue, mmc_prep_request);
+ blk_queue_bounce_limit(mq->queue, limit);
+ blk_queue_max_sectors(mq->queue, host->max_sectors);
+ blk_queue_max_phys_segments(mq->queue, host->max_phys_segs);
+ blk_queue_max_hw_segments(mq->queue, host->max_hw_segs);
+ blk_queue_max_segment_size(mq->queue, host->max_seg_size);
+
+ mq->queue->queuedata = mq;
+ mq->req = NULL;
+
+ init_completion(&mq->thread_complete);
+ init_waitqueue_head(&mq->thread_wq);
+ init_MUTEX(&mq->thread_sem);
+
+ ret = kernel_thread(mmc_queue_thread, mq, CLONE_KERNEL);
+ if (ret < 0) {
+ blk_cleanup_queue(mq->queue);
+ } else {
+ wait_for_completion(&mq->thread_complete);
+ init_completion(&mq->thread_complete);
+ ret = 0;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(mmc_init_queue);
+
+void mmc_cleanup_queue(struct mmc_queue *mq)
+{
+ mq->flags |= MMC_QUEUE_EXIT;
+ wake_up(&mq->thread_wq);
+ wait_for_completion(&mq->thread_complete);
+ blk_cleanup_queue(mq->queue);
+
+ mq->card = NULL;
+}
+EXPORT_SYMBOL(mmc_cleanup_queue);
+
+/**
+ * mmc_queue_suspend - suspend a MMC request queue
+ * @mq: MMC queue to suspend
+ *
+ * Stop the block request queue, and wait for our thread to
+ * complete any outstanding requests. This ensures that we
+ * won't suspend while a request is being processed.
+ */
+void mmc_queue_suspend(struct mmc_queue *mq)
+{
+ request_queue_t *q = mq->queue;
+ unsigned long flags;
+
+ if (!(mq->flags & MMC_QUEUE_SUSPENDED)) {
+ mq->flags |= MMC_QUEUE_SUSPENDED;
+
+ spin_lock_irqsave(q->queue_lock, flags);
+ blk_stop_queue(q);
+ spin_unlock_irqrestore(q->queue_lock, flags);
+
+ down(&mq->thread_sem);
+ }
+}
+EXPORT_SYMBOL(mmc_queue_suspend);
+
+/**
+ * mmc_queue_resume - resume a previously suspended MMC request queue
+ * @mq: MMC queue to resume
+ */
+void mmc_queue_resume(struct mmc_queue *mq)
+{
+ request_queue_t *q = mq->queue;
+ unsigned long flags;
+
+ if (mq->flags & MMC_QUEUE_SUSPENDED) {
+ mq->flags &= ~MMC_QUEUE_SUSPENDED;
+
+ up(&mq->thread_sem);
+
+ spin_lock_irqsave(q->queue_lock, flags);
+ blk_start_queue(q);
+ spin_unlock_irqrestore(q->queue_lock, flags);
+ }
+}
+EXPORT_SYMBOL(mmc_queue_resume);
--- /dev/null
+#ifndef MMC_QUEUE_H
+#define MMC_QUEUE_H
+
+struct request;
+struct task_struct;
+
+struct mmc_queue {
+ struct mmc_card *card;
+ struct completion thread_complete;
+ wait_queue_head_t thread_wq;
+ struct semaphore thread_sem;
+ unsigned int flags;
+ struct request *req;
+ int (*prep_fn)(struct mmc_queue *, struct request *);
+ int (*issue_fn)(struct mmc_queue *, struct request *);
+ void *data;
+ struct request_queue *queue;
+};
+
+struct mmc_io_request {
+ struct request *rq;
+ int num;
+ struct mmc_command selcmd; /* mmc_queue private */
+ struct mmc_command cmd[4]; /* max 4 commands */
+};
+
+extern int mmc_init_queue(struct mmc_queue *, struct mmc_card *, spinlock_t *);
+extern void mmc_cleanup_queue(struct mmc_queue *);
+extern void mmc_queue_suspend(struct mmc_queue *);
+extern void mmc_queue_resume(struct mmc_queue *);
+
+#endif
--- /dev/null
+/*
+ * linux/drivers/mmc/mmc_sysfs.c
+ *
+ * Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * MMC sysfs/driver model support.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include "mmc.h"
+
+#define dev_to_mmc_card(d) container_of(d, struct mmc_card, dev)
+#define to_mmc_driver(d) container_of(d, struct mmc_driver, drv)
+
+static void mmc_release_card(struct device *dev)
+{
+ struct mmc_card *card = dev_to_mmc_card(dev);
+
+ kfree(card);
+}
+
+/*
+ * This currently matches any MMC driver to any MMC card - drivers
+ * themselves make the decision whether to drive this card in their
+ * probe method. However, we force "bad" cards to fail.
+ */
+static int mmc_bus_match(struct device *dev, struct device_driver *drv)
+{
+ struct mmc_card *card = dev_to_mmc_card(dev);
+ return !mmc_card_bad(card);
+}
+
+static int
+mmc_bus_hotplug(struct device *dev, char **envp, int num_envp, char *buf,
+ int buf_size)
+{
+ struct mmc_card *card = dev_to_mmc_card(dev);
+ char ccc[13];
+ int i = 0;
+
+#define add_env(fmt,val) \
+ ({ \
+ int len, ret = -ENOMEM; \
+ if (i < num_envp) { \
+ envp[i++] = buf; \
+ len = snprintf(buf, buf_size, fmt, val) + 1; \
+ buf_size -= len; \
+ buf += len; \
+ if (buf_size >= 0) \
+ ret = 0; \
+ } \
+ ret; \
+ })
+
+ for (i = 0; i < 12; i++)
+ ccc[i] = card->csd.cmdclass & (1 << i) ? '1' : '0';
+ ccc[12] = '\0';
+
+ i = 0;
+ add_env("MMC_CCC=%s", ccc);
+ add_env("MMC_MANFID=%06x", card->cid.manfid);
+ add_env("MMC_NAME=%s", mmc_card_name(card));
+ add_env("MMC_OEMID=%04x", card->cid.oemid);
+
+ return 0;
+}
+
+static int mmc_bus_suspend(struct device *dev, u32 state)
+{
+ struct mmc_driver *drv = to_mmc_driver(dev->driver);
+ struct mmc_card *card = dev_to_mmc_card(dev);
+ int ret = 0;
+
+ if (dev->driver && drv->suspend)
+ ret = drv->suspend(card, state);
+ return ret;
+}
+
+static int mmc_bus_resume(struct device *dev)
+{
+ struct mmc_driver *drv = to_mmc_driver(dev->driver);
+ struct mmc_card *card = dev_to_mmc_card(dev);
+ int ret = 0;
+
+ if (dev->driver && drv->resume)
+ ret = drv->resume(card);
+ return ret;
+}
+
+static struct bus_type mmc_bus_type = {
+ .name = "mmc",
+ .match = mmc_bus_match,
+ .hotplug = mmc_bus_hotplug,
+ .suspend = mmc_bus_suspend,
+ .resume = mmc_bus_resume,
+};
+
+
+static int mmc_drv_probe(struct device *dev)
+{
+ struct mmc_driver *drv = to_mmc_driver(dev->driver);
+ struct mmc_card *card = dev_to_mmc_card(dev);
+
+ return drv->probe(card);
+}
+
+static int mmc_drv_remove(struct device *dev)
+{
+ struct mmc_driver *drv = to_mmc_driver(dev->driver);
+ struct mmc_card *card = dev_to_mmc_card(dev);
+
+ drv->remove(card);
+
+ return 0;
+}
+
+
+/**
+ * mmc_register_driver - register a media driver
+ * @drv: MMC media driver
+ */
+int mmc_register_driver(struct mmc_driver *drv)
+{
+ drv->drv.bus = &mmc_bus_type;
+ drv->drv.probe = mmc_drv_probe;
+ drv->drv.remove = mmc_drv_remove;
+ return driver_register(&drv->drv);
+}
+
+EXPORT_SYMBOL(mmc_register_driver);
+
+/**
+ * mmc_unregister_driver - unregister a media driver
+ * @drv: MMC media driver
+ */
+void mmc_unregister_driver(struct mmc_driver *drv)
+{
+ drv->drv.bus = &mmc_bus_type;
+ driver_unregister(&drv->drv);
+}
+
+EXPORT_SYMBOL(mmc_unregister_driver);
+
+
+#define MMC_ATTR(name, fmt, args...) \
+static ssize_t mmc_dev_show_##name (struct device *dev, char *buf) \
+{ \
+ struct mmc_card *card = dev_to_mmc_card(dev); \
+ return sprintf(buf, fmt, args); \
+} \
+static DEVICE_ATTR(name, S_IRUGO, mmc_dev_show_##name, NULL)
+
+MMC_ATTR(cid, "%08x%08x%08x%08x\n", card->raw_cid[0], card->raw_cid[1],
+ card->raw_cid[2], card->raw_cid[3]);
+MMC_ATTR(csd, "%08x%08x%08x%08x\n", card->raw_csd[0], card->raw_csd[1],
+ card->raw_csd[2], card->raw_csd[3]);
+MMC_ATTR(date, "%02d/%04d\n", card->cid.month, card->cid.year);
+MMC_ATTR(fwrev, "0x%x\n", card->cid.fwrev);
+MMC_ATTR(hwrev, "0x%x\n", card->cid.hwrev);
+MMC_ATTR(manfid, "0x%06x\n", card->cid.manfid);
+MMC_ATTR(name, "%s\n", card->cid.prod_name);
+MMC_ATTR(oemid, "0x%04x\n", card->cid.oemid);
+MMC_ATTR(serial, "0x%08x\n", card->cid.serial);
+
+static struct device_attribute *mmc_dev_attributes[] = {
+ &dev_attr_cid,
+ &dev_attr_csd,
+ &dev_attr_date,
+ &dev_attr_fwrev,
+ &dev_attr_hwrev,
+ &dev_attr_manfid,
+ &dev_attr_name,
+ &dev_attr_oemid,
+ &dev_attr_serial,
+};
+
+/*
+ * Internal function. Initialise a MMC card structure.
+ */
+void mmc_init_card(struct mmc_card *card, struct mmc_host *host)
+{
+ memset(card, 0, sizeof(struct mmc_card));
+ card->host = host;
+ device_initialize(&card->dev);
+ card->dev.parent = card->host->dev;
+ card->dev.bus = &mmc_bus_type;
+ card->dev.release = mmc_release_card;
+}
+
+/*
+ * Internal function. Register a new MMC card with the driver model.
+ */
+int mmc_register_card(struct mmc_card *card)
+{
+ int ret, i;
+
+ snprintf(card->dev.bus_id, sizeof(card->dev.bus_id),
+ "%s:%04x", card->host->host_name, card->rca);
+
+ ret = device_add(&card->dev);
+ if (ret == 0)
+ for (i = 0; i < ARRAY_SIZE(mmc_dev_attributes); i++)
+ device_create_file(&card->dev, mmc_dev_attributes[i]);
+
+ return ret;
+}
+
+/*
+ * Internal function. Unregister a new MMC card with the
+ * driver model, and (eventually) free it.
+ */
+void mmc_remove_card(struct mmc_card *card)
+{
+ if (mmc_card_present(card))
+ device_del(&card->dev);
+
+ put_device(&card->dev);
+}
+
+
+static int __init mmc_init(void)
+{
+ return bus_register(&mmc_bus_type);
+}
+
+static void __exit mmc_exit(void)
+{
+ bus_unregister(&mmc_bus_type);
+}
+
+module_init(mmc_init);
+module_exit(mmc_exit);
--- /dev/null
+/*
+ * linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
+ *
+ * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/hardware/amba.h>
+#include <asm/hardware/clock.h>
+#include <asm/mach/mmc.h>
+
+#include "mmci.h"
+
+#define DRIVER_NAME "mmci-pl18x"
+
+#ifdef CONFIG_MMC_DEBUG
+#define DBG(host,fmt,args...) \
+ pr_debug("%s: %s: " fmt, host->mmc->host_name, __func__ , args)
+#else
+#define DBG(host,fmt,args...) do { } while (0)
+#endif
+
+static unsigned int fmax = 515633;
+
+static void
+mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
+{
+ writel(0, host->base + MMCICOMMAND);
+
+ host->mrq = NULL;
+ host->cmd = NULL;
+
+ if (mrq->data)
+ mrq->data->bytes_xfered = host->data_xfered;
+
+ /*
+ * Need to drop the host lock here; mmc_request_done may call
+ * back into the driver...
+ */
+ spin_unlock(&host->lock);
+ mmc_request_done(host->mmc, mrq);
+ spin_lock(&host->lock);
+}
+
+static void mmci_stop_data(struct mmci_host *host)
+{
+ writel(0, host->base + MMCIDATACTRL);
+ writel(0, host->base + MMCIMASK1);
+ host->data = NULL;
+}
+
+static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
+{
+ unsigned int datactrl, timeout, irqmask;
+ void *base;
+
+ DBG(host, "blksz %04x blks %04x flags %08x\n",
+ 1 << data->blksz_bits, data->blocks, data->flags);
+
+ host->data = data;
+ host->size = data->blocks << data->blksz_bits;
+ host->data_xfered = 0;
+
+ mmci_init_sg(host, data);
+
+ timeout = data->timeout_clks +
+ ((unsigned long long)data->timeout_ns * host->cclk) /
+ 1000000000ULL;
+
+ base = host->base;
+ writel(timeout, base + MMCIDATATIMER);
+ writel(host->size, base + MMCIDATALENGTH);
+
+ datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
+ if (data->flags & MMC_DATA_READ) {
+ datactrl |= MCI_DPSM_DIRECTION;
+ irqmask = MCI_RXFIFOHALFFULLMASK;
+ } else {
+ /*
+ * We don't actually need to include "FIFO empty" here
+ * since its implicit in "FIFO half empty".
+ */
+ irqmask = MCI_TXFIFOHALFEMPTYMASK;
+ }
+
+ writel(datactrl, base + MMCIDATACTRL);
+ writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
+ writel(irqmask, base + MMCIMASK1);
+}
+
+static void
+mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
+{
+ void *base = host->base;
+
+ DBG(host, "op %02x arg %08x flags %08x\n",
+ cmd->opcode, cmd->arg, cmd->flags);
+
+ if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
+ writel(0, base + MMCICOMMAND);
+ udelay(1);
+ }
+
+ c |= cmd->opcode | MCI_CPSM_ENABLE;
+ switch (cmd->flags & MMC_RSP_MASK) {
+ case MMC_RSP_NONE:
+ default:
+ break;
+ case MMC_RSP_LONG:
+ c |= MCI_CPSM_LONGRSP;
+ case MMC_RSP_SHORT:
+ c |= MCI_CPSM_RESPONSE;
+ break;
+ }
+ if (/*interrupt*/0)
+ c |= MCI_CPSM_INTERRUPT;
+
+ host->cmd = cmd;
+
+ writel(cmd->arg, base + MMCIARGUMENT);
+ writel(c, base + MMCICOMMAND);
+}
+
+static void
+mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
+ unsigned int status)
+{
+ if (status & MCI_DATABLOCKEND) {
+ host->data_xfered += 1 << data->blksz_bits;
+ }
+ if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
+ if (status & MCI_DATACRCFAIL)
+ data->error = MMC_ERR_BADCRC;
+ else if (status & MCI_DATATIMEOUT)
+ data->error = MMC_ERR_TIMEOUT;
+ else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
+ data->error = MMC_ERR_FIFO;
+ status |= MCI_DATAEND;
+ }
+ if (status & MCI_DATAEND) {
+ mmci_stop_data(host);
+
+ if (!data->stop) {
+ mmci_request_end(host, data->mrq);
+ } else {
+ mmci_start_command(host, data->stop, 0);
+ }
+ }
+}
+
+static void
+mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
+ unsigned int status)
+{
+ void *base = host->base;
+
+ host->cmd = NULL;
+
+ cmd->resp[0] = readl(base + MMCIRESPONSE0);
+ cmd->resp[1] = readl(base + MMCIRESPONSE1);
+ cmd->resp[2] = readl(base + MMCIRESPONSE2);
+ cmd->resp[3] = readl(base + MMCIRESPONSE3);
+
+ if (status & MCI_CMDTIMEOUT) {
+ cmd->error = MMC_ERR_TIMEOUT;
+ } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
+ cmd->error = MMC_ERR_BADCRC;
+ }
+
+ if (!cmd->data || cmd->error != MMC_ERR_NONE) {
+ mmci_request_end(host, cmd->mrq);
+ } else if (!(cmd->data->flags & MMC_DATA_READ)) {
+ mmci_start_data(host, cmd->data);
+ }
+}
+
+static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
+{
+ void *base = host->base;
+ char *ptr = buffer;
+ u32 status;
+
+ do {
+ int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
+
+ if (count > remain)
+ count = remain;
+
+ if (count <= 0)
+ break;
+
+ readsl(base + MMCIFIFO, ptr, count >> 2);
+
+ ptr += count;
+ remain -= count;
+
+ if (remain == 0)
+ break;
+
+ status = readl(base + MMCISTATUS);
+ } while (status & MCI_RXDATAAVLBL);
+
+ return ptr - buffer;
+}
+
+static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
+{
+ void *base = host->base;
+ char *ptr = buffer;
+
+ do {
+ unsigned int count, maxcnt;
+
+ maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
+ count = min(remain, maxcnt);
+
+ writesl(base + MMCIFIFO, ptr, count >> 2);
+
+ ptr += count;
+ remain -= count;
+
+ if (remain == 0)
+ break;
+
+ status = readl(base + MMCISTATUS);
+ } while (status & MCI_TXFIFOHALFEMPTY);
+
+ return ptr - buffer;
+}
+
+/*
+ * PIO data transfer IRQ handler.
+ */
+static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct mmci_host *host = dev_id;
+ void *base = host->base;
+ u32 status;
+
+ status = readl(base + MMCISTATUS);
+
+ DBG(host, "irq1 %08x\n", status);
+
+ do {
+ unsigned long flags;
+ unsigned int remain, len;
+ char *buffer;
+
+ /*
+ * For write, we only need to test the half-empty flag
+ * here - if the FIFO is completely empty, then by
+ * definition it is more than half empty.
+ *
+ * For read, check for data available.
+ */
+ if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
+ break;
+
+ /*
+ * Map the current scatter buffer.
+ */
+ buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
+ remain = host->sg_ptr->length - host->sg_off;
+
+ len = 0;
+ if (status & MCI_RXACTIVE)
+ len = mmci_pio_read(host, buffer, remain);
+ if (status & MCI_TXACTIVE)
+ len = mmci_pio_write(host, buffer, remain, status);
+
+ /*
+ * Unmap the buffer.
+ */
+ mmci_kunmap_atomic(host, &flags);
+
+ host->sg_off += len;
+ host->size -= len;
+ remain -= len;
+
+ if (remain)
+ break;
+
+ if (!mmci_next_sg(host))
+ break;
+
+ status = readl(base + MMCISTATUS);
+ } while (1);
+
+ /*
+ * If we're nearing the end of the read, switch to
+ * "any data available" mode.
+ */
+ if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
+ writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
+
+ /*
+ * If we run out of data, disable the data IRQs; this
+ * prevents a race where the FIFO becomes empty before
+ * the chip itself has disabled the data path, and
+ * stops us racing with our data end IRQ.
+ */
+ if (host->size == 0) {
+ writel(0, base + MMCIMASK1);
+ writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Handle completion of command and data transfers.
+ */
+static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct mmci_host *host = dev_id;
+ u32 status;
+ int ret = 0;
+
+ spin_lock(&host->lock);
+
+ do {
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+
+ status = readl(host->base + MMCISTATUS);
+ status &= readl(host->base + MMCIMASK0);
+ writel(status, host->base + MMCICLEAR);
+
+ DBG(host, "irq0 %08x\n", status);
+
+ data = host->data;
+ if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
+ MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
+ mmci_data_irq(host, data, status);
+
+ cmd = host->cmd;
+ if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
+ mmci_cmd_irq(host, cmd, status);
+
+ ret = 1;
+ } while (status);
+
+ spin_unlock(&host->lock);
+
+ return IRQ_RETVAL(ret);
+}
+
+static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct mmci_host *host = mmc_priv(mmc);
+
+ WARN_ON(host->mrq != NULL);
+
+ spin_lock_irq(&host->lock);
+
+ host->mrq = mrq;
+
+ if (mrq->data && mrq->data->flags & MMC_DATA_READ)
+ mmci_start_data(host, mrq->data);
+
+ mmci_start_command(host, mrq->cmd, 0);
+
+ spin_unlock_irq(&host->lock);
+}
+
+static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct mmci_host *host = mmc_priv(mmc);
+ u32 clk = 0, pwr = 0;
+
+ DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
+ ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
+
+ if (ios->clock) {
+ if (ios->clock >= host->mclk) {
+ clk = MCI_CLK_BYPASS;
+ host->cclk = host->mclk;
+ } else {
+ clk = host->mclk / (2 * ios->clock) - 1;
+ if (clk > 256)
+ clk = 255;
+ host->cclk = host->mclk / (2 * (clk + 1));
+ }
+ clk |= MCI_CLK_ENABLE;
+ }
+
+ if (host->plat->translate_vdd)
+ pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
+
+ switch (ios->power_mode) {
+ case MMC_POWER_OFF:
+ break;
+ case MMC_POWER_UP:
+ pwr |= MCI_PWR_UP;
+ break;
+ case MMC_POWER_ON:
+ pwr |= MCI_PWR_ON;
+ break;
+ }
+
+ if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
+ pwr |= MCI_ROD;
+
+ writel(clk, host->base + MMCICLOCK);
+
+ if (host->pwr != pwr) {
+ host->pwr = pwr;
+ writel(pwr, host->base + MMCIPOWER);
+ }
+}
+
+static struct mmc_host_ops mmci_ops = {
+ .request = mmci_request,
+ .set_ios = mmci_set_ios,
+};
+
+static void mmci_check_status(unsigned long data)
+{
+ struct mmci_host *host = (struct mmci_host *)data;
+ unsigned int status;
+
+ status = host->plat->status(mmc_dev(host->mmc));
+ if (status ^ host->oldstat)
+ mmc_detect_change(host->mmc);
+
+ host->oldstat = status;
+ mod_timer(&host->timer, jiffies + HZ);
+}
+
+static int mmci_probe(struct amba_device *dev, void *id)
+{
+ struct mmc_platform_data *plat = dev->dev.platform_data;
+ struct mmci_host *host;
+ struct mmc_host *mmc;
+ int ret;
+
+ /* must have platform data */
+ if (!plat) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = amba_request_regions(dev, DRIVER_NAME);
+ if (ret)
+ goto out;
+
+ mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
+ if (!mmc) {
+ ret = -ENOMEM;
+ goto rel_regions;
+ }
+
+ host = mmc_priv(mmc);
+ host->clk = clk_get(&dev->dev, "MCLK");
+ if (IS_ERR(host->clk)) {
+ ret = PTR_ERR(host->clk);
+ host->clk = NULL;
+ goto host_free;
+ }
+
+ ret = clk_use(host->clk);
+ if (ret)
+ goto clk_free;
+
+ ret = clk_enable(host->clk);
+ if (ret)
+ goto clk_unuse;
+
+ host->plat = plat;
+ host->mclk = clk_get_rate(host->clk);
+ host->mmc = mmc;
+ host->base = ioremap(dev->res.start, SZ_4K);
+ if (!host->base) {
+ ret = -ENOMEM;
+ goto clk_disable;
+ }
+
+ mmc->ops = &mmci_ops;
+ mmc->f_min = (host->mclk + 511) / 512;
+ mmc->f_max = min(host->mclk, fmax);
+ mmc->ocr_avail = plat->ocr_mask;
+
+ /*
+ * We can do SGIO
+ */
+ mmc->max_hw_segs = 16;
+ mmc->max_phys_segs = 16;
+
+ /*
+ * Since we only have a 16-bit data length register, we must
+ * ensure that we don't exceed 2^16-1 bytes in a single request.
+ * Choose 64 (512-byte) sectors as the limit.
+ */
+ mmc->max_sectors = 64;
+
+ /*
+ * Set the maximum segment size. Since we aren't doing DMA
+ * (yet) we are only limited by the data length register.
+ */
+ mmc->max_seg_size = mmc->max_sectors << 9;
+
+ spin_lock_init(&host->lock);
+
+ writel(0, host->base + MMCIMASK0);
+ writel(0, host->base + MMCIMASK1);
+ writel(0xfff, host->base + MMCICLEAR);
+
+ ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
+ if (ret)
+ goto unmap;
+
+ ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
+ if (ret)
+ goto irq0_free;
+
+ writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+
+ amba_set_drvdata(dev, mmc);
+
+ mmc_add_host(mmc);
+
+ printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
+ mmc->host_name, amba_rev(dev), amba_config(dev),
+ dev->res.start, dev->irq[0], dev->irq[1]);
+
+ init_timer(&host->timer);
+ host->timer.data = (unsigned long)host;
+ host->timer.function = mmci_check_status;
+ host->timer.expires = jiffies + HZ;
+ add_timer(&host->timer);
+
+ return 0;
+
+ irq0_free:
+ free_irq(dev->irq[0], host);
+ unmap:
+ iounmap(host->base);
+ clk_disable:
+ clk_disable(host->clk);
+ clk_unuse:
+ clk_unuse(host->clk);
+ clk_free:
+ clk_put(host->clk);
+ host_free:
+ mmc_free_host(mmc);
+ rel_regions:
+ amba_release_regions(dev);
+ out:
+ return ret;
+}
+
+static int mmci_remove(struct amba_device *dev)
+{
+ struct mmc_host *mmc = amba_get_drvdata(dev);
+
+ amba_set_drvdata(dev, NULL);
+
+ if (mmc) {
+ struct mmci_host *host = mmc_priv(mmc);
+
+ del_timer_sync(&host->timer);
+
+ mmc_remove_host(mmc);
+
+ writel(0, host->base + MMCIMASK0);
+ writel(0, host->base + MMCIMASK1);
+
+ writel(0, host->base + MMCICOMMAND);
+ writel(0, host->base + MMCIDATACTRL);
+
+ free_irq(dev->irq[0], host);
+ free_irq(dev->irq[1], host);
+
+ iounmap(host->base);
+ clk_disable(host->clk);
+ clk_unuse(host->clk);
+ clk_put(host->clk);
+
+ mmc_free_host(mmc);
+
+ amba_release_regions(dev);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mmci_suspend(struct amba_device *dev, u32 state)
+{
+ struct mmc_host *mmc = amba_get_drvdata(dev);
+ int ret = 0;
+
+ if (mmc) {
+ struct mmci_host *host = mmc_priv(mmc);
+
+ ret = mmc_suspend_host(mmc, state);
+ if (ret == 0)
+ writel(0, host->base + MMCIMASK0);
+ }
+
+ return ret;
+}
+
+static int mmci_resume(struct amba_device *dev)
+{
+ struct mmc_host *mmc = amba_get_drvdata(dev);
+ int ret = 0;
+
+ if (mmc) {
+ struct mmci_host *host = mmc_priv(mmc);
+
+ writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+
+ ret = mmc_resume_host(mmc);
+ }
+
+ return ret;
+}
+#else
+#define mmci_suspend NULL
+#define mmci_resume NULL
+#endif
+
+static struct amba_id mmci_ids[] = {
+ {
+ .id = 0x00041180,
+ .mask = 0x000fffff,
+ },
+ {
+ .id = 0x00041181,
+ .mask = 0x000fffff,
+ },
+ { 0, 0 },
+};
+
+static struct amba_driver mmci_driver = {
+ .drv = {
+ .name = DRIVER_NAME,
+ },
+ .probe = mmci_probe,
+ .remove = mmci_remove,
+ .suspend = mmci_suspend,
+ .resume = mmci_resume,
+ .id_table = mmci_ids,
+};
+
+static int __init mmci_init(void)
+{
+ return amba_driver_register(&mmci_driver);
+}
+
+static void __exit mmci_exit(void)
+{
+ amba_driver_unregister(&mmci_driver);
+}
+
+module_init(mmci_init);
+module_exit(mmci_exit);
+module_param(fmax, uint, 0444);
+
+MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * linux/drivers/mmc/mmci.h - ARM PrimeCell MMCI PL180/1 driver
+ *
+ * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define MMCIPOWER 0x000
+#define MCI_PWR_OFF 0x00
+#define MCI_PWR_UP 0x02
+#define MCI_PWR_ON 0x03
+#define MCI_OD (1 << 6)
+#define MCI_ROD (1 << 7)
+
+#define MMCICLOCK 0x004
+#define MCI_CLK_ENABLE (1 << 8)
+#define MCI_CLK_PWRSAVE (1 << 9)
+#define MCI_CLK_BYPASS (1 << 10)
+
+#define MMCIARGUMENT 0x008
+#define MMCICOMMAND 0x00c
+#define MCI_CPSM_RESPONSE (1 << 6)
+#define MCI_CPSM_LONGRSP (1 << 7)
+#define MCI_CPSM_INTERRUPT (1 << 8)
+#define MCI_CPSM_PENDING (1 << 9)
+#define MCI_CPSM_ENABLE (1 << 10)
+
+#define MMCIRESPCMD 0x010
+#define MMCIRESPONSE0 0x014
+#define MMCIRESPONSE1 0x018
+#define MMCIRESPONSE2 0x01c
+#define MMCIRESPONSE3 0x020
+#define MMCIDATATIMER 0x024
+#define MMCIDATALENGTH 0x028
+#define MMCIDATACTRL 0x02c
+#define MCI_DPSM_ENABLE (1 << 0)
+#define MCI_DPSM_DIRECTION (1 << 1)
+#define MCI_DPSM_MODE (1 << 2)
+#define MCI_DPSM_DMAENABLE (1 << 3)
+
+#define MMCIDATACNT 0x030
+#define MMCISTATUS 0x034
+#define MCI_CMDCRCFAIL (1 << 0)
+#define MCI_DATACRCFAIL (1 << 1)
+#define MCI_CMDTIMEOUT (1 << 2)
+#define MCI_DATATIMEOUT (1 << 3)
+#define MCI_TXUNDERRUN (1 << 4)
+#define MCI_RXOVERRUN (1 << 5)
+#define MCI_CMDRESPEND (1 << 6)
+#define MCI_CMDSENT (1 << 7)
+#define MCI_DATAEND (1 << 8)
+#define MCI_DATABLOCKEND (1 << 10)
+#define MCI_CMDACTIVE (1 << 11)
+#define MCI_TXACTIVE (1 << 12)
+#define MCI_RXACTIVE (1 << 13)
+#define MCI_TXFIFOHALFEMPTY (1 << 14)
+#define MCI_RXFIFOHALFFULL (1 << 15)
+#define MCI_TXFIFOFULL (1 << 16)
+#define MCI_RXFIFOFULL (1 << 17)
+#define MCI_TXFIFOEMPTY (1 << 18)
+#define MCI_RXFIFOEMPTY (1 << 19)
+#define MCI_TXDATAAVLBL (1 << 20)
+#define MCI_RXDATAAVLBL (1 << 21)
+
+#define MMCICLEAR 0x038
+#define MCI_CMDCRCFAILCLR (1 << 0)
+#define MCI_DATACRCFAILCLR (1 << 1)
+#define MCI_CMDTIMEOUTCLR (1 << 2)
+#define MCI_DATATIMEOUTCLR (1 << 3)
+#define MCI_TXUNDERRUNCLR (1 << 4)
+#define MCI_RXOVERRUNCLR (1 << 5)
+#define MCI_CMDRESPENDCLR (1 << 6)
+#define MCI_CMDSENTCLR (1 << 7)
+#define MCI_DATAENDCLR (1 << 8)
+#define MCI_DATABLOCKENDCLR (1 << 10)
+
+#define MMCIMASK0 0x03c
+#define MCI_CMDCRCFAILMASK (1 << 0)
+#define MCI_DATACRCFAILMASK (1 << 1)
+#define MCI_CMDTIMEOUTMASK (1 << 2)
+#define MCI_DATATIMEOUTMASK (1 << 3)
+#define MCI_TXUNDERRUNMASK (1 << 4)
+#define MCI_RXOVERRUNMASK (1 << 5)
+#define MCI_CMDRESPENDMASK (1 << 6)
+#define MCI_CMDSENTMASK (1 << 7)
+#define MCI_DATAENDMASK (1 << 8)
+#define MCI_DATABLOCKENDMASK (1 << 10)
+#define MCI_CMDACTIVEMASK (1 << 11)
+#define MCI_TXACTIVEMASK (1 << 12)
+#define MCI_RXACTIVEMASK (1 << 13)
+#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
+#define MCI_RXFIFOHALFFULLMASK (1 << 15)
+#define MCI_TXFIFOFULLMASK (1 << 16)
+#define MCI_RXFIFOFULLMASK (1 << 17)
+#define MCI_TXFIFOEMPTYMASK (1 << 18)
+#define MCI_RXFIFOEMPTYMASK (1 << 19)
+#define MCI_TXDATAAVLBLMASK (1 << 20)
+#define MCI_RXDATAAVLBLMASK (1 << 21)
+
+#define MMCIMASK1 0x040
+#define MMCIFIFOCNT 0x048
+#define MMCIFIFO 0x080 /* to 0x0bc */
+
+#define MCI_IRQENABLE \
+ (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
+ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
+ MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
+
+/*
+ * The size of the FIFO in bytes.
+ */
+#define MCI_FIFOSIZE (16*4)
+
+#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
+
+#define NR_SG 16
+
+struct clk;
+
+struct mmci_host {
+ void *base;
+ struct mmc_request *mrq;
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+ struct mmc_host *mmc;
+ struct clk *clk;
+
+ unsigned int data_xfered;
+
+ spinlock_t lock;
+
+ unsigned int mclk;
+ unsigned int cclk;
+ u32 pwr;
+ struct mmc_platform_data *plat;
+
+ struct timer_list timer;
+ unsigned int oldstat;
+
+ struct scatterlist sg[NR_SG];
+ unsigned int sg_len;
+
+ /* pio stuff */
+ struct scatterlist *sg_ptr;
+ unsigned int sg_off;
+ unsigned int size;
+};
+
+static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
+{
+ struct scatterlist *sg = host->sg;
+ struct request *req = data->req;
+
+ /*
+ * Ideally, we want the higher levels to pass us a scatter list.
+ */
+ host->sg_len = blk_rq_map_sg(req->q, req, sg);
+ host->sg_ptr = sg;
+ host->sg_off = 0;
+}
+
+static inline int mmci_next_sg(struct mmci_host *host)
+{
+ host->sg_ptr++;
+ host->sg_off = 0;
+ return --host->sg_len;
+}
+
+static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags)
+{
+ struct scatterlist *sg = host->sg_ptr;
+
+ local_irq_save(*flags);
+ return kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
+}
+
+static inline void mmci_kunmap_atomic(struct mmci_host *host, unsigned long *flags)
+{
+ kunmap_atomic(host->sg_ptr->page, KM_BIO_SRC_IRQ);
+ local_irq_restore(*flags);
+}
--- /dev/null
+/*
+ * linux/drivers/mmc/pxa.c - PXA MMCI driver
+ *
+ * Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This hardware is really sick:
+ * - No way to clear interrupts.
+ * - Have to turn off the clock whenever we touch the device.
+ * - Doesn't tell you how many data blocks were transferred.
+ * Yuck!
+ *
+ * 1 and 3 byte data transfers not supported
+ * max block length up to 1023
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/dma-mapping.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/mmc.h>
+
+#include "pxamci.h"
+
+#ifdef CONFIG_MMC_DEBUG
+#define DBG(x...) printk(KERN_DEBUG x)
+#else
+#define DBG(x...) do { } while (0)
+#endif
+
+struct pxamci_host {
+ struct mmc_host *mmc;
+ spinlock_t lock;
+ struct resource *res;
+ void *base;
+ int irq;
+ int dma;
+ unsigned int clkrt;
+ unsigned int cmdat;
+ unsigned int imask;
+ unsigned int power_mode;
+ struct pxamci_platform_data *pdata;
+
+ struct mmc_request *mrq;
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+
+ dma_addr_t sg_dma;
+ struct pxa_dma_desc *sg_cpu;
+
+ dma_addr_t dma_buf;
+ unsigned int dma_size;
+ unsigned int dma_dir;
+};
+
+/*
+ * The base MMC clock rate
+ */
+#define CLOCKRATE 20000000
+
+static inline unsigned int ns_to_clocks(unsigned int ns)
+{
+ return (ns * (CLOCKRATE / 1000000) + 999) / 1000;
+}
+
+static void pxamci_stop_clock(struct pxamci_host *host)
+{
+ if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
+ unsigned long timeout = 10000;
+ unsigned int v;
+
+ writel(STOP_CLOCK, host->base + MMC_STRPCL);
+
+ do {
+ v = readl(host->base + MMC_STAT);
+ if (!(v & STAT_CLK_EN))
+ break;
+ udelay(1);
+ } while (timeout--);
+
+ if (v & STAT_CLK_EN)
+ dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
+ }
+}
+
+static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->imask &= ~mask;
+ writel(host->imask, host->base + MMC_I_MASK);
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->imask |= mask;
+ writel(host->imask, host->base + MMC_I_MASK);
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
+{
+ unsigned int nob = data->blocks;
+ unsigned int timeout, size;
+ dma_addr_t dma;
+ u32 dcmd;
+ int i;
+
+ host->data = data;
+
+ if (data->flags & MMC_DATA_STREAM)
+ nob = 0xffff;
+
+ writel(nob, host->base + MMC_NOB);
+ writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
+
+ timeout = ns_to_clocks(data->timeout_ns) + data->timeout_clks;
+ writel((timeout + 255) / 256, host->base + MMC_RDTO);
+
+ if (data->flags & MMC_DATA_READ) {
+ host->dma_dir = DMA_FROM_DEVICE;
+ dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
+ DRCMRTXMMC = 0;
+ DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
+ } else {
+ host->dma_dir = DMA_TO_DEVICE;
+ dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
+ DRCMRRXMMC = 0;
+ DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
+ }
+
+ dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
+
+ host->dma_size = data->blocks << data->blksz_bits;
+ host->dma_buf = dma_map_single(mmc_dev(host->mmc), data->req->buffer,
+ host->dma_size, host->dma_dir);
+
+ for (i = 0, size = host->dma_size, dma = host->dma_buf; size; i++) {
+ u32 len = size;
+
+ if (len > DCMD_LENGTH)
+ len = 0x1000;
+
+ if (data->flags & MMC_DATA_READ) {
+ host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
+ host->sg_cpu[i].dtadr = dma;
+ } else {
+ host->sg_cpu[i].dsadr = dma;
+ host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
+ }
+ host->sg_cpu[i].dcmd = dcmd | len;
+
+ dma += len;
+ size -= len;
+
+ if (size) {
+ host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
+ sizeof(struct pxa_dma_desc);
+ } else {
+ host->sg_cpu[i].ddadr = DDADR_STOP;
+ }
+ }
+ wmb();
+
+ DDADR(host->dma) = host->sg_dma;
+ DCSR(host->dma) = DCSR_RUN;
+}
+
+static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
+{
+ WARN_ON(host->cmd != NULL);
+ host->cmd = cmd;
+
+ if (cmd->flags & MMC_RSP_BUSY)
+ cmdat |= CMDAT_BUSY;
+
+ switch (cmd->flags & (MMC_RSP_MASK | MMC_RSP_CRC)) {
+ case MMC_RSP_SHORT | MMC_RSP_CRC:
+ cmdat |= CMDAT_RESP_SHORT;
+ break;
+ case MMC_RSP_SHORT:
+ cmdat |= CMDAT_RESP_R3;
+ break;
+ case MMC_RSP_LONG | MMC_RSP_CRC:
+ cmdat |= CMDAT_RESP_R2;
+ break;
+ default:
+ break;
+ }
+
+ writel(cmd->opcode, host->base + MMC_CMD);
+ writel(cmd->arg >> 16, host->base + MMC_ARGH);
+ writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
+ writel(cmdat, host->base + MMC_CMDAT);
+ writel(host->clkrt, host->base + MMC_CLKRT);
+
+ writel(START_CLOCK, host->base + MMC_STRPCL);
+
+ pxamci_enable_irq(host, END_CMD_RES);
+}
+
+static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
+{
+ DBG("PXAMCI: request done\n");
+ host->mrq = NULL;
+ host->cmd = NULL;
+ host->data = NULL;
+ mmc_request_done(host->mmc, mrq);
+}
+
+static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
+{
+ struct mmc_command *cmd = host->cmd;
+ int i;
+ u32 v;
+
+ if (!cmd)
+ return 0;
+
+ host->cmd = NULL;
+
+ /*
+ * Did I mention this is Sick. We always need to
+ * discard the upper 8 bits of the first 16-bit word.
+ */
+ v = readl(host->base + MMC_RES) & 0xffff;
+ for (i = 0; i < 4; i++) {
+ u32 w1 = readl(host->base + MMC_RES) & 0xffff;
+ u32 w2 = readl(host->base + MMC_RES) & 0xffff;
+ cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
+ v = w2;
+ }
+
+ if (stat & STAT_TIME_OUT_RESPONSE) {
+ cmd->error = MMC_ERR_TIMEOUT;
+ } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
+ cmd->error = MMC_ERR_BADCRC;
+ }
+
+ pxamci_disable_irq(host, END_CMD_RES);
+ if (host->data && cmd->error == MMC_ERR_NONE) {
+ pxamci_enable_irq(host, DATA_TRAN_DONE);
+ } else {
+ pxamci_finish_request(host, host->mrq);
+ }
+
+ return 1;
+}
+
+static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
+{
+ struct mmc_data *data = host->data;
+
+ if (!data)
+ return 0;
+
+ DCSR(host->dma) = 0;
+ dma_unmap_single(mmc_dev(host->mmc), host->dma_buf, host->dma_size,
+ host->dma_dir);
+
+ if (stat & STAT_READ_TIME_OUT)
+ data->error = MMC_ERR_TIMEOUT;
+ else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
+ data->error = MMC_ERR_BADCRC;
+
+ /*
+ * There appears to be a hardware design bug here. There seems to
+ * be no way to find out how much data was transferred to the card.
+ * This means that if there was an error on any block, we mark all
+ * data blocks as being in error.
+ */
+ if (data->error == MMC_ERR_NONE)
+ data->bytes_xfered = data->blocks << data->blksz_bits;
+ else
+ data->bytes_xfered = 0;
+
+ pxamci_disable_irq(host, DATA_TRAN_DONE);
+
+ host->data = NULL;
+ if (host->mrq->stop && data->error == MMC_ERR_NONE) {
+ pxamci_stop_clock(host);
+ pxamci_start_cmd(host, host->mrq->stop, 0);
+ } else {
+ pxamci_finish_request(host, host->mrq);
+ }
+
+ return 1;
+}
+
+static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
+{
+ struct pxamci_host *host = devid;
+ unsigned int ireg;
+ int handled = 0;
+
+ ireg = readl(host->base + MMC_I_REG);
+
+ DBG("PXAMCI: irq %08x\n", ireg);
+
+ if (ireg) {
+ unsigned stat = readl(host->base + MMC_STAT);
+
+ DBG("PXAMCI: stat %08x\n", stat);
+
+ if (ireg & END_CMD_RES)
+ handled |= pxamci_cmd_done(host, stat);
+ if (ireg & DATA_TRAN_DONE)
+ handled |= pxamci_data_done(host, stat);
+ }
+
+ return IRQ_RETVAL(handled);
+}
+
+static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct pxamci_host *host = mmc_priv(mmc);
+ unsigned int cmdat;
+
+ WARN_ON(host->mrq != NULL);
+
+ host->mrq = mrq;
+
+ pxamci_stop_clock(host);
+
+ cmdat = host->cmdat;
+ host->cmdat &= ~CMDAT_INIT;
+
+ if (mrq->data) {
+ pxamci_setup_data(host, mrq->data);
+
+ cmdat &= ~CMDAT_BUSY;
+ cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
+ if (mrq->data->flags & MMC_DATA_WRITE)
+ cmdat |= CMDAT_WRITE;
+
+ if (mrq->data->flags & MMC_DATA_STREAM)
+ cmdat |= CMDAT_STREAM;
+ }
+
+ pxamci_start_cmd(host, mrq->cmd, cmdat);
+}
+
+static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct pxamci_host *host = mmc_priv(mmc);
+
+ DBG("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
+ ios->clock, ios->power_mode, ios->vdd / 100,
+ ios->vdd % 100);
+
+ if (ios->clock) {
+ unsigned int clk = CLOCKRATE / ios->clock;
+ if (CLOCKRATE / clk > ios->clock)
+ clk <<= 1;
+ host->clkrt = fls(clk) - 1;
+
+ /*
+ * we write clkrt on the next command
+ */
+ } else if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
+ /*
+ * Ensure that the clock is off.
+ */
+ writel(STOP_CLOCK, host->base + MMC_STRPCL);
+ }
+
+ if (host->power_mode != ios->power_mode) {
+ host->power_mode = ios->power_mode;
+
+ if (host->pdata && host->pdata->setpower)
+ host->pdata->setpower(mmc->dev, ios->vdd);
+
+ if (ios->power_mode == MMC_POWER_ON)
+ host->cmdat |= CMDAT_INIT;
+ }
+
+ DBG("pxamci_set_ios: clkrt = %x cmdat = %x\n",
+ host->clkrt, host->cmdat);
+}
+
+static struct mmc_host_ops pxamci_ops = {
+ .request = pxamci_request,
+ .set_ios = pxamci_set_ios,
+};
+
+static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
+{
+ printk(KERN_ERR "DMA%d: IRQ???\n", dma);
+ DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
+}
+
+static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
+{
+ mmc_detect_change(devid);
+ return IRQ_HANDLED;
+}
+
+static int pxamci_probe(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct mmc_host *mmc;
+ struct pxamci_host *host = NULL;
+ struct resource *r;
+ int ret, irq;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irq = platform_get_irq(pdev, 0);
+ if (!r || irq == NO_IRQ)
+ return -ENXIO;
+
+ r = request_mem_region(r->start, SZ_4K, "PXAMCI");
+ if (!r)
+ return -EBUSY;
+
+ mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
+ if (!mmc) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ mmc->ops = &pxamci_ops;
+ mmc->f_min = 312500;
+ mmc->f_max = 20000000;
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+ host->dma = -1;
+ host->pdata = pdev->dev.platform_data;
+ mmc->ocr_avail = host->pdata ?
+ host->pdata->ocr_mask :
+ MMC_VDD_32_33|MMC_VDD_33_34;
+
+ host->sg_cpu = dma_alloc_coherent(dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
+ if (!host->sg_cpu) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ spin_lock_init(&host->lock);
+ host->res = r;
+ host->irq = irq;
+ host->imask = TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
+ END_CMD_RES|PRG_DONE|DATA_TRAN_DONE;
+
+ host->base = ioremap(r->start, SZ_4K);
+ if (!host->base) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /*
+ * Ensure that the host controller is shut down, and setup
+ * with our defaults.
+ */
+ pxamci_stop_clock(host);
+ writel(0, host->base + MMC_SPI);
+ writel(64, host->base + MMC_RESTO);
+ writel(host->imask, host->base + MMC_I_MASK);
+
+ pxa_gpio_mode(GPIO6_MMCCLK_MD);
+ pxa_gpio_mode(GPIO8_MMCCS0_MD);
+ pxa_set_cken(CKEN12_MMC, 1);
+
+ host->dma = pxa_request_dma("PXAMCI", DMA_PRIO_LOW, pxamci_dma_irq, host);
+ if (host->dma < 0) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ ret = request_irq(host->irq, pxamci_irq, 0, "PXAMCI", host);
+ if (ret)
+ goto out;
+
+ dev_set_drvdata(dev, mmc);
+
+ if (host->pdata && host->pdata->init)
+ host->pdata->init(dev, pxamci_detect_irq, mmc);
+
+ mmc_add_host(mmc);
+
+ return 0;
+
+ out:
+ if (host) {
+ if (host->dma >= 0)
+ pxa_free_dma(host->dma);
+ if (host->base)
+ iounmap(host->base);
+ if (host->sg_cpu)
+ dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ }
+ if (mmc)
+ mmc_free_host(mmc);
+ release_resource(r);
+ return ret;
+}
+
+static int pxamci_remove(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+
+ dev_set_drvdata(dev, NULL);
+
+ if (mmc) {
+ struct pxamci_host *host = mmc_priv(mmc);
+
+ if (host->pdata && host->pdata->exit)
+ host->pdata->exit(dev, mmc);
+
+ mmc_remove_host(mmc);
+
+ pxamci_stop_clock(host);
+ writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
+ END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
+ host->base + MMC_I_MASK);
+
+ pxa_set_cken(CKEN12_MMC, 0);
+
+ free_irq(host->irq, host);
+ pxa_free_dma(host->dma);
+ iounmap(host->base);
+ dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+
+ pxa_set_cken(CKEN12_MMC, 0);
+
+ release_resource(host->res);
+
+ mmc_free_host(mmc);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int pxamci_suspend(struct device *dev, u32 state, u32 level)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ int ret = 0;
+
+ if (mmc && level == SUSPEND_DISABLE)
+ ret = mmc_suspend_host(mmc, state);
+
+ return ret;
+}
+
+static int pxamci_resume(struct device *dev, u32 level)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ int ret = 0;
+
+ if (mmc && level == RESUME_ENABLE)
+ ret = mmc_resume_host(mmc);
+
+ return ret;
+}
+#else
+#define pxamci_suspend NULL
+#define pxamci_resume NULL
+#endif
+
+static struct device_driver pxamci_driver = {
+ .name = "pxa2xx-mci",
+ .bus = &platform_bus_type,
+ .probe = pxamci_probe,
+ .remove = pxamci_remove,
+ .suspend = pxamci_suspend,
+ .resume = pxamci_resume,
+};
+
+static int __init pxamci_init(void)
+{
+ return driver_register(&pxamci_driver);
+}
+
+static void __exit pxamci_exit(void)
+{
+ driver_unregister(&pxamci_driver);
+}
+
+module_init(pxamci_init);
+module_exit(pxamci_exit);
+
+MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+#undef MMC_STRPCL
+#undef MMC_STAT
+#undef MMC_CLKRT
+#undef MMC_SPI
+#undef MMC_CMDAT
+#undef MMC_RESTO
+#undef MMC_RDTO
+#undef MMC_BLKLEN
+#undef MMC_NOB
+#undef MMC_PRTBUF
+#undef MMC_I_MASK
+#undef END_CMD_RES
+#undef PRG_DONE
+#undef DATA_TRAN_DONE
+#undef MMC_I_REG
+#undef MMC_CMD
+#undef MMC_ARGH
+#undef MMC_ARGL
+#undef MMC_RES
+#undef MMC_RXFIFO
+#undef MMC_TXFIFO
+
+#define MMC_STRPCL 0x0000
+#define STOP_CLOCK (1 << 0)
+#define START_CLOCK (2 << 0)
+
+#define MMC_STAT 0x0004
+#define STAT_END_CMD_RES (1 << 13)
+#define STAT_PRG_DONE (1 << 12)
+#define STAT_DATA_TRAN_DONE (1 << 11)
+#define STAT_CLK_EN (1 << 8)
+#define STAT_RECV_FIFO_FULL (1 << 7)
+#define STAT_XMIT_FIFO_EMPTY (1 << 6)
+#define STAT_RES_CRC_ERR (1 << 5)
+#define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
+#define STAT_CRC_READ_ERROR (1 << 3)
+#define STAT_CRC_WRITE_ERROR (1 << 2)
+#define STAT_TIME_OUT_RESPONSE (1 << 1)
+#define STAT_READ_TIME_OUT (1 << 0)
+
+#define MMC_CLKRT 0x0008 /* 3 bit */
+
+#define MMC_SPI 0x000c
+#define SPI_CS_ADDRESS (1 << 3)
+#define SPI_CS_EN (1 << 2)
+#define CRC_ON (1 << 1)
+#define SPI_EN (1 << 0)
+
+#define MMC_CMDAT 0x0010
+#define CMDAT_DMAEN (1 << 7)
+#define CMDAT_INIT (1 << 6)
+#define CMDAT_BUSY (1 << 5)
+#define CMDAT_STREAM (1 << 4) /* 1 = stream */
+#define CMDAT_WRITE (1 << 3) /* 1 = write */
+#define CMDAT_DATAEN (1 << 2)
+#define CMDAT_RESP_NONE (0 << 0)
+#define CMDAT_RESP_SHORT (1 << 0)
+#define CMDAT_RESP_R2 (2 << 0)
+#define CMDAT_RESP_R3 (3 << 0)
+
+#define MMC_RESTO 0x0014 /* 7 bit */
+
+#define MMC_RDTO 0x0018 /* 16 bit */
+
+#define MMC_BLKLEN 0x001c /* 10 bit */
+
+#define MMC_NOB 0x0020 /* 16 bit */
+
+#define MMC_PRTBUF 0x0024
+#define BUF_PART_FULL (1 << 0)
+
+#define MMC_I_MASK 0x0028
+#define TXFIFO_WR_REQ (1 << 6)
+#define RXFIFO_RD_REQ (1 << 5)
+#define CLK_IS_OFF (1 << 4)
+#define STOP_CMD (1 << 3)
+#define END_CMD_RES (1 << 2)
+#define PRG_DONE (1 << 1)
+#define DATA_TRAN_DONE (1 << 0)
+
+#define MMC_I_REG 0x002c
+/* same as MMC_I_MASK */
+
+#define MMC_CMD 0x0030
+
+#define MMC_ARGH 0x0034 /* 16 bit */
+
+#define MMC_ARGL 0x0038 /* 16 bit */
+
+#define MMC_RES 0x003c /* 16 bit */
+
+#define MMC_RXFIFO 0x0040 /* 8 bit */
+
+#define MMC_TXFIFO 0x0044 /* 8 bit */
--- /dev/null
+/*
+ * $Id: ixp2000.c,v 1.1 2004/09/02 00:13:41 dsaxena Exp $
+ *
+ * drivers/mtd/maps/ixp2000.c
+ *
+ * Mapping for the Intel XScale IXP2000 based systems
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/flash.h>
+
+#include <linux/reboot.h>
+
+struct ixp2000_flash_info {
+ struct mtd_info *mtd;
+ struct map_info map;
+ struct mtd_partition *partitions;
+ struct resource *res;
+ int nr_banks;
+};
+
+static inline unsigned long flash_bank_setup(struct map_info *map, unsigned long ofs)
+{
+ unsigned long (*set_bank)(unsigned long) =
+ (unsigned long(*)(unsigned long))map->map_priv_2;
+
+ return (set_bank ? set_bank(ofs) : ofs);
+}
+
+#ifdef __ARMEB__
+/*
+ * Rev A0 and A1 of IXP2400 silicon have a broken addressing unit which
+ * causes the lower address bits to be XORed with 0x11 on 8 bit accesses
+ * and XORed with 0x10 on 16 bit accesses. See the spec update, erratta 44.
+ */
+static int errata44_workaround = 0;
+
+static inline unsigned long address_fix8_write(unsigned long addr)
+{
+ if (errata44_workaround) {
+ return (addr ^ 3);
+ }
+ return addr;
+}
+#else
+
+#define address_fix8_write(x) (x)
+#endif
+
+static map_word ixp2000_flash_read8(struct map_info *map, unsigned long ofs)
+{
+ map_word val;
+
+ val.x[0] = *((u8 *)(map->map_priv_1 + flash_bank_setup(map, ofs)));
+ return val;
+}
+
+/*
+ * We can't use the standard memcpy due to the broken SlowPort
+ * address translation on rev A0 and A1 silicon and the fact that
+ * we have banked flash.
+ */
+static void ixp2000_flash_copy_from(struct map_info *map, void *to,
+ unsigned long from, ssize_t len)
+{
+ from = flash_bank_setup(map, from);
+ while(len--)
+ *(__u8 *) to++ = *(__u8 *)(map->map_priv_1 + from++);
+}
+
+static void ixp2000_flash_write8(struct map_info *map, map_word d, unsigned long ofs)
+{
+ *(__u8 *) (address_fix8_write(map->map_priv_1 +
+ flash_bank_setup(map, ofs))) = d.x[0];
+}
+
+static void ixp2000_flash_copy_to(struct map_info *map, unsigned long to,
+ const void *from, ssize_t len)
+{
+ to = flash_bank_setup(map, to);
+ while(len--) {
+ unsigned long tmp = address_fix8_write(map->map_priv_1 + to++);
+ *(__u8 *)(tmp) = *(__u8 *)(from++);
+ }
+}
+
+
+static int ixp2000_flash_remove(struct device *_dev)
+{
+ struct platform_device *dev = to_platform_device(_dev);
+ struct flash_platform_data *plat = dev->dev.platform_data;
+ struct ixp2000_flash_info *info = dev_get_drvdata(&dev->dev);
+
+ dev_set_drvdata(&dev->dev, NULL);
+
+ if(!info)
+ return 0;
+
+ if (info->mtd) {
+ del_mtd_partitions(info->mtd);
+ map_destroy(info->mtd);
+ }
+ if (info->map.map_priv_1)
+ iounmap((void *) info->map.map_priv_1);
+
+ if (info->partitions)
+ kfree(info->partitions);
+
+ if (info->res) {
+ release_resource(info->res);
+ kfree(info->res);
+ }
+
+ if (plat->exit)
+ plat->exit();
+
+ return 0;
+}
+
+
+static int ixp2000_flash_probe(struct device *_dev)
+{
+ static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };
+ struct platform_device *dev = to_platform_device(_dev);
+ struct ixp2000_flash_data *ixp_data = dev->dev.platform_data;
+ struct flash_platform_data *plat;
+ struct ixp2000_flash_info *info;
+ unsigned long window_size;
+ int err = -1;
+
+ if (!ixp_data)
+ return -ENODEV;
+
+ plat = ixp_data->platform_data;
+ if (!plat)
+ return -ENODEV;
+
+ window_size = dev->resource->end - dev->resource->start + 1;
+ dev_info(_dev, "Probe of IXP2000 flash(%d banks x %dM)\n",
+ ixp_data->nr_banks, ((u32)window_size >> 20));
+
+ if (plat->width != 1) {
+ dev_err(_dev, "IXP2000 MTD map only supports 8-bit mode, asking for %d\n",
+ plat->width * 8);
+ return -EIO;
+ }
+
+ info = kmalloc(sizeof(struct ixp2000_flash_info), GFP_KERNEL);
+ if(!info) {
+ err = -ENOMEM;
+ goto Error;
+ }
+ memzero(info, sizeof(struct ixp2000_flash_info));
+
+ dev_set_drvdata(&dev->dev, info);
+
+ /*
+ * Tell the MTD layer we're not 1:1 mapped so that it does
+ * not attempt to do a direct access on us.
+ */
+ info->map.phys = NO_XIP;
+
+ info->nr_banks = ixp_data->nr_banks;
+ info->map.size = ixp_data->nr_banks * window_size;
+ info->map.bankwidth = 1;
+
+ /*
+ * map_priv_2 is used to store a ptr to to the bank_setup routine
+ */
+ info->map.map_priv_2 = (u32) ixp_data->bank_setup;
+
+ info->map.name = dev->dev.bus_id;
+ info->map.read = ixp2000_flash_read8;
+ info->map.write = ixp2000_flash_write8;
+ info->map.copy_from = ixp2000_flash_copy_from;
+ info->map.copy_to = ixp2000_flash_copy_to;
+
+ info->res = request_mem_region(dev->resource->start,
+ dev->resource->end - dev->resource->start + 1,
+ dev->dev.bus_id);
+ if (!info->res) {
+ dev_err(_dev, "Could not reserve memory region\n");
+ err = -ENOMEM;
+ goto Error;
+ }
+
+ info->map.map_priv_1 =
+ (unsigned long) ioremap(dev->resource->start,
+ dev->resource->end - dev->resource->start + 1);
+ if (!info->map.map_priv_1) {
+ dev_err(_dev, "Failed to ioremap flash region\n");
+ err = -EIO;
+ goto Error;
+ }
+
+ /*
+ * Setup read mode for FLASH
+ */
+ *IXP2000_SLOWPORT_FRM = 1;
+
+#if defined(__ARMEB__)
+ /*
+ * Enable errata 44 workaround for NPUs with broken slowport
+ */
+
+ errata44_workaround = ixp2000_has_broken_slowport();
+ dev_info(_dev, "Errata 44 workaround %s\n",
+ errata44_workaround ? "enabled" : "disabled");
+#endif
+
+ info->mtd = do_map_probe(plat->map_name, &info->map);
+ if (!info->mtd) {
+ dev_err(_dev, "map_probe failed\n");
+ err = -ENXIO;
+ goto Error;
+ }
+ info->mtd->owner = THIS_MODULE;
+
+ err = parse_mtd_partitions(info->mtd, probes, &info->partitions, 0);
+ if (err > 0) {
+ err = add_mtd_partitions(info->mtd, info->partitions, err);
+ if(err)
+ dev_err(_dev, "Could not parse partitions\n");
+ }
+
+ if (err)
+ goto Error;
+
+ return 0;
+
+Error:
+ ixp2000_flash_remove(_dev);
+ return err;
+}
+
+static struct device_driver ixp2000_flash_driver = {
+ .name = "IXP2000-Flash",
+ .bus = &platform_bus_type,
+ .probe = &ixp2000_flash_probe,
+ .remove = &ixp2000_flash_remove
+};
+
+static int __init ixp2000_flash_init(void)
+{
+ return driver_register(&ixp2000_flash_driver);
+}
+
+static void __exit ixp2000_flash_exit(void)
+{
+ driver_unregister(&ixp2000_flash_driver);
+}
+
+module_init(ixp2000_flash_init);
+module_exit(ixp2000_flash_exit);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
+
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Patton Electronics Company
+ * Copyright (C) 2002 Momentum Computer
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel@mvista.com or support@mvista.com
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Ethernet driver definitions for the MIPS GT96100 Advanced
+ * Communication Controller.
+ *
+ * Modified for the Marvellous GT64240 Retarded Communication Controller.
+ */
+#ifndef _GT64240ETH_H
+#define _GT64240ETH_H
+
+#include <asm/gt64240.h>
+
+#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
+
+/* Translate those weanie names from Galileo/VxWorks header files: */
+
+#define GT64240_MRR MAIN_ROUTING_REGISTER
+#define GT64240_CIU_ARBITER_CONFIG COMM_UNIT_ARBITER_CONFIGURATION_REGISTER
+#define GT64240_CIU_ARBITER_CONTROL COMM_UNIT_ARBITER_CONTROL
+#define GT64240_MAIN_LOW_CAUSE LOW_INTERRUPT_CAUSE_REGISTER
+#define GT64240_MAIN_HIGH_CAUSE HIGH_INTERRUPT_CAUSE_REGISTER
+#define GT64240_CPU_LOW_MASK CPU_INTERRUPT_MASK_REGISTER_LOW
+#define GT64240_CPU_HIGH_MASK CPU_INTERRUPT_MASK_REGISTER_HIGH
+#define GT64240_CPU_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER
+
+#define GT64240_ETH_PHY_ADDR_REG ETHERNET_PHY_ADDRESS_REGISTER
+#define GT64240_ETH_PORT_CONFIG ETHERNET0_PORT_CONFIGURATION_REGISTER
+#define GT64240_ETH_PORT_CONFIG_EXT ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER
+#define GT64240_ETH_PORT_COMMAND ETHERNET0_PORT_COMMAND_REGISTER
+#define GT64240_ETH_PORT_STATUS ETHERNET0_PORT_STATUS_REGISTER
+#define GT64240_ETH_IO_SIZE ETHERNET_PORTS_DIFFERENCE_OFFSETS
+#define GT64240_ETH_SMI_REG ETHERNET_SMI_REGISTER
+#define GT64240_ETH_MIB_COUNT_BASE ETHERNET0_MIB_COUNTER_BASE
+#define GT64240_ETH_SDMA_CONFIG ETHERNET0_SDMA_CONFIGURATION_REGISTER
+#define GT64240_ETH_SDMA_COMM ETHERNET0_SDMA_COMMAND_REGISTER
+#define GT64240_ETH_INT_MASK ETHERNET0_INTERRUPT_MASK_REGISTER
+#define GT64240_ETH_INT_CAUSE ETHERNET0_INTERRUPT_CAUSE_REGISTER
+#define GT64240_ETH_CURR_TX_DESC_PTR0 ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0
+#define GT64240_ETH_CURR_TX_DESC_PTR1 ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1
+#define GT64240_ETH_1ST_RX_DESC_PTR0 ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0
+#define GT64240_ETH_CURR_RX_DESC_PTR0 ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0
+#define GT64240_ETH_HASH_TBL_PTR ETHERNET0_HASH_TABLE_POINTER_REGISTER
+
+/* Turn on NAPI by default */
+
+#define GT64240_NAPI 1
+
+/* Some 64240 settings that SHOULD eventually be setup in PROM monitor: */
+/* (Board-specific to the DSL3224 Rev A board ONLY!) */
+#define D3224_MPP_CTRL0_SETTING 0x66669900
+#define D3224_MPP_CTRL1_SETTING 0x00000000
+#define D3224_MPP_CTRL2_SETTING 0x00887700
+#define D3224_MPP_CTRL3_SETTING 0x00000044
+#define D3224_GPP_IO_CTRL_SETTING 0x0000e800
+#define D3224_GPP_LEVEL_CTRL_SETTING 0xf001f703
+#define D3224_GPP_VALUE_SETTING 0x00000000
+
+/* Keep the ring sizes a power of two for efficiency. */
+//-#define TX_RING_SIZE 16
+#define TX_RING_SIZE 64 /* TESTING !!! */
+#define RX_RING_SIZE 32
+#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
+
+#define RX_HASH_TABLE_SIZE 16384
+#define HASH_HOP_NUMBER 12
+
+#define NUM_INTERFACES 3
+
+#define GT64240ETH_TX_TIMEOUT HZ/4
+
+#define MIPS_GT64240_BASE 0xf4000000
+#define GT64240_ETH0_BASE (MIPS_GT64240_BASE + GT64240_ETH_PORT_CONFIG)
+#define GT64240_ETH1_BASE (GT64240_ETH0_BASE + GT64240_ETH_IO_SIZE)
+#define GT64240_ETH2_BASE (GT64240_ETH1_BASE + GT64240_ETH_IO_SIZE)
+
+#if defined(CONFIG_MIPS_DSL3224)
+#define GT64240_ETHER0_IRQ 4
+#define GT64240_ETHER1_IRQ 4
+#else
+#define GT64240_ETHER0_IRQ -1
+#define GT64240_ETHER1_IRQ -1
+#endif
+
+#define REV_GT64240 0x1
+#define REV_GT64240A 0x10
+
+#define GT64240ETH_READ(gp, offset) \
+ GT_READ((gp)->port_offset + (offset))
+
+#define GT64240ETH_WRITE(gp, offset, data) \
+ GT_WRITE((gp)->port_offset + (offset), (data))
+
+#define GT64240ETH_SETBIT(gp, offset, bits) \
+ GT64240ETH_WRITE((gp), (offset), \
+ GT64240ETH_READ((gp), (offset)) | (bits))
+
+#define GT64240ETH_CLRBIT(gp, offset, bits) \
+ GT64240ETH_WRITE((gp), (offset), \
+ GT64240ETH_READ((gp), (offset)) & ~(bits))
+
+#define GT64240_READ(ofs) GT_READ(ofs)
+#define GT64240_WRITE(ofs, data) GT_WRITE((ofs), (data))
+
+/* Bit definitions of the SMI Reg */
+enum {
+ smirDataMask = 0xffff,
+ smirPhyAdMask = 0x1f << 16,
+ smirPhyAdBit = 16,
+ smirRegAdMask = 0x1f << 21,
+ smirRegAdBit = 21,
+ smirOpCode = 1 << 26,
+ smirReadValid = 1 << 27,
+ smirBusy = 1 << 28
+};
+
+/* Bit definitions of the Port Config Reg */
+enum pcr_bits {
+ pcrPM = 1 << 0,
+ pcrRBM = 1 << 1,
+ pcrPBF = 1 << 2,
+ pcrEN = 1 << 7,
+ pcrLPBKMask = 0x3 << 8,
+ pcrLPBKBit = 1 << 8,
+ pcrFC = 1 << 10,
+ pcrHS = 1 << 12,
+ pcrHM = 1 << 13,
+ pcrHDM = 1 << 14,
+ pcrHD = 1 << 15,
+ pcrISLMask = 0x7 << 28,
+ pcrISLBit = 28,
+ pcrACCS = 1 << 31
+};
+
+/* Bit definitions of the Port Config Extend Reg */
+enum pcxr_bits {
+ pcxrIGMP = 1,
+ pcxrSPAN = 2,
+ pcxrPAR = 4,
+ pcxrPRIOtxMask = 0x7 << 3,
+ pcxrPRIOtxBit = 3,
+ pcxrPRIOrxMask = 0x3 << 6,
+ pcxrPRIOrxBit = 6,
+ pcxrPRIOrxOverride = 1 << 8,
+ pcxrDPLXen = 1 << 9,
+ pcxrFCTLen = 1 << 10,
+ pcxrFLP = 1 << 11,
+ pcxrFCTL = 1 << 12,
+ pcxrMFLMask = 0x3 << 14,
+ pcxrMFLBit = 14,
+ pcxrMIBclrMode = 1 << 16,
+ pcxrSpeed = 1 << 18,
+ pcxrSpeeden = 1 << 19,
+ pcxrRMIIen = 1 << 20,
+ pcxrDSCPen = 1 << 21
+};
+
+/* Bit definitions of the Port Command Reg */
+enum pcmr_bits {
+ pcmrFJ = 1 << 15
+};
+
+
+/* Bit definitions of the Port Status Reg */
+enum psr_bits {
+ psrSpeed = 1,
+ psrDuplex = 2,
+ psrFctl = 4,
+ psrLink = 8,
+ psrPause = 1 << 4,
+ psrTxLow = 1 << 5,
+ psrTxHigh = 1 << 6,
+ psrTxInProg = 1 << 7
+};
+
+/* Bit definitions of the SDMA Config Reg */
+enum sdcr_bits {
+ sdcrRCMask = 0xf << 2,
+ sdcrRCBit = 2,
+ sdcrBLMR = 1 << 6,
+ sdcrBLMT = 1 << 7,
+ sdcrPOVR = 1 << 8,
+ sdcrRIFB = 1 << 9,
+ sdcrBSZMask = 0x3 << 12,
+ sdcrBSZBit = 12
+};
+
+/* Bit definitions of the SDMA Command Reg */
+enum sdcmr_bits {
+ sdcmrERD = 1 << 7,
+ sdcmrAR = 1 << 15,
+ sdcmrSTDH = 1 << 16,
+ sdcmrSTDL = 1 << 17,
+ sdcmrTXDH = 1 << 23,
+ sdcmrTXDL = 1 << 24,
+ sdcmrAT = 1 << 31
+};
+
+/* Bit definitions of the Interrupt Cause Reg */
+enum icr_bits {
+ icrRxBuffer = 1,
+ icrTxBufferHigh = 1 << 2,
+ icrTxBufferLow = 1 << 3,
+ icrTxEndHigh = 1 << 6,
+ icrTxEndLow = 1 << 7,
+ icrRxError = 1 << 8,
+ icrTxErrorHigh = 1 << 10,
+ icrTxErrorLow = 1 << 11,
+ icrRxOVR = 1 << 12,
+ icrTxUdr = 1 << 13,
+ icrRxBufferQ0 = 1 << 16,
+ icrRxBufferQ1 = 1 << 17,
+ icrRxBufferQ2 = 1 << 18,
+ icrRxBufferQ3 = 1 << 19,
+ icrRxErrorQ0 = 1 << 20,
+ icrRxErrorQ1 = 1 << 21,
+ icrRxErrorQ2 = 1 << 22,
+ icrRxErrorQ3 = 1 << 23,
+ icrMIIPhySTC = 1 << 28,
+ icrSMIdone = 1 << 29,
+ icrEtherIntSum = 1 << 31
+};
+
+
+/* The Rx and Tx descriptor lists. */
+#ifdef __LITTLE_ENDIAN
+typedef struct {
+ u32 cmdstat;
+ u16 reserved; //-prk21aug01 u32 reserved:16;
+ u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16;
+ u32 buff_ptr;
+ u32 next;
+} gt64240_td_t;
+
+typedef struct {
+ u32 cmdstat;
+ u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16;
+ u16 buff_sz; //-prk21aug01 u32 buff_sz:16;
+ u32 buff_ptr;
+ u32 next;
+} gt64240_rd_t;
+#elif defined(__BIG_ENDIAN)
+typedef struct {
+ u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16;
+ u16 reserved; //-prk21aug01 u32 reserved:16;
+ u32 cmdstat;
+ u32 next;
+ u32 buff_ptr;
+} gt64240_td_t;
+
+typedef struct {
+ u16 buff_sz; //-prk21aug01 u32 buff_sz:16;
+ u16 byte_cnt; //-prk21aug01 u32 byte_cnt:16;
+ u32 cmdstat;
+ u32 next;
+ u32 buff_ptr;
+} gt64240_rd_t;
+#else
+#error Either __BIG_ENDIAN or __LITTLE_ENDIAN must be defined!
+#endif
+
+
+/* Values for the Tx command-status descriptor entry. */
+enum td_cmdstat {
+ txOwn = 1 << 31,
+ txAutoMode = 1 << 30,
+ txEI = 1 << 23,
+ txGenCRC = 1 << 22,
+ txPad = 1 << 18,
+ txFirst = 1 << 17,
+ txLast = 1 << 16,
+ txErrorSummary = 1 << 15,
+ txReTxCntMask = 0x0f << 10,
+ txReTxCntBit = 10,
+ txCollision = 1 << 9,
+ txReTxLimit = 1 << 8,
+ txUnderrun = 1 << 6,
+ txLateCollision = 1 << 5
+};
+
+
+/* Values for the Rx command-status descriptor entry. */
+enum rd_cmdstat {
+ rxOwn = 1 << 31,
+ rxAutoMode = 1 << 30,
+ rxEI = 1 << 23,
+ rxFirst = 1 << 17,
+ rxLast = 1 << 16,
+ rxErrorSummary = 1 << 15,
+ rxIGMP = 1 << 14,
+ rxHashExpired = 1 << 13,
+ rxMissedFrame = 1 << 12,
+ rxFrameType = 1 << 11,
+ rxShortFrame = 1 << 8,
+ rxMaxFrameLen = 1 << 7,
+ rxOverrun = 1 << 6,
+ rxCollision = 1 << 4,
+ rxCRCError = 1
+};
+
+/* Bit fields of a Hash Table Entry */
+enum hash_table_entry {
+ hteValid = 1,
+ hteSkip = 2,
+ hteRD = 4
+};
+
+// The MIB counters
+typedef struct {
+ u32 byteReceived;
+ u32 byteSent;
+ u32 framesReceived;
+ u32 framesSent;
+ u32 totalByteReceived;
+ u32 totalFramesReceived;
+ u32 broadcastFramesReceived;
+ u32 multicastFramesReceived;
+ u32 cRCError;
+ u32 oversizeFrames;
+ u32 fragments;
+ u32 jabber;
+ u32 collision;
+ u32 lateCollision;
+ u32 frames64;
+ u32 frames65_127;
+ u32 frames128_255;
+ u32 frames256_511;
+ u32 frames512_1023;
+ u32 frames1024_MaxSize;
+ u32 macRxError;
+ u32 droppedFrames;
+ u32 outMulticastFrames;
+ u32 outBroadcastFrames;
+ u32 undersizeFrames;
+} mib_counters_t;
+
+
+struct gt64240_private {
+ gt64240_rd_t *rx_ring;
+ gt64240_td_t *tx_ring;
+ // The Rx and Tx rings must be 16-byte aligned
+ dma_addr_t rx_ring_dma;
+ dma_addr_t tx_ring_dma;
+ char *hash_table;
+ // The Hash Table must be 8-byte aligned
+ dma_addr_t hash_table_dma;
+ int hash_mode;
+
+ // The Rx buffers must be 8-byte aligned
+ char *rx_buff;
+ dma_addr_t rx_buff_dma;
+ // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
+ // of payload must be 8-byte aligned
+ struct sk_buff *tx_skbuff[TX_RING_SIZE];
+ int rx_next_out; /* The next free ring entry to receive */
+ int tx_next_in; /* The next free ring entry to send */
+ int tx_next_out; /* The last ring entry the ISR processed */
+ int tx_count; /* current # of pkts waiting to be sent in Tx ring */
+ int intr_work_done; /* number of Rx and Tx pkts processed in the isr */
+ int tx_full; /* Tx ring is full */
+
+ mib_counters_t mib;
+ struct net_device_stats stats;
+
+ int io_size;
+ int port_num; // 0 or 1
+ u32 port_offset;
+
+ int phy_addr; // PHY address
+ u32 last_psr; // last value of the port status register
+
+ int options; /* User-settable misc. driver options. */
+ int drv_flags;
+ spinlock_t lock; /* Serialise access to device */
+ struct mii_if_info mii_if;
+
+ u32 msg_enable;
+};
+
+#endif /* _GT64240ETH_H */
--- /dev/null
+/*
+ * drivers/net/mv64340_eth.c - Driver for MV64340X ethernet ports
+ * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
+ *
+ * Based on the 64360 driver from:
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * Copyright (C) 2003 PMC-Sierra, Inc.,
+ * written by Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/fcntl.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ip.h>
+#include <linux/init.h>
+#include <linux/in.h>
+#include <linux/pci.h>
+#include <linux/workqueue.h>
+#include <asm/smp.h>
+#include <linux/skbuff.h>
+#include <linux/tcp.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/ip.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include "mv643xx_eth.h"
+
+/*
+ * The first part is the high level driver of the gigE ethernet ports.
+ */
+
+/* Definition for configuring driver */
+#undef MV64340_RX_QUEUE_FILL_ON_TASK
+
+/* Constants */
+#define EXTRA_BYTES 32
+#define WRAP ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL 0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
+#ifdef MV64340_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL 0x00000000
+#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Static function declarations */
+static int mv64340_eth_real_open(struct net_device *);
+static int mv64340_eth_real_stop(struct net_device *);
+static int mv64340_eth_change_mtu(struct net_device *, int);
+static struct net_device_stats *mv64340_eth_get_stats(struct net_device *);
+static void eth_port_init_mac_tables(unsigned int eth_port_num);
+#ifdef MV64340_NAPI
+static int mv64340_poll(struct net_device *dev, int *budget);
+#endif
+
+unsigned char prom_mac_addr_base[6];
+unsigned long mv64340_sram_base;
+
+/*
+ * Changes MTU (maximum transfer unit) of the gigabit ethenret port
+ *
+ * Input : pointer to ethernet interface network device structure
+ * new mtu size
+ * Output : 0 upon success, -EINVAL upon failure
+ */
+static int mv64340_eth_change_mtu(struct net_device *dev, int new_mtu)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&mp->lock, flags);
+
+ if ((new_mtu > 9500) || (new_mtu < 64)) {
+ spin_unlock_irqrestore(&mp->lock, flags);
+ return -EINVAL;
+ }
+
+ dev->mtu = new_mtu;
+ /*
+ * Stop then re-open the interface. This will allocate RX skb's with
+ * the new MTU.
+ * There is a possible danger that the open will not successed, due
+ * to memory is full, which might fail the open function.
+ */
+ if (netif_running(dev)) {
+ if (mv64340_eth_real_stop(dev))
+ printk(KERN_ERR
+ "%s: Fatal error on stopping device\n",
+ dev->name);
+ if (mv64340_eth_real_open(dev))
+ printk(KERN_ERR
+ "%s: Fatal error on opening device\n",
+ dev->name);
+ }
+
+ spin_unlock_irqrestore(&mp->lock, flags);
+ return 0;
+}
+
+/*
+ * mv64340_eth_rx_task
+ *
+ * Fills / refills RX queue on a certain gigabit ethernet port
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ */
+static void mv64340_eth_rx_task(void *data)
+{
+ struct net_device *dev = (struct net_device *) data;
+ struct mv64340_private *mp = netdev_priv(dev);
+ struct pkt_info pkt_info;
+ struct sk_buff *skb;
+
+ if (test_and_set_bit(0, &mp->rx_task_busy))
+ panic("%s: Error in test_set_bit / clear_bit", dev->name);
+
+ while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
+ /* The +8 for buffer allignment and another 32 byte extra */
+
+ skb = dev_alloc_skb(BUFFER_MTU + 8 + EXTRA_BYTES);
+ if (!skb)
+ /* Better luck next time */
+ break;
+ mp->rx_ring_skbs++;
+ pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
+ pkt_info.byte_cnt = dev->mtu + ETH_HLEN + 4 + 2 + EXTRA_BYTES;
+ /* Allign buffer to 8 bytes */
+ if (pkt_info.byte_cnt & ~0x7) {
+ pkt_info.byte_cnt &= ~0x7;
+ pkt_info.byte_cnt += 8;
+ }
+ pkt_info.buf_ptr =
+ pci_map_single(0, skb->data,
+ dev->mtu + ETH_HLEN + 4 + 2 + EXTRA_BYTES,
+ PCI_DMA_FROMDEVICE);
+ pkt_info.return_info = skb;
+ if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
+ printk(KERN_ERR
+ "%s: Error allocating RX Ring\n", dev->name);
+ break;
+ }
+ skb_reserve(skb, 2);
+ }
+ clear_bit(0, &mp->rx_task_busy);
+ /*
+ * If RX ring is empty of SKB, set a timer to try allocating
+ * again in a later time .
+ */
+ if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
+ printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
+ /* After 100mSec */
+ mp->timeout.expires = jiffies + (HZ / 10);
+ add_timer(&mp->timeout);
+ mp->rx_timer_flag = 1;
+ }
+#if MV64340_RX_QUEUE_FILL_ON_TASK
+ else {
+ /* Return interrupts */
+ MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(mp->port_num),
+ INT_CAUSE_UNMASK_ALL);
+ }
+#endif
+}
+
+/*
+ * mv64340_eth_rx_task_timer_wrapper
+ *
+ * Timer routine to wake up RX queue filling task. This function is
+ * used only in case the RX queue is empty, and all alloc_skb has
+ * failed (due to out of memory event).
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ */
+static void mv64340_eth_rx_task_timer_wrapper(unsigned long data)
+{
+ struct net_device *dev = (struct net_device *) data;
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ mp->rx_timer_flag = 0;
+ mv64340_eth_rx_task((void *) data);
+}
+
+
+/*
+ * mv64340_eth_update_mac_address
+ *
+ * Update the MAC address of the port in the address table
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ */
+static void mv64340_eth_update_mac_address(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+
+ eth_port_init_mac_tables(port_num);
+ memcpy(mp->port_mac_addr, dev->dev_addr, 6);
+ eth_port_uc_addr_set(port_num, mp->port_mac_addr);
+}
+
+/*
+ * mv64340_eth_set_rx_mode
+ *
+ * Change from promiscuos to regular rx mode
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ */
+static void mv64340_eth_set_rx_mode(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ if (dev->flags & IFF_PROMISC) {
+ ethernet_set_config_reg
+ (mp->port_num,
+ ethernet_get_config_reg(mp->port_num) |
+ ETH_UNICAST_PROMISCUOUS_MODE);
+ } else {
+ ethernet_set_config_reg
+ (mp->port_num,
+ ethernet_get_config_reg(mp->port_num) &
+ ~(unsigned int) ETH_UNICAST_PROMISCUOUS_MODE);
+ }
+}
+
+
+/*
+ * mv64340_eth_set_mac_address
+ *
+ * Change the interface's mac address.
+ * No special hardware thing should be done because interface is always
+ * put in promiscuous mode.
+ *
+ * Input : pointer to ethernet interface network device structure and
+ * a pointer to the designated entry to be added to the cache.
+ * Output : zero upon success, negative upon failure
+ */
+static int mv64340_eth_set_mac_address(struct net_device *dev, void *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ /* +2 is for the offset of the HW addr type */
+ dev->dev_addr[i] = ((unsigned char *) addr)[i + 2];
+ mv64340_eth_update_mac_address(dev);
+ return 0;
+}
+
+/*
+ * mv64340_eth_tx_timeout
+ *
+ * Called upon a timeout on transmitting a packet
+ *
+ * Input : pointer to ethernet interface network device structure.
+ * Output : N/A
+ */
+static void mv64340_eth_tx_timeout(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ printk(KERN_INFO "%s: TX timeout ", dev->name);
+
+ /* Do the reset outside of interrupt context */
+ schedule_work(&mp->tx_timeout_task);
+}
+
+/*
+ * mv64340_eth_tx_timeout_task
+ *
+ * Actual routine to reset the adapter when a timeout on Tx has occurred
+ */
+static void mv64340_eth_tx_timeout_task(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ netif_device_detach(dev);
+ eth_port_reset(mp->port_num);
+ eth_port_start(mp);
+ netif_device_attach(dev);
+}
+
+/*
+ * mv64340_eth_free_tx_queue
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : 0 if was able to release skb , nonzero otherwise
+ */
+static int mv64340_eth_free_tx_queue(struct net_device *dev,
+ unsigned int eth_int_cause_ext)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &mp->stats;
+ struct pkt_info pkt_info;
+ int released = 1;
+
+ if (!(eth_int_cause_ext & (BIT0 | BIT8)))
+ return released;
+
+ spin_lock(&mp->lock);
+
+ /* Check only queue 0 */
+ while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
+ if (pkt_info.cmd_sts & BIT0) {
+ printk("%s: Error in TX\n", dev->name);
+ stats->tx_errors++;
+ }
+
+ /*
+ * If return_info is different than 0, release the skb.
+ * The case where return_info is not 0 is only in case
+ * when transmitted a scatter/gather packet, where only
+ * last skb releases the whole chain.
+ */
+ if (pkt_info.return_info) {
+ dev_kfree_skb_irq((struct sk_buff *)
+ pkt_info.return_info);
+ released = 0;
+ if (skb_shinfo(pkt_info.return_info)->nr_frags)
+ pci_unmap_page(NULL, pkt_info.buf_ptr,
+ pkt_info.byte_cnt, PCI_DMA_TODEVICE);
+
+ if (mp->tx_ring_skbs != 1)
+ mp->tx_ring_skbs--;
+ } else
+ pci_unmap_page(NULL, pkt_info.buf_ptr,
+ pkt_info.byte_cnt, PCI_DMA_TODEVICE);
+
+ /*
+ * Decrement the number of outstanding skbs counter on
+ * the TX queue.
+ */
+ if (mp->tx_ring_skbs == 0)
+ panic("ERROR - TX outstanding SKBs counter is corrupted");
+
+ }
+
+ spin_unlock(&mp->lock);
+
+ return released;
+}
+
+/*
+ * mv64340_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ * max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ */
+#ifdef MV64340_NAPI
+static int mv64340_eth_receive_queue(struct net_device *dev, unsigned int max,
+ int budget)
+#else
+static int mv64340_eth_receive_queue(struct net_device *dev, unsigned int max)
+#endif
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &mp->stats;
+ unsigned int received_packets = 0;
+ struct sk_buff *skb;
+ struct pkt_info pkt_info;
+
+#ifdef MV64340_NAPI
+ while (eth_port_receive(mp, &pkt_info) == ETH_OK && budget > 0) {
+#else
+ while ((--max) && eth_port_receive(mp, &pkt_info) == ETH_OK) {
+#endif
+ mp->rx_ring_skbs--;
+ received_packets++;
+#ifdef MV64340_NAPI
+ budget--;
+#endif
+ /* Update statistics. Note byte count includes 4 byte CRC count */
+ stats->rx_packets++;
+ stats->rx_bytes += pkt_info.byte_cnt;
+ skb = (struct sk_buff *) pkt_info.return_info;
+ /*
+ * In case received a packet without first / last bits on OR
+ * the error summary bit is on, the packets needs to be dropeed.
+ */
+ if (((pkt_info.cmd_sts
+ & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+ (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+ || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+ stats->rx_dropped++;
+ if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
+ ETH_RX_LAST_DESC)) !=
+ (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
+ if (net_ratelimit())
+ printk(KERN_ERR
+ "%s: Received packet spread on multiple"
+ " descriptors\n",
+ dev->name);
+ }
+ if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
+ stats->rx_errors++;
+
+ dev_kfree_skb_irq(skb);
+ } else {
+ /*
+ * The -4 is for the CRC in the trailer of the
+ * received packet
+ */
+ skb_put(skb, pkt_info.byte_cnt - 4);
+ skb->dev = dev;
+
+ if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ skb->csum = htons((pkt_info.cmd_sts
+ & 0x0007fff8) >> 3);
+ }
+ skb->protocol = eth_type_trans(skb, dev);
+#ifdef MV64340_NAPI
+ netif_receive_skb(skb);
+#else
+ netif_rx(skb);
+#endif
+ }
+ }
+
+ return received_packets;
+}
+
+/*
+ * mv64340_eth_int_handler
+ *
+ * Main interrupt handler for the gigbit ethernet ports
+ *
+ * Input : irq - irq number (not used)
+ * dev_id - a pointer to the required interface's data structure
+ * regs - not used
+ * Output : N/A
+ */
+
+static irqreturn_t mv64340_eth_int_handler(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ struct net_device *dev = (struct net_device *) dev_id;
+ struct mv64340_private *mp = netdev_priv(dev);
+ u32 eth_int_cause, eth_int_cause_ext = 0;
+ unsigned int port_num = mp->port_num;
+
+ /* Read interrupt cause registers */
+ eth_int_cause = MV_READ(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num)) &
+ INT_CAUSE_UNMASK_ALL;
+
+ if (eth_int_cause & BIT1)
+ eth_int_cause_ext =
+ MV_READ(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
+ INT_CAUSE_UNMASK_ALL_EXT;
+
+#ifdef MV64340_NAPI
+ if (!(eth_int_cause & 0x0007fffd)) {
+ /* Dont ack the Rx interrupt */
+#endif
+ /*
+ * Clear specific ethernet port intrerrupt registers by
+ * acknowleding relevant bits.
+ */
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num),
+ ~eth_int_cause);
+ if (eth_int_cause_ext != 0x0)
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
+ ~eth_int_cause_ext);
+
+ /* UDP change : We may need this */
+ if ((eth_int_cause_ext & 0x0000ffff) &&
+ (mv64340_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
+ (MV64340_TX_QUEUE_SIZE > mp->tx_ring_skbs + 1))
+ netif_wake_queue(dev);
+#ifdef MV64340_NAPI
+ } else {
+ if (netif_rx_schedule_prep(dev)) {
+ /* Mask all the interrupts */
+ MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),0);
+ MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
+ __netif_rx_schedule(dev);
+ }
+#else
+ {
+ if (eth_int_cause & (BIT2 | BIT11))
+ mv64340_eth_receive_queue(dev, 0);
+
+ /*
+ * After forwarded received packets to upper layer, add a task
+ * in an interrupts enabled context that refills the RX ring
+ * with skb's.
+ */
+#if MV64340_RX_QUEUE_FILL_ON_TASK
+ /* Unmask all interrupts on ethernet port */
+ MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),
+ INT_CAUSE_MASK_ALL);
+ queue_task(&mp->rx_task, &tq_immediate);
+ mark_bh(IMMEDIATE_BH);
+#else
+ mp->rx_task.func(dev);
+#endif
+#endif
+ }
+ /* PHY status changed */
+ if (eth_int_cause_ext & (BIT16 | BIT20)) {
+ unsigned int phy_reg_data;
+
+ /* Check Link status on ethernet port */
+ eth_port_read_smi_reg(port_num, 1, &phy_reg_data);
+ if (!(phy_reg_data & 0x20)) {
+ netif_stop_queue(dev);
+ } else {
+ netif_wake_queue(dev);
+
+ /*
+ * Start all TX queues on ethernet port. This is good in
+ * case of previous packets where not transmitted, due
+ * to link down and this command re-enables all TX
+ * queues.
+ * Note that it is possible to get a TX resource error
+ * interrupt after issuing this, since not all TX queues
+ * are enabled, or has anything to send.
+ */
+ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 1);
+ }
+ }
+
+ /*
+ * If no real interrupt occured, exit.
+ * This can happen when using gigE interrupt coalescing mechanism.
+ */
+ if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+
+#ifdef MV64340_COAL
+
+/*
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ * This routine sets the RX coalescing interrupt mechanism parameter.
+ * This parameter is a timeout counter, that counts in 64 t_clk
+ * chunks ; that when timeout event occurs a maskable interrupt
+ * occurs.
+ * The parameter is calculated using the tClk of the MV-643xx chip
+ * , and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet port number
+ * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
+ * unsigned int delay Delay in usec
+ *
+ * OUTPUT:
+ * Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ * The interrupt coalescing value set in the gigE port.
+ *
+ */
+static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
+ unsigned int t_clk, unsigned int delay)
+{
+ unsigned int coal = ((t_clk / 1000000) * delay) / 64;
+
+ /* Set RX Coalescing mechanism */
+ MV_WRITE(MV64340_ETH_SDMA_CONFIG_REG(eth_port_num),
+ ((coal & 0x3fff) << 8) |
+ (MV_READ(MV64340_ETH_SDMA_CONFIG_REG(eth_port_num))
+ & 0xffc000ff));
+
+ return coal;
+}
+#endif
+
+/*
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ * This routine sets the TX coalescing interrupt mechanism parameter.
+ * This parameter is a timeout counter, that counts in 64 t_clk
+ * chunks ; that when timeout event occurs a maskable interrupt
+ * occurs.
+ * The parameter is calculated using the t_cLK frequency of the
+ * MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet port number
+ * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
+ * unsigned int delay Delay in uSeconds
+ *
+ * OUTPUT:
+ * Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ * The interrupt coalescing value set in the gigE port.
+ *
+ */
+static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
+ unsigned int t_clk, unsigned int delay)
+{
+ unsigned int coal;
+ coal = ((t_clk / 1000000) * delay) / 64;
+ /* Set TX Coalescing mechanism */
+ MV_WRITE(MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
+ coal << 4);
+ return coal;
+}
+
+/*
+ * mv64340_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ *
+ * Output : zero of success , nonzero if fails.
+ */
+
+static int mv64340_eth_open(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+ int err = err;
+
+ spin_lock_irq(&mp->lock);
+
+ err = request_irq(dev->irq, mv64340_eth_int_handler,
+ SA_INTERRUPT | SA_SAMPLE_RANDOM, dev->name, dev);
+
+ if (err) {
+ printk(KERN_ERR "Can not assign IRQ number to MV64340_eth%d\n",
+ port_num);
+ err = -EAGAIN;
+ goto out;
+ }
+
+ if (mv64340_eth_real_open(dev)) {
+ printk("%s: Error opening interface\n", dev->name);
+ err = -EBUSY;
+ goto out_free;
+ }
+
+ spin_unlock_irq(&mp->lock);
+
+ return 0;
+
+out_free:
+ free_irq(dev->irq, dev);
+
+out:
+ spin_unlock_irq(&mp->lock);
+
+ return err;
+}
+
+/*
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ * This function prepares a Rx chained list of descriptors and packet
+ * buffers in a form of a ring. The routine must be called after port
+ * initialization routine and before port start routine.
+ * The Ethernet SDMA engine uses CPU bus addresses to access the various
+ * devices in the system (i.e. DRAM). This function uses the ethernet
+ * struct 'virtual to physical' routine (set by the user) to set the ring
+ * with physical addresses.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet Port Control srtuct.
+ * int rx_desc_num Number of Rx descriptors
+ * int rx_buff_size Size of Rx buffer
+ * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
+ * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ * The routine updates the Ethernet port control struct with information
+ * regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ * false if the given descriptors memory area is not aligned according to
+ * Ethernet SDMA specifications.
+ * true otherwise.
+ */
+static int ether_init_rx_desc_ring(struct mv64340_private * mp,
+ unsigned long rx_buff_base_addr)
+{
+ unsigned long buffer_addr = rx_buff_base_addr;
+ volatile struct eth_rx_desc *p_rx_desc;
+ int rx_desc_num = mp->rx_ring_size;
+ unsigned long rx_desc_base_addr = (unsigned long) mp->p_rx_desc_area;
+ int rx_buff_size = 1536; /* Dummy, will be replaced later */
+ int i;
+
+ p_rx_desc = (struct eth_rx_desc *) rx_desc_base_addr;
+
+ /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+ if (rx_buff_base_addr & 0xf)
+ return 0;
+
+ /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
+ if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+ return 0;
+
+ /* Rx buffers must be 64-bit aligned. */
+ if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+ return 0;
+
+ /* initialize the Rx descriptors ring */
+ for (i = 0; i < rx_desc_num; i++) {
+ p_rx_desc[i].buf_size = rx_buff_size;
+ p_rx_desc[i].byte_cnt = 0x0000;
+ p_rx_desc[i].cmd_sts =
+ ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+ p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
+ ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
+ p_rx_desc[i].buf_ptr = buffer_addr;
+
+ mp->rx_skb[i] = NULL;
+ buffer_addr += rx_buff_size;
+ }
+
+ /* Save Rx desc pointer to driver struct. */
+ mp->rx_curr_desc_q = 0;
+ mp->rx_used_desc_q = 0;
+
+ mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
+
+ mp->port_rx_queue_command |= 1;
+
+ return 1;
+}
+
+/*
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ * This function prepares a Tx chained list of descriptors and packet
+ * buffers in a form of a ring. The routine must be called after port
+ * initialization routine and before port start routine.
+ * The Ethernet SDMA engine uses CPU bus addresses to access the various
+ * devices in the system (i.e. DRAM). This function uses the ethernet
+ * struct 'virtual to physical' routine (set by the user) to set the ring
+ * with physical addresses.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet Port Control srtuct.
+ * int tx_desc_num Number of Tx descriptors
+ * int tx_buff_size Size of Tx buffer
+ * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
+ *
+ * OUTPUT:
+ * The routine updates the Ethernet port control struct with information
+ * regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ * false if the given descriptors memory area is not aligned according to
+ * Ethernet SDMA specifications.
+ * true otherwise.
+ */
+static int ether_init_tx_desc_ring(struct mv64340_private *mp)
+{
+ unsigned long tx_desc_base_addr = (unsigned long) mp->p_tx_desc_area;
+ int tx_desc_num = mp->tx_ring_size;
+ struct eth_tx_desc *p_tx_desc;
+ int i;
+
+ /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+ if (tx_desc_base_addr & 0xf)
+ return 0;
+
+ /* save the first desc pointer to link with the last descriptor */
+ p_tx_desc = (struct eth_tx_desc *) tx_desc_base_addr;
+
+ /* Initialize the Tx descriptors ring */
+ for (i = 0; i < tx_desc_num; i++) {
+ p_tx_desc[i].byte_cnt = 0x0000;
+ p_tx_desc[i].l4i_chk = 0x0000;
+ p_tx_desc[i].cmd_sts = 0x00000000;
+ p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
+ ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
+ p_tx_desc[i].buf_ptr = 0x00000000;
+ mp->tx_skb[i] = NULL;
+ }
+
+ /* Set Tx desc pointer in driver struct. */
+ mp->tx_curr_desc_q = 0;
+ mp->tx_used_desc_q = 0;
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ mp->tx_first_desc_q = 0;
+#endif
+ /* Init Tx ring base and size parameters */
+ mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
+
+ /* Add the queue to the list of Tx queues of this port */
+ mp->port_tx_queue_command |= 1;
+
+ return 1;
+}
+
+/* Helper function for mv64340_eth_open */
+static int mv64340_eth_real_open(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+ u32 phy_reg_data;
+ unsigned int size;
+
+ /* Stop RX Queues */
+ MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
+ 0x0000ff00);
+
+ /* Clear the ethernet port interrupts */
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
+
+ /* Unmask RX buffer and TX end interrupt */
+ MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),
+ INT_CAUSE_UNMASK_ALL);
+
+ /* Unmask phy and link status changes interrupts */
+ MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
+ INT_CAUSE_UNMASK_ALL_EXT);
+
+ /* Set the MAC Address */
+ memcpy(mp->port_mac_addr, dev->dev_addr, 6);
+
+ eth_port_init(mp);
+
+ INIT_WORK(&mp->rx_task, (void (*)(void *)) mv64340_eth_rx_task, dev);
+
+ memset(&mp->timeout, 0, sizeof(struct timer_list));
+ mp->timeout.function = mv64340_eth_rx_task_timer_wrapper;
+ mp->timeout.data = (unsigned long) dev;
+
+ mp->rx_task_busy = 0;
+ mp->rx_timer_flag = 0;
+
+ /* Allocate TX ring */
+ mp->tx_ring_skbs = 0;
+ mp->tx_ring_size = MV64340_TX_QUEUE_SIZE;
+ size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
+ mp->tx_desc_area_size = size;
+
+ /* Assumes allocated ring is 16 bytes alligned */
+ mp->p_tx_desc_area = pci_alloc_consistent(NULL, size, &mp->tx_desc_dma);
+ if (!mp->p_tx_desc_area) {
+ printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
+ dev->name, size);
+ return -ENOMEM;
+ }
+ memset((void *) mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
+
+ /* Dummy will be replaced upon real tx */
+ ether_init_tx_desc_ring(mp);
+
+ /* Allocate RX ring */
+ /* Meantime RX Ring are fixed - but must be configurable by user */
+ mp->rx_ring_size = MV64340_RX_QUEUE_SIZE;
+ mp->rx_ring_skbs = 0;
+ size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
+ mp->rx_desc_area_size = size;
+
+ /* Assumes allocated ring is 16 bytes aligned */
+
+ mp->p_rx_desc_area = pci_alloc_consistent(NULL, size, &mp->rx_desc_dma);
+
+ if (!mp->p_rx_desc_area) {
+ printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
+ dev->name, size);
+ printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
+ dev->name);
+ pci_free_consistent(0, mp->tx_desc_area_size,
+ (void *) mp->p_tx_desc_area,
+ mp->tx_desc_dma);
+ return -ENOMEM;
+ }
+ memset(mp->p_rx_desc_area, 0, size);
+
+ if (!(ether_init_rx_desc_ring(mp, 0)))
+ panic("%s: Error initializing RX Ring", dev->name);
+
+ mv64340_eth_rx_task(dev); /* Fill RX ring with skb's */
+
+ eth_port_start(mp);
+
+ /* Interrupt Coalescing */
+
+#ifdef MV64340_COAL
+ mp->rx_int_coal =
+ eth_port_set_rx_coal(port_num, 133000000, MV64340_RX_COAL);
+#endif
+
+ mp->tx_int_coal =
+ eth_port_set_tx_coal (port_num, 133000000, MV64340_TX_COAL);
+
+ /* Increase the Rx side buffer size */
+
+ MV_WRITE (MV64340_ETH_PORT_SERIAL_CONTROL_REG(port_num), (0x5 << 17) |
+ (MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(port_num))
+ & 0xfff1ffff));
+
+ /* Check Link status on phy */
+ eth_port_read_smi_reg(port_num, 1, &phy_reg_data);
+ if (!(phy_reg_data & 0x20))
+ netif_stop_queue(dev);
+ else
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+static void mv64340_eth_free_tx_rings(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+ unsigned int curr;
+
+ /* Stop Tx Queues */
+ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
+ 0x0000ff00);
+
+ /* Free TX rings */
+ /* Free outstanding skb's on TX rings */
+ for (curr = 0;
+ (mp->tx_ring_skbs) && (curr < MV64340_TX_QUEUE_SIZE);
+ curr++) {
+ if (mp->tx_skb[curr]) {
+ dev_kfree_skb(mp->tx_skb[curr]);
+ mp->tx_ring_skbs--;
+ }
+ }
+ if (mp->tx_ring_skbs != 0)
+ printk("%s: Error on Tx descriptor free - could not free %d"
+ " descriptors\n", dev->name,
+ mp->tx_ring_skbs);
+ pci_free_consistent(0, mp->tx_desc_area_size,
+ (void *) mp->p_tx_desc_area, mp->tx_desc_dma);
+}
+
+static void mv64340_eth_free_rx_rings(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+ int curr;
+
+ /* Stop RX Queues */
+ MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
+ 0x0000ff00);
+
+ /* Free RX rings */
+ /* Free preallocated skb's on RX rings */
+ for (curr = 0;
+ mp->rx_ring_skbs && (curr < MV64340_RX_QUEUE_SIZE);
+ curr++) {
+ if (mp->rx_skb[curr]) {
+ dev_kfree_skb(mp->rx_skb[curr]);
+ mp->rx_ring_skbs--;
+ }
+ }
+
+ if (mp->rx_ring_skbs != 0)
+ printk(KERN_ERR
+ "%s: Error in freeing Rx Ring. %d skb's still"
+ " stuck in RX Ring - ignoring them\n", dev->name,
+ mp->rx_ring_skbs);
+ pci_free_consistent(0, mp->rx_desc_area_size,
+ (void *) mp->p_rx_desc_area,
+ mp->rx_desc_dma);
+}
+
+/*
+ * mv64340_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ */
+
+/* Helper function for mv64340_eth_stop */
+
+static int mv64340_eth_real_stop(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+
+ netif_stop_queue(dev);
+
+ mv64340_eth_free_tx_rings(dev);
+ mv64340_eth_free_rx_rings(dev);
+
+ eth_port_reset(mp->port_num);
+
+ /* Disable ethernet port interrupts */
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
+
+ /* Mask RX buffer and TX end interrupt */
+ MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num), 0);
+
+ /* Mask phy and link status changes interrupts */
+ MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
+
+ return 0;
+}
+
+static int mv64340_eth_stop(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ spin_lock_irq(&mp->lock);
+
+ mv64340_eth_real_stop(dev);
+
+ free_irq(dev->irq, dev);
+ spin_unlock_irq(&mp->lock);
+
+ return 0;
+}
+
+#ifdef MV64340_NAPI
+static void mv64340_tx(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ struct pkt_info pkt_info;
+
+ while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
+ if (pkt_info.return_info) {
+ dev_kfree_skb_irq((struct sk_buff *)
+ pkt_info.return_info);
+ if (skb_shinfo(pkt_info.return_info)->nr_frags)
+ pci_unmap_page(NULL, pkt_info.buf_ptr,
+ pkt_info.byte_cnt,
+ PCI_DMA_TODEVICE);
+
+ if (mp->tx_ring_skbs != 1)
+ mp->tx_ring_skbs--;
+ } else
+ pci_unmap_page(NULL, pkt_info.buf_ptr, pkt_info.byte_cnt,
+ PCI_DMA_TODEVICE);
+ }
+
+ if (netif_queue_stopped(dev) &&
+ MV64340_TX_QUEUE_SIZE > mp->tx_ring_skbs + 1)
+ netif_wake_queue(dev);
+}
+
+/*
+ * mv64340_poll
+ *
+ * This function is used in case of NAPI
+ */
+static int mv64340_poll(struct net_device *dev, int *budget)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ int done = 1, orig_budget, work_done;
+ unsigned int port_num = mp->port_num;
+ unsigned long flags;
+
+#ifdef MV64340_TX_FAST_REFILL
+ if (++mp->tx_clean_threshold > 5) {
+ spin_lock_irqsave(&mp->lock, flags);
+ mv64340_tx(dev);
+ mp->tx_clean_threshold = 0;
+ spin_unlock_irqrestore(&mp->lock, flags);
+ }
+#endif
+
+ if ((u32)(MV_READ(MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) != (u32)mp->rx_used_desc_q) {
+ orig_budget = *budget;
+ if (orig_budget > dev->quota)
+ orig_budget = dev->quota;
+ work_done = mv64340_eth_receive_queue(dev, 0, orig_budget);
+ mp->rx_task.func(dev);
+ *budget -= work_done;
+ dev->quota -= work_done;
+ if (work_done >= orig_budget)
+ done = 0;
+ }
+
+ if (done) {
+ spin_lock_irqsave(&mp->lock, flags);
+ __netif_rx_complete(dev);
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num),0);
+ MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),0);
+ MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),
+ INT_CAUSE_UNMASK_ALL);
+ MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
+ INT_CAUSE_UNMASK_ALL_EXT);
+ spin_unlock_irqrestore(&mp->lock, flags);
+ }
+
+ return done ? 0 : 1;
+}
+#endif
+
+/*
+ * mv64340_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ * dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ */
+static int mv64340_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &mp->stats;
+ ETH_FUNC_RET_STATUS status;
+ unsigned long flags;
+ struct pkt_info pkt_info;
+
+ if (netif_queue_stopped(dev)) {
+ printk(KERN_ERR
+ "%s: Tried sending packet when interface is stopped\n",
+ dev->name);
+ return 1;
+ }
+
+ /* This is a hard error, log it. */
+ if ((MV64340_TX_QUEUE_SIZE - mp->tx_ring_skbs) <=
+ (skb_shinfo(skb)->nr_frags + 1)) {
+ netif_stop_queue(dev);
+ printk(KERN_ERR
+ "%s: Bug in mv64340_eth - Trying to transmit when"
+ " queue full !\n", dev->name);
+ return 1;
+ }
+
+ /* Paranoid check - this shouldn't happen */
+ if (skb == NULL) {
+ stats->tx_dropped++;
+ return 1;
+ }
+
+ spin_lock_irqsave(&mp->lock, flags);
+
+ /* Update packet info data structure -- DMA owned, first last */
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ if (!skb_shinfo(skb)->nr_frags || (skb_shinfo(skb)->nr_frags > 3)) {
+#endif
+ pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
+ ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;
+
+ pkt_info.byte_cnt = skb->len;
+ pkt_info.buf_ptr = pci_map_single(0, skb->data, skb->len,
+ PCI_DMA_TODEVICE);
+
+
+ pkt_info.return_info = skb;
+ status = eth_port_send(mp, &pkt_info);
+ if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
+ printk(KERN_ERR "%s: Error on transmitting packet\n",
+ dev->name);
+ mp->tx_ring_skbs++;
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ } else {
+ unsigned int frag;
+ u32 ipheader;
+
+ /* first frag which is skb header */
+ pkt_info.byte_cnt = skb_headlen(skb);
+ pkt_info.buf_ptr = pci_map_single(0, skb->data,
+ skb_headlen(skb), PCI_DMA_TODEVICE);
+ pkt_info.return_info = 0;
+ ipheader = skb->nh.iph->ihl << 11;
+ pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
+ ETH_GEN_TCP_UDP_CHECKSUM |
+ ETH_GEN_IP_V_4_CHECKSUM |
+ ipheader;
+ /* CPU already calculated pseudo header checksum. So, use it */
+ pkt_info.l4i_chk = skb->h.th->check;
+ status = eth_port_send(mp, &pkt_info);
+ if (status != ETH_OK) {
+ if ((status == ETH_ERROR))
+ printk(KERN_ERR "%s: Error on transmitting packet\n", dev->name);
+ if (status == ETH_QUEUE_FULL)
+ printk("Error on Queue Full \n");
+ if (status == ETH_QUEUE_LAST_RESOURCE)
+ printk("Tx resource error \n");
+ }
+
+ /* Check for the remaining frags */
+ for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
+ skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
+ pkt_info.l4i_chk = 0x0000;
+ pkt_info.cmd_sts = 0x00000000;
+
+ /* Last Frag enables interrupt and frees the skb */
+ if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
+ pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
+ ETH_TX_LAST_DESC;
+ pkt_info.return_info = skb;
+ mp->tx_ring_skbs++;
+ }
+ else {
+ pkt_info.return_info = 0;
+ }
+ pkt_info.byte_cnt = this_frag->size;
+ if (this_frag->size < 8)
+ printk("%d : \n", skb_shinfo(skb)->nr_frags);
+
+ pkt_info.buf_ptr = pci_map_page(NULL, this_frag->page,
+ this_frag->page_offset,
+ this_frag->size, PCI_DMA_TODEVICE);
+
+ status = eth_port_send(mp, &pkt_info);
+
+ if (status != ETH_OK) {
+ if ((status == ETH_ERROR))
+ printk(KERN_ERR "%s: Error on transmitting packet\n", dev->name);
+
+ if (status == ETH_QUEUE_LAST_RESOURCE)
+ printk("Tx resource error \n");
+
+ if (status == ETH_QUEUE_FULL)
+ printk("Queue is full \n");
+ }
+ }
+ }
+#endif
+
+ /* Check if TX queue can handle another skb. If not, then
+ * signal higher layers to stop requesting TX
+ */
+ if (MV64340_TX_QUEUE_SIZE <= (mp->tx_ring_skbs + 1))
+ /*
+ * Stop getting skb's from upper layers.
+ * Getting skb's from upper layers will be enabled again after
+ * packets are released.
+ */
+ netif_stop_queue(dev);
+
+ /* Update statistics and start of transmittion time */
+ stats->tx_bytes += skb->len;
+ stats->tx_packets++;
+ dev->trans_start = jiffies;
+
+ spin_unlock_irqrestore(&mp->lock, flags);
+
+ return 0; /* success */
+}
+
+/*
+ * mv64340_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ */
+
+static struct net_device_stats *mv64340_eth_get_stats(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ return &mp->stats;
+}
+
+/*/
+ * mv64340_eth_init
+ *
+ * First function called after registering the network device.
+ * It's purpose is to initialize the device as an ethernet device,
+ * fill the structure that was given in registration with pointers
+ * to functions, and setting the MAC address of the interface
+ *
+ * Input : number of port to initialize
+ * Output : -ENONMEM if failed , 0 if success
+ */
+static struct net_device *mv64340_eth_init(int port_num)
+{
+ struct mv64340_private *mp;
+ struct net_device *dev;
+ int err;
+
+ dev = alloc_etherdev(sizeof(struct mv64340_private));
+ if (!dev)
+ return NULL;
+
+ mp = netdev_priv(dev);
+
+ dev->irq = ETH_PORT0_IRQ_NUM + port_num;
+
+ dev->open = mv64340_eth_open;
+ dev->stop = mv64340_eth_stop;
+ dev->hard_start_xmit = mv64340_eth_start_xmit;
+ dev->get_stats = mv64340_eth_get_stats;
+ dev->set_mac_address = mv64340_eth_set_mac_address;
+ dev->set_multicast_list = mv64340_eth_set_rx_mode;
+
+ /* No need to Tx Timeout */
+ dev->tx_timeout = mv64340_eth_tx_timeout;
+#ifdef MV64340_NAPI
+ dev->poll = mv64340_poll;
+ dev->weight = 64;
+#endif
+
+ dev->watchdog_timeo = 2 * HZ;
+ dev->tx_queue_len = MV64340_TX_QUEUE_SIZE;
+ dev->base_addr = 0;
+ dev->change_mtu = mv64340_eth_change_mtu;
+
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+#ifdef MAX_SKB_FRAGS
+#ifndef CONFIG_JAGUAR_DMALOW
+ /*
+ * Zero copy can only work if we use Discovery II memory. Else, we will
+ * have to map the buffers to ISA memory which is only 16 MB
+ */
+ dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
+#endif
+#endif
+#endif
+
+ mp->port_num = port_num;
+
+ /* Configure the timeout task */
+ INIT_WORK(&mp->tx_timeout_task,
+ (void (*)(void *))mv64340_eth_tx_timeout_task, dev);
+
+ spin_lock_init(&mp->lock);
+
+ /* set MAC addresses */
+ memcpy(dev->dev_addr, prom_mac_addr_base, 6);
+ dev->dev_addr[5] += port_num;
+
+ err = register_netdev(dev);
+ if (err)
+ goto out_free_dev;
+
+ printk(KERN_NOTICE "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->name, port_num,
+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
+
+ if (dev->features & NETIF_F_SG)
+ printk("Scatter Gather Enabled ");
+
+ if (dev->features & NETIF_F_IP_CSUM)
+ printk("TX TCP/IP Checksumming Supported \n");
+
+ printk("RX TCP/UDP Checksum Offload ON, \n");
+ printk("TX and RX Interrupt Coalescing ON \n");
+
+#ifdef MV64340_NAPI
+ printk("RX NAPI Enabled \n");
+#endif
+
+ return dev;
+
+out_free_dev:
+ free_netdev(dev);
+
+ return NULL;
+}
+
+static void mv64340_eth_remove(struct net_device *dev)
+{
+ struct mv64340_private *mp = netdev_priv(dev);
+
+ unregister_netdev(dev);
+ flush_scheduled_work();
+ free_netdev(dev);
+}
+
+static struct net_device *mv64340_dev0;
+static struct net_device *mv64340_dev1;
+static struct net_device *mv64340_dev2;
+
+/*
+ * mv64340_init_module
+ *
+ * Registers the network drivers into the Linux kernel
+ *
+ * Input : N/A
+ *
+ * Output : N/A
+ */
+static int __init mv64340_init_module(void)
+{
+ printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
+
+#ifdef CONFIG_MV643XX_ETH_0
+ mv64340_dev0 = mv64340_eth_init(0);
+ if (!mv64340_dev0) {
+ printk(KERN_ERR
+ "Error registering MV-64360 ethernet port 0\n");
+ }
+#endif
+#ifdef CONFIG_MV643XX_ETH_1
+ mv64340_dev1 = mv64340_eth_init(1);
+ if (!mv64340_dev1) {
+ printk(KERN_ERR
+ "Error registering MV-64360 ethernet port 1\n");
+ }
+#endif
+#ifdef CONFIG_MV643XX_ETH_2
+ mv64340_dev2 = mv64340_eth_init(2);
+ if (!mv64340_dev2) {
+ printk(KERN_ERR
+ "Error registering MV-64360 ethernet port 2\n");
+ }
+#endif
+ return 0;
+}
+
+/*
+ * mv64340_cleanup_module
+ *
+ * Registers the network drivers into the Linux kernel
+ *
+ * Input : N/A
+ *
+ * Output : N/A
+ */
+static void __exit mv64340_cleanup_module(void)
+{
+ if (mv64340_dev2)
+ mv64340_eth_remove(mv64340_dev2);
+ if (mv64340_dev1)
+ mv64340_eth_remove(mv64340_dev1);
+ if (mv64340_dev0)
+ mv64340_eth_remove(mv64340_dev0);
+}
+
+module_init(mv64340_init_module);
+module_exit(mv64340_cleanup_module);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm and Manish Lachwani");
+MODULE_DESCRIPTION("Ethernet driver for Marvell MV64340");
+
+/*
+ * The second part is the low level driver of the gigE ethernet ports.
+ */
+
+/*
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ * This file introduce low level API to Marvell's Gigabit Ethernet
+ * controller. This Gigabit Ethernet Controller driver API controls
+ * 1) Operations (i.e. port init, start, reset etc').
+ * 2) Data flow (i.e. port send, receive etc').
+ * Each Gigabit Ethernet port is controlled via
+ * struct mv64340_private.
+ * This struct includes user configuration information as well as
+ * driver internal data needed for its operations.
+ *
+ * Supported Features:
+ * - This low level driver is OS independent. Allocating memory for
+ * the descriptor rings and buffers are not within the scope of
+ * this driver.
+ * - The user is free from Rx/Tx queue managing.
+ * - This low level driver introduce functionality API that enable
+ * the to operate Marvell's Gigabit Ethernet Controller in a
+ * convenient way.
+ * - Simple Gigabit Ethernet port operation API.
+ * - Simple Gigabit Ethernet port data flow API.
+ * - Data flow and operation API support per queue functionality.
+ * - Support cached descriptors for better performance.
+ * - Enable access to all four DRAM banks and internal SRAM memory
+ * spaces.
+ * - PHY access and control API.
+ * - Port control register configuration API.
+ * - Full control over Unicast and Multicast MAC configurations.
+ *
+ * Operation flow:
+ *
+ * Initialization phase
+ * This phase complete the initialization of the the mv64340_private
+ * struct.
+ * User information regarding port configuration has to be set
+ * prior to calling the port initialization routine.
+ *
+ * In this phase any port Tx/Rx activity is halted, MIB counters
+ * are cleared, PHY address is set according to user parameter and
+ * access to DRAM and internal SRAM memory spaces.
+ *
+ * Driver ring initialization
+ * Allocating memory for the descriptor rings and buffers is not
+ * within the scope of this driver. Thus, the user is required to
+ * allocate memory for the descriptors ring and buffers. Those
+ * memory parameters are used by the Rx and Tx ring initialization
+ * routines in order to curve the descriptor linked list in a form
+ * of a ring.
+ * Note: Pay special attention to alignment issues when using
+ * cached descriptors/buffers. In this phase the driver store
+ * information in the mv64340_private struct regarding each queue
+ * ring.
+ *
+ * Driver start
+ * This phase prepares the Ethernet port for Rx and Tx activity.
+ * It uses the information stored in the mv64340_private struct to
+ * initialize the various port registers.
+ *
+ * Data flow:
+ * All packet references to/from the driver are done using
+ * struct pkt_info.
+ * This struct is a unified struct used with Rx and Tx operations.
+ * This way the user is not required to be familiar with neither
+ * Tx nor Rx descriptors structures.
+ * The driver's descriptors rings are management by indexes.
+ * Those indexes controls the ring resources and used to indicate
+ * a SW resource error:
+ * 'current'
+ * This index points to the current available resource for use. For
+ * example in Rx process this index will point to the descriptor
+ * that will be passed to the user upon calling the receive routine.
+ * In Tx process, this index will point to the descriptor
+ * that will be assigned with the user packet info and transmitted.
+ * 'used'
+ * This index points to the descriptor that need to restore its
+ * resources. For example in Rx process, using the Rx buffer return
+ * API will attach the buffer returned in packet info to the
+ * descriptor pointed by 'used'. In Tx process, using the Tx
+ * descriptor return will merely return the user packet info with
+ * the command status of the transmitted buffer pointed by the
+ * 'used' index. Nevertheless, it is essential to use this routine
+ * to update the 'used' index.
+ * 'first'
+ * This index supports Tx Scatter-Gather. It points to the first
+ * descriptor of a packet assembled of multiple buffers. For example
+ * when in middle of Such packet we have a Tx resource error the
+ * 'curr' index get the value of 'first' to indicate that the ring
+ * returned to its state before trying to transmit this packet.
+ *
+ * Receive operation:
+ * The eth_port_receive API set the packet information struct,
+ * passed by the caller, with received information from the
+ * 'current' SDMA descriptor.
+ * It is the user responsibility to return this resource back
+ * to the Rx descriptor ring to enable the reuse of this source.
+ * Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ * Transmit operation:
+ * The eth_port_send API supports Scatter-Gather which enables to
+ * send a packet spanned over multiple buffers. This means that
+ * for each packet info structure given by the user and put into
+ * the Tx descriptors ring, will be transmitted only if the 'LAST'
+ * bit will be set in the packet info command status field. This
+ * API also consider restriction regarding buffer alignments and
+ * sizes.
+ * The user must return a Tx resource after ensuring the buffer
+ * has been transmitted to enable the Tx ring indexes to update.
+ *
+ * BOARD LAYOUT
+ * This device is on-board. No jumper diagram is necessary.
+ *
+ * EXTERNAL INTERFACE
+ *
+ * Prior to calling the initialization routine eth_port_init() the user
+ * must set the following fields under mv64340_private struct:
+ * port_num User Ethernet port number.
+ * port_mac_addr[6] User defined port MAC address.
+ * port_config User port configuration value.
+ * port_config_extend User port config extend value.
+ * port_sdma_config User port SDMA config value.
+ * port_serial_control User port serial control value.
+ *
+ * This driver introduce a set of default values:
+ * PORT_CONFIG_VALUE Default port configuration value
+ * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
+ * PORT_SDMA_CONFIG_VALUE Default sdma control value
+ * PORT_SERIAL_CONTROL_VALUE Default port serial control value
+ *
+ * This driver data flow is done using the struct pkt_info which
+ * is a unified struct for Rx and Tx operations:
+ *
+ * byte_cnt Tx/Rx descriptor buffer byte count.
+ * l4i_chk CPU provided TCP Checksum. For Tx operation
+ * only.
+ * cmd_sts Tx/Rx descriptor command status.
+ * buf_ptr Tx/Rx descriptor buffer pointer.
+ * return_info Tx/Rx user resource return information.
+ */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(eth_port) \
+ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
+
+#define ETH_DISABLE_TX_QUEUE(eth_port) \
+ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), \
+ (1 << 8))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+ MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), \
+ (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+ MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), \
+ (1 << (8 + rx_queue)))
+
+#define LINK_UP_TIMEOUT 100000
+#define PHY_BUSY_TIMEOUT 10000000
+
+/* locals */
+
+/* PHY routines */
+static int ethernet_phy_get(unsigned int eth_port_num);
+
+/* Ethernet Port routines */
+static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
+ int option);
+
+/*
+ * eth_port_init - Initialize the Ethernet port driver
+ *
+ * DESCRIPTION:
+ * This function prepares the ethernet port to start its activity:
+ * 1) Completes the ethernet port driver struct initialization toward port
+ * start routine.
+ * 2) Resets the device to a quiescent state in case of warm reboot.
+ * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+ * 4) Clean MAC tables. The reset status of those tables is unknown.
+ * 5) Set PHY address.
+ * Note: Call this routine prior to eth_port_start routine and after
+ * setting user values in the user fields of Ethernet port control
+ * struct.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet port control struct
+ *
+ * OUTPUT:
+ * See description.
+ *
+ * RETURN:
+ * None.
+ */
+static void eth_port_init(struct mv64340_private * mp)
+{
+ mp->port_config = PORT_CONFIG_VALUE;
+ mp->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+#if defined(__BIG_ENDIAN)
+ mp->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+#elif defined(__LITTLE_ENDIAN)
+ mp->port_sdma_config = PORT_SDMA_CONFIG_VALUE |
+ ETH_BLM_RX_NO_SWAP | ETH_BLM_TX_NO_SWAP;
+#else
+#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be defined!
+#endif
+ mp->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+ mp->port_rx_queue_command = 0;
+ mp->port_tx_queue_command = 0;
+
+ mp->rx_resource_err = 0;
+ mp->tx_resource_err = 0;
+
+ eth_port_reset(mp->port_num);
+
+ eth_port_init_mac_tables(mp->port_num);
+
+ ethernet_phy_reset(mp->port_num);
+}
+
+/*
+ * eth_port_start - Start the Ethernet port activity.
+ *
+ * DESCRIPTION:
+ * This routine prepares the Ethernet port for Rx and Tx activity:
+ * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+ * has been initialized a descriptor's ring (using
+ * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
+ * 2. Initialize and enable the Ethernet configuration port by writing to
+ * the port's configuration and command registers.
+ * 3. Initialize and enable the SDMA by writing to the SDMA's
+ * configuration and command registers. After completing these steps,
+ * the ethernet port SDMA can starts to perform Rx and Tx activities.
+ *
+ * Note: Each Rx and Tx queue descriptor's list must be initialized prior
+ * to calling this function (use ether_init_tx_desc_ring for Tx queues
+ * and ether_init_rx_desc_ring for Rx queues).
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet port control struct
+ *
+ * OUTPUT:
+ * Ethernet port is ready to receive and transmit.
+ *
+ * RETURN:
+ * false if the port PHY is not up.
+ * true otherwise.
+ */
+static int eth_port_start(struct mv64340_private *mp)
+{
+ unsigned int eth_port_num = mp->port_num;
+ int tx_curr_desc, rx_curr_desc;
+ unsigned int phy_reg_data;
+
+ /* Assignment of Tx CTRP of given queue */
+ tx_curr_desc = mp->tx_curr_desc_q;
+ MV_WRITE(MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(eth_port_num),
+ (struct eth_tx_desc *) mp->tx_desc_dma + tx_curr_desc);
+
+ /* Assignment of Rx CRDP of given queue */
+ rx_curr_desc = mp->rx_curr_desc_q;
+ MV_WRITE(MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(eth_port_num),
+ (struct eth_rx_desc *) mp->rx_desc_dma + rx_curr_desc);
+
+ /* Add the assigned Ethernet address to the port's address table */
+ eth_port_uc_addr_set(mp->port_num, mp->port_mac_addr);
+
+ /* Assign port configuration and command. */
+ MV_WRITE(MV64340_ETH_PORT_CONFIG_REG(eth_port_num),
+ mp->port_config);
+
+ MV_WRITE(MV64340_ETH_PORT_CONFIG_EXTEND_REG(eth_port_num),
+ mp->port_config_extend);
+
+ MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(eth_port_num),
+ mp->port_serial_control);
+
+ MV_SET_REG_BITS(MV64340_ETH_PORT_SERIAL_CONTROL_REG(eth_port_num),
+ ETH_SERIAL_PORT_ENABLE);
+
+ /* Assign port SDMA configuration */
+ MV_WRITE(MV64340_ETH_SDMA_CONFIG_REG(eth_port_num),
+ mp->port_sdma_config);
+
+ /* Enable port Rx. */
+ MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port_num),
+ mp->port_rx_queue_command);
+
+ /* Check if link is up */
+ eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data);
+
+ if (!(phy_reg_data & 0x20))
+ return 0;
+
+ return 1;
+}
+
+/*
+ * eth_port_uc_addr_set - This function Set the port Unicast address.
+ *
+ * DESCRIPTION:
+ * This function Set the port Ethernet MAC address.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Port number.
+ * char * p_addr Address to be set
+ *
+ * OUTPUT:
+ * Set MAC address low and high registers. also calls eth_port_uc_addr()
+ * To set the unicast table with the proper information.
+ *
+ * RETURN:
+ * N/A.
+ *
+ */
+static void eth_port_uc_addr_set(unsigned int eth_port_num,
+ unsigned char *p_addr)
+{
+ unsigned int mac_h;
+ unsigned int mac_l;
+
+ mac_l = (p_addr[4] << 8) | (p_addr[5]);
+ mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+ (p_addr[2] << 8) | (p_addr[3] << 0);
+
+ MV_WRITE(MV64340_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
+ MV_WRITE(MV64340_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
+
+ /* Accept frames of this address */
+ eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
+
+ return;
+}
+
+/*
+ * eth_port_uc_addr - This function Set the port unicast address table
+ *
+ * DESCRIPTION:
+ * This function locates the proper entry in the Unicast table for the
+ * specified MAC nibble and sets its properties according to function
+ * parameters.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Port number.
+ * unsigned char uc_nibble Unicast MAC Address last nibble.
+ * int option 0 = Add, 1 = remove address.
+ *
+ * OUTPUT:
+ * This function add/removes MAC addresses from the port unicast address
+ * table.
+ *
+ * RETURN:
+ * true is output succeeded.
+ * false if option parameter is invalid.
+ *
+ */
+static int eth_port_uc_addr(unsigned int eth_port_num,
+ unsigned char uc_nibble, int option)
+{
+ unsigned int unicast_reg;
+ unsigned int tbl_offset;
+ unsigned int reg_offset;
+
+ /* Locate the Unicast table entry */
+ uc_nibble = (0xf & uc_nibble);
+ tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
+ reg_offset = uc_nibble % 4; /* Entry offset within the above register */
+
+ switch (option) {
+ case REJECT_MAC_ADDR:
+ /* Clear accepts frame bit at specified unicast DA table entry */
+ unicast_reg = MV_READ((MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+ (eth_port_num) + tbl_offset));
+
+ unicast_reg &= (0x0E << (8 * reg_offset));
+
+ MV_WRITE(
+ (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+ (eth_port_num) + tbl_offset), unicast_reg);
+ break;
+
+ case ACCEPT_MAC_ADDR:
+ /* Set accepts frame bit at unicast DA filter table entry */
+ unicast_reg =
+ MV_READ(
+ (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+ (eth_port_num) + tbl_offset));
+
+ unicast_reg |= (0x01 << (8 * reg_offset));
+
+ MV_WRITE(
+ (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+ (eth_port_num) + tbl_offset), unicast_reg);
+
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+ *
+ * DESCRIPTION:
+ * Go through all the DA filter tables (Unicast, Special Multicast &
+ * Other Multicast) and set each entry to 0.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+ * Multicast and Unicast packets are rejected.
+ *
+ * RETURN:
+ * None.
+ */
+static void eth_port_init_mac_tables(unsigned int eth_port_num)
+{
+ int table_index;
+
+ /* Clear DA filter unicast table (Ex_dFUT) */
+ for (table_index = 0; table_index <= 0xC; table_index += 4)
+ MV_WRITE(
+ (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+ (eth_port_num) + table_index), 0);
+
+ for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+ /* Clear DA filter special multicast table (Ex_dFSMT) */
+ MV_WRITE(
+ (MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
+ (eth_port_num) + table_index), 0);
+ /* Clear DA filter other multicast table (Ex_dFOMT) */
+ MV_WRITE((MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
+ (eth_port_num) + table_index), 0);
+ }
+}
+
+/*
+ * eth_clear_mib_counters - Clear all MIB counters
+ *
+ * DESCRIPTION:
+ * This function clears all MIB counters of a specific ethernet port.
+ * A read from the MIB counter will reset the counter.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+ * After reading all MIB counters, the counters resets.
+ *
+ * RETURN:
+ * MIB counter value.
+ *
+ */
+static void eth_clear_mib_counters(unsigned int eth_port_num)
+{
+ int i;
+
+ /* Perform dummy reads from MIB counters */
+ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4)
+ MV_READ(MV64340_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
+}
+
+
+/*
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ * This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * PHY address.
+ *
+ */
+static int ethernet_phy_get(unsigned int eth_port_num)
+{
+ unsigned int reg_data;
+
+ reg_data = MV_READ(MV64340_ETH_PHY_ADDR_REG);
+
+ return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ * This routine utilize the SMI interface to reset the ethernet port PHY.
+ * The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+ * The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ * None.
+ *
+ */
+static int ethernet_phy_reset(unsigned int eth_port_num)
+{
+ unsigned int time_out = 50;
+ unsigned int phy_reg_data;
+
+ /* Reset the PHY */
+ eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
+ phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
+ eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
+
+ /* Poll on the PHY LINK */
+ do {
+ eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data);
+
+ if (time_out-- == 0)
+ return 0;
+ } while (!(phy_reg_data & 0x20));
+
+ return 1;
+}
+
+/*
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ * This routine resets the chip by aborting any SDMA engine activity and
+ * clearing the MIB counters. The Receiver and the Transmit unit are in
+ * idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+ * Channel activity is halted.
+ *
+ * RETURN:
+ * None.
+ *
+ */
+static void eth_port_reset(unsigned int eth_port_num)
+{
+ unsigned int reg_data;
+
+ /* Stop Tx port activity. Check port Tx activity. */
+ reg_data =
+ MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port_num));
+
+ if (reg_data & 0xFF) {
+ /* Issue stop command for active channels only */
+ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG
+ (eth_port_num), (reg_data << 8));
+
+ /* Wait for all Tx activity to terminate. */
+ do {
+ /* Check port cause register that all Tx queues are stopped */
+ reg_data =
+ MV_READ
+ (MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG
+ (eth_port_num));
+ }
+ while (reg_data & 0xFF);
+ }
+
+ /* Stop Rx port activity. Check port Rx activity. */
+ reg_data =
+ MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG
+ (eth_port_num));
+
+ if (reg_data & 0xFF) {
+ /* Issue stop command for active channels only */
+ MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG
+ (eth_port_num), (reg_data << 8));
+
+ /* Wait for all Rx activity to terminate. */
+ do {
+ /* Check port cause register that all Rx queues are stopped */
+ reg_data =
+ MV_READ
+ (MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG
+ (eth_port_num));
+ }
+ while (reg_data & 0xFF);
+ }
+
+
+ /* Clear all MIB counters */
+ eth_clear_mib_counters(eth_port_num);
+
+ /* Reset the Enable bit in the Configuration Register */
+ reg_data =
+ MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num));
+ reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+ MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(eth_port_num), reg_data);
+
+ return;
+}
+
+/*
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ * This function sets specified bits in the given ethernet
+ * configuration register.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ * unsigned int value 32 bit value.
+ *
+ * OUTPUT:
+ * The set bits in the value parameter are set in the configuration
+ * register.
+ *
+ * RETURN:
+ * None.
+ *
+ */
+static void ethernet_set_config_reg(unsigned int eth_port_num,
+ unsigned int value)
+{
+ unsigned int eth_config_reg;
+
+ eth_config_reg =
+ MV_READ(MV64340_ETH_PORT_CONFIG_REG(eth_port_num));
+ eth_config_reg |= value;
+ MV_WRITE(MV64340_ETH_PORT_CONFIG_REG(eth_port_num),
+ eth_config_reg);
+}
+
+/*
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ * This function returns the configuration register value of the given
+ * ethernet port.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * Port configuration register value.
+ */
+static unsigned int ethernet_get_config_reg(unsigned int eth_port_num)
+{
+ unsigned int eth_config_reg;
+
+ eth_config_reg = MV_READ(MV64340_ETH_PORT_CONFIG_EXTEND_REG
+ (eth_port_num));
+ return eth_config_reg;
+}
+
+
+/*
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ * This routine utilize the SMI interface to interact with the PHY in
+ * order to perform PHY register read.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ * unsigned int phy_reg PHY register address offset.
+ * unsigned int *value Register value buffer.
+ *
+ * OUTPUT:
+ * Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ * false if the PHY is busy or read data is not in valid state.
+ * true otherwise.
+ *
+ */
+static int eth_port_read_smi_reg(unsigned int eth_port_num,
+ unsigned int phy_reg, unsigned int *value)
+{
+ int phy_addr = ethernet_phy_get(eth_port_num);
+ unsigned int time_out = PHY_BUSY_TIMEOUT;
+ unsigned int reg_value;
+
+ /* first check that it is not busy */
+ do {
+ reg_value = MV_READ(MV64340_ETH_SMI_REG);
+ if (time_out-- == 0)
+ return 0;
+ } while (reg_value & ETH_SMI_BUSY);
+
+ /* not busy */
+
+ MV_WRITE(MV64340_ETH_SMI_REG,
+ (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
+
+ time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
+
+ do {
+ reg_value = MV_READ(MV64340_ETH_SMI_REG);
+ if (time_out-- == 0)
+ return 0;
+ } while (reg_value & ETH_SMI_READ_VALID);
+
+ /* Wait for the data to update in the SMI register */
+ for (time_out = 0; time_out < PHY_BUSY_TIMEOUT; time_out++);
+
+ reg_value = MV_READ(MV64340_ETH_SMI_REG);
+
+ *value = reg_value & 0xffff;
+
+ return 1;
+}
+
+/*
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ * This routine utilize the SMI interface to interact with the PHY in
+ * order to perform writes to PHY registers.
+ *
+ * INPUT:
+ * unsigned int eth_port_num Ethernet Port number.
+ * unsigned int phy_reg PHY register address offset.
+ * unsigned int value Register value.
+ *
+ * OUTPUT:
+ * Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ * false if the PHY is busy.
+ * true otherwise.
+ *
+ */
+static int eth_port_write_smi_reg(unsigned int eth_port_num,
+ unsigned int phy_reg, unsigned int value)
+{
+ unsigned int time_out = PHY_BUSY_TIMEOUT;
+ unsigned int reg_value;
+ int phy_addr;
+
+ phy_addr = ethernet_phy_get(eth_port_num);
+
+ /* first check that it is not busy */
+ do {
+ reg_value = MV_READ(MV64340_ETH_SMI_REG);
+ if (time_out-- == 0)
+ return 0;
+ } while (reg_value & ETH_SMI_BUSY);
+
+ /* not busy */
+ MV_WRITE(MV64340_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
+ ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+
+ return 1;
+}
+
+/*
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ * This routine send a given packet described by p_pktinfo parameter. It
+ * supports transmitting of a packet spaned over multiple buffers. The
+ * routine updates 'curr' and 'first' indexes according to the packet
+ * segment passed to the routine. In case the packet segment is first,
+ * the 'first' index is update. In any case, the 'curr' index is updated.
+ * If the routine get into Tx resource error it assigns 'curr' index as
+ * 'first'. This way the function can abort Tx process of multiple
+ * descriptors per packet.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet Port Control srtuct.
+ * struct pkt_info *p_pkt_info User packet buffer.
+ *
+ * OUTPUT:
+ * Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ * ETH_QUEUE_FULL in case of Tx resource error.
+ * ETH_ERROR in case the routine can not access Tx desc ring.
+ * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ * ETH_OK otherwise.
+ *
+ */
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+/*
+ * Modified to include the first descriptor pointer in case of SG
+ */
+static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private * mp,
+ struct pkt_info * p_pkt_info)
+{
+ int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
+ volatile struct eth_tx_desc *current_descriptor;
+ volatile struct eth_tx_desc *first_descriptor;
+ u32 command_status, first_chip_ptr;
+
+ /* Do not process Tx ring in case of Tx ring resource error */
+ if (mp->tx_resource_err)
+ return ETH_QUEUE_FULL;
+
+ /* Get the Tx Desc ring indexes */
+ tx_desc_curr = mp->tx_curr_desc_q;
+ tx_desc_used = mp->tx_used_desc_q;
+
+ current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
+ if (current_descriptor == NULL)
+ return ETH_ERROR;
+
+ tx_next_desc = (tx_desc_curr + 1) % MV64340_TX_QUEUE_SIZE;
+ command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+ if (command_status & ETH_TX_FIRST_DESC) {
+ tx_first_desc = tx_desc_curr;
+ mp->tx_first_desc_q = tx_first_desc;
+
+ /* fill first descriptor */
+ first_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
+ first_descriptor->l4i_chk = p_pkt_info->l4i_chk;
+ first_descriptor->cmd_sts = command_status;
+ first_descriptor->byte_cnt = p_pkt_info->byte_cnt;
+ first_descriptor->buf_ptr = p_pkt_info->buf_ptr;
+ first_descriptor->next_desc_ptr = mp->tx_desc_dma +
+ tx_next_desc * sizeof(struct eth_tx_desc);
+ wmb();
+ } else {
+ tx_first_desc = mp->tx_first_desc_q;
+ first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
+ if (first_descriptor == NULL) {
+ printk("First desc is NULL !!\n");
+ return ETH_ERROR;
+ }
+ if (command_status & ETH_TX_LAST_DESC)
+ current_descriptor->next_desc_ptr = 0x00000000;
+ else {
+ command_status |= ETH_BUFFER_OWNED_BY_DMA;
+ current_descriptor->next_desc_ptr = mp->tx_desc_dma +
+ tx_next_desc * sizeof(struct eth_tx_desc);
+ }
+ }
+
+ if (p_pkt_info->byte_cnt < 8) {
+ printk(" < 8 problem \n");
+ return ETH_ERROR;
+ }
+
+ current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
+ current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
+ current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
+ current_descriptor->cmd_sts = command_status;
+
+ mp->tx_skb[tx_desc_curr] = (struct sk_buff*) p_pkt_info->return_info;
+
+ wmb();
+
+ /* Set last desc with DMA ownership and interrupt enable. */
+ if (command_status & ETH_TX_LAST_DESC) {
+ current_descriptor->cmd_sts = command_status |
+ ETH_TX_ENABLE_INTERRUPT |
+ ETH_BUFFER_OWNED_BY_DMA;
+
+ if (!(command_status & ETH_TX_FIRST_DESC))
+ first_descriptor->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+ wmb();
+
+ first_chip_ptr = MV_READ(MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(mp->port_num));
+
+ /* Apply send command */
+ if (first_chip_ptr == 0x00000000)
+ MV_WRITE(MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(mp->port_num), (struct eth_tx_desc *) mp->tx_desc_dma + tx_first_desc);
+
+ ETH_ENABLE_TX_QUEUE(mp->port_num);
+
+ /*
+ * Finish Tx packet. Update first desc in case of Tx resource
+ * error */
+ tx_first_desc = tx_next_desc;
+ mp->tx_first_desc_q = tx_first_desc;
+ } else {
+ if (! (command_status & ETH_TX_FIRST_DESC) ) {
+ current_descriptor->cmd_sts = command_status;
+ wmb();
+ }
+ }
+
+ /* Check for ring index overlap in the Tx desc ring */
+ if (tx_next_desc == tx_desc_used) {
+ mp->tx_resource_err = 1;
+ mp->tx_curr_desc_q = tx_first_desc;
+
+ return ETH_QUEUE_LAST_RESOURCE;
+ }
+
+ mp->tx_curr_desc_q = tx_next_desc;
+ wmb();
+
+ return ETH_OK;
+}
+#else
+static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private * mp,
+ struct pkt_info * p_pkt_info)
+{
+ int tx_desc_curr;
+ int tx_desc_used;
+ volatile struct eth_tx_desc* current_descriptor;
+ unsigned int command_status;
+
+ /* Do not process Tx ring in case of Tx ring resource error */
+ if (mp->tx_resource_err)
+ return ETH_QUEUE_FULL;
+
+ /* Get the Tx Desc ring indexes */
+ tx_desc_curr = mp->tx_curr_desc_q;
+ tx_desc_used = mp->tx_used_desc_q;
+ current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
+
+ if (current_descriptor == NULL)
+ return ETH_ERROR;
+
+ command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+/* XXX Is this for real ?!?!? */
+ /* Buffers with a payload smaller than 8 bytes must be aligned to a
+ * 64-bit boundary. We use the memory allocated for Tx descriptor.
+ * This memory is located in TX_BUF_OFFSET_IN_DESC offset within the
+ * Tx descriptor. */
+ if (p_pkt_info->byte_cnt <= 8) {
+ printk(KERN_ERR
+ "You have failed in the < 8 bytes errata - fixme\n");
+ return ETH_ERROR;
+ }
+ current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
+ current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
+ mp->tx_skb[tx_desc_curr] = (struct sk_buff *) p_pkt_info->return_info;
+
+ mb();
+
+ /* Set last desc with DMA ownership and interrupt enable. */
+ current_descriptor->cmd_sts = command_status |
+ ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+ /* Apply send command */
+ ETH_ENABLE_TX_QUEUE(mp->port_num);
+
+ /* Finish Tx packet. Update first desc in case of Tx resource error */
+ tx_desc_curr = (tx_desc_curr + 1) % MV64340_TX_QUEUE_SIZE;
+
+ /* Update the current descriptor */
+ mp->tx_curr_desc_q = tx_desc_curr;
+
+ /* Check for ring index overlap in the Tx desc ring */
+ if (tx_desc_curr == tx_desc_used) {
+ mp->tx_resource_err = 1;
+ return ETH_QUEUE_LAST_RESOURCE;
+ }
+
+ return ETH_OK;
+}
+#endif
+
+/*
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ * This routine returns the transmitted packet information to the caller.
+ * It uses the 'first' index to support Tx desc return in case a transmit
+ * of a packet spanned over multiple buffer still in process.
+ * In case the Tx queue was in "resource error" condition, where there are
+ * no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet Port Control srtuct.
+ * struct pkt_info *p_pkt_info User packet buffer.
+ *
+ * OUTPUT:
+ * Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ * ETH_ERROR in case the routine can not access Tx desc ring.
+ * ETH_RETRY in case there is transmission in process.
+ * ETH_END_OF_JOB if the routine has nothing to release.
+ * ETH_OK otherwise.
+ *
+ */
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private * mp,
+ struct pkt_info * p_pkt_info)
+{
+ int tx_desc_used, tx_desc_curr;
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ int tx_first_desc;
+#endif
+ volatile struct eth_tx_desc *p_tx_desc_used;
+ unsigned int command_status;
+
+ /* Get the Tx Desc ring indexes */
+ tx_desc_curr = mp->tx_curr_desc_q;
+ tx_desc_used = mp->tx_used_desc_q;
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ tx_first_desc = mp->tx_first_desc_q;
+#endif
+ p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
+
+ /* XXX Sanity check */
+ if (p_tx_desc_used == NULL)
+ return ETH_ERROR;
+
+ command_status = p_tx_desc_used->cmd_sts;
+
+ /* Still transmitting... */
+#ifndef MV64340_CHECKSUM_OFFLOAD_TX
+ if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
+ return ETH_RETRY;
+#endif
+ /* Stop release. About to overlap the current available Tx descriptor */
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ if (tx_desc_used == tx_first_desc && !mp->tx_resource_err)
+ return ETH_END_OF_JOB;
+#else
+ if (tx_desc_used == tx_desc_curr && !mp->tx_resource_err)
+ return ETH_END_OF_JOB;
+#endif
+
+ /* Pass the packet information to the caller */
+ p_pkt_info->cmd_sts = command_status;
+ p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
+ mp->tx_skb[tx_desc_used] = NULL;
+
+ /* Update the next descriptor to release. */
+ mp->tx_used_desc_q = (tx_desc_used + 1) % MV64340_TX_QUEUE_SIZE;
+
+ /* Any Tx return cancels the Tx resource error status */
+ mp->tx_resource_err = 0;
+
+ return ETH_OK;
+}
+
+/*
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ * This routine returns the received data to the caller. There is no
+ * data copying during routine operation. All information is returned
+ * using pointer to packet information struct passed from the caller.
+ * If the routine exhausts Rx ring resources then the resource error flag
+ * is set.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet Port Control srtuct.
+ * struct pkt_info *p_pkt_info User packet buffer.
+ *
+ * OUTPUT:
+ * Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ * ETH_ERROR in case the routine can not access Rx desc ring.
+ * ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ * ETH_END_OF_JOB if there is no received data.
+ * ETH_OK otherwise.
+ */
+static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private * mp,
+ struct pkt_info * p_pkt_info)
+{
+ int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
+ volatile struct eth_rx_desc * p_rx_desc;
+ unsigned int command_status;
+
+ /* Do not process Rx ring in case of Rx ring resource error */
+ if (mp->rx_resource_err)
+ return ETH_QUEUE_FULL;
+
+ /* Get the Rx Desc ring 'curr and 'used' indexes */
+ rx_curr_desc = mp->rx_curr_desc_q;
+ rx_used_desc = mp->rx_used_desc_q;
+
+ p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
+
+ /* The following parameters are used to save readings from memory */
+ command_status = p_rx_desc->cmd_sts;
+
+ /* Nothing to receive... */
+ if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
+ return ETH_END_OF_JOB;
+
+ p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
+ p_pkt_info->cmd_sts = command_status;
+ p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
+ p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
+ p_pkt_info->l4i_chk = p_rx_desc->buf_size;
+
+ /* Clean the return info field to indicate that the packet has been */
+ /* moved to the upper layers */
+ mp->rx_skb[rx_curr_desc] = NULL;
+
+ /* Update current index in data structure */
+ rx_next_curr_desc = (rx_curr_desc + 1) % MV64340_RX_QUEUE_SIZE;
+ mp->rx_curr_desc_q = rx_next_curr_desc;
+
+ /* Rx descriptors exhausted. Set the Rx ring resource error flag */
+ if (rx_next_curr_desc == rx_used_desc)
+ mp->rx_resource_err = 1;
+
+ mb();
+ return ETH_OK;
+}
+
+/*
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ * This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ * next 'used' descriptor and attached the returned buffer to it.
+ * In case the Rx ring was in "resource error" condition, where there are
+ * no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ * struct mv64340_private *mp Ethernet Port Control srtuct.
+ * struct pkt_info *p_pkt_info Information on the returned buffer.
+ *
+ * OUTPUT:
+ * New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ * ETH_ERROR in case the routine can not access Rx desc ring.
+ * ETH_OK otherwise.
+ */
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private * mp,
+ struct pkt_info * p_pkt_info)
+{
+ int used_rx_desc; /* Where to return Rx resource */
+ volatile struct eth_rx_desc* p_used_rx_desc;
+
+ /* Get 'used' Rx descriptor */
+ used_rx_desc = mp->rx_used_desc_q;
+ p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
+
+ p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+ p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
+ mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
+
+ /* Flush the write pipe */
+ mb();
+
+ /* Return the descriptor to DMA ownership */
+ p_used_rx_desc->cmd_sts =
+ ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+ /* Flush descriptor and CPU pipe */
+ mb();
+
+ /* Move the used descriptor pointer to the next descriptor */
+ mp->rx_used_desc_q = (used_rx_desc + 1) % MV64340_RX_QUEUE_SIZE;
+
+ /* Any Rx return cancels the Rx resource error status */
+ mp->rx_resource_err = 0;
+
+ return ETH_OK;
+}
--- /dev/null
+#ifndef __MV64340_ETH_H__
+#define __MV64340_ETH_H__
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+#include <linux/mv643xx.h>
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+/*
+ * The first part is the high level driver of the gigE ethernet ports.
+ */
+
+#define ETH_PORT0_IRQ_NUM 48 /* main high register, bit0 */
+#define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1 /* main high register, bit1 */
+#define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2 /* main high register, bit1 */
+
+/* Checksum offload for Tx works */
+#define MV64340_CHECKSUM_OFFLOAD_TX
+#define MV64340_NAPI
+#define MV64340_TX_FAST_REFILL
+#undef MV64340_COAL
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 1000 descriptors */
+#define MV64340_TX_QUEUE_SIZE 1000
+
+/* Default RX ring size is 400 descriptors */
+#define MV64340_RX_QUEUE_SIZE 400
+
+#define MV64340_TX_COAL 100
+#ifdef MV64340_COAL
+#define MV64340_RX_COAL 100
+#endif
+
+
+/*
+ * The second part is the low level driver of the gigE ethernet ports. *
+ */
+
+
+/*
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ * This header file contains macros typedefs and function declaration for
+ * the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ * None.
+ *
+ */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE \
+ ETH_UNICAST_NORMAL_MODE | \
+ ETH_DEFAULT_RX_QUEUE_0 | \
+ ETH_DEFAULT_RX_ARP_QUEUE_0 | \
+ ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
+ ETH_RECEIVE_BC_IF_IP | \
+ ETH_RECEIVE_BC_IF_ARP | \
+ ETH_CAPTURE_TCP_FRAMES_DIS | \
+ ETH_CAPTURE_UDP_FRAMES_DIS | \
+ ETH_DEFAULT_RX_TCP_QUEUE_0 | \
+ ETH_DEFAULT_RX_UDP_QUEUE_0 | \
+ ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE \
+ ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
+ ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#define PORT_SDMA_CONFIG_VALUE \
+ ETH_RX_BURST_SIZE_16_64BIT | \
+ GT_ETH_IPG_INT_RX(0) | \
+ ETH_TX_BURST_SIZE_16_64BIT;
+
+#define GT_ETH_IPG_INT_RX(value) \
+ ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE \
+ ETH_FORCE_LINK_PASS | \
+ ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
+ ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
+ ETH_ADV_SYMMETRIC_FLOW_CTRL | \
+ ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ ETH_FORCE_BP_MODE_NO_JAM | \
+ BIT9 | \
+ ETH_DO_NOT_FORCE_LINK_FAIL | \
+ ETH_RETRANSMIT_16_ATTEMPTS | \
+ ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
+ ETH_DTE_ADV_0 | \
+ ETH_DISABLE_AUTO_NEG_BYPASS | \
+ ETH_AUTO_NEG_NO_CHANGE | \
+ ETH_MAX_RX_PACKET_9700BYTE | \
+ ETH_CLR_EXT_LOOPBACK | \
+ ETH_SET_FULL_DUPLEX_MODE | \
+ ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
+
+#define RX_BUFFER_MAX_SIZE 0x4000000
+#define TX_BUFFER_MAX_SIZE 0x4000000
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR 0
+#define REJECT_MAC_ADDR 1
+
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET 0x2
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
+#define ETH_MIB_FRAMES_64_OCTETS 0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT 0x40
+#define ETH_MIB_EXCESSIVE_COLLISION 0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT 0x54
+#define ETH_MIB_GOOD_FC_RECEIVED 0x58
+#define ETH_MIB_BAD_FC_RECEIVED 0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
+#define ETH_MIB_OVERSIZE_RECEIVED 0x68
+#define ETH_MIB_JABBER_RECEIVED 0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
+#define ETH_MIB_BAD_CRC_EVENT 0x74
+#define ETH_MIB_COLLISION 0x78
+#define ETH_MIB_LATE_COLLISION 0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII 0
+#define ETH_INTERFACE_PCM BIT0
+#define ETH_LINK_IS_DOWN 0
+#define ETH_LINK_IS_UP BIT1
+#define ETH_PORT_AT_HALF_DUPLEX 0
+#define ETH_PORT_AT_FULL_DUPLEX BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED 0
+#define ETH_RX_FLOW_CTRL_ENBALED BIT3
+#define ETH_GMII_SPEED_100_10 0
+#define ETH_GMII_SPEED_1000 BIT4
+#define ETH_MII_SPEED_10 0
+#define ETH_MII_SPEED_100 BIT5
+#define ETH_NO_TX 0
+#define ETH_TX_IN_PROGRESS BIT7
+#define ETH_BYPASS_NO_ACTIVE 0
+#define ETH_BYPASS_ACTIVE BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE 0
+#define ETH_PORT_AT_PARTITION_STATE BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
+#define ETH_PORT_TX_FIFO_EMPTY BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE 0
+#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
+#define ETH_DEFAULT_RX_QUEUE_0 0
+#define ETH_DEFAULT_RX_QUEUE_1 BIT1
+#define ETH_DEFAULT_RX_QUEUE_2 BIT2
+#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4 BIT3
+#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
+#define ETH_RECEIVE_BC_IF_IP 0
+#define ETH_REJECT_BC_IF_IP BIT8
+#define ETH_RECEIVE_BC_IF_ARP 0
+#define ETH_REJECT_BC_IF_ARP BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS 0
+#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS 0
+#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
+#define ETH_PARTITION_DISABLE 0
+#define ETH_PARTITION_ENABLE BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE BIT0
+#define ETH_QUEUE_1_ENABLE BIT1
+#define ETH_QUEUE_2_ENABLE BIT2
+#define ETH_QUEUE_3_ENABLE BIT3
+#define ETH_QUEUE_4_ENABLE BIT4
+#define ETH_QUEUE_5_ENABLE BIT5
+#define ETH_QUEUE_6_ENABLE BIT6
+#define ETH_QUEUE_7_ENABLE BIT7
+#define ETH_QUEUE_0_DISABLE BIT8
+#define ETH_QUEUE_1_DISABLE BIT9
+#define ETH_QUEUE_2_DISABLE BIT10
+#define ETH_QUEUE_3_DISABLE BIT11
+#define ETH_QUEUE_4_DISABLE BIT12
+#define ETH_QUEUE_5_DISABLE BIT13
+#define ETH_QUEUE_6_DISABLE BIT14
+#define ETH_QUEUE_7_DISABLE BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT 0
+#define ETH_RX_BURST_SIZE_2_64BIT BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT BIT3
+#define ETH_BLM_RX_NO_SWAP BIT4
+#define ETH_BLM_RX_BYTE_SWAP 0
+#define ETH_BLM_TX_NO_SWAP BIT5
+#define ETH_BLM_TX_BYTE_SWAP 0
+#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
+#define ETH_DESCRIPTORS_NO_SWAP 0
+#define ETH_TX_BURST_SIZE_1_64BIT 0
+#define ETH_TX_BURST_SIZE_2_64BIT BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT BIT24
+
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE 0
+#define ETH_SERIAL_PORT_ENABLE BIT0
+#define ETH_FORCE_LINK_PASS BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS 0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
+#define ETH_ADV_NO_FLOW_CTRL 0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM 0
+#define ETH_FORCE_BP_MODE_JAM_TX BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
+#define ETH_FORCE_LINK_FAIL 0
+#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
+#define ETH_RETRANSMIT_16_ATTEMPTS 0
+#define ETH_RETRANSMIT_FOREVER BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
+#define ETH_DTE_ADV_0 0
+#define ETH_DTE_ADV_1 BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS 0
+#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
+#define ETH_AUTO_NEG_NO_CHANGE 0
+#define ETH_RESTART_AUTO_NEG BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE 0
+#define ETH_MAX_RX_PACKET_1522BYTE BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK BIT20
+#define ETH_CLR_EXT_LOOPBACK 0
+#define ETH_SET_FULL_DUPLEX_MODE BIT21
+#define ETH_SET_HALF_DUPLEX_MODE 0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define ETH_SET_GMII_SPEED_TO_10_100 0
+#define ETH_SET_GMII_SPEED_TO_1000 BIT23
+#define ETH_SET_MII_SPEED_TO_10 0
+#define ETH_SET_MII_SPEED_TO_100 BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
+#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
+#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR (0 )
+#define ETH_UR_ERROR (BIT1 )
+#define ETH_RL_ERROR (BIT2 )
+#define ETH_LLC_SNAP_FORMAT (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR (0 )
+#define ETH_OVERRUN_ERROR (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
+#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED (BIT19)
+#define ETH_BPDU_FRAME (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
+#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
+#define ETH_OTHER_FRAME_TYPE (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
+#define ETH_FRAME_HEADER_OK (BIT25)
+#define ETH_RX_LAST_DESC (BIT26)
+#define ETH_RX_FIRST_DESC (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
+#define ETH_FRAME_SET_TO_VLAN (BIT15)
+#define ETH_TCP_FRAME (0 )
+#define ETH_UDP_FRAME (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
+#define ETH_ZERO_PADDING (BIT19)
+#define ETH_TX_LAST_DESC (BIT20)
+#define ETH_TX_FIRST_DESC (BIT21)
+#define ETH_GEN_CRC (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT (BIT23)
+#define ETH_AUTO_MODE (BIT30)
+
+/* typedefs */
+
+typedef enum _eth_func_ret_status {
+ ETH_OK, /* Returned as expected. */
+ ETH_ERROR, /* Fundamental error. */
+ ETH_RETRY, /* Could not process request. Try later. */
+ ETH_END_OF_JOB, /* Ring has nothing to process. */
+ ETH_QUEUE_FULL, /* Ring resource error. */
+ ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
+} ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_target {
+ ETH_TARGET_DRAM,
+ ETH_TARGET_DEVICE,
+ ETH_TARGET_CBS,
+ ETH_TARGET_PCI0,
+ ETH_TARGET_PCI1
+} ETH_TARGET;
+
+/* These are for big-endian machines. Little endian needs different
+ * definitions.
+ */
+#if defined(__BIG_ENDIAN)
+struct eth_rx_desc {
+ u16 byte_cnt; /* Descriptor buffer byte count */
+ u16 buf_size; /* Buffer size */
+ u32 cmd_sts; /* Descriptor command status */
+ u32 next_desc_ptr; /* Next descriptor pointer */
+ u32 buf_ptr; /* Descriptor buffer pointer */
+};
+
+struct eth_tx_desc {
+ u16 byte_cnt; /* buffer byte count */
+ u16 l4i_chk; /* CPU provided TCP checksum */
+ u32 cmd_sts; /* Command/status field */
+ u32 next_desc_ptr; /* Pointer to next descriptor */
+ u32 buf_ptr; /* pointer to buffer for this descriptor */
+};
+
+#elif defined(__LITTLE_ENDIAN)
+struct eth_rx_desc {
+ u32 cmd_sts; /* Descriptor command status */
+ u16 buf_size; /* Buffer size */
+ u16 byte_cnt; /* Descriptor buffer byte count */
+ u32 buf_ptr; /* Descriptor buffer pointer */
+ u32 next_desc_ptr; /* Next descriptor pointer */
+};
+
+struct eth_tx_desc {
+ u32 cmd_sts; /* Command/status field */
+ u16 l4i_chk; /* CPU provided TCP checksum */
+ u16 byte_cnt; /* buffer byte count */
+ u32 buf_ptr; /* pointer to buffer for this descriptor */
+ u32 next_desc_ptr; /* Pointer to next descriptor */
+};
+#else
+#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
+#endif
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors. */
+struct pkt_info {
+ unsigned short byte_cnt; /* Descriptor buffer byte count */
+ unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
+ unsigned int cmd_sts; /* Descriptor command status */
+ dma_addr_t buf_ptr; /* Descriptor buffer pointer */
+ struct sk_buff * return_info; /* User resource return information */
+};
+
+
+/* Ethernet port specific infomation */
+
+struct mv64340_private {
+ int port_num; /* User Ethernet port number */
+ u8 port_mac_addr[6]; /* User defined port MAC address. */
+ u32 port_config; /* User port configuration value */
+ u32 port_config_extend; /* User port config extend value */
+ u32 port_sdma_config; /* User port SDMA config value */
+ u32 port_serial_control; /* User port serial control value */
+ u32 port_tx_queue_command; /* Port active Tx queues summary */
+ u32 port_rx_queue_command; /* Port active Rx queues summary */
+
+ int rx_resource_err; /* Rx ring resource error flag */
+ int tx_resource_err; /* Tx ring resource error flag */
+
+ /* Tx/Rx rings managment indexes fields. For driver use */
+
+ /* Next available and first returning Rx resource */
+ int rx_curr_desc_q, rx_used_desc_q;
+
+ /* Next available and first returning Tx resource */
+ int tx_curr_desc_q, tx_used_desc_q;
+#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+ int tx_first_desc_q;
+#endif
+
+#ifdef MV64340_TX_FAST_REFILL
+ u32 tx_clean_threshold;
+#endif
+
+ volatile struct eth_rx_desc * p_rx_desc_area;
+ dma_addr_t rx_desc_dma;
+ unsigned int rx_desc_area_size;
+ struct sk_buff * rx_skb[MV64340_RX_QUEUE_SIZE];
+
+ volatile struct eth_tx_desc * p_tx_desc_area;
+ dma_addr_t tx_desc_dma;
+ unsigned int tx_desc_area_size;
+ struct sk_buff * tx_skb[MV64340_TX_QUEUE_SIZE];
+
+ struct work_struct tx_timeout_task;
+
+ /*
+ * Former struct mv64340_eth_priv members start here
+ */
+ struct net_device_stats stats;
+ spinlock_t lock;
+ /* Size of Tx Ring per queue */
+ unsigned int tx_ring_size;
+ /* Ammont of SKBs outstanding on Tx queue */
+ unsigned int tx_ring_skbs;
+ /* Size of Rx Ring per queue */
+ unsigned int rx_ring_size;
+ /* Ammount of SKBs allocated to Rx Ring per queue */
+ unsigned int rx_ring_skbs;
+
+ /*
+ * rx_task used to fill RX ring out of bottom half context
+ */
+ struct work_struct rx_task;
+
+ /*
+ * Used in case RX Ring is empty, which can be caused when
+ * system does not have resources (skb's)
+ */
+ struct timer_list timeout;
+ long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
+ unsigned rx_timer_flag;
+
+ u32 rx_int_coal;
+ u32 tx_int_coal;
+};
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init(struct mv64340_private *mp);
+static void eth_port_reset(unsigned int eth_port_num);
+static int eth_port_start(struct mv64340_private *mp);
+
+static void ethernet_set_config_reg(unsigned int eth_port_num,
+ unsigned int value);
+static unsigned int ethernet_get_config_reg(unsigned int eth_port_num);
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set(unsigned int eth_port_num,
+ unsigned char *p_addr);
+
+/* PHY and MIB routines */
+static int ethernet_phy_reset(unsigned int eth_port_num);
+
+static int eth_port_write_smi_reg(unsigned int eth_port_num,
+ unsigned int phy_reg,
+ unsigned int value);
+
+static int eth_port_read_smi_reg(unsigned int eth_port_num,
+ unsigned int phy_reg,
+ unsigned int *value);
+
+static void eth_clear_mib_counters(unsigned int eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private *mp,
+ struct pkt_info * p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private *mp,
+ struct pkt_info * p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private *mp,
+ struct pkt_info * p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private *mp,
+ struct pkt_info * p_pkt_info);
+
+#endif /* __MV64340_ETH_H__ */
--- /dev/null
+/*
+ * ACPI PCI Hot Plug IBM Extension
+ *
+ * Copyright (C) 2004 Vernon Mauery <vernux@us.ibm.com>
+ * Copyright (C) 2004 IBM Corp.
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Send feedback to <vernux@us.ibm.com>
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <acpi/acpi_bus.h>
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+#include <asm/uaccess.h>
+#include <linux/moduleparam.h>
+
+#include "acpiphp.h"
+#include "pci_hotplug.h"
+
+#define DRIVER_VERSION "1.0.1"
+#define DRIVER_AUTHOR "Irene Zubarev <zubarev@us.ibm.com>, Vernon Mauery <vernux@us.ibm.com>"
+#define DRIVER_DESC "ACPI Hot Plug PCI Controller Driver IBM extension"
+
+static int debug;
+
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRIVER_VERSION);
+module_param(debug, bool, 644);
+MODULE_PARM_DESC(debug, " Debugging mode enabled or not");
+#define MY_NAME "acpiphp_ibm"
+
+#undef dbg
+#define dbg(format, arg...) \
+do { \
+ if (debug) \
+ printk(KERN_DEBUG "%s: " format, \
+ MY_NAME , ## arg); \
+} while (0)
+
+#define FOUND_APCI 0x61504349
+/* these are the names for the IBM ACPI pseudo-device */
+#define IBM_HARDWARE_ID1 "IBM37D0"
+#define IBM_HARDWARE_ID2 "IBM37D4"
+
+/* union apci_descriptor - allows access to the
+ * various device descriptors that are embedded in the
+ * aPCI table
+ */
+union apci_descriptor {
+ struct {
+ char sig[4];
+ u8 len;
+ } header;
+ struct {
+ u8 type;
+ u8 len;
+ u16 slot_id;
+ u8 bus_id;
+ u8 dev_num;
+ u8 slot_num;
+ u8 slot_attr[2];
+ u8 attn;
+ u8 status[2];
+ u8 sun;
+ } slot;
+ struct {
+ u8 type;
+ u8 len;
+ } generic;
+};
+
+/* struct notification - keeps info about the device
+ * that cause the ACPI notification event
+ */
+struct notification {
+ struct acpi_device *device;
+ u8 event;
+};
+
+static int ibm_set_attention_status(struct hotplug_slot *slot, u8 status);
+static int ibm_get_attention_status(struct hotplug_slot *slot, u8 *status);
+static void ibm_handle_events(acpi_handle handle, u32 event, void *context);
+static int ibm_get_table_from_acpi(char **bufp);
+static ssize_t ibm_read_apci_table(struct kobject *kobj,
+ char *buffer, loff_t pos, size_t size);
+static acpi_status __init ibm_find_acpi_device(acpi_handle handle,
+ u32 lvl, void *context, void **rv);
+static int __init ibm_acpiphp_init(void);
+static void __exit ibm_acpiphp_exit(void);
+
+static acpi_handle ibm_acpi_handle;
+static struct notification ibm_note;
+static struct bin_attribute ibm_apci_table_attr = {
+ .attr = {
+ .name = "apci_table",
+ .owner = THIS_MODULE,
+ .mode = S_IRUGO,
+ },
+ .read = ibm_read_apci_table,
+ .write = NULL,
+};
+static struct acpiphp_attention_info ibm_attention_info =
+{
+ .set_attn = ibm_set_attention_status,
+ .get_attn = ibm_get_attention_status,
+ .owner = THIS_MODULE,
+};
+
+
+/**
+ * ibm_set_attention_status - callback method to set the attention LED
+ * @slot: the hotplug_slot to work with
+ * @status: what to set the LED to (0 or 1)
+ *
+ * Description: this method is registered with the acpiphp module as a
+ * callback to do the device specific task of setting the LED status
+ **/
+static int ibm_set_attention_status(struct hotplug_slot *slot, u8 status)
+{
+ int retval = 0;
+ union acpi_object args[2];
+ struct acpi_object_list params = { .pointer = args, .count = 2 };
+ acpi_status stat;
+ unsigned long rc = 0;
+ struct acpiphp_slot *acpi_slot;
+
+ acpi_slot = ((struct slot *)(slot->private))->acpi_slot;
+
+ dbg("%s: set slot %d attention status to %d\n", __FUNCTION__,
+ acpi_slot->sun, (status ? 1 : 0));
+
+ args[0].type = ACPI_TYPE_INTEGER;
+ args[0].integer.value = acpi_slot->sun;
+ args[1].type = ACPI_TYPE_INTEGER;
+ args[1].integer.value = (status) ? 1 : 0;
+
+ stat = acpi_evaluate_integer(ibm_acpi_handle, "APLS", ¶ms, &rc);
+ if (ACPI_FAILURE(stat)) {
+ retval = -ENODEV;
+ err("APLS evaluation failed: 0x%08x\n", stat);
+ } else if (!rc) {
+ retval = -ERANGE;
+ err("APLS method failed: 0x%08lx\n", rc);
+ }
+ return retval;
+}
+
+/**
+ * ibm_get_attention_status - callback method to get attention LED status
+ * @slot: the hotplug_slot to work with
+ * @status: returns what the LED is set to (0 or 1)
+ *
+ * Description: this method is registered with the acpiphp module as a
+ * callback to do the device specific task of getting the LED status
+ *
+ * Because there is no direct method of getting the LED status directly
+ * from an ACPI call, we read the aPCI table and parse out our
+ * slot descriptor to read the status from that.
+ **/
+static int ibm_get_attention_status(struct hotplug_slot *slot, u8 *status)
+{
+ int retval = -EINVAL, ind = 0, size;
+ char *table = NULL;
+ struct acpiphp_slot *acpi_slot;
+ union apci_descriptor *des;
+
+ acpi_slot = ((struct slot *)(slot->private))->acpi_slot;
+
+ size = ibm_get_table_from_acpi(&table);
+ if (size <= 0 || !table)
+ goto get_attn_done;
+ // read the header
+ des = (union apci_descriptor *)&table[ind];
+ if (memcmp(des->header.sig, "aPCI", 4) != 0)
+ goto get_attn_done;
+ des = (union apci_descriptor *)&table[ind += des->header.len];
+ while (ind < size && (des->generic.type != 0x82 ||
+ des->slot.slot_id != acpi_slot->sun))
+ des = (union apci_descriptor *)&table[ind += des->generic.len];
+ if (ind < size && des->slot.slot_id == acpi_slot->sun) {
+ retval = 0;
+ if (des->slot.attn & 0xa0 || des->slot.status[1] & 0x08)
+ *status = 1;
+ else
+ *status = 0;
+ }
+
+ dbg("%s: get slot %d attention status is %d retval=%x\n",
+ __FUNCTION__, acpi_slot->sun, *status, retval);
+
+get_attn_done:
+ kfree(table);
+ return retval;
+}
+
+/**
+ * ibm_handle_events - listens for ACPI events for the IBM37D0 device
+ * @handle: an ACPI handle to the device that caused the event
+ * @event: the event info (device specific)
+ * @context: passed context (our notification struct)
+ *
+ * Description: this method is registered as a callback with the ACPI
+ * subsystem it is called when this device has an event to notify the OS of
+ *
+ * The events actually come from the device as two events that get
+ * synthesized into one event with data by this function. The event
+ * ID comes first and then the slot number that caused it. We report
+ * this as one event to the OS.
+ *
+ * From section 5.6.2.2 of the ACPI 2.0 spec, I understand that the OSPM will
+ * only re-enable the interrupt that causes this event AFTER this method
+ * has returned, thereby enforcing serial access for the notification struct.
+ **/
+static void ibm_handle_events(acpi_handle handle, u32 event, void *context)
+{
+ u8 detail = event & 0x0f;
+ u8 subevent = event & 0xf0;
+ struct notification *note = context;
+
+ dbg("%s: Received notification %02x\n", __FUNCTION__, event);
+
+ if (subevent == 0x80) {
+ dbg("%s: generationg bus event\n", __FUNCTION__);
+ acpi_bus_generate_event(note->device, note->event, detail);
+ } else
+ note->event = event;
+}
+
+/**
+ * ibm_get_table_from_acpi - reads the APLS buffer from ACPI
+ * @bufp: address to pointer to allocate for the table
+ *
+ * Description: this method reads the APLS buffer in from ACPI and
+ * stores the "stripped" table into a single buffer
+ * it allocates and passes the address back in bufp
+ *
+ * If NULL is passed in as buffer, this method only calculates
+ * the size of the table and returns that without filling
+ * in the buffer
+ *
+ * returns < 0 on error or the size of the table on success
+ **/
+static int ibm_get_table_from_acpi(char **bufp)
+{
+ union acpi_object *package;
+ struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+ acpi_status status;
+ char *lbuf = NULL;
+ int i, size = -EIO;
+
+ status = acpi_evaluate_object(ibm_acpi_handle, "APCI", NULL, &buffer);
+ if (ACPI_FAILURE(status)) {
+ err("%s: APCI evaluation failed\n", __FUNCTION__);
+ return -ENODEV;
+ }
+
+ package = (union acpi_object *) buffer.pointer;
+ if(!(package) ||
+ (package->type != ACPI_TYPE_PACKAGE) ||
+ !(package->package.elements)) {
+ err("%s: Invalid APCI object\n", __FUNCTION__);
+ goto read_table_done;
+ }
+
+ for(size = 0, i = 0; i < package->package.count; i++) {
+ if (package->package.elements[i].type != ACPI_TYPE_BUFFER) {
+ err("%s: Invalid APCI element %d\n", __FUNCTION__, i);
+ goto read_table_done;
+ }
+ size += package->package.elements[i].buffer.length;
+ }
+
+ if (bufp == NULL)
+ goto read_table_done;
+
+ lbuf = kmalloc(size, GFP_KERNEL);
+ dbg("%s: element count: %i, ASL table size: %i, &table = 0x%p\n",
+ __FUNCTION__, package->package.count, size, lbuf);
+
+ if (lbuf) {
+ *bufp = lbuf;
+ memset(lbuf, 0, size);
+ } else {
+ size = -ENOMEM;
+ goto read_table_done;
+ }
+
+ size = 0;
+ for (i=0; i<package->package.count; i++) {
+ memcpy(&lbuf[size],
+ package->package.elements[i].buffer.pointer,
+ package->package.elements[i].buffer.length);
+ size += package->package.elements[i].buffer.length;
+ }
+
+read_table_done:
+ kfree(buffer.pointer);
+ return size;
+}
+
+/**
+ * ibm_read_apci_table - callback for the sysfs apci_table file
+ * @kobj: the kobject this binary attribute is a part of
+ * @buffer: the kernel space buffer to fill
+ * @pos: the offset into the file
+ * @size: the number of bytes requested
+ *
+ * Description: gets registered with sysfs as the reader callback
+ * to be executed when /sys/bus/pci/slots/apci_table gets read
+ *
+ * Since we don't get notified on open and close for this file,
+ * things get really tricky here...
+ * our solution is to only allow reading the table in all at once
+ **/
+static ssize_t ibm_read_apci_table(struct kobject *kobj,
+ char *buffer, loff_t pos, size_t size)
+{
+ int bytes_read = -EINVAL;
+ char *table = NULL;
+
+ dbg("%s: pos = %d, size = %zd\n", __FUNCTION__, (int)pos, size);
+
+ if (pos == 0) {
+ bytes_read = ibm_get_table_from_acpi(&table);
+ if (bytes_read > 0 && bytes_read <= size)
+ memcpy(buffer, table, bytes_read);
+ kfree(table);
+ }
+ return bytes_read;
+}
+
+/**
+ * ibm_find_acpi_device - callback to find our ACPI device
+ * @handle: the ACPI handle of the device we are inspecting
+ * @lvl: depth into the namespace tree
+ * @context: a pointer to our handle to fill when we find the device
+ * @rv: a return value to fill if desired
+ *
+ * Description: used as a callback when calling acpi_walk_namespace
+ * to find our device. When this method returns non-zero
+ * acpi_walk_namespace quits its search and returns our value
+ **/
+static acpi_status __init ibm_find_acpi_device(acpi_handle handle,
+ u32 lvl, void *context, void **rv)
+{
+ acpi_handle *phandle = (acpi_handle *)context;
+ acpi_status status;
+ struct acpi_device_info info;
+ struct acpi_buffer info_buffer = {
+ .length = sizeof(struct acpi_device_info),
+ .pointer = &info,
+ };
+
+ status = acpi_get_object_info(handle, &info_buffer);
+ if (ACPI_FAILURE(status)) {
+ err("%s: Failed to get device information", __FUNCTION__);
+ return 0;
+ }
+ info.hardware_id.value[sizeof(info.hardware_id.value) - 1] = '\0';
+
+ if(info.current_status && (info.valid & ACPI_VALID_HID) &&
+ (!strcmp(info.hardware_id.value, IBM_HARDWARE_ID1) ||
+ !strcmp(info.hardware_id.value, IBM_HARDWARE_ID2))) {
+ dbg("found hardware: %s, handle: %p\n", info.hardware_id.value,
+ handle);
+ *phandle = handle;
+ /* returning non-zero causes the search to stop
+ * and returns this value to the caller of
+ * acpi_walk_namespace, but it also causes some warnings
+ * in the acpi debug code to print...
+ */
+ return FOUND_APCI;
+ }
+ return 0;
+}
+
+static int __init ibm_acpiphp_init(void)
+{
+ int retval = 0;
+ acpi_status status;
+ struct acpi_device *device;
+ struct kobject *sysdir = &pci_hotplug_slots_subsys.kset.kobj;
+
+ dbg("%s\n", __FUNCTION__);
+
+ if (acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
+ ACPI_UINT32_MAX, ibm_find_acpi_device,
+ &ibm_acpi_handle, NULL) != FOUND_APCI) {
+ err("%s: acpi_walk_namespace failed\n", __FUNCTION__);
+ retval = -ENODEV;
+ goto init_return;
+ }
+ dbg("%s: found IBM aPCI device\n", __FUNCTION__);
+ if (acpi_bus_get_device(ibm_acpi_handle, &device)) {
+ err("%s: acpi_bus_get_device failed\n", __FUNCTION__);
+ retval = -ENODEV;
+ goto init_return;
+ }
+ if (acpiphp_register_attention(&ibm_attention_info)) {
+ retval = -ENODEV;
+ goto init_return;
+ }
+
+ ibm_note.device = device;
+ status = acpi_install_notify_handler(
+ ibm_acpi_handle,
+ ACPI_DEVICE_NOTIFY,
+ ibm_handle_events,
+ &ibm_note);
+ if (ACPI_FAILURE(status)) {
+ err("%s: Failed to register notification handler\n",
+ __FUNCTION__);
+ retval = -EBUSY;
+ goto init_cleanup;
+ }
+
+ ibm_apci_table_attr.size = ibm_get_table_from_acpi(NULL);
+ retval = sysfs_create_bin_file(sysdir, &ibm_apci_table_attr);
+
+ return retval;
+
+init_cleanup:
+ acpiphp_unregister_attention(&ibm_attention_info);
+init_return:
+ return retval;
+}
+
+static void __exit ibm_acpiphp_exit(void)
+{
+ acpi_status status;
+ struct kobject *sysdir = &pci_hotplug_slots_subsys.kset.kobj;
+
+ dbg("%s\n", __FUNCTION__);
+
+ if (acpiphp_unregister_attention(&ibm_attention_info))
+ err("%s: attention info deregistration failed", __FUNCTION__);
+
+ status = acpi_remove_notify_handler(
+ ibm_acpi_handle,
+ ACPI_DEVICE_NOTIFY,
+ ibm_handle_events);
+ if (ACPI_FAILURE(status))
+ err("%s: Notification handler removal failed\n",
+ __FUNCTION__);
+ // remove the /sys entries
+ if (sysfs_remove_bin_file(sysdir, &ibm_apci_table_attr))
+ err("%s: removal of sysfs file apci_table failed\n",
+ __FUNCTION__);
+}
+
+module_init(ibm_acpiphp_init);
+module_exit(ibm_acpiphp_exit);
--- /dev/null
+obj-$(CONFIG_SCSI_IBMVSCSI) += ibmvscsic.o
+
+ibmvscsic-y += ibmvscsi.o
+ibmvscsic-$(CONFIG_PPC_ISERIES) += iseries_vscsi.o
+ibmvscsic-$(CONFIG_PPC_PSERIES) += rpa_vscsi.o
--- /dev/null
+/* ------------------------------------------------------------
+ * ibmvscsi.c
+ * (C) Copyright IBM Corporation 1994, 2004
+ * Authors: Colin DeVilbiss (devilbis@us.ibm.com)
+ * Santiago Leon (santil@us.ibm.com)
+ * Dave Boutcher (sleddog@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ *
+ * ------------------------------------------------------------
+ * Emulation of a SCSI host adapter for Virtual I/O devices
+ *
+ * This driver supports the SCSI adapter implemented by the IBM
+ * Power5 firmware. That SCSI adapter is not a physical adapter,
+ * but allows Linux SCSI peripheral drivers to directly
+ * access devices in another logical partition on the physical system.
+ *
+ * The virtual adapter(s) are present in the open firmware device
+ * tree just like real adapters.
+ *
+ * One of the capabilities provided on these systems is the ability
+ * to DMA between partitions. The architecture states that for VSCSI,
+ * the server side is allowed to DMA to and from the client. The client
+ * is never trusted to DMA to or from the server directly.
+ *
+ * Messages are sent between partitions on a "Command/Response Queue"
+ * (CRQ), which is just a buffer of 16 byte entries in the receiver's
+ * Senders cannot access the buffer directly, but send messages by
+ * making a hypervisor call and passing in the 16 bytes. The hypervisor
+ * puts the message in the next 16 byte space in round-robbin fashion,
+ * turns on the high order bit of the message (the valid bit), and
+ * generates an interrupt to the receiver (if interrupts are turned on.)
+ * The receiver just turns off the valid bit when they have copied out
+ * the message.
+ *
+ * The VSCSI client builds a SCSI Remote Protocol (SRP) Information Unit
+ * (IU) (as defined in the T10 standard available at www.t10.org), gets
+ * a DMA address for the message, and sends it to the server as the
+ * payload of a CRQ message. The server DMAs the SRP IU and processes it,
+ * including doing any additional data transfers. When it is done, it
+ * DMAs the SRP response back to the same address as the request came from,
+ * and sends a CRQ message back to inform the client that the request has
+ * completed.
+ *
+ * Note that some of the underlying infrastructure is different between
+ * machines conforming to the "RS/6000 Platform Architecture" (RPA) and
+ * the older iSeries hypervisor models. To support both, some low level
+ * routines have been broken out into rpa_vscsi.c and iseries_vscsi.c.
+ * The Makefile should pick one, not two, not zero, of these.
+ *
+ * TODO: This is currently pretty tied to the IBM i/pSeries hypervisor
+ * interfaces. It would be really nice to abstract this above an RDMA
+ * layer.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/dma-mapping.h>
+#include <asm/vio.h>
+#include <scsi/scsi.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_device.h>
+#include "ibmvscsi.h"
+
+/* The values below are somewhat arbitrary default values, but
+ * OS/400 will use 3 busses (disks, CDs, tapes, I think.)
+ * Note that there are 3 bits of channel value, 6 bits of id, and
+ * 5 bits of LUN.
+ */
+static int max_id = 64;
+static int max_channel = 3;
+static int init_timeout = 5;
+static int max_requests = 50;
+
+#define IBMVSCSI_VERSION "1.5.1"
+
+MODULE_DESCRIPTION("IBM Virtual SCSI");
+MODULE_AUTHOR("Dave Boutcher");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(IBMVSCSI_VERSION);
+
+module_param_named(max_id, max_id, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(max_id, "Largest ID value for each channel");
+module_param_named(max_channel, max_channel, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(max_channel, "Largest channel value");
+module_param_named(init_timeout, init_timeout, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(init_timeout, "Initialization timeout in seconds");
+module_param_named(max_requests, max_requests, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(max_requests, "Maximum requests for this adapter");
+
+/* ------------------------------------------------------------
+ * Routines for the event pool and event structs
+ */
+/**
+ * initialize_event_pool: - Allocates and initializes the event pool for a host
+ * @pool: event_pool to be initialized
+ * @size: Number of events in pool
+ * @hostdata: ibmvscsi_host_data who owns the event pool
+ *
+ * Returns zero on success.
+*/
+static int initialize_event_pool(struct event_pool *pool,
+ int size, struct ibmvscsi_host_data *hostdata)
+{
+ int i;
+
+ pool->size = size;
+ pool->next = 0;
+ pool->events = kmalloc(pool->size * sizeof(*pool->events), GFP_KERNEL);
+ if (!pool->events)
+ return -ENOMEM;
+ memset(pool->events, 0x00, pool->size * sizeof(*pool->events));
+
+ pool->iu_storage =
+ dma_alloc_coherent(hostdata->dev,
+ pool->size * sizeof(*pool->iu_storage),
+ &pool->iu_token, 0);
+ if (!pool->iu_storage) {
+ kfree(pool->events);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < pool->size; ++i) {
+ struct srp_event_struct *evt = &pool->events[i];
+ memset(&evt->crq, 0x00, sizeof(evt->crq));
+ atomic_set(&evt->free, 1);
+ evt->crq.valid = 0x80;
+ evt->crq.IU_length = sizeof(*evt->xfer_iu);
+ evt->crq.IU_data_ptr = pool->iu_token +
+ sizeof(*evt->xfer_iu) * i;
+ evt->xfer_iu = pool->iu_storage + i;
+ evt->hostdata = hostdata;
+ }
+
+ return 0;
+}
+
+/**
+ * release_event_pool: - Frees memory of an event pool of a host
+ * @pool: event_pool to be released
+ * @hostdata: ibmvscsi_host_data who owns the even pool
+ *
+ * Returns zero on success.
+*/
+static void release_event_pool(struct event_pool *pool,
+ struct ibmvscsi_host_data *hostdata)
+{
+ int i, in_use = 0;
+ for (i = 0; i < pool->size; ++i)
+ if (atomic_read(&pool->events[i].free) != 1)
+ ++in_use;
+ if (in_use)
+ printk(KERN_WARNING
+ "ibmvscsi: releasing event pool with %d "
+ "events still in use?\n", in_use);
+ kfree(pool->events);
+ dma_free_coherent(hostdata->dev,
+ pool->size * sizeof(*pool->iu_storage),
+ pool->iu_storage, pool->iu_token);
+}
+
+/**
+ * valid_event_struct: - Determines if event is valid.
+ * @pool: event_pool that contains the event
+ * @evt: srp_event_struct to be checked for validity
+ *
+ * Returns zero if event is invalid, one otherwise.
+*/
+static int valid_event_struct(struct event_pool *pool,
+ struct srp_event_struct *evt)
+{
+ int index = evt - pool->events;
+ if (index < 0 || index >= pool->size) /* outside of bounds */
+ return 0;
+ if (evt != pool->events + index) /* unaligned */
+ return 0;
+ return 1;
+}
+
+/**
+ * ibmvscsi_free-event_struct: - Changes status of event to "free"
+ * @pool: event_pool that contains the event
+ * @evt: srp_event_struct to be modified
+ *
+*/
+static void free_event_struct(struct event_pool *pool,
+ struct srp_event_struct *evt)
+{
+ if (!valid_event_struct(pool, evt)) {
+ printk(KERN_ERR
+ "ibmvscsi: Freeing invalid event_struct %p "
+ "(not in pool %p)\n", evt, pool->events);
+ return;
+ }
+ if (atomic_inc_return(&evt->free) != 1) {
+ printk(KERN_ERR
+ "ibmvscsi: Freeing event_struct %p "
+ "which is not in use!\n", evt);
+ return;
+ }
+}
+
+/**
+ * get_evt_struct: - Gets the next free event in pool
+ * @pool: event_pool that contains the events to be searched
+ *
+ * Returns the next event in "free" state, and NULL if none are free.
+ * Note that no synchronization is done here, we assume the host_lock
+ * will syncrhonze things.
+*/
+static struct srp_event_struct *get_event_struct(struct event_pool *pool)
+{
+ int i;
+ int poolsize = pool->size;
+ int offset = pool->next;
+
+ for (i = 0; i < poolsize; i++) {
+ offset = (offset + 1) % poolsize;
+ if (!atomic_dec_if_positive(&pool->events[offset].free)) {
+ pool->next = offset;
+ return &pool->events[offset];
+ }
+ }
+
+ printk(KERN_ERR "ibmvscsi: found no event struct in pool!\n");
+ return NULL;
+}
+
+/**
+ * init_event_struct: Initialize fields in an event struct that are always
+ * required.
+ * @evt: The event
+ * @done: Routine to call when the event is responded to
+ * @format: SRP or MAD format
+ * @timeout: timeout value set in the CRQ
+ */
+static void init_event_struct(struct srp_event_struct *evt_struct,
+ void (*done) (struct srp_event_struct *),
+ u8 format,
+ int timeout)
+{
+ evt_struct->cmnd = NULL;
+ evt_struct->cmnd_done = NULL;
+ evt_struct->crq.format = format;
+ evt_struct->crq.timeout = timeout;
+ evt_struct->done = done;
+}
+
+/* ------------------------------------------------------------
+ * Routines for receiving SCSI responses from the hosting partition
+ */
+
+/**
+ * set_srp_direction: Set the fields in the srp related to data
+ * direction and number of buffers based on the direction in
+ * the scsi_cmnd and the number of buffers
+ */
+static void set_srp_direction(struct scsi_cmnd *cmd,
+ struct srp_cmd *srp_cmd,
+ int numbuf)
+{
+ if (numbuf == 0)
+ return;
+
+ if (numbuf == 1) {
+ if (cmd->sc_data_direction == DMA_TO_DEVICE)
+ srp_cmd->data_out_format = SRP_DIRECT_BUFFER;
+ else
+ srp_cmd->data_in_format = SRP_DIRECT_BUFFER;
+ } else {
+ if (cmd->sc_data_direction == DMA_TO_DEVICE) {
+ srp_cmd->data_out_format = SRP_INDIRECT_BUFFER;
+ srp_cmd->data_out_count = numbuf;
+ } else {
+ srp_cmd->data_in_format = SRP_INDIRECT_BUFFER;
+ srp_cmd->data_in_count = numbuf;
+ }
+ }
+}
+
+/**
+ * unmap_cmd_data: - Unmap data pointed in srp_cmd based on the format
+ * @cmd: srp_cmd whose additional_data member will be unmapped
+ * @dev: device for which the memory is mapped
+ *
+*/
+static void unmap_cmd_data(struct srp_cmd *cmd, struct device *dev)
+{
+ int i;
+
+ if ((cmd->data_out_format == SRP_NO_BUFFER) &&
+ (cmd->data_in_format == SRP_NO_BUFFER))
+ return;
+ else if ((cmd->data_out_format == SRP_DIRECT_BUFFER) ||
+ (cmd->data_in_format == SRP_DIRECT_BUFFER)) {
+ struct memory_descriptor *data =
+ (struct memory_descriptor *)cmd->additional_data;
+ dma_unmap_single(dev, data->virtual_address, data->length,
+ DMA_BIDIRECTIONAL);
+ } else {
+ struct indirect_descriptor *indirect =
+ (struct indirect_descriptor *)cmd->additional_data;
+ int num_mapped = indirect->head.length /
+ sizeof(indirect->list[0]);
+ for (i = 0; i < num_mapped; ++i) {
+ struct memory_descriptor *data = &indirect->list[i];
+ dma_unmap_single(dev,
+ data->virtual_address,
+ data->length, DMA_BIDIRECTIONAL);
+ }
+ }
+}
+
+/**
+ * map_sg_data: - Maps dma for a scatterlist and initializes decriptor fields
+ * @cmd: Scsi_Cmnd with the scatterlist
+ * @srp_cmd: srp_cmd that contains the memory descriptor
+ * @dev: device for which to map dma memory
+ *
+ * Called by map_data_for_srp_cmd() when building srp cmd from scsi cmd.
+ * Returns 1 on success.
+*/
+static int map_sg_data(struct scsi_cmnd *cmd,
+ struct srp_cmd *srp_cmd, struct device *dev)
+{
+
+ int i, sg_mapped;
+ u64 total_length = 0;
+ struct scatterlist *sg = cmd->request_buffer;
+ struct memory_descriptor *data =
+ (struct memory_descriptor *)srp_cmd->additional_data;
+ struct indirect_descriptor *indirect =
+ (struct indirect_descriptor *)data;
+
+ sg_mapped = dma_map_sg(dev, sg, cmd->use_sg, DMA_BIDIRECTIONAL);
+
+ if (sg_mapped == 0)
+ return 0;
+
+ set_srp_direction(cmd, srp_cmd, sg_mapped);
+
+ /* special case; we can use a single direct descriptor */
+ if (sg_mapped == 1) {
+ data->virtual_address = sg_dma_address(&sg[0]);
+ data->length = sg_dma_len(&sg[0]);
+ data->memory_handle = 0;
+ return 1;
+ }
+
+ if (sg_mapped > MAX_INDIRECT_BUFS) {
+ printk(KERN_ERR
+ "ibmvscsi: More than %d mapped sg entries, got %d\n",
+ MAX_INDIRECT_BUFS, sg_mapped);
+ return 0;
+ }
+
+ indirect->head.virtual_address = 0;
+ indirect->head.length = sg_mapped * sizeof(indirect->list[0]);
+ indirect->head.memory_handle = 0;
+ for (i = 0; i < sg_mapped; ++i) {
+ struct memory_descriptor *descr = &indirect->list[i];
+ struct scatterlist *sg_entry = &sg[i];
+ descr->virtual_address = sg_dma_address(sg_entry);
+ descr->length = sg_dma_len(sg_entry);
+ descr->memory_handle = 0;
+ total_length += sg_dma_len(sg_entry);
+ }
+ indirect->total_length = total_length;
+
+ return 1;
+}
+
+/**
+ * map_single_data: - Maps memory and initializes memory decriptor fields
+ * @cmd: struct scsi_cmnd with the memory to be mapped
+ * @srp_cmd: srp_cmd that contains the memory descriptor
+ * @dev: device for which to map dma memory
+ *
+ * Called by map_data_for_srp_cmd() when building srp cmd from scsi cmd.
+ * Returns 1 on success.
+*/
+static int map_single_data(struct scsi_cmnd *cmd,
+ struct srp_cmd *srp_cmd, struct device *dev)
+{
+ struct memory_descriptor *data =
+ (struct memory_descriptor *)srp_cmd->additional_data;
+
+ data->virtual_address =
+ dma_map_single(dev, cmd->request_buffer,
+ cmd->request_bufflen,
+ DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(data->virtual_address)) {
+ printk(KERN_ERR
+ "ibmvscsi: Unable to map request_buffer for command!\n");
+ return 0;
+ }
+ data->length = cmd->request_bufflen;
+ data->memory_handle = 0;
+
+ set_srp_direction(cmd, srp_cmd, 1);
+
+ return 1;
+}
+
+/**
+ * map_data_for_srp_cmd: - Calls functions to map data for srp cmds
+ * @cmd: struct scsi_cmnd with the memory to be mapped
+ * @srp_cmd: srp_cmd that contains the memory descriptor
+ * @dev: dma device for which to map dma memory
+ *
+ * Called by scsi_cmd_to_srp_cmd() when converting scsi cmds to srp cmds
+ * Returns 1 on success.
+*/
+static int map_data_for_srp_cmd(struct scsi_cmnd *cmd,
+ struct srp_cmd *srp_cmd, struct device *dev)
+{
+ switch (cmd->sc_data_direction) {
+ case DMA_FROM_DEVICE:
+ case DMA_TO_DEVICE:
+ break;
+ case DMA_NONE:
+ return 1;
+ case DMA_BIDIRECTIONAL:
+ printk(KERN_ERR
+ "ibmvscsi: Can't map DMA_BIDIRECTIONAL to read/write\n");
+ return 0;
+ default:
+ printk(KERN_ERR
+ "ibmvscsi: Unknown data direction 0x%02x; can't map!\n",
+ cmd->sc_data_direction);
+ return 0;
+ }
+
+ if (!cmd->request_buffer)
+ return 1;
+ if (cmd->use_sg)
+ return map_sg_data(cmd, srp_cmd, dev);
+ return map_single_data(cmd, srp_cmd, dev);
+}
+
+/* ------------------------------------------------------------
+ * Routines for sending and receiving SRPs
+ */
+/**
+ * ibmvscsi_send_srp_event: - Transforms event to u64 array and calls send_crq()
+ * @evt_struct: evt_struct to be sent
+ * @hostdata: ibmvscsi_host_data of host
+ *
+ * Returns the value returned from ibmvscsi_send_crq(). (Zero for success)
+ * Note that this routine assumes that host_lock is held for synchronization
+*/
+static int ibmvscsi_send_srp_event(struct srp_event_struct *evt_struct,
+ struct ibmvscsi_host_data *hostdata)
+{
+ struct scsi_cmnd *cmnd = evt_struct->cmnd;
+ u64 *crq_as_u64 = (u64 *) &evt_struct->crq;
+ int rc;
+
+ /* If we have exhausted our request limit, just fail this request.
+ * Note that there are rare cases involving driver generated requests
+ * (such as task management requests) that the mid layer may think we
+ * can handle more requests (can_queue) when we actually can't
+ */
+ if ((evt_struct->crq.format == VIOSRP_SRP_FORMAT) &&
+ (atomic_dec_if_positive(&hostdata->request_limit) < 0)) {
+ /* See if the adapter is disabled */
+ if (atomic_read(&hostdata->request_limit) < 0) {
+ if (cmnd)
+ cmnd->result = DID_ERROR << 16;
+ if (evt_struct->cmnd_done)
+ evt_struct->cmnd_done(cmnd);
+ unmap_cmd_data(&evt_struct->iu.srp.cmd,
+ hostdata->dev);
+ free_event_struct(&hostdata->pool, evt_struct);
+ return 0;
+ } else {
+ printk("ibmvscsi: Warning, request_limit exceeded\n");
+ unmap_cmd_data(&evt_struct->iu.srp.cmd,
+ hostdata->dev);
+ free_event_struct(&hostdata->pool, evt_struct);
+ return SCSI_MLQUEUE_HOST_BUSY;
+ }
+ }
+
+ /* Copy the IU into the transfer area */
+ *evt_struct->xfer_iu = evt_struct->iu;
+ evt_struct->xfer_iu->srp.generic.tag = (u64)evt_struct;
+
+ /* Add this to the sent list. We need to do this
+ * before we actually send
+ * in case it comes back REALLY fast
+ */
+ list_add_tail(&evt_struct->list, &hostdata->sent);
+
+ if ((rc =
+ ibmvscsi_send_crq(hostdata, crq_as_u64[0], crq_as_u64[1])) != 0) {
+ list_del(&evt_struct->list);
+
+ cmnd = evt_struct->cmnd;
+ printk(KERN_ERR "ibmvscsi: failed to send event struct rc %d\n",
+ rc);
+ unmap_cmd_data(&evt_struct->iu.srp.cmd, hostdata->dev);
+ free_event_struct(&hostdata->pool, evt_struct);
+ if (cmnd)
+ cmnd->result = DID_ERROR << 16;
+ if (evt_struct->cmnd_done)
+ evt_struct->cmnd_done(cmnd);
+ }
+
+ return 0;
+}
+
+/**
+ * handle_cmd_rsp: - Handle responses from commands
+ * @evt_struct: srp_event_struct to be handled
+ *
+ * Used as a callback by when sending scsi cmds.
+ * Gets called by ibmvscsi_handle_crq()
+*/
+static void handle_cmd_rsp(struct srp_event_struct *evt_struct)
+{
+ struct srp_rsp *rsp = &evt_struct->xfer_iu->srp.rsp;
+ struct scsi_cmnd *cmnd = evt_struct->cmnd;
+
+ if (cmnd) {
+ cmnd->result = rsp->status;
+ if (((cmnd->result >> 1) & 0x1f) == CHECK_CONDITION)
+ memcpy(cmnd->sense_buffer,
+ rsp->sense_and_response_data,
+ rsp->sense_data_list_length);
+ unmap_cmd_data(&evt_struct->iu.srp.cmd,
+ evt_struct->hostdata->dev);
+
+ if (rsp->doover)
+ cmnd->resid = rsp->data_out_residual_count;
+ else if (rsp->diover)
+ cmnd->resid = rsp->data_in_residual_count;
+ }
+
+ if (evt_struct->cmnd_done)
+ evt_struct->cmnd_done(cmnd);
+}
+
+/**
+ * lun_from_dev: - Returns the lun of the scsi device
+ * @dev: struct scsi_device
+ *
+*/
+static inline u16 lun_from_dev(struct scsi_device *dev)
+{
+ return (0x2 << 14) | (dev->id << 8) | (dev->channel << 5) | dev->lun;
+}
+
+/**
+ * ibmvscsi_queue: - The queuecommand function of the scsi template
+ * @cmd: struct scsi_cmnd to be executed
+ * @done: Callback function to be called when cmd is completed
+*/
+static int ibmvscsi_queuecommand(struct scsi_cmnd *cmnd,
+ void (*done) (struct scsi_cmnd *))
+{
+ struct srp_cmd *srp_cmd;
+ struct srp_event_struct *evt_struct;
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)&cmnd->device->host->hostdata;
+ u16 lun = lun_from_dev(cmnd->device);
+
+ evt_struct = get_event_struct(&hostdata->pool);
+ if (!evt_struct)
+ return SCSI_MLQUEUE_HOST_BUSY;
+
+ init_event_struct(evt_struct,
+ handle_cmd_rsp,
+ VIOSRP_SRP_FORMAT,
+ cmnd->timeout);
+
+ evt_struct->cmnd = cmnd;
+ evt_struct->cmnd_done = done;
+
+ /* Set up the actual SRP IU */
+ srp_cmd = &evt_struct->iu.srp.cmd;
+ memset(srp_cmd, 0x00, sizeof(*srp_cmd));
+ srp_cmd->type = SRP_CMD_TYPE;
+ memcpy(srp_cmd->cdb, cmnd->cmnd, sizeof(cmnd->cmnd));
+ srp_cmd->lun = ((u64) lun) << 48;
+
+ if (!map_data_for_srp_cmd(cmnd, srp_cmd, hostdata->dev)) {
+ printk(KERN_ERR "ibmvscsi: couldn't convert cmd to srp_cmd\n");
+ free_event_struct(&hostdata->pool, evt_struct);
+ return SCSI_MLQUEUE_HOST_BUSY;
+ }
+
+ /* Fix up dma address of the buffer itself */
+ if ((srp_cmd->data_out_format == SRP_INDIRECT_BUFFER) ||
+ (srp_cmd->data_in_format == SRP_INDIRECT_BUFFER)) {
+ struct indirect_descriptor *indirect =
+ (struct indirect_descriptor *)srp_cmd->additional_data;
+ indirect->head.virtual_address = evt_struct->crq.IU_data_ptr +
+ offsetof(struct srp_cmd, additional_data) +
+ offsetof(struct indirect_descriptor, list);
+ }
+
+ return ibmvscsi_send_srp_event(evt_struct, hostdata);
+}
+
+/* ------------------------------------------------------------
+ * Routines for driver initialization
+ */
+/**
+ * adapter_info_rsp: - Handle response to MAD adapter info request
+ * @evt_struct: srp_event_struct with the response
+ *
+ * Used as a "done" callback by when sending adapter_info. Gets called
+ * by ibmvscsi_handle_crq()
+*/
+static void adapter_info_rsp(struct srp_event_struct *evt_struct)
+{
+ struct ibmvscsi_host_data *hostdata = evt_struct->hostdata;
+ dma_unmap_single(hostdata->dev,
+ evt_struct->iu.mad.adapter_info.buffer,
+ evt_struct->iu.mad.adapter_info.common.length,
+ DMA_BIDIRECTIONAL);
+
+ if (evt_struct->xfer_iu->mad.adapter_info.common.status) {
+ printk("ibmvscsi: error %d getting adapter info\n",
+ evt_struct->xfer_iu->mad.adapter_info.common.status);
+ } else {
+ printk("ibmvscsi: host srp version: %s, "
+ "host partition %s (%d), OS %d\n",
+ hostdata->madapter_info.srp_version,
+ hostdata->madapter_info.partition_name,
+ hostdata->madapter_info.partition_number,
+ hostdata->madapter_info.os_type);
+ }
+}
+
+/**
+ * send_mad_adapter_info: - Sends the mad adapter info request
+ * and stores the result so it can be retrieved with
+ * sysfs. We COULD consider causing a failure if the
+ * returned SRP version doesn't match ours.
+ * @hostdata: ibmvscsi_host_data of host
+ *
+ * Returns zero if successful.
+*/
+static void send_mad_adapter_info(struct ibmvscsi_host_data *hostdata)
+{
+ struct viosrp_adapter_info *req;
+ struct srp_event_struct *evt_struct;
+
+ memset(&hostdata->madapter_info, 0x00, sizeof(hostdata->madapter_info));
+
+ evt_struct = get_event_struct(&hostdata->pool);
+ if (!evt_struct) {
+ printk(KERN_ERR "ibmvscsi: couldn't allocate an event "
+ "for ADAPTER_INFO_REQ!\n");
+ return;
+ }
+
+ init_event_struct(evt_struct,
+ adapter_info_rsp,
+ VIOSRP_MAD_FORMAT,
+ init_timeout * HZ);
+
+ req = &evt_struct->iu.mad.adapter_info;
+ memset(req, 0x00, sizeof(*req));
+
+ req->common.type = VIOSRP_ADAPTER_INFO_TYPE;
+ req->common.length = sizeof(hostdata->madapter_info);
+ req->buffer = dma_map_single(hostdata->dev,
+ &hostdata->madapter_info,
+ sizeof(hostdata->madapter_info),
+ DMA_BIDIRECTIONAL);
+
+ if (dma_mapping_error(req->buffer)) {
+ printk(KERN_ERR
+ "ibmvscsi: Unable to map request_buffer "
+ "for adapter_info!\n");
+ free_event_struct(&hostdata->pool, evt_struct);
+ return;
+ }
+
+ if (ibmvscsi_send_srp_event(evt_struct, hostdata))
+ printk(KERN_ERR "ibmvscsi: couldn't send ADAPTER_INFO_REQ!\n");
+};
+
+/**
+ * login_rsp: - Handle response to SRP login request
+ * @evt_struct: srp_event_struct with the response
+ *
+ * Used as a "done" callback by when sending srp_login. Gets called
+ * by ibmvscsi_handle_crq()
+*/
+static void login_rsp(struct srp_event_struct *evt_struct)
+{
+ struct ibmvscsi_host_data *hostdata = evt_struct->hostdata;
+ switch (evt_struct->xfer_iu->srp.generic.type) {
+ case SRP_LOGIN_RSP_TYPE: /* it worked! */
+ break;
+ case SRP_LOGIN_REJ_TYPE: /* refused! */
+ printk(KERN_INFO "ibmvscsi: SRP_LOGIN_REQ rejected\n");
+ /* Login failed. */
+ atomic_set(&hostdata->request_limit, -1);
+ return;
+ default:
+ printk(KERN_ERR
+ "ibmvscsi: Invalid login response typecode 0x%02x!\n",
+ evt_struct->xfer_iu->srp.generic.type);
+ /* Login failed. */
+ atomic_set(&hostdata->request_limit, -1);
+ return;
+ }
+
+ printk(KERN_INFO "ibmvscsi: SRP_LOGIN succeeded\n");
+
+ if (evt_struct->xfer_iu->srp.login_rsp.request_limit_delta >
+ (max_requests - 2))
+ evt_struct->xfer_iu->srp.login_rsp.request_limit_delta =
+ max_requests - 2;
+
+ /* Now we know what the real request-limit is */
+ atomic_set(&hostdata->request_limit,
+ evt_struct->xfer_iu->srp.login_rsp.request_limit_delta);
+
+ hostdata->host->can_queue =
+ evt_struct->xfer_iu->srp.login_rsp.request_limit_delta - 2;
+
+ if (hostdata->host->can_queue < 1) {
+ printk(KERN_ERR "ibmvscsi: Invalid request_limit_delta\n");
+ return;
+ }
+
+ send_mad_adapter_info(hostdata);
+ return;
+}
+
+/**
+ * send_srp_login: - Sends the srp login
+ * @hostdata: ibmvscsi_host_data of host
+ *
+ * Returns zero if successful.
+*/
+static int send_srp_login(struct ibmvscsi_host_data *hostdata)
+{
+ int rc;
+ unsigned long flags;
+ struct srp_login_req *login;
+ struct srp_event_struct *evt_struct = get_event_struct(&hostdata->pool);
+ if (!evt_struct) {
+ printk(KERN_ERR
+ "ibmvscsi: couldn't allocate an event for login req!\n");
+ return FAILED;
+ }
+
+ init_event_struct(evt_struct,
+ login_rsp,
+ VIOSRP_SRP_FORMAT,
+ init_timeout * HZ);
+
+ login = &evt_struct->iu.srp.login_req;
+ login->type = SRP_LOGIN_REQ_TYPE;
+ login->max_requested_initiator_to_target_iulen = sizeof(union srp_iu);
+ login->required_buffer_formats = 0x0006;
+
+ /* Start out with a request limit of 1, since this is negotiated in
+ * the login request we are just sending
+ */
+ atomic_set(&hostdata->request_limit, 1);
+
+ spin_lock_irqsave(hostdata->host->host_lock, flags);
+ rc = ibmvscsi_send_srp_event(evt_struct, hostdata);
+ spin_unlock_irqrestore(hostdata->host->host_lock, flags);
+ return rc;
+};
+
+/**
+ * sync_completion: Signal that a synchronous command has completed
+ * Note that after returning from this call, the evt_struct is freed.
+ * the caller waiting on this completion shouldn't touch the evt_struct
+ * again.
+ */
+static void sync_completion(struct srp_event_struct *evt_struct)
+{
+ complete(&evt_struct->comp);
+}
+
+/**
+ * ibmvscsi_abort: Abort a command...from scsi host template
+ * send this over to the server and wait synchronously for the response
+ */
+static int ibmvscsi_eh_abort_handler(struct scsi_cmnd *cmd)
+{
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)cmd->device->host->hostdata;
+ struct srp_tsk_mgmt *tsk_mgmt;
+ struct srp_event_struct *evt;
+ struct srp_event_struct *tmp_evt, *found_evt;
+ u16 lun = lun_from_dev(cmd->device);
+
+ /* First, find this command in our sent list so we can figure
+ * out the correct tag
+ */
+ found_evt = NULL;
+ list_for_each_entry(tmp_evt, &hostdata->sent, list) {
+ if (tmp_evt->cmnd == cmd) {
+ found_evt = tmp_evt;
+ break;
+ }
+ }
+
+ if (!found_evt)
+ return FAILED;
+
+ evt = get_event_struct(&hostdata->pool);
+ if (evt == NULL) {
+ printk(KERN_ERR "ibmvscsi: failed to allocate abort event\n");
+ return FAILED;
+ }
+
+ init_event_struct(evt,
+ sync_completion,
+ VIOSRP_SRP_FORMAT,
+ init_timeout * HZ);
+
+ tsk_mgmt = &evt->iu.srp.tsk_mgmt;
+
+ /* Set up an abort SRP command */
+ memset(tsk_mgmt, 0x00, sizeof(*tsk_mgmt));
+ tsk_mgmt->type = SRP_TSK_MGMT_TYPE;
+ tsk_mgmt->lun = ((u64) lun) << 48;
+ tsk_mgmt->task_mgmt_flags = 0x01; /* ABORT TASK */
+ tsk_mgmt->managed_task_tag = (u64) found_evt;
+
+ printk(KERN_INFO "ibmvscsi: aborting command. lun 0x%lx, tag 0x%lx\n",
+ tsk_mgmt->lun, tsk_mgmt->managed_task_tag);
+
+ init_completion(&evt->comp);
+ if (ibmvscsi_send_srp_event(evt, hostdata) != 0) {
+ printk(KERN_ERR "ibmvscsi: failed to send abort() event\n");
+ return FAILED;
+ }
+
+ spin_unlock_irq(hostdata->host->host_lock);
+ wait_for_completion(&evt->comp);
+ spin_lock_irq(hostdata->host->host_lock);
+
+ /* Because we dropped the spinlock above, it's possible
+ * The event is no longer in our list. Make sure it didn't
+ * complete while we were aborting
+ */
+ found_evt = NULL;
+ list_for_each_entry(tmp_evt, &hostdata->sent, list) {
+ if (tmp_evt->cmnd == cmd) {
+ found_evt = tmp_evt;
+ break;
+ }
+ }
+
+ printk(KERN_INFO
+ "ibmvscsi: successfully aborted task tag 0x%lx\n",
+ tsk_mgmt->managed_task_tag);
+
+ if (found_evt == NULL)
+ return SUCCESS;
+
+ cmd->result = (DID_ABORT << 16);
+ list_del(&found_evt->list);
+ unmap_cmd_data(&found_evt->iu.srp.cmd, found_evt->hostdata->dev);
+ free_event_struct(&found_evt->hostdata->pool, found_evt);
+ atomic_inc(&hostdata->request_limit);
+ return SUCCESS;
+}
+
+/**
+ * ibmvscsi_eh_device_reset_handler: Reset a single LUN...from scsi host
+ * template send this over to the server and wait synchronously for the
+ * response
+ */
+static int ibmvscsi_eh_device_reset_handler(struct scsi_cmnd *cmd)
+{
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)cmd->device->host->hostdata;
+
+ struct srp_tsk_mgmt *tsk_mgmt;
+ struct srp_event_struct *evt;
+ struct srp_event_struct *tmp_evt, *pos;
+ u16 lun = lun_from_dev(cmd->device);
+
+ evt = get_event_struct(&hostdata->pool);
+ if (evt == NULL) {
+ printk(KERN_ERR "ibmvscsi: failed to allocate reset event\n");
+ return FAILED;
+ }
+
+ init_event_struct(evt,
+ sync_completion,
+ VIOSRP_SRP_FORMAT,
+ init_timeout * HZ);
+
+ tsk_mgmt = &evt->iu.srp.tsk_mgmt;
+
+ /* Set up a lun reset SRP command */
+ memset(tsk_mgmt, 0x00, sizeof(*tsk_mgmt));
+ tsk_mgmt->type = SRP_TSK_MGMT_TYPE;
+ tsk_mgmt->lun = ((u64) lun) << 48;
+ tsk_mgmt->task_mgmt_flags = 0x08; /* LUN RESET */
+
+ printk(KERN_INFO "ibmvscsi: resetting device. lun 0x%lx\n",
+ tsk_mgmt->lun);
+
+ init_completion(&evt->comp);
+ if (ibmvscsi_send_srp_event(evt, hostdata) != 0) {
+ printk(KERN_ERR "ibmvscsi: failed to send reset event\n");
+ return FAILED;
+ }
+
+ spin_unlock_irq(hostdata->host->host_lock);
+ wait_for_completion(&evt->comp);
+ spin_lock_irq(hostdata->host->host_lock);
+
+ /* We need to find all commands for this LUN that have not yet been
+ * responded to, and fail them with DID_RESET
+ */
+ list_for_each_entry_safe(tmp_evt, pos, &hostdata->sent, list) {
+ if ((tmp_evt->cmnd) && (tmp_evt->cmnd->device == cmd->device)) {
+ if (tmp_evt->cmnd)
+ tmp_evt->cmnd->result = (DID_RESET << 16);
+ list_del(&tmp_evt->list);
+ unmap_cmd_data(&tmp_evt->iu.srp.cmd, tmp_evt->hostdata->dev);
+ free_event_struct(&tmp_evt->hostdata->pool,
+ tmp_evt);
+ atomic_inc(&hostdata->request_limit);
+ if (tmp_evt->cmnd_done)
+ tmp_evt->cmnd_done(tmp_evt->cmnd);
+ else if (tmp_evt->done)
+ tmp_evt->done(tmp_evt);
+ }
+ }
+ return SUCCESS;
+}
+
+/**
+ * purge_requests: Our virtual adapter just shut down. purge any sent requests
+ * @hostdata: the adapter
+ */
+static void purge_requests(struct ibmvscsi_host_data *hostdata)
+{
+ struct srp_event_struct *tmp_evt, *pos;
+ unsigned long flags;
+
+ spin_lock_irqsave(hostdata->host->host_lock, flags);
+ list_for_each_entry_safe(tmp_evt, pos, &hostdata->sent, list) {
+ list_del(&tmp_evt->list);
+ if (tmp_evt->cmnd) {
+ tmp_evt->cmnd->result = (DID_ERROR << 16);
+ unmap_cmd_data(&tmp_evt->iu.srp.cmd,
+ tmp_evt->hostdata->dev);
+ if (tmp_evt->cmnd_done)
+ tmp_evt->cmnd_done(tmp_evt->cmnd);
+ } else {
+ if (tmp_evt->done) {
+ tmp_evt->done(tmp_evt);
+ }
+ }
+ free_event_struct(&tmp_evt->hostdata->pool, tmp_evt);
+ }
+ spin_unlock_irqrestore(hostdata->host->host_lock, flags);
+}
+
+/**
+ * ibmvscsi_handle_crq: - Handles and frees received events in the CRQ
+ * @crq: Command/Response queue
+ * @hostdata: ibmvscsi_host_data of host
+ *
+*/
+void ibmvscsi_handle_crq(struct viosrp_crq *crq,
+ struct ibmvscsi_host_data *hostdata)
+{
+ unsigned long flags;
+ struct srp_event_struct *evt_struct =
+ (struct srp_event_struct *)crq->IU_data_ptr;
+ switch (crq->valid) {
+ case 0xC0: /* initialization */
+ switch (crq->format) {
+ case 0x01: /* Initialization message */
+ printk(KERN_INFO "ibmvscsi: partner initialized\n");
+ /* Send back a response */
+ if (ibmvscsi_send_crq(hostdata,
+ 0xC002000000000000LL, 0) == 0) {
+ /* Now login */
+ send_srp_login(hostdata);
+ } else {
+ printk(KERN_ERR
+ "ibmvscsi: Unable to send init rsp\n");
+ }
+
+ break;
+ case 0x02: /* Initialization response */
+ printk(KERN_INFO
+ "ibmvscsi: partner initialization complete\n");
+
+ /* Now login */
+ send_srp_login(hostdata);
+ break;
+ default:
+ printk(KERN_ERR "ibmvscsi: unknown crq message type\n");
+ }
+ return;
+ case 0xFF: /* Hypervisor telling us the connection is closed */
+ printk(KERN_INFO "ibmvscsi: Virtual adapter failed!\n");
+
+ atomic_set(&hostdata->request_limit, -1);
+ purge_requests(hostdata);
+ ibmvscsi_reset_crq_queue(&hostdata->queue, hostdata);
+ return;
+ case 0x80: /* real payload */
+ break;
+ default:
+ printk(KERN_ERR
+ "ibmvscsi: got an invalid message type 0x%02x\n",
+ crq->valid);
+ return;
+ }
+
+ /* The only kind of payload CRQs we should get are responses to
+ * things we send. Make sure this response is to something we
+ * actually sent
+ */
+ if (!valid_event_struct(&hostdata->pool, evt_struct)) {
+ printk(KERN_ERR
+ "ibmvscsi: returned correlation_token 0x%p is invalid!\n",
+ (void *)crq->IU_data_ptr);
+ return;
+ }
+
+ if (crq->format == VIOSRP_SRP_FORMAT)
+ atomic_add(evt_struct->xfer_iu->srp.rsp.request_limit_delta,
+ &hostdata->request_limit);
+
+ if (evt_struct->done)
+ evt_struct->done(evt_struct);
+ else
+ printk(KERN_ERR
+ "ibmvscsi: returned done() is NULL; not running it!\n");
+
+ /*
+ * Lock the host_lock before messing with these structures, since we
+ * are running in a task context
+ */
+ spin_lock_irqsave(evt_struct->hostdata->host->host_lock, flags);
+ list_del(&evt_struct->list);
+ free_event_struct(&evt_struct->hostdata->pool, evt_struct);
+ spin_unlock_irqrestore(evt_struct->hostdata->host->host_lock, flags);
+}
+
+/**
+ * ibmvscsi_get_host_config: Send the command to the server to get host
+ * configuration data. The data is opaque to us.
+ */
+static int ibmvscsi_do_host_config(struct ibmvscsi_host_data *hostdata,
+ unsigned char *buffer, int length)
+{
+ struct viosrp_host_config *host_config;
+ struct srp_event_struct *evt_struct;
+ int rc;
+
+ evt_struct = get_event_struct(&hostdata->pool);
+ if (!evt_struct) {
+ printk(KERN_ERR
+ "ibmvscsi: could't allocate event for HOST_CONFIG!\n");
+ return -1;
+ }
+
+ init_event_struct(evt_struct,
+ sync_completion,
+ VIOSRP_MAD_FORMAT,
+ init_timeout * HZ);
+
+ host_config = &evt_struct->iu.mad.host_config;
+
+ /* Set up a lun reset SRP command */
+ memset(host_config, 0x00, sizeof(*host_config));
+ host_config->common.type = VIOSRP_HOST_CONFIG_TYPE;
+ host_config->common.length = length;
+ host_config->buffer = dma_map_single(hostdata->dev, buffer, length,
+ DMA_BIDIRECTIONAL);
+
+ if (dma_mapping_error(host_config->buffer)) {
+ printk(KERN_ERR
+ "ibmvscsi: dma_mapping error " "getting host config\n");
+ free_event_struct(&hostdata->pool, evt_struct);
+ return -1;
+ }
+
+ init_completion(&evt_struct->comp);
+ rc = ibmvscsi_send_srp_event(evt_struct, hostdata);
+ if (rc == 0) {
+ wait_for_completion(&evt_struct->comp);
+ dma_unmap_single(hostdata->dev, host_config->buffer,
+ length, DMA_BIDIRECTIONAL);
+ }
+
+ return rc;
+}
+
+/* ------------------------------------------------------------
+ * sysfs attributes
+ */
+static ssize_t show_host_srp_version(struct class_device *class_dev, char *buf)
+{
+ struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)shost->hostdata;
+ int len;
+
+ len = snprintf(buf, PAGE_SIZE, "%s\n",
+ hostdata->madapter_info.srp_version);
+ return len;
+}
+
+static struct class_device_attribute ibmvscsi_host_srp_version = {
+ .attr = {
+ .name = "srp_version",
+ .mode = S_IRUGO,
+ },
+ .show = show_host_srp_version,
+};
+
+static ssize_t show_host_partition_name(struct class_device *class_dev,
+ char *buf)
+{
+ struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)shost->hostdata;
+ int len;
+
+ len = snprintf(buf, PAGE_SIZE, "%s\n",
+ hostdata->madapter_info.partition_name);
+ return len;
+}
+
+static struct class_device_attribute ibmvscsi_host_partition_name = {
+ .attr = {
+ .name = "partition_name",
+ .mode = S_IRUGO,
+ },
+ .show = show_host_partition_name,
+};
+
+static ssize_t show_host_partition_number(struct class_device *class_dev,
+ char *buf)
+{
+ struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)shost->hostdata;
+ int len;
+
+ len = snprintf(buf, PAGE_SIZE, "%d\n",
+ hostdata->madapter_info.partition_number);
+ return len;
+}
+
+static struct class_device_attribute ibmvscsi_host_partition_number = {
+ .attr = {
+ .name = "partition_number",
+ .mode = S_IRUGO,
+ },
+ .show = show_host_partition_number,
+};
+
+static ssize_t show_host_mad_version(struct class_device *class_dev, char *buf)
+{
+ struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)shost->hostdata;
+ int len;
+
+ len = snprintf(buf, PAGE_SIZE, "%d\n",
+ hostdata->madapter_info.mad_version);
+ return len;
+}
+
+static struct class_device_attribute ibmvscsi_host_mad_version = {
+ .attr = {
+ .name = "mad_version",
+ .mode = S_IRUGO,
+ },
+ .show = show_host_mad_version,
+};
+
+static ssize_t show_host_os_type(struct class_device *class_dev, char *buf)
+{
+ struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)shost->hostdata;
+ int len;
+
+ len = snprintf(buf, PAGE_SIZE, "%d\n", hostdata->madapter_info.os_type);
+ return len;
+}
+
+static struct class_device_attribute ibmvscsi_host_os_type = {
+ .attr = {
+ .name = "os_type",
+ .mode = S_IRUGO,
+ },
+ .show = show_host_os_type,
+};
+
+static ssize_t show_host_config(struct class_device *class_dev, char *buf)
+{
+ struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)shost->hostdata;
+
+ /* returns null-terminated host config data */
+ if (ibmvscsi_do_host_config(hostdata, buf, PAGE_SIZE) == 0)
+ return strlen(buf);
+ else
+ return 0;
+}
+
+static struct class_device_attribute ibmvscsi_host_config = {
+ .attr = {
+ .name = "config",
+ .mode = S_IRUGO,
+ },
+ .show = show_host_config,
+};
+
+static struct class_device_attribute *ibmvscsi_attrs[] = {
+ &ibmvscsi_host_srp_version,
+ &ibmvscsi_host_partition_name,
+ &ibmvscsi_host_partition_number,
+ &ibmvscsi_host_mad_version,
+ &ibmvscsi_host_os_type,
+ &ibmvscsi_host_config,
+ NULL
+};
+
+/* ------------------------------------------------------------
+ * SCSI driver registration
+ */
+static struct scsi_host_template driver_template = {
+ .module = THIS_MODULE,
+ .name = "IBM POWER Virtual SCSI Adapter " IBMVSCSI_VERSION,
+ .proc_name = "ibmvscsi",
+ .queuecommand = ibmvscsi_queuecommand,
+ .eh_abort_handler = ibmvscsi_eh_abort_handler,
+ .eh_device_reset_handler = ibmvscsi_eh_device_reset_handler,
+ .cmd_per_lun = 16,
+ .can_queue = 1, /* Updated after SRP_LOGIN */
+ .this_id = -1,
+ .sg_tablesize = MAX_INDIRECT_BUFS,
+ .use_clustering = ENABLE_CLUSTERING,
+ .shost_attrs = ibmvscsi_attrs,
+};
+
+/**
+ * Called by bus code for each adapter
+ */
+static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id *id)
+{
+ struct ibmvscsi_host_data *hostdata;
+ struct Scsi_Host *host;
+ struct device *dev = &vdev->dev;
+ unsigned long wait_switch = 0;
+
+ vdev->dev.driver_data = NULL;
+
+ host = scsi_host_alloc(&driver_template, sizeof(*hostdata));
+ if (!host) {
+ printk(KERN_ERR "ibmvscsi: couldn't allocate host data\n");
+ goto scsi_host_alloc_failed;
+ }
+
+ hostdata = (struct ibmvscsi_host_data *)host->hostdata;
+ memset(hostdata, 0x00, sizeof(*hostdata));
+ INIT_LIST_HEAD(&hostdata->sent);
+ hostdata->host = host;
+ hostdata->dev = dev;
+ atomic_set(&hostdata->request_limit, -1);
+
+ if (ibmvscsi_init_crq_queue(&hostdata->queue, hostdata,
+ max_requests) != 0) {
+ printk(KERN_ERR "ibmvscsi: couldn't initialize crq\n");
+ goto init_crq_failed;
+ }
+ if (initialize_event_pool(&hostdata->pool, max_requests, hostdata) != 0) {
+ printk(KERN_ERR "ibmvscsi: couldn't initialize event pool\n");
+ goto init_pool_failed;
+ }
+
+ host->max_lun = 8;
+ host->max_id = max_id;
+ host->max_channel = max_channel;
+
+ if (scsi_add_host(hostdata->host, hostdata->dev))
+ goto add_host_failed;
+
+ /* Try to send an initialization message. Note that this is allowed
+ * to fail if the other end is not acive. In that case we don't
+ * want to scan
+ */
+ if (ibmvscsi_send_crq(hostdata, 0xC001000000000000LL, 0) == 0) {
+ /*
+ * Wait around max init_timeout secs for the adapter to finish
+ * initializing. When we are done initializing, we will have a
+ * valid request_limit. We don't want Linux scanning before
+ * we are ready.
+ */
+ for (wait_switch = jiffies + (init_timeout * HZ);
+ time_before(jiffies, wait_switch) &&
+ atomic_read(&hostdata->request_limit) < 0;) {
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 100);
+ }
+
+ /* if we now have a valid request_limit, initiate a scan */
+ if (atomic_read(&hostdata->request_limit) > 0)
+ scsi_scan_host(host);
+ }
+
+ vdev->dev.driver_data = hostdata;
+ return 0;
+
+ add_host_failed:
+ release_event_pool(&hostdata->pool, hostdata);
+ init_pool_failed:
+ ibmvscsi_release_crq_queue(&hostdata->queue, hostdata, max_requests);
+ init_crq_failed:
+ scsi_host_put(host);
+ scsi_host_alloc_failed:
+ return -1;
+}
+
+static int ibmvscsi_remove(struct vio_dev *vdev)
+{
+ struct ibmvscsi_host_data *hostdata = vdev->dev.driver_data;
+ release_event_pool(&hostdata->pool, hostdata);
+ ibmvscsi_release_crq_queue(&hostdata->queue, hostdata,
+ max_requests);
+
+ scsi_remove_host(hostdata->host);
+ scsi_host_put(hostdata->host);
+
+ return 0;
+}
+
+/**
+ * ibmvscsi_device_table: Used by vio.c to match devices in the device tree we
+ * support.
+ */
+static struct vio_device_id ibmvscsi_device_table[] __devinitdata = {
+ {"vscsi", "IBM,v-scsi"},
+ {0,}
+};
+
+MODULE_DEVICE_TABLE(vio, ibmvscsi_device_table);
+static struct vio_driver ibmvscsi_driver = {
+ .name = "ibmvscsi",
+ .id_table = ibmvscsi_device_table,
+ .probe = ibmvscsi_probe,
+ .remove = ibmvscsi_remove
+};
+
+int __init ibmvscsi_module_init(void)
+{
+ return vio_register_driver(&ibmvscsi_driver);
+}
+
+void __exit ibmvscsi_module_exit(void)
+{
+ vio_unregister_driver(&ibmvscsi_driver);
+}
+
+module_init(ibmvscsi_module_init);
+module_exit(ibmvscsi_module_exit);
--- /dev/null
+/* ------------------------------------------------------------
+ * ibmvscsi.h
+ * (C) Copyright IBM Corporation 1994, 2003
+ * Authors: Colin DeVilbiss (devilbis@us.ibm.com)
+ * Santiago Leon (santil@us.ibm.com)
+ * Dave Boutcher (sleddog@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ *
+ * ------------------------------------------------------------
+ * Emulation of a SCSI host adapter for Virtual I/O devices
+ *
+ * This driver allows the Linux SCSI peripheral drivers to directly
+ * access devices in the hosting partition, either on an iSeries
+ * hypervisor system or a converged hypervisor system.
+ */
+#ifndef IBMVSCSI_H
+#define IBMVSCSI_H
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include "viosrp.h"
+
+struct scsi_cmnd;
+struct Scsi_Host;
+
+/* Number of indirect bufs...the list of these has to fit in the
+ * additional data of the srp_cmd struct along with the indirect
+ * descriptor
+ */
+#define MAX_INDIRECT_BUFS 10
+
+/* ------------------------------------------------------------
+ * Data Structures
+ */
+/* an RPA command/response transport queue */
+struct crq_queue {
+ struct viosrp_crq *msgs;
+ int size, cur;
+ dma_addr_t msg_token;
+ spinlock_t lock;
+};
+
+/* a unit of work for the hosting partition */
+struct srp_event_struct {
+ union viosrp_iu *xfer_iu;
+ struct scsi_cmnd *cmnd;
+ struct list_head list;
+ void (*done) (struct srp_event_struct *);
+ struct viosrp_crq crq;
+ struct ibmvscsi_host_data *hostdata;
+ atomic_t free;
+ union viosrp_iu iu;
+ void (*cmnd_done) (struct scsi_cmnd *);
+ struct completion comp;
+};
+
+/* a pool of event structs for use */
+struct event_pool {
+ struct srp_event_struct *events;
+ u32 size;
+ int next;
+ union viosrp_iu *iu_storage;
+ dma_addr_t iu_token;
+};
+
+/* all driver data associated with a host adapter */
+struct ibmvscsi_host_data {
+ atomic_t request_limit;
+ struct device *dev;
+ struct event_pool pool;
+ struct crq_queue queue;
+ struct tasklet_struct srp_task;
+ struct list_head sent;
+ struct Scsi_Host *host;
+ struct mad_adapter_info_data madapter_info;
+};
+
+/* routines for managing a command/response queue */
+int ibmvscsi_init_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata,
+ int max_requests);
+void ibmvscsi_release_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata,
+ int max_requests);
+void ibmvscsi_reset_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata);
+
+void ibmvscsi_handle_crq(struct viosrp_crq *crq,
+ struct ibmvscsi_host_data *hostdata);
+int ibmvscsi_send_crq(struct ibmvscsi_host_data *hostdata,
+ u64 word1, u64 word2);
+
+#endif /* IBMVSCSI_H */
--- /dev/null
+/* ------------------------------------------------------------
+ * iSeries_vscsi.c
+ * (C) Copyright IBM Corporation 1994, 2003
+ * Authors: Colin DeVilbiss (devilbis@us.ibm.com)
+ * Santiago Leon (santil@us.ibm.com)
+ * Dave Boutcher (sleddog@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ *
+ * ------------------------------------------------------------
+ * iSeries-specific functions of the SCSI host adapter for Virtual I/O devices
+ *
+ * This driver allows the Linux SCSI peripheral drivers to directly
+ * access devices in the hosting partition, either on an iSeries
+ * hypervisor system or a converged hypervisor system.
+ */
+
+#include <asm/iSeries/vio.h>
+#include <asm/iSeries/HvLpEvent.h>
+#include <asm/iSeries/HvTypes.h>
+#include <asm/iSeries/HvLpConfig.h>
+#include <asm/vio.h>
+#include <linux/device.h>
+#include "ibmvscsi.h"
+
+/* global variables */
+static struct ibmvscsi_host_data *single_host_data;
+
+/* ------------------------------------------------------------
+ * Routines for direct interpartition interaction
+ */
+struct srp_lp_event {
+ struct HvLpEvent lpevt; /* 0x00-0x17 */
+ u32 reserved1; /* 0x18-0x1B; unused */
+ u16 version; /* 0x1C-0x1D; unused */
+ u16 subtype_rc; /* 0x1E-0x1F; unused */
+ struct viosrp_crq crq; /* 0x20-0x3F */
+};
+
+/**
+ * standard interface for handling logical partition events.
+ */
+static void ibmvscsi_handle_event(struct HvLpEvent *lpevt)
+{
+ struct srp_lp_event *evt = (struct srp_lp_event *)lpevt;
+
+ if (!evt) {
+ printk(KERN_ERR "ibmvscsi: received null event\n");
+ return;
+ }
+
+ if (single_host_data == NULL) {
+ printk(KERN_ERR
+ "ibmvscsi: received event, no adapter present\n");
+ return;
+ }
+
+ ibmvscsi_handle_crq(&evt->crq, single_host_data);
+}
+
+/* ------------------------------------------------------------
+ * Routines for driver initialization
+ */
+int ibmvscsi_init_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata,
+ int max_requests)
+{
+ int rc;
+
+ single_host_data = hostdata;
+ rc = viopath_open(viopath_hostLp, viomajorsubtype_scsi, 0);
+ if (rc < 0) {
+ printk("viopath_open failed with rc %d in open_event_path\n",
+ rc);
+ goto viopath_open_failed;
+ }
+
+ rc = vio_setHandler(viomajorsubtype_scsi, ibmvscsi_handle_event);
+ if (rc < 0) {
+ printk("vio_setHandler failed with rc %d in open_event_path\n",
+ rc);
+ goto vio_setHandler_failed;
+ }
+ return 0;
+
+ vio_setHandler_failed:
+ viopath_close(viopath_hostLp, viomajorsubtype_scsi, max_requests);
+ viopath_open_failed:
+ return -1;
+}
+
+void ibmvscsi_release_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata,
+ int max_requests)
+{
+ vio_clearHandler(viomajorsubtype_scsi);
+ viopath_close(viopath_hostLp, viomajorsubtype_scsi, max_requests);
+}
+
+/**
+ * reset_crq_queue: - resets a crq after a failure
+ * @queue: crq_queue to initialize and register
+ * @hostdata: ibmvscsi_host_data of host
+ *
+ * no-op for iSeries
+ */
+void ibmvscsi_reset_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata)
+{
+}
+
+/**
+ * ibmvscsi_send_crq: - Send a CRQ
+ * @hostdata: the adapter
+ * @word1: the first 64 bits of the data
+ * @word2: the second 64 bits of the data
+ */
+int ibmvscsi_send_crq(struct ibmvscsi_host_data *hostdata, u64 word1, u64 word2)
+{
+ single_host_data = hostdata;
+ return HvCallEvent_signalLpEventFast(viopath_hostLp,
+ HvLpEvent_Type_VirtualIo,
+ viomajorsubtype_scsi,
+ HvLpEvent_AckInd_NoAck,
+ HvLpEvent_AckType_ImmediateAck,
+ viopath_sourceinst(viopath_hostLp),
+ viopath_targetinst(viopath_hostLp),
+ 0,
+ VIOVERSION << 16, word1, word2, 0,
+ 0);
+}
--- /dev/null
+/* ------------------------------------------------------------
+ * rpa_vscsi.c
+ * (C) Copyright IBM Corporation 1994, 2003
+ * Authors: Colin DeVilbiss (devilbis@us.ibm.com)
+ * Santiago Leon (santil@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
+ *
+ * ------------------------------------------------------------
+ * RPA-specific functions of the SCSI host adapter for Virtual I/O devices
+ *
+ * This driver allows the Linux SCSI peripheral drivers to directly
+ * access devices in the hosting partition, either on an iSeries
+ * hypervisor system or a converged hypervisor system.
+ */
+
+#include <asm/vio.h>
+#include <asm/iommu.h>
+#include <asm/hvcall.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include "ibmvscsi.h"
+
+/* ------------------------------------------------------------
+ * Routines for managing the command/response queue
+ */
+/**
+ * ibmvscsi_handle_event: - Interrupt handler for crq events
+ * @irq: number of irq to handle, not used
+ * @dev_instance: ibmvscsi_host_data of host that received interrupt
+ * @regs: pt_regs with registers
+ *
+ * Disables interrupts and schedules srp_task
+ * Always returns IRQ_HANDLED
+ */
+static irqreturn_t ibmvscsi_handle_event(int irq,
+ void *dev_instance,
+ struct pt_regs *regs)
+{
+ struct ibmvscsi_host_data *hostdata =
+ (struct ibmvscsi_host_data *)dev_instance;
+ vio_disable_interrupts(to_vio_dev(hostdata->dev));
+ tasklet_schedule(&hostdata->srp_task);
+ return IRQ_HANDLED;
+}
+
+/**
+ * release_crq_queue: - Deallocates data and unregisters CRQ
+ * @queue: crq_queue to initialize and register
+ * @host_data: ibmvscsi_host_data of host
+ *
+ * Frees irq, deallocates a page for messages, unmaps dma, and unregisters
+ * the crq with the hypervisor.
+ */
+void ibmvscsi_release_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata,
+ int max_requests)
+{
+ long rc;
+ struct vio_dev *vdev = to_vio_dev(hostdata->dev);
+ free_irq(vdev->irq, (void *)hostdata);
+ tasklet_kill(&hostdata->srp_task);
+ do {
+ rc = plpar_hcall_norets(H_FREE_CRQ, vdev->unit_address);
+ } while ((rc == H_Busy) || (H_isLongBusy(rc)));
+ dma_unmap_single(hostdata->dev,
+ queue->msg_token,
+ queue->size * sizeof(*queue->msgs), DMA_BIDIRECTIONAL);
+ free_page((unsigned long)queue->msgs);
+}
+
+/**
+ * crq_queue_next_crq: - Returns the next entry in message queue
+ * @queue: crq_queue to use
+ *
+ * Returns pointer to next entry in queue, or NULL if there are no new
+ * entried in the CRQ.
+ */
+static struct viosrp_crq *crq_queue_next_crq(struct crq_queue *queue)
+{
+ struct viosrp_crq *crq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&queue->lock, flags);
+ crq = &queue->msgs[queue->cur];
+ if (crq->valid & 0x80) {
+ if (++queue->cur == queue->size)
+ queue->cur = 0;
+ } else
+ crq = NULL;
+ spin_unlock_irqrestore(&queue->lock, flags);
+
+ return crq;
+}
+
+/**
+ * ibmvscsi_send_crq: - Send a CRQ
+ * @hostdata: the adapter
+ * @word1: the first 64 bits of the data
+ * @word2: the second 64 bits of the data
+ */
+int ibmvscsi_send_crq(struct ibmvscsi_host_data *hostdata, u64 word1, u64 word2)
+{
+ struct vio_dev *vdev = to_vio_dev(hostdata->dev);
+
+ return plpar_hcall_norets(H_SEND_CRQ, vdev->unit_address, word1, word2);
+}
+
+/**
+ * ibmvscsi_task: - Process srps asynchronously
+ * @data: ibmvscsi_host_data of host
+ */
+static void ibmvscsi_task(void *data)
+{
+ struct ibmvscsi_host_data *hostdata = (struct ibmvscsi_host_data *)data;
+ struct vio_dev *vdev = to_vio_dev(hostdata->dev);
+ struct viosrp_crq *crq;
+ int done = 0;
+
+ while (!done) {
+ /* Pull all the valid messages off the CRQ */
+ while ((crq = crq_queue_next_crq(&hostdata->queue)) != NULL) {
+ ibmvscsi_handle_crq(crq, hostdata);
+ crq->valid = 0x00;
+ }
+
+ vio_enable_interrupts(vdev);
+ if ((crq = crq_queue_next_crq(&hostdata->queue)) != NULL) {
+ vio_disable_interrupts(vdev);
+ ibmvscsi_handle_crq(crq, hostdata);
+ crq->valid = 0x00;
+ } else {
+ done = 1;
+ }
+ }
+}
+
+/**
+ * initialize_crq_queue: - Initializes and registers CRQ with hypervisor
+ * @queue: crq_queue to initialize and register
+ * @hostdata: ibmvscsi_host_data of host
+ *
+ * Allocates a page for messages, maps it for dma, and registers
+ * the crq with the hypervisor.
+ * Returns zero on success.
+ */
+int ibmvscsi_init_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata,
+ int max_requests)
+{
+ int rc;
+ struct vio_dev *vdev = to_vio_dev(hostdata->dev);
+
+ queue->msgs = (struct viosrp_crq *)get_zeroed_page(GFP_KERNEL);
+
+ if (!queue->msgs)
+ goto malloc_failed;
+ queue->size = PAGE_SIZE / sizeof(*queue->msgs);
+
+ queue->msg_token = dma_map_single(hostdata->dev, queue->msgs,
+ queue->size * sizeof(*queue->msgs),
+ DMA_BIDIRECTIONAL);
+
+ if (dma_mapping_error(queue->msg_token))
+ goto map_failed;
+
+ rc = plpar_hcall_norets(H_REG_CRQ,
+ vdev->unit_address,
+ queue->msg_token, PAGE_SIZE);
+ if (rc == 2) {
+ /* Adapter is good, but other end is not ready */
+ printk(KERN_WARNING "ibmvscsi: Partner adapter not ready\n");
+ } else if (rc != 0) {
+ printk(KERN_WARNING "ibmvscsi: Error %d opening adapter\n", rc);
+ goto reg_crq_failed;
+ }
+
+ if (request_irq(vdev->irq,
+ ibmvscsi_handle_event,
+ 0, "ibmvscsi", (void *)hostdata) != 0) {
+ printk(KERN_ERR "ibmvscsi: couldn't register irq 0x%x\n",
+ vdev->irq);
+ goto req_irq_failed;
+ }
+
+ rc = vio_enable_interrupts(vdev);
+ if (rc != 0) {
+ printk(KERN_ERR "ibmvscsi: Error %d enabling interrupts!!!\n",
+ rc);
+ goto req_irq_failed;
+ }
+
+ queue->cur = 0;
+ queue->lock = SPIN_LOCK_UNLOCKED;
+
+ tasklet_init(&hostdata->srp_task, (void *)ibmvscsi_task,
+ (unsigned long)hostdata);
+
+ return 0;
+
+ req_irq_failed:
+ do {
+ rc = plpar_hcall_norets(H_FREE_CRQ, vdev->unit_address);
+ } while ((rc == H_Busy) || (H_isLongBusy(rc)));
+ reg_crq_failed:
+ dma_unmap_single(hostdata->dev,
+ queue->msg_token,
+ queue->size * sizeof(*queue->msgs), DMA_BIDIRECTIONAL);
+ map_failed:
+ free_page((unsigned long)queue->msgs);
+ malloc_failed:
+ return -1;
+}
+
+/**
+ * reset_crq_queue: - resets a crq after a failure
+ * @queue: crq_queue to initialize and register
+ * @hostdata: ibmvscsi_host_data of host
+ *
+ */
+void ibmvscsi_reset_crq_queue(struct crq_queue *queue,
+ struct ibmvscsi_host_data *hostdata)
+{
+ int rc;
+ struct vio_dev *vdev = to_vio_dev(hostdata->dev);
+
+ /* Close the CRQ */
+ do {
+ rc = plpar_hcall_norets(H_FREE_CRQ, vdev->unit_address);
+ } while ((rc == H_Busy) || (H_isLongBusy(rc)));
+
+ /* Clean out the queue */
+ memset(queue->msgs, 0x00, PAGE_SIZE);
+ queue->cur = 0;
+
+ /* And re-open it again */
+ rc = plpar_hcall_norets(H_REG_CRQ,
+ vdev->unit_address,
+ queue->msg_token, PAGE_SIZE);
+ if (rc == 2) {
+ /* Adapter is good, but other end is not ready */
+ printk(KERN_WARNING "ibmvscsi: Partner adapter not ready\n");
+ } else if (rc != 0) {
+ printk(KERN_WARNING
+ "ibmvscsi: couldn't register crq--rc 0x%x\n", rc);
+ }
+}
--- /dev/null
+/*****************************************************************************/
+/* srp.h -- SCSI RDMA Protocol definitions */
+/* */
+/* Written By: Colin Devilbis, IBM Corporation */
+/* */
+/* Copyright (C) 2003 IBM Corporation */
+/* */
+/* This program is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU General Public License as published by */
+/* the Free Software Foundation; either version 2 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, */
+/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
+/* GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program; if not, write to the Free Software */
+/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
+/* */
+/* */
+/* This file contains structures and definitions for the SCSI RDMA Protocol */
+/* (SRP) as defined in the T10 standard available at www.t10.org. This */
+/* file was based on the 16a version of the standard */
+/* */
+/*****************************************************************************/
+#ifndef SRP_H
+#define SRP_H
+
+#define PACKED __attribute__((packed))
+
+enum srp_types {
+ SRP_LOGIN_REQ_TYPE = 0x00,
+ SRP_LOGIN_RSP_TYPE = 0xC0,
+ SRP_LOGIN_REJ_TYPE = 0x80,
+ SRP_I_LOGOUT_TYPE = 0x03,
+ SRP_T_LOGOUT_TYPE = 0x80,
+ SRP_TSK_MGMT_TYPE = 0x01,
+ SRP_CMD_TYPE = 0x02,
+ SRP_RSP_TYPE = 0xC1,
+ SRP_CRED_REQ_TYPE = 0x81,
+ SRP_CRED_RSP_TYPE = 0x41,
+ SRP_AER_REQ_TYPE = 0x82,
+ SRP_AER_RSP_TYPE = 0x42
+};
+
+enum srp_descriptor_formats {
+ SRP_NO_BUFFER = 0x00,
+ SRP_DIRECT_BUFFER = 0x01,
+ SRP_INDIRECT_BUFFER = 0x02
+};
+
+struct memory_descriptor {
+ u64 virtual_address;
+ u32 memory_handle;
+ u32 length;
+};
+
+struct indirect_descriptor {
+ struct memory_descriptor head;
+ u32 total_length;
+ struct memory_descriptor list[1] PACKED;
+};
+
+struct srp_generic {
+ u8 type;
+ u8 reserved1[7];
+ u64 tag;
+};
+
+struct srp_login_req {
+ u8 type;
+ u8 reserved1[7];
+ u64 tag;
+ u32 max_requested_initiator_to_target_iulen;
+ u32 reserved2;
+ u16 required_buffer_formats;
+ u8 reserved3:6;
+ u8 multi_channel_action:2;
+ u8 reserved4;
+ u32 reserved5;
+ u8 initiator_port_identifier[16];
+ u8 target_port_identifier[16];
+};
+
+struct srp_login_rsp {
+ u8 type;
+ u8 reserved1[3];
+ u32 request_limit_delta;
+ u64 tag;
+ u32 max_initiator_to_target_iulen;
+ u32 max_target_to_initiator_iulen;
+ u16 supported_buffer_formats;
+ u8 reserved2:6;
+ u8 multi_channel_result:2;
+ u8 reserved3;
+ u8 reserved4[24];
+};
+
+struct srp_login_rej {
+ u8 type;
+ u8 reserved1[3];
+ u32 reason;
+ u64 tag;
+ u64 reserved2;
+ u16 supported_buffer_formats;
+ u8 reserved3[6];
+};
+
+struct srp_i_logout {
+ u8 type;
+ u8 reserved1[7];
+ u64 tag;
+};
+
+struct srp_t_logout {
+ u8 type;
+ u8 reserved1[3];
+ u32 reason;
+ u64 tag;
+};
+
+struct srp_tsk_mgmt {
+ u8 type;
+ u8 reserved1[7];
+ u64 tag;
+ u32 reserved2;
+ u64 lun PACKED;
+ u8 reserved3;
+ u8 reserved4;
+ u8 task_mgmt_flags;
+ u8 reserved5;
+ u64 managed_task_tag;
+ u64 reserved6;
+};
+
+struct srp_cmd {
+ u8 type;
+ u32 reserved1 PACKED;
+ u8 data_out_format:4;
+ u8 data_in_format:4;
+ u8 data_out_count;
+ u8 data_in_count;
+ u64 tag;
+ u32 reserved2;
+ u64 lun PACKED;
+ u8 reserved3;
+ u8 reserved4:5;
+ u8 task_attribute:3;
+ u8 reserved5;
+ u8 additional_cdb_len;
+ u8 cdb[16];
+ u8 additional_data[0x100 - 0x30];
+};
+
+struct srp_rsp {
+ u8 type;
+ u8 reserved1[3];
+ u32 request_limit_delta;
+ u64 tag;
+ u16 reserved2;
+ u8 reserved3:2;
+ u8 diunder:1;
+ u8 diover:1;
+ u8 dounder:1;
+ u8 doover:1;
+ u8 snsvalid:1;
+ u8 rspvalid:1;
+ u8 status;
+ u32 data_in_residual_count;
+ u32 data_out_residual_count;
+ u32 sense_data_list_length;
+ u32 response_data_list_length;
+ u8 sense_and_response_data[18];
+};
+
+struct srp_cred_req {
+ u8 type;
+ u8 reserved1[3];
+ u32 request_limit_delta;
+ u64 tag;
+};
+
+struct srp_cred_rsp {
+ u8 type;
+ u8 reserved1[7];
+ u64 tag;
+};
+
+struct srp_aer_req {
+ u8 type;
+ u8 reserved1[3];
+ u32 request_limit_delta;
+ u64 tag;
+ u32 reserved2;
+ u64 lun;
+ u32 sense_data_list_length;
+ u32 reserved3;
+ u8 sense_data[20];
+};
+
+struct srp_aer_rsp {
+ u8 type;
+ u8 reserved1[7];
+ u64 tag;
+};
+
+union srp_iu {
+ struct srp_generic generic;
+ struct srp_login_req login_req;
+ struct srp_login_rsp login_rsp;
+ struct srp_login_rej login_rej;
+ struct srp_i_logout i_logout;
+ struct srp_t_logout t_logout;
+ struct srp_tsk_mgmt tsk_mgmt;
+ struct srp_cmd cmd;
+ struct srp_rsp rsp;
+ struct srp_cred_req cred_req;
+ struct srp_cred_rsp cred_rsp;
+ struct srp_aer_req aer_req;
+ struct srp_aer_rsp aer_rsp;
+};
+
+#endif
--- /dev/null
+/*****************************************************************************/
+/* srp.h -- SCSI RDMA Protocol definitions */
+/* */
+/* Written By: Colin Devilbis, IBM Corporation */
+/* */
+/* Copyright (C) 2003 IBM Corporation */
+/* */
+/* This program is free software; you can redistribute it and/or modify */
+/* it under the terms of the GNU General Public License as published by */
+/* the Free Software Foundation; either version 2 of the License, or */
+/* (at your option) any later version. */
+/* */
+/* This program is distributed in the hope that it will be useful, */
+/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
+/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
+/* GNU General Public License for more details. */
+/* */
+/* You should have received a copy of the GNU General Public License */
+/* along with this program; if not, write to the Free Software */
+/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
+/* */
+/* */
+/* This file contains structures and definitions for IBM RPA (RS/6000 */
+/* platform architecture) implementation of the SRP (SCSI RDMA Protocol) */
+/* standard. SRP is used on IBM iSeries and pSeries platforms to send SCSI */
+/* commands between logical partitions. */
+/* */
+/* SRP Information Units (IUs) are sent on a "Command/Response Queue" (CRQ) */
+/* between partitions. The definitions in this file are architected, */
+/* and cannot be changed without breaking compatibility with other versions */
+/* of Linux and other operating systems (AIX, OS/400) that talk this protocol*/
+/* between logical partitions */
+/*****************************************************************************/
+#ifndef VIOSRP_H
+#define VIOSRP_H
+#include "srp.h"
+
+enum viosrp_crq_formats {
+ VIOSRP_SRP_FORMAT = 0x01,
+ VIOSRP_MAD_FORMAT = 0x02,
+ VIOSRP_OS400_FORMAT = 0x03,
+ VIOSRP_AIX_FORMAT = 0x04,
+ VIOSRP_LINUX_FORMAT = 0x06,
+ VIOSRP_INLINE_FORMAT = 0x07
+};
+
+struct viosrp_crq {
+ u8 valid; /* used by RPA */
+ u8 format; /* SCSI vs out-of-band */
+ u8 reserved;
+ u8 status; /* non-scsi failure? (e.g. DMA failure) */
+ u16 timeout; /* in seconds */
+ u16 IU_length; /* in bytes */
+ u64 IU_data_ptr; /* the TCE for transferring data */
+};
+
+/* MADs are Management requests above and beyond the IUs defined in the SRP
+ * standard.
+ */
+enum viosrp_mad_types {
+ VIOSRP_EMPTY_IU_TYPE = 0x01,
+ VIOSRP_ERROR_LOG_TYPE = 0x02,
+ VIOSRP_ADAPTER_INFO_TYPE = 0x03,
+ VIOSRP_HOST_CONFIG_TYPE = 0x04
+};
+
+/*
+ * Common MAD header
+ */
+struct mad_common {
+ u32 type;
+ u16 status;
+ u16 length;
+ u64 tag;
+};
+
+/*
+ * All SRP (and MAD) requests normally flow from the
+ * client to the server. There is no way for the server to send
+ * an asynchronous message back to the client. The Empty IU is used
+ * to hang out a meaningless request to the server so that it can respond
+ * asynchrouously with something like a SCSI AER
+ */
+struct viosrp_empty_iu {
+ struct mad_common common;
+ u64 buffer;
+ u32 port;
+};
+
+struct viosrp_error_log {
+ struct mad_common common;
+ u64 buffer;
+};
+
+struct viosrp_adapter_info {
+ struct mad_common common;
+ u64 buffer;
+};
+
+struct viosrp_host_config {
+ struct mad_common common;
+ u64 buffer;
+};
+
+union mad_iu {
+ struct viosrp_empty_iu empty_iu;
+ struct viosrp_error_log error_log;
+ struct viosrp_adapter_info adapter_info;
+ struct viosrp_host_config host_config;
+};
+
+union viosrp_iu {
+ union srp_iu srp;
+ union mad_iu mad;
+};
+
+struct mad_adapter_info_data {
+ char srp_version[8];
+ char partition_name[96];
+ u32 partition_number;
+ u32 mad_version;
+ u32 os_type;
+ u32 port_max_txu[8]; /* per-port maximum transfer */
+};
+
+#endif
--- /dev/null
+config MEGARAID_NEWGEN
+ bool "LSI Logic New Generation RAID Device Drivers"
+ depends on PCI && SCSI
+ help
+ LSI Logic RAID Device Drivers
+
+config MEGARAID_MM
+ tristate "LSI Logic Management Module (New Driver)"
+ depends on PCI && SCSI && MEGARAID_NEWGEN
+ help
+ Management Module provides ioctl, sysfs support for LSI Logic
+ RAID controllers.
+ To compile this driver as a module, choose M here: the
+ module will be called megaraid_mm
+
+
+config MEGARAID_MAILBOX
+ tristate "LSI Logic MegaRAID Driver (New Driver)"
+ depends on PCI && SCSI && MEGARAID_MM
+ help
+ List of supported controllers
+
+ OEM Product Name VID :DID :SVID:SSID
+ --- ------------ ---- ---- ---- ----
+ Dell PERC3/QC 101E:1960:1028:0471
+ Dell PERC3/DC 101E:1960:1028:0493
+ Dell PERC3/SC 101E:1960:1028:0475
+ Dell PERC3/Di 1028:000E:1028:0123
+ Dell PERC4/SC 1000:1960:1028:0520
+ Dell PERC4/DC 1000:1960:1028:0518
+ Dell PERC4/QC 1000:0407:1028:0531
+ Dell PERC4/Di 1028:000F:1028:014A
+ Dell PERC 4e/Si 1028:0013:1028:016c
+ Dell PERC 4e/Di 1028:0013:1028:016d
+ Dell PERC 4e/Di 1028:0013:1028:016e
+ Dell PERC 4e/Di 1028:0013:1028:016f
+ Dell PERC 4e/Di 1028:0013:1028:0170
+ Dell PERC 4e/DC 1000:0408:1028:0002
+ Dell PERC 4e/SC 1000:0408:1028:0001
+ LSI MegaRAID SCSI 320-0 1000:1960:1000:A520
+ LSI MegaRAID SCSI 320-1 1000:1960:1000:0520
+ LSI MegaRAID SCSI 320-2 1000:1960:1000:0518
+ LSI MegaRAID SCSI 320-0X 1000:0407:1000:0530
+ LSI MegaRAID SCSI 320-2X 1000:0407:1000:0532
+ LSI MegaRAID SCSI 320-4X 1000:0407:1000:0531
+ LSI MegaRAID SCSI 320-1E 1000:0408:1000:0001
+ LSI MegaRAID SCSI 320-2E 1000:0408:1000:0002
+ LSI MegaRAID SATA 150-4 1000:1960:1000:4523
+ LSI MegaRAID SATA 150-6 1000:1960:1000:0523
+ LSI MegaRAID SATA 300-4X 1000:0409:1000:3004
+ LSI MegaRAID SATA 300-8X 1000:0409:1000:3008
+ INTEL RAID Controller SRCU42X 1000:0407:8086:0532
+ INTEL RAID Controller SRCS16 1000:1960:8086:0523
+ INTEL RAID Controller SRCU42E 1000:0408:8086:0002
+ INTEL RAID Controller SRCZCRX 1000:0407:8086:0530
+ INTEL RAID Controller SRCS28X 1000:0409:8086:3008
+ INTEL RAID Controller SROMBU42E 1000:0408:8086:3431
+ INTEL RAID Controller SROMBU42E 1000:0408:8086:3499
+ INTEL RAID Controller SRCU51L 1000:1960:8086:0520
+ FSC MegaRAID PCI Express ROMB 1000:0408:1734:1065
+ ACER MegaRAID ROMB-2E 1000:0408:1025:004D
+
+ To compile this driver as a module, choose M here: the
+ module will be called megaraid_mbox
+
+if MEGARAID_NEWGEN=n
+config MEGARAID_LEGACY
+ tristate "LSI Logic Legacy MegaRAID Driver"
+ depends on PCI && SCSI
+ help
+ This driver supports the LSI MegaRAID 418, 428, 438, 466, 762, 490
+ and 467 SCSI host adapters. This driver also support the all U320
+ RAID controllers
+
+ To compile this driver as a module, choose M here: the
+ module will be called megaraid
+endif
--- /dev/null
+obj-$(CONFIG_MEGARAID_MM) += megaraid_mm.o
+obj-$(CONFIG_MEGARAID_MAILBOX) += megaraid_mbox.o
--- /dev/null
+/*
+ *
+ * Linux MegaRAID Unified device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : mbox_defs.h
+ *
+ */
+#ifndef _MRAID_MBOX_DEFS_H_
+#define _MRAID_MBOX_DEFS_H_
+
+#include <linux/types.h>
+
+/*
+ * Commands and states for mailbox based controllers
+ */
+
+#define MBOXCMD_LREAD 0x01
+#define MBOXCMD_LWRITE 0x02
+#define MBOXCMD_PASSTHRU 0x03
+#define MBOXCMD_ADPEXTINQ 0x04
+#define MBOXCMD_ADAPTERINQ 0x05
+#define MBOXCMD_LREAD64 0xA7
+#define MBOXCMD_LWRITE64 0xA8
+#define MBOXCMD_PASSTHRU64 0xC3
+#define MBOXCMD_EXTPTHRU 0xE3
+
+#define MAIN_MISC_OPCODE 0xA4
+#define GET_MAX_SG_SUPPORT 0x01
+#define SUPPORT_EXT_CDB 0x16
+
+#define FC_NEW_CONFIG 0xA1
+#define NC_SUBOP_PRODUCT_INFO 0x0E
+#define NC_SUBOP_ENQUIRY3 0x0F
+#define ENQ3_GET_SOLICITED_FULL 0x02
+#define OP_DCMD_READ_CONFIG 0x04
+#define NEW_READ_CONFIG_8LD 0x67
+#define READ_CONFIG_8LD 0x07
+#define FLUSH_ADAPTER 0x0A
+#define FLUSH_SYSTEM 0xFE
+
+/*
+ * Command for random deletion of logical drives
+ */
+#define FC_DEL_LOGDRV 0xA4
+#define OP_SUP_DEL_LOGDRV 0x2A
+#define OP_GET_LDID_MAP 0x18
+#define OP_DEL_LOGDRV 0x1C
+
+/*
+ * BIOS commands
+ */
+#define IS_BIOS_ENABLED 0x62
+#define GET_BIOS 0x01
+#define CHNL_CLASS 0xA9
+#define GET_CHNL_CLASS 0x00
+#define SET_CHNL_CLASS 0x01
+#define CH_RAID 0x01
+#define CH_SCSI 0x00
+#define BIOS_PVT_DATA 0x40
+#define GET_BIOS_PVT_DATA 0x00
+
+
+/*
+ * Commands to support clustering
+ */
+#define GET_TARGET_ID 0x7D
+#define CLUSTER_OP 0x70
+#define GET_CLUSTER_MODE 0x02
+#define CLUSTER_CMD 0x6E
+#define RESERVE_LD 0x01
+#define RELEASE_LD 0x02
+#define RESET_RESERVATIONS 0x03
+#define RESERVATION_STATUS 0x04
+#define RESERVE_PD 0x05
+#define RELEASE_PD 0x06
+
+
+/*
+ * Module battery status
+ */
+#define BATTERY_MODULE_MISSING 0x01
+#define BATTERY_LOW_VOLTAGE 0x02
+#define BATTERY_TEMP_HIGH 0x04
+#define BATTERY_PACK_MISSING 0x08
+#define BATTERY_CHARGE_MASK 0x30
+#define BATTERY_CHARGE_DONE 0x00
+#define BATTERY_CHARGE_INPROG 0x10
+#define BATTERY_CHARGE_FAIL 0x20
+#define BATTERY_CYCLES_EXCEEDED 0x40
+
+/*
+ * Physical drive states.
+ */
+#define PDRV_UNCNF 0
+#define PDRV_ONLINE 3
+#define PDRV_FAILED 4
+#define PDRV_RBLD 5
+#define PDRV_HOTSPARE 6
+
+
+/*
+ * Raid logical drive states.
+ */
+#define RDRV_OFFLINE 0
+#define RDRV_DEGRADED 1
+#define RDRV_OPTIMAL 2
+#define RDRV_DELETED 3
+
+/*
+ * Read, write and cache policies
+ */
+#define NO_READ_AHEAD 0
+#define READ_AHEAD 1
+#define ADAP_READ_AHEAD 2
+#define WRMODE_WRITE_THRU 0
+#define WRMODE_WRITE_BACK 1
+#define CACHED_IO 0
+#define DIRECT_IO 1
+
+#define MAX_LOGICAL_DRIVES_8LD 8
+#define MAX_LOGICAL_DRIVES_40LD 40
+#define FC_MAX_PHYSICAL_DEVICES 256
+#define MAX_MBOX_CHANNELS 5
+#define MAX_MBOX_TARGET 15
+#define MBOX_MAX_PHYSICAL_DRIVES MAX_MBOX_CHANNELS*MAX_MBOX_TARGET
+#define MAX_ROW_SIZE_40LD 32
+#define MAX_ROW_SIZE_8LD 8
+#define SPAN_DEPTH_8_SPANS 8
+#define SPAN_DEPTH_4_SPANS 4
+#define MAX_REQ_SENSE_LEN 0x20
+
+
+
+/**
+ * struct mbox_t - Driver and f/w handshake structure.
+ * @cmd : firmware command
+ * @cmdid : command id
+ * @numsectors : number of sectors to be transferred
+ * @lba : Logical Block Address on LD
+ * @xferaddr : DMA address for data transfer
+ * @logdrv : logical drive number
+ * @numsge : number of scatter gather elements in sg list
+ * @resvd : reserved
+ * @busy : f/w busy, must wait to issue more commands.
+ * @numstatus : number of commands completed.
+ * @status : status of the commands completed
+ * @completed : array of completed command ids.
+ * @poll : poll and ack sequence
+ * @ack : poll and ack sequence
+ *
+ * The central handshake structure between the driver and the firmware. This
+ * structure must be allocated by the driver and aligned at 8-byte boundary.
+ */
+#define MBOX_MAX_FIRMWARE_STATUS 46
+typedef struct {
+ uint8_t cmd;
+ uint8_t cmdid;
+ uint16_t numsectors;
+ uint32_t lba;
+ uint32_t xferaddr;
+ uint8_t logdrv;
+ uint8_t numsge;
+ uint8_t resvd;
+ uint8_t busy;
+ uint8_t numstatus;
+ uint8_t status;
+ uint8_t completed[MBOX_MAX_FIRMWARE_STATUS];
+ uint8_t poll;
+ uint8_t ack;
+} __attribute__ ((packed)) mbox_t;
+
+
+/**
+ * mbox64_t - 64-bit extension for the mailbox
+ * @segment_lo : the low 32-bits of the address of the scatter-gather list
+ * @segment_hi : the upper 32-bits of the address of the scatter-gather list
+ * @mbox : 32-bit mailbox, whose xferadder field must be set to
+ * 0xFFFFFFFF
+ *
+ * This is the extension of the 32-bit mailbox to be able to perform DMA
+ * beyond 4GB address range.
+ */
+typedef struct {
+ uint32_t xferaddr_lo;
+ uint32_t xferaddr_hi;
+ mbox_t mbox32;
+} __attribute__ ((packed)) mbox64_t;
+
+/*
+ * mailbox structure used for internal commands
+ */
+typedef struct {
+ u8 cmd;
+ u8 cmdid;
+ u8 opcode;
+ u8 subopcode;
+ u32 lba;
+ u32 xferaddr;
+ u8 logdrv;
+ u8 rsvd[3];
+ u8 numstatus;
+ u8 status;
+} __attribute__ ((packed)) int_mbox_t;
+
+/**
+ * mraid_passthru_t - passthru structure to issue commands to physical devices
+ * @timeout : command timeout, 0=6sec, 1=60sec, 2=10min, 3=3hr
+ * @ars : set if ARS required after check condition
+ * @islogical : set if command meant for logical devices
+ * @logdrv : logical drive number if command for LD
+ * @channel : Channel on which physical device is located
+ * @target : SCSI target of the device
+ * @queuetag : unused
+ * @queueaction : unused
+ * @cdb : SCSI CDB
+ * @cdblen : length of the CDB
+ * @reqsenselen : amount of request sense data to be returned
+ * @reqsensearea : Sense information buffer
+ * @numsge : number of scatter-gather elements in the sg list
+ * @scsistatus : SCSI status of the command completed.
+ * @dataxferaddr : DMA data transfer address
+ * @dataxferlen : amount of the data to be transferred.
+ */
+typedef struct {
+ uint8_t timeout :3;
+ uint8_t ars :1;
+ uint8_t reserved :3;
+ uint8_t islogical :1;
+ uint8_t logdrv;
+ uint8_t channel;
+ uint8_t target;
+ uint8_t queuetag;
+ uint8_t queueaction;
+ uint8_t cdb[10];
+ uint8_t cdblen;
+ uint8_t reqsenselen;
+ uint8_t reqsensearea[MAX_REQ_SENSE_LEN];
+ uint8_t numsge;
+ uint8_t scsistatus;
+ uint32_t dataxferaddr;
+ uint32_t dataxferlen;
+} __attribute__ ((packed)) mraid_passthru_t;
+
+typedef struct {
+
+ uint32_t dataxferaddr_lo;
+ uint32_t dataxferaddr_hi;
+ mraid_passthru_t pthru32;
+
+} __attribute__ ((packed)) mega_passthru64_t;
+
+/**
+ * mraid_epassthru_t - passthru structure to issue commands to physical devices
+ * @timeout : command timeout, 0=6sec, 1=60sec, 2=10min, 3=3hr
+ * @ars : set if ARS required after check condition
+ * @rsvd1 : reserved field
+ * @cd_rom : (?)
+ * @rsvd2 : reserved field
+ * @islogical : set if command meant for logical devices
+ * @logdrv : logical drive number if command for LD
+ * @channel : Channel on which physical device is located
+ * @target : SCSI target of the device
+ * @queuetag : unused
+ * @queueaction : unused
+ * @cdblen : length of the CDB
+ * @rsvd3 : reserved field
+ * @cdb : SCSI CDB
+ * @numsge : number of scatter-gather elements in the sg list
+ * @status : SCSI status of the command completed.
+ * @reqsenselen : amount of request sense data to be returned
+ * @reqsensearea : Sense information buffer
+ * @rsvd4 : reserved field
+ * @dataxferaddr : DMA data transfer address
+ * @dataxferlen : amount of the data to be transferred.
+ */
+typedef struct {
+ uint8_t timeout :3;
+ uint8_t ars :1;
+ uint8_t rsvd1 :1;
+ uint8_t cd_rom :1;
+ uint8_t rsvd2 :1;
+ uint8_t islogical :1;
+ uint8_t logdrv;
+ uint8_t channel;
+ uint8_t target;
+ uint8_t queuetag;
+ uint8_t queueaction;
+ uint8_t cdblen;
+ uint8_t rsvd3;
+ uint8_t cdb[16];
+ uint8_t numsge;
+ uint8_t status;
+ uint8_t reqsenselen;
+ uint8_t reqsensearea[MAX_REQ_SENSE_LEN];
+ uint8_t rsvd4;
+ uint32_t dataxferaddr;
+ uint32_t dataxferlen;
+} __attribute__ ((packed)) mraid_epassthru_t;
+
+
+/**
+ * mraid_pinfo_t - product info, static information about the controller
+ * @data_size : current size in bytes (not including resvd)
+ * @config_signature : Current value is 0x00282008
+ * @fw_version : Firmware version
+ * @bios_version : version of the BIOS
+ * @product_name : Name given to the controller
+ * @max_commands : Maximum concurrent commands supported
+ * @nchannels : Number of SCSI Channels detected
+ * @fc_loop_present : Number of Fibre Loops detected
+ * @mem_type : EDO, FPM, SDRAM etc
+ * @signature :
+ * @dram_size : In terms of MB
+ * @subsysid : device PCI subsystem ID
+ * @subsysvid : device PCI subsystem vendor ID
+ * @notify_counters :
+ * @pad1k : 135 + 889 resvd = 1024 total size
+ *
+ * This structures holds the information about the controller which is not
+ * expected to change dynamically.
+ *
+ * The current value of config signature is 0x00282008:
+ * 0x28 = MAX_LOGICAL_DRIVES,
+ * 0x20 = Number of stripes and
+ * 0x08 = Number of spans
+ */
+typedef struct {
+ uint32_t data_size;
+ uint32_t config_signature;
+ uint8_t fw_version[16];
+ uint8_t bios_version[16];
+ uint8_t product_name[80];
+ uint8_t max_commands;
+ uint8_t nchannels;
+ uint8_t fc_loop_present;
+ uint8_t mem_type;
+ uint32_t signature;
+ uint16_t dram_size;
+ uint16_t subsysid;
+ uint16_t subsysvid;
+ uint8_t notify_counters;
+ uint8_t pad1k[889];
+} __attribute__ ((packed)) mraid_pinfo_t;
+
+
+/**
+ * mraid_notify_t - the notification structure
+ * @global_counter : Any change increments this counter
+ * @param_counter : Indicates any params changed
+ * @param_id : Param modified - defined below
+ * @param_val : New val of last param modified
+ * @write_config_counter : write config occurred
+ * @write_config_rsvd :
+ * @ldrv_op_counter : Indicates ldrv op started/completed
+ * @ldrv_opid : ldrv num
+ * @ldrv_opcmd : ldrv operation - defined below
+ * @ldrv_opstatus : status of the operation
+ * @ldrv_state_counter : Indicates change of ldrv state
+ * @ldrv_state_id : ldrv num
+ * @ldrv_state_new : New state
+ * @ldrv_state_old : old state
+ * @pdrv_state_counter : Indicates change of ldrv state
+ * @pdrv_state_id : pdrv id
+ * @pdrv_state_new : New state
+ * @pdrv_state_old : old state
+ * @pdrv_fmt_counter : Indicates pdrv format started/over
+ * @pdrv_fmt_id : pdrv id
+ * @pdrv_fmt_val : format started/over
+ * @pdrv_fmt_rsvd :
+ * @targ_xfer_counter : Indicates SCSI-2 Xfer rate change
+ * @targ_xfer_id : pdrv Id
+ * @targ_xfer_val : new Xfer params of last pdrv
+ * @targ_xfer_rsvd :
+ * @fcloop_id_chg_counter : Indicates loopid changed
+ * @fcloopid_pdrvid : pdrv id
+ * @fcloop_id0 : loopid on fc loop 0
+ * @fcloop_id1 : loopid on fc loop 1
+ * @fcloop_state_counter : Indicates loop state changed
+ * @fcloop_state0 : state of fc loop 0
+ * @fcloop_state1 : state of fc loop 1
+ * @fcloop_state_rsvd :
+ */
+typedef struct {
+ uint32_t global_counter;
+ uint8_t param_counter;
+ uint8_t param_id;
+ uint16_t param_val;
+ uint8_t write_config_counter;
+ uint8_t write_config_rsvd[3];
+ uint8_t ldrv_op_counter;
+ uint8_t ldrv_opid;
+ uint8_t ldrv_opcmd;
+ uint8_t ldrv_opstatus;
+ uint8_t ldrv_state_counter;
+ uint8_t ldrv_state_id;
+ uint8_t ldrv_state_new;
+ uint8_t ldrv_state_old;
+ uint8_t pdrv_state_counter;
+ uint8_t pdrv_state_id;
+ uint8_t pdrv_state_new;
+ uint8_t pdrv_state_old;
+ uint8_t pdrv_fmt_counter;
+ uint8_t pdrv_fmt_id;
+ uint8_t pdrv_fmt_val;
+ uint8_t pdrv_fmt_rsvd;
+ uint8_t targ_xfer_counter;
+ uint8_t targ_xfer_id;
+ uint8_t targ_xfer_val;
+ uint8_t targ_xfer_rsvd;
+ uint8_t fcloop_id_chg_counter;
+ uint8_t fcloopid_pdrvid;
+ uint8_t fcloop_id0;
+ uint8_t fcloop_id1;
+ uint8_t fcloop_state_counter;
+ uint8_t fcloop_state0;
+ uint8_t fcloop_state1;
+ uint8_t fcloop_state_rsvd;
+} __attribute__ ((packed)) mraid_notify_t;
+
+
+/**
+ * mraid_inquiry3_t - enquiry for device information
+ *
+ * @data_size : current size in bytes (not including resvd)
+ * @notify :
+ * @notify_rsvd :
+ * @rebuild_rate : rebuild rate (0% - 100%)
+ * @cache_flush_int : cache flush interval in seconds
+ * @sense_alert :
+ * @drive_insert_count : drive insertion count
+ * @battery_status :
+ * @num_ldrv : no. of Log Drives configured
+ * @recon_state : state of reconstruct
+ * @ldrv_op_status : logdrv Status
+ * @ldrv_size : size of each log drv
+ * @ldrv_prop :
+ * @ldrv_state : state of log drives
+ * @pdrv_state : state of phys drvs.
+ * @pdrv_format :
+ * @targ_xfer : phys device transfer rate
+ * @pad1k : 761 + 263reserved = 1024 bytes total size
+ */
+#define MAX_NOTIFY_SIZE 0x80
+#define CUR_NOTIFY_SIZE sizeof(mraid_notify_t)
+
+typedef struct {
+ uint32_t data_size;
+
+ mraid_notify_t notify;
+
+ uint8_t notify_rsvd[MAX_NOTIFY_SIZE - CUR_NOTIFY_SIZE];
+
+ uint8_t rebuild_rate;
+ uint8_t cache_flush_int;
+ uint8_t sense_alert;
+ uint8_t drive_insert_count;
+
+ uint8_t battery_status;
+ uint8_t num_ldrv;
+ uint8_t recon_state[MAX_LOGICAL_DRIVES_40LD / 8];
+ uint16_t ldrv_op_status[MAX_LOGICAL_DRIVES_40LD / 8];
+
+ uint32_t ldrv_size[MAX_LOGICAL_DRIVES_40LD];
+ uint8_t ldrv_prop[MAX_LOGICAL_DRIVES_40LD];
+ uint8_t ldrv_state[MAX_LOGICAL_DRIVES_40LD];
+ uint8_t pdrv_state[FC_MAX_PHYSICAL_DEVICES];
+ uint16_t pdrv_format[FC_MAX_PHYSICAL_DEVICES / 16];
+
+ uint8_t targ_xfer[80];
+ uint8_t pad1k[263];
+} __attribute__ ((packed)) mraid_inquiry3_t;
+
+
+/**
+ * mraid_adapinfo_t - information about the adapter
+ * @max_commands : max concurrent commands supported
+ * @rebuild_rate : rebuild rate - 0% thru 100%
+ * @max_targ_per_chan : max targ per channel
+ * @nchannels : number of channels on HBA
+ * @fw_version : firmware version
+ * @age_of_flash : number of times FW has been flashed
+ * @chip_set_value : contents of 0xC0000832
+ * @dram_size : in MB
+ * @cache_flush_interval : in seconds
+ * @bios_version :
+ * @board_type :
+ * @sense_alert :
+ * @write_config_count : increase with every configuration change
+ * @drive_inserted_count : increase with every drive inserted
+ * @inserted_drive : channel:Id of inserted drive
+ * @battery_status : bit 0: battery module missing
+ * bit 1: VBAD
+ * bit 2: temprature high
+ * bit 3: battery pack missing
+ * bit 4,5:
+ * 00 - charge complete
+ * 01 - fast charge in progress
+ * 10 - fast charge fail
+ * 11 - undefined
+ * bit 6: counter > 1000
+ * bit 7: Undefined
+ * @dec_fault_bus_info :
+ */
+typedef struct {
+ uint8_t max_commands;
+ uint8_t rebuild_rate;
+ uint8_t max_targ_per_chan;
+ uint8_t nchannels;
+ uint8_t fw_version[4];
+ uint16_t age_of_flash;
+ uint8_t chip_set_value;
+ uint8_t dram_size;
+ uint8_t cache_flush_interval;
+ uint8_t bios_version[4];
+ uint8_t board_type;
+ uint8_t sense_alert;
+ uint8_t write_config_count;
+ uint8_t battery_status;
+ uint8_t dec_fault_bus_info;
+} __attribute__ ((packed)) mraid_adapinfo_t;
+
+
+/**
+ * mraid_ldrv_info_t - information about the logical drives
+ * @nldrv : Number of logical drives configured
+ * @rsvd :
+ * @size : size of each logical drive
+ * @prop :
+ * @state : state of each logical drive
+ */
+typedef struct {
+ uint8_t nldrv;
+ uint8_t rsvd[3];
+ uint32_t size[MAX_LOGICAL_DRIVES_8LD];
+ uint8_t prop[MAX_LOGICAL_DRIVES_8LD];
+ uint8_t state[MAX_LOGICAL_DRIVES_8LD];
+} __attribute__ ((packed)) mraid_ldrv_info_t;
+
+
+/**
+ * mraid_pdrv_info_t - information about the physical drives
+ * @pdrv_state : state of each physical drive
+ */
+typedef struct {
+ uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];
+ uint8_t rsvd;
+} __attribute__ ((packed)) mraid_pdrv_info_t;
+
+
+/**
+ * mraid_inquiry_t - RAID inquiry, mailbox command 0x05
+ * @mraid_adapinfo_t : adapter information
+ * @mraid_ldrv_info_t : logical drives information
+ * @mraid_pdrv_info_t : physical drives information
+ */
+typedef struct {
+ mraid_adapinfo_t adapter_info;
+ mraid_ldrv_info_t logdrv_info;
+ mraid_pdrv_info_t pdrv_info;
+} __attribute__ ((packed)) mraid_inquiry_t;
+
+
+/**
+ * mraid_extinq_t - RAID extended inquiry, mailbox command 0x04
+ *
+ * @raid_inq : raid inquiry
+ * @phys_drv_format :
+ * @stack_attn :
+ * @modem_status :
+ * @rsvd :
+ */
+typedef struct {
+ mraid_inquiry_t raid_inq;
+ uint16_t phys_drv_format[MAX_MBOX_CHANNELS];
+ uint8_t stack_attn;
+ uint8_t modem_status;
+ uint8_t rsvd[2];
+} __attribute__ ((packed)) mraid_extinq_t;
+
+
+/**
+ * adap_device_t - device information
+ * @channel : channel fpor the device
+ * @target : target ID of the device
+ */
+typedef struct {
+ uint8_t channel;
+ uint8_t target;
+}__attribute__ ((packed)) adap_device_t;
+
+
+/**
+ * adap_span_40ld_t - 40LD span
+ * @start_blk : starting block
+ * @num_blks : number of blocks
+ */
+typedef struct {
+ uint32_t start_blk;
+ uint32_t num_blks;
+ adap_device_t device[MAX_ROW_SIZE_40LD];
+}__attribute__ ((packed)) adap_span_40ld_t;
+
+
+/**
+ * adap_span_8ld_t - 8LD span
+ * @start_blk : starting block
+ * @num_blks : number of blocks
+ */
+typedef struct {
+ uint32_t start_blk;
+ uint32_t num_blks;
+ adap_device_t device[MAX_ROW_SIZE_8LD];
+}__attribute__ ((packed)) adap_span_8ld_t;
+
+
+/**
+ * logdrv_param_t - logical drives parameters
+ *
+ * @span_depth : total number of spans
+ * @level : RAID level
+ * @read_ahead : read ahead, no read ahead, adaptive read ahead
+ * @stripe_sz : encoded stripe size
+ * @status : status of the logical drive
+ * @write_mode : write mode, write_through/write_back
+ * @direct_io : direct io or through cache
+ * @row_size : number of stripes in a row
+ */
+typedef struct {
+ uint8_t span_depth;
+ uint8_t level;
+ uint8_t read_ahead;
+ uint8_t stripe_sz;
+ uint8_t status;
+ uint8_t write_mode;
+ uint8_t direct_io;
+ uint8_t row_size;
+} __attribute__ ((packed)) logdrv_param_t;
+
+
+/**
+ * logdrv_40ld_t - logical drive definition for 40LD controllers
+ * @lparam : logical drives parameters
+ * @span : span
+ */
+typedef struct {
+ logdrv_param_t lparam;
+ adap_span_40ld_t span[SPAN_DEPTH_8_SPANS];
+}__attribute__ ((packed)) logdrv_40ld_t;
+
+
+/**
+ * logdrv_8ld_span8_t - logical drive definition for 8LD controllers
+ * @lparam : logical drives parameters
+ * @span : span
+ *
+ * 8-LD logical drive with upto 8 spans
+ */
+typedef struct {
+ logdrv_param_t lparam;
+ adap_span_8ld_t span[SPAN_DEPTH_8_SPANS];
+}__attribute__ ((packed)) logdrv_8ld_span8_t;
+
+
+/**
+ * logdrv_8ld_span4_t - logical drive definition for 8LD controllers
+ * @lparam : logical drives parameters
+ * @span : span
+ *
+ * 8-LD logical drive with upto 4 spans
+ */
+typedef struct {
+ logdrv_param_t lparam;
+ adap_span_8ld_t span[SPAN_DEPTH_4_SPANS];
+}__attribute__ ((packed)) logdrv_8ld_span4_t;
+
+
+/**
+ * phys_drive_t - physical device information
+ * @type : Type of the device
+ * @cur_status : current status of the device
+ * @tag_depth : Level of tagging
+ * @sync_neg : sync negotiation - ENABLE or DISBALE
+ * @size : configurable size in terms of 512 byte
+ */
+typedef struct {
+ uint8_t type;
+ uint8_t cur_status;
+ uint8_t tag_depth;
+ uint8_t sync_neg;
+ uint32_t size;
+}__attribute__ ((packed)) phys_drive_t;
+
+
+/**
+ * disk_array_40ld_t - disk array for 40LD controllers
+ * @numldrv : number of logical drives
+ * @resvd :
+ * @ldrv : logical drives information
+ * @pdrv : physical drives information
+ */
+typedef struct {
+ uint8_t numldrv;
+ uint8_t resvd[3];
+ logdrv_40ld_t ldrv[MAX_LOGICAL_DRIVES_40LD];
+ phys_drive_t pdrv[MBOX_MAX_PHYSICAL_DRIVES];
+}__attribute__ ((packed)) disk_array_40ld_t;
+
+
+/**
+ * disk_array_8ld_span8_t - disk array for 8LD controllers
+ * @numldrv : number of logical drives
+ * @resvd :
+ * @ldrv : logical drives information
+ * @pdrv : physical drives information
+ *
+ * Disk array for 8LD logical drives with upto 8 spans
+ */
+typedef struct {
+ uint8_t numldrv;
+ uint8_t resvd[3];
+ logdrv_8ld_span8_t ldrv[MAX_LOGICAL_DRIVES_8LD];
+ phys_drive_t pdrv[MBOX_MAX_PHYSICAL_DRIVES];
+}__attribute__ ((packed)) disk_array_8ld_span8_t;
+
+
+/**
+ * disk_array_8ld_span4_t - disk array for 8LD controllers
+ * @numldrv : number of logical drives
+ * @resvd :
+ * @ldrv : logical drives information
+ * @pdrv : physical drives information
+ *
+ * Disk array for 8LD logical drives with upto 4 spans
+ */
+typedef struct {
+ uint8_t numldrv;
+ uint8_t resvd[3];
+ logdrv_8ld_span4_t ldrv[MAX_LOGICAL_DRIVES_8LD];
+ phys_drive_t pdrv[MBOX_MAX_PHYSICAL_DRIVES];
+}__attribute__ ((packed)) disk_array_8ld_span4_t;
+
+
+/**
+ * private_bios_data - bios private data for boot devices
+ * @geometry : bits 0-3 - BIOS geometry, 0x0001 - 1GB, 0x0010 - 2GB,
+ * 0x1000 - 8GB, Others values are invalid
+ * @unused : bits 4-7 are unused
+ * @boot_drv : logical drive set as boot drive, 0..7 - for 8LD cards,
+ * 0..39 - for 40LD cards
+ * @cksum : 0-(sum of first 13 bytes of this structure)
+ */
+struct private_bios_data {
+ uint8_t geometry :4;
+ uint8_t unused :4;
+ uint8_t boot_drv;
+ uint8_t rsvd[12];
+ uint16_t cksum;
+} __attribute__ ((packed));
+
+
+/**
+ * mbox_sgl64 - 64-bit scatter list for mailbox based controllers
+ * @address : address of the buffer
+ * @length : data transfer length
+ */
+typedef struct {
+ uint64_t address;
+ uint32_t length;
+} __attribute__ ((packed)) mbox_sgl64;
+
+/**
+ * mbox_sgl32 - 32-bit scatter list for mailbox based controllers
+ * @address : address of the buffer
+ * @length : data transfer length
+ */
+typedef struct {
+ uint32_t address;
+ uint32_t length;
+} __attribute__ ((packed)) mbox_sgl32;
+
+#endif // _MRAID_MBOX_DEFS_H_
+
+/* vim: set ts=8 sw=8 tw=78: */
--- /dev/null
+/*
+ *
+ * Linux MegaRAID device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : mega_common.h
+ *
+ * Libaray of common routine used by all low-level megaraid drivers
+ */
+
+#ifndef _MEGA_COMMON_H_
+#define _MEGA_COMMON_H_
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/blkdev.h>
+#include <linux/list.h>
+#include <linux/version.h>
+#include <linux/moduleparam.h>
+#include <asm/semaphore.h>
+#include <scsi/scsi.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_device.h>
+#include <scsi/scsi_host.h>
+
+
+#define LSI_MAX_CHANNELS 16
+#define LSI_MAX_LOGICAL_DRIVES_64LD (64+1)
+
+
+/**
+ * scb_t - scsi command control block
+ * @param ccb : command control block for individual driver
+ * @param list : list of control blocks
+ * @param gp : general purpose field for LLDs
+ * @param sno : all SCBs have a serial number
+ * @param scp : associated scsi command
+ * @param state : current state of scb
+ * @param dma_dir : direction of data transfer
+ * @param dma_type : transfer with sg list, buffer, or no data transfer
+ * @param dev_channel : actual channel on the device
+ * @param dev_target : actual target on the device
+ * @param status : completion status
+ *
+ * This is our central data structure to issue commands the each driver.
+ * Driver specific data structures are maintained in the ccb field.
+ * scb provides a field 'gp', which can be used by LLD for its own purposes
+ *
+ * dev_channel and dev_target must be initialized with the actual channel and
+ * target on the controller.
+ */
+typedef struct {
+ caddr_t ccb;
+ struct list_head list;
+ unsigned long gp;
+ unsigned int sno;
+ struct scsi_cmnd *scp;
+ uint32_t state;
+ uint32_t dma_direction;
+ uint32_t dma_type;
+ uint16_t dev_channel;
+ uint16_t dev_target;
+ uint32_t status;
+} scb_t;
+
+/*
+ * SCB states as it transitions from one state to another
+ */
+#define SCB_FREE 0x0000 /* on the free list */
+#define SCB_ACTIVE 0x0001 /* off the free list */
+#define SCB_PENDQ 0x0002 /* on the pending queue */
+#define SCB_ISSUED 0x0004 /* issued - owner f/w */
+#define SCB_ABORT 0x0008 /* Got an abort for this one */
+#define SCB_RESET 0x0010 /* Got a reset for this one */
+
+/*
+ * DMA types for scb
+ */
+#define MRAID_DMA_NONE 0x0000 /* no data transfer for this command */
+#define MRAID_DMA_WSG 0x0001 /* data transfer using a sg list */
+#define MRAID_DMA_WBUF 0x0002 /* data transfer using a contiguous buffer */
+
+
+/**
+ * struct adapter_t - driver's initialization structure
+ * @param dpc_h : tasklet handle
+ * @param pdev : pci configuration pointer for kernel
+ * @param host : pointer to host structure of mid-layer
+ * @param host_lock : pointer to appropriate lock
+ * @param lock : synchronization lock for mid-layer and driver
+ * @param quiescent : driver is quiescent for now.
+ * @param outstanding_cmds : number of commands pending in the driver
+ * @param kscb_list : pointer to the bulk of SCBs pointers for IO
+ * @param kscb_pool : pool of free scbs for IO
+ * @param kscb_pool_lock : lock for pool of free scbs
+ * @param pend_list : pending commands list
+ * @param pend_list_lock : exlusion lock for pending commands list
+ * @param completed_list : list of completed commands
+ * @param completed_list_lock : exclusion lock for list of completed commands
+ * @param sglen : max sg elements supported
+ * @param device_ids : to convert kernel device addr to our devices.
+ * @param raid_device : raid adapter specific pointer
+ * @param max_channel : maximum channel number supported - inclusive
+ * @param max_target : max target supported - inclusive
+ * @param max_lun : max lun supported - inclusive
+ * @param unique_id : unique identifier for each adapter
+ * @param irq : IRQ for this adapter
+ * @param ito : internal timeout value, (-1) means no timeout
+ * @param ibuf : buffer to issue internal commands
+ * @param ibuf_dma_h : dma handle for the above buffer
+ * @param uscb_list : SCB pointers for user cmds, common mgmt module
+ * @param uscb_pool : pool of SCBs for user commands
+ * @param uscb_pool_lock : exclusion lock for these SCBs
+ * @param max_cmds : max outstanding commands
+ * @param fw_version : firmware version
+ * @param bios_version : bios version
+ * @param max_cdb_sz : biggest CDB size supported.
+ * @param ha : is high availability present - clustering
+ * @param init_id : initiator ID, the default value should be 7
+ * @param max_sectors : max sectors per request
+ * @param cmd_per_lun : max outstanding commands per LUN
+ * @param being_detached : set when unloading, no more mgmt calls
+ *
+ *
+ * mraid_setup_device_map() can be called anytime after the device map is
+ * available and MRAID_GET_DEVICE_MAP() can be called whenever the mapping is
+ * required, usually from LLD's queue entry point. The formar API sets up the
+ * MRAID_IS_LOGICAL(adapter_t *, struct scsi_cmnd *) to find out if the
+ * device in question is a logical drive.
+ *
+ * quiescent flag should be set by the driver if it is not accepting more
+ * commands
+ *
+ * NOTE: The fields of this structures are placed to minimize cache misses
+ */
+
+// amount of space required to store the bios and firmware version strings
+#define VERSION_SIZE 16
+
+typedef struct {
+ struct tasklet_struct dpc_h;
+ struct pci_dev *pdev;
+ struct Scsi_Host *host;
+ spinlock_t *host_lock;
+ spinlock_t lock;
+ uint8_t quiescent;
+ int outstanding_cmds;
+ scb_t *kscb_list;
+ struct list_head kscb_pool;
+ spinlock_t kscb_pool_lock;
+ struct list_head pend_list;
+ spinlock_t pend_list_lock;
+ struct list_head completed_list;
+ spinlock_t completed_list_lock;
+ uint16_t sglen;
+ int device_ids[LSI_MAX_CHANNELS]
+ [LSI_MAX_LOGICAL_DRIVES_64LD];
+ caddr_t raid_device;
+ uint8_t max_channel;
+ uint16_t max_target;
+ uint8_t max_lun;
+
+ uint32_t unique_id;
+ uint8_t irq;
+ uint8_t ito;
+ caddr_t ibuf;
+ dma_addr_t ibuf_dma_h;
+ scb_t *uscb_list;
+ struct list_head uscb_pool;
+ spinlock_t uscb_pool_lock;
+ int max_cmds;
+ uint8_t fw_version[VERSION_SIZE];
+ uint8_t bios_version[VERSION_SIZE];
+ uint8_t max_cdb_sz;
+ uint8_t ha;
+ uint16_t init_id;
+ uint16_t max_sectors;
+ uint16_t cmd_per_lun;
+ atomic_t being_detached;
+} adapter_t;
+
+#define SCSI_FREE_LIST_LOCK(adapter) (&adapter->kscb_pool_lock)
+#define USER_FREE_LIST_LOCK(adapter) (&adapter->uscb_pool_lock)
+#define PENDING_LIST_LOCK(adapter) (&adapter->pend_list_lock)
+#define COMPLETED_LIST_LOCK(adapter) (&adapter->completed_list_lock)
+
+
+// conversion from scsi command
+#define SCP2HOST(scp) (scp)->device->host // to host
+#define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata // to soft state
+#define SCP2CHANNEL(scp) (scp)->device->channel // to channel
+#define SCP2TARGET(scp) (scp)->device->id // to target
+#define SCP2LUN(scp) (scp)->device->lun // to LUN
+
+// generic macro to convert scsi command and host to controller's soft state
+#define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
+#define SCP2ADAPTER(scp) (adapter_t *)SCSIHOST2ADAP(SCP2HOST(scp))
+
+
+/**
+ * MRAID_GET_DEVICE_MAP - device ids
+ * @param adp - Adapter's soft state
+ * @param scp - mid-layer scsi command pointer
+ * @param p_chan - physical channel on the controller
+ * @param target - target id of the device or logical drive number
+ * @param islogical - set if the command is for the logical drive
+ *
+ * Macro to retrieve information about device class, logical or physical and
+ * the corresponding physical channel and target or logical drive number
+ **/
+#define MRAID_IS_LOGICAL(adp, scp) \
+ (SCP2CHANNEL(scp) == (adp)->max_channel) ? 1 : 0
+
+#define MRAID_GET_DEVICE_MAP(adp, scp, p_chan, target, islogical) \
+ /* \
+ * Is the request coming for the virtual channel \
+ */ \
+ islogical = MRAID_IS_LOGICAL(adp, scp); \
+ \
+ /* \
+ * Get an index into our table of drive ids mapping \
+ */ \
+ if (islogical) { \
+ p_chan = 0xFF; \
+ target = \
+ (adp)->device_ids[(adp)->max_channel][SCP2TARGET(scp)]; \
+ } \
+ else { \
+ p_chan = ((adp)->device_ids[SCP2CHANNEL(scp)] \
+ [SCP2TARGET(scp)] >> 8) & 0xFF; \
+ target = ((adp)->device_ids[SCP2CHANNEL(scp)] \
+ [SCP2TARGET(scp)] & 0xFF); \
+ }
+
+/*
+ * ### Helper routines ###
+ */
+#define LSI_DBGLVL mraid_debug_level // each LLD must define a global
+ // mraid_debug_level
+
+#ifdef DEBUG
+#if defined (_ASSERT_PANIC)
+#define ASSERT_ACTION panic
+#else
+#define ASSERT_ACTION printk
+#endif
+
+#define ASSERT(expression) \
+ if (!(expression)) { \
+ ASSERT_ACTION("assertion failed:(%s), file: %s, line: %d:%s\n", \
+ #expression, __FILE__, __LINE__, __FUNCTION__); \
+ }
+#else
+#define ASSERT(expression)
+#endif
+
+/*
+ * struct mraid_pci_blk - structure holds DMA memory block info
+ * @param vaddr : virtual address to a memory block
+ * @param dma_addr : DMA handle to a memory block
+ *
+ * This structure is filled up for the caller. It is the responsibilty of the
+ * caller to allocate this array big enough to store addresses for all
+ * requested elements
+ */
+struct mraid_pci_blk {
+ caddr_t vaddr;
+ dma_addr_t dma_addr;
+};
+
+#endif // _MEGA_COMMON_H_
+
+// vim: set ts=8 sw=8 tw=78:
--- /dev/null
+/*
+ *
+ * Linux MegaRAID device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : megaraid_ioctl.h
+ *
+ * Definitions to interface with user level applications
+ */
+
+#ifndef _MEGARAID_IOCTL_H_
+#define _MEGARAID_IOCTL_H_
+
+#include <linux/types.h>
+#include <asm/semaphore.h>
+
+#include "mbox_defs.h"
+
+/**
+ * con_log() - console log routine
+ * @param level : indicates the severity of the message.
+ * @fparam mt : format string
+ *
+ * con_log displays the error messages on the console based on the current
+ * debug level. Also it attaches the appropriate kernel severity level with
+ * the message.
+ *
+ *
+ * consolge messages debug levels
+ */
+#define CL_ANN 0 /* print unconditionally, announcements */
+#define CL_DLEVEL1 1 /* debug level 1, informative */
+#define CL_DLEVEL2 2 /* debug level 2, verbose */
+#define CL_DLEVEL3 3 /* debug level 3, very verbose */
+
+#define con_log(level, fmt) if (LSI_DBGLVL >= level) printk fmt;
+
+/*
+ * Definitions & Declarations needed to use common management module
+ */
+
+#define MEGAIOC_MAGIC 'm'
+#define MEGAIOCCMD _IOWR(MEGAIOC_MAGIC, 0, mimd_t)
+
+#define MEGAIOC_QNADAP 'm' /* Query # of adapters */
+#define MEGAIOC_QDRVRVER 'e' /* Query driver version */
+#define MEGAIOC_QADAPINFO 'g' /* Query adapter information */
+
+#define USCSICMD 0x80
+#define UIOC_RD 0x00001
+#define UIOC_WR 0x00002
+
+#define MBOX_CMD 0x00000
+#define GET_DRIVER_VER 0x10000
+#define GET_N_ADAP 0x20000
+#define GET_ADAP_INFO 0x30000
+#define GET_CAP 0x40000
+#define GET_STATS 0x50000
+#define GET_IOCTL_VERSION 0x01
+
+#define EXT_IOCTL_SIGN_SZ 16
+#define EXT_IOCTL_SIGN "$$_EXTD_IOCTL_$$"
+
+#define MBOX_LEGACY 0x00 /* ioctl has legacy mbox*/
+#define MBOX_HPE 0x01 /* ioctl has hpe mbox */
+
+#define APPTYPE_MIMD 0x00 /* old existing apps */
+#define APPTYPE_UIOC 0x01 /* new apps using uioc */
+
+#define IOCTL_ISSUE 0x00000001 /* Issue ioctl */
+#define IOCTL_ABORT 0x00000002 /* Abort previous ioctl */
+
+#define DRVRTYPE_MBOX 0x00000001 /* regular mbox driver */
+#define DRVRTYPE_HPE 0x00000002 /* new hpe driver */
+
+#define MKADAP(adapno) (MEGAIOC_MAGIC << 8 | (adapno) )
+#define GETADAP(mkadap) ((mkadap) ^ MEGAIOC_MAGIC << 8)
+
+#define MAX_DMA_POOLS 5 /* 4k, 8k, 16k, 32k, 64k*/
+
+
+/**
+ * struct uioc_t - the common ioctl packet structure
+ *
+ * @signature : Must be "$$_EXTD_IOCTL_$$"
+ * @mb_type : Type of the mail box (MB_LEGACY or MB_HPE)
+ * @app_type : Type of the issuing application (existing or new)
+ * @opcode : Opcode of the command
+ * @adapno : Adapter number
+ * @cmdbuf : Pointer to buffer - can point to mbox or plain data buffer
+ * @xferlen : xferlen for DCMD and non mailbox commands
+ * @data_dir : Direction of the data transfer
+ * @status : Status from the driver
+ * @reserved : reserved bytes for future expansion
+ *
+ * @user_data : user data transfer address is saved in this
+ * @user_data_len: length of the data buffer sent by user app
+ * @user_pthru : user passthru address is saves in this (null if DCMD)
+ * @pthru32 : kernel address passthru (allocated per kioc)
+ * @pthru32_h : physicall address of @pthru32
+ * @list : for kioc free pool list maintenance
+ * @done : call back routine for llds to call when kioc is completed
+ * @buf_vaddr : dma pool buffer attached to kioc for data transfer
+ * @buf_paddr : physical address of the dma pool buffer
+ * @pool_index : index of the dma pool that @buf_vaddr is taken from
+ * @free_buf : indicates if buffer needs to be freed after kioc completes
+ *
+ * Note : All LSI drivers understand only this packet. Any other
+ * : format sent by applications would be converted to this.
+ */
+typedef struct uioc {
+
+/* User Apps: */
+
+ uint8_t signature[EXT_IOCTL_SIGN_SZ];
+ uint16_t mb_type;
+ uint16_t app_type;
+ uint32_t opcode;
+ uint32_t adapno;
+ uint64_t cmdbuf;
+ uint32_t xferlen;
+ uint32_t data_dir;
+ int32_t status;
+ uint8_t reserved[128];
+
+/* Driver Data: */
+ void __user * user_data;
+ uint32_t user_data_len;
+ mraid_passthru_t __user *user_pthru;
+
+ mraid_passthru_t *pthru32;
+ dma_addr_t pthru32_h;
+
+ struct list_head list;
+ void (*done)(struct uioc*);
+
+ caddr_t buf_vaddr;
+ dma_addr_t buf_paddr;
+ uint8_t pool_index;
+ uint8_t free_buf;
+
+} __attribute__ ((aligned(1024),packed)) uioc_t;
+
+
+/**
+ * struct mraid_hba_info - information about the controller
+ *
+ * @param pci_vendor_id : PCI vendor id
+ * @param pci_device_id : PCI device id
+ * @param subsystem_vendor_id : PCI subsystem vendor id
+ * @param subsystem_device_id : PCI subsystem device id
+ * @param baseport : base port of hba memory
+ * @param pci_bus : PCI bus
+ * @param pci_dev_fn : PCI device/function values
+ * @param irq : interrupt vector for the device
+ *
+ * Extended information of 256 bytes about the controller. Align on the single
+ * byte boundary so that 32-bit applications can be run on 64-bit platform
+ * drivers withoug re-compilation.
+ * NOTE: reduce the number of reserved bytes whenever new field are added, so
+ * that total size of the structure remains 256 bytes.
+ */
+typedef struct mraid_hba_info {
+
+ uint16_t pci_vendor_id;
+ uint16_t pci_device_id;
+ uint16_t subsys_vendor_id;
+ uint16_t subsys_device_id;
+
+ uint64_t baseport;
+ uint8_t pci_bus;
+ uint8_t pci_dev_fn;
+ uint8_t pci_slot;
+ uint8_t irq;
+
+ uint32_t unique_id;
+ uint32_t host_no;
+
+ uint8_t num_ldrv;
+} __attribute__ ((aligned(256), packed)) mraid_hba_info_t;
+
+
+/**
+ * mcontroller : adapter info structure for old mimd_t apps
+ *
+ * @base : base address
+ * @irq : irq number
+ * @numldrv : number of logical drives
+ * @pcibus : pci bus
+ * @pcidev : pci device
+ * @pcifun : pci function
+ * @pciid : pci id
+ * @pcivendor : vendor id
+ * @pcislot : slot number
+ * @uid : unique id
+ */
+typedef struct mcontroller {
+
+ uint64_t base;
+ uint8_t irq;
+ uint8_t numldrv;
+ uint8_t pcibus;
+ uint16_t pcidev;
+ uint8_t pcifun;
+ uint16_t pciid;
+ uint16_t pcivendor;
+ uint8_t pcislot;
+ uint32_t uid;
+
+} __attribute__ ((packed)) mcontroller_t;
+
+
+/**
+ * mm_dmapool_t : Represents one dma pool with just one buffer
+ *
+ * @vaddr : Virtual address
+ * @paddr : DMA physicall address
+ * @bufsize : In KB - 4 = 4k, 8 = 8k etc.
+ * @handle : Handle to the dma pool
+ * @lock : lock to synchronize access to the pool
+ * @in_use : If pool already in use, attach new block
+ */
+typedef struct mm_dmapool {
+ caddr_t vaddr;
+ dma_addr_t paddr;
+ uint32_t buf_size;
+ struct dma_pool *handle;
+ spinlock_t lock;
+ uint8_t in_use;
+} mm_dmapool_t;
+
+
+/**
+ * mraid_mmadp_t: Structure that drivers pass during (un)registration
+ *
+ * @unique_id : Any unique id (usually PCI bus+dev+fn)
+ * @drvr_type : megaraid or hpe (DRVRTYPE_MBOX or DRVRTYPE_HPE)
+ * @drv_data : Driver specific; not touched by the common module
+ * @timeout : timeout for issued kiocs
+ * @max_kioc : Maximum ioctl packets acceptable by the lld
+ * @pdev : pci dev; used for allocating dma'ble memory
+ * @issue_uioc : Driver supplied routine to issue uioc_t commands
+ * : issue_uioc(drvr_data, kioc, ISSUE/ABORT, uioc_done)
+ * @list : attach with the global list of adapters
+ * @kioc_list : block of mem for @max_kioc number of kiocs
+ * @kioc_pool : pool of free kiocs
+ * @kioc_pool_lock : protection for free pool
+ * @kioc_semaphore : so as not to exceed @max_kioc parallel ioctls
+ * @mbox_list : block of mem for @max_kioc number of mboxes
+ * @pthru_dma_pool : DMA pool to allocate passthru packets
+ * @dma_pool_list : array of dma pools
+ */
+
+typedef struct mraid_mmadp {
+
+/* Filled by driver */
+
+ uint32_t unique_id;
+ uint32_t drvr_type;
+ unsigned long drvr_data;
+ uint8_t timeout;
+ uint8_t max_kioc;
+
+ struct pci_dev *pdev;
+
+ int(*issue_uioc)(unsigned long, uioc_t *, uint32_t);
+
+/* Maintained by common module */
+
+ struct list_head list;
+ uioc_t *kioc_list;
+ struct list_head kioc_pool;
+ spinlock_t kioc_pool_lock;
+ struct semaphore kioc_semaphore;
+
+ mbox64_t *mbox_list;
+ struct dma_pool *pthru_dma_pool;
+ mm_dmapool_t dma_pool_list[MAX_DMA_POOLS];
+
+} mraid_mmadp_t;
+
+int mraid_mm_register_adp(mraid_mmadp_t *);
+int mraid_mm_unregister_adp(uint32_t);
+
+#endif /* _MEGARAID_IOCTL_H_ */
--- /dev/null
+/*
+ *
+ * Linux MegaRAID device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : megaraid_mbox.c
+ * Version : v2.20.4 (September 27 2004)
+ *
+ * Authors:
+ * Atul Mukker <Atul.Mukker@lsil.com>
+ * Sreenivas Bagalkote <Sreenivas.Bagalkote@lsil.com>
+ * Manoj Jose <Manoj.Jose@lsil.com>
+ *
+ * List of supported controllers
+ *
+ * OEM Product Name VID DID SSVID SSID
+ * --- ------------ --- --- ---- ----
+ * Dell PERC3/QC 101E 1960 1028 0471
+ * Dell PERC3/DC 101E 1960 1028 0493
+ * Dell PERC3/SC 101E 1960 1028 0475
+ * Dell PERC3/Di 1028 1960 1028 0123
+ * Dell PERC4/SC 1000 1960 1028 0520
+ * Dell PERC4/DC 1000 1960 1028 0518
+ * Dell PERC4/QC 1000 0407 1028 0531
+ * Dell PERC4/Di 1028 000F 1028 014A
+ * Dell PERC 4e/Si 1028 0013 1028 016c
+ * Dell PERC 4e/Di 1028 0013 1028 016d
+ * Dell PERC 4e/Di 1028 0013 1028 016e
+ * Dell PERC 4e/Di 1028 0013 1028 016f
+ * Dell PERC 4e/Di 1028 0013 1028 0170
+ * Dell PERC 4e/DC 1000 0408 1028 0002
+ * Dell PERC 4e/SC 1000 0408 1028 0001
+ *
+ *
+ * LSI MegaRAID SCSI 320-0 1000 1960 1000 A520
+ * LSI MegaRAID SCSI 320-1 1000 1960 1000 0520
+ * LSI MegaRAID SCSI 320-2 1000 1960 1000 0518
+ * LSI MegaRAID SCSI 320-0X 1000 0407 1000 0530
+ * LSI MegaRAID SCSI 320-2X 1000 0407 1000 0532
+ * LSI MegaRAID SCSI 320-4X 1000 0407 1000 0531
+ * LSI MegaRAID SCSI 320-1E 1000 0408 1000 0001
+ * LSI MegaRAID SCSI 320-2E 1000 0408 1000 0002
+ * LSI MegaRAID SATA 150-4 1000 1960 1000 4523
+ * LSI MegaRAID SATA 150-6 1000 1960 1000 0523
+ * LSI MegaRAID SATA 300-4X 1000 0409 1000 3004
+ * LSI MegaRAID SATA 300-8X 1000 0409 1000 3008
+ *
+ * INTEL RAID Controller SRCU42X 1000 0407 8086 0532
+ * INTEL RAID Controller SRCS16 1000 1960 8086 0523
+ * INTEL RAID Controller SRCU42E 1000 0408 8086 0002
+ * INTEL RAID Controller SRCZCRX 1000 0407 8086 0530
+ * INTEL RAID Controller SRCS28X 1000 0409 8086 3008
+ * INTEL RAID Controller SROMBU42E 1000 0408 8086 3431
+ * INTEL RAID Controller SROMBU42E 1000 0408 8086 3499
+ * INTEL RAID Controller SRCU51L 1000 1960 8086 0520
+ *
+ *
+ * FSC MegaRAID PCI Express ROMB 1000 0408 1734 1065
+ *
+ *
+ * ACER MegaRAID ROMB-2E 1000 0408 1025 004D
+ *
+ *
+ * For history of changes, see Documentation/ChangeLog.megaraid
+ */
+
+#include "megaraid_mbox.h"
+
+static int megaraid_init(void);
+static void megaraid_exit(void);
+
+static int megaraid_probe_one(struct pci_dev*, const struct pci_device_id *);
+static void megaraid_detach_one(struct pci_dev *);
+static void megaraid_mbox_shutdown(struct device *);
+
+static int megaraid_io_attach(adapter_t *);
+static void megaraid_io_detach(adapter_t *);
+
+static int megaraid_init_mbox(adapter_t *);
+static void megaraid_fini_mbox(adapter_t *);
+
+static int megaraid_alloc_cmd_packets(adapter_t *);
+static void megaraid_free_cmd_packets(adapter_t *);
+
+static int megaraid_mbox_setup_dma_pools(adapter_t *);
+static void megaraid_mbox_teardown_dma_pools(adapter_t *);
+
+static int megaraid_abort_handler(struct scsi_cmnd *);
+static int megaraid_reset_handler(struct scsi_cmnd *);
+
+static int mbox_post_sync_cmd(adapter_t *, uint8_t []);
+static int mbox_post_sync_cmd_fast(adapter_t *, uint8_t []);
+static int megaraid_busywait_mbox(mraid_device_t *);
+static int megaraid_mbox_product_info(adapter_t *);
+static int megaraid_mbox_extended_cdb(adapter_t *);
+static int megaraid_mbox_support_ha(adapter_t *, uint16_t *);
+static int megaraid_mbox_support_random_del(adapter_t *);
+static int megaraid_mbox_get_max_sg(adapter_t *);
+static void megaraid_mbox_enum_raid_scsi(adapter_t *);
+static void megaraid_mbox_flush_cache(adapter_t *);
+
+static void megaraid_mbox_display_scb(adapter_t *, scb_t *);
+static void megaraid_mbox_setup_device_map(adapter_t *);
+
+static int megaraid_queue_command(struct scsi_cmnd *,
+ void (*)(struct scsi_cmnd *));
+static scb_t *megaraid_mbox_build_cmd(adapter_t *, struct scsi_cmnd *, int *);
+static void megaraid_mbox_runpendq(adapter_t *, scb_t *);
+static void megaraid_mbox_prepare_pthru(adapter_t *, scb_t *,
+ struct scsi_cmnd *);
+static void megaraid_mbox_prepare_epthru(adapter_t *, scb_t *,
+ struct scsi_cmnd *);
+
+static irqreturn_t megaraid_isr(int, void *, struct pt_regs *);
+
+static void megaraid_mbox_dpc(unsigned long);
+
+static int megaraid_cmm_register(adapter_t *);
+static int megaraid_cmm_unregister(adapter_t *);
+static int megaraid_mbox_mm_handler(unsigned long, uioc_t *, uint32_t);
+static int megaraid_mbox_mm_command(adapter_t *, uioc_t *);
+static void megaraid_mbox_mm_done(adapter_t *, scb_t *);
+static int gather_hbainfo(adapter_t *, mraid_hba_info_t *);
+static int wait_till_fw_empty(adapter_t *);
+
+
+
+MODULE_AUTHOR("LSI Logic Corporation");
+MODULE_DESCRIPTION("LSI Logic MegaRAID Mailbox Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(MEGARAID_VERSION);
+
+/*
+ * ### modules parameters for driver ###
+ */
+
+/**
+ * Set to enable driver to expose unconfigured disk to kernel
+ */
+static int megaraid_expose_unconf_disks = 0;
+module_param_named(unconf_disks, megaraid_expose_unconf_disks, int, 0);
+MODULE_PARM_DESC(unconf_disks,
+ "Set to expose unconfigured disks to kernel (default=0)");
+
+/**
+ * driver wait time if the adapter's mailbox is busy
+ */
+static unsigned int max_mbox_busy_wait = MBOX_BUSY_WAIT;
+module_param_named(busy_wait, max_mbox_busy_wait, int, 0);
+MODULE_PARM_DESC(busy_wait,
+ "Max wait for mailbox in microseconds if busy (default=10)");
+
+/**
+ * number of sectors per IO command
+ */
+static unsigned int megaraid_max_sectors = MBOX_MAX_SECTORS;
+module_param_named(max_sectors, megaraid_max_sectors, int, 0);
+MODULE_PARM_DESC(max_sectors,
+ "Maximum number of sectors per IO command (default=128)");
+
+/**
+ * number of commands per logical unit
+ */
+static unsigned int megaraid_cmd_per_lun = MBOX_DEF_CMD_PER_LUN;
+module_param_named(cmd_per_lun, megaraid_cmd_per_lun, int, 0);
+MODULE_PARM_DESC(cmd_per_lun,
+ "Maximum number of commands per logical unit (default=64)");
+
+
+/**
+ * Fast driver load option, skip scanning for physical devices during load.
+ * This would result in non-disk devices being skipped during driver load
+ * time. These can be later added though, using /proc/scsi/scsi
+ */
+static unsigned int megaraid_fast_load = 0;
+module_param_named(fast_load, megaraid_fast_load, int, 0);
+MODULE_PARM_DESC(fast_load,
+ "Faster loading of the driver, skips physical devices! (default=0)");
+
+
+/**
+ * mraid_debug level - threshold for amount of information to be displayed by
+ * the driver. This level can be changed through modules parameters, ioctl or
+ * sysfs/proc interface. By default, print the announcement messages only.
+ */
+int mraid_debug_level = CL_ANN;
+module_param_named(debug_level, mraid_debug_level, int, 0);
+MODULE_PARM_DESC(debug_level, "Debug level for driver (default=0)");
+
+/*
+ * ### global data ###
+ */
+static uint8_t megaraid_mbox_version[8] =
+ { 0x02, 0x20, 0x04, 0x00, 9, 27, 20, 4 };
+
+
+/*
+ * PCI table for all supported controllers.
+ */
+static struct pci_device_id pci_id_table_g[] = {
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4_DI_DISCOVERY,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4_DI_DISCOVERY,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_PERC4_SC,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4_SC,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_PERC4_DC,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4_DC,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_PERC4_QC,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4_QC,
+ },
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4_DI_EVERGLADES,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4_DI_EVERGLADES,
+ },
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4E_SI_BIGBEND,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_SI_BIGBEND,
+ },
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4E_DI_KOBUK,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_DI_KOBUK,
+ },
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4E_DI_CORVETTE,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_DI_CORVETTE,
+ },
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4E_DI_EXPEDITION,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION,
+ },
+ {
+ PCI_VENDOR_ID_DELL,
+ PCI_DEVICE_ID_PERC4E_DI_GUADALUPE,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_PERC4E_DC_320_2E,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_DC_320_2E,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_PERC4E_SC_320_1E,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC4E_SC_320_1E,
+ },
+ {
+ PCI_VENDOR_ID_AMI,
+ PCI_DEVICE_ID_AMI_MEGARAID3,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC3_QC,
+ },
+ {
+ PCI_VENDOR_ID_AMI,
+ PCI_DEVICE_ID_AMI_MEGARAID3,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC3_DC,
+ },
+ {
+ PCI_VENDOR_ID_AMI,
+ PCI_DEVICE_ID_AMI_MEGARAID3,
+ PCI_VENDOR_ID_DELL,
+ PCI_SUBSYS_ID_PERC3_SC,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_0,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_0,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_1,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_1,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_2,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_2,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_0x,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_0x,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_2x,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_2x,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_4x,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_4x,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_1E,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_1E,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SCSI_320_2E,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SCSI_320_2E,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_I4_133_RAID,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_I4_133_RAID,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SATA_150_4,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SATA_150_4,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SATA_150_6,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SATA_150_6,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SATA_300_4x,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SATA_300_4x,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_SATA_300_8x,
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_SUBSYS_ID_MEGARAID_SATA_300_8x,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SRCU42X,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SRCU42X,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SRCS16,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SRCS16,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SRCU42E,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SRCU42E,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SRCZCRX,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SRCZCRX,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SRCS28X,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SRCS28X,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SROMBU42E_ALIEF,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SROMBU42E_ALIEF,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SROMBU42E_HARWICH,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SROMBU42E_HARWICH,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK,
+ PCI_VENDOR_ID_INTEL,
+ PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_FSC_MEGARAID_PCI_EXPRESS_ROMB,
+ PCI_SUBSYS_ID_FSC,
+ PCI_SUBSYS_ID_FSC_MEGARAID_PCI_EXPRESS_ROMB,
+ },
+ {
+ PCI_VENDOR_ID_LSI_LOGIC,
+ PCI_DEVICE_ID_MEGARAID_ACER_ROMB_2E,
+ PCI_VENDOR_ID_AI,
+ PCI_SUBSYS_ID_MEGARAID_ACER_ROMB_2E,
+ },
+ {0} /* Terminating entry */
+};
+MODULE_DEVICE_TABLE(pci, pci_id_table_g);
+
+
+static struct pci_driver megaraid_pci_driver_g = {
+ .name = "megaraid",
+ .id_table = pci_id_table_g,
+ .probe = megaraid_probe_one,
+ .remove = __devexit_p(megaraid_detach_one),
+ .driver = {
+ .shutdown = megaraid_mbox_shutdown,
+ }
+};
+
+
+/*
+ * Scsi host template for megaraid unified driver
+ */
+static struct scsi_host_template megaraid_template_g = {
+ .module = THIS_MODULE,
+ .name = "LSI Logic MegaRAID driver",
+ .proc_name = "megaraid",
+ .queuecommand = megaraid_queue_command,
+ .eh_abort_handler = megaraid_abort_handler,
+ .eh_device_reset_handler = megaraid_reset_handler,
+ .eh_bus_reset_handler = megaraid_reset_handler,
+ .eh_host_reset_handler = megaraid_reset_handler,
+ .use_clustering = ENABLE_CLUSTERING,
+};
+
+
+/**
+ * megaraid_init - module load hook
+ *
+ * We register ourselves as hotplug enabled module and let PCI subsystem
+ * discover our adaters
+ **/
+static int __init
+megaraid_init(void)
+{
+ int rval;
+
+ // Announce the driver version
+ con_log(CL_ANN, (KERN_INFO "megaraid: %s %s\n", MEGARAID_VERSION,
+ MEGARAID_EXT_VERSION));
+
+ // check validity of module parameters
+ if (megaraid_cmd_per_lun > MBOX_MAX_SCSI_CMDS) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mailbox: max commands per lun reset to %d\n",
+ MBOX_MAX_SCSI_CMDS));
+
+ megaraid_cmd_per_lun = MBOX_MAX_SCSI_CMDS;
+ }
+
+
+ // register as a PCI hot-plug driver module
+ if ((rval = pci_module_init(&megaraid_pci_driver_g))) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: could not register hotplug support.\n"));
+ }
+
+ return rval;
+}
+
+
+/**
+ * megaraid_exit - driver unload entry point
+ *
+ * We simply unwrap the megaraid_init routine here
+ */
+static void __exit
+megaraid_exit(void)
+{
+ con_log(CL_DLEVEL1, (KERN_NOTICE "megaraid: unloading framework\n"));
+
+ // unregister as PCI hotplug driver
+ pci_unregister_driver(&megaraid_pci_driver_g);
+
+ return;
+}
+
+
+/**
+ * megaraid_probe_one - PCI hotplug entry point
+ * @param pdev : handle to this controller's PCI configuration space
+ * @param id : pci device id of the class of controllers
+ *
+ * This routine should be called whenever a new adapter is detected by the
+ * PCI hotplug susbsytem.
+ **/
+static int __devinit
+megaraid_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ adapter_t *adapter;
+
+
+ // detected a new controller
+ con_log(CL_ANN, (KERN_INFO
+ "megaraid: probe new device %#4.04x:%#4.04x:%#4.04x:%#4.04x: ",
+ pdev->vendor, pdev->device, pdev->subsystem_vendor,
+ pdev->subsystem_device));
+
+ con_log(CL_ANN, ("bus %d:slot %d:func %d\n", pdev->bus->number,
+ PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)));
+
+ if (pci_enable_device(pdev)) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: pci_enable_device failed\n"));
+
+ return -ENODEV;
+ }
+
+ // Enable bus-mastering on this controller
+ pci_set_master(pdev);
+
+ // Allocate the per driver initialization structure
+ adapter = kmalloc(sizeof(adapter_t), GFP_KERNEL);
+
+ if (adapter == NULL) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d.\n", __FUNCTION__, __LINE__));
+
+ goto out_probe_one;
+ }
+ memset(adapter, 0, sizeof(adapter_t));
+
+
+ // set up PCI related soft state and other pre-known parameters
+ adapter->unique_id = pdev->bus->number << 8 | pdev->devfn;
+ adapter->irq = pdev->irq;
+ adapter->pdev = pdev;
+
+ atomic_set(&adapter->being_detached, 0);
+
+ // Setup the default DMA mask. This would be changed later on
+ // depending on hardware capabilities
+ if (pci_set_dma_mask(adapter->pdev, 0xFFFFFFFF) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: pci_set_dma_mask failed:%d\n", __LINE__));
+
+ goto out_free_adapter;
+ }
+
+
+ // Initialize the synchronization lock for kernel and LLD
+ spin_lock_init(&adapter->lock);
+ adapter->host_lock = &adapter->lock;
+
+
+ // Initialize the command queues: the list of free SCBs and the list
+ // of pending SCBs.
+ INIT_LIST_HEAD(&adapter->kscb_pool);
+ spin_lock_init(SCSI_FREE_LIST_LOCK(adapter));
+
+ INIT_LIST_HEAD(&adapter->pend_list);
+ spin_lock_init(PENDING_LIST_LOCK(adapter));
+
+ INIT_LIST_HEAD(&adapter->completed_list);
+ spin_lock_init(COMPLETED_LIST_LOCK(adapter));
+
+
+ // Start the mailbox based controller
+ if (megaraid_init_mbox(adapter) != 0) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: maibox adapter did not initialize\n"));
+
+ goto out_free_adapter;
+ }
+
+ // Register with LSI Common Management Module
+ if (megaraid_cmm_register(adapter) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: could not register with management module\n"));
+
+ goto out_fini_mbox;
+ }
+
+ // setup adapter handle in PCI soft state
+ pci_set_drvdata(pdev, adapter);
+
+ // attach with scsi mid-layer
+ if (megaraid_io_attach(adapter) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING "megaraid: io attach failed\n"));
+
+ goto out_cmm_unreg;
+ }
+
+ return 0;
+
+out_cmm_unreg:
+ pci_set_drvdata(pdev, NULL);
+ megaraid_cmm_unregister(adapter);
+out_fini_mbox:
+ megaraid_fini_mbox(adapter);
+out_free_adapter:
+ kfree(adapter);
+out_probe_one:
+ pci_disable_device(pdev);
+
+ return -ENODEV;
+}
+
+
+/**
+ * megaraid_detach_one - release the framework resources and call LLD release
+ * routine
+ * @param pdev : handle for our PCI cofiguration space
+ *
+ * This routine is called during driver unload. We free all the allocated
+ * resources and call the corresponding LLD so that it can also release all
+ * its resources.
+ *
+ * This routine is also called from the PCI hotplug system
+ **/
+static void
+megaraid_detach_one(struct pci_dev *pdev)
+{
+ adapter_t *adapter;
+ struct Scsi_Host *host;
+
+
+ // Start a rollback on this adapter
+ adapter = pci_get_drvdata(pdev);
+
+ if (!adapter) {
+ con_log(CL_ANN, (KERN_CRIT
+ "megaraid: Invalid detach on %#4.04x:%#4.04x:%#4.04x:%#4.04x\n",
+ pdev->vendor, pdev->device, pdev->subsystem_vendor,
+ pdev->subsystem_device));
+
+ return;
+ }
+ else {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid: detaching device %#4.04x:%#4.04x:%#4.04x:%#4.04x\n",
+ pdev->vendor, pdev->device, pdev->subsystem_vendor,
+ pdev->subsystem_device));
+ }
+
+
+ host = adapter->host;
+
+ // do not allow any more requests from the management module for this
+ // adapter.
+ // FIXME: How do we account for the request which might still be
+ // pending with us?
+ atomic_set(&adapter->being_detached, 1);
+
+ // detach from the IO sub-system
+ megaraid_io_detach(adapter);
+
+ // reset the device state in the PCI structure. We check this
+ // condition when we enter here. If the device state is NULL,
+ // that would mean the device has already been removed
+ pci_set_drvdata(pdev, NULL);
+
+ // Unregister from common management module
+ //
+ // FIXME: this must return success or failure for conditions if there
+ // is a command pending with LLD or not.
+ megaraid_cmm_unregister(adapter);
+
+ // finalize the mailbox based controller and release all resources
+ megaraid_fini_mbox(adapter);
+
+ kfree(adapter);
+
+ scsi_host_put(host);
+
+ pci_disable_device(pdev);
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_shutdown - PCI shutdown for megaraid HBA
+ * @param device : generice driver model device
+ *
+ * Shutdown notification, perform flush cache
+ */
+static void
+megaraid_mbox_shutdown(struct device *device)
+{
+ adapter_t *adapter = pci_get_drvdata(to_pci_dev(device));
+ static int counter;
+
+ if (!adapter) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: null device in shutdown\n"));
+ return;
+ }
+
+ // flush caches now
+ con_log(CL_ANN, (KERN_INFO "megaraid: flushing adapter %d...",
+ counter++));
+
+ megaraid_mbox_flush_cache(adapter);
+
+ con_log(CL_ANN, ("done\n"));
+}
+
+
+/**
+ * megaraid_io_attach - attach a device with the IO subsystem
+ * @param adapter : controller's soft state
+ *
+ * Attach this device with the IO subsystem
+ **/
+static int
+megaraid_io_attach(adapter_t *adapter)
+{
+ struct Scsi_Host *host;
+
+ // Initialize SCSI Host structure
+ host = scsi_host_alloc(&megaraid_template_g, 8);
+ if (!host) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mbox: scsi_register failed\n"));
+
+ return -1;
+ }
+
+ SCSIHOST2ADAP(host) = (caddr_t)adapter;
+ adapter->host = host;
+
+ // export the parameters required by the mid-layer
+ scsi_assign_lock(host, adapter->host_lock);
+ scsi_set_device(host, &adapter->pdev->dev);
+
+ host->irq = adapter->irq;
+ host->unique_id = adapter->unique_id;
+ host->can_queue = adapter->max_cmds;
+ host->this_id = adapter->init_id;
+ host->sg_tablesize = adapter->sglen;
+ host->max_sectors = adapter->max_sectors;
+ host->cmd_per_lun = adapter->cmd_per_lun;
+ host->max_channel = adapter->max_channel;
+ host->max_id = adapter->max_target;
+ host->max_lun = adapter->max_lun;
+
+
+ // notify mid-layer about the new controller
+ if (scsi_add_host(host, &adapter->pdev->dev)) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mbox: scsi_add_host failed\n"));
+
+ scsi_host_put(host);
+
+ return -1;
+ }
+
+ scsi_scan_host(host);
+
+ return 0;
+}
+
+
+/**
+ * megaraid_io_detach - detach a device from the IO subsystem
+ * @param adapter : controller's soft state
+ *
+ * Detach this device from the IO subsystem
+ **/
+static void
+megaraid_io_detach(adapter_t *adapter)
+{
+ struct Scsi_Host *host;
+
+ con_log(CL_DLEVEL1, (KERN_INFO "megaraid: io detach\n"));
+
+ host = adapter->host;
+
+ scsi_remove_host(host);
+
+ return;
+}
+
+
+/*
+ * START: Mailbox Low Level Driver
+ *
+ * This is section specific to the single mailbox based controllers
+ */
+
+/**
+ * megaraid_init_mbox - initialize controller
+ * @param adapter - our soft state
+ *
+ * . Allocate 16-byte aligned mailbox memory for firmware handshake
+ * . Allocate controller's memory resources
+ * . Find out all initialization data
+ * . Allocate memory required for all the commands
+ * . Use internal library of FW routines, build up complete soft state
+ */
+static int __init
+megaraid_init_mbox(adapter_t *adapter)
+{
+ struct pci_dev *pdev;
+ mraid_device_t *raid_dev;
+ int i;
+
+
+ adapter->ito = MBOX_TIMEOUT;
+ pdev = adapter->pdev;
+
+ /*
+ * Allocate and initialize the init data structure for mailbox
+ * controllers
+ */
+ raid_dev = kmalloc(sizeof(mraid_device_t), GFP_KERNEL);
+ if (raid_dev == NULL) return -1;
+
+ memset(raid_dev, 0, sizeof(mraid_device_t));
+
+ /*
+ * Attach the adapter soft state to raid device soft state
+ */
+ adapter->raid_device = (caddr_t)raid_dev;
+ raid_dev->fast_load = megaraid_fast_load;
+
+
+ // our baseport
+ raid_dev->baseport = pci_resource_start(pdev, 0);
+
+ if (pci_request_regions(pdev, "MegaRAID: LSI Logic Corporation") != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: mem region busy\n"));
+
+ goto out_free_raid_dev;
+ }
+
+ raid_dev->baseaddr = (unsigned long)
+ ioremap_nocache(raid_dev->baseport, 128);
+
+ if (!raid_dev->baseaddr) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: could not map hba memory\n") );
+
+ goto out_release_regions;
+ }
+
+ //
+ // Setup the rest of the soft state using the library of FW routines
+ //
+
+ // request IRQ and register the interrupt service routine
+ if (request_irq(adapter->irq, megaraid_isr, SA_SHIRQ, "megaraid",
+ adapter)) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: Couldn't register IRQ %d!\n", adapter->irq));
+
+ goto out_iounmap;
+ }
+
+
+ // initialize the mutual exclusion lock for the mailbox
+ spin_lock_init(&raid_dev->mailbox_lock);
+
+ // allocate memory required for commands
+ if (megaraid_alloc_cmd_packets(adapter) != 0) {
+ goto out_free_irq;
+ }
+
+ // Product info
+ if (megaraid_mbox_product_info(adapter) != 0) {
+ goto out_alloc_cmds;
+ }
+
+ // Do we support extended CDBs
+ adapter->max_cdb_sz = 10;
+ if (megaraid_mbox_extended_cdb(adapter) == 0) {
+ adapter->max_cdb_sz = 16;
+ }
+
+ /*
+ * Do we support cluster environment, if we do, what is the initiator
+ * id.
+ * NOTE: In a non-cluster aware firmware environment, the LLD should
+ * return 7 as initiator id.
+ */
+ adapter->ha = 0;
+ adapter->init_id = -1;
+ if (megaraid_mbox_support_ha(adapter, &adapter->init_id) == 0) {
+ adapter->ha = 1;
+ }
+
+ /*
+ * Prepare the device ids array to have the mapping between the kernel
+ * device address and megaraid device address.
+ * We export the physical devices on their actual addresses. The
+ * logical drives are exported on a virtual SCSI channel
+ */
+ megaraid_mbox_setup_device_map(adapter);
+
+ // If the firmware supports random deletion, update the device id map
+ if (megaraid_mbox_support_random_del(adapter)) {
+
+ // Change the logical drives numbers in device_ids array one
+ // slot in device_ids is reserved for target id, that's why
+ // "<=" below
+ for (i = 0; i <= MAX_LOGICAL_DRIVES_40LD; i++) {
+ adapter->device_ids[adapter->max_channel][i] += 0x80;
+ }
+ adapter->device_ids[adapter->max_channel][adapter->init_id] =
+ 0xFF;
+ }
+
+ /*
+ * find out the maximum number of scatter-gather elements supported by
+ * this firmware
+ */
+ adapter->sglen = megaraid_mbox_get_max_sg(adapter);
+
+ // enumerate RAID and SCSI channels so that all devices on SCSI
+ // channels can later be exported, including disk devices
+ megaraid_mbox_enum_raid_scsi(adapter);
+
+ /*
+ * Other parameters required by upper layer
+ *
+ * maximum number of sectors per IO command
+ */
+ adapter->max_sectors = megaraid_max_sectors;
+
+ /*
+ * number of queued commands per LUN.
+ */
+ adapter->cmd_per_lun = megaraid_cmd_per_lun;
+
+ // Set the DMA mask to 64-bit. All supported controllers as capable of
+ // DMA in this range
+ if (pci_set_dma_mask(adapter->pdev, 0xFFFFFFFFFFFFFFFFULL) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: could not set DMA mask for 64-bit.\n"));
+
+ goto out_alloc_cmds;
+ }
+
+ // setup tasklet for DPC
+ tasklet_init(&adapter->dpc_h, megaraid_mbox_dpc,
+ (unsigned long)adapter);
+
+ con_log(CL_DLEVEL1, (KERN_INFO
+ "megaraid mbox hba successfully initialized\n"));
+
+ return 0;
+
+out_alloc_cmds:
+ megaraid_free_cmd_packets(adapter);
+out_free_irq:
+ free_irq(adapter->irq, adapter);
+out_iounmap:
+ iounmap((caddr_t)raid_dev->baseaddr);
+out_release_regions:
+ pci_release_regions(pdev);
+out_free_raid_dev:
+ kfree(raid_dev);
+
+ return -1;
+}
+
+
+/**
+ * megaraid_fini_mbox - undo controller initialization
+ * @param adapter : our soft state
+ */
+static void
+megaraid_fini_mbox(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+
+ // flush all caches
+ megaraid_mbox_flush_cache(adapter);
+
+ tasklet_kill(&adapter->dpc_h);
+
+ megaraid_free_cmd_packets(adapter);
+
+ free_irq(adapter->irq, adapter);
+
+ iounmap((caddr_t)raid_dev->baseaddr);
+
+ pci_release_regions(adapter->pdev);
+
+ kfree(raid_dev);
+
+ return;
+}
+
+
+/**
+ * megaraid_alloc_cmd_packets - allocate shared mailbox
+ * @param adapter : soft state of the raid controller
+ *
+ * Allocate and align the shared mailbox. This maibox is used to issue
+ * all the commands. For IO based controllers, the mailbox is also regsitered
+ * with the FW. Allocate memory for all commands as well.
+ * This is our big allocator
+ */
+static int
+megaraid_alloc_cmd_packets(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ struct pci_dev *pdev;
+ unsigned long align;
+ scb_t *scb;
+ mbox_ccb_t *ccb;
+ struct mraid_pci_blk *epthru_pci_blk;
+ struct mraid_pci_blk *sg_pci_blk;
+ struct mraid_pci_blk *mbox_pci_blk;
+ int i;
+
+ pdev = adapter->pdev;
+
+ /*
+ * Setup the mailbox
+ * Allocate the common 16-byte aligned memory for the handshake
+ * mailbox.
+ */
+ raid_dev->una_mbox64 = pci_alloc_consistent(adapter->pdev,
+ sizeof(mbox64_t), &raid_dev->una_mbox64_dma);
+
+ if (!raid_dev->una_mbox64) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+ return -1;
+ }
+ memset(raid_dev->una_mbox64, 0, sizeof(mbox64_t));
+
+ /*
+ * Align the mailbox at 16-byte boundary
+ */
+ raid_dev->mbox = &raid_dev->una_mbox64->mbox32;
+
+ raid_dev->mbox = (mbox_t *)((((unsigned long)raid_dev->mbox) + 15) &
+ (~0UL ^ 0xFUL));
+
+ raid_dev->mbox64 = (mbox64_t *)(((unsigned long)raid_dev->mbox) - 8);
+
+ align = ((void *)raid_dev->mbox -
+ ((void *)&raid_dev->una_mbox64->mbox32));
+
+ raid_dev->mbox_dma = (unsigned long)raid_dev->una_mbox64_dma + 8 +
+ align;
+
+ // Allocate memory for commands issued internally
+ adapter->ibuf = pci_alloc_consistent(pdev, MBOX_IBUF_SIZE,
+ &adapter->ibuf_dma_h);
+ if (!adapter->ibuf) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+
+ goto out_free_common_mbox;
+ }
+ memset(adapter->ibuf, 0, MBOX_IBUF_SIZE);
+
+ // Allocate memory for our SCSI Command Blocks and their associated
+ // memory
+
+ /*
+ * Allocate memory for the base list of scb. Later allocate memory for
+ * CCBs and embedded components of each CCB and point the pointers in
+ * scb to the allocated components
+ * NOTE: The code to allocate SCB will be duplicated in all the LLD
+ * since the calling routine does not yet know the number of available
+ * commands.
+ */
+ adapter->kscb_list = kmalloc(sizeof(scb_t) * MBOX_MAX_SCSI_CMDS,
+ GFP_KERNEL);
+
+ if (adapter->kscb_list == NULL) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+ goto out_free_ibuf;
+ }
+ memset(adapter->kscb_list, 0, sizeof(scb_t) * MBOX_MAX_SCSI_CMDS);
+
+ // memory allocation for our command packets
+ if (megaraid_mbox_setup_dma_pools(adapter) != 0) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+ goto out_free_scb_list;
+ }
+
+ // Adjust the scb pointers and link in the free pool
+ epthru_pci_blk = raid_dev->epthru_pool;
+ sg_pci_blk = raid_dev->sg_pool;
+ mbox_pci_blk = raid_dev->mbox_pool;
+
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS; i++) {
+ scb = adapter->kscb_list + i;
+ ccb = raid_dev->ccb_list + i;
+
+ ccb->mbox = (mbox_t *)(mbox_pci_blk[i].vaddr + 16);
+ ccb->raw_mbox = (uint8_t *)ccb->mbox;
+ ccb->mbox64 = (mbox64_t *)(mbox_pci_blk[i].vaddr + 8);
+ ccb->mbox_dma_h = (unsigned long)mbox_pci_blk[i].dma_addr + 16;
+
+ // make sure the mailbox is aligned properly
+ if (ccb->mbox_dma_h & 0x0F) {
+ con_log(CL_ANN, (KERN_CRIT
+ "megaraid mbox: not aligned on 16-bytes\n"));
+
+ goto out_teardown_dma_pools;
+ }
+
+ ccb->epthru = (mraid_epassthru_t *)
+ epthru_pci_blk[i].vaddr;
+ ccb->epthru_dma_h = epthru_pci_blk[i].dma_addr;
+ ccb->pthru = (mraid_passthru_t *)ccb->epthru;
+ ccb->pthru_dma_h = ccb->epthru_dma_h;
+
+
+ ccb->sgl64 = (mbox_sgl64 *)sg_pci_blk[i].vaddr;
+ ccb->sgl_dma_h = sg_pci_blk[i].dma_addr;
+ ccb->sgl32 = (mbox_sgl32 *)ccb->sgl64;
+
+ scb->ccb = (caddr_t)ccb;
+ scb->gp = 0;
+
+ scb->sno = i; // command index
+
+ scb->scp = NULL;
+ scb->state = SCB_FREE;
+ scb->dma_direction = PCI_DMA_NONE;
+ scb->dma_type = MRAID_DMA_NONE;
+ scb->dev_channel = -1;
+ scb->dev_target = -1;
+
+ // put scb in the free pool
+ list_add_tail(&scb->list, &adapter->kscb_pool);
+ }
+
+ return 0;
+
+out_teardown_dma_pools:
+ megaraid_mbox_teardown_dma_pools(adapter);
+out_free_scb_list:
+ kfree(adapter->kscb_list);
+out_free_ibuf:
+ pci_free_consistent(pdev, MBOX_IBUF_SIZE, (void *)adapter->ibuf,
+ adapter->ibuf_dma_h);
+out_free_common_mbox:
+ pci_free_consistent(adapter->pdev, sizeof(mbox64_t),
+ (caddr_t)raid_dev->una_mbox64, raid_dev->una_mbox64_dma);
+
+ return -1;
+}
+
+
+/**
+ * megaraid_free_cmd_packets - free memory
+ * @param adapter : soft state of the raid controller
+ *
+ * Release memory resources allocated for commands
+ */
+static void
+megaraid_free_cmd_packets(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+
+ megaraid_mbox_teardown_dma_pools(adapter);
+
+ kfree(adapter->kscb_list);
+
+ pci_free_consistent(adapter->pdev, MBOX_IBUF_SIZE,
+ (void *)adapter->ibuf, adapter->ibuf_dma_h);
+
+ pci_free_consistent(adapter->pdev, sizeof(mbox64_t),
+ (caddr_t)raid_dev->una_mbox64, raid_dev->una_mbox64_dma);
+ return;
+}
+
+
+/**
+ * megaraid_mbox_setup_dma_pools - setup dma pool for command packets
+ * @param adapter : HBA soft state
+ *
+ * setup the dma pools for mailbox, passthru and extended passthru structures,
+ * and scatter-gather lists
+ */
+static int
+megaraid_mbox_setup_dma_pools(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ struct mraid_pci_blk *epthru_pci_blk;
+ struct mraid_pci_blk *sg_pci_blk;
+ struct mraid_pci_blk *mbox_pci_blk;
+ int i;
+
+
+
+ // Allocate memory for 16-bytes aligned mailboxes
+ raid_dev->mbox_pool_handle = pci_pool_create("megaraid mbox pool",
+ adapter->pdev,
+ sizeof(mbox64_t) + 16,
+ 16, 0);
+
+ if (raid_dev->mbox_pool_handle == NULL) {
+ goto fail_setup_dma_pool;
+ }
+
+ mbox_pci_blk = raid_dev->mbox_pool;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS; i++) {
+ mbox_pci_blk[i].vaddr = pci_pool_alloc(
+ raid_dev->mbox_pool_handle,
+ GFP_KERNEL,
+ &mbox_pci_blk[i].dma_addr);
+ if (!mbox_pci_blk[i].vaddr) {
+ goto fail_setup_dma_pool;
+ }
+ }
+
+ /*
+ * Allocate memory for each embedded passthru strucuture pointer
+ * Request for a 128 bytes aligned structure for each passthru command
+ * structure
+ * Since passthru and extended passthru commands are exclusive, they
+ * share common memory pool. Passthru structures piggyback on memory
+ * allocted to extended passthru since passthru is smaller of the two
+ */
+ raid_dev->epthru_pool_handle = pci_pool_create("megaraid mbox pthru",
+ adapter->pdev, sizeof(mraid_epassthru_t), 128, 0);
+
+ if (raid_dev->epthru_pool_handle == NULL) {
+ goto fail_setup_dma_pool;
+ }
+
+ epthru_pci_blk = raid_dev->epthru_pool;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS; i++) {
+ epthru_pci_blk[i].vaddr = pci_pool_alloc(
+ raid_dev->epthru_pool_handle,
+ GFP_KERNEL,
+ &epthru_pci_blk[i].dma_addr);
+ if (!epthru_pci_blk[i].vaddr) {
+ goto fail_setup_dma_pool;
+ }
+ }
+
+
+ // Allocate memory for each scatter-gather list. Request for 512 bytes
+ // alignment for each sg list
+ raid_dev->sg_pool_handle = pci_pool_create("megaraid mbox sg",
+ adapter->pdev,
+ sizeof(mbox_sgl64) * MBOX_MAX_SG_SIZE,
+ 512, 0);
+
+ if (raid_dev->sg_pool_handle == NULL) {
+ goto fail_setup_dma_pool;
+ }
+
+ sg_pci_blk = raid_dev->sg_pool;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS; i++) {
+ sg_pci_blk[i].vaddr = pci_pool_alloc(
+ raid_dev->sg_pool_handle,
+ GFP_KERNEL,
+ &sg_pci_blk[i].dma_addr);
+ if (!sg_pci_blk[i].vaddr) {
+ goto fail_setup_dma_pool;
+ }
+ }
+
+ return 0;
+
+fail_setup_dma_pool:
+ megaraid_mbox_teardown_dma_pools(adapter);
+ return -1;
+}
+
+
+/**
+ * megaraid_mbox_teardown_dma_pools - teardown dma pools for command packets
+ * @param adapter : HBA soft state
+ *
+ * teardown the dma pool for mailbox, passthru and extended passthru
+ * structures, and scatter-gather lists
+ */
+static void
+megaraid_mbox_teardown_dma_pools(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ struct mraid_pci_blk *epthru_pci_blk;
+ struct mraid_pci_blk *sg_pci_blk;
+ struct mraid_pci_blk *mbox_pci_blk;
+ int i;
+
+
+ sg_pci_blk = raid_dev->sg_pool;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS && sg_pci_blk[i].vaddr; i++) {
+ pci_pool_free(raid_dev->sg_pool_handle, sg_pci_blk[i].vaddr,
+ sg_pci_blk[i].dma_addr);
+ }
+ if (raid_dev->sg_pool_handle)
+ pci_pool_destroy(raid_dev->sg_pool_handle);
+
+
+ epthru_pci_blk = raid_dev->epthru_pool;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS && epthru_pci_blk[i].vaddr; i++) {
+ pci_pool_free(raid_dev->epthru_pool_handle,
+ epthru_pci_blk[i].vaddr, epthru_pci_blk[i].dma_addr);
+ }
+ if (raid_dev->epthru_pool_handle)
+ pci_pool_destroy(raid_dev->epthru_pool_handle);
+
+
+ mbox_pci_blk = raid_dev->mbox_pool;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS && mbox_pci_blk[i].vaddr; i++) {
+ pci_pool_free(raid_dev->mbox_pool_handle,
+ mbox_pci_blk[i].vaddr, mbox_pci_blk[i].dma_addr);
+ }
+ if (raid_dev->mbox_pool_handle)
+ pci_pool_destroy(raid_dev->mbox_pool_handle);
+
+ return;
+}
+
+
+/**
+ * megaraid_alloc_scb - detach and return a scb from the free list
+ * @adapter : controller's soft state
+ *
+ * return the scb from the head of the free list. NULL if there are none
+ * available
+ **/
+static inline scb_t *
+megaraid_alloc_scb(adapter_t *adapter, struct scsi_cmnd *scp)
+{
+ struct list_head *head = &adapter->kscb_pool;
+ scb_t *scb = NULL;
+ unsigned long flags;
+
+ // detach scb from free pool
+ spin_lock_irqsave(SCSI_FREE_LIST_LOCK(adapter), flags);
+
+ if (list_empty(head)) {
+ spin_unlock_irqrestore(SCSI_FREE_LIST_LOCK(adapter), flags);
+ return NULL;
+ }
+
+ scb = list_entry(head->next, scb_t, list);
+ list_del_init(&scb->list);
+
+ spin_unlock_irqrestore(SCSI_FREE_LIST_LOCK(adapter), flags);
+
+ scb->state = SCB_ACTIVE;
+ scb->scp = scp;
+ scb->dma_type = MRAID_DMA_NONE;
+
+ return scb;
+}
+
+
+/**
+ * megaraid_dealloc_scb - return the scb to the free pool
+ * @adapter : controller's soft state
+ * @scb : scb to be freed
+ *
+ * return the scb back to the free list of scbs. The caller must 'flush' the
+ * SCB before calling us. E.g., performing pci_unamp and/or pci_sync etc.
+ * NOTE NOTE: Make sure the scb is not on any list before calling this
+ * routine.
+ **/
+static inline void
+megaraid_dealloc_scb(adapter_t *adapter, scb_t *scb)
+{
+ unsigned long flags;
+
+ // put scb in the free pool
+ scb->state = SCB_FREE;
+ scb->scp = NULL;
+ spin_lock_irqsave(SCSI_FREE_LIST_LOCK(adapter), flags);
+
+ list_add(&scb->list, &adapter->kscb_pool);
+
+ spin_unlock_irqrestore(SCSI_FREE_LIST_LOCK(adapter), flags);
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_mksgl - make the scatter-gather list
+ * @adapter - controller's soft state
+ * @scb - scsi control block
+ *
+ * prepare the scatter-gather list
+ */
+static inline int
+megaraid_mbox_mksgl(adapter_t *adapter, scb_t *scb)
+{
+ struct scatterlist *sgl;
+ mbox_ccb_t *ccb;
+ struct page *page;
+ unsigned long offset;
+ struct scsi_cmnd *scp;
+ int sgcnt;
+ int i;
+
+
+ scp = scb->scp;
+ ccb = (mbox_ccb_t *)scb->ccb;
+
+ // no mapping required if no data to be transferred
+ if (!scp->request_buffer || !scp->request_bufflen)
+ return 0;
+
+ if (!scp->use_sg) { /* scatter-gather list not used */
+
+ page = virt_to_page(scp->request_buffer);
+
+ offset = ((unsigned long)scp->request_buffer & ~PAGE_MASK);
+
+ ccb->buf_dma_h = pci_map_page(adapter->pdev, page, offset,
+ scp->request_bufflen,
+ scb->dma_direction);
+ scb->dma_type = MRAID_DMA_WBUF;
+
+ /*
+ * We need to handle special 64-bit commands that need a
+ * minimum of 1 SG
+ */
+ sgcnt = 1;
+ ccb->sgl64[0].address = ccb->buf_dma_h;
+ ccb->sgl64[0].length = scp->request_bufflen;
+
+ return sgcnt;
+ }
+
+ sgl = (struct scatterlist *)scp->request_buffer;
+
+ // The number of sg elements returned must not exceed our limit
+ sgcnt = pci_map_sg(adapter->pdev, sgl, scp->use_sg,
+ scb->dma_direction);
+
+ if (sgcnt > adapter->sglen) {
+ con_log(CL_ANN, (KERN_CRIT
+ "megaraid critical: too many sg elements:%d\n",
+ sgcnt));
+ BUG();
+ }
+
+ scb->dma_type = MRAID_DMA_WSG;
+
+ for (i = 0; i < sgcnt; i++, sgl++) {
+ ccb->sgl64[i].address = sg_dma_address(sgl);
+ ccb->sgl64[i].length = sg_dma_len(sgl);
+ }
+
+ // Return count of SG nodes
+ return sgcnt;
+}
+
+
+/**
+ * mbox_post_cmd - issue a mailbox command
+ * @adapter - controller's soft state
+ * @scb - command to be issued
+ *
+ * post the command to the controller if mailbox is availble.
+ */
+static inline int
+mbox_post_cmd(adapter_t *adapter, scb_t *scb)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mbox64_t *mbox64;
+ mbox_t *mbox;
+ mbox_ccb_t *ccb;
+ unsigned long flags;
+ unsigned int i = 0;
+
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ mbox = raid_dev->mbox;
+ mbox64 = raid_dev->mbox64;
+
+ /*
+ * Check for busy mailbox. If it is, return failure - the caller
+ * should retry later.
+ */
+ spin_lock_irqsave(MAILBOX_LOCK(raid_dev), flags);
+
+ if (unlikely(mbox->busy)) {
+ do {
+ udelay(1);
+ i++;
+ rmb();
+ } while(mbox->busy && (i < max_mbox_busy_wait));
+
+ if (mbox->busy) {
+
+ spin_unlock_irqrestore(MAILBOX_LOCK(raid_dev), flags);
+
+ return -1;
+ }
+ }
+
+
+ // Copy this command's mailbox data into "adapter's" mailbox
+ memcpy((caddr_t)mbox64, (caddr_t)ccb->mbox64, 22);
+ mbox->cmdid = scb->sno;
+
+ adapter->outstanding_cmds++;
+
+ if (scb->dma_direction == PCI_DMA_TODEVICE) {
+ if (!scb->scp->use_sg) { // sg list not used
+ pci_dma_sync_single(adapter->pdev, ccb->buf_dma_h,
+ scb->scp->request_bufflen,
+ PCI_DMA_TODEVICE);
+ }
+ else {
+ pci_dma_sync_sg(adapter->pdev, scb->scp->request_buffer,
+ scb->scp->use_sg, PCI_DMA_TODEVICE);
+ }
+ }
+
+ mbox->busy = 1; // Set busy
+ mbox->poll = 0;
+ mbox->ack = 0;
+ wmb();
+
+ WRINDOOR(raid_dev, raid_dev->mbox_dma | 0x1);
+
+ spin_unlock_irqrestore(MAILBOX_LOCK(raid_dev), flags);
+
+ return 0;
+}
+
+
+/**
+ * megaraid_queue_command - generic queue entry point for all LLDs
+ * @scp : pointer to the scsi command to be executed
+ * @done : callback routine to be called after the cmd has be completed
+ *
+ * Queue entry point for mailbox based controllers.
+ */
+static int
+megaraid_queue_command(struct scsi_cmnd *scp, void (* done)(struct scsi_cmnd *))
+{
+ adapter_t *adapter;
+ scb_t *scb;
+ int if_busy;
+
+ adapter = SCP2ADAPTER(scp);
+ scp->scsi_done = done;
+ scp->result = 0;
+
+ ASSERT(spin_is_locked(adapter->host_lock));
+
+ spin_unlock(adapter->host_lock);
+
+ /*
+ * Allocate and build a SCB request
+ * if_busy flag will be set if megaraid_mbox_build_cmd() command could
+ * not allocate scb. We will return non-zero status in that case.
+ * NOTE: scb can be null even though certain commands completed
+ * successfully, e.g., MODE_SENSE and TEST_UNIT_READY, it would
+ * return 0 in that case, and we would do the callback right away.
+ */
+ if_busy = 0;
+ scb = megaraid_mbox_build_cmd(adapter, scp, &if_busy);
+
+ if (scb) {
+ megaraid_mbox_runpendq(adapter, scb);
+ }
+
+ spin_lock(adapter->host_lock);
+
+ if (!scb) { // command already completed
+ done(scp);
+ }
+
+ return if_busy;
+}
+
+
+/**
+ * megaraid_mbox_build_cmd - transform the mid-layer scsi command to megaraid
+ * firmware lingua
+ * @adapter - controller's soft state
+ * @scp - mid-layer scsi command pointer
+ * @busy - set if request could not be completed because of lack of
+ * resources
+ *
+ * convert the command issued by mid-layer to format understood by megaraid
+ * firmware. We also complete certain command without sending them to firmware
+ */
+static scb_t *
+megaraid_mbox_build_cmd(adapter_t *adapter, struct scsi_cmnd *scp, int *busy)
+{
+ mraid_device_t *rdev = ADAP2RAIDDEV(adapter);
+ int channel;
+ int target;
+ int islogical;
+ mbox_ccb_t *ccb;
+ mraid_passthru_t *pthru;
+ mbox64_t *mbox64;
+ mbox_t *mbox;
+ scb_t *scb;
+ char skip[] = "skipping";
+ char scan[] = "scanning";
+ char *ss;
+
+
+ /*
+ * Get the appropriate device map for the device this command is
+ * intended for
+ */
+ MRAID_GET_DEVICE_MAP(adapter, scp, channel, target, islogical);
+
+ /*
+ * Logical drive commands
+ */
+ if (islogical) {
+ switch (scp->cmnd[0]) {
+ case TEST_UNIT_READY:
+ /*
+ * Do we support clustering and is the support enabled
+ * If no, return success always
+ */
+ if (!adapter->ha) {
+ scp->result = (DID_OK << 16);
+ return NULL;
+ }
+
+ if (!(scb = megaraid_alloc_scb(adapter, scp))) {
+ scp->result = (DID_ERROR << 16);
+ *busy = 1;
+ return NULL;
+ }
+
+ scb->dma_direction = scp->sc_data_direction;
+ scb->dev_channel = 0xFF;
+ scb->dev_target = target;
+ ccb = (mbox_ccb_t *)scb->ccb;
+
+ /*
+ * The command id will be provided by the command
+ * issuance routine
+ */
+ ccb->raw_mbox[0] = CLUSTER_CMD;
+ ccb->raw_mbox[2] = RESERVATION_STATUS;
+ ccb->raw_mbox[3] = target;
+
+ return scb;
+
+ case MODE_SENSE:
+ if (scp->use_sg) {
+ struct scatterlist *sgl;
+ caddr_t vaddr;
+
+ sgl = (struct scatterlist *)scp->request_buffer;
+ if (sgl->page) {
+ vaddr = (caddr_t)
+ (page_address((&sgl[0])->page)
+ + (&sgl[0])->offset);
+
+ memset(vaddr, 0, scp->cmnd[4]);
+ }
+ else {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mailbox: invalid sg:%d\n",
+ __LINE__));
+ }
+ }
+ else {
+ memset(scp->request_buffer, 0, scp->cmnd[4]);
+ }
+ scp->result = (DID_OK << 16);
+ return NULL;
+
+ case INQUIRY:
+ /*
+ * Display the channel scan for logical drives
+ * Do not display scan for a channel if already done.
+ */
+ if (!(rdev->last_disp & (1L << SCP2CHANNEL(scp)))) {
+
+ con_log(CL_ANN, (KERN_INFO
+ "scsi[%d]: scanning scsi channel %d",
+ adapter->host->host_no,
+ SCP2CHANNEL(scp)));
+
+ con_log(CL_ANN, (
+ " [virtual] for logical drives\n"));
+
+ rdev->last_disp |= (1L << SCP2CHANNEL(scp));
+ }
+
+ /* Fall through */
+
+ case READ_CAPACITY:
+ /*
+ * Do not allow LUN > 0 for logical drives and
+ * requests for more than 40 logical drives
+ */
+ if (SCP2LUN(scp)) {
+ scp->result = (DID_BAD_TARGET << 16);
+ return NULL;
+ }
+ if ((target % 0x80) >= MAX_LOGICAL_DRIVES_40LD) {
+ scp->result = (DID_BAD_TARGET << 16);
+ return NULL;
+ }
+
+
+ /* Allocate a SCB and initialize passthru */
+ if (!(scb = megaraid_alloc_scb(adapter, scp))) {
+ scp->result = (DID_ERROR << 16);
+ *busy = 1;
+ return NULL;
+ }
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ scb->dev_channel = 0xFF;
+ scb->dev_target = target;
+ pthru = ccb->pthru;
+ mbox = ccb->mbox;
+ mbox64 = ccb->mbox64;
+
+ pthru->timeout = 0;
+ pthru->ars = 1;
+ pthru->reqsenselen = 14;
+ pthru->islogical = 1;
+ pthru->logdrv = target;
+ pthru->cdblen = scp->cmd_len;
+ memcpy(pthru->cdb, scp->cmnd, scp->cmd_len);
+
+ mbox->cmd = MBOXCMD_PASSTHRU64;
+ scb->dma_direction = scp->sc_data_direction;
+
+ pthru->dataxferlen = scp->request_bufflen;
+ pthru->dataxferaddr = ccb->sgl_dma_h;
+ pthru->numsge = megaraid_mbox_mksgl(adapter,
+ scb);
+
+ mbox->xferaddr = 0xFFFFFFFF;
+ mbox64->xferaddr_lo = (uint32_t )ccb->pthru_dma_h;
+ mbox64->xferaddr_hi = 0;
+
+ return scb;
+
+ case READ_6:
+ case WRITE_6:
+ case READ_10:
+ case WRITE_10:
+ case READ_12:
+ case WRITE_12:
+
+ /*
+ * Allocate a SCB and initialize mailbox
+ */
+ if (!(scb = megaraid_alloc_scb(adapter, scp))) {
+ scp->result = (DID_ERROR << 16);
+ *busy = 1;
+ return NULL;
+ }
+ ccb = (mbox_ccb_t *)scb->ccb;
+ scb->dev_channel = 0xFF;
+ scb->dev_target = target;
+ mbox = ccb->mbox;
+ mbox64 = ccb->mbox64;
+ mbox->logdrv = target;
+
+ /*
+ * A little HACK: 2nd bit is zero for all scsi read
+ * commands and is set for all scsi write commands
+ */
+ mbox->cmd = (scp->cmnd[0] & 0x02) ? MBOXCMD_LWRITE64:
+ MBOXCMD_LREAD64 ;
+
+ /*
+ * 6-byte READ(0x08) or WRITE(0x0A) cdb
+ */
+ if (scp->cmd_len == 6) {
+ mbox->numsectors = (uint32_t)scp->cmnd[4];
+ mbox->lba =
+ ((uint32_t)scp->cmnd[1] << 16) |
+ ((uint32_t)scp->cmnd[2] << 8) |
+ (uint32_t)scp->cmnd[3];
+
+ mbox->lba &= 0x1FFFFF;
+ }
+
+ /*
+ * 10-byte READ(0x28) or WRITE(0x2A) cdb
+ */
+ else if (scp->cmd_len == 10) {
+ mbox->numsectors =
+ (uint32_t)scp->cmnd[8] |
+ ((uint32_t)scp->cmnd[7] << 8);
+ mbox->lba =
+ ((uint32_t)scp->cmnd[2] << 24) |
+ ((uint32_t)scp->cmnd[3] << 16) |
+ ((uint32_t)scp->cmnd[4] << 8) |
+ (uint32_t)scp->cmnd[5];
+ }
+
+ /*
+ * 12-byte READ(0xA8) or WRITE(0xAA) cdb
+ */
+ else if (scp->cmd_len == 12) {
+ mbox->lba =
+ ((uint32_t)scp->cmnd[2] << 24) |
+ ((uint32_t)scp->cmnd[3] << 16) |
+ ((uint32_t)scp->cmnd[4] << 8) |
+ (uint32_t)scp->cmnd[5];
+
+ mbox->numsectors =
+ ((uint32_t)scp->cmnd[6] << 24) |
+ ((uint32_t)scp->cmnd[7] << 16) |
+ ((uint32_t)scp->cmnd[8] << 8) |
+ (uint32_t)scp->cmnd[9];
+ }
+ else {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: unsupported CDB length\n"));
+
+ megaraid_dealloc_scb(adapter, scb);
+
+ scp->result = (DID_ERROR << 16);
+ return NULL;
+ }
+
+ scb->dma_direction = scp->sc_data_direction;
+
+ // Calculate Scatter-Gather info
+ mbox64->xferaddr_lo = (uint32_t )ccb->sgl_dma_h;
+ mbox->numsge = megaraid_mbox_mksgl(adapter,
+ scb);
+ mbox->xferaddr = 0xFFFFFFFF;
+ mbox64->xferaddr_hi = 0;
+
+ return scb;
+
+ case RESERVE:
+ case RELEASE:
+ /*
+ * Do we support clustering and is the support enabled
+ */
+ if (!adapter->ha) {
+ scp->result = (DID_BAD_TARGET << 16);
+ return NULL;
+ }
+
+ /*
+ * Allocate a SCB and initialize mailbox
+ */
+ if (!(scb = megaraid_alloc_scb(adapter, scp))) {
+ scp->result = (DID_ERROR << 16);
+ *busy = 1;
+ return NULL;
+ }
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ scb->dev_channel = 0xFF;
+ scb->dev_target = target;
+ ccb->raw_mbox[0] = CLUSTER_CMD;
+ ccb->raw_mbox[2] = (scp->cmnd[0] == RESERVE) ?
+ RESERVE_LD : RELEASE_LD;
+
+ ccb->raw_mbox[3] = target;
+ scb->dma_direction = scp->sc_data_direction;
+
+ return scb;
+
+ default:
+ scp->result = (DID_BAD_TARGET << 16);
+ return NULL;
+ }
+ }
+ else { // Passthru device commands
+
+ // Do not allow access to target id > 15 or LUN > 7
+ if (target > 15 || SCP2LUN(scp) > 7) {
+ scp->result = (DID_BAD_TARGET << 16);
+ return NULL;
+ }
+
+ // if fast load option was set and scan for last device is
+ // over, reset the fast_load flag so that during a possible
+ // next scan, devices can be made available
+ if (rdev->fast_load && (target == 15) &&
+ (SCP2CHANNEL(scp) == adapter->max_channel -1)) {
+
+ con_log(CL_ANN, (KERN_INFO
+ "megaraid[%d]: physical device scan re-enabled\n",
+ adapter->host->host_no));
+ rdev->fast_load = 0;
+ }
+
+ /*
+ * Display the channel scan for physical devices
+ */
+ if (!(rdev->last_disp & (1L << SCP2CHANNEL(scp)))) {
+
+ ss = rdev->fast_load ? skip : scan;
+
+ con_log(CL_ANN, (KERN_INFO
+ "scsi[%d]: %s scsi channel %d [Phy %d]",
+ adapter->host->host_no, ss, SCP2CHANNEL(scp),
+ channel));
+
+ con_log(CL_ANN, (
+ " for non-raid devices\n"));
+
+ rdev->last_disp |= (1L << SCP2CHANNEL(scp));
+ }
+
+ // disable channel sweep if fast load option given
+ if (rdev->fast_load) {
+ scp->result = (DID_BAD_TARGET << 16);
+ return NULL;
+ }
+
+ // Allocate a SCB and initialize passthru
+ if (!(scb = megaraid_alloc_scb(adapter, scp))) {
+ scp->result = (DID_ERROR << 16);
+ *busy = 1;
+ return NULL;
+ }
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ scb->dev_channel = channel;
+ scb->dev_target = target;
+ scb->dma_direction = scp->sc_data_direction;
+ mbox = ccb->mbox;
+ mbox64 = ccb->mbox64;
+
+ // Does this firmware support extended CDBs
+ if (adapter->max_cdb_sz == 16) {
+ mbox->cmd = MBOXCMD_EXTPTHRU;
+
+ megaraid_mbox_prepare_epthru(adapter, scb, scp);
+
+ mbox64->xferaddr_lo = (uint32_t)ccb->epthru_dma_h;
+ mbox64->xferaddr_hi = 0;
+ mbox->xferaddr = 0xFFFFFFFF;
+ }
+ else {
+ mbox->cmd = MBOXCMD_PASSTHRU64;
+
+ megaraid_mbox_prepare_pthru(adapter, scb, scp);
+
+ mbox64->xferaddr_lo = (uint32_t)ccb->pthru_dma_h;
+ mbox64->xferaddr_hi = 0;
+ mbox->xferaddr = 0xFFFFFFFF;
+ }
+ return scb;
+ }
+
+ // NOT REACHED
+}
+
+
+/**
+ * megaraid_mbox_runpendq - execute commands queued in the pending queue
+ * @adapter : controller's soft state
+ * @scb : SCB to be queued in the pending list
+ *
+ * scan the pending list for commands which are not yet issued and try to
+ * post to the controller. The SCB can be a null pointer, which would indicate
+ * no SCB to be queue, just try to execute the ones in the pending list.
+ *
+ * NOTE: We do not actually traverse the pending list. The SCBs are plucked
+ * out from the head of the pending list. If it is successfully issued, the
+ * next SCB is at the head now.
+ */
+static void
+megaraid_mbox_runpendq(adapter_t *adapter, scb_t *scb_q)
+{
+ scb_t *scb;
+ unsigned long flags;
+
+ spin_lock_irqsave(PENDING_LIST_LOCK(adapter), flags);
+
+ if (scb_q) {
+ scb_q->state = SCB_PENDQ;
+ list_add_tail(&scb_q->list, &adapter->pend_list);
+ }
+
+ // if the adapter in not in quiescent mode, post the commands to FW
+ if (adapter->quiescent) {
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter), flags);
+ return;
+ }
+
+ while (!list_empty(&adapter->pend_list)) {
+
+ ASSERT(spin_is_locked(PENDING_LIST_LOCK(adapter)));
+
+ scb = list_entry(adapter->pend_list.next, scb_t, list);
+
+ // remove the scb from the pending list and try to
+ // issue. If we are unable to issue it, put back in
+ // the pending list and return
+
+ list_del_init(&scb->list);
+
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter), flags);
+
+ // if mailbox was busy, return SCB back to pending
+ // list. Make sure to add at the head, since that's
+ // where it would have been removed from
+
+ scb->state = SCB_ISSUED;
+
+ if (mbox_post_cmd(adapter, scb) != 0) {
+
+ spin_lock_irqsave(PENDING_LIST_LOCK(adapter), flags);
+
+ scb->state = SCB_PENDQ;
+
+ list_add(&scb->list, &adapter->pend_list);
+
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter),
+ flags);
+
+ return;
+ }
+
+ spin_lock_irqsave(PENDING_LIST_LOCK(adapter), flags);
+ }
+
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter), flags);
+
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_prepare_pthru - prepare a command for physical devices
+ * @adapter - pointer to controller's soft state
+ * @scb - scsi control block
+ * @scp - scsi command from the mid-layer
+ *
+ * prepare a command for the scsi physical devices
+ */
+static void
+megaraid_mbox_prepare_pthru(adapter_t *adapter, scb_t *scb,
+ struct scsi_cmnd *scp)
+{
+ mbox_ccb_t *ccb;
+ mraid_passthru_t *pthru;
+ uint8_t channel;
+ uint8_t target;
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ pthru = ccb->pthru;
+ channel = scb->dev_channel;
+ target = scb->dev_target;
+
+ pthru->timeout = 1; // 0=6sec, 1=60sec, 2=10min, 3=3hrs
+ pthru->ars = 1;
+ pthru->islogical = 0;
+ pthru->channel = 0;
+ pthru->target = (channel << 4) | target;
+ pthru->logdrv = SCP2LUN(scp);
+ pthru->reqsenselen = 14;
+ pthru->cdblen = scp->cmd_len;
+
+ memcpy(pthru->cdb, scp->cmnd, scp->cmd_len);
+
+ if (scp->request_bufflen) {
+ pthru->dataxferlen = scp->request_bufflen;
+ pthru->dataxferaddr = ccb->sgl_dma_h;
+ pthru->numsge = megaraid_mbox_mksgl(adapter, scb);
+ }
+ else {
+ pthru->dataxferaddr = 0;
+ pthru->dataxferlen = 0;
+ pthru->numsge = 0;
+ }
+ return;
+}
+
+
+/**
+ * megaraid_mbox_prepare_epthru - prepare a command for physical devices
+ * @adapter - pointer to controller's soft state
+ * @scb - scsi control block
+ * @scp - scsi command from the mid-layer
+ *
+ * prepare a command for the scsi physical devices. This rountine prepares
+ * commands for devices which can take extended CDBs (>10 bytes)
+ */
+static void
+megaraid_mbox_prepare_epthru(adapter_t *adapter, scb_t *scb,
+ struct scsi_cmnd *scp)
+{
+ mbox_ccb_t *ccb;
+ mraid_epassthru_t *epthru;
+ uint8_t channel;
+ uint8_t target;
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ epthru = ccb->epthru;
+ channel = scb->dev_channel;
+ target = scb->dev_target;
+
+ epthru->timeout = 1; // 0=6sec, 1=60sec, 2=10min, 3=3hrs
+ epthru->ars = 1;
+ epthru->islogical = 0;
+ epthru->channel = 0;
+ epthru->target = (channel << 4) | target;
+ epthru->logdrv = SCP2LUN(scp);
+ epthru->reqsenselen = 14;
+ epthru->cdblen = scp->cmd_len;
+
+ memcpy(epthru->cdb, scp->cmnd, scp->cmd_len);
+
+ if (scp->request_bufflen) {
+ epthru->dataxferlen = scp->request_bufflen;
+ epthru->dataxferaddr = ccb->sgl_dma_h;
+ epthru->numsge = megaraid_mbox_mksgl(adapter, scb);
+ }
+ else {
+ epthru->dataxferaddr = 0;
+ epthru->dataxferlen = 0;
+ epthru->numsge = 0;
+ }
+ return;
+}
+
+
+/**
+ * megaraid_ack_sequence - interrupt ack sequence for memory mapped HBAs
+ * @adapter - controller's soft state
+ *
+ * Interrupt ackrowledgement sequence for memory mapped HBAs. Find out the
+ * completed command and put them on the completed list for later processing.
+ *
+ * Returns: 1 if the interrupt is valid, 0 otherwise
+ */
+static inline int
+megaraid_ack_sequence(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mbox_t *mbox;
+ scb_t *scb;
+ uint8_t nstatus;
+ uint8_t completed[MBOX_MAX_FIRMWARE_STATUS];
+ struct list_head clist;
+ int handled;
+ uint32_t dword;
+ unsigned long flags;
+ int i, j;
+
+
+ mbox = raid_dev->mbox;
+
+ // move the SCBs from the firmware completed array to our local list
+ INIT_LIST_HEAD(&clist);
+
+ // loop till F/W has more commands for us to complete
+ handled = 0;
+ spin_lock_irqsave(MAILBOX_LOCK(raid_dev), flags);
+ do {
+ /*
+ * Check if a valid interrupt is pending. If found, force the
+ * interrupt line low.
+ */
+ dword = RDOUTDOOR(raid_dev);
+ if (dword != 0x10001234) break;
+
+ handled = 1;
+
+ WROUTDOOR(raid_dev, 0x10001234);
+
+ nstatus = 0;
+ // wait for valid numstatus to post
+ for (i = 0; i < 0xFFFFF; i++) {
+ if (mbox->numstatus != 0xFF) {
+ nstatus = mbox->numstatus;
+ break;
+ }
+ rmb();
+ }
+ mbox->numstatus = 0xFF;
+
+ adapter->outstanding_cmds -= nstatus;
+
+ for (i = 0; i < nstatus; i++) {
+
+ // wait for valid command index to post
+ for (j = 0; j < 0xFFFFF; j++) {
+ if (mbox->completed[i] != 0xFF) break;
+ rmb();
+ }
+ completed[i] = mbox->completed[i];
+ mbox->completed[i] = 0xFF;
+
+ if (completed[i] == 0xFF) {
+ con_log(CL_ANN, (KERN_CRIT
+ "megaraid: command posting timed out\n"));
+
+ BUG();
+ continue;
+ }
+
+ // Get SCB associated with this command id
+ if (completed[i] >= MBOX_MAX_SCSI_CMDS) {
+ // a cmm command
+ scb = adapter->uscb_list + (completed[i] -
+ MBOX_MAX_SCSI_CMDS);
+ }
+ else {
+ // an os command
+ scb = adapter->kscb_list + completed[i];
+ }
+
+ scb->status = mbox->status;
+ list_add_tail(&scb->list, &clist);
+ }
+
+ // Acknowledge interrupt
+ WRINDOOR(raid_dev, 0x02);
+
+ } while(1);
+
+ spin_unlock_irqrestore(MAILBOX_LOCK(raid_dev), flags);
+
+
+ // put the completed commands in the completed list. DPC would
+ // complete these commands later
+ spin_lock_irqsave(COMPLETED_LIST_LOCK(adapter), flags);
+
+ list_splice(&clist, &adapter->completed_list);
+
+ spin_unlock_irqrestore(COMPLETED_LIST_LOCK(adapter), flags);
+
+
+ // schedule the DPC if there is some work for it
+ if (handled)
+ tasklet_schedule(&adapter->dpc_h);
+
+ return handled;
+}
+
+
+/**
+ * megaraid_isr - isr for memory based mailbox based controllers
+ * @irq - irq
+ * @devp - pointer to our soft state
+ * @regs - unused
+ *
+ * Interrupt service routine for memory-mapped mailbox controllers.
+ */
+static irqreturn_t
+megaraid_isr(int irq, void *devp, struct pt_regs *regs)
+{
+ adapter_t *adapter = devp;
+ int handled;
+
+ handled = megaraid_ack_sequence(adapter);
+
+ /* Loop through any pending requests */
+ if (!adapter->quiescent) {
+ megaraid_mbox_runpendq(adapter, NULL);
+ }
+
+ return IRQ_RETVAL(handled);
+}
+
+
+/**
+ * megaraid_mbox_sync_scb - sync kernel buffers
+ * @adapter : controller's soft state
+ * @scb : pointer to the resource packet
+ *
+ * DMA sync if required.
+ */
+static inline void
+megaraid_mbox_sync_scb(adapter_t *adapter, scb_t *scb)
+{
+ mbox_ccb_t *ccb;
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+
+ switch (scb->dma_type) {
+
+ case MRAID_DMA_WBUF:
+ if (scb->dma_direction == PCI_DMA_FROMDEVICE) {
+ pci_dma_sync_single(adapter->pdev,
+ ccb->buf_dma_h,
+ scb->scp->request_bufflen,
+ PCI_DMA_FROMDEVICE);
+ }
+
+ pci_unmap_page(adapter->pdev, ccb->buf_dma_h,
+ scb->scp->request_bufflen, scb->dma_direction);
+
+ break;
+
+ case MRAID_DMA_WSG:
+ if (scb->dma_direction == PCI_DMA_FROMDEVICE) {
+ pci_dma_sync_sg(adapter->pdev,
+ scb->scp->request_buffer,
+ scb->scp->use_sg, PCI_DMA_FROMDEVICE);
+ }
+
+ pci_unmap_sg(adapter->pdev, scb->scp->request_buffer,
+ scb->scp->use_sg, scb->dma_direction);
+
+ break;
+
+ default:
+ break;
+ }
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_dpc - the tasklet to complete the commands from completed list
+ * @devp : pointer to HBA soft state
+ *
+ * Pick up the commands from the completed list and send back to the owners.
+ * This is a reentrant function and does not assume any locks are held while
+ * it is being called.
+ */
+static void
+megaraid_mbox_dpc(unsigned long devp)
+{
+ adapter_t *adapter = (adapter_t *)devp;
+ mraid_device_t *raid_dev;
+ struct list_head clist;
+ struct scatterlist *sgl;
+ scb_t *scb;
+ scb_t *tmp;
+ struct scsi_cmnd *scp;
+ mraid_passthru_t *pthru;
+ mraid_epassthru_t *epthru;
+ mbox_ccb_t *ccb;
+ int islogical;
+ int pdev_index;
+ int pdev_state;
+ mbox_t *mbox;
+ unsigned long flags;
+ uint8_t c;
+ int status;
+
+
+ if (!adapter) return;
+
+ raid_dev = ADAP2RAIDDEV(adapter);
+
+ // move the SCBs from the completed list to our local list
+ INIT_LIST_HEAD(&clist);
+
+ spin_lock_irqsave(COMPLETED_LIST_LOCK(adapter), flags);
+
+ list_splice_init(&adapter->completed_list, &clist);
+
+ spin_unlock_irqrestore(COMPLETED_LIST_LOCK(adapter), flags);
+
+
+ list_for_each_entry_safe(scb, tmp, &clist, list) {
+
+ status = scb->status;
+ scp = scb->scp;
+ ccb = (mbox_ccb_t *)scb->ccb;
+ pthru = ccb->pthru;
+ epthru = ccb->epthru;
+ mbox = ccb->mbox;
+
+ // Make sure f/w has completed a valid command
+ if (scb->state != SCB_ISSUED) {
+ con_log(CL_ANN, (KERN_CRIT
+ "megaraid critical err: invalid command %d:%d:%p\n",
+ scb->sno, scb->state, scp));
+ BUG();
+ continue; // Must never happen!
+ }
+
+ // check for the management command and complete it right away
+ if (scb->sno >= MBOX_MAX_SCSI_CMDS) {
+ scb->state = SCB_FREE;
+ scb->status = status;
+
+ // remove from local clist
+ list_del_init(&scb->list);
+
+ megaraid_mbox_mm_done(adapter, scb);
+
+ continue;
+ }
+
+ // Was an abort issued for this command earlier
+ if (scb->state & SCB_ABORT) {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid: aborted cmd %lx[%x] completed\n",
+ scp->serial_number, scb->sno));
+ }
+
+ /*
+ * If the inquiry came of a disk drive which is not part of
+ * any RAID array, expose it to the kernel. For this to be
+ * enabled, user must set the "megaraid_expose_unconf_disks"
+ * flag to 1 by specifying it on module parameter list.
+ * This would enable data migration off drives from other
+ * configurations.
+ */
+ islogical = MRAID_IS_LOGICAL(adapter, scp);
+ if (scp->cmnd[0] == INQUIRY && status == 0 && islogical == 0
+ && IS_RAID_CH(raid_dev, scb->dev_channel)) {
+
+ if (scp->use_sg) {
+ sgl = (struct scatterlist *)
+ scp->request_buffer;
+
+ if (sgl->page) {
+ c = *(unsigned char *)
+ (page_address((&sgl[0])->page) +
+ (&sgl[0])->offset);
+ }
+ else {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mailbox: invalid sg:%d\n",
+ __LINE__));
+ c = 0;
+ }
+ }
+ else {
+ c = *(uint8_t *)scp->request_buffer;
+ }
+
+ if ((c & 0x1F ) == TYPE_DISK) {
+ pdev_index = (scb->dev_channel * 16) +
+ scb->dev_target;
+ pdev_state =
+ raid_dev->pdrv_state[pdev_index] & 0x0F;
+
+ if (pdev_state == PDRV_ONLINE ||
+ pdev_state == PDRV_FAILED ||
+ pdev_state == PDRV_RBLD ||
+ pdev_state == PDRV_HOTSPARE ||
+ megaraid_expose_unconf_disks == 0) {
+
+ status = 0xF0;
+ }
+ }
+ }
+
+ // Convert MegaRAID status to Linux error code
+ switch (status) {
+
+ case 0x00:
+
+ scp->result = (DID_OK << 16);
+ break;
+
+ case 0x02:
+
+ /* set sense_buffer and result fields */
+ if (mbox->cmd == MBOXCMD_PASSTHRU ||
+ mbox->cmd == MBOXCMD_PASSTHRU64) {
+
+ memcpy(scp->sense_buffer, pthru->reqsensearea,
+ 14);
+
+ scp->result = DRIVER_SENSE << 24 |
+ DID_OK << 16 | CHECK_CONDITION << 1;
+ }
+ else {
+ if (mbox->cmd == MBOXCMD_EXTPTHRU) {
+
+ memcpy(scp->sense_buffer,
+ epthru->reqsensearea, 14);
+
+ scp->result = DRIVER_SENSE << 24 |
+ DID_OK << 16 |
+ CHECK_CONDITION << 1;
+ } else {
+ scp->sense_buffer[0] = 0x70;
+ scp->sense_buffer[2] = ABORTED_COMMAND;
+ scp->result = CHECK_CONDITION << 1;
+ }
+ }
+ break;
+
+ case 0x08:
+
+ scp->result = DID_BUS_BUSY << 16 | status;
+ break;
+
+ default:
+
+ /*
+ * If TEST_UNIT_READY fails, we know RESERVATION_STATUS
+ * failed
+ */
+ if (scp->cmnd[0] == TEST_UNIT_READY) {
+ scp->result = DID_ERROR << 16 |
+ RESERVATION_CONFLICT << 1;
+ }
+ else
+ /*
+ * Error code returned is 1 if Reserve or Release
+ * failed or the input parameter is invalid
+ */
+ if (status == 1 && (scp->cmnd[0] == RESERVE ||
+ scp->cmnd[0] == RELEASE)) {
+
+ scp->result = DID_ERROR << 16 |
+ RESERVATION_CONFLICT << 1;
+ }
+ else {
+ scp->result = DID_BAD_TARGET << 16 | status;
+ }
+ }
+
+ // print a debug message for all failed commands
+ if (status) {
+ megaraid_mbox_display_scb(adapter, scb);
+ }
+
+ // Free our internal resources and call the mid-layer callback
+ // routine
+ megaraid_mbox_sync_scb(adapter, scb);
+
+ // remove from local clist
+ list_del_init(&scb->list);
+
+ // put back in free list
+ megaraid_dealloc_scb(adapter, scb);
+
+ // send the scsi packet back to kernel
+ spin_lock(adapter->host_lock);
+ scp->scsi_done(scp);
+ spin_unlock(adapter->host_lock);
+ }
+
+ return;
+}
+
+
+/**
+ * megaraid_abort_handler - abort the scsi command
+ * @scp : command to be aborted
+ *
+ * Abort a previous SCSI request. Only commands on the pending list can be
+ * aborted. All the commands issued to the F/W must complete.
+ **/
+static int
+megaraid_abort_handler(struct scsi_cmnd *scp)
+{
+ adapter_t *adapter;
+ mraid_device_t *raid_dev;
+ scb_t *scb;
+ scb_t *tmp;
+ int found;
+ unsigned long flags;
+ int i;
+
+
+ adapter = SCP2ADAPTER(scp);
+ raid_dev = ADAP2RAIDDEV(adapter);
+
+ ASSERT(spin_is_locked(adapter->host_lock));
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: aborting-%ld cmd=%x <c=%d t=%d l=%d>\n",
+ scp->serial_number, scp->cmnd[0], SCP2CHANNEL(scp),
+ SCP2TARGET(scp), SCP2LUN(scp)));
+
+ // If FW has stopped responding, simply return failure
+ if (raid_dev->hw_error) {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid: hw error, not aborting\n"));
+ return FAILED;
+ }
+
+ // There might a race here, where the command was completed by the
+ // firmware and now it is on the completed list. Before we could
+ // complete the command to the kernel in dpc, the abort came.
+ // Find out if this is the case to avoid the race.
+ scb = NULL;
+ spin_lock_irqsave(COMPLETED_LIST_LOCK(adapter), flags);
+ list_for_each_entry_safe(scb, tmp, &adapter->completed_list, list) {
+
+ if (scb->scp == scp) { // Found command
+
+ list_del_init(&scb->list); // from completed list
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: %ld:%d[%d:%d], abort from completed list\n",
+ scp->serial_number, scb->sno,
+ scb->dev_channel, scb->dev_target));
+
+ scp->result = (DID_ABORT << 16);
+ scp->scsi_done(scp);
+
+ megaraid_dealloc_scb(adapter, scb);
+
+ spin_unlock_irqrestore(COMPLETED_LIST_LOCK(adapter),
+ flags);
+
+ return SUCCESS;
+ }
+ }
+ spin_unlock_irqrestore(COMPLETED_LIST_LOCK(adapter), flags);
+
+
+ // Find out if this command is still on the pending list. If it is and
+ // was never issued, abort and return success. If the command is owned
+ // by the firmware, we must wait for it to complete by the FW.
+ spin_lock_irqsave(PENDING_LIST_LOCK(adapter), flags);
+ list_for_each_entry_safe(scb, tmp, &adapter->pend_list, list) {
+
+ if (scb->scp == scp) { // Found command
+
+ list_del_init(&scb->list); // from pending list
+
+ ASSERT(!(scb->state & SCB_ISSUED));
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid abort: %ld[%d:%d], driver owner\n",
+ scp->serial_number, scb->dev_channel,
+ scb->dev_target));
+
+ scp->result = (DID_ABORT << 16);
+ scp->scsi_done(scp);
+
+ megaraid_dealloc_scb(adapter, scb);
+
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter),
+ flags);
+
+ return SUCCESS;
+ }
+ }
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter), flags);
+
+
+ // Check do we even own this command, in which case this would be
+ // owned by the firmware. The only way to locate the FW scb is to
+ // traverse through the list of all SCB, since driver does not
+ // maintain these SCBs on any list
+ found = 0;
+ for (i = 0; i < MBOX_MAX_SCSI_CMDS; i++) {
+ scb = adapter->kscb_list + i;
+
+ if (scb->scp == scp) {
+
+ found = 1;
+
+ if (!(scb->state & SCB_ISSUED)) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid abort: %ld%d[%d:%d], invalid state\n",
+ scp->serial_number, scb->sno, scb->dev_channel,
+ scb->dev_target));
+ BUG();
+ }
+ else {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid abort: %ld:%d[%d:%d], fw owner\n",
+ scp->serial_number, scb->sno, scb->dev_channel,
+ scb->dev_target));
+ }
+ }
+ }
+
+ if (!found) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid abort: scsi cmd:%ld, do now own\n",
+ scp->serial_number));
+
+ // FIXME: Should there be a callback for this command?
+ return SUCCESS;
+ }
+
+ // We cannot actually abort a command owned by firmware, return
+ // failure and wait for reset. In host reset handler, we will find out
+ // if the HBA is still live
+ return FAILED;
+}
+
+
+/**
+ * megaraid_reset_handler - device reset hadler for mailbox based driver
+ * @scp : reference command
+ *
+ * Reset handler for the mailbox based controller. First try to find out if
+ * the FW is still live, in which case the outstanding commands counter mut go
+ * down to 0. If that happens, also issue the reservation reset command to
+ * relinquish (possible) reservations on the logical drives connected to this
+ * host
+ **/
+static int
+megaraid_reset_handler(struct scsi_cmnd *scp)
+{
+ adapter_t *adapter;
+ scb_t *scb;
+ scb_t *tmp;
+ mraid_device_t *raid_dev;
+ unsigned long flags;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+ int rval;
+ int recovery_window;
+ int recovering;
+ int i;
+
+ adapter = SCP2ADAPTER(scp);
+ raid_dev = ADAP2RAIDDEV(adapter);
+
+ ASSERT(spin_is_locked(adapter->host_lock));
+
+ con_log(CL_ANN, (KERN_WARNING "megaraid: reseting the host...\n"));
+
+ // return failure if adapter is not responding
+ if (raid_dev->hw_error) {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid: hw error, cannot reset\n"));
+ return FAILED;
+ }
+
+
+ // Under exceptional conditions, FW can take up to 3 minutes to
+ // complete command processing. Wait for additional 2 minutes for the
+ // pending commands counter to go down to 0. If it doesn't, let the
+ // controller be marked offline
+ // Also, reset all the commands currently owned by the driver
+ spin_lock_irqsave(PENDING_LIST_LOCK(adapter), flags);
+ list_for_each_entry_safe(scb, tmp, &adapter->pend_list, list) {
+
+ list_del_init(&scb->list); // from pending list
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: %ld:%d[%d:%d], reset from pending list\n",
+ scp->serial_number, scb->sno,
+ scb->dev_channel, scb->dev_target));
+
+ scp->result = (DID_RESET << 16);
+ scp->scsi_done(scp);
+
+ megaraid_dealloc_scb(adapter, scb);
+ }
+ spin_unlock_irqrestore(PENDING_LIST_LOCK(adapter), flags);
+
+ if (adapter->outstanding_cmds) {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid: %d outstanding commands. Max wait %d sec\n",
+ adapter->outstanding_cmds, MBOX_RESET_WAIT));
+ }
+
+ spin_unlock(adapter->host_lock);
+
+ recovery_window = MBOX_RESET_WAIT + MBOX_RESET_EXT_WAIT;
+
+ recovering = adapter->outstanding_cmds;
+
+ for (i = 0; i < recovery_window && adapter->outstanding_cmds; i++) {
+
+ megaraid_ack_sequence(adapter);
+
+ // print a message once every 5 seconds only
+ if (!(i % 5)) {
+ con_log(CL_ANN, (
+ "megaraid mbox: Wait for %d commands to complete:%d\n",
+ adapter->outstanding_cmds,
+ MBOX_RESET_WAIT - i));
+ }
+
+ // bailout if no recovery happended in reset time
+ if ((i == MBOX_RESET_WAIT) &&
+ (recovering == adapter->outstanding_cmds)) {
+ break;
+ }
+
+ msleep(1000);
+ }
+
+ spin_lock(adapter->host_lock);
+
+ // If still outstanding commands, bail out
+ if (adapter->outstanding_cmds) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mbox: critical hardware error!\n"));
+
+ raid_dev->hw_error = 1;
+
+ return FAILED;
+ }
+ else {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid mbox: reset sequence completed sucessfully\n"));
+ }
+
+
+ // If the controller supports clustering, reset reservations
+ if (!adapter->ha) return SUCCESS;
+
+ // clear reservations if any
+ raw_mbox[0] = CLUSTER_CMD;
+ raw_mbox[2] = RESET_RESERVATIONS;
+
+ rval = SUCCESS;
+ if (mbox_post_sync_cmd_fast(adapter, raw_mbox) == 0) {
+ con_log(CL_ANN,
+ (KERN_INFO "megaraid: reservation reset\n"));
+ }
+ else {
+ rval = FAILED;
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: reservation reset failed\n"));
+ }
+
+ return rval;
+}
+
+
+/*
+ * START: internal commands library
+ *
+ * This section of the driver has the common routine used by the driver and
+ * also has all the FW routines
+ */
+
+/**
+ * mbox_post_sync_cmd() - blocking command to the mailbox based controllers
+ * @adapter - controller's soft state
+ * @raw_mbox - the mailbox
+ *
+ * Issue a scb in synchronous and non-interrupt mode for mailbox based
+ * controllers
+ */
+static int
+mbox_post_sync_cmd(adapter_t *adapter, uint8_t raw_mbox[])
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mbox64_t *mbox64;
+ mbox_t *mbox;
+ uint8_t status;
+ int i;
+
+
+ mbox64 = raid_dev->mbox64;
+ mbox = raid_dev->mbox;
+
+ /*
+ * Wait until mailbox is free
+ */
+ if (megaraid_busywait_mbox(raid_dev) != 0)
+ goto blocked_mailbox;
+
+ /*
+ * Copy mailbox data into host structure
+ */
+ memcpy((caddr_t)mbox, (caddr_t)raw_mbox, 16);
+ mbox->cmdid = 0xFE;
+ mbox->busy = 1;
+ mbox->poll = 0;
+ mbox->ack = 0;
+ mbox->numstatus = 0xFF;
+ mbox->status = 0xFF;
+
+ wmb();
+ WRINDOOR(raid_dev, raid_dev->mbox_dma | 0x1);
+
+ // wait for maximum 1 second for status to post. If the status is not
+ // available within 1 second, assume FW is initializing and wait
+ // for an extended amount of time
+ if (mbox->numstatus == 0xFF) { // status not yet available
+ udelay(25);;
+
+ for (i = 0; mbox->numstatus == 0xFF && i < 1000; i++) {
+ rmb();
+ msleep(1);
+ }
+
+
+ if (i == 1000) {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid mailbox: wait for FW to boot "));
+
+ for (i = 0; (mbox->numstatus == 0xFF) &&
+ (i < MBOX_RESET_WAIT); i++) {
+ rmb();
+ con_log(CL_ANN, ("\b\b\b\b\b[%03d]",
+ MBOX_RESET_WAIT - i));
+ msleep(1000);
+ }
+
+ if (i == MBOX_RESET_WAIT) {
+
+ con_log(CL_ANN, (
+ "\nmegaraid mailbox: status not available\n"));
+
+ return -1;
+ }
+ con_log(CL_ANN, ("\b\b\b\b\b[ok] \n"));
+ }
+ }
+
+ // wait for maximum 1 second for poll semaphore
+ if (mbox->poll != 0x77) {
+ udelay(25);
+
+ for (i = 0; (mbox->poll != 0x77) && (i < 1000); i++) {
+ rmb();
+ msleep(1);
+ }
+
+ if (i == 1000) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mailbox: could not get poll semaphore\n"));
+ return -1;
+ }
+ }
+
+ WRINDOOR(raid_dev, raid_dev->mbox_dma | 0x2);
+ wmb();
+
+ // wait for maximum 1 second for acknowledgement
+ if (RDINDOOR(raid_dev) & 0x2) {
+ udelay(25);
+
+ for (i = 0; (RDINDOOR(raid_dev) & 0x2) && (i < 1000); i++) {
+ rmb();
+ msleep(1);
+ }
+
+ if (i == 1000) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mailbox: could not acknowledge\n"));
+ return -1;
+ }
+ }
+ mbox->poll = 0;
+ mbox->ack = 0x77;
+
+ status = mbox->status;
+
+ // invalidate the completed command id array. After command
+ // completion, firmware would write the valid id.
+ mbox->numstatus = 0xFF;
+ mbox->status = 0xFF;
+ for (i = 0; i < MBOX_MAX_FIRMWARE_STATUS; i++) {
+ mbox->completed[i] = 0xFF;
+ }
+
+ return status;
+
+blocked_mailbox:
+
+ con_log(CL_ANN, (KERN_WARNING "megaraid: blocked mailbox\n") );
+ return -1;
+}
+
+
+/**
+ * mbox_post_sync_cmd_fast - blocking command to the mailbox based controllers
+ * @adapter - controller's soft state
+ * @raw_mbox - the mailbox
+ *
+ * Issue a scb in synchronous and non-interrupt mode for mailbox based
+ * controllers. This is a faster version of the synchronous command and
+ * therefore can be called in interrupt-context as well
+ */
+static int
+mbox_post_sync_cmd_fast(adapter_t *adapter, uint8_t raw_mbox[])
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mbox_t *mbox;
+ long i;
+
+
+ mbox = raid_dev->mbox;
+
+ // return immediately if the mailbox is busy
+ if (mbox->busy) return -1;
+
+ // Copy mailbox data into host structure
+ memcpy((caddr_t)mbox, (caddr_t)raw_mbox, 14);
+ mbox->cmdid = 0xFE;
+ mbox->busy = 1;
+ mbox->poll = 0;
+ mbox->ack = 0;
+ mbox->numstatus = 0xFF;
+ mbox->status = 0xFF;
+
+ wmb();
+ WRINDOOR(raid_dev, raid_dev->mbox_dma | 0x1);
+
+ for (i = 0; i < 0xFFFFF; i++) {
+ if (mbox->numstatus != 0xFF) break;
+ }
+
+ if (i == 0xFFFFF) {
+ // We may need to re-calibrate the counter
+ con_log(CL_ANN, (KERN_CRIT
+ "megaraid: fast sync command timed out\n"));
+ }
+
+ WRINDOOR(raid_dev, raid_dev->mbox_dma | 0x2);
+ wmb();
+
+ return mbox->status;
+}
+
+
+/**
+ * megaraid_busywait_mbox() - Wait until the controller's mailbox is available
+ * @raid_dev - RAID device (HBA) soft state
+ *
+ * wait until the controller's mailbox is available to accept more commands.
+ * wait for at most 1 second
+ */
+static int
+megaraid_busywait_mbox(mraid_device_t *raid_dev)
+{
+ mbox_t *mbox = raid_dev->mbox;
+ int i = 0;
+
+ if (mbox->busy) {
+ udelay(25);
+ for (i = 0; mbox->busy && i < 1000; i++)
+ msleep(1);
+ }
+
+ if (i < 1000) return 0;
+ else return -1;
+}
+
+
+/**
+ * megaraid_mbox_product_info - some static information about the controller
+ * @adapter - our soft state
+ *
+ * issue commands to the controller to grab some parameters required by our
+ * caller.
+ */
+static int
+megaraid_mbox_product_info(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+ mraid_pinfo_t *pinfo;
+ dma_addr_t pinfo_dma_h;
+ mraid_inquiry3_t *mraid_inq3;
+ int i;
+
+
+ memset((caddr_t)raw_mbox, 0, sizeof(raw_mbox));
+ mbox = (mbox_t *)raw_mbox;
+
+ /*
+ * Issue an ENQUIRY3 command to find out certain adapter parameters,
+ * e.g., max channels, max commands etc.
+ */
+ pinfo = pci_alloc_consistent(adapter->pdev, sizeof(mraid_pinfo_t),
+ &pinfo_dma_h);
+
+ if (pinfo == NULL) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+
+ return -1;
+ }
+ memset(pinfo, 0, sizeof(mraid_pinfo_t));
+
+ mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h;
+ memset((void *)adapter->ibuf, 0, MBOX_IBUF_SIZE);
+
+ raw_mbox[0] = FC_NEW_CONFIG;
+ raw_mbox[2] = NC_SUBOP_ENQUIRY3;
+ raw_mbox[3] = ENQ3_GET_SOLICITED_FULL;
+
+ // Issue the command
+ if (mbox_post_sync_cmd(adapter, raw_mbox) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING "megaraid: Inquiry3 failed\n"));
+
+ pci_free_consistent(adapter->pdev, sizeof(mraid_pinfo_t),
+ pinfo, pinfo_dma_h);
+
+ return -1;
+ }
+
+ /*
+ * Collect information about state of each physical drive
+ * attached to the controller. We will expose all the disks
+ * which are not part of RAID
+ */
+ mraid_inq3 = (mraid_inquiry3_t *)adapter->ibuf;
+ for (i = 0; i < MBOX_MAX_PHYSICAL_DRIVES; i++) {
+ raid_dev->pdrv_state[i] = mraid_inq3->pdrv_state[i];
+ }
+
+ /*
+ * Get product info for information like number of channels,
+ * maximum commands supported.
+ */
+ memset((caddr_t)raw_mbox, 0, sizeof(raw_mbox));
+ mbox->xferaddr = (uint32_t)pinfo_dma_h;
+
+ raw_mbox[0] = FC_NEW_CONFIG;
+ raw_mbox[2] = NC_SUBOP_PRODUCT_INFO;
+
+ if (mbox_post_sync_cmd(adapter, raw_mbox) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: product info failed\n"));
+
+ pci_free_consistent(adapter->pdev, sizeof(mraid_pinfo_t),
+ pinfo, pinfo_dma_h);
+
+ return -1;
+ }
+
+ /*
+ * Setup some parameters for host, as required by our caller
+ */
+ adapter->max_channel = pinfo->nchannels;
+
+ /*
+ * we will export all the logical drives on a single channel.
+ * Add 1 since inquires do not come for inititor ID
+ */
+ adapter->max_target = MAX_LOGICAL_DRIVES_40LD + 1;
+ adapter->max_lun = 8; // up to 8 LUNs for non-disk devices
+
+ /*
+ * These are the maximum outstanding commands for the scsi-layer
+ */
+ adapter->max_cmds = MBOX_MAX_SCSI_CMDS;
+
+ memset(adapter->fw_version, 0, VERSION_SIZE);
+ memset(adapter->bios_version, 0, VERSION_SIZE);
+
+ memcpy(adapter->fw_version, pinfo->fw_version, 4);
+ adapter->fw_version[4] = 0;
+
+ memcpy(adapter->bios_version, pinfo->bios_version, 4);
+ adapter->bios_version[4] = 0;
+
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid: fw version:[%s] bios version:[%s]\n",
+ adapter->fw_version, adapter->bios_version));
+
+ pci_free_consistent(adapter->pdev, sizeof(mraid_pinfo_t), pinfo,
+ pinfo_dma_h);
+
+ return 0;
+}
+
+
+
+/**
+ * megaraid_mbox_extended_cdb - check for support for extended CDBs
+ * @adapter - soft state for the controller
+ *
+ * this routine check whether the controller in question supports extended
+ * ( > 10 bytes ) CDBs
+ */
+static int
+megaraid_mbox_extended_cdb(adapter_t *adapter)
+{
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+ int rval;
+
+ mbox = (mbox_t *)raw_mbox;
+
+ memset((caddr_t)raw_mbox, 0, sizeof(raw_mbox));
+ mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h;
+
+ memset((void *)adapter->ibuf, 0, MBOX_IBUF_SIZE);
+
+ raw_mbox[0] = MAIN_MISC_OPCODE;
+ raw_mbox[2] = SUPPORT_EXT_CDB;
+
+ /*
+ * Issue the command
+ */
+ rval = 0;
+ if (mbox_post_sync_cmd(adapter, raw_mbox) != 0) {
+ rval = -1;
+ }
+
+ return rval;
+}
+
+
+/**
+ * megaraid_mbox_support_ha - Do we support clustering
+ * @adapter - soft state for the controller
+ * @init_id - ID of the initiator
+ *
+ * Determine if the firmware supports clustering and the ID of the initiator.
+ */
+static int
+megaraid_mbox_support_ha(adapter_t *adapter, uint16_t *init_id)
+{
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+ int rval;
+
+
+ mbox = (mbox_t *)raw_mbox;
+
+ memset((caddr_t)raw_mbox, 0, sizeof(raw_mbox));
+
+ mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h;
+
+ memset((void *)adapter->ibuf, 0, MBOX_IBUF_SIZE);
+
+ raw_mbox[0] = GET_TARGET_ID;
+
+ // Issue the command
+ *init_id = 7;
+ rval = -1;
+ if (mbox_post_sync_cmd(adapter, raw_mbox) == 0) {
+
+ *init_id = *(uint8_t *)adapter->ibuf;
+
+ con_log(CL_ANN, (KERN_INFO
+ "megaraid: cluster firmware, initiator ID: %d\n",
+ *init_id));
+
+ rval = 0;
+ }
+
+ return rval;
+}
+
+
+/**
+ * megaraid_mbox_support_random_del - Do we support random deletion
+ * @adapter - soft state for the controller
+ *
+ * Determine if the firmware supports random deletion
+ * Return: 1 is operation supported, 0 otherwise
+ */
+static int
+megaraid_mbox_support_random_del(adapter_t *adapter)
+{
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+ int rval;
+
+
+ mbox = (mbox_t *)raw_mbox;
+
+ memset((caddr_t)raw_mbox, 0, sizeof(mbox_t));
+
+ raw_mbox[0] = FC_DEL_LOGDRV;
+ raw_mbox[0] = OP_SUP_DEL_LOGDRV;
+
+ // Issue the command
+ rval = 0;
+ if (mbox_post_sync_cmd(adapter, raw_mbox) == 0) {
+
+ con_log(CL_DLEVEL1, ("megaraid: supports random deletion\n"));
+
+ rval = 1;
+ }
+
+ return rval;
+}
+
+
+/**
+ * megaraid_mbox_get_max_sg - maximum sg elements supported by the firmware
+ * @adapter - soft state for the controller
+ *
+ * Find out the maximum number of scatter-gather elements supported by the
+ * firmware
+ */
+static int
+megaraid_mbox_get_max_sg(adapter_t *adapter)
+{
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+ int nsg;
+
+
+ mbox = (mbox_t *)raw_mbox;
+
+ memset((caddr_t)raw_mbox, 0, sizeof(mbox_t));
+
+ mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h;
+
+ memset((void *)adapter->ibuf, 0, MBOX_IBUF_SIZE);
+
+ raw_mbox[0] = MAIN_MISC_OPCODE;
+ raw_mbox[2] = GET_MAX_SG_SUPPORT;
+
+ // Issue the command
+ if (mbox_post_sync_cmd(adapter, raw_mbox) == 0) {
+ nsg = *(uint8_t *)adapter->ibuf;
+ }
+ else {
+ nsg = MBOX_DEFAULT_SG_SIZE;
+ }
+
+ if (nsg > MBOX_MAX_SG_SIZE) nsg = MBOX_MAX_SG_SIZE;
+
+ return nsg;
+}
+
+
+/**
+ * megaraid_mbox_enum_raid_scsi - enumerate the RAID and SCSI channels
+ * @adapter - soft state for the controller
+ *
+ * Enumerate the RAID and SCSI channels for ROMB platoforms so that channels
+ * can be exported as regular SCSI channels
+ */
+static void
+megaraid_mbox_enum_raid_scsi(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+
+
+ mbox = (mbox_t *)raw_mbox;
+
+ memset((caddr_t)raw_mbox, 0, sizeof(mbox_t));
+
+ mbox->xferaddr = (uint32_t)adapter->ibuf_dma_h;
+
+ memset((void *)adapter->ibuf, 0, MBOX_IBUF_SIZE);
+
+ raw_mbox[0] = CHNL_CLASS;
+ raw_mbox[2] = GET_CHNL_CLASS;
+
+ // Issue the command. If the command fails, all channels are RAID
+ // channels
+ raid_dev->channel_class = 0xFF;
+ if (mbox_post_sync_cmd(adapter, raw_mbox) == 0) {
+ raid_dev->channel_class = *(uint8_t *)adapter->ibuf;
+ }
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_flush_cache - flush adapter and disks cache
+ * @param adapter : soft state for the controller
+ *
+ * Flush adapter cache followed by disks cache
+ */
+static void
+megaraid_mbox_flush_cache(adapter_t *adapter)
+{
+ mbox_t *mbox;
+ uint8_t raw_mbox[sizeof(mbox_t)];
+
+
+ mbox = (mbox_t *)raw_mbox;
+
+ memset((caddr_t)raw_mbox, 0, sizeof(mbox_t));
+
+ raw_mbox[0] = FLUSH_ADAPTER;
+
+ if (mbox_post_sync_cmd(adapter, raw_mbox) != 0) {
+ con_log(CL_ANN, ("megaraid: flush adapter failed\n"));
+ }
+
+ raw_mbox[0] = FLUSH_SYSTEM;
+
+ if (mbox_post_sync_cmd(adapter, raw_mbox) != 0) {
+ con_log(CL_ANN, ("megaraid: flush disks cache failed\n"));
+ }
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_display_scb - display SCB information, mostly debug purposes
+ * @param adapter : controllers' soft state
+ * @param scb : SCB to be displayed
+ * @param level : debug level for console print
+ *
+ * Diplay information about the given SCB iff the current debug level is
+ * verbose
+ */
+static void
+megaraid_mbox_display_scb(adapter_t *adapter, scb_t *scb)
+{
+ mbox_ccb_t *ccb;
+ struct scsi_cmnd *scp;
+ mbox_t *mbox;
+ int level;
+ int i;
+
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ scp = scb->scp;
+ mbox = ccb->mbox;
+
+ level = CL_DLEVEL3;
+
+ con_log(level, (KERN_NOTICE
+ "megaraid mailbox: status:%#x cmd:%#x id:%#x ", scb->status,
+ mbox->cmd, scb->sno));
+
+ con_log(level, ("sec:%#x lba:%#x addr:%#x ld:%d sg:%d\n",
+ mbox->numsectors, mbox->lba, mbox->xferaddr, mbox->logdrv,
+ mbox->numsge));
+
+ if (!scp) return;
+
+ con_log(level, (KERN_NOTICE "scsi cmnd: "));
+
+ for (i = 0; i < scp->cmd_len; i++) {
+ con_log(level, ("%#2.02x ", scp->cmnd[i]));
+ }
+
+ con_log(level, ("\n"));
+
+ return;
+}
+
+
+/**
+ * megaraid_mbox_setup_device_map - manage device ids
+ * @adapter : Driver's soft state
+ *
+ * Manange the device ids to have an appropraite mapping between the kernel
+ * scsi addresses and megaraid scsi and logical drive addresses. We export
+ * scsi devices on their actual addresses, whereas the logical drives are
+ * exported on a virtual scsi channel.
+ **/
+static void
+megaraid_mbox_setup_device_map(adapter_t *adapter)
+{
+ uint8_t c;
+ uint8_t t;
+
+ /*
+ * First fill the values on the logical drive channel
+ */
+ for (t = 0; t < LSI_MAX_LOGICAL_DRIVES_64LD; t++)
+ adapter->device_ids[adapter->max_channel][t] =
+ (t < adapter->init_id) ? t : t - 1;
+
+ adapter->device_ids[adapter->max_channel][adapter->init_id] = 0xFF;
+
+ /*
+ * Fill the values on the physical devices channels
+ */
+ for (c = 0; c < adapter->max_channel; c++)
+ for (t = 0; t < LSI_MAX_LOGICAL_DRIVES_64LD; t++)
+ adapter->device_ids[c][t] = (c << 8) | t;
+}
+
+
+/*
+ * END: internal commands library
+ */
+
+/*
+ * START: Interface for the common management module
+ *
+ * This is the module, which interfaces with the common mangement module to
+ * provide support for ioctl and sysfs
+ */
+
+/**
+ * megaraid_cmm_register - register with the mangement module
+ * @param adapter : HBA soft state
+ *
+ * Register with the management module, which allows applications to issue
+ * ioctl calls to the drivers. This interface is used by the management module
+ * to setup sysfs support as well.
+ */
+static int
+megaraid_cmm_register(adapter_t *adapter)
+{
+ mraid_device_t *raid_dev = ADAP2RAIDDEV(adapter);
+ mraid_mmadp_t adp;
+ scb_t *scb;
+ mbox_ccb_t *ccb;
+ int rval;
+ int i;
+
+ // Allocate memory for the base list of scb for management module.
+ adapter->uscb_list = kmalloc(sizeof(scb_t) * MBOX_MAX_USER_CMDS,
+ GFP_KERNEL);
+
+ if (adapter->uscb_list == NULL) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+ return -1;
+ }
+ memset(adapter->uscb_list, 0, sizeof(scb_t) * MBOX_MAX_USER_CMDS);
+
+
+ // Initialize the synchronization parameters for resources for
+ // commands for management module
+ INIT_LIST_HEAD(&adapter->uscb_pool);
+
+ spin_lock_init(USER_FREE_LIST_LOCK(adapter));
+
+
+
+ // link all the packets. Note, CCB for commands, coming from the
+ // commom management module, mailbox physical address are already
+ // setup by it. We just need placeholder for that in our local command
+ // control blocks
+ for (i = 0; i < MBOX_MAX_USER_CMDS; i++) {
+
+ scb = adapter->uscb_list + i;
+ ccb = raid_dev->uccb_list + i;
+
+ scb->ccb = (caddr_t)ccb;
+ ccb->mbox64 = raid_dev->umbox64 + i;
+ ccb->mbox = &ccb->mbox64->mbox32;
+ ccb->raw_mbox = (uint8_t *)ccb->mbox;
+
+ scb->gp = 0;
+
+ // COMMAND ID 0 - (MBOX_MAX_SCSI_CMDS-1) ARE RESERVED FOR
+ // COMMANDS COMING FROM IO SUBSYSTEM (MID-LAYER)
+ scb->sno = i + MBOX_MAX_SCSI_CMDS;
+
+ scb->scp = NULL;
+ scb->state = SCB_FREE;
+ scb->dma_direction = PCI_DMA_NONE;
+ scb->dma_type = MRAID_DMA_NONE;
+ scb->dev_channel = -1;
+ scb->dev_target = -1;
+
+ // put scb in the free pool
+ list_add_tail(&scb->list, &adapter->uscb_pool);
+ }
+
+ adp.unique_id = adapter->unique_id;
+ adp.drvr_type = DRVRTYPE_MBOX;
+ adp.drvr_data = (unsigned long)adapter;
+ adp.pdev = adapter->pdev;
+ adp.issue_uioc = megaraid_mbox_mm_handler;
+ adp.timeout = 30;
+ adp.max_kioc = MBOX_MAX_USER_CMDS;
+
+ if ((rval = mraid_mm_register_adp(&adp)) != 0) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mbox: did not register with CMM\n"));
+
+ kfree(adapter->uscb_list);
+ }
+
+ return rval;
+}
+
+
+/**
+ * megaraid_cmm_unregister - un-register with the mangement module
+ * @param adapter : HBA soft state
+ *
+ * Un-register with the management module.
+ * FIXME: mgmt module must return failure for unregister if it has pending
+ * commands in LLD
+ */
+static int
+megaraid_cmm_unregister(adapter_t *adapter)
+{
+ kfree(adapter->uscb_list);
+ mraid_mm_unregister_adp(adapter->unique_id);
+ return 0;
+}
+
+
+/**
+ * megaraid_mbox_mm_handler - interface for CMM to issue commands to LLD
+ * @param drvr_data : LLD specific data
+ * @param kioc : CMM interface packet
+ * @param action : command action
+ *
+ * This routine is invoked whenever the Common Mangement Module (CMM) has a
+ * command for us. The 'action' parameter specifies if this is a new command
+ * or otherwise.
+ */
+static int
+megaraid_mbox_mm_handler(unsigned long drvr_data, uioc_t *kioc, uint32_t action)
+{
+ adapter_t *adapter;
+
+ if (action != IOCTL_ISSUE) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: unsupported management action:%#2x\n",
+ action));
+ return (-ENOTSUPP);
+ }
+
+ adapter = (adapter_t *)drvr_data;
+
+ // make sure this adapter is not being detached right now.
+ if (atomic_read(&adapter->being_detached)) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid: reject management request, detaching\n"));
+ return (-ENODEV);
+ }
+
+ switch (kioc->opcode) {
+
+ case GET_ADAP_INFO:
+
+ kioc->status = gather_hbainfo(adapter, (mraid_hba_info_t *)
+ (unsigned long)kioc->buf_vaddr);
+
+ kioc->done(kioc);
+
+ return kioc->status;
+
+ case MBOX_CMD:
+
+ return megaraid_mbox_mm_command(adapter, kioc);
+
+ default:
+ kioc->status = (-EINVAL);
+ kioc->done(kioc);
+ return (-EINVAL);
+ }
+
+ return 0; // not reached
+}
+
+/**
+ * megaraid_mbox_mm_command - issues commands routed through CMM
+ * @param adapter : HBA soft state
+ * @param kioc : management command packet
+ *
+ * Issues commands, which are routed through the management module.
+ */
+static int
+megaraid_mbox_mm_command(adapter_t *adapter, uioc_t *kioc)
+{
+ struct list_head *head = &adapter->uscb_pool;
+ mbox64_t *mbox64;
+ uint8_t *raw_mbox;
+ scb_t *scb;
+ mbox_ccb_t *ccb;
+ unsigned long flags;
+
+ // detach one scb from free pool
+ spin_lock_irqsave(USER_FREE_LIST_LOCK(adapter), flags);
+
+ if (list_empty(head)) { // should never happen because of CMM
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid mbox: bug in cmm handler, lost resources\n"));
+
+ spin_unlock_irqrestore(USER_FREE_LIST_LOCK(adapter), flags);
+
+ return (-EINVAL);
+ }
+
+ scb = list_entry(head->next, scb_t, list);
+ list_del_init(&scb->list);
+
+ spin_unlock_irqrestore(USER_FREE_LIST_LOCK(adapter), flags);
+
+ scb->state = SCB_ACTIVE;
+ scb->dma_type = MRAID_DMA_NONE;
+
+ ccb = (mbox_ccb_t *)scb->ccb;
+ mbox64 = (mbox64_t *)(unsigned long)kioc->cmdbuf;
+ raw_mbox = (uint8_t *)&mbox64->mbox32;
+
+ memcpy(ccb->mbox64, mbox64, sizeof(mbox64_t));
+
+ scb->gp = (unsigned long)kioc;
+
+ /*
+ * If it is a logdrv random delete operation, we have to wait till
+ * there are no outstanding cmds at the fw and then issue it directly
+ */
+ if (raw_mbox[0] == FC_DEL_LOGDRV && raw_mbox[2] == OP_DEL_LOGDRV) {
+
+ if (wait_till_fw_empty(adapter)) {
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid mbox: LD delete, timed out\n"));
+
+ kioc->status = -ETIME;
+
+ scb->status = -1;
+
+ megaraid_mbox_mm_done(adapter, scb);
+
+ return (-ETIME);
+ }
+
+ INIT_LIST_HEAD(&scb->list);
+
+ scb->state = SCB_ISSUED;
+ if (mbox_post_cmd(adapter, scb) != 0) {
+
+ con_log(CL_ANN, (KERN_NOTICE
+ "megaraid mbox: LD delete, mailbox busy\n"));
+
+ kioc->status = -EBUSY;
+
+ scb->status = -1;
+
+ megaraid_mbox_mm_done(adapter, scb);
+
+ return (-EBUSY);
+ }
+
+ return 0;
+ }
+
+ // put the command on the pending list and execute
+ megaraid_mbox_runpendq(adapter, scb);
+
+ return 0;
+}
+
+
+static int
+wait_till_fw_empty(adapter_t *adapter)
+{
+ unsigned long flags = 0;
+ int i;
+
+
+ /*
+ * Set the quiescent flag to stop issuing cmds to FW.
+ */
+ spin_lock_irqsave(adapter->host_lock, flags);
+ adapter->quiescent++;
+ spin_unlock_irqrestore(adapter->host_lock, flags);
+
+ /*
+ * Wait till there are no more cmds outstanding at FW. Try for at most
+ * 60 seconds
+ */
+ for (i = 0; i < 60 && adapter->outstanding_cmds; i++) {
+ con_log(CL_DLEVEL1, (KERN_INFO
+ "megaraid: FW has %d pending commands\n",
+ adapter->outstanding_cmds));
+
+ msleep(1000);
+ }
+
+ return adapter->outstanding_cmds;
+}
+
+
+/**
+ * megaraid_mbox_mm_done - callback for CMM commands
+ * @adapter : HBA soft state
+ * @scb : completed command
+ *
+ * Callback routine for internal commands originated from the management
+ * module.
+ */
+static void
+megaraid_mbox_mm_done(adapter_t *adapter, scb_t *scb)
+{
+ uioc_t *kioc;
+ mbox64_t *mbox64;
+ uint8_t *raw_mbox;
+ unsigned long flags;
+
+ kioc = (uioc_t *)scb->gp;
+ kioc->status = 0;
+ mbox64 = (mbox64_t *)(unsigned long)kioc->cmdbuf;
+ mbox64->mbox32.status = scb->status;
+ raw_mbox = (uint8_t *)&mbox64->mbox32;
+
+
+ // put scb in the free pool
+ scb->state = SCB_FREE;
+ scb->scp = NULL;
+
+ spin_lock_irqsave(USER_FREE_LIST_LOCK(adapter), flags);
+
+ list_add(&scb->list, &adapter->uscb_pool);
+
+ spin_unlock_irqrestore(USER_FREE_LIST_LOCK(adapter), flags);
+
+ // if a delete logical drive operation succeeded, restart the
+ // controller
+ if (raw_mbox[0] == FC_DEL_LOGDRV && raw_mbox[2] == OP_DEL_LOGDRV) {
+
+ adapter->quiescent--;
+
+ megaraid_mbox_runpendq(adapter, NULL);
+ }
+
+ kioc->done(kioc);
+
+ return;
+}
+
+
+/**
+ * gather_hbainfo - HBA characteristics for the applications
+ * @param adapter : HBA soft state
+ * @param hinfo : pointer to the caller's host info strucuture
+ */
+static int
+gather_hbainfo(adapter_t *adapter, mraid_hba_info_t *hinfo)
+{
+ uint8_t dmajor;
+
+ dmajor = megaraid_mbox_version[0];
+
+ hinfo->pci_vendor_id = adapter->pdev->vendor;
+ hinfo->pci_device_id = adapter->pdev->device;
+ hinfo->subsys_vendor_id = adapter->pdev->subsystem_vendor;
+ hinfo->subsys_device_id = adapter->pdev->subsystem_device;
+
+ hinfo->pci_bus = adapter->pdev->bus->number;
+ hinfo->pci_dev_fn = adapter->pdev->devfn;
+ hinfo->pci_slot = PCI_SLOT(adapter->pdev->devfn);
+ hinfo->irq = adapter->host->irq;
+ hinfo->baseport = ADAP2RAIDDEV(adapter)->baseport;
+
+ hinfo->unique_id = (hinfo->pci_bus << 8) | adapter->pdev->devfn;
+ hinfo->host_no = adapter->host->host_no;
+
+ return 0;
+}
+
+/*
+ * END: Interface for the common management module
+ */
+
+
+/*
+ * END: Mailbox Low Level Driver
+ */
+module_init(megaraid_init);
+module_exit(megaraid_exit);
+
+/* vim: set ts=8 sw=8 tw=78 ai si: */
--- /dev/null
+/*
+ *
+ * Linux MegaRAID device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : megaraid_mbox.h
+ */
+
+#ifndef _MEGARAID_H_
+#define _MEGARAID_H_
+
+
+#include "mega_common.h"
+#include "mbox_defs.h"
+#include "megaraid_ioctl.h"
+
+
+#define MEGARAID_VERSION "2.20.4.0"
+#define MEGARAID_EXT_VERSION "(Release Date: Mon Sep 27 22:15:07 EDT 2004)"
+
+
+/*
+ * Define some PCI values here until they are put in the kernel
+ */
+#define PCI_DEVICE_ID_PERC4_DI_DISCOVERY 0x000E
+#define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY 0x0123
+
+#define PCI_DEVICE_ID_PERC4_SC 0x1960
+#define PCI_SUBSYS_ID_PERC4_SC 0x0520
+
+#define PCI_DEVICE_ID_PERC4_DC 0x1960
+#define PCI_SUBSYS_ID_PERC4_DC 0x0518
+
+#define PCI_DEVICE_ID_PERC4_QC 0x0407
+#define PCI_SUBSYS_ID_PERC4_QC 0x0531
+
+#define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F
+#define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A
+
+#define PCI_DEVICE_ID_PERC4E_SI_BIGBEND 0x0013
+#define PCI_SUBSYS_ID_PERC4E_SI_BIGBEND 0x016c
+
+#define PCI_DEVICE_ID_PERC4E_DI_KOBUK 0x0013
+#define PCI_SUBSYS_ID_PERC4E_DI_KOBUK 0x016d
+
+#define PCI_DEVICE_ID_PERC4E_DI_CORVETTE 0x0013
+#define PCI_SUBSYS_ID_PERC4E_DI_CORVETTE 0x016e
+
+#define PCI_DEVICE_ID_PERC4E_DI_EXPEDITION 0x0013
+#define PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION 0x016f
+
+#define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE 0x0013
+#define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE 0x0170
+
+#define PCI_DEVICE_ID_PERC4E_DC_320_2E 0x0408
+#define PCI_SUBSYS_ID_PERC4E_DC_320_2E 0x0002
+
+#define PCI_DEVICE_ID_PERC4E_SC_320_1E 0x0408
+#define PCI_SUBSYS_ID_PERC4E_SC_320_1E 0x0001
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_0 0x1960
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0 0xA520
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_1 0x1960
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1 0x0520
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2 0x1960
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2 0x0518
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_0x 0x0407
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0x 0x0530
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2x 0x0407
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2x 0x0532
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_4x 0x0407
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_4x 0x0531
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_1E 0x0408
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1E 0x0001
+
+#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2E 0x0408
+#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2E 0x0002
+
+#define PCI_DEVICE_ID_MEGARAID_I4_133_RAID 0x1960
+#define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID 0x0522
+
+#define PCI_DEVICE_ID_MEGARAID_SATA_150_4 0x1960
+#define PCI_SUBSYS_ID_MEGARAID_SATA_150_4 0x4523
+
+#define PCI_DEVICE_ID_MEGARAID_SATA_150_6 0x1960
+#define PCI_SUBSYS_ID_MEGARAID_SATA_150_6 0x0523
+
+#define PCI_DEVICE_ID_MEGARAID_SATA_300_4x 0x0409
+#define PCI_SUBSYS_ID_MEGARAID_SATA_300_4x 0x3004
+
+#define PCI_DEVICE_ID_MEGARAID_SATA_300_8x 0x0409
+#define PCI_SUBSYS_ID_MEGARAID_SATA_300_8x 0x3008
+
+#define PCI_DEVICE_ID_INTEL_RAID_SRCU42X 0x0407
+#define PCI_SUBSYS_ID_INTEL_RAID_SRCU42X 0x0532
+
+#define PCI_DEVICE_ID_INTEL_RAID_SRCS16 0x1960
+#define PCI_SUBSYS_ID_INTEL_RAID_SRCS16 0x0523
+
+#define PCI_DEVICE_ID_INTEL_RAID_SRCU42E 0x0408
+#define PCI_SUBSYS_ID_INTEL_RAID_SRCU42E 0x0002
+
+#define PCI_DEVICE_ID_INTEL_RAID_SRCZCRX 0x0407
+#define PCI_SUBSYS_ID_INTEL_RAID_SRCZCRX 0x0530
+
+#define PCI_DEVICE_ID_INTEL_RAID_SRCS28X 0x0409
+#define PCI_SUBSYS_ID_INTEL_RAID_SRCS28X 0x3008
+
+#define PCI_DEVICE_ID_INTEL_RAID_SROMBU42E_ALIEF 0x0408
+#define PCI_SUBSYS_ID_INTEL_RAID_SROMBU42E_ALIEF 0x3431
+
+#define PCI_DEVICE_ID_INTEL_RAID_SROMBU42E_HARWICH 0x0408
+#define PCI_SUBSYS_ID_INTEL_RAID_SROMBU42E_HARWICH 0x3499
+
+#define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x1960
+#define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x0520
+
+#define PCI_DEVICE_ID_FSC_MEGARAID_PCI_EXPRESS_ROMB 0x0408
+#define PCI_SUBSYS_ID_FSC_MEGARAID_PCI_EXPRESS_ROMB 0x1065
+
+#define PCI_DEVICE_ID_MEGARAID_ACER_ROMB_2E 0x0408
+#define PCI_SUBSYS_ID_MEGARAID_ACER_ROMB_2E 0x004D
+
+#define PCI_SUBSYS_ID_PERC3_QC 0x0471
+#define PCI_SUBSYS_ID_PERC3_DC 0x0493
+#define PCI_SUBSYS_ID_PERC3_SC 0x0475
+
+#ifndef PCI_SUBSYS_ID_FSC
+#define PCI_SUBSYS_ID_FSC 0x1734
+#endif
+
+#define MBOX_MAX_SCSI_CMDS 128 // number of cmds reserved for kernel
+#define MBOX_MAX_USER_CMDS 32 // number of cmds for applications
+#define MBOX_DEF_CMD_PER_LUN 64 // default commands per lun
+#define MBOX_DEFAULT_SG_SIZE 26 // default sg size supported by all fw
+#define MBOX_MAX_SG_SIZE 32 // maximum scatter-gather list size
+#define MBOX_MAX_SECTORS 128 // maximum sectors per IO
+#define MBOX_TIMEOUT 30 // timeout value for internal cmds
+#define MBOX_BUSY_WAIT 10 // max usec to wait for busy mailbox
+#define MBOX_RESET_WAIT 180 // wait these many seconds in reset
+#define MBOX_RESET_EXT_WAIT 120 // extended wait reset
+
+/*
+ * maximum transfer that can happen through the firmware commands issued
+ * internnaly from the driver.
+ */
+#define MBOX_IBUF_SIZE 4096
+
+
+/**
+ * mbox_ccb_t - command control block specific to mailbox based controllers
+ * @raw_mbox : raw mailbox pointer
+ * @mbox : mailbox
+ * @mbox64 : extended mailbox
+ * @mbox_dma_h : maibox dma address
+ * @sgl64 : 64-bit scatter-gather list
+ * @sgl32 : 32-bit scatter-gather list
+ * @sgl_dma_h : dma handle for the scatter-gather list
+ * @pthru : passthru structure
+ * @pthru_dma_h : dma handle for the passthru structure
+ * @epthru : extended passthru structure
+ * @epthru_dma_h : dma handle for extended passthru structure
+ * @buf_dma_h : dma handle for buffers w/o sg list
+ *
+ * command control block specific to the mailbox based controllers
+ */
+typedef struct {
+ uint8_t *raw_mbox;
+ mbox_t *mbox;
+ mbox64_t *mbox64;
+ dma_addr_t mbox_dma_h;
+ mbox_sgl64 *sgl64;
+ mbox_sgl32 *sgl32;
+ dma_addr_t sgl_dma_h;
+ mraid_passthru_t *pthru;
+ dma_addr_t pthru_dma_h;
+ mraid_epassthru_t *epthru;
+ dma_addr_t epthru_dma_h;
+ dma_addr_t buf_dma_h;
+} mbox_ccb_t;
+
+
+/**
+ * mraid_device_t - adapter soft state structure for mailbox controllers
+ * @param una_mbox64 : 64-bit mbox - unaligned
+ * @param una_mbox64_dma : mbox dma addr - unaligned
+ * @param mbox : 32-bit mbox - aligned
+ * @param mbox64 : 64-bit mbox - aligned
+ * @param mbox_dma : mbox dma addr - aligned
+ * @param mailbox_lock : exclusion lock for the mailbox
+ * @param baseport : base port of hba memory
+ * @param baseaddr : mapped addr of hba memory
+ * @param mbox_pool : pool of mailboxes
+ * @param mbox_pool_handle : handle for the mailbox pool memory
+ * @param epthru_pool : a pool for extended passthru commands
+ * @param epthru_pool_handle : handle to the pool above
+ * @param sg_pool : pool of scatter-gather lists for this driver
+ * @param sg_pool_handle : handle to the pool above
+ * @param ccb_list : list of our command control blocks
+ * @param uccb_list : list of cmd control blocks for mgmt module
+ * @param umbox64 : array of mailbox for user commands (cmm)
+ * @param pdrv_state : array for state of each physical drive.
+ * @param last_disp : flag used to show device scanning
+ * @param hw_error : set if FW not responding
+ * @param fast_load : If set, skip physical device scanning
+ * @channel_class : channel class, RAID or SCSI
+ *
+ * Initialization structure for mailbox controllers: memory based and IO based
+ * All the fields in this structure are LLD specific and may be discovered at
+ * init() or start() time.
+ *
+ * NOTE: The fields of this structures are placed to minimize cache misses
+ */
+typedef struct {
+ mbox64_t *una_mbox64;
+ dma_addr_t una_mbox64_dma;
+ mbox_t *mbox;
+ mbox64_t *mbox64;
+ dma_addr_t mbox_dma;
+ spinlock_t mailbox_lock;
+ unsigned long baseport;
+ unsigned long baseaddr;
+ struct mraid_pci_blk mbox_pool[MBOX_MAX_SCSI_CMDS];
+ struct dma_pool *mbox_pool_handle;
+ struct mraid_pci_blk epthru_pool[MBOX_MAX_SCSI_CMDS];
+ struct dma_pool *epthru_pool_handle;
+ struct mraid_pci_blk sg_pool[MBOX_MAX_SCSI_CMDS];
+ struct dma_pool *sg_pool_handle;
+ mbox_ccb_t ccb_list[MBOX_MAX_SCSI_CMDS];
+ mbox_ccb_t uccb_list[MBOX_MAX_USER_CMDS];
+ mbox64_t umbox64[MBOX_MAX_USER_CMDS];
+
+ uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];
+ uint32_t last_disp;
+ int hw_error;
+ int fast_load;
+ uint8_t channel_class;
+} mraid_device_t;
+
+// route to raid device from adapter
+#define ADAP2RAIDDEV(adp) ((mraid_device_t *)((adp)->raid_device))
+
+#define MAILBOX_LOCK(rdev) (&(rdev)->mailbox_lock)
+
+// Find out if this channel is a RAID or SCSI
+#define IS_RAID_CH(rdev, ch) (((rdev)->channel_class >> (ch)) & 0x01)
+
+
+#define RDINDOOR(rdev) readl((rdev)->baseaddr + 0x20)
+#define RDOUTDOOR(rdev) readl((rdev)->baseaddr + 0x2C)
+#define WRINDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x20)
+#define WROUTDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x2C)
+
+#endif // _MEGARAID_H_
+
+// vim: set ts=8 sw=8 tw=78:
--- /dev/null
+/*
+ *
+ * Linux MegaRAID device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : megaraid_mm.c
+ * Version : v2.20.2.0 (August 19 2004)
+ *
+ * Common management module
+ */
+
+#include "megaraid_mm.h"
+
+
+// Entry points for char node driver
+static int mraid_mm_open(struct inode *, struct file *);
+static int mraid_mm_ioctl(struct inode *, struct file *, uint, unsigned long);
+
+
+// routines to convert to and from the old the format
+static int mimd_to_kioc(mimd_t __user *, mraid_mmadp_t *, uioc_t *);
+static int kioc_to_mimd(uioc_t *, mimd_t __user *);
+
+
+// Helper functions
+static int handle_drvrcmd(void __user *, uint8_t, int *);
+static int lld_ioctl(mraid_mmadp_t *, uioc_t *);
+static void ioctl_done(uioc_t *);
+static void lld_timedout(unsigned long);
+static void hinfo_to_cinfo(mraid_hba_info_t *, mcontroller_t *);
+static mraid_mmadp_t *mraid_mm_get_adapter(mimd_t __user *, int *);
+static uioc_t *mraid_mm_alloc_kioc(mraid_mmadp_t *);
+static void mraid_mm_dealloc_kioc(mraid_mmadp_t *, uioc_t *);
+static int mraid_mm_attach_buf(mraid_mmadp_t *, uioc_t *, int);
+static int mraid_mm_setup_dma_pools(mraid_mmadp_t *);
+static void mraid_mm_free_adp_resources(mraid_mmadp_t *);
+static void mraid_mm_teardown_dma_pools(mraid_mmadp_t *);
+
+#ifdef CONFIG_COMPAT
+static int mraid_mm_compat_ioctl(unsigned int, unsigned int, unsigned long,
+ struct file *);
+#endif
+
+MODULE_AUTHOR("LSI Logic Corporation");
+MODULE_DESCRIPTION("LSI Logic Management Module");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(LSI_COMMON_MOD_VERSION);
+
+static int dbglevel = CL_ANN;
+module_param_named(dlevel, dbglevel, int, 0);
+MODULE_PARM_DESC(dlevel, "Debug level (default=0)");
+
+EXPORT_SYMBOL(mraid_mm_register_adp);
+EXPORT_SYMBOL(mraid_mm_unregister_adp);
+
+static int majorno;
+static uint32_t drvr_ver = 0x02200100;
+
+static int adapters_count_g;
+static struct list_head adapters_list_g;
+
+wait_queue_head_t wait_q;
+
+static struct file_operations lsi_fops = {
+ .open = mraid_mm_open,
+ .ioctl = mraid_mm_ioctl,
+ .owner = THIS_MODULE,
+};
+
+/**
+ * mraid_mm_open - open routine for char node interface
+ * @inod : unused
+ * @filep : unused
+ *
+ * allow ioctl operations by apps only if they superuser privilege
+ */
+static int
+mraid_mm_open(struct inode *inode, struct file *filep)
+{
+ /*
+ * Only allow superuser to access private ioctl interface
+ */
+ if (!capable(CAP_SYS_ADMIN)) return (-EACCES);
+
+ return 0;
+}
+
+/**
+ * mraid_mm_ioctl - module entry-point for ioctls
+ * @inode : inode (ignored)
+ * @filep : file operations pointer (ignored)
+ * @cmd : ioctl command
+ * @arg : user ioctl packet
+ */
+static int
+mraid_mm_ioctl(struct inode *inode, struct file *filep, unsigned int cmd,
+ unsigned long arg)
+{
+ uioc_t *kioc;
+ char signature[EXT_IOCTL_SIGN_SZ] = {0};
+ int rval;
+ mraid_mmadp_t *adp;
+ uint8_t old_ioctl;
+ int drvrcmd_rval;
+ void __user *argp = (void __user *)arg;
+
+ /*
+ * Make sure only USCSICMD are issued through this interface.
+ * MIMD application would still fire different command.
+ */
+
+ if ((_IOC_TYPE(cmd) != MEGAIOC_MAGIC) && (cmd != USCSICMD)) {
+ return (-EINVAL);
+ }
+
+ /*
+ * Look for signature to see if this is the new or old ioctl format.
+ */
+ if (copy_from_user(signature, argp, EXT_IOCTL_SIGN_SZ)) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid cmm: copy from usr addr failed\n"));
+ return (-EFAULT);
+ }
+
+ if (memcmp(signature, EXT_IOCTL_SIGN, EXT_IOCTL_SIGN_SZ) == 0)
+ old_ioctl = 0;
+ else
+ old_ioctl = 1;
+
+ /*
+ * At present, we don't support the new ioctl packet
+ */
+ if (!old_ioctl )
+ return (-EINVAL);
+
+ /*
+ * If it is a driver ioctl (as opposed to fw ioctls), then we can
+ * handle the command locally. rval > 0 means it is not a drvr cmd
+ */
+ rval = handle_drvrcmd(argp, old_ioctl, &drvrcmd_rval);
+
+ if (rval < 0)
+ return rval;
+ else if (rval == 0)
+ return drvrcmd_rval;
+
+ rval = 0;
+ if ((adp = mraid_mm_get_adapter(argp, &rval)) == NULL) {
+ return rval;
+ }
+
+ /*
+ * The following call will block till a kioc is available
+ */
+ kioc = mraid_mm_alloc_kioc(adp);
+
+ /*
+ * User sent the old mimd_t ioctl packet. Convert it to uioc_t.
+ */
+ if ((rval = mimd_to_kioc(argp, adp, kioc))) {
+ mraid_mm_dealloc_kioc(adp, kioc);
+ return rval;
+ }
+
+ kioc->done = ioctl_done;
+
+ /*
+ * Issue the IOCTL to the low level driver
+ */
+ if ((rval = lld_ioctl(adp, kioc))) {
+ mraid_mm_dealloc_kioc(adp, kioc);
+ return rval;
+ }
+
+ /*
+ * Convert the kioc back to user space
+ */
+ rval = kioc_to_mimd(kioc, argp);
+
+ /*
+ * Return the kioc to free pool
+ */
+ mraid_mm_dealloc_kioc(adp, kioc);
+
+ return rval;
+}
+
+
+/**
+ * mraid_mm_get_adapter - Returns corresponding adapters for the mimd packet
+ * @umimd : User space mimd_t ioctl packet
+ * @adapter : pointer to the adapter (OUT)
+ */
+static mraid_mmadp_t *
+mraid_mm_get_adapter(mimd_t __user *umimd, int *rval)
+{
+ mraid_mmadp_t *adapter;
+ mimd_t mimd;
+ uint32_t adapno;
+ int iterator;
+
+
+ if (copy_from_user(&mimd, umimd, sizeof(mimd_t))) {
+ *rval = -EFAULT;
+ return NULL;
+ }
+
+ adapno = GETADAP(mimd.ui.fcs.adapno);
+
+ if (adapno >= adapters_count_g) {
+ *rval = -ENODEV;
+ return NULL;
+ }
+
+ adapter = NULL;
+ iterator = 0;
+
+ list_for_each_entry(adapter, &adapters_list_g, list) {
+ if (iterator++ == adapno) break;
+ }
+
+ if (!adapter) {
+ *rval = -ENODEV;
+ return NULL;
+ }
+
+ return adapter;
+}
+
+/*
+ * handle_drvrcmd - This routine checks if the opcode is a driver
+ * cmd and if it is, handles it.
+ * @arg : packet sent by the user app
+ * @old_ioctl : mimd if 1; uioc otherwise
+ */
+static int
+handle_drvrcmd(void __user *arg, uint8_t old_ioctl, int *rval)
+{
+ mimd_t __user *umimd;
+ mimd_t kmimd;
+ uint8_t opcode;
+ uint8_t subopcode;
+
+ if (old_ioctl)
+ goto old_packet;
+ else
+ goto new_packet;
+
+new_packet:
+ return (-ENOTSUPP);
+
+old_packet:
+ *rval = 0;
+ umimd = arg;
+
+ if (copy_from_user(&kmimd, umimd, sizeof(mimd_t)))
+ return (-EFAULT);
+
+ opcode = kmimd.ui.fcs.opcode;
+ subopcode = kmimd.ui.fcs.subopcode;
+
+ /*
+ * If the opcode is 0x82 and the subopcode is either GET_DRVRVER or
+ * GET_NUMADP, then we can handle. Otherwise we should return 1 to
+ * indicate that we cannot handle this.
+ */
+ if (opcode != 0x82)
+ return 1;
+
+ switch (subopcode) {
+
+ case MEGAIOC_QDRVRVER:
+
+ if (copy_to_user(kmimd.data, &drvr_ver, sizeof(uint32_t)))
+ return (-EFAULT);
+
+ return 0;
+
+ case MEGAIOC_QNADAP:
+
+ *rval = adapters_count_g;
+
+ if (copy_to_user(kmimd.data, &adapters_count_g,
+ sizeof(uint32_t)))
+ return (-EFAULT);
+
+ return 0;
+
+ default:
+ /* cannot handle */
+ return 1;
+ }
+
+ return 0;
+}
+
+
+/**
+ * mimd_to_kioc - Converter from old to new ioctl format
+ *
+ * @umimd : user space old MIMD IOCTL
+ * @kioc : kernel space new format IOCTL
+ *
+ * Routine to convert MIMD interface IOCTL to new interface IOCTL packet. The
+ * new packet is in kernel space so that driver can perform operations on it
+ * freely.
+ */
+
+static int
+mimd_to_kioc(mimd_t __user *umimd, mraid_mmadp_t *adp, uioc_t *kioc)
+{
+ mbox64_t *mbox64;
+ mbox_t *mbox;
+ mraid_passthru_t *pthru32;
+ uint32_t adapno;
+ uint8_t opcode;
+ uint8_t subopcode;
+ mimd_t mimd;
+
+ if (copy_from_user(&mimd, umimd, sizeof(mimd_t)))
+ return (-EFAULT);
+
+ /*
+ * Applications are not allowed to send extd pthru
+ */
+ if ((mimd.mbox[0] == MBOXCMD_PASSTHRU64) ||
+ (mimd.mbox[0] == MBOXCMD_EXTPTHRU))
+ return (-EINVAL);
+
+ opcode = mimd.ui.fcs.opcode;
+ subopcode = mimd.ui.fcs.subopcode;
+ adapno = GETADAP(mimd.ui.fcs.adapno);
+
+ if (adapno >= adapters_count_g)
+ return (-ENODEV);
+
+ kioc->adapno = adapno;
+ kioc->mb_type = MBOX_LEGACY;
+ kioc->app_type = APPTYPE_MIMD;
+
+ switch (opcode) {
+
+ case 0x82:
+
+ if (subopcode == MEGAIOC_QADAPINFO) {
+
+ kioc->opcode = GET_ADAP_INFO;
+ kioc->data_dir = UIOC_RD;
+ kioc->xferlen = sizeof(mraid_hba_info_t);
+
+ if (mraid_mm_attach_buf(adp, kioc, kioc->xferlen))
+ return (-ENOMEM);
+ }
+ else {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid cmm: Invalid subop\n"));
+ return (-EINVAL);
+ }
+
+ break;
+
+ case 0x81:
+
+ kioc->opcode = MBOX_CMD;
+ kioc->xferlen = mimd.ui.fcs.length;
+ kioc->user_data_len = kioc->xferlen;
+ kioc->user_data = mimd.ui.fcs.buffer;
+
+ if (mraid_mm_attach_buf(adp, kioc, kioc->xferlen))
+ return (-ENOMEM);
+
+ if (mimd.outlen) kioc->data_dir = UIOC_RD;
+ if (mimd.inlen) kioc->data_dir |= UIOC_WR;
+
+ break;
+
+ case 0x80:
+
+ kioc->opcode = MBOX_CMD;
+ kioc->xferlen = (mimd.outlen > mimd.inlen) ?
+ mimd.outlen : mimd.inlen;
+ kioc->user_data_len = kioc->xferlen;
+ kioc->user_data = mimd.data;
+
+ if (mraid_mm_attach_buf(adp, kioc, kioc->xferlen))
+ return (-ENOMEM);
+
+ if (mimd.outlen) kioc->data_dir = UIOC_RD;
+ if (mimd.inlen) kioc->data_dir |= UIOC_WR;
+
+ break;
+
+ default:
+ return (-EINVAL);
+ }
+
+ /*
+ * If driver command, nothing else to do
+ */
+ if (opcode == 0x82)
+ return 0;
+
+ /*
+ * This is a mailbox cmd; copy the mailbox from mimd
+ */
+ mbox64 = (mbox64_t *)((unsigned long)kioc->cmdbuf);
+ mbox = &mbox64->mbox32;
+ memcpy(mbox, mimd.mbox, 14);
+
+ if (mbox->cmd != MBOXCMD_PASSTHRU) { // regular DCMD
+
+ mbox->xferaddr = (uint32_t)kioc->buf_paddr;
+
+ if (kioc->data_dir & UIOC_WR) {
+ if (copy_from_user(kioc->buf_vaddr, kioc->user_data,
+ kioc->xferlen)) {
+ return (-EFAULT);
+ }
+ }
+
+ return 0;
+ }
+
+ /*
+ * This is a regular 32-bit pthru cmd; mbox points to pthru struct.
+ * Just like in above case, the beginning for memblk is treated as
+ * a mailbox. The passthru will begin at next 1K boundary. And the
+ * data will start 1K after that.
+ */
+ pthru32 = kioc->pthru32;
+ kioc->user_pthru = &umimd->pthru;
+ mbox->xferaddr = (uint32_t)kioc->pthru32_h;
+
+ if (copy_from_user(pthru32, kioc->user_pthru,
+ sizeof(mraid_passthru_t))) {
+ return (-EFAULT);
+ }
+
+ pthru32->dataxferaddr = kioc->buf_paddr;
+ if (kioc->data_dir & UIOC_WR) {
+ if (copy_from_user(kioc->buf_vaddr, kioc->user_data,
+ pthru32->dataxferlen)) {
+ return (-EFAULT);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * mraid_mm_attch_buf - Attach a free dma buffer for required size
+ *
+ * @adp : Adapter softstate
+ * @kioc : kioc that the buffer needs to be attached to
+ * @xferlen : required length for buffer
+ *
+ * First we search for a pool with smallest buffer that is >= @xferlen. If
+ * that pool has no free buffer, we will try for the next bigger size. If none
+ * is available, we will try to allocate the smallest buffer that is >=
+ * @xferlen and attach it the pool.
+ */
+static int
+mraid_mm_attach_buf(mraid_mmadp_t *adp, uioc_t *kioc, int xferlen)
+{
+ mm_dmapool_t *pool;
+ int right_pool = -1;
+ unsigned long flags;
+ int i;
+
+ kioc->pool_index = -1;
+ kioc->buf_vaddr = NULL;
+ kioc->buf_paddr = 0;
+ kioc->free_buf = 0;
+
+ /*
+ * We need xferlen amount of memory. See if we can get it from our
+ * dma pools. If we don't get exact size, we will try bigger buffer
+ */
+
+ for (i = 0; i < MAX_DMA_POOLS; i++) {
+
+ pool = &adp->dma_pool_list[i];
+
+ if (xferlen > pool->buf_size)
+ continue;
+
+ if (right_pool == -1)
+ right_pool = i;
+
+ spin_lock_irqsave(&pool->lock, flags);
+
+ if (!pool->in_use) {
+
+ pool->in_use = 1;
+ kioc->pool_index = i;
+ kioc->buf_vaddr = pool->vaddr;
+ kioc->buf_paddr = pool->paddr;
+
+ spin_unlock_irqrestore(&pool->lock, flags);
+ return 0;
+ }
+ else {
+ spin_unlock_irqrestore(&pool->lock, flags);
+ continue;
+ }
+ }
+
+ /*
+ * If xferlen doesn't match any of our pools, return error
+ */
+ if (right_pool == -1)
+ return -EINVAL;
+
+ /*
+ * We did not get any buffer from the preallocated pool. Let us try
+ * to allocate one new buffer. NOTE: This is a blocking call.
+ */
+ pool = &adp->dma_pool_list[right_pool];
+
+ spin_lock_irqsave(&pool->lock, flags);
+
+ kioc->pool_index = right_pool;
+ kioc->free_buf = 1;
+ kioc->buf_vaddr = pci_pool_alloc(pool->handle, GFP_KERNEL,
+ &kioc->buf_paddr);
+ spin_unlock_irqrestore(&pool->lock, flags);
+
+ if (!kioc->buf_vaddr)
+ return -ENOMEM;
+
+ return 0;
+}
+
+/**
+ * mraid_mm_alloc_kioc - Returns a uioc_t from free list
+ * @adp : Adapter softstate for this module
+ *
+ * The kioc_semaphore is initialized with number of kioc nodes in the
+ * free kioc pool. If the kioc pool is empty, this function blocks till
+ * a kioc becomes free.
+ */
+static uioc_t *
+mraid_mm_alloc_kioc(mraid_mmadp_t *adp)
+{
+ uioc_t *kioc;
+ struct list_head* head;
+ unsigned long flags;
+
+ down(&adp->kioc_semaphore);
+
+ spin_lock_irqsave(&adp->kioc_pool_lock, flags);
+
+ head = &adp->kioc_pool;
+
+ if (list_empty(head)) {
+ up(&adp->kioc_semaphore);
+ spin_unlock_irqrestore(&adp->kioc_pool_lock, flags);
+
+ con_log(CL_ANN, ("megaraid cmm: kioc list empty!\n"));
+ return NULL;
+ }
+
+ kioc = list_entry(head->next, uioc_t, list);
+ list_del_init(&kioc->list);
+
+ spin_unlock_irqrestore(&adp->kioc_pool_lock, flags);
+
+ memset((caddr_t)(unsigned long)kioc->cmdbuf, 0, sizeof(mbox64_t));
+ memset((caddr_t) kioc->pthru32, 0, sizeof(mraid_passthru_t));
+
+ kioc->buf_vaddr = NULL;
+ kioc->buf_paddr = 0;
+ kioc->pool_index =-1;
+ kioc->free_buf = 0;
+ kioc->user_data = NULL;
+ kioc->user_data_len = 0;
+ kioc->user_pthru = NULL;
+
+ return kioc;
+}
+
+/**
+ * mraid_mm_dealloc_kioc - Return kioc to free pool
+ *
+ * @adp : Adapter softstate
+ * @kioc : uioc_t node to be returned to free pool
+ */
+static void
+mraid_mm_dealloc_kioc(mraid_mmadp_t *adp, uioc_t *kioc)
+{
+ mm_dmapool_t *pool;
+ unsigned long flags;
+
+ pool = &adp->dma_pool_list[kioc->pool_index];
+
+ /* This routine may be called in non-isr context also */
+ spin_lock_irqsave(&pool->lock, flags);
+
+ /*
+ * While attaching the dma buffer, if we didn't get the required
+ * buffer from the pool, we would have allocated it at the run time
+ * and set the free_buf flag. We must free that buffer. Otherwise,
+ * just mark that the buffer is not in use
+ */
+ if (kioc->free_buf == 1)
+ pci_pool_free(pool->handle, kioc->buf_vaddr, kioc->buf_paddr);
+ else
+ pool->in_use = 0;
+
+ spin_unlock_irqrestore(&pool->lock, flags);
+
+ /* Return the kioc to the free pool */
+ spin_lock_irqsave(&adp->kioc_pool_lock, flags);
+ list_add(&kioc->list, &adp->kioc_pool);
+ spin_unlock_irqrestore(&adp->kioc_pool_lock, flags);
+
+ /* increment the free kioc count */
+ up(&adp->kioc_semaphore);
+
+ return;
+}
+
+/**
+ * lld_ioctl - Routine to issue ioctl to low level drvr
+ *
+ * @adp : The adapter handle
+ * @kioc : The ioctl packet with kernel addresses
+ */
+static int
+lld_ioctl(mraid_mmadp_t *adp, uioc_t *kioc)
+{
+ int rval;
+ struct timer_list timer;
+ struct timer_list *tp = NULL;
+
+ kioc->status = -ENODATA;
+ rval = adp->issue_uioc(adp->drvr_data, kioc, IOCTL_ISSUE);
+
+ if (rval) return rval;
+
+ /*
+ * Start the timer
+ */
+ if (adp->timeout > 0) {
+ tp = &timer;
+ init_timer(tp);
+
+ tp->function = lld_timedout;
+ tp->data = (unsigned long)kioc;
+ tp->expires = jiffies + adp->timeout * HZ;
+
+ add_timer(tp);
+ }
+
+ /*
+ * Wait till the low level driver completes the ioctl. After this
+ * call, the ioctl either completed successfully or timedout.
+ */
+ wait_event(wait_q, (kioc->status != -ENODATA));
+ if (tp) {
+ del_timer_sync(tp);
+ }
+
+ return kioc->status;
+}
+
+
+/**
+ * ioctl_done - callback from the low level driver
+ *
+ * @kioc : completed ioctl packet
+ */
+static void
+ioctl_done(uioc_t *kioc)
+{
+ /*
+ * When the kioc returns from driver, make sure it still doesn't
+ * have ENODATA in status. Otherwise, driver will hang on wait_event
+ * forever
+ */
+ if (kioc->status == -ENODATA) {
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid cmm: lld didn't change status!\n"));
+
+ kioc->status = -EINVAL;
+ }
+
+ wake_up(&wait_q);
+}
+
+
+/*
+ * lld_timedout : callback from the expired timer
+ *
+ * @ptr : ioctl packet that timed out
+ */
+static void
+lld_timedout(unsigned long ptr)
+{
+ uioc_t *kioc = (uioc_t *)ptr;
+
+ kioc->status = -ETIME;
+
+ con_log(CL_ANN, (KERN_WARNING "megaraid cmm: ioctl timed out\n"));
+
+ wake_up(&wait_q);
+}
+
+
+/**
+ * kioc_to_mimd : Converter from new back to old format
+ *
+ * @kioc : Kernel space IOCTL packet (successfully issued)
+ * @mimd : User space MIMD packet
+ */
+static int
+kioc_to_mimd(uioc_t *kioc, mimd_t __user *mimd)
+{
+ mimd_t kmimd;
+ uint8_t opcode;
+ uint8_t subopcode;
+
+ mbox64_t *mbox64;
+ mraid_passthru_t __user *upthru32;
+ mraid_passthru_t *kpthru32;
+ mcontroller_t cinfo;
+ mraid_hba_info_t *hinfo;
+
+
+ if (copy_from_user(&kmimd, mimd, sizeof(mimd_t)))
+ return (-EFAULT);
+
+ opcode = kmimd.ui.fcs.opcode;
+ subopcode = kmimd.ui.fcs.subopcode;
+
+ if (opcode == 0x82) {
+ switch (subopcode) {
+
+ case MEGAIOC_QADAPINFO:
+
+ hinfo = (mraid_hba_info_t *)(unsigned long)
+ kioc->buf_vaddr;
+
+ hinfo_to_cinfo(hinfo, &cinfo);
+
+ if (copy_to_user(kmimd.data, &cinfo, sizeof(cinfo)))
+ return (-EFAULT);
+
+ return 0;
+
+ default:
+ return (-EINVAL);
+ }
+
+ return 0;
+ }
+
+ mbox64 = (mbox64_t *)(unsigned long)kioc->cmdbuf;
+
+ if (kioc->user_pthru) {
+
+ upthru32 = kioc->user_pthru;
+ kpthru32 = kioc->pthru32;
+
+ if (copy_to_user(&upthru32->scsistatus,
+ &kpthru32->scsistatus,
+ sizeof(uint8_t))) {
+ return (-EFAULT);
+ }
+ }
+
+ if (kioc->user_data) {
+ if (copy_to_user(kioc->user_data, kioc->buf_vaddr,
+ kioc->user_data_len)) {
+ return (-EFAULT);
+ }
+ }
+
+ if (copy_to_user(&mimd->mbox[17],
+ &mbox64->mbox32.status, sizeof(uint8_t))) {
+ return (-EFAULT);
+ }
+
+ return 0;
+}
+
+
+/**
+ * hinfo_to_cinfo - Convert new format hba info into old format
+ *
+ * @hinfo : New format, more comprehensive adapter info
+ * @cinfo : Old format adapter info to support mimd_t apps
+ */
+static void
+hinfo_to_cinfo(mraid_hba_info_t *hinfo, mcontroller_t *cinfo)
+{
+ if (!hinfo || !cinfo)
+ return;
+
+ cinfo->base = hinfo->baseport;
+ cinfo->irq = hinfo->irq;
+ cinfo->numldrv = hinfo->num_ldrv;
+ cinfo->pcibus = hinfo->pci_bus;
+ cinfo->pcidev = hinfo->pci_slot;
+ cinfo->pcifun = PCI_FUNC(hinfo->pci_dev_fn);
+ cinfo->pciid = hinfo->pci_device_id;
+ cinfo->pcivendor = hinfo->pci_vendor_id;
+ cinfo->pcislot = hinfo->pci_slot;
+ cinfo->uid = hinfo->unique_id;
+}
+
+
+/*
+ * mraid_mm_register_adp - Registration routine for low level drvrs
+ *
+ * @adp : Adapter objejct
+ */
+int
+mraid_mm_register_adp(mraid_mmadp_t *lld_adp)
+{
+ mraid_mmadp_t *adapter;
+ mbox64_t *mbox_list;
+ uioc_t *kioc;
+ uint32_t rval;
+ int i;
+
+
+ if (lld_adp->drvr_type != DRVRTYPE_MBOX)
+ return (-EINVAL);
+
+ adapter = kmalloc(sizeof(mraid_mmadp_t), GFP_KERNEL);
+
+ if (!adapter) {
+ rval = -ENOMEM;
+ goto memalloc_error;
+ }
+
+ memset(adapter, 0, sizeof(mraid_mmadp_t));
+
+ adapter->unique_id = lld_adp->unique_id;
+ adapter->drvr_type = lld_adp->drvr_type;
+ adapter->drvr_data = lld_adp->drvr_data;
+ adapter->pdev = lld_adp->pdev;
+ adapter->issue_uioc = lld_adp->issue_uioc;
+ adapter->timeout = lld_adp->timeout;
+ adapter->max_kioc = lld_adp->max_kioc;
+
+ /*
+ * Allocate single blocks of memory for all required kiocs,
+ * mailboxes and passthru structures.
+ */
+ adapter->kioc_list = kmalloc(sizeof(uioc_t) * lld_adp->max_kioc,
+ GFP_KERNEL);
+ adapter->mbox_list = kmalloc(sizeof(mbox64_t) * lld_adp->max_kioc,
+ GFP_KERNEL);
+ adapter->pthru_dma_pool = pci_pool_create("megaraid mm pthru pool",
+ adapter->pdev,
+ sizeof(mraid_passthru_t),
+ 16, 0);
+
+ if (!adapter->kioc_list || !adapter->mbox_list ||
+ !adapter->pthru_dma_pool) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid cmm: out of memory, %s %d\n", __FUNCTION__,
+ __LINE__));
+
+ rval = (-ENOMEM);
+
+ goto memalloc_error;
+ }
+
+ /*
+ * Slice kioc_list and make a kioc_pool with the individiual kiocs
+ */
+ INIT_LIST_HEAD(&adapter->kioc_pool);
+ spin_lock_init(&adapter->kioc_pool_lock);
+ sema_init(&adapter->kioc_semaphore, lld_adp->max_kioc);
+
+ mbox_list = (mbox64_t *)adapter->mbox_list;
+
+ for (i = 0; i < lld_adp->max_kioc; i++) {
+
+ kioc = adapter->kioc_list + i;
+ kioc->cmdbuf = (uint64_t)(unsigned long)(mbox_list + i);
+ kioc->pthru32 = pci_pool_alloc(adapter->pthru_dma_pool,
+ GFP_KERNEL, &kioc->pthru32_h);
+
+ if (!kioc->pthru32) {
+
+ con_log(CL_ANN, (KERN_WARNING
+ "megaraid cmm: out of memory, %s %d\n",
+ __FUNCTION__, __LINE__));
+
+ rval = (-ENOMEM);
+
+ goto pthru_dma_pool_error;
+ }
+
+ list_add_tail(&kioc->list, &adapter->kioc_pool);
+ }
+
+ // Setup the dma pools for data buffers
+ if ((rval = mraid_mm_setup_dma_pools(adapter)) != 0) {
+ goto dma_pool_error;
+ }
+
+ list_add_tail(&adapter->list, &adapters_list_g);
+
+ adapters_count_g++;
+
+ return 0;
+
+dma_pool_error:
+ /* Do nothing */
+
+pthru_dma_pool_error:
+
+ for (i = 0; i < lld_adp->max_kioc; i++) {
+ kioc = adapter->kioc_list + i;
+ if (kioc->pthru32) {
+ pci_pool_free(adapter->pthru_dma_pool, kioc->pthru32,
+ kioc->pthru32_h);
+ }
+ }
+
+memalloc_error:
+
+ if (adapter->kioc_list)
+ kfree(adapter->kioc_list);
+
+ if (adapter->mbox_list)
+ kfree(adapter->mbox_list);
+
+ if (adapter->pthru_dma_pool)
+ pci_pool_destroy(adapter->pthru_dma_pool);
+
+ if (adapter)
+ kfree(adapter);
+
+ return rval;
+}
+
+/**
+ * mraid_mm_setup_dma_pools - Set up dma buffer pools per adapter
+ *
+ * @adp : Adapter softstate
+ *
+ * We maintain a pool of dma buffers per each adapter. Each pool has one
+ * buffer. E.g, we may have 5 dma pools - one each for 4k, 8k ... 64k buffers.
+ * We have just one 4k buffer in 4k pool, one 8k buffer in 8k pool etc. We
+ * dont' want to waste too much memory by allocating more buffers per each
+ * pool.
+ */
+static int
+mraid_mm_setup_dma_pools(mraid_mmadp_t *adp)
+{
+ mm_dmapool_t *pool;
+ int bufsize;
+ int i;
+
+ /*
+ * Create MAX_DMA_POOLS number of pools
+ */
+ bufsize = MRAID_MM_INIT_BUFF_SIZE;
+
+ for (i = 0; i < MAX_DMA_POOLS; i++){
+
+ pool = &adp->dma_pool_list[i];
+
+ pool->buf_size = bufsize;
+ spin_lock_init(&pool->lock);
+
+ pool->handle = pci_pool_create("megaraid mm data buffer",
+ adp->pdev, bufsize, 16, 0);
+
+ if (!pool->handle) {
+ goto dma_pool_setup_error;
+ }
+
+ pool->vaddr = pci_pool_alloc(pool->handle, GFP_KERNEL,
+ &pool->paddr);
+
+ if (!pool->vaddr)
+ goto dma_pool_setup_error;
+
+ bufsize = bufsize * 2;
+ }
+
+ return 0;
+
+dma_pool_setup_error:
+
+ mraid_mm_teardown_dma_pools(adp);
+ return (-ENOMEM);
+}
+
+
+/*
+ * mraid_mm_unregister_adp - Unregister routine for low level drivers
+ * Assume no outstanding ioctls to llds.
+ *
+ * @unique_id : UID of the adpater
+ */
+int
+mraid_mm_unregister_adp(uint32_t unique_id)
+{
+ mraid_mmadp_t *adapter;
+ mraid_mmadp_t *tmp;
+
+ list_for_each_entry_safe(adapter, tmp, &adapters_list_g, list) {
+
+
+ if (adapter->unique_id == unique_id) {
+
+ adapters_count_g--;
+
+ list_del_init(&adapter->list);
+
+ mraid_mm_free_adp_resources(adapter);
+
+ kfree(adapter);
+
+ con_log(CL_ANN, (
+ "megaraid cmm: Unregistered one adapter:%#x\n",
+ unique_id));
+
+ return 0;
+ }
+ }
+
+ return (-ENODEV);
+}
+
+/**
+ * mraid_mm_free_adp_resources - Free adapter softstate
+ *
+ * @adp : Adapter softstate
+ */
+static void
+mraid_mm_free_adp_resources(mraid_mmadp_t *adp)
+{
+ uioc_t *kioc;
+ int i;
+
+ mraid_mm_teardown_dma_pools(adp);
+
+ for (i = 0; i < adp->max_kioc; i++) {
+
+ kioc = adp->kioc_list + i;
+
+ pci_pool_free(adp->pthru_dma_pool, kioc->pthru32,
+ kioc->pthru32_h);
+ }
+
+ kfree(adp->kioc_list);
+
+ kfree(adp->mbox_list);
+
+ pci_pool_destroy(adp->pthru_dma_pool);
+
+
+ return;
+}
+
+
+/**
+ * mraid_mm_teardown_dma_pools - Free all per adapter dma buffers
+ *
+ * @adp : Adapter softstate
+ */
+static void
+mraid_mm_teardown_dma_pools(mraid_mmadp_t *adp)
+{
+ int i;
+ mm_dmapool_t *pool;
+
+ for (i = 0; i < MAX_DMA_POOLS; i++) {
+
+ pool = &adp->dma_pool_list[i];
+
+ if (pool->handle) {
+
+ if (pool->vaddr)
+ pci_pool_free(pool->handle, pool->vaddr,
+ pool->paddr);
+
+ pci_pool_destroy(pool->handle);
+ pool->handle = NULL;
+ }
+ }
+
+ return;
+}
+
+/**
+ * mraid_mm_init : Module entry point
+ */
+static int __init
+mraid_mm_init(void)
+{
+ // Announce the driver version
+ con_log(CL_ANN, (KERN_INFO "megaraid cmm: %s %s\n",
+ LSI_COMMON_MOD_VERSION, LSI_COMMON_MOD_EXT_VERSION));
+
+ majorno = register_chrdev(0, "megadev", &lsi_fops);
+
+ if (majorno < 0) {
+ con_log(CL_ANN, ("megaraid cmm: cannot get major\n"));
+ return majorno;
+ }
+
+ init_waitqueue_head(&wait_q);
+
+ INIT_LIST_HEAD(&adapters_list_g);
+
+#ifdef CONFIG_COMPAT
+ register_ioctl32_conversion(MEGAIOCCMD, mraid_mm_compat_ioctl);
+#endif
+
+ return 0;
+}
+
+
+/**
+ * mraid_mm_compat_ioctl : 32bit to 64bit ioctl conversion routine
+ */
+#ifdef CONFIG_COMPAT
+static int
+mraid_mm_compat_ioctl(unsigned int fd, unsigned int cmd,
+ unsigned long arg, struct file *filep)
+{
+ struct inode *inode = filep->f_dentry->d_inode;
+
+ return mraid_mm_ioctl(inode, filep, cmd, arg);
+}
+#endif
+
+/**
+ * mraid_mm_exit : Module exit point
+ */
+static void __exit
+mraid_mm_exit(void)
+{
+ con_log(CL_DLEVEL1 , ("exiting common mod\n"));
+
+ unregister_chrdev(majorno, "megadev");
+ unregister_ioctl32_conversion(MEGAIOCCMD);
+}
+
+module_init(mraid_mm_init);
+module_exit(mraid_mm_exit);
+
+/* vi: set ts=8 sw=8 tw=78: */
--- /dev/null
+/*
+ *
+ * Linux MegaRAID device driver
+ *
+ * Copyright (c) 2003-2004 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : megaraid_mm.h
+ */
+
+#ifndef MEGARAID_MM_H
+#define MEGARAID_MM_H
+
+#include <linux/spinlock.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/list.h>
+#include <linux/ioctl32.h>
+
+#include "mbox_defs.h"
+#include "megaraid_ioctl.h"
+
+
+#define LSI_COMMON_MOD_VERSION "2.20.2.0"
+#define LSI_COMMON_MOD_EXT_VERSION \
+ "(Release Date: Thu Aug 19 09:58:33 EDT 2004)"
+
+
+#define LSI_DBGLVL dbglevel
+
+// The smallest dma pool
+#define MRAID_MM_INIT_BUFF_SIZE 4096
+
+/**
+ * mimd_t : Old style ioctl packet structure (deprecated)
+ *
+ * @inlen :
+ * @outlen :
+ * @fca :
+ * @opcode :
+ * @subopcode :
+ * @adapno :
+ * @buffer :
+ * @pad :
+ * @length :
+ * @mbox :
+ * @pthru :
+ * @data :
+ * @pad :
+ *
+ * Note : This structure is DEPRECATED. New applications must use
+ * : uioc_t structure instead. All new hba drivers use the new
+ * : format. If we get this mimd packet, we will convert it into
+ * : new uioc_t format and send it to the hba drivers.
+ */
+
+typedef struct mimd {
+
+ uint32_t inlen;
+ uint32_t outlen;
+
+ union {
+ uint8_t fca[16];
+ struct {
+ uint8_t opcode;
+ uint8_t subopcode;
+ uint16_t adapno;
+#if BITS_PER_LONG == 32
+ uint8_t __user *buffer;
+ uint8_t pad[4];
+#endif
+#if BITS_PER_LONG == 64
+ uint8_t __user *buffer;
+#endif
+ uint32_t length;
+ } __attribute__ ((packed)) fcs;
+ } __attribute__ ((packed)) ui;
+
+ uint8_t mbox[18]; /* 16 bytes + 2 status bytes */
+ mraid_passthru_t pthru;
+
+#if BITS_PER_LONG == 32
+ char __user *data; /* buffer <= 4096 for 0x80 commands */
+ char pad[4];
+#endif
+#if BITS_PER_LONG == 64
+ char __user *data;
+#endif
+
+} __attribute__ ((packed))mimd_t;
+
+#endif // MEGARAID_MM_H
+
+// vi: set ts=8 sw=8 tw=78:
--- /dev/null
+/*
+ * icom.c
+ *
+ * Copyright (C) 2001 IBM Corporation. All rights reserved.
+ *
+ * Serial device driver.
+ *
+ * Based on code from serial.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#define SERIAL_DO_RESTART
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/termios.h>
+#include <linux/fs.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_reg.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/fcntl.h>
+#include <linux/ptrace.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/vmalloc.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/spinlock.h>
+#include <linux/kobject.h>
+#include <linux/firmware.h>
+
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/bitops.h>
+
+#include "icom.h"
+
+/*#define ICOM_TRACE enable port trace capabilities */
+
+#define ICOM_DRIVER_NAME "icom"
+#define ICOM_VERSION_STR "1.3.1"
+#define NR_PORTS 128
+#define ICOM_PORT ((struct icom_port *)port)
+#define to_icom_adapter(d) container_of(d, struct icom_adapter, kobj)
+
+static const struct pci_device_id icom_pci_table[] = {
+ {
+ .vendor = PCI_VENDOR_ID_IBM,
+ .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .driver_data = ADAPTER_V1,
+ },
+ {
+ .vendor = PCI_VENDOR_ID_IBM,
+ .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
+ .subvendor = PCI_VENDOR_ID_IBM,
+ .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX,
+ .driver_data = ADAPTER_V2,
+ },
+ {
+ .vendor = PCI_VENDOR_ID_IBM,
+ .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
+ .subvendor = PCI_VENDOR_ID_IBM,
+ .subdevice = PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM,
+ .driver_data = ADAPTER_V2,
+ },
+ {
+ .vendor = PCI_VENDOR_ID_IBM,
+ .device = PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2,
+ .subvendor = PCI_VENDOR_ID_IBM,
+ .subdevice = PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL,
+ .driver_data = ADAPTER_V2,
+ },
+ {}
+};
+
+struct lookup_proc_table start_proc[4] = {
+ {0, ICOM_CONTROL_START_A},
+ {0, ICOM_CONTROL_START_B},
+ {0, ICOM_CONTROL_START_C},
+ {0, ICOM_CONTROL_START_D}
+};
+
+
+struct lookup_proc_table stop_proc[4] = {
+ {0, ICOM_CONTROL_STOP_A},
+ {0, ICOM_CONTROL_STOP_B},
+ {0, ICOM_CONTROL_STOP_C},
+ {0, ICOM_CONTROL_STOP_D}
+};
+
+struct lookup_int_table int_mask_tbl[4] = {
+ {0, ICOM_INT_MASK_PRC_A},
+ {0, ICOM_INT_MASK_PRC_B},
+ {0, ICOM_INT_MASK_PRC_C},
+ {0, ICOM_INT_MASK_PRC_D},
+};
+
+
+MODULE_DEVICE_TABLE(pci, icom_pci_table);
+
+static LIST_HEAD(icom_adapter_head);
+
+/* spinlock for adapter initialization and changing adapter operations */
+static spinlock_t icom_lock;
+
+#ifdef ICOM_TRACE
+static inline void trace(struct icom_port *, char *, unsigned long) {};
+#else
+static inline void trace(struct icom_port *icom_port, char *trace_pt, unsigned long trace_data) {};
+#endif
+
+static void msleep(unsigned long msecs)
+{
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(MSECS_TO_JIFFIES(msecs));
+}
+
+static void free_port_memory(struct icom_port *icom_port)
+{
+ struct pci_dev *dev = icom_port->adapter->pci_dev;
+
+ trace(icom_port, "RET_PORT_MEM", 0);
+ if (icom_port->recv_buf) {
+ pci_free_consistent(dev, 4096, icom_port->recv_buf,
+ icom_port->recv_buf_pci);
+ icom_port->recv_buf = 0;
+ }
+ if (icom_port->xmit_buf) {
+ pci_free_consistent(dev, 4096, icom_port->xmit_buf,
+ icom_port->xmit_buf_pci);
+ icom_port->xmit_buf = 0;
+ }
+ if (icom_port->statStg) {
+ pci_free_consistent(dev, 4096, icom_port->statStg,
+ icom_port->statStg_pci);
+ icom_port->statStg = 0;
+ }
+
+ if (icom_port->xmitRestart) {
+ pci_free_consistent(dev, 4096, icom_port->xmitRestart,
+ icom_port->xmitRestart_pci);
+ icom_port->xmitRestart = 0;
+ }
+}
+
+static int __init get_port_memory(struct icom_port *icom_port)
+{
+ int index;
+ unsigned long stgAddr;
+ unsigned long startStgAddr;
+ unsigned long offset;
+ struct pci_dev *dev = icom_port->adapter->pci_dev;
+
+ icom_port->xmit_buf =
+ pci_alloc_consistent(dev, 4096, &icom_port->xmit_buf_pci);
+ if (!icom_port->xmit_buf) {
+ dev_err(&dev->dev, "Can not allocate Transmit buffer\n");
+ return -ENOMEM;
+ }
+
+ trace(icom_port, "GET_PORT_MEM",
+ (unsigned long) icom_port->xmit_buf);
+
+ icom_port->recv_buf =
+ pci_alloc_consistent(dev, 4096, &icom_port->recv_buf_pci);
+ if (!icom_port->recv_buf) {
+ dev_err(&dev->dev, "Can not allocate Receive buffer\n");
+ free_port_memory(icom_port);
+ return -ENOMEM;
+ }
+ trace(icom_port, "GET_PORT_MEM",
+ (unsigned long) icom_port->recv_buf);
+
+ icom_port->statStg =
+ pci_alloc_consistent(dev, 4096, &icom_port->statStg_pci);
+ if (!icom_port->statStg) {
+ dev_err(&dev->dev, "Can not allocate Status buffer\n");
+ free_port_memory(icom_port);
+ return -ENOMEM;
+ }
+ trace(icom_port, "GET_PORT_MEM",
+ (unsigned long) icom_port->statStg);
+
+ icom_port->xmitRestart =
+ pci_alloc_consistent(dev, 4096, &icom_port->xmitRestart_pci);
+ if (!icom_port->xmitRestart) {
+ dev_err(&dev->dev,
+ "Can not allocate xmit Restart buffer\n");
+ free_port_memory(icom_port);
+ return -ENOMEM;
+ }
+
+ memset(icom_port->statStg, 0, 4096);
+
+ /* FODs: Frame Out Descriptor Queue, this is a FIFO queue that
+ indicates that frames are to be transmitted
+ */
+
+ stgAddr = (unsigned long) icom_port->statStg;
+ for (index = 0; index < NUM_XBUFFS; index++) {
+ trace(icom_port, "FOD_ADDR", stgAddr);
+ stgAddr = stgAddr + sizeof(icom_port->statStg->xmit[0]);
+ if (index < (NUM_XBUFFS - 1)) {
+ memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
+ icom_port->statStg->xmit[index].leLengthASD =
+ (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
+ trace(icom_port, "FOD_ADDR", stgAddr);
+ trace(icom_port, "FOD_XBUFF",
+ (unsigned long) icom_port->xmit_buf);
+ icom_port->statStg->xmit[index].leBuffer =
+ cpu_to_le32(icom_port->xmit_buf_pci);
+ } else if (index == (NUM_XBUFFS - 1)) {
+ memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
+ icom_port->statStg->xmit[index].leLengthASD =
+ (unsigned short int) cpu_to_le16(XMIT_BUFF_SZ);
+ trace(icom_port, "FOD_XBUFF",
+ (unsigned long) icom_port->xmit_buf);
+ icom_port->statStg->xmit[index].leBuffer =
+ cpu_to_le32(icom_port->xmit_buf_pci);
+ } else {
+ memset(&icom_port->statStg->xmit[index], 0, sizeof(struct xmit_status_area));
+ }
+ }
+ /* FIDs */
+ startStgAddr = stgAddr;
+
+ /* fill in every entry, even if no buffer */
+ for (index = 0; index < NUM_RBUFFS; index++) {
+ trace(icom_port, "FID_ADDR", stgAddr);
+ stgAddr = stgAddr + sizeof(icom_port->statStg->rcv[0]);
+ icom_port->statStg->rcv[index].leLength = 0;
+ icom_port->statStg->rcv[index].WorkingLength =
+ (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
+ if (index < (NUM_RBUFFS - 1) ) {
+ offset = stgAddr - (unsigned long) icom_port->statStg;
+ icom_port->statStg->rcv[index].leNext =
+ cpu_to_le32(icom_port-> statStg_pci + offset);
+ trace(icom_port, "FID_RBUFF",
+ (unsigned long) icom_port->recv_buf);
+ icom_port->statStg->rcv[index].leBuffer =
+ cpu_to_le32(icom_port->recv_buf_pci);
+ } else if (index == (NUM_RBUFFS -1) ) {
+ offset = startStgAddr - (unsigned long) icom_port->statStg;
+ icom_port->statStg->rcv[index].leNext =
+ cpu_to_le32(icom_port-> statStg_pci + offset);
+ trace(icom_port, "FID_RBUFF",
+ (unsigned long) icom_port->recv_buf + 2048);
+ icom_port->statStg->rcv[index].leBuffer =
+ cpu_to_le32(icom_port->recv_buf_pci + 2048);
+ } else {
+ icom_port->statStg->rcv[index].leNext = 0;
+ icom_port->statStg->rcv[index].leBuffer = 0;
+ }
+ }
+
+ return 0;
+}
+
+static void stop_processor(struct icom_port *icom_port)
+{
+ unsigned long temp;
+ unsigned long flags;
+ int port;
+
+ spin_lock_irqsave(&icom_lock, flags);
+
+ port = icom_port->port;
+ if (port == 0 || port == 1)
+ stop_proc[port].global_control_reg = &icom_port->global_reg->control;
+ else
+ stop_proc[port].global_control_reg = &icom_port->global_reg->control_2;
+
+
+ if (port < 4) {
+ temp = readl(stop_proc[port].global_control_reg);
+ temp =
+ (temp & ~start_proc[port].processor_id) | stop_proc[port].processor_id;
+ writel(temp, stop_proc[port].global_control_reg);
+
+ /* write flush */
+ readl(stop_proc[port].global_control_reg);
+ } else {
+ dev_err(&icom_port->adapter->pci_dev->dev,
+ "Invalid port assignment\n");
+ }
+
+ spin_unlock_irqrestore(&icom_lock, flags);
+}
+
+static void start_processor(struct icom_port *icom_port)
+{
+ unsigned long temp;
+ unsigned long flags;
+ int port;
+
+ spin_lock_irqsave(&icom_lock, flags);
+
+ port = icom_port->port;
+ if (port == 0 || port == 1)
+ start_proc[port].global_control_reg = &icom_port->global_reg->control;
+ else
+ start_proc[port].global_control_reg = &icom_port->global_reg->control_2;
+ if (port < 4) {
+ temp = readl(start_proc[port].global_control_reg);
+ temp =
+ (temp & ~stop_proc[port].processor_id) | start_proc[port].processor_id;
+ writel(temp, start_proc[port].global_control_reg);
+
+ /* write flush */
+ readl(start_proc[port].global_control_reg);
+ } else {
+ dev_err(&icom_port->adapter->pci_dev->dev,
+ "Invalid port assignment\n");
+ }
+
+ spin_unlock_irqrestore(&icom_lock, flags);
+}
+
+static void load_code(struct icom_port *icom_port)
+{
+ const struct firmware *fw;
+ char *iram_ptr;
+ int index;
+ int status = 0;
+ char *dram_ptr = (char *) icom_port->dram;
+ dma_addr_t temp_pci;
+ unsigned char *new_page = NULL;
+ unsigned char cable_id = NO_CABLE;
+ struct pci_dev *dev = icom_port->adapter->pci_dev;
+
+ /* Clear out any pending interrupts */
+ writew(0x3FFF, (void *) icom_port->int_reg);
+
+ trace(icom_port, "CLEAR_INTERRUPTS", 0);
+
+ /* Stop processor */
+ stop_processor(icom_port);
+
+ /* Zero out DRAM */
+ memset_io(dram_ptr, 0, 512);
+
+ /* Load Call Setup into Adapter */
+ if (request_firmware(&fw, "icom_call_setup.bin", &dev->dev) < 0) {
+ dev_err(&dev->dev,"Unable to load icom_call_setup.bin firmware image\n");
+ status = -1;
+ goto load_code_exit;
+ }
+
+ if (fw->size > ICOM_DCE_IRAM_OFFSET) {
+ dev_err(&dev->dev, "Invalid firmware image for icom_call_setup.bin found.\n");
+ release_firmware(fw);
+ status = -1;
+ goto load_code_exit;
+ }
+
+ iram_ptr = (char *) icom_port->dram + ICOM_IRAM_OFFSET;
+ for (index = 0; index < fw->size; index++)
+ writeb(fw->data[index], &iram_ptr[index]);
+
+ release_firmware(fw);
+
+ /* Load Resident DCE portion of Adapter */
+ if (request_firmware(&fw, "icom_res_dce.bin", &dev->dev) < 0) {
+ dev_err(&dev->dev,"Unable to load icom_res_dce.bin firmware image\n");
+ status = -1;
+ goto load_code_exit;
+ }
+
+ if (fw->size > ICOM_IRAM_SIZE) {
+ dev_err(&dev->dev, "Invalid firmware image for icom_res_dce.bin found.\n");
+ release_firmware(fw);
+ status = -1;
+ goto load_code_exit;
+ }
+
+ iram_ptr = (char *) icom_port->dram + ICOM_IRAM_OFFSET;
+ for (index = ICOM_DCE_IRAM_OFFSET; index < fw->size; index++)
+ writeb(fw->data[index], &iram_ptr[index]);
+
+ release_firmware(fw);
+
+ /* Set Hardware level */
+ if ((icom_port->adapter->version | ADAPTER_V2) == ADAPTER_V2)
+ writeb(V2_HARDWARE, &(icom_port->dram->misc_flags));
+
+ /* Start the processor in Adapter */
+ start_processor(icom_port);
+
+ writeb((HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL),
+ &(icom_port->dram->HDLCConfigReg));
+ writeb(0x04, &(icom_port->dram->FlagFillIdleTimer)); /* 0.5 seconds */
+ writeb(0x00, &(icom_port->dram->CmdReg));
+ writeb(0x10, &(icom_port->dram->async_config3));
+ writeb((ICOM_ACFG_DRIVE1 | ICOM_ACFG_NO_PARITY | ICOM_ACFG_8BPC |
+ ICOM_ACFG_1STOP_BIT), &(icom_port->dram->async_config2));
+
+ /*Set up data in icom DRAM to indicate where personality
+ *code is located and its length.
+ */
+ new_page = pci_alloc_consistent(dev, 4096, &temp_pci);
+
+ if (!new_page) {
+ dev_err(&dev->dev, "Can not allocate DMA buffer\n");
+ status = -1;
+ goto load_code_exit;
+ }
+
+ if (request_firmware(&fw, "icom_asc.bin", &dev->dev) < 0) {
+ dev_err(&dev->dev,"Unable to load icom_asc.bin firmware image\n");
+ status = -1;
+ goto load_code_exit;
+ }
+
+ if (fw->size > ICOM_DCE_IRAM_OFFSET) {
+ dev_err(&dev->dev, "Invalid firmware image for icom_asc.bin found.\n");
+ release_firmware(fw);
+ status = -1;
+ goto load_code_exit;
+ }
+
+ for (index = 0; index < fw->size; index++)
+ new_page[index] = fw->data[index];
+
+ release_firmware(fw);
+
+ writeb((char) ((fw->size + 16)/16), &icom_port->dram->mac_length);
+ writel(temp_pci, &icom_port->dram->mac_load_addr);
+
+ /*Setting the syncReg to 0x80 causes adapter to start downloading
+ the personality code into adapter instruction RAM.
+ Once code is loaded, it will begin executing and, based on
+ information provided above, will start DMAing data from
+ shared memory to adapter DRAM.
+ */
+ /* the wait loop below verifies this write operation has been done
+ and processed
+ */
+ writeb(START_DOWNLOAD, &icom_port->dram->sync);
+
+ /* Wait max 1 Sec for data download and processor to start */
+ for (index = 0; index < 10; index++) {
+ msleep(100);
+ if (readb(&icom_port->dram->misc_flags) & ICOM_HDW_ACTIVE)
+ break;
+ }
+
+ if (index == 10)
+ status = -1;
+
+ /*
+ * check Cable ID
+ */
+ cable_id = readb(&icom_port->dram->cable_id);
+
+ if (cable_id & ICOM_CABLE_ID_VALID) {
+ /* Get cable ID into the lower 4 bits (standard form) */
+ cable_id = (cable_id & ICOM_CABLE_ID_MASK) >> 4;
+ icom_port->cable_id = cable_id;
+ } else {
+ dev_err(&dev->dev,"Invalid or no cable attached\n");
+ icom_port->cable_id = NO_CABLE;
+ }
+
+ load_code_exit:
+
+ if (status != 0) {
+ /* Clear out any pending interrupts */
+ writew(0x3FFF, (void *) icom_port->int_reg);
+
+ /* Turn off port */
+ writeb(ICOM_DISABLE, &(icom_port->dram->disable));
+
+ /* Stop processor */
+ stop_processor(icom_port);
+
+ dev_err(&icom_port->adapter->pci_dev->dev,"Port not opertional\n");
+ }
+
+ if (new_page != NULL)
+ pci_free_consistent(dev, 4096, new_page, temp_pci);
+}
+
+static int startup(struct icom_port *icom_port)
+{
+ unsigned long temp;
+ unsigned char cable_id, raw_cable_id;
+ unsigned long flags;
+ int port;
+
+ trace(icom_port, "STARTUP", 0);
+
+ if (icom_port->dram == 0x00000000) {
+ /* should NEVER be zero */
+ dev_err(&icom_port->adapter->pci_dev->dev,
+ "Unusable Port, port configuration missing\n");
+ return -ENODEV;
+ }
+
+ /*
+ * check Cable ID
+ */
+ raw_cable_id = readb(&icom_port->dram->cable_id);
+ trace(icom_port, "CABLE_ID", raw_cable_id);
+
+ /* Get cable ID into the lower 4 bits (standard form) */
+ cable_id = (raw_cable_id & ICOM_CABLE_ID_MASK) >> 4;
+
+ /* Check for valid Cable ID */
+ if (!(raw_cable_id & ICOM_CABLE_ID_VALID) ||
+ (cable_id != icom_port->cable_id)) {
+
+ /* reload adapter code, pick up any potential changes in cable id */
+ load_code(icom_port);
+
+ /* still no sign of cable, error out */
+ raw_cable_id = readb(&icom_port->dram->cable_id);
+ cable_id = (raw_cable_id & ICOM_CABLE_ID_MASK) >> 4;
+ if (!(raw_cable_id & ICOM_CABLE_ID_VALID) ||
+ (icom_port->cable_id == NO_CABLE))
+ return -EIO;
+ }
+
+ /*
+ * Finally, clear and enable interrupts
+ */
+ spin_lock_irqsave(&icom_lock, flags);
+ port = icom_port->port;
+ if (port == 0 || port == 1)
+ int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask;
+ else
+ int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask_2;
+
+ if (port == 0 || port == 2)
+ writew(0x00FF,(void *) icom_port->int_reg);
+ else
+ writew(0x3F00,(void *) icom_port->int_reg);
+ if (port < 4) {
+ temp = readl(int_mask_tbl[port].global_int_mask);
+ writel(temp & ~int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
+
+ /* write flush */
+ readl(int_mask_tbl[port].global_int_mask);
+ } else {
+ dev_err(&icom_port->adapter->pci_dev->dev,
+ "Invalid port assignment\n");
+ }
+
+ spin_unlock_irqrestore(&icom_lock, flags);
+ return 0;
+}
+
+static void shutdown(struct icom_port *icom_port)
+{
+ unsigned long temp;
+ unsigned char cmdReg;
+ unsigned long flags;
+ int port;
+
+ spin_lock_irqsave(&icom_lock, flags);
+ trace(icom_port, "SHUTDOWN", 0);
+
+ /*
+ * disable all interrupts
+ */
+ port = icom_port->port;
+ if (port == 0 || port == 1)
+ int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask;
+ else
+ int_mask_tbl[port].global_int_mask = &icom_port->global_reg->int_mask_2;
+
+ if (port < 4) {
+ temp = readl(int_mask_tbl[port].global_int_mask);
+ writel(temp | int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
+
+ /* write flush */
+ readl(int_mask_tbl[port].global_int_mask);
+ } else {
+ dev_err(&icom_port->adapter->pci_dev->dev,
+ "Invalid port assignment\n");
+ }
+ spin_unlock_irqrestore(&icom_lock, flags);
+
+ /*
+ * disable break condition
+ */
+ cmdReg = readb(&icom_port->dram->CmdReg);
+ if ((cmdReg | CMD_SND_BREAK) == CMD_SND_BREAK) {
+ writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg);
+ }
+}
+
+static int icom_write(struct uart_port *port)
+{
+ unsigned long data_count;
+ unsigned char cmdReg;
+ unsigned long offset;
+ int temp_tail = port->info->xmit.tail;
+
+ trace(ICOM_PORT, "WRITE", 0);
+
+ if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
+ SA_FLAGS_READY_TO_XMIT) {
+ trace(ICOM_PORT, "WRITE_FULL", 0);
+ return 0;
+ }
+
+ data_count = 0;
+ while ((port->info->xmit.head != temp_tail) &&
+ (data_count <= XMIT_BUFF_SZ)) {
+
+ ICOM_PORT->xmit_buf[data_count++] =
+ port->info->xmit.buf[temp_tail];
+
+ temp_tail++;
+ temp_tail &= (UART_XMIT_SIZE - 1);
+ }
+
+ if (data_count) {
+ ICOM_PORT->statStg->xmit[0].flags =
+ cpu_to_le16(SA_FLAGS_READY_TO_XMIT);
+ ICOM_PORT->statStg->xmit[0].leLength =
+ cpu_to_le16(data_count);
+ offset =
+ (unsigned long) &ICOM_PORT->statStg->xmit[0] -
+ (unsigned long) ICOM_PORT->statStg;
+ *ICOM_PORT->xmitRestart =
+ cpu_to_le32(ICOM_PORT->statStg_pci + offset);
+ cmdReg = readb(&ICOM_PORT->dram->CmdReg);
+ writeb(cmdReg | CMD_XMIT_RCV_ENABLE,
+ &ICOM_PORT->dram->CmdReg);
+ writeb(START_XMIT, &ICOM_PORT->dram->StartXmitCmd);
+ trace(ICOM_PORT, "WRITE_START", data_count);
+ /* write flush */
+ readb(&ICOM_PORT->dram->StartXmitCmd);
+ }
+
+ return data_count;
+}
+
+static inline void check_modem_status(struct icom_port *icom_port)
+{
+ static char old_status = 0;
+ char delta_status;
+ unsigned char status;
+
+ spin_lock(&icom_port->uart_port.lock);
+
+ /*modem input register */
+ status = readb(&icom_port->dram->isr);
+ trace(icom_port, "CHECK_MODEM", status);
+ delta_status = status ^ old_status;
+ if (delta_status) {
+ if (delta_status & ICOM_RI)
+ icom_port->uart_port.icount.rng++;
+ if (delta_status & ICOM_DSR)
+ icom_port->uart_port.icount.dsr++;
+ if (delta_status & ICOM_DCD)
+ uart_handle_dcd_change(&icom_port->uart_port,
+ delta_status & ICOM_DCD);
+ if (delta_status & ICOM_CTS)
+ uart_handle_cts_change(&icom_port->uart_port,
+ delta_status & ICOM_CTS);
+
+ wake_up_interruptible(&icom_port->uart_port.info->
+ delta_msr_wait);
+ old_status = status;
+ }
+ spin_unlock(&icom_port->uart_port.lock);
+}
+
+static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port)
+{
+ unsigned short int count;
+ int i;
+
+ if (port_int_reg & (INT_XMIT_COMPLETED)) {
+ trace(icom_port, "XMIT_COMPLETE", 0);
+
+ /* clear buffer in use bit */
+ icom_port->statStg->xmit[0].flags &=
+ cpu_to_le16(~SA_FLAGS_READY_TO_XMIT);
+
+ count = (unsigned short int)
+ cpu_to_le16(icom_port->statStg->xmit[0].leLength);
+ icom_port->uart_port.icount.tx += count;
+
+ for (i=0; i<count &&
+ !uart_circ_empty(&icom_port->uart_port.info->xmit); i++) {
+
+ icom_port->uart_port.info->xmit.tail++;
+ icom_port->uart_port.info->xmit.tail &=
+ (UART_XMIT_SIZE - 1);
+ }
+
+ if (!icom_write(&icom_port->uart_port))
+ /* activate write queue */
+ uart_write_wakeup(&icom_port->uart_port);
+ } else
+ trace(icom_port, "XMIT_DISABLED", 0);
+}
+
+static void recv_interrupt(u16 port_int_reg, struct icom_port *icom_port)
+{
+ short int count, rcv_buff;
+ struct tty_struct *tty = icom_port->uart_port.info->tty;
+ unsigned short int status;
+ struct uart_icount *icount;
+ unsigned long offset;
+
+ trace(icom_port, "RCV_COMPLETE", 0);
+ rcv_buff = icom_port->next_rcv;
+
+ status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
+ while (status & SA_FL_RCV_DONE) {
+
+ trace(icom_port, "FID_STATUS", status);
+ count = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].leLength);
+
+ trace(icom_port, "RCV_COUNT", count);
+ if (count > (TTY_FLIPBUF_SIZE - tty->flip.count))
+ count = TTY_FLIPBUF_SIZE - tty->flip.count;
+
+ trace(icom_port, "REAL_COUNT", count);
+
+ offset =
+ cpu_to_le32(icom_port->statStg->rcv[rcv_buff].leBuffer) -
+ icom_port->recv_buf_pci;
+
+ memcpy(tty->flip.char_buf_ptr,(unsigned char *)
+ ((unsigned long)icom_port->recv_buf + offset), count);
+
+ if (count > 0) {
+ tty->flip.count += count - 1;
+ tty->flip.char_buf_ptr += count - 1;
+
+ memset(tty->flip.flag_buf_ptr, 0, count);
+ tty->flip.flag_buf_ptr += count - 1;
+ }
+
+ icount = &icom_port->uart_port.icount;
+ icount->rx += count;
+
+ /* Break detect logic */
+ if ((status & SA_FLAGS_FRAME_ERROR)
+ && (tty->flip.char_buf_ptr[0] == 0x00)) {
+ status &= ~SA_FLAGS_FRAME_ERROR;
+ status |= SA_FLAGS_BREAK_DET;
+ trace(icom_port, "BREAK_DET", 0);
+ }
+
+ if (status &
+ (SA_FLAGS_BREAK_DET | SA_FLAGS_PARITY_ERROR |
+ SA_FLAGS_FRAME_ERROR | SA_FLAGS_OVERRUN)) {
+
+ if (status & SA_FLAGS_BREAK_DET)
+ icount->brk++;
+ if (status & SA_FLAGS_PARITY_ERROR)
+ icount->parity++;
+ if (status & SA_FLAGS_FRAME_ERROR)
+ icount->frame++;
+ if (status & SA_FLAGS_OVERRUN)
+ icount->overrun++;
+
+ /*
+ * Now check to see if character should be
+ * ignored, and mask off conditions which
+ * should be ignored.
+ */
+ if (status & icom_port->ignore_status_mask) {
+ trace(icom_port, "IGNORE_CHAR", 0);
+ goto ignore_char;
+ }
+
+ status &= icom_port->read_status_mask;
+
+ if (status & SA_FLAGS_BREAK_DET) {
+ *tty->flip.flag_buf_ptr = TTY_BREAK;
+ } else if (status & SA_FLAGS_PARITY_ERROR) {
+ trace(icom_port, "PARITY_ERROR", 0);
+ *tty->flip.flag_buf_ptr = TTY_PARITY;
+ } else if (status & SA_FLAGS_FRAME_ERROR)
+ *tty->flip.flag_buf_ptr = TTY_FRAME;
+
+ if (status & SA_FLAGS_OVERRUN) {
+ /*
+ * Overrun is special, since it's
+ * reported immediately, and doesn't
+ * affect the current character
+ */
+ if (tty->flip.count < TTY_FLIPBUF_SIZE) {
+ tty->flip.count++;
+ tty->flip.flag_buf_ptr++;
+ tty->flip.char_buf_ptr++;
+ *tty->flip.flag_buf_ptr = TTY_OVERRUN;
+ }
+ }
+ }
+
+ tty->flip.flag_buf_ptr++;
+ tty->flip.char_buf_ptr++;
+ tty->flip.count++;
+ ignore_char:
+ icom_port->statStg->rcv[rcv_buff].flags = 0;
+ icom_port->statStg->rcv[rcv_buff].leLength = 0;
+ icom_port->statStg->rcv[rcv_buff].WorkingLength =
+ (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
+
+ rcv_buff++;
+ if (rcv_buff == NUM_RBUFFS)
+ rcv_buff = 0;
+
+ status = cpu_to_le16(icom_port->statStg->rcv[rcv_buff].flags);
+ }
+ icom_port->next_rcv = rcv_buff;
+ tty_flip_buffer_push(tty);
+}
+
+static void process_interrupt(u16 port_int_reg,
+ struct icom_port *icom_port)
+{
+
+ spin_lock(&icom_port->uart_port.lock);
+ trace(icom_port, "INTERRUPT", port_int_reg);
+
+ if (port_int_reg & (INT_XMIT_COMPLETED | INT_XMIT_DISABLED))
+ xmit_interrupt(port_int_reg, icom_port);
+
+ if (port_int_reg & INT_RCV_COMPLETED)
+ recv_interrupt(port_int_reg, icom_port);
+
+ spin_unlock(&icom_port->uart_port.lock);
+}
+
+static irqreturn_t icom_interrupt(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ unsigned long int_reg;
+ u32 adapter_interrupts;
+ u16 port_int_reg;
+ struct icom_adapter *icom_adapter;
+ struct icom_port *icom_port;
+
+ /* find icom_port for this interrupt */
+ icom_adapter = (struct icom_adapter *) dev_id;
+
+ if ((icom_adapter->version | ADAPTER_V2) == ADAPTER_V2) {
+ int_reg = icom_adapter->base_addr + 0x8024;
+
+ adapter_interrupts = readl((void *) int_reg);
+
+ if (adapter_interrupts & 0x00003FFF) {
+ /* port 2 interrupt, NOTE: for all ADAPTER_V2, port 2 will be active */
+ icom_port = &icom_adapter->port_info[2];
+ port_int_reg = (u16) adapter_interrupts;
+ process_interrupt(port_int_reg, icom_port);
+ check_modem_status(icom_port);
+ }
+ if (adapter_interrupts & 0x3FFF0000) {
+ /* port 3 interrupt */
+ icom_port = &icom_adapter->port_info[3];
+ if (icom_port->status == ICOM_PORT_ACTIVE) {
+ port_int_reg =
+ (u16) (adapter_interrupts >> 16);
+ process_interrupt(port_int_reg, icom_port);
+ check_modem_status(icom_port);
+ }
+ }
+
+ /* Clear out any pending interrupts */
+ writel(adapter_interrupts, (void *) int_reg);
+
+ int_reg = icom_adapter->base_addr + 0x8004;
+ } else {
+ int_reg = icom_adapter->base_addr + 0x4004;
+ }
+
+ adapter_interrupts = readl((void *) int_reg);
+
+ if (adapter_interrupts & 0x00003FFF) {
+ /* port 0 interrupt, NOTE: for all adapters, port 0 will be active */
+ icom_port = &icom_adapter->port_info[0];
+ port_int_reg = (u16) adapter_interrupts;
+ process_interrupt(port_int_reg, icom_port);
+ check_modem_status(icom_port);
+ }
+ if (adapter_interrupts & 0x3FFF0000) {
+ /* port 1 interrupt */
+ icom_port = &icom_adapter->port_info[1];
+ if (icom_port->status == ICOM_PORT_ACTIVE) {
+ port_int_reg = (u16) (adapter_interrupts >> 16);
+ process_interrupt(port_int_reg, icom_port);
+ check_modem_status(icom_port);
+ }
+ }
+
+ /* Clear out any pending interrupts */
+ writel(adapter_interrupts, (void *) int_reg);
+
+ /* flush the write */
+ adapter_interrupts = readl((void *) int_reg);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * ------------------------------------------------------------------
+ * Begin serial-core API
+ * ------------------------------------------------------------------
+ */
+static unsigned int icom_tx_empty(struct uart_port *port)
+{
+ int ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+ if (cpu_to_le16(ICOM_PORT->statStg->xmit[0].flags) &
+ SA_FLAGS_READY_TO_XMIT)
+ ret = TIOCSER_TEMT;
+ else
+ ret = 0;
+
+ spin_unlock_irqrestore(&port->lock, flags);
+ return ret;
+}
+
+static void icom_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ unsigned char local_osr;
+
+ trace(ICOM_PORT, "SET_MODEM", 0);
+ local_osr = readb(&ICOM_PORT->dram->osr);
+
+ if (mctrl & TIOCM_RTS) {
+ trace(ICOM_PORT, "RAISE_RTS", 0);
+ local_osr |= ICOM_RTS;
+ } else {
+ trace(ICOM_PORT, "LOWER_RTS", 0);
+ local_osr &= ~ICOM_RTS;
+ }
+
+ if (mctrl & TIOCM_DTR) {
+ trace(ICOM_PORT, "RAISE_DTR", 0);
+ local_osr |= ICOM_DTR;
+ } else {
+ trace(ICOM_PORT, "LOWER_DTR", 0);
+ local_osr &= ~ICOM_DTR;
+ }
+
+ writeb(local_osr, &ICOM_PORT->dram->osr);
+}
+
+static unsigned int icom_get_mctrl(struct uart_port *port)
+{
+ unsigned char status;
+ unsigned int result;
+
+ trace(ICOM_PORT, "GET_MODEM", 0);
+
+ status = readb(&ICOM_PORT->dram->isr);
+
+ result = ((status & ICOM_DCD) ? TIOCM_CAR : 0)
+ | ((status & ICOM_RI) ? TIOCM_RNG : 0)
+ | ((status & ICOM_DSR) ? TIOCM_DSR : 0)
+ | ((status & ICOM_CTS) ? TIOCM_CTS : 0);
+ return result;
+}
+
+static void icom_stop_tx(struct uart_port *port, unsigned int tty_stop)
+{
+ unsigned char cmdReg;
+
+ if (tty_stop) {
+ trace(ICOM_PORT, "STOP", 0);
+ cmdReg = readb(&ICOM_PORT->dram->CmdReg);
+ writeb(cmdReg | CMD_HOLD_XMIT, &ICOM_PORT->dram->CmdReg);
+ }
+}
+
+static void icom_start_tx(struct uart_port *port, unsigned int tty_start)
+{
+ unsigned char cmdReg;
+
+ trace(ICOM_PORT, "START", 0);
+ cmdReg = readb(&ICOM_PORT->dram->CmdReg);
+ if ((cmdReg & CMD_HOLD_XMIT) == CMD_HOLD_XMIT)
+ writeb(cmdReg & ~CMD_HOLD_XMIT,
+ &ICOM_PORT->dram->CmdReg);
+
+ icom_write(port);
+}
+
+static void icom_send_xchar(struct uart_port *port, char ch)
+{
+ unsigned char xdata;
+ int index;
+ unsigned long flags;
+
+ trace(ICOM_PORT, "SEND_XCHAR", ch);
+
+ /* wait .1 sec to send char */
+ for (index = 0; index < 10; index++) {
+ spin_lock_irqsave(&port->lock, flags);
+ xdata = readb(&ICOM_PORT->dram->xchar);
+ if (xdata == 0x00) {
+ trace(ICOM_PORT, "QUICK_WRITE", 0);
+ writeb(ch, &ICOM_PORT->dram->xchar);
+
+ /* flush write operation */
+ xdata = readb(&ICOM_PORT->dram->xchar);
+ spin_unlock_irqrestore(&port->lock, flags);
+ break;
+ }
+ spin_unlock_irqrestore(&port->lock, flags);
+ msleep(10);
+ }
+}
+
+static void icom_stop_rx(struct uart_port *port)
+{
+ unsigned char cmdReg;
+
+ cmdReg = readb(&ICOM_PORT->dram->CmdReg);
+ writeb(cmdReg & ~CMD_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
+}
+
+static void icom_enable_ms(struct uart_port *port)
+{
+ /* no-op */
+}
+
+static void icom_break(struct uart_port *port, int break_state)
+{
+ unsigned char cmdReg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+ trace(ICOM_PORT, "BREAK", 0);
+ cmdReg = readb(&ICOM_PORT->dram->CmdReg);
+ if (break_state == -1) {
+ writeb(cmdReg | CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
+ } else {
+ writeb(cmdReg & ~CMD_SND_BREAK, &ICOM_PORT->dram->CmdReg);
+ }
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static int icom_open(struct uart_port *port)
+{
+ int retval;
+
+ kobject_get(&ICOM_PORT->adapter->kobj);
+ retval = startup(ICOM_PORT);
+
+ if (retval) {
+ kobject_put(&ICOM_PORT->adapter->kobj);
+ trace(ICOM_PORT, "STARTUP_ERROR", 0);
+ return retval;
+ }
+
+ return 0;
+}
+
+static void icom_close(struct uart_port *port)
+{
+ unsigned char cmdReg;
+
+ trace(ICOM_PORT, "CLOSE", 0);
+
+ /* stop receiver */
+ cmdReg = readb(&ICOM_PORT->dram->CmdReg);
+ writeb(cmdReg & (unsigned char) ~CMD_RCV_ENABLE,
+ &ICOM_PORT->dram->CmdReg);
+
+ shutdown(ICOM_PORT);
+
+ kobject_put(&ICOM_PORT->adapter->kobj);
+}
+
+static void icom_set_termios(struct uart_port *port,
+ struct termios *termios,
+ struct termios *old_termios)
+{
+ int baud;
+ unsigned cflag, iflag;
+ int bits;
+ char new_config2;
+ char new_config3 = 0;
+ char tmp_byte;
+ int index;
+ int rcv_buff, xmit_buff;
+ unsigned long offset;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+ trace(ICOM_PORT, "CHANGE_SPEED", 0);
+
+ cflag = termios->c_cflag;
+ iflag = termios->c_iflag;
+
+ new_config2 = ICOM_ACFG_DRIVE1;
+
+ /* byte size and parity */
+ switch (cflag & CSIZE) {
+ case CS5: /* 5 bits/char */
+ new_config2 |= ICOM_ACFG_5BPC;
+ bits = 7;
+ break;
+ case CS6: /* 6 bits/char */
+ new_config2 |= ICOM_ACFG_6BPC;
+ bits = 8;
+ break;
+ case CS7: /* 7 bits/char */
+ new_config2 |= ICOM_ACFG_7BPC;
+ bits = 9;
+ break;
+ case CS8: /* 8 bits/char */
+ new_config2 |= ICOM_ACFG_8BPC;
+ bits = 10;
+ break;
+ default:
+ bits = 10;
+ break;
+ }
+ if (cflag & CSTOPB) {
+ /* 2 stop bits */
+ new_config2 |= ICOM_ACFG_2STOP_BIT;
+ bits++;
+ }
+ if (cflag & PARENB) {
+ /* parity bit enabled */
+ new_config2 |= ICOM_ACFG_PARITY_ENAB;
+ trace(ICOM_PORT, "PARENB", 0);
+ bits++;
+ }
+ if (cflag & PARODD) {
+ /* odd parity */
+ new_config2 |= ICOM_ACFG_PARITY_ODD;
+ trace(ICOM_PORT, "PARODD", 0);
+ }
+
+ /* Determine divisor based on baud rate */
+ baud = uart_get_baud_rate(port, termios, old_termios,
+ icom_acfg_baud[0],
+ icom_acfg_baud[BAUD_TABLE_LIMIT]);
+ if (!baud)
+ baud = 9600; /* B0 transition handled in rs_set_termios */
+
+ for (index = 0; index < BAUD_TABLE_LIMIT; index++) {
+ if (icom_acfg_baud[index] == baud) {
+ new_config3 = index;
+ break;
+ }
+ }
+
+ uart_update_timeout(port, cflag, baud);
+
+ /* CTS flow control flag and modem status interrupts */
+ tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
+ if (cflag & CRTSCTS)
+ tmp_byte |= HDLC_HDW_FLOW;
+ else
+ tmp_byte &= ~HDLC_HDW_FLOW;
+ writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
+
+ /*
+ * Set up parity check flag
+ */
+ ICOM_PORT->read_status_mask = SA_FLAGS_OVERRUN | SA_FL_RCV_DONE;
+ if (iflag & INPCK)
+ ICOM_PORT->read_status_mask |=
+ SA_FLAGS_FRAME_ERROR | SA_FLAGS_PARITY_ERROR;
+
+ if ((iflag & BRKINT) || (iflag & PARMRK))
+ ICOM_PORT->read_status_mask |= SA_FLAGS_BREAK_DET;
+
+ /*
+ * Characters to ignore
+ */
+ ICOM_PORT->ignore_status_mask = 0;
+ if (iflag & IGNPAR)
+ ICOM_PORT->ignore_status_mask |=
+ SA_FLAGS_PARITY_ERROR | SA_FLAGS_FRAME_ERROR;
+ if (iflag & IGNBRK) {
+ ICOM_PORT->ignore_status_mask |= SA_FLAGS_BREAK_DET;
+ /*
+ * If we're ignore parity and break indicators, ignore
+ * overruns too. (For real raw support).
+ */
+ if (iflag & IGNPAR)
+ ICOM_PORT->ignore_status_mask |= SA_FLAGS_OVERRUN;
+ }
+
+ /*
+ * !!! ignore all characters if CREAD is not set
+ */
+ if ((cflag & CREAD) == 0)
+ ICOM_PORT->ignore_status_mask |= SA_FL_RCV_DONE;
+
+ /* Turn off Receiver to prepare for reset */
+ writeb(CMD_RCV_DISABLE, &ICOM_PORT->dram->CmdReg);
+
+ for (index = 0; index < 10; index++) {
+ if (readb(&ICOM_PORT->dram->PrevCmdReg) == 0x00) {
+ break;
+ }
+ }
+
+ /* clear all current buffers of data */
+ for (rcv_buff = 0; rcv_buff < NUM_RBUFFS; rcv_buff++) {
+ ICOM_PORT->statStg->rcv[rcv_buff].flags = 0;
+ ICOM_PORT->statStg->rcv[rcv_buff].leLength = 0;
+ ICOM_PORT->statStg->rcv[rcv_buff].WorkingLength =
+ (unsigned short int) cpu_to_le16(RCV_BUFF_SZ);
+ }
+
+ for (xmit_buff = 0; xmit_buff < NUM_XBUFFS; xmit_buff++) {
+ ICOM_PORT->statStg->xmit[xmit_buff].flags = 0;
+ }
+
+ /* activate changes and start xmit and receiver here */
+ /* Enable the receiver */
+ writeb(new_config3, &(ICOM_PORT->dram->async_config3));
+ writeb(new_config2, &(ICOM_PORT->dram->async_config2));
+ tmp_byte = readb(&(ICOM_PORT->dram->HDLCConfigReg));
+ tmp_byte |= HDLC_PPP_PURE_ASYNC | HDLC_FF_FILL;
+ writeb(tmp_byte, &(ICOM_PORT->dram->HDLCConfigReg));
+ writeb(0x04, &(ICOM_PORT->dram->FlagFillIdleTimer)); /* 0.5 seconds */
+ writeb(0xFF, &(ICOM_PORT->dram->ier)); /* enable modem signal interrupts */
+
+ /* reset processor */
+ writeb(CMD_RESTART, &ICOM_PORT->dram->CmdReg);
+
+ for (index = 0; index < 10; index++) {
+ if (readb(&ICOM_PORT->dram->CmdReg) == 0x00) {
+ break;
+ }
+ }
+
+ /* Enable Transmitter and Reciever */
+ offset =
+ (unsigned long) &ICOM_PORT->statStg->rcv[0] -
+ (unsigned long) ICOM_PORT->statStg;
+ writel(ICOM_PORT->statStg_pci + offset,
+ &ICOM_PORT->dram->RcvStatusAddr);
+ ICOM_PORT->next_rcv = 0;
+ ICOM_PORT->put_length = 0;
+ *ICOM_PORT->xmitRestart = 0;
+ writel(ICOM_PORT->xmitRestart_pci,
+ &ICOM_PORT->dram->XmitStatusAddr);
+ trace(ICOM_PORT, "XR_ENAB", 0);
+ writeb(CMD_XMIT_RCV_ENABLE, &ICOM_PORT->dram->CmdReg);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *icom_type(struct uart_port *port)
+{
+ return "icom";
+}
+
+static void icom_release_port(struct uart_port *port)
+{
+}
+
+static int icom_request_port(struct uart_port *port)
+{
+ return 0;
+}
+
+static void icom_config_port(struct uart_port *port, int flags)
+{
+ port->type = PORT_ICOM;
+}
+
+static struct uart_ops icom_ops = {
+ .tx_empty = icom_tx_empty,
+ .set_mctrl = icom_set_mctrl,
+ .get_mctrl = icom_get_mctrl,
+ .stop_tx = icom_stop_tx,
+ .start_tx = icom_start_tx,
+ .send_xchar = icom_send_xchar,
+ .stop_rx = icom_stop_rx,
+ .enable_ms = icom_enable_ms,
+ .break_ctl = icom_break,
+ .startup = icom_open,
+ .shutdown = icom_close,
+ .set_termios = icom_set_termios,
+ .type = icom_type,
+ .release_port = icom_release_port,
+ .request_port = icom_request_port,
+ .config_port = icom_config_port,
+};
+
+#define ICOM_CONSOLE NULL
+
+static struct uart_driver icom_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = ICOM_DRIVER_NAME,
+ .dev_name = "ttyA",
+ .major = ICOM_MAJOR,
+ .minor = ICOM_MINOR_START,
+ .nr = NR_PORTS,
+ .cons = ICOM_CONSOLE,
+};
+
+static int __devinit icom_init_ports(struct icom_adapter *icom_adapter)
+{
+ u32 subsystem_id = icom_adapter->subsystem_id;
+ int retval = 0;
+ int i;
+ struct icom_port *icom_port;
+
+ if (icom_adapter->version == ADAPTER_V1) {
+ icom_adapter->numb_ports = 2;
+
+ for (i = 0; i < 2; i++) {
+ icom_port = &icom_adapter->port_info[i];
+ icom_port->port = i;
+ icom_port->status = ICOM_PORT_ACTIVE;
+ icom_port->imbed_modem = ICOM_UNKNOWN;
+ }
+ } else {
+ if (subsystem_id == PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL) {
+ icom_adapter->numb_ports = 4;
+
+ for (i = 0; i < 4; i++) {
+ icom_port = &icom_adapter->port_info[i];
+
+ icom_port->port = i;
+ icom_port->status = ICOM_PORT_ACTIVE;
+ icom_port->imbed_modem = ICOM_IMBED_MODEM;
+ }
+ } else {
+ icom_adapter->numb_ports = 4;
+
+ icom_adapter->port_info[0].port = 0;
+ icom_adapter->port_info[0].status = ICOM_PORT_ACTIVE;
+
+ if (subsystem_id ==
+ PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM) {
+ icom_adapter->port_info[0].imbed_modem = ICOM_IMBED_MODEM;
+ } else {
+ icom_adapter->port_info[0].imbed_modem = ICOM_RVX;
+ }
+
+ icom_adapter->port_info[1].status = ICOM_PORT_OFF;
+
+ icom_adapter->port_info[2].port = 2;
+ icom_adapter->port_info[2].status = ICOM_PORT_ACTIVE;
+ icom_adapter->port_info[2].imbed_modem = ICOM_RVX;
+ icom_adapter->port_info[3].status = ICOM_PORT_OFF;
+ }
+ }
+
+ return retval;
+}
+
+static void icom_port_active(struct icom_port *icom_port, struct icom_adapter *icom_adapter, int port_num)
+{
+ if (icom_adapter->version == ADAPTER_V1) {
+ icom_port->global_reg = (struct icom_regs *) ((char *)
+ icom_adapter->base_addr + 0x4000);
+ icom_port->int_reg = (unsigned long) icom_adapter->base_addr +
+ 0x4004 + 2 - 2 * port_num;
+ } else {
+ icom_port->global_reg = (struct icom_regs *) ((char *)
+ icom_adapter->base_addr + 0x8000);
+ if (icom_port->port < 2)
+ icom_port->int_reg = (unsigned long) icom_adapter->base_addr +
+ 0x8004 + 2 - 2 * icom_port->port;
+ else
+ icom_port->int_reg = (unsigned long) icom_adapter->base_addr +
+ 0x8024 + 2 - 2 * (icom_port->port - 2);
+ }
+}
+static int __init icom_load_ports(struct icom_adapter *icom_adapter)
+{
+ struct icom_port *icom_port;
+ int port_num;
+ int retval;
+
+ for (port_num = 0; port_num < icom_adapter->numb_ports; port_num++) {
+
+ icom_port = &icom_adapter->port_info[port_num];
+
+ if (icom_port->status == ICOM_PORT_ACTIVE) {
+ icom_port_active(icom_port, icom_adapter, port_num);
+ icom_port->dram = (struct func_dram *) ((char *)
+ icom_adapter->base_addr +
+ 0x2000 * icom_port->port);
+
+ icom_port->adapter = icom_adapter;
+
+ /* get port memory */
+ if ((retval = get_port_memory(icom_port)) != 0) {
+ dev_err(&icom_port->adapter->pci_dev->dev,
+ "Memory allocation for port FAILED\n");
+ }
+ }
+ }
+ return 0;
+}
+
+static int __devinit icom_alloc_adapter(struct icom_adapter
+ **icom_adapter_ref)
+{
+ int adapter_count = 0;
+ struct icom_adapter *icom_adapter;
+ struct icom_adapter *cur_adapter_entry;
+ struct list_head *tmp;
+
+ icom_adapter = (struct icom_adapter *)
+ kmalloc(sizeof(struct icom_adapter), GFP_KERNEL);
+
+ if (!icom_adapter) {
+ return -ENOMEM;
+ }
+
+ memset(icom_adapter, 0, sizeof(struct icom_adapter));
+
+ list_for_each(tmp, &icom_adapter_head) {
+ cur_adapter_entry =
+ list_entry(tmp, struct icom_adapter,
+ icom_adapter_entry);
+ if (cur_adapter_entry->index != adapter_count) {
+ break;
+ }
+ adapter_count++;
+ }
+
+ icom_adapter->index = adapter_count;
+ list_add_tail(&icom_adapter->icom_adapter_entry, tmp);
+
+ *icom_adapter_ref = icom_adapter;
+ return 0;
+}
+
+static void icom_free_adapter(struct icom_adapter *icom_adapter)
+{
+ list_del(&icom_adapter->icom_adapter_entry);
+ kfree(icom_adapter);
+}
+
+static void icom_remove_adapter(struct icom_adapter *icom_adapter)
+{
+ struct icom_port *icom_port;
+ int index;
+
+ for (index = 0; index < icom_adapter->numb_ports; index++) {
+ icom_port = &icom_adapter->port_info[index];
+
+ if (icom_port->status == ICOM_PORT_ACTIVE) {
+ dev_info(&icom_adapter->pci_dev->dev,
+ "Device removed\n");
+
+ uart_remove_one_port(&icom_uart_driver,
+ &icom_port->uart_port);
+
+ /* be sure that DTR and RTS are dropped */
+ writeb(0x00, &icom_port->dram->osr);
+
+ /* Wait 0.1 Sec for simple Init to complete */
+ msleep(100);
+
+ /* Stop proccessor */
+ stop_processor(icom_port);
+
+ free_port_memory(icom_port);
+ }
+ }
+
+ free_irq(icom_adapter->irq_number, (void *) icom_adapter);
+ iounmap((void *) icom_adapter->base_addr);
+ icom_free_adapter(icom_adapter);
+ pci_release_regions(icom_adapter->pci_dev);
+}
+
+static void icom_kobj_release(struct kobject *kobj)
+{
+ struct icom_adapter *icom_adapter;
+
+ icom_adapter = to_icom_adapter(kobj);
+ icom_remove_adapter(icom_adapter);
+}
+
+static struct kobj_type icom_kobj_type = {
+ .release = icom_kobj_release,
+};
+
+static int __devinit icom_probe(struct pci_dev *dev,
+ const struct pci_device_id *ent)
+{
+ int index;
+ unsigned int command_reg;
+ int retval;
+ struct icom_adapter *icom_adapter;
+ struct icom_port *icom_port;
+
+ retval = pci_enable_device(dev);
+ if (retval) {
+ dev_err(&dev->dev, "Device enable FAILED\n");
+ return retval;
+ }
+
+ if ( (retval = pci_request_regions(dev, "icom"))) {
+ dev_err(&dev->dev, "pci_request_region FAILED\n");
+ pci_disable_device(dev);
+ return retval;
+ }
+
+ pci_set_master(dev);
+
+ if ( (retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg))) {
+ dev_err(&dev->dev, "PCI Config read FAILED\n");
+ return retval;
+ }
+
+ pci_write_config_dword(dev, PCI_COMMAND,
+ command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
+
+ if (ent->driver_data == ADAPTER_V1) {
+ pci_write_config_dword(dev, 0x44, 0x8300830A);
+ } else {
+ pci_write_config_dword(dev, 0x44, 0x42004200);
+ pci_write_config_dword(dev, 0x48, 0x42004200);
+ }
+
+
+ retval = icom_alloc_adapter(&icom_adapter);
+ if (retval) {
+ dev_err(&dev->dev, "icom_alloc_adapter FAILED\n");
+ retval = -EIO;
+ goto probe_exit0;
+ }
+
+ icom_adapter->base_addr_pci = pci_resource_start(dev, 0);
+ icom_adapter->irq_number = dev->irq;
+ icom_adapter->pci_dev = dev;
+ icom_adapter->version = ent->driver_data;
+ icom_adapter->subsystem_id = ent->subdevice;
+
+
+ retval = icom_init_ports(icom_adapter);
+ if (retval) {
+ dev_err(&dev->dev, "Port configuration failed\n");
+ goto probe_exit1;
+ }
+
+ icom_adapter->base_addr =
+ (unsigned long) ioremap(icom_adapter->base_addr_pci,
+ pci_resource_len(dev, 0));
+
+ if (!icom_adapter->base_addr)
+ goto probe_exit1;
+
+ /* save off irq and request irq line */
+ if ( (retval = request_irq(dev->irq, icom_interrupt,
+ SA_INTERRUPT | SA_SHIRQ, ICOM_DRIVER_NAME,
+ (void *) icom_adapter))) {
+ goto probe_exit2;
+ }
+
+ retval = icom_load_ports(icom_adapter);
+
+ for (index = 0; index < icom_adapter->numb_ports; index++) {
+ icom_port = &icom_adapter->port_info[index];
+
+ if (icom_port->status == ICOM_PORT_ACTIVE) {
+ icom_port->uart_port.irq = icom_port->adapter->irq_number;
+ icom_port->uart_port.type = PORT_ICOM;
+ icom_port->uart_port.iotype = UPIO_MEM;
+ icom_port->uart_port.membase =
+ (char *) icom_adapter->base_addr_pci;
+ icom_port->uart_port.fifosize = 16;
+ icom_port->uart_port.ops = &icom_ops;
+ icom_port->uart_port.line =
+ icom_port->port + icom_adapter->index * 4;
+ if (uart_add_one_port (&icom_uart_driver, &icom_port->uart_port)) {
+ icom_port->status = ICOM_PORT_OFF;
+ dev_err(&dev->dev, "Device add failed\n");
+ } else
+ dev_info(&dev->dev, "Device added\n");
+ }
+ }
+
+ kobject_init(&icom_adapter->kobj);
+ icom_adapter->kobj.ktype = &icom_kobj_type;
+ return 0;
+
+probe_exit2:
+ iounmap((void *) icom_adapter->base_addr);
+probe_exit1:
+ icom_free_adapter(icom_adapter);
+
+probe_exit0:
+ pci_release_regions(dev);
+ pci_disable_device(dev);
+
+ return retval;
+
+
+}
+
+static void __devexit icom_remove(struct pci_dev *dev)
+{
+ struct icom_adapter *icom_adapter;
+ struct list_head *tmp;
+
+ list_for_each(tmp, &icom_adapter_head) {
+ icom_adapter = list_entry(tmp, struct icom_adapter,
+ icom_adapter_entry);
+ if (icom_adapter->pci_dev == dev) {
+ kobject_put(&icom_adapter->kobj);
+ return;
+ }
+ }
+
+ dev_err(&dev->dev, "Unable to find device to remove\n");
+}
+
+static struct pci_driver icom_pci_driver = {
+ .name = ICOM_DRIVER_NAME,
+ .id_table = icom_pci_table,
+ .probe = icom_probe,
+ .remove = __devexit_p(icom_remove),
+};
+
+static int __init icom_init(void)
+{
+ int ret;
+
+ spin_lock_init(&icom_lock);
+ icom_lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
+
+ ret = uart_register_driver(&icom_uart_driver);
+ if (ret)
+ return ret;
+
+ ret = pci_register_driver(&icom_pci_driver);
+
+ if (ret < 0)
+ uart_unregister_driver(&icom_uart_driver);
+
+ return ret;
+}
+
+static void __exit icom_exit(void)
+{
+ pci_unregister_driver(&icom_pci_driver);
+ uart_unregister_driver(&icom_uart_driver);
+}
+
+module_init(icom_init);
+module_exit(icom_exit);
+
+#ifdef ICOM_TRACE
+static inline void trace(struct icom_port *icom_port, char *trace_pt,
+ unsigned long trace_data)
+{
+ dev_info(&icom_port->adapter->pci_dev->dev, ":%d:%s - %lx\n",
+ icom_port->port, trace_pt, trace_data);
+}
+#endif
+
+MODULE_AUTHOR("Michael Anderson <mjanders@us.ibm.com>");
+MODULE_DESCRIPTION("IBM iSeries Serial IOA driver");
+MODULE_SUPPORTED_DEVICE
+ ("IBM iSeries 2745, 2771, 2772, 2742, 2793 and 2805 Communications adapters");
+MODULE_LICENSE("GPL");
+
--- /dev/null
+/*
+ * icom.h
+ *
+ * Copyright (C) 2001 Michael Anderson, IBM Corporation
+ *
+ * Serial device driver include file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include<linux/serial_core.h>
+
+#define BAUD_TABLE_LIMIT ((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
+static int icom_acfg_baud[] = {
+ 300,
+ 600,
+ 900,
+ 1200,
+ 1800,
+ 2400,
+ 3600,
+ 4800,
+ 7200,
+ 9600,
+ 14400,
+ 19200,
+ 28800,
+ 38400,
+ 57600,
+ 76800,
+ 115200,
+ 153600,
+ 230400,
+ 307200,
+ 460800,
+};
+
+struct icom_regs {
+ u32 control; /* Adapter Control Register */
+ u32 interrupt; /* Adapter Interrupt Register */
+ u32 int_mask; /* Adapter Interrupt Mask Reg */
+ u32 int_pri; /* Adapter Interrupt Priority r */
+ u32 int_reg_b; /* Adapter non-masked Interrupt */
+ u32 resvd01;
+ u32 resvd02;
+ u32 resvd03;
+ u32 control_2; /* Adapter Control Register 2 */
+ u32 interrupt_2; /* Adapter Interrupt Register 2 */
+ u32 int_mask_2; /* Adapter Interrupt Mask 2 */
+ u32 int_pri_2; /* Adapter Interrupt Prior 2 */
+ u32 int_reg_2b; /* Adapter non-masked 2 */
+};
+
+struct func_dram {
+ u32 reserved[108]; /* 0-1B0 reserved by personality code */
+ u32 RcvStatusAddr; /* 1B0-1B3 Status Address for Next rcv */
+ u8 RcvStnAddr; /* 1B4 Receive Station Addr */
+ u8 IdleState; /* 1B5 Idle State */
+ u8 IdleMonitor; /* 1B6 Idle Monitor */
+ u8 FlagFillIdleTimer; /* 1B7 Flag Fill Idle Timer */
+ u32 XmitStatusAddr; /* 1B8-1BB Transmit Status Address */
+ u8 StartXmitCmd; /* 1BC Start Xmit Command */
+ u8 HDLCConfigReg; /* 1BD Reserved */
+ u8 CauseCode; /* 1BE Cause code for fatal error */
+ u8 xchar; /* 1BF High priority send */
+ u32 reserved3; /* 1C0-1C3 Reserved */
+ u8 PrevCmdReg; /* 1C4 Reserved */
+ u8 CmdReg; /* 1C5 Command Register */
+ u8 async_config2; /* 1C6 Async Config Byte 2 */
+ u8 async_config3; /* 1C7 Async Config Byte 3 */
+ u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
+ u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
+ u8 misc_flags; /* 1DD misc flags */
+#define V2_HARDWARE 0x40
+#define ICOM_HDW_ACTIVE 0x01
+ u8 call_length; /* 1DE Phone #/CFI buff ln */
+ u8 call_length2; /* 1DF Upper byte (unused) */
+ u32 call_addr; /* 1E0-1E3 Phn #/CFI buff addr */
+ u16 timer_value; /* 1E4-1E5 general timer value */
+ u8 timer_command; /* 1E6 general timer cmd */
+ u8 dce_command; /* 1E7 dce command reg */
+ u8 dce_cmd_status; /* 1E8 dce command stat */
+ u8 x21_r1_ioff; /* 1E9 dce ready counter */
+ u8 x21_r0_ioff; /* 1EA dce not ready ctr */
+ u8 x21_ralt_ioff; /* 1EB dce CNR counter */
+ u8 x21_r1_ion; /* 1EC dce ready I on ctr */
+ u8 rsvd_ier; /* 1ED Rsvd for IER (if ne */
+ u8 ier; /* 1EE Interrupt Enable */
+ u8 isr; /* 1EF Input Signal Reg */
+ u8 osr; /* 1F0 Output Signal Reg */
+ u8 reset; /* 1F1 Reset/Reload Reg */
+ u8 disable; /* 1F2 Disable Reg */
+ u8 sync; /* 1F3 Sync Reg */
+ u8 error_stat; /* 1F4 Error Status */
+ u8 cable_id; /* 1F5 Cable ID */
+ u8 cs_length; /* 1F6 CS Load Length */
+ u8 mac_length; /* 1F7 Mac Load Length */
+ u32 cs_load_addr; /* 1F8-1FB Call Load PCI Addr */
+ u32 mac_load_addr; /* 1FC-1FF Mac Load PCI Addr */
+};
+
+/*
+ * adapter defines and structures
+ */
+#define ICOM_CONTROL_START_A 0x00000008
+#define ICOM_CONTROL_STOP_A 0x00000004
+#define ICOM_CONTROL_START_B 0x00000002
+#define ICOM_CONTROL_STOP_B 0x00000001
+#define ICOM_CONTROL_START_C 0x00000008
+#define ICOM_CONTROL_STOP_C 0x00000004
+#define ICOM_CONTROL_START_D 0x00000002
+#define ICOM_CONTROL_STOP_D 0x00000001
+#define ICOM_IRAM_OFFSET 0x1000
+#define ICOM_IRAM_SIZE 0x0C00
+#define ICOM_DCE_IRAM_OFFSET 0x0A00
+#define ICOM_CABLE_ID_VALID 0x01
+#define ICOM_CABLE_ID_MASK 0xF0
+#define ICOM_DISABLE 0x80
+#define CMD_XMIT_RCV_ENABLE 0xC0
+#define CMD_XMIT_ENABLE 0x40
+#define CMD_RCV_DISABLE 0x00
+#define CMD_RCV_ENABLE 0x80
+#define CMD_RESTART 0x01
+#define CMD_HOLD_XMIT 0x02
+#define CMD_SND_BREAK 0x04
+#define RS232_CABLE 0x06
+#define V24_CABLE 0x0E
+#define V35_CABLE 0x0C
+#define V36_CABLE 0x02
+#define NO_CABLE 0x00
+#define START_DOWNLOAD 0x80
+#define ICOM_INT_MASK_PRC_A 0x00003FFF
+#define ICOM_INT_MASK_PRC_B 0x3FFF0000
+#define ICOM_INT_MASK_PRC_C 0x00003FFF
+#define ICOM_INT_MASK_PRC_D 0x3FFF0000
+#define INT_RCV_COMPLETED 0x1000
+#define INT_XMIT_COMPLETED 0x2000
+#define INT_IDLE_DETECT 0x0800
+#define INT_RCV_DISABLED 0x0400
+#define INT_XMIT_DISABLED 0x0200
+#define INT_RCV_XMIT_SHUTDOWN 0x0100
+#define INT_FATAL_ERROR 0x0080
+#define INT_CABLE_PULL 0x0020
+#define INT_SIGNAL_CHANGE 0x0010
+#define HDLC_PPP_PURE_ASYNC 0x02
+#define HDLC_FF_FILL 0x00
+#define HDLC_HDW_FLOW 0x01
+#define START_XMIT 0x80
+#define ICOM_ACFG_DRIVE1 0x20
+#define ICOM_ACFG_NO_PARITY 0x00
+#define ICOM_ACFG_PARITY_ENAB 0x02
+#define ICOM_ACFG_PARITY_ODD 0x01
+#define ICOM_ACFG_8BPC 0x00
+#define ICOM_ACFG_7BPC 0x04
+#define ICOM_ACFG_6BPC 0x08
+#define ICOM_ACFG_5BPC 0x0C
+#define ICOM_ACFG_1STOP_BIT 0x00
+#define ICOM_ACFG_2STOP_BIT 0x10
+#define ICOM_DTR 0x80
+#define ICOM_RTS 0x40
+#define ICOM_RI 0x08
+#define ICOM_DSR 0x80
+#define ICOM_DCD 0x20
+#define ICOM_CTS 0x40
+
+#define NUM_XBUFFS 1
+#define NUM_RBUFFS 2
+#define RCV_BUFF_SZ 0x0200
+#define XMIT_BUFF_SZ 0x1000
+struct statusArea {
+ /**********************************************/
+ /* Transmit Status Area */
+ /**********************************************/
+ struct xmit_status_area{
+ u32 leNext; /* Next entry in Little Endian on Adapter */
+ u32 leNextASD;
+ u32 leBuffer; /* Buffer for entry in LE for Adapter */
+ u16 leLengthASD;
+ u16 leOffsetASD;
+ u16 leLength; /* Length of data in segment */
+ u16 flags;
+#define SA_FLAGS_DONE 0x0080 /* Done with Segment */
+#define SA_FLAGS_CONTINUED 0x8000 /* More Segments */
+#define SA_FLAGS_IDLE 0x4000 /* Mark IDLE after frm */
+#define SA_FLAGS_READY_TO_XMIT 0x0800
+#define SA_FLAGS_STAT_MASK 0x007F
+ } xmit[NUM_XBUFFS];
+
+ /**********************************************/
+ /* Receive Status Area */
+ /**********************************************/
+ struct {
+ u32 leNext; /* Next entry in Little Endian on Adapter */
+ u32 leNextASD;
+ u32 leBuffer; /* Buffer for entry in LE for Adapter */
+ u16 WorkingLength; /* size of segment */
+ u16 reserv01;
+ u16 leLength; /* Length of data in segment */
+ u16 flags;
+#define SA_FL_RCV_DONE 0x0010 /* Data ready */
+#define SA_FLAGS_OVERRUN 0x0040
+#define SA_FLAGS_PARITY_ERROR 0x0080
+#define SA_FLAGS_FRAME_ERROR 0x0001
+#define SA_FLAGS_FRAME_TRUNC 0x0002
+#define SA_FLAGS_BREAK_DET 0x0004 /* set conditionally by device driver, not hardware */
+#define SA_FLAGS_RCV_MASK 0xFFE6
+ } rcv[NUM_RBUFFS];
+};
+
+struct icom_adapter;
+
+
+#define ICOM_MAJOR 243
+#define ICOM_MINOR_START 0
+
+struct icom_port {
+ struct uart_port uart_port;
+ u8 imbed_modem;
+#define ICOM_UNKNOWN 1
+#define ICOM_RVX 2
+#define ICOM_IMBED_MODEM 3
+ unsigned char cable_id;
+ unsigned char read_status_mask;
+ unsigned char ignore_status_mask;
+ unsigned long int_reg;
+ struct icom_regs *global_reg;
+ struct func_dram *dram;
+ int port;
+ struct statusArea *statStg;
+ dma_addr_t statStg_pci;
+ u32 *xmitRestart;
+ dma_addr_t xmitRestart_pci;
+ unsigned char *xmit_buf;
+ dma_addr_t xmit_buf_pci;
+ unsigned char *recv_buf;
+ dma_addr_t recv_buf_pci;
+ int next_rcv;
+ int put_length;
+ int status;
+#define ICOM_PORT_ACTIVE 1 /* Port exists. */
+#define ICOM_PORT_OFF 0 /* Port does not exist. */
+ int load_in_progress;
+ struct icom_adapter *adapter;
+};
+
+struct icom_adapter {
+ unsigned long base_addr;
+ unsigned long base_addr_pci;
+ unsigned char irq_number;
+ struct pci_dev *pci_dev;
+ struct icom_port port_info[4];
+ int index;
+ int version;
+#define ADAPTER_V1 0x0001
+#define ADAPTER_V2 0x0002
+ u32 subsystem_id;
+#define FOUR_PORT_MODEL 0x0252
+#define V2_TWO_PORTS_RVX 0x021A
+#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM 0x0251
+ int numb_ports;
+ struct list_head icom_adapter_entry;
+ struct kobject kobj;
+};
+
+/* prototype */
+extern void iCom_sercons_init(void);
+
+struct lookup_proc_table {
+ u32 *global_control_reg;
+ unsigned long processor_id;
+};
+
+struct lookup_int_table {
+ u32 *global_int_mask;
+ unsigned long processor_id;
+};
+
+#define MSECS_TO_JIFFIES(ms) (((ms)*HZ+999)/1000)
--- /dev/null
+/*
+ * drivers/usb/core/otg_whitelist.h
+ *
+ * Copyright (C) 2004 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/*
+ * This OTG Whitelist is the OTG "Targeted Peripheral List". It should
+ * mostly use of USB_DEVICE() or USB_DEVICE_VER() entries..
+ *
+ * YOU _SHOULD_ CHANGE THIS LIST TO MATCH YOUR PRODUCT AND ITS TESTING!
+ */
+
+static struct usb_device_id whitelist_table [] = {
+
+/* hubs are optional in OTG, but very handy ... */
+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
+
+#ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
+/* FIXME actually, printers are NOT supposed to use device classes;
+ * they're supposed to use interface classes...
+ */
+{ USB_DEVICE_INFO(7, 1, 1) },
+{ USB_DEVICE_INFO(7, 1, 2) },
+{ USB_DEVICE_INFO(7, 1, 3) },
+#endif
+
+#ifdef CONFIG_USB_CDCETHER
+/* Linux-USB CDC Ethernet gadget */
+{ USB_DEVICE(0x0525, 0xa4a1), },
+/* Linux-USB CDC Ethernet + RNDIS gadget */
+{ USB_DEVICE(0x0525, 0xa4a2), },
+#endif
+
+#if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
+/* gadget zero, for testing */
+{ USB_DEVICE(0x0525, 0xa4a0), },
+#endif
+
+{ } /* Terminating entry */
+};
+
+static int is_targeted(struct usb_device *dev)
+{
+ struct usb_device_id *id = whitelist_table;
+
+ /* possible in developer configs only! */
+ if (!dev->bus->otg_port)
+ return 1;
+
+ /* HNP test device is _never_ targeted (see OTG spec 6.6.6) */
+ if (dev->descriptor.idVendor == 0x1a0a
+ && dev->descriptor.idProduct == 0xbadd)
+ return 0;
+
+ /* NOTE: can't use usb_match_id() since interface caches
+ * aren't set up yet. this is cut/paste from that code.
+ */
+ for (id = whitelist_table; id->match_flags; id++) {
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
+ id->idVendor != dev->descriptor.idVendor)
+ continue;
+
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
+ id->idProduct != dev->descriptor.idProduct)
+ continue;
+
+ /* No need to test id->bcdDevice_lo != 0, since 0 is never
+ greater than any unsigned number. */
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
+ (id->bcdDevice_lo > dev->descriptor.bcdDevice))
+ continue;
+
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
+ (id->bcdDevice_hi < dev->descriptor.bcdDevice))
+ continue;
+
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
+ (id->bDeviceClass != dev->descriptor.bDeviceClass))
+ continue;
+
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
+ (id->bDeviceSubClass!= dev->descriptor.bDeviceSubClass))
+ continue;
+
+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
+ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
+ continue;
+
+ return 1;
+ }
+
+ /* add other match criteria here ... */
+
+
+ /* OTG MESSAGE: report errors here, customize to match your product */
+ dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
+ dev->descriptor.idVendor,
+ dev->descriptor.idProduct);
+#ifdef CONFIG_USB_OTG_WHITELIST
+ return 0;
+#else
+ return 1;
+#endif
+}
+
--- /dev/null
+/*
+ * linux/drivers/usb/gadget/lh7a40x_udc.c
+ * Sharp LH7A40x on-chip full speed USB device controllers
+ *
+ * Copyright (C) 2004 Mikko Lahteenmaki, Nordic ID
+ * Copyright (C) 2004 Bo Henriksen, Nordic ID
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include "lh7a40x_udc.h"
+
+//#define DEBUG printk
+//#define DEBUG_EP0 printk
+//#define DEBUG_SETUP printk
+
+#ifndef DEBUG_EP0
+# define DEBUG_EP0(fmt,args...)
+#endif
+#ifndef DEBUG_SETUP
+# define DEBUG_SETUP(fmt,args...)
+#endif
+#ifndef DEBUG
+# define NO_STATES
+# define DEBUG(fmt,args...)
+#endif
+
+#define DRIVER_DESC "LH7A40x USB Device Controller"
+#define DRIVER_VERSION __DATE__
+
+#ifndef _BIT /* FIXME - what happended to _BIT in 2.6.7bk18? */
+#define _BIT(x) (1<<(x))
+#endif
+
+struct lh7a40x_udc *the_controller;
+
+static const char driver_name[] = "lh7a40x_udc";
+static const char driver_desc[] = DRIVER_DESC;
+static const char ep0name[] = "ep0-control";
+
+/*
+ Local definintions.
+*/
+#define UDC_PROC_FILE
+
+#ifndef NO_STATES
+static char *state_names[] = {
+ "WAIT_FOR_SETUP",
+ "DATA_STATE_XMIT",
+ "DATA_STATE_NEED_ZLP",
+ "WAIT_FOR_OUT_STATUS",
+ "DATA_STATE_RECV"
+};
+#endif
+
+/*
+ Local declarations.
+*/
+static int lh7a40x_ep_enable(struct usb_ep *ep,
+ const struct usb_endpoint_descriptor *);
+static int lh7a40x_ep_disable(struct usb_ep *ep);
+static struct usb_request *lh7a40x_alloc_request(struct usb_ep *ep, int);
+static void lh7a40x_free_request(struct usb_ep *ep, struct usb_request *);
+static void *lh7a40x_alloc_buffer(struct usb_ep *ep, unsigned, dma_addr_t *,
+ int);
+static void lh7a40x_free_buffer(struct usb_ep *ep, void *, dma_addr_t,
+ unsigned);
+static int lh7a40x_queue(struct usb_ep *ep, struct usb_request *, int);
+static int lh7a40x_dequeue(struct usb_ep *ep, struct usb_request *);
+static int lh7a40x_set_halt(struct usb_ep *ep, int);
+static int lh7a40x_fifo_status(struct usb_ep *ep);
+static int lh7a40x_fifo_status(struct usb_ep *ep);
+static void lh7a40x_fifo_flush(struct usb_ep *ep);
+static void lh7a40x_ep0_kick(struct lh7a40x_udc *dev, struct lh7a40x_ep *ep);
+static void lh7a40x_handle_ep0(struct lh7a40x_udc *dev, u32 intr);
+
+static void done(struct lh7a40x_ep *ep, struct lh7a40x_request *req,
+ int status);
+static void pio_irq_enable(int bEndpointAddress);
+static void pio_irq_disable(int bEndpointAddress);
+static void stop_activity(struct lh7a40x_udc *dev,
+ struct usb_gadget_driver *driver);
+static void flush(struct lh7a40x_ep *ep);
+static void udc_enable(struct lh7a40x_udc *dev);
+static void udc_set_address(struct lh7a40x_udc *dev, unsigned char address);
+
+static struct usb_ep_ops lh7a40x_ep_ops = {
+ .enable = lh7a40x_ep_enable,
+ .disable = lh7a40x_ep_disable,
+
+ .alloc_request = lh7a40x_alloc_request,
+ .free_request = lh7a40x_free_request,
+
+ .alloc_buffer = lh7a40x_alloc_buffer,
+ .free_buffer = lh7a40x_free_buffer,
+
+ .queue = lh7a40x_queue,
+ .dequeue = lh7a40x_dequeue,
+
+ .set_halt = lh7a40x_set_halt,
+ .fifo_status = lh7a40x_fifo_status,
+ .fifo_flush = lh7a40x_fifo_flush,
+};
+
+/* Inline code */
+
+static __inline__ int write_packet(struct lh7a40x_ep *ep,
+ struct lh7a40x_request *req, int max)
+{
+ u8 *buf;
+ int length, count;
+ volatile u32 *fifo = (volatile u32 *)ep->fifo;
+
+ buf = req->req.buf + req->req.actual;
+ prefetch(buf);
+
+ length = req->req.length - req->req.actual;
+ length = min(length, max);
+ req->req.actual += length;
+
+ DEBUG("Write %d (max %d), fifo %p\n", length, max, fifo);
+
+ count = length;
+ while (count--) {
+ *fifo = *buf++;
+ }
+
+ return length;
+}
+
+static __inline__ void usb_set_index(u32 ep)
+{
+ *(volatile u32 *)io_p2v(USB_INDEX) = ep;
+}
+
+static __inline__ u32 usb_read(u32 port)
+{
+ return *(volatile u32 *)io_p2v(port);
+}
+
+static __inline__ void usb_write(u32 val, u32 port)
+{
+ *(volatile u32 *)io_p2v(port) = val;
+}
+
+static __inline__ void usb_set(u32 val, u32 port)
+{
+ volatile u32 *ioport = (volatile u32 *)io_p2v(port);
+ u32 after = (*ioport) | val;
+ *ioport = after;
+}
+
+static __inline__ void usb_clear(u32 val, u32 port)
+{
+ volatile u32 *ioport = (volatile u32 *)io_p2v(port);
+ u32 after = (*ioport) & ~val;
+ *ioport = after;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define GPIO_PORTC_DR (0x80000E08)
+#define GPIO_PORTC_DDR (0x80000E18)
+#define GPIO_PORTC_PDR (0x80000E70)
+
+/* get port C pin data register */
+#define get_portc_pdr(bit) ((usb_read(GPIO_PORTC_PDR) & _BIT(bit)) != 0)
+/* get port C data direction register */
+#define get_portc_ddr(bit) ((usb_read(GPIO_PORTC_DDR) & _BIT(bit)) != 0)
+/* set port C data register */
+#define set_portc_dr(bit, val) (val ? usb_set(_BIT(bit), GPIO_PORTC_DR) : usb_clear(_BIT(bit), GPIO_PORTC_DR))
+/* set port C data direction register */
+#define set_portc_ddr(bit, val) (val ? usb_set(_BIT(bit), GPIO_PORTC_DDR) : usb_clear(_BIT(bit), GPIO_PORTC_DDR))
+
+/*
+ * LPD7A404 GPIO's:
+ * Port C bit 1 = USB Port 1 Power Enable
+ * Port C bit 2 = USB Port 1 Data Carrier Detect
+ */
+#define is_usb_connected() get_portc_pdr(2)
+
+#ifdef UDC_PROC_FILE
+
+static const char proc_node_name[] = "driver/udc";
+
+static int
+udc_proc_read(char *page, char **start, off_t off, int count,
+ int *eof, void *_dev)
+{
+ char *buf = page;
+ struct lh7a40x_udc *dev = _dev;
+ char *next = buf;
+ unsigned size = count;
+ unsigned long flags;
+ int t;
+
+ if (off != 0)
+ return 0;
+
+ local_irq_save(flags);
+
+ /* basic device status */
+ t = scnprintf(next, size,
+ DRIVER_DESC "\n"
+ "%s version: %s\n"
+ "Gadget driver: %s\n"
+ "Host: %s\n\n",
+ driver_name, DRIVER_VERSION,
+ dev->driver ? dev->driver->driver.name : "(none)",
+ is_usb_connected()? "full speed" : "disconnected");
+ size -= t;
+ next += t;
+
+ t = scnprintf(next, size,
+ "GPIO:\n"
+ " Port C bit 1: %d, dir %d\n"
+ " Port C bit 2: %d, dir %d\n\n",
+ get_portc_pdr(1), get_portc_ddr(1),
+ get_portc_pdr(2), get_portc_ddr(2)
+ );
+ size -= t;
+ next += t;
+
+ t = scnprintf(next, size,
+ "DCP pullup: %d\n\n",
+ (usb_read(USB_PM) & PM_USB_DCP) != 0);
+ size -= t;
+ next += t;
+
+ local_irq_restore(flags);
+ *eof = 1;
+ return count - size;
+}
+
+#define create_proc_files() create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
+#define remove_proc_files() remove_proc_entry(proc_node_name, NULL)
+
+#else /* !UDC_PROC_FILE */
+
+#define create_proc_files() do {} while (0)
+#define remove_proc_files() do {} while (0)
+
+#endif /* UDC_PROC_FILE */
+
+/*
+ * udc_disable - disable USB device controller
+ */
+static void udc_disable(struct lh7a40x_udc *dev)
+{
+ DEBUG("%s, %p\n", __FUNCTION__, dev);
+
+ udc_set_address(dev, 0);
+
+ /* Disable interrupts */
+ usb_write(0, USB_IN_INT_EN);
+ usb_write(0, USB_OUT_INT_EN);
+ usb_write(0, USB_INT_EN);
+
+ /* Disable the USB */
+ usb_write(0, USB_PM);
+
+#ifdef CONFIG_ARCH_LH7A404
+ /* Disable USB power */
+ set_portc_dr(1, 0);
+#endif
+
+ /* if hardware supports it, disconnect from usb */
+ /* make_usb_disappear(); */
+
+ dev->ep0state = WAIT_FOR_SETUP;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ dev->usb_address = 0;
+}
+
+/*
+ * udc_reinit - initialize software state
+ */
+static void udc_reinit(struct lh7a40x_udc *dev)
+{
+ u32 i;
+
+ DEBUG("%s, %p\n", __FUNCTION__, dev);
+
+ /* device/ep0 records init */
+ INIT_LIST_HEAD(&dev->gadget.ep_list);
+ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
+ dev->ep0state = WAIT_FOR_SETUP;
+
+ /* basic endpoint records init */
+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
+ struct lh7a40x_ep *ep = &dev->ep[i];
+
+ if (i != 0)
+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
+
+ ep->desc = 0;
+ ep->stopped = 0;
+ INIT_LIST_HEAD(&ep->queue);
+ ep->pio_irqs = 0;
+ }
+
+ /* the rest was statically initialized, and is read-only */
+}
+
+#define BYTES2MAXP(x) (x / 8)
+#define MAXP2BYTES(x) (x * 8)
+
+/* until it's enabled, this UDC should be completely invisible
+ * to any USB host.
+ */
+static void udc_enable(struct lh7a40x_udc *dev)
+{
+ int ep;
+
+ DEBUG("%s, %p\n", __FUNCTION__, dev);
+
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+
+#ifdef CONFIG_ARCH_LH7A404
+ /* Set Port C bit 1 & 2 as output */
+ set_portc_ddr(1, 1);
+ set_portc_ddr(2, 1);
+
+ /* Enable USB power */
+ set_portc_dr(1, 0);
+#endif
+
+ /*
+ * C.f Chapter 18.1.3.1 Initializing the USB
+ */
+
+ /* Disable the USB */
+ usb_clear(PM_USB_ENABLE, USB_PM);
+
+ /* Reset APB & I/O sides of the USB */
+ usb_set(USB_RESET_APB | USB_RESET_IO, USB_RESET);
+ mdelay(5);
+ usb_clear(USB_RESET_APB | USB_RESET_IO, USB_RESET);
+
+ /* Set MAXP values for each */
+ for (ep = 0; ep < UDC_MAX_ENDPOINTS; ep++) {
+ struct lh7a40x_ep *ep_reg = &dev->ep[ep];
+ u32 csr;
+
+ usb_set_index(ep);
+
+ switch (ep_reg->ep_type) {
+ case ep_bulk_in:
+ case ep_interrupt:
+ usb_clear(USB_IN_CSR2_USB_DMA_EN | USB_IN_CSR2_AUTO_SET,
+ ep_reg->csr2);
+ /* Fall through */
+ case ep_control:
+ usb_write(BYTES2MAXP(ep_maxpacket(ep_reg)),
+ USB_IN_MAXP);
+ break;
+ case ep_bulk_out:
+ usb_clear(USB_OUT_CSR2_USB_DMA_EN |
+ USB_OUT_CSR2_AUTO_CLR, ep_reg->csr2);
+ usb_write(BYTES2MAXP(ep_maxpacket(ep_reg)),
+ USB_OUT_MAXP);
+ break;
+ }
+
+ /* Read & Write CSR1, just in case */
+ csr = usb_read(ep_reg->csr1);
+ usb_write(csr, ep_reg->csr1);
+
+ flush(ep_reg);
+ }
+
+ /* Disable interrupts */
+ usb_write(0, USB_IN_INT_EN);
+ usb_write(0, USB_OUT_INT_EN);
+ usb_write(0, USB_INT_EN);
+
+ /* Enable interrupts */
+ usb_set(USB_IN_INT_EP0, USB_IN_INT_EN);
+ usb_set(USB_INT_RESET_INT | USB_INT_RESUME_INT, USB_INT_EN);
+ /* Dont enable rest of the interrupts */
+ /* usb_set(USB_IN_INT_EP3 | USB_IN_INT_EP1 | USB_IN_INT_EP0, USB_IN_INT_EN);
+ usb_set(USB_OUT_INT_EP2, USB_OUT_INT_EN); */
+
+ /* Enable SUSPEND */
+ usb_set(PM_ENABLE_SUSPEND, USB_PM);
+
+ /* Enable the USB */
+ usb_set(PM_USB_ENABLE, USB_PM);
+
+#ifdef CONFIG_ARCH_LH7A404
+ /* NOTE: DOES NOT WORK! */
+ /* Let host detect UDC:
+ * Software must write a 0 to the PMR:DCP_CTRL bit to turn this
+ * transistor on and pull the USBDP pin HIGH.
+ */
+ /* usb_clear(PM_USB_DCP, USB_PM);
+ usb_set(PM_USB_DCP, USB_PM); */
+#endif
+}
+
+/*
+ Register entry point for the peripheral controller driver.
+*/
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct lh7a40x_udc *dev = the_controller;
+ int retval;
+
+ DEBUG("%s: %s\n", __FUNCTION__, driver->driver.name);
+
+ if (!driver
+ || driver->speed != USB_SPEED_FULL
+ || !driver->bind
+ || !driver->unbind || !driver->disconnect || !driver->setup)
+ return -EINVAL;
+ if (!dev)
+ return -ENODEV;
+ if (dev->driver)
+ return -EBUSY;
+
+ /* first hook up the driver ... */
+ dev->driver = driver;
+ dev->gadget.dev.driver = &driver->driver;
+
+ device_add(&dev->gadget.dev);
+ retval = driver->bind(&dev->gadget);
+ if (retval) {
+ printk("%s: bind to driver %s --> error %d\n", dev->gadget.name,
+ driver->driver.name, retval);
+ device_del(&dev->gadget.dev);
+
+ dev->driver = 0;
+ dev->gadget.dev.driver = 0;
+ return retval;
+ }
+
+ /* ... then enable host detection and ep0; and we're ready
+ * for set_configuration as well as eventual disconnect.
+ * NOTE: this shouldn't power up until later.
+ */
+ printk("%s: registered gadget driver '%s'\n", dev->gadget.name,
+ driver->driver.name);
+
+ udc_enable(dev);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+/*
+ Unregister entry point for the peripheral controller driver.
+*/
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct lh7a40x_udc *dev = the_controller;
+ unsigned long flags;
+
+ if (!dev)
+ return -ENODEV;
+ if (!driver || driver != dev->driver)
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev->lock, flags);
+ dev->driver = 0;
+ stop_activity(dev, driver);
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ driver->unbind(&dev->gadget);
+ device_del(&dev->gadget.dev);
+
+ udc_disable(dev);
+
+ DEBUG("unregistered gadget driver '%s'\n", driver->driver.name);
+ return 0;
+}
+
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+/*-------------------------------------------------------------------------*/
+
+/** Write request to FIFO (max write == maxp size)
+ * Return: 0 = still running, 1 = completed, negative = errno
+ * NOTE: INDEX register must be set for EP
+ */
+static int write_fifo(struct lh7a40x_ep *ep, struct lh7a40x_request *req)
+{
+ u32 max;
+ u32 csr;
+
+ max = le16_to_cpu(ep->desc->wMaxPacketSize);
+
+ csr = usb_read(ep->csr1);
+ DEBUG("CSR: %x %d\n", csr, csr & USB_IN_CSR1_FIFO_NOT_EMPTY);
+
+ if (!(csr & USB_IN_CSR1_FIFO_NOT_EMPTY)) {
+ unsigned count;
+ int is_last, is_short;
+
+ count = write_packet(ep, req, max);
+ usb_set(USB_IN_CSR1_IN_PKT_RDY, ep->csr1);
+
+ /* last packet is usually short (or a zlp) */
+ if (unlikely(count != max))
+ is_last = is_short = 1;
+ else {
+ if (likely(req->req.length != req->req.actual)
+ || req->req.zero)
+ is_last = 0;
+ else
+ is_last = 1;
+ /* interrupt/iso maxpacket may not fill the fifo */
+ is_short = unlikely(max < ep_maxpacket(ep));
+ }
+
+ DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
+ ep->ep.name, count,
+ is_last ? "/L" : "", is_short ? "/S" : "",
+ req->req.length - req->req.actual, req);
+
+ /* requests complete when all IN data is in the FIFO */
+ if (is_last) {
+ done(ep, req, 0);
+ if (list_empty(&ep->queue)) {
+ pio_irq_disable(ep_index(ep));
+ }
+ return 1;
+ }
+ } else {
+ DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
+ }
+
+ return 0;
+}
+
+/** Read to request from FIFO (max read == bytes in fifo)
+ * Return: 0 = still running, 1 = completed, negative = errno
+ * NOTE: INDEX register must be set for EP
+ */
+static int read_fifo(struct lh7a40x_ep *ep, struct lh7a40x_request *req)
+{
+ u32 csr;
+ u8 *buf;
+ unsigned bufferspace, count, is_short;
+ volatile u32 *fifo = (volatile u32 *)ep->fifo;
+
+ /* make sure there's a packet in the FIFO. */
+ csr = usb_read(ep->csr1);
+ if (!(csr & USB_OUT_CSR1_OUT_PKT_RDY)) {
+ DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+ bufferspace = req->req.length - req->req.actual;
+
+ /* read all bytes from this packet */
+ count = usb_read(USB_OUT_FIFO_WC1);
+ req->req.actual += min(count, bufferspace);
+
+ is_short = (count < ep->ep.maxpacket);
+ DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
+ ep->ep.name, csr, count,
+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
+
+ while (likely(count-- != 0)) {
+ u8 byte = (u8) (*fifo & 0xff);
+
+ if (unlikely(bufferspace == 0)) {
+ /* this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ printk("%s overflow %d\n", ep->ep.name, count);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ bufferspace--;
+ }
+ }
+
+ usb_clear(USB_OUT_CSR1_OUT_PKT_RDY, ep->csr1);
+
+ /* completion */
+ if (is_short || req->req.actual == req->req.length) {
+ done(ep, req, 0);
+ usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1);
+
+ if (list_empty(&ep->queue))
+ pio_irq_disable(ep_index(ep));
+ return 1;
+ }
+
+ /* finished that packet. the next one may be waiting... */
+ return 0;
+}
+
+/*
+ * done - retire a request; caller blocked irqs
+ * INDEX register is preserved to keep same
+ */
+static void done(struct lh7a40x_ep *ep, struct lh7a40x_request *req, int status)
+{
+ unsigned int stopped = ep->stopped;
+ u32 index;
+
+ DEBUG("%s, %p\n", __FUNCTION__, ep);
+ list_del_init(&req->queue);
+
+ if (likely(req->req.status == -EINPROGRESS))
+ req->req.status = status;
+ else
+ status = req->req.status;
+
+ if (status && status != -ESHUTDOWN)
+ DEBUG("complete %s req %p stat %d len %u/%u\n",
+ ep->ep.name, &req->req, status,
+ req->req.actual, req->req.length);
+
+ /* don't modify queue heads during completion callback */
+ ep->stopped = 1;
+ /* Read current index (completion may modify it) */
+ index = usb_read(USB_INDEX);
+
+ spin_unlock(&ep->dev->lock);
+ req->req.complete(&ep->ep, &req->req);
+ spin_lock(&ep->dev->lock);
+
+ /* Restore index */
+ usb_set_index(index);
+ ep->stopped = stopped;
+}
+
+/** Enable EP interrupt */
+static void pio_irq_enable(int ep)
+{
+ DEBUG("%s: %d\n", __FUNCTION__, ep);
+
+ switch (ep) {
+ case 1:
+ usb_set(USB_IN_INT_EP1, USB_IN_INT_EN);
+ break;
+ case 2:
+ usb_set(USB_OUT_INT_EP2, USB_OUT_INT_EN);
+ break;
+ case 3:
+ usb_set(USB_IN_INT_EP3, USB_IN_INT_EN);
+ break;
+ default:
+ DEBUG("Unknown endpoint: %d\n", ep);
+ break;
+ }
+}
+
+/** Disable EP interrupt */
+static void pio_irq_disable(int ep)
+{
+ DEBUG("%s: %d\n", __FUNCTION__, ep);
+
+ switch (ep) {
+ case 1:
+ usb_clear(USB_IN_INT_EP1, USB_IN_INT_EN);
+ break;
+ case 2:
+ usb_clear(USB_OUT_INT_EP2, USB_OUT_INT_EN);
+ break;
+ case 3:
+ usb_clear(USB_IN_INT_EP3, USB_IN_INT_EN);
+ break;
+ default:
+ DEBUG("Unknown endpoint: %d\n", ep);
+ break;
+ }
+}
+
+/*
+ * nuke - dequeue ALL requests
+ */
+void nuke(struct lh7a40x_ep *ep, int status)
+{
+ struct lh7a40x_request *req;
+
+ DEBUG("%s, %p\n", __FUNCTION__, ep);
+
+ /* Flush FIFO */
+ flush(ep);
+
+ /* called with irqs blocked */
+ while (!list_empty(&ep->queue)) {
+ req = list_entry(ep->queue.next, struct lh7a40x_request, queue);
+ done(ep, req, status);
+ }
+
+ /* Disable IRQ if EP is enabled (has decriptor) */
+ if (ep->desc)
+ pio_irq_disable(ep_index(ep));
+}
+
+/*
+void nuke_all(struct lh7a40x_udc *dev)
+{
+ int n;
+ for(n=0; n<UDC_MAX_ENDPOINTS; n++) {
+ struct lh7a40x_ep *ep = &dev->ep[n];
+ usb_set_index(n);
+ nuke(ep, 0);
+ }
+}*/
+
+/*
+static void flush_all(struct lh7a40x_udc *dev)
+{
+ int n;
+ for (n = 0; n < UDC_MAX_ENDPOINTS; n++)
+ {
+ struct lh7a40x_ep *ep = &dev->ep[n];
+ flush(ep);
+ }
+}
+*/
+
+/** Flush EP
+ * NOTE: INDEX register must be set before this call
+ */
+static void flush(struct lh7a40x_ep *ep)
+{
+ DEBUG("%s, %p\n", __FUNCTION__, ep);
+
+ switch (ep->ep_type) {
+ case ep_control:
+ /* check, by implication c.f. 15.1.2.11 */
+ break;
+
+ case ep_bulk_in:
+ case ep_interrupt:
+ /* if(csr & USB_IN_CSR1_IN_PKT_RDY) */
+ usb_set(USB_IN_CSR1_FIFO_FLUSH, ep->csr1);
+ break;
+
+ case ep_bulk_out:
+ /* if(csr & USB_OUT_CSR1_OUT_PKT_RDY) */
+ usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1);
+ break;
+ }
+}
+
+/**
+ * lh7a40x_in_epn - handle IN interrupt
+ */
+static void lh7a40x_in_epn(struct lh7a40x_udc *dev, u32 ep_idx, u32 intr)
+{
+ u32 csr;
+ struct lh7a40x_ep *ep = &dev->ep[ep_idx];
+ struct lh7a40x_request *req;
+
+ usb_set_index(ep_idx);
+
+ csr = usb_read(ep->csr1);
+ DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
+
+ if (csr & USB_IN_CSR1_SENT_STALL) {
+ DEBUG("USB_IN_CSR1_SENT_STALL\n");
+ usb_set(USB_IN_CSR1_SENT_STALL /*|USB_IN_CSR1_SEND_STALL */ ,
+ ep->csr1);
+ return;
+ }
+
+ if (!ep->desc) {
+ DEBUG("%s: NO EP DESC\n", __FUNCTION__);
+ return;
+ }
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct lh7a40x_request, queue);
+
+ DEBUG("req: %p\n", req);
+
+ if (!req)
+ return;
+
+ write_fifo(ep, req);
+}
+
+/* ********************************************************************************************* */
+/* Bulk OUT (recv)
+ */
+
+static void lh7a40x_out_epn(struct lh7a40x_udc *dev, u32 ep_idx, u32 intr)
+{
+ struct lh7a40x_ep *ep = &dev->ep[ep_idx];
+ struct lh7a40x_request *req;
+
+ DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
+
+ usb_set_index(ep_idx);
+
+ if (ep->desc) {
+ u32 csr;
+ csr = usb_read(ep->csr1);
+
+ while ((csr =
+ usb_read(ep->
+ csr1)) & (USB_OUT_CSR1_OUT_PKT_RDY |
+ USB_OUT_CSR1_SENT_STALL)) {
+ DEBUG("%s: %x\n", __FUNCTION__, csr);
+
+ if (csr & USB_OUT_CSR1_SENT_STALL) {
+ DEBUG("%s: stall sent, flush fifo\n",
+ __FUNCTION__);
+ /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
+ flush(ep);
+ } else if (csr & USB_OUT_CSR1_OUT_PKT_RDY) {
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req =
+ list_entry(ep->queue.next,
+ struct lh7a40x_request,
+ queue);
+
+ if (!req) {
+ printk("%s: NULL REQ %d\n",
+ __FUNCTION__, ep_idx);
+ flush(ep);
+ break;
+ } else {
+ read_fifo(ep, req);
+ }
+ }
+
+ }
+
+ } else {
+ /* Throw packet away.. */
+ printk("%s: No descriptor?!?\n", __FUNCTION__);
+ flush(ep);
+ }
+}
+
+static void stop_activity(struct lh7a40x_udc *dev,
+ struct usb_gadget_driver *driver)
+{
+ int i;
+
+ /* don't disconnect drivers more than once */
+ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
+ driver = 0;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+
+ /* prevent new request submissions, kill any outstanding requests */
+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
+ struct lh7a40x_ep *ep = &dev->ep[i];
+ ep->stopped = 1;
+
+ usb_set_index(i);
+ nuke(ep, -ESHUTDOWN);
+ }
+
+ /* report disconnect; the driver is already quiesced */
+ if (driver) {
+ spin_unlock(&dev->lock);
+ driver->disconnect(&dev->gadget);
+ spin_lock(&dev->lock);
+ }
+
+ /* re-init driver-visible data structures */
+ udc_reinit(dev);
+}
+
+/** Handle USB RESET interrupt
+ */
+static void lh7a40x_reset_intr(struct lh7a40x_udc *dev)
+{
+#if 0 /* def CONFIG_ARCH_LH7A404 */
+ /* Does not work always... */
+
+ DEBUG("%s: %d\n", __FUNCTION__, dev->usb_address);
+
+ if (!dev->usb_address) {
+ /*usb_set(USB_RESET_IO, USB_RESET);
+ mdelay(5);
+ usb_clear(USB_RESET_IO, USB_RESET); */
+ return;
+ }
+ /* Put the USB controller into reset. */
+ usb_set(USB_RESET_IO, USB_RESET);
+
+ /* Set Device ID to 0 */
+ udc_set_address(dev, 0);
+
+ /* Let PLL2 settle down */
+ mdelay(5);
+
+ /* Release the USB controller from reset */
+ usb_clear(USB_RESET_IO, USB_RESET);
+
+ /* Re-enable UDC */
+ udc_enable(dev);
+
+#endif
+ dev->gadget.speed = USB_SPEED_FULL;
+}
+
+/*
+ * lh7a40x usb client interrupt handler.
+ */
+static irqreturn_t lh7a40x_udc_irq(int irq, void *_dev, struct pt_regs *r)
+{
+ struct lh7a40x_udc *dev = _dev;
+
+ DEBUG("\n\n");
+
+ spin_lock(&dev->lock);
+
+ for (;;) {
+ u32 intr_in = usb_read(USB_IN_INT);
+ u32 intr_out = usb_read(USB_OUT_INT);
+ u32 intr_int = usb_read(USB_INT);
+
+ /* Test also against enable bits.. (lh7a40x errata).. Sigh.. */
+ u32 in_en = usb_read(USB_IN_INT_EN);
+ u32 out_en = usb_read(USB_OUT_INT_EN);
+
+ if (!intr_out && !intr_in && !intr_int)
+ break;
+
+ DEBUG("%s (on state %s)\n", __FUNCTION__,
+ state_names[dev->ep0state]);
+ DEBUG("intr_out = %x\n", intr_out);
+ DEBUG("intr_in = %x\n", intr_in);
+ DEBUG("intr_int = %x\n", intr_int);
+
+ if (intr_in) {
+ usb_write(intr_in, USB_IN_INT);
+
+ if ((intr_in & USB_IN_INT_EP1)
+ && (in_en & USB_IN_INT_EP1)) {
+ DEBUG("USB_IN_INT_EP1\n");
+ lh7a40x_in_epn(dev, 1, intr_in);
+ }
+ if ((intr_in & USB_IN_INT_EP3)
+ && (in_en & USB_IN_INT_EP3)) {
+ DEBUG("USB_IN_INT_EP3\n");
+ lh7a40x_in_epn(dev, 3, intr_in);
+ }
+ if (intr_in & USB_IN_INT_EP0) {
+ DEBUG("USB_IN_INT_EP0 (control)\n");
+ lh7a40x_handle_ep0(dev, intr_in);
+ }
+ }
+
+ if (intr_out) {
+ usb_write(intr_out, USB_OUT_INT);
+
+ if ((intr_out & USB_OUT_INT_EP2)
+ && (out_en & USB_OUT_INT_EP2)) {
+ DEBUG("USB_OUT_INT_EP2\n");
+ lh7a40x_out_epn(dev, 2, intr_out);
+ }
+ }
+
+ if (intr_int) {
+ usb_write(intr_int, USB_INT);
+
+ if (intr_int & USB_INT_RESET_INT) {
+ lh7a40x_reset_intr(dev);
+ }
+
+ if (intr_int & USB_INT_RESUME_INT) {
+ DEBUG("USB resume\n");
+
+ if (dev->gadget.speed != USB_SPEED_UNKNOWN
+ && dev->driver
+ && dev->driver->resume
+ && is_usb_connected()) {
+ dev->driver->resume(&dev->gadget);
+ }
+ }
+
+ if (intr_int & USB_INT_SUSPEND_INT) {
+ DEBUG("USB suspend%s\n",
+ is_usb_connected()? "" : "+disconnect");
+ if (!is_usb_connected()) {
+ stop_activity(dev, dev->driver);
+ } else if (dev->gadget.speed !=
+ USB_SPEED_UNKNOWN && dev->driver
+ && dev->driver->suspend) {
+ dev->driver->suspend(&dev->gadget);
+ }
+ }
+
+ }
+ }
+
+ spin_unlock(&dev->lock);
+
+ return IRQ_HANDLED;
+}
+
+static int lh7a40x_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct lh7a40x_ep *ep;
+ struct lh7a40x_udc *dev;
+ unsigned long flags;
+
+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (!_ep || !desc || ep->desc || _ep->name == ep0name
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || ep->bEndpointAddress != desc->bEndpointAddress
+ || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
+ DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ /* xfer types must match, except that interrupt ~= bulk */
+ if (ep->bmAttributes != desc->bmAttributes
+ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
+ DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
+ return -EINVAL;
+ }
+
+ /* hardware _could_ do smaller, but driver doesn't */
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
+ || !desc->wMaxPacketSize) {
+ DEBUG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
+ return -ERANGE;
+ }
+
+ dev = ep->dev;
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+ DEBUG("%s, bogus device state\n", __FUNCTION__);
+ return -ESHUTDOWN;
+ }
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ ep->stopped = 0;
+ ep->desc = desc;
+ ep->pio_irqs = 0;
+ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+
+ /* Reset halt state (does flush) */
+ lh7a40x_set_halt(_ep, 0);
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+
+ DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
+ return 0;
+}
+
+/** Disable EP
+ * NOTE: Sets INDEX register
+ */
+static int lh7a40x_ep_disable(struct usb_ep *_ep)
+{
+ struct lh7a40x_ep *ep;
+ unsigned long flags;
+
+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (!_ep || !ep->desc) {
+ DEBUG("%s, %s not enabled\n", __FUNCTION__,
+ _ep ? ep->ep.name : NULL);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ usb_set_index(ep_index(ep));
+
+ /* Nuke all pending requests (does flush) */
+ nuke(ep, -ESHUTDOWN);
+
+ /* Disable ep IRQ */
+ pio_irq_disable(ep_index(ep));
+
+ ep->desc = 0;
+ ep->stopped = 1;
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+
+ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
+ return 0;
+}
+
+static struct usb_request *lh7a40x_alloc_request(struct usb_ep *ep,
+ int gfp_flags)
+{
+ struct lh7a40x_request *req;
+
+ DEBUG("%s, %p\n", __FUNCTION__, ep);
+
+ req = kmalloc(sizeof *req, gfp_flags);
+ if (!req)
+ return 0;
+
+ memset(req, 0, sizeof *req);
+ INIT_LIST_HEAD(&req->queue);
+
+ return &req->req;
+}
+
+static void lh7a40x_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+ struct lh7a40x_request *req;
+
+ DEBUG("%s, %p\n", __FUNCTION__, ep);
+
+ req = container_of(_req, struct lh7a40x_request, req);
+ WARN_ON(!list_empty(&req->queue));
+ kfree(req);
+}
+
+static void *lh7a40x_alloc_buffer(struct usb_ep *ep, unsigned bytes,
+ dma_addr_t * dma, int gfp_flags)
+{
+ char *retval;
+
+ DEBUG("%s (%p, %d, %d)\n", __FUNCTION__, ep, bytes, gfp_flags);
+
+ retval = kmalloc(bytes, gfp_flags & ~(__GFP_DMA | __GFP_HIGHMEM));
+ if (retval)
+ *dma = virt_to_bus(retval);
+ return retval;
+}
+
+static void lh7a40x_free_buffer(struct usb_ep *ep, void *buf, dma_addr_t dma,
+ unsigned bytes)
+{
+ DEBUG("%s, %p\n", __FUNCTION__, ep);
+ kfree(buf);
+}
+
+/** Queue one request
+ * Kickstart transfer if needed
+ * NOTE: Sets INDEX register
+ */
+static int lh7a40x_queue(struct usb_ep *_ep, struct usb_request *_req,
+ int gfp_flags)
+{
+ struct lh7a40x_request *req;
+ struct lh7a40x_ep *ep;
+ struct lh7a40x_udc *dev;
+ unsigned long flags;
+
+ DEBUG("\n\n\n%s, %p\n", __FUNCTION__, _ep);
+
+ req = container_of(_req, struct lh7a40x_request, req);
+ if (unlikely
+ (!_req || !_req->complete || !_req->buf
+ || !list_empty(&req->queue))) {
+ DEBUG("%s, bad params\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+ DEBUG("%s, bad ep\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ dev = ep->dev;
+ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
+ DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
+ return -ESHUTDOWN;
+ }
+
+ DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
+ _req->buf);
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+
+ /* kickstart this i/o queue? */
+ DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
+ ep->stopped);
+ if (list_empty(&ep->queue) && likely(!ep->stopped)) {
+ u32 csr;
+
+ if (unlikely(ep_index(ep) == 0)) {
+ /* EP0 */
+ list_add_tail(&req->queue, &ep->queue);
+ lh7a40x_ep0_kick(dev, ep);
+ req = 0;
+ } else if (ep_is_in(ep)) {
+ /* EP1 & EP3 */
+ usb_set_index(ep_index(ep));
+ csr = usb_read(ep->csr1);
+ pio_irq_enable(ep_index(ep));
+ if ((csr & USB_IN_CSR1_FIFO_NOT_EMPTY) == 0) {
+ if (write_fifo(ep, req) == 1)
+ req = 0;
+ }
+ } else {
+ /* EP2 */
+ usb_set_index(ep_index(ep));
+ csr = usb_read(ep->csr1);
+ pio_irq_enable(ep_index(ep));
+ if (!(csr & USB_OUT_CSR1_FIFO_FULL)) {
+ if (read_fifo(ep, req) == 1)
+ req = 0;
+ }
+ }
+ }
+
+ /* pio or dma irq handler advances the queue. */
+ if (likely(req != 0))
+ list_add_tail(&req->queue, &ep->queue);
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ return 0;
+}
+
+/* dequeue JUST ONE request */
+static int lh7a40x_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct lh7a40x_ep *ep;
+ struct lh7a40x_request *req;
+ unsigned long flags;
+
+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (!_ep || ep->ep.name == ep0name)
+ return -EINVAL;
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ /* make sure it's actually queued on this endpoint */
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+ if (&req->req != _req) {
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+ return -EINVAL;
+ }
+
+ done(ep, req, -ECONNRESET);
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+ return 0;
+}
+
+/** Halt specific EP
+ * Return 0 if success
+ * NOTE: Sets INDEX register to EP !
+ */
+static int lh7a40x_set_halt(struct usb_ep *_ep, int value)
+{
+ struct lh7a40x_ep *ep;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+ DEBUG("%s, bad ep\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ usb_set_index(ep_index(ep));
+
+ DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ if (ep_index(ep) == 0) {
+ /* EP0 */
+ usb_set(EP0_SEND_STALL, ep->csr1);
+ } else if (ep_is_in(ep)) {
+ u32 csr = usb_read(ep->csr1);
+ if (value && ((csr & USB_IN_CSR1_FIFO_NOT_EMPTY)
+ || !list_empty(&ep->queue))) {
+ /*
+ * Attempts to halt IN endpoints will fail (returning -EAGAIN)
+ * if any transfer requests are still queued, or if the controller
+ * FIFO still holds bytes that the host hasn\92t collected.
+ */
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+ DEBUG
+ ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
+ (csr & USB_IN_CSR1_FIFO_NOT_EMPTY),
+ !list_empty(&ep->queue));
+ return -EAGAIN;
+ }
+ flush(ep);
+ if (value)
+ usb_set(USB_IN_CSR1_SEND_STALL, ep->csr1);
+ else {
+ usb_clear(USB_IN_CSR1_SEND_STALL, ep->csr1);
+ usb_set(USB_IN_CSR1_CLR_DATA_TOGGLE, ep->csr1);
+ }
+
+ } else {
+
+ flush(ep);
+ if (value)
+ usb_set(USB_OUT_CSR1_SEND_STALL, ep->csr1);
+ else {
+ usb_clear(USB_OUT_CSR1_SEND_STALL, ep->csr1);
+ usb_set(USB_OUT_CSR1_CLR_DATA_REG, ep->csr1);
+ }
+ }
+
+ if (value) {
+ ep->stopped = 1;
+ } else {
+ ep->stopped = 0;
+ }
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+
+ DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
+
+ return 0;
+}
+
+/** Return bytes in EP FIFO
+ * NOTE: Sets INDEX register to EP
+ */
+static int lh7a40x_fifo_status(struct usb_ep *_ep)
+{
+ u32 csr;
+ int count = 0;
+ struct lh7a40x_ep *ep;
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (!_ep) {
+ DEBUG("%s, bad ep\n", __FUNCTION__);
+ return -ENODEV;
+ }
+
+ DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
+
+ /* LPD can't report unclaimed bytes from IN fifos */
+ if (ep_is_in(ep))
+ return -EOPNOTSUPP;
+
+ usb_set_index(ep_index(ep));
+
+ csr = usb_read(ep->csr1);
+ if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
+ csr & USB_OUT_CSR1_OUT_PKT_RDY) {
+ count = usb_read(USB_OUT_FIFO_WC1);
+ }
+
+ return count;
+}
+
+/** Flush EP FIFO
+ * NOTE: Sets INDEX register to EP
+ */
+static void lh7a40x_fifo_flush(struct usb_ep *_ep)
+{
+ struct lh7a40x_ep *ep;
+
+ ep = container_of(_ep, struct lh7a40x_ep, ep);
+ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+ DEBUG("%s, bad ep\n", __FUNCTION__);
+ return;
+ }
+
+ usb_set_index(ep_index(ep));
+ flush(ep);
+}
+
+/****************************************************************/
+/* End Point 0 related functions */
+/****************************************************************/
+
+/* return: 0 = still running, 1 = completed, negative = errno */
+static int write_fifo_ep0(struct lh7a40x_ep *ep, struct lh7a40x_request *req)
+{
+ u32 max;
+ unsigned count;
+ int is_last;
+
+ max = ep_maxpacket(ep);
+
+ DEBUG_EP0("%s\n", __FUNCTION__);
+
+ count = write_packet(ep, req, max);
+
+ /* last packet is usually short (or a zlp) */
+ if (unlikely(count != max))
+ is_last = 1;
+ else {
+ if (likely(req->req.length != req->req.actual) || req->req.zero)
+ is_last = 0;
+ else
+ is_last = 1;
+ }
+
+ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
+ ep->ep.name, count,
+ is_last ? "/L" : "", req->req.length - req->req.actual, req);
+
+ /* requests complete when all IN data is in the FIFO */
+ if (is_last) {
+ done(ep, req, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+static __inline__ int lh7a40x_fifo_read(struct lh7a40x_ep *ep,
+ unsigned char *cp, int max)
+{
+ int bytes;
+ int count = usb_read(USB_OUT_FIFO_WC1);
+ volatile u32 *fifo = (volatile u32 *)ep->fifo;
+
+ if (count > max)
+ count = max;
+ bytes = count;
+ while (count--)
+ *cp++ = *fifo & 0xFF;
+ return bytes;
+}
+
+static __inline__ void lh7a40x_fifo_write(struct lh7a40x_ep *ep,
+ unsigned char *cp, int count)
+{
+ volatile u32 *fifo = (volatile u32 *)ep->fifo;
+ DEBUG_EP0("fifo_write: %d %d\n", ep_index(ep), count);
+ while (count--)
+ *fifo = *cp++;
+}
+
+static int read_fifo_ep0(struct lh7a40x_ep *ep, struct lh7a40x_request *req)
+{
+ u32 csr;
+ u8 *buf;
+ unsigned bufferspace, count, is_short;
+ volatile u32 *fifo = (volatile u32 *)ep->fifo;
+
+ DEBUG_EP0("%s\n", __FUNCTION__);
+
+ csr = usb_read(USB_EP0_CSR);
+ if (!(csr & USB_OUT_CSR1_OUT_PKT_RDY))
+ return 0;
+
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+ bufferspace = req->req.length - req->req.actual;
+
+ /* read all bytes from this packet */
+ if (likely(csr & EP0_OUT_PKT_RDY)) {
+ count = usb_read(USB_OUT_FIFO_WC1);
+ req->req.actual += min(count, bufferspace);
+ } else /* zlp */
+ count = 0;
+
+ is_short = (count < ep->ep.maxpacket);
+ DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
+ ep->ep.name, csr, count,
+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
+
+ while (likely(count-- != 0)) {
+ u8 byte = (u8) (*fifo & 0xff);
+
+ if (unlikely(bufferspace == 0)) {
+ /* this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ DEBUG_EP0("%s overflow %d\n", ep->ep.name,
+ count);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ bufferspace--;
+ }
+ }
+
+ /* completion */
+ if (is_short || req->req.actual == req->req.length) {
+ done(ep, req, 0);
+ return 1;
+ }
+
+ /* finished that packet. the next one may be waiting... */
+ return 0;
+}
+
+/**
+ * udc_set_address - set the USB address for this device
+ * @address:
+ *
+ * Called from control endpoint function after it decodes a set address setup packet.
+ */
+static void udc_set_address(struct lh7a40x_udc *dev, unsigned char address)
+{
+ DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
+ /* c.f. 15.1.2.2 Table 15-4 address will be used after DATA_END is set */
+ dev->usb_address = address;
+ usb_set((address & USB_FA_FUNCTION_ADDR), USB_FA);
+ usb_set(USB_FA_ADDR_UPDATE | (address & USB_FA_FUNCTION_ADDR), USB_FA);
+ /* usb_read(USB_FA); */
+}
+
+/*
+ * DATA_STATE_RECV (OUT_PKT_RDY)
+ * - if error
+ * set EP0_CLR_OUT | EP0_DATA_END | EP0_SEND_STALL bits
+ * - else
+ * set EP0_CLR_OUT bit
+ if last set EP0_DATA_END bit
+ */
+static void lh7a40x_ep0_out(struct lh7a40x_udc *dev, u32 csr)
+{
+ struct lh7a40x_request *req;
+ struct lh7a40x_ep *ep = &dev->ep[0];
+ int ret;
+
+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct lh7a40x_request, queue);
+
+ if (req) {
+
+ if (req->req.length == 0) {
+ DEBUG_EP0("ZERO LENGTH OUT!\n");
+ usb_set((EP0_CLR_OUT | EP0_DATA_END), USB_EP0_CSR);
+ dev->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+ ret = read_fifo_ep0(ep, req);
+ if (ret) {
+ /* Done! */
+ DEBUG_EP0("%s: finished, waiting for status\n",
+ __FUNCTION__);
+
+ usb_set((EP0_CLR_OUT | EP0_DATA_END), USB_EP0_CSR);
+ dev->ep0state = WAIT_FOR_SETUP;
+ } else {
+ /* Not done yet.. */
+ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
+ usb_set(EP0_CLR_OUT, USB_EP0_CSR);
+ }
+ } else {
+ DEBUG_EP0("NO REQ??!\n");
+ }
+}
+
+/*
+ * DATA_STATE_XMIT
+ */
+static int lh7a40x_ep0_in(struct lh7a40x_udc *dev, u32 csr)
+{
+ struct lh7a40x_request *req;
+ struct lh7a40x_ep *ep = &dev->ep[0];
+ int ret, need_zlp = 0;
+
+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct lh7a40x_request, queue);
+
+ if (!req) {
+ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
+ return 0;
+ }
+
+ if (req->req.length == 0) {
+
+ usb_set((EP0_IN_PKT_RDY | EP0_DATA_END), USB_EP0_CSR);
+ dev->ep0state = WAIT_FOR_SETUP;
+ return 1;
+ }
+
+ if (req->req.length - req->req.actual == EP0_PACKETSIZE) {
+ /* Next write will end with the packet size, */
+ /* so we need Zero-length-packet */
+ need_zlp = 1;
+ }
+
+ ret = write_fifo_ep0(ep, req);
+
+ if (ret == 1 && !need_zlp) {
+ /* Last packet */
+ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
+
+ usb_set((EP0_IN_PKT_RDY | EP0_DATA_END), USB_EP0_CSR);
+ dev->ep0state = WAIT_FOR_SETUP;
+ } else {
+ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
+ usb_set(EP0_IN_PKT_RDY, USB_EP0_CSR);
+ }
+
+ if (need_zlp) {
+ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
+ usb_set(EP0_IN_PKT_RDY, USB_EP0_CSR);
+ dev->ep0state = DATA_STATE_NEED_ZLP;
+ }
+
+ return 1;
+}
+
+static int lh7a40x_handle_get_status(struct lh7a40x_udc *dev,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct lh7a40x_ep *ep0 = &dev->ep[0];
+ struct lh7a40x_ep *qep;
+ int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
+ u16 val = 0;
+
+ if (reqtype == USB_RECIP_INTERFACE) {
+ /* This is not supported.
+ * And according to the USB spec, this one does nothing..
+ * Just return 0
+ */
+ DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
+ } else if (reqtype == USB_RECIP_DEVICE) {
+ DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
+ val |= (1 << 0); /* Self powered */
+ /*val |= (1<<1); *//* Remote wakeup */
+ } else if (reqtype == USB_RECIP_ENDPOINT) {
+ int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
+
+ DEBUG_SETUP
+ ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
+ ep_num, ctrl->wLength);
+
+ if (ctrl->wLength > 2 || ep_num > 3)
+ return -EOPNOTSUPP;
+
+ qep = &dev->ep[ep_num];
+ if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
+ && ep_index(qep) != 0) {
+ return -EOPNOTSUPP;
+ }
+
+ usb_set_index(ep_index(qep));
+
+ /* Return status on next IN token */
+ switch (qep->ep_type) {
+ case ep_control:
+ val =
+ (usb_read(qep->csr1) & EP0_SEND_STALL) ==
+ EP0_SEND_STALL;
+ break;
+ case ep_bulk_in:
+ case ep_interrupt:
+ val =
+ (usb_read(qep->csr1) & USB_IN_CSR1_SEND_STALL) ==
+ USB_IN_CSR1_SEND_STALL;
+ break;
+ case ep_bulk_out:
+ val =
+ (usb_read(qep->csr1) & USB_OUT_CSR1_SEND_STALL) ==
+ USB_OUT_CSR1_SEND_STALL;
+ break;
+ }
+
+ /* Back to EP0 index */
+ usb_set_index(0);
+
+ DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
+ ctrl->wIndex, val);
+ } else {
+ DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
+ return -EOPNOTSUPP;
+ }
+
+ /* Clear "out packet ready" */
+ usb_set((EP0_CLR_OUT), USB_EP0_CSR);
+ /* Put status to FIFO */
+ lh7a40x_fifo_write(ep0, (u8 *) & val, sizeof(val));
+ /* Issue "In packet ready" */
+ usb_set((EP0_IN_PKT_RDY | EP0_DATA_END), USB_EP0_CSR);
+
+ return 0;
+}
+
+/*
+ * WAIT_FOR_SETUP (OUT_PKT_RDY)
+ * - read data packet from EP0 FIFO
+ * - decode command
+ * - if error
+ * set EP0_CLR_OUT | EP0_DATA_END | EP0_SEND_STALL bits
+ * - else
+ * set EP0_CLR_OUT | EP0_DATA_END bits
+ */
+static void lh7a40x_ep0_setup(struct lh7a40x_udc *dev, u32 csr)
+{
+ struct lh7a40x_ep *ep = &dev->ep[0];
+ struct usb_ctrlrequest ctrl;
+ int i, bytes, is_in;
+
+ DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
+
+ /* Nuke all previous transfers */
+ nuke(ep, -EPROTO);
+
+ /* read control req from fifo (8 bytes) */
+ bytes = lh7a40x_fifo_read(ep, (unsigned char *)&ctrl, 8);
+
+ DEBUG_SETUP("Read CTRL REQ %d bytes\n", bytes);
+ DEBUG_SETUP("CTRL.bRequestType = %d (is_in %d)\n", ctrl.bRequestType,
+ ctrl.bRequestType == USB_DIR_IN);
+ DEBUG_SETUP("CTRL.bRequest = %d\n", ctrl.bRequest);
+ DEBUG_SETUP("CTRL.wLength = %d\n", ctrl.wLength);
+ DEBUG_SETUP("CTRL.wValue = %d (%d)\n", ctrl.wValue, ctrl.wValue >> 8);
+ DEBUG_SETUP("CTRL.wIndex = %d\n", ctrl.wIndex);
+
+ /* Set direction of EP0 */
+ if (likely(ctrl.bRequestType & USB_DIR_IN)) {
+ ep->bEndpointAddress |= USB_DIR_IN;
+ is_in = 1;
+ } else {
+ ep->bEndpointAddress &= ~USB_DIR_IN;
+ is_in = 0;
+ }
+
+ dev->req_pending = 1;
+
+ /* Handle some SETUP packets ourselves */
+ switch (ctrl.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
+ break;
+
+ DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
+ udc_set_address(dev, ctrl.wValue);
+ usb_set((EP0_CLR_OUT | EP0_DATA_END), USB_EP0_CSR);
+ return;
+
+ case USB_REQ_GET_STATUS:{
+ if (lh7a40x_handle_get_status(dev, &ctrl) == 0)
+ return;
+
+ case USB_REQ_CLEAR_FEATURE:
+ case USB_REQ_SET_FEATURE:
+ if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
+ struct lh7a40x_ep *qep;
+ int ep_num = (ctrl.wIndex & 0x0f);
+
+ /* Support only HALT feature */
+ if (ctrl.wValue != 0 || ctrl.wLength != 0
+ || ep_num > 3 || ep_num < 1)
+ break;
+
+ qep = &dev->ep[ep_num];
+ if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
+ DEBUG_SETUP("SET_FEATURE (%d)\n",
+ ep_num);
+ lh7a40x_set_halt(&qep->ep, 1);
+ } else {
+ DEBUG_SETUP("CLR_FEATURE (%d)\n",
+ ep_num);
+ lh7a40x_set_halt(&qep->ep, 0);
+ }
+ usb_set_index(0);
+
+ /* Reply with a ZLP on next IN token */
+ usb_set((EP0_CLR_OUT | EP0_DATA_END),
+ USB_EP0_CSR);
+ return;
+ }
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ if (likely(dev->driver)) {
+ /* device-2-host (IN) or no data setup command, process immediately */
+ spin_unlock(&dev->lock);
+ i = dev->driver->setup(&dev->gadget, &ctrl);
+ spin_lock(&dev->lock);
+
+ if (i < 0) {
+ /* setup processing failed, force stall */
+ DEBUG_SETUP
+ (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
+ i);
+ usb_set_index(0);
+ usb_set((EP0_CLR_OUT | EP0_DATA_END | EP0_SEND_STALL),
+ USB_EP0_CSR);
+
+ /* ep->stopped = 1; */
+ dev->ep0state = WAIT_FOR_SETUP;
+ }
+ }
+}
+
+/*
+ * DATA_STATE_NEED_ZLP
+ */
+static void lh7a40x_ep0_in_zlp(struct lh7a40x_udc *dev, u32 csr)
+{
+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
+
+ /* c.f. Table 15-14 */
+ usb_set((EP0_IN_PKT_RDY | EP0_DATA_END), USB_EP0_CSR);
+ dev->ep0state = WAIT_FOR_SETUP;
+}
+
+/*
+ * handle ep0 interrupt
+ */
+static void lh7a40x_handle_ep0(struct lh7a40x_udc *dev, u32 intr)
+{
+ struct lh7a40x_ep *ep = &dev->ep[0];
+ u32 csr;
+
+ /* Set index 0 */
+ usb_set_index(0);
+ csr = usb_read(USB_EP0_CSR);
+
+ DEBUG_EP0("%s: csr = %x\n", __FUNCTION__, csr);
+
+ /*
+ * For overview of what we should be doing see c.f. Chapter 18.1.2.4
+ * We will follow that outline here modified by our own global state
+ * indication which provides hints as to what we think should be
+ * happening..
+ */
+
+ /*
+ * if SENT_STALL is set
+ * - clear the SENT_STALL bit
+ */
+ if (csr & EP0_SENT_STALL) {
+ DEBUG_EP0("%s: EP0_SENT_STALL is set: %x\n", __FUNCTION__, csr);
+ usb_clear((EP0_SENT_STALL | EP0_SEND_STALL), USB_EP0_CSR);
+ nuke(ep, -ECONNABORTED);
+ dev->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+
+ /*
+ * if a transfer is in progress && IN_PKT_RDY and OUT_PKT_RDY are clear
+ * - fill EP0 FIFO
+ * - if last packet
+ * - set IN_PKT_RDY | DATA_END
+ * - else
+ * set IN_PKT_RDY
+ */
+ if (!(csr & (EP0_IN_PKT_RDY | EP0_OUT_PKT_RDY))) {
+ DEBUG_EP0("%s: IN_PKT_RDY and OUT_PKT_RDY are clear\n",
+ __FUNCTION__);
+
+ switch (dev->ep0state) {
+ case DATA_STATE_XMIT:
+ DEBUG_EP0("continue with DATA_STATE_XMIT\n");
+ lh7a40x_ep0_in(dev, csr);
+ return;
+ case DATA_STATE_NEED_ZLP:
+ DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
+ lh7a40x_ep0_in_zlp(dev, csr);
+ return;
+ default:
+ /* Stall? */
+ DEBUG_EP0("Odd state!! state = %s\n",
+ state_names[dev->ep0state]);
+ dev->ep0state = WAIT_FOR_SETUP;
+ /* nuke(ep, 0); */
+ /* usb_set(EP0_SEND_STALL, ep->csr1); */
+ break;
+ }
+ }
+
+ /*
+ * if SETUP_END is set
+ * - abort the last transfer
+ * - set SERVICED_SETUP_END_BIT
+ */
+ if (csr & EP0_SETUP_END) {
+ DEBUG_EP0("%s: EP0_SETUP_END is set: %x\n", __FUNCTION__, csr);
+
+ usb_set(EP0_CLR_SETUP_END, USB_EP0_CSR);
+
+ nuke(ep, 0);
+ dev->ep0state = WAIT_FOR_SETUP;
+ }
+
+ /*
+ * if EP0_OUT_PKT_RDY is set
+ * - read data packet from EP0 FIFO
+ * - decode command
+ * - if error
+ * set SERVICED_OUT_PKT_RDY | DATA_END bits | SEND_STALL
+ * - else
+ * set SERVICED_OUT_PKT_RDY | DATA_END bits
+ */
+ if (csr & EP0_OUT_PKT_RDY) {
+
+ DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
+ csr);
+
+ switch (dev->ep0state) {
+ case WAIT_FOR_SETUP:
+ DEBUG_EP0("WAIT_FOR_SETUP\n");
+ lh7a40x_ep0_setup(dev, csr);
+ break;
+
+ case DATA_STATE_RECV:
+ DEBUG_EP0("DATA_STATE_RECV\n");
+ lh7a40x_ep0_out(dev, csr);
+ break;
+
+ default:
+ /* send stall? */
+ DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
+ dev->ep0state);
+ break;
+ }
+ }
+}
+
+static void lh7a40x_ep0_kick(struct lh7a40x_udc *dev, struct lh7a40x_ep *ep)
+{
+ u32 csr;
+
+ usb_set_index(0);
+ csr = usb_read(USB_EP0_CSR);
+
+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
+
+ /* Clear "out packet ready" */
+ usb_set(EP0_CLR_OUT, USB_EP0_CSR);
+
+ if (ep_is_in(ep)) {
+ dev->ep0state = DATA_STATE_XMIT;
+ lh7a40x_ep0_in(dev, csr);
+ } else {
+ dev->ep0state = DATA_STATE_RECV;
+ lh7a40x_ep0_out(dev, csr);
+ }
+}
+
+/* ---------------------------------------------------------------------------
+ * device-scoped parts of the api to the usb controller hardware
+ * ---------------------------------------------------------------------------
+ */
+
+static int lh7a40x_udc_get_frame(struct usb_gadget *_gadget)
+{
+ u32 frame1 = usb_read(USB_FRM_NUM1); /* Least significant 8 bits */
+ u32 frame2 = usb_read(USB_FRM_NUM2); /* Most significant 3 bits */
+ DEBUG("%s, %p\n", __FUNCTION__, _gadget);
+ return ((frame2 & 0x07) << 8) | (frame1 & 0xff);
+}
+
+static int lh7a40x_udc_wakeup(struct usb_gadget *_gadget)
+{
+ /* host may not have enabled remote wakeup */
+ /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
+ return -EHOSTUNREACH;
+ udc_set_mask_UDCCR(UDCCR_RSM); */
+ return -ENOTSUPP;
+}
+
+static const struct usb_gadget_ops lh7a40x_udc_ops = {
+ .get_frame = lh7a40x_udc_get_frame,
+ .wakeup = lh7a40x_udc_wakeup,
+ /* current versions must always be self-powered */
+};
+
+static void nop_release(struct device *dev)
+{
+ DEBUG("%s %s\n", __FUNCTION__, dev->bus_id);
+}
+
+static struct lh7a40x_udc memory = {
+ .usb_address = 0,
+
+ .gadget = {
+ .ops = &lh7a40x_udc_ops,
+ .ep0 = &memory.ep[0].ep,
+ .name = driver_name,
+ .dev = {
+ .bus_id = "gadget",
+ .release = nop_release,
+ },
+ },
+
+ /* control endpoint */
+ .ep[0] = {
+ .ep = {
+ .name = ep0name,
+ .ops = &lh7a40x_ep_ops,
+ .maxpacket = EP0_PACKETSIZE,
+ },
+ .dev = &memory,
+
+ .bEndpointAddress = 0,
+ .bmAttributes = 0,
+
+ .ep_type = ep_control,
+ .fifo = io_p2v(USB_EP0_FIFO),
+ .csr1 = USB_EP0_CSR,
+ .csr2 = USB_EP0_CSR,
+ },
+
+ /* first group of endpoints */
+ .ep[1] = {
+ .ep = {
+ .name = "ep1in-bulk",
+ .ops = &lh7a40x_ep_ops,
+ .maxpacket = 64,
+ },
+ .dev = &memory,
+
+ .bEndpointAddress = USB_DIR_IN | 1,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+
+ .ep_type = ep_bulk_in,
+ .fifo = io_p2v(USB_EP1_FIFO),
+ .csr1 = USB_IN_CSR1,
+ .csr2 = USB_IN_CSR2,
+ },
+
+ .ep[2] = {
+ .ep = {
+ .name = "ep2out-bulk",
+ .ops = &lh7a40x_ep_ops,
+ .maxpacket = 64,
+ },
+ .dev = &memory,
+
+ .bEndpointAddress = 2,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+
+ .ep_type = ep_bulk_out,
+ .fifo = io_p2v(USB_EP2_FIFO),
+ .csr1 = USB_OUT_CSR1,
+ .csr2 = USB_OUT_CSR2,
+ },
+
+ .ep[3] = {
+ .ep = {
+ .name = "ep3in-int",
+ .ops = &lh7a40x_ep_ops,
+ .maxpacket = 64,
+ },
+ .dev = &memory,
+
+ .bEndpointAddress = USB_DIR_IN | 3,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+
+ .ep_type = ep_interrupt,
+ .fifo = io_p2v(USB_EP3_FIFO),
+ .csr1 = USB_IN_CSR1,
+ .csr2 = USB_IN_CSR2,
+ },
+};
+
+/*
+ * probe - binds to the platform device
+ */
+static int lh7a40x_udc_probe(struct device *_dev)
+{
+ struct lh7a40x_udc *dev = &memory;
+ int retval;
+
+ DEBUG("%s: %p\n", __FUNCTION__, _dev);
+
+ spin_lock_init(&dev->lock);
+ dev->dev = _dev;
+
+ device_initialize(&dev->gadget.dev);
+ dev->gadget.dev.parent = _dev;
+
+ the_controller = dev;
+ dev_set_drvdata(_dev, dev);
+
+ udc_disable(dev);
+ udc_reinit(dev);
+
+ /* irq setup after old hardware state is cleaned up */
+ retval =
+ request_irq(IRQ_USBINTR, lh7a40x_udc_irq, SA_INTERRUPT, driver_name,
+ dev);
+ if (retval != 0) {
+ DEBUG(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name,
+ IRQ_USBINTR, retval);
+ return -EBUSY;
+ }
+
+ create_proc_files();
+
+ return retval;
+}
+
+static int lh7a40x_udc_remove(struct device *_dev)
+{
+ struct lh7a40x_udc *dev = _dev->driver_data;
+
+ DEBUG("%s: %p\n", __FUNCTION__, dev);
+
+ udc_disable(dev);
+ remove_proc_files();
+ usb_gadget_unregister_driver(dev->driver);
+
+ free_irq(IRQ_USBINTR, dev);
+
+ dev_set_drvdata(_dev, 0);
+
+ the_controller = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static struct device_driver udc_driver = {
+ .name = (char *)driver_name,
+ .bus = &platform_bus_type,
+ .probe = lh7a40x_udc_probe,
+ .remove = lh7a40x_udc_remove
+ /* FIXME power management support */
+ /* .suspend = ... disable UDC */
+ /* .resume = ... re-enable UDC */
+};
+
+static int __init udc_init(void)
+{
+ DEBUG("%s: %s version %s\n", __FUNCTION__, driver_name, DRIVER_VERSION);
+ return driver_register(&udc_driver);
+}
+
+static void __exit udc_exit(void)
+{
+ driver_unregister(&udc_driver);
+}
+
+module_init(udc_init);
+module_exit(udc_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Mikko Lahteenmaki, Bo Henriksen");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * linux/drivers/usb/gadget/lh7a40x_udc.h
+ * Sharp LH7A40x on-chip full speed USB device controllers
+ *
+ * Copyright (C) 2004 Mikko Lahteenmaki, Nordic ID
+ * Copyright (C) 2004 Bo Henriksen, Nordic ID
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __LH7A40X_H_
+#define __LH7A40X_H_
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/byteorder.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/hardware.h>
+
+#include <linux/usb_ch9.h>
+#include <linux/usb_gadget.h>
+
+/*
+ * Memory map
+ */
+
+#define USB_FA 0x80000200 // function address register
+#define USB_PM 0x80000204 // power management register
+
+#define USB_IN_INT 0x80000208 // IN interrupt register bank (EP0-EP3)
+#define USB_OUT_INT 0x80000210 // OUT interrupt register bank (EP2)
+#define USB_INT 0x80000218 // interrupt register bank
+
+#define USB_IN_INT_EN 0x8000021C // IN interrupt enable register bank
+#define USB_OUT_INT_EN 0x80000224 // OUT interrupt enable register bank
+#define USB_INT_EN 0x8000022C // USB interrupt enable register bank
+
+#define USB_FRM_NUM1 0x80000230 // Frame number1 register
+#define USB_FRM_NUM2 0x80000234 // Frame number2 register
+#define USB_INDEX 0x80000238 // index register
+
+#define USB_IN_MAXP 0x80000240 // IN MAXP register
+#define USB_IN_CSR1 0x80000244 // IN CSR1 register/EP0 CSR register
+#define USB_EP0_CSR 0x80000244 // IN CSR1 register/EP0 CSR register
+#define USB_IN_CSR2 0x80000248 // IN CSR2 register
+#define USB_OUT_MAXP 0x8000024C // OUT MAXP register
+
+#define USB_OUT_CSR1 0x80000250 // OUT CSR1 register
+#define USB_OUT_CSR2 0x80000254 // OUT CSR2 register
+#define USB_OUT_FIFO_WC1 0x80000258 // OUT FIFO write count1 register
+#define USB_OUT_FIFO_WC2 0x8000025C // OUT FIFO write count2 register
+
+#define USB_RESET 0x8000044C // USB reset register
+
+#define USB_EP0_FIFO 0x80000280
+#define USB_EP1_FIFO 0x80000284
+#define USB_EP2_FIFO 0x80000288
+#define USB_EP3_FIFO 0x8000028c
+
+/*
+ * USB reset register
+ */
+#define USB_RESET_APB (1<<1) //resets USB APB control side WRITE
+#define USB_RESET_IO (1<<0) //resets USB IO side WRITE
+
+/*
+ * USB function address register
+ */
+#define USB_FA_ADDR_UPDATE (1<<7)
+#define USB_FA_FUNCTION_ADDR (0x7F)
+
+/*
+ * Power Management register
+ */
+#define PM_USB_DCP (1<<5)
+#define PM_USB_ENABLE (1<<4)
+#define PM_USB_RESET (1<<3)
+#define PM_UC_RESUME (1<<2)
+#define PM_SUSPEND_MODE (1<<1)
+#define PM_ENABLE_SUSPEND (1<<0)
+
+/*
+ * IN interrupt register
+ */
+#define USB_IN_INT_EP3 (1<<3)
+#define USB_IN_INT_EP1 (1<<1)
+#define USB_IN_INT_EP0 (1<<0)
+
+/*
+ * OUT interrupt register
+ */
+#define USB_OUT_INT_EP2 (1<<2)
+
+/*
+ * USB interrupt register
+ */
+#define USB_INT_RESET_INT (1<<2)
+#define USB_INT_RESUME_INT (1<<1)
+#define USB_INT_SUSPEND_INT (1<<0)
+
+/*
+ * USB interrupt enable register
+ */
+#define USB_INT_EN_USB_RESET_INTER (1<<2)
+#define USB_INT_EN_RESUME_INTER (1<<1)
+#define USB_INT_EN_SUSPEND_INTER (1<<0)
+
+/*
+ * INCSR1 register
+ */
+#define USB_IN_CSR1_CLR_DATA_TOGGLE (1<<6)
+#define USB_IN_CSR1_SENT_STALL (1<<5)
+#define USB_IN_CSR1_SEND_STALL (1<<4)
+#define USB_IN_CSR1_FIFO_FLUSH (1<<3)
+#define USB_IN_CSR1_FIFO_NOT_EMPTY (1<<1)
+#define USB_IN_CSR1_IN_PKT_RDY (1<<0)
+
+/*
+ * INCSR2 register
+ */
+#define USB_IN_CSR2_AUTO_SET (1<<7)
+#define USB_IN_CSR2_USB_DMA_EN (1<<4)
+
+/*
+ * OUT CSR1 register
+ */
+#define USB_OUT_CSR1_CLR_DATA_REG (1<<7)
+#define USB_OUT_CSR1_SENT_STALL (1<<6)
+#define USB_OUT_CSR1_SEND_STALL (1<<5)
+#define USB_OUT_CSR1_FIFO_FLUSH (1<<4)
+#define USB_OUT_CSR1_FIFO_FULL (1<<1)
+#define USB_OUT_CSR1_OUT_PKT_RDY (1<<0)
+
+/*
+ * OUT CSR2 register
+ */
+#define USB_OUT_CSR2_AUTO_CLR (1<<7)
+#define USB_OUT_CSR2_USB_DMA_EN (1<<4)
+
+/*
+ * EP0 CSR
+ */
+#define EP0_CLR_SETUP_END (1<<7) /* Clear "Setup Ends" Bit (w) */
+#define EP0_CLR_OUT (1<<6) /* Clear "Out packet ready" Bit (w) */
+#define EP0_SEND_STALL (1<<5) /* Send STALL Handshake (rw) */
+#define EP0_SETUP_END (1<<4) /* Setup Ends (r) */
+
+#define EP0_DATA_END (1<<3) /* Data end (rw) */
+#define EP0_SENT_STALL (1<<2) /* Sent Stall Handshake (r) */
+#define EP0_IN_PKT_RDY (1<<1) /* In packet ready (rw) */
+#define EP0_OUT_PKT_RDY (1<<0) /* Out packet ready (r) */
+
+/* general CSR */
+#define OUT_PKT_RDY (1<<0)
+#define IN_PKT_RDY (1<<0)
+
+/*
+ * IN/OUT MAXP register
+ */
+#define USB_OUT_MAXP_MAXP (0xF)
+#define USB_IN_MAXP_MAXP (0xF)
+
+// Max packet size
+//#define EP0_PACKETSIZE 0x10
+#define EP0_PACKETSIZE 0x8
+#define EP0_MAXPACKETSIZE 0x10
+
+#define UDC_MAX_ENDPOINTS 4
+
+#define WAIT_FOR_SETUP 0
+#define DATA_STATE_XMIT 1
+#define DATA_STATE_NEED_ZLP 2
+#define WAIT_FOR_OUT_STATUS 3
+#define DATA_STATE_RECV 4
+
+/* ********************************************************************************************* */
+/* IO
+ */
+
+typedef enum ep_type {
+ ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
+} ep_type_t;
+
+struct lh7a40x_ep {
+ struct usb_ep ep;
+ struct lh7a40x_udc *dev;
+
+ const struct usb_endpoint_descriptor *desc;
+ struct list_head queue;
+ unsigned long pio_irqs;
+
+ u8 stopped;
+ u8 bEndpointAddress;
+ u8 bmAttributes;
+
+ ep_type_t ep_type;
+ u32 fifo;
+ u32 csr1;
+ u32 csr2;
+};
+
+struct lh7a40x_request {
+ struct usb_request req;
+ struct list_head queue;
+};
+
+struct lh7a40x_udc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct device *dev;
+ spinlock_t lock;
+
+ int ep0state;
+ struct lh7a40x_ep ep[UDC_MAX_ENDPOINTS];
+
+ unsigned char usb_address;
+
+ unsigned req_pending:1, req_std:1, req_config:1;
+};
+
+extern struct lh7a40x_udc *the_controller;
+
+#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
+#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
+#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
+
+#endif
--- /dev/null
+/*
+ * omap_udc.c -- for OMAP 1610 udc, with OTG support
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#undef DEBUG
+#undef VERBOSE
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/mm.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb_ch9.h>
+#include <linux/usb_gadget.h>
+#include <linux/usb_otg.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+
+#include "omap_udc.h"
+
+#undef USB_TRACE
+
+/* OUT-dma seems to be behaving */
+#define USE_DMA
+
+/* ISO too */
+#define USE_ISO
+
+
+#define DRIVER_DESC "OMAP UDC driver"
+#define DRIVER_VERSION "24 August 2004"
+
+#define DMA_ADDR_INVALID (~(dma_addr_t)0)
+
+
+/*
+ * The OMAP UDC needs _very_ early endpoint setup: before enabling the
+ * D+ pullup to allow enumeration. That's too early for the gadget
+ * framework to use from usb_endpoint_enable(), which happens after
+ * enumeration as part of activating an interface. (But if we add an
+ * optional new "UDC not yet running" state to the gadget driver model,
+ * even just during driver binding, the endpoint autoconfig logic is the
+ * natural spot to manufacture new endpoints.)
+ *
+ * So instead of using endpoint enable calls to control the hardware setup,
+ * this driver defines a "fifo mode" parameter. It's used during driver
+ * initialization to choose among a set of pre-defined endpoint configs.
+ * See omap_udc_setup() for available modes, or to add others. That code
+ * lives in an init section, so use this driver as a module if you need
+ * to change the fifo mode after the kernel boots.
+ *
+ * Gadget drivers normally ignore endpoints they don't care about, and
+ * won't include them in configuration descriptors. That means only
+ * misbehaving hosts would even notice they exist.
+ */
+#ifdef USE_ISO
+static unsigned fifo_mode = 3;
+#else
+static unsigned fifo_mode = 0;
+#endif
+
+/* "modprobe omap_udc fifo_mode=42", or else as a kernel
+ * boot parameter "omap_udc:fifo_mode=42"
+ */
+module_param (fifo_mode, uint, 0);
+MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
+
+
+#ifdef USE_DMA
+static unsigned use_dma = 1;
+
+/* "modprobe omap_udc use_dma=y", or else as a kernel
+ * boot parameter "omap_udc:use_dma=y"
+ */
+module_param (use_dma, bool, 0);
+MODULE_PARM_DESC (use_dma, "enable/disable DMA");
+#else /* !USE_DMA */
+
+/* save a bit of code */
+#define use_dma 0
+#endif /* !USE_DMA */
+
+
+static const char driver_name [] = "omap_udc";
+static const char driver_desc [] = DRIVER_DESC;
+
+/*-------------------------------------------------------------------------*/
+
+/* there's a notion of "current endpoint" for modifying endpoint
+ * state, and PIO access to its FIFO.
+ */
+
+static void use_ep(struct omap_ep *ep, u16 select)
+{
+ u16 num = ep->bEndpointAddress & 0x0f;
+
+ if (ep->bEndpointAddress & USB_DIR_IN)
+ num |= UDC_EP_DIR;
+ UDC_EP_NUM_REG = num | select;
+ /* when select, MUST deselect later !! */
+}
+
+static inline void deselect_ep(void)
+{
+ UDC_EP_NUM_REG &= ~UDC_EP_SEL;
+ /* 6 wait states before TX will happen */
+}
+
+static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
+
+/*-------------------------------------------------------------------------*/
+
+static int omap_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
+ struct omap_udc *udc;
+ unsigned long flags;
+ u16 maxp;
+
+ /* catch various bogus parameters */
+ if (!_ep || !desc || ep->desc
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || ep->bEndpointAddress != desc->bEndpointAddress
+ || ep->maxpacket < le16_to_cpu
+ (desc->wMaxPacketSize)) {
+ DBG("%s, bad ep or descriptor\n", __FUNCTION__);
+ return -EINVAL;
+ }
+ maxp = le16_to_cpu (desc->wMaxPacketSize);
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && maxp != ep->maxpacket)
+ || desc->wMaxPacketSize > ep->maxpacket
+ || !desc->wMaxPacketSize) {
+ DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
+ return -ERANGE;
+ }
+
+#ifdef USE_ISO
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ && desc->bInterval != 1)) {
+ /* hardware wants period = 1; USB allows 2^(Interval-1) */
+ DBG("%s, unsupported ISO period %dms\n", _ep->name,
+ 1 << (desc->bInterval - 1));
+ return -EDOM;
+ }
+#else
+ if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ DBG("%s, ISO nyet\n", _ep->name);
+ return -EDOM;
+ }
+#endif
+
+ /* xfer types must match, except that interrupt ~= bulk */
+ if (ep->bmAttributes != desc->bmAttributes
+ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
+ DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
+ return -EINVAL;
+ }
+
+ udc = ep->udc;
+ if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+ DBG("%s, bogus device state\n", __FUNCTION__);
+ return -ESHUTDOWN;
+ }
+
+ spin_lock_irqsave(&udc->lock, flags);
+
+ ep->desc = desc;
+ ep->irqs = 0;
+ ep->stopped = 0;
+ ep->ep.maxpacket = maxp;
+
+ /* set endpoint to initial state */
+ ep->dma_channel = 0;
+ ep->has_dma = 0;
+ ep->lch = -1;
+ use_ep(ep, UDC_EP_SEL);
+ UDC_CTRL_REG = UDC_RESET_EP;
+ ep->ackwait = 0;
+ deselect_ep();
+
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
+ list_add(&ep->iso, &udc->iso);
+
+ /* maybe assign a DMA channel to this endpoint */
+ if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && !(ep->bEndpointAddress & USB_DIR_IN))
+ /* FIXME ISO can dma, but prefers first channel.
+ * IN can dma, but lacks debugging.
+ */
+ dma_channel_claim(ep, 0);
+
+ /* PIO OUT may RX packets */
+ if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
+ && !ep->has_dma
+ && !(ep->bEndpointAddress & USB_DIR_IN))
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+
+ spin_unlock_irqrestore(&udc->lock, flags);
+ VDBG("%s enabled\n", _ep->name);
+ return 0;
+}
+
+static void nuke(struct omap_ep *, int status);
+
+static int omap_ep_disable(struct usb_ep *_ep)
+{
+ struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
+ unsigned long flags;
+
+ if (!_ep || !ep->desc) {
+ DBG("%s, %s not enabled\n", __FUNCTION__,
+ _ep ? ep->ep.name : NULL);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&ep->udc->lock, flags);
+ ep->desc = 0;
+ nuke (ep, -ESHUTDOWN);
+ ep->ep.maxpacket = ep->maxpacket;
+ ep->has_dma = 0;
+ UDC_CTRL_REG = UDC_SET_HALT;
+ list_del_init(&ep->iso);
+
+ spin_unlock_irqrestore(&ep->udc->lock, flags);
+
+ VDBG("%s disabled\n", _ep->name);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static struct usb_request *
+omap_alloc_request(struct usb_ep *ep, int gfp_flags)
+{
+ struct omap_req *req;
+
+ req = kmalloc(sizeof *req, gfp_flags);
+ if (req) {
+ memset (req, 0, sizeof *req);
+ req->req.dma = DMA_ADDR_INVALID;
+ INIT_LIST_HEAD (&req->queue);
+ }
+ return &req->req;
+}
+
+static void
+omap_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+ struct omap_req *req = container_of(_req, struct omap_req, req);
+
+ if (_req)
+ kfree (req);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void *
+omap_alloc_buffer(
+ struct usb_ep *_ep,
+ unsigned bytes,
+ dma_addr_t *dma,
+ int gfp_flags
+)
+{
+ void *retval;
+ struct omap_ep *ep;
+
+ ep = container_of(_ep, struct omap_ep, ep);
+ if (use_dma && ep->has_dma) {
+ static int warned;
+ if (!warned && bytes < PAGE_SIZE) {
+ dev_warn(ep->udc->gadget.dev.parent,
+ "using dma_alloc_coherent for "
+ "small allocations wastes memory\n");
+ warned++;
+ }
+ return dma_alloc_coherent(ep->udc->gadget.dev.parent,
+ bytes, dma, gfp_flags);
+ }
+
+ retval = kmalloc(bytes, gfp_flags);
+ if (retval)
+ *dma = virt_to_phys(retval);
+ return retval;
+}
+
+static void omap_free_buffer(
+ struct usb_ep *_ep,
+ void *buf,
+ dma_addr_t dma,
+ unsigned bytes
+)
+{
+ struct omap_ep *ep;
+
+ ep = container_of(_ep, struct omap_ep, ep);
+ if (use_dma && _ep && ep->has_dma)
+ dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
+ else
+ kfree (buf);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void
+done(struct omap_ep *ep, struct omap_req *req, int status)
+{
+ unsigned stopped = ep->stopped;
+
+ list_del_init(&req->queue);
+
+ if (req->req.status == -EINPROGRESS)
+ req->req.status = status;
+ else
+ status = req->req.status;
+
+ if (use_dma && ep->has_dma) {
+ if (req->mapped) {
+ dma_unmap_single(ep->udc->gadget.dev.parent,
+ req->req.dma, req->req.length,
+ (ep->bEndpointAddress & USB_DIR_IN)
+ ? DMA_TO_DEVICE
+ : DMA_FROM_DEVICE);
+ req->req.dma = DMA_ADDR_INVALID;
+ req->mapped = 0;
+ } else
+ dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
+ req->req.dma, req->req.length,
+ (ep->bEndpointAddress & USB_DIR_IN)
+ ? DMA_TO_DEVICE
+ : DMA_FROM_DEVICE);
+ }
+
+#ifndef USB_TRACE
+ if (status && status != -ESHUTDOWN)
+#endif
+ VDBG("complete %s req %p stat %d len %u/%u\n",
+ ep->ep.name, &req->req, status,
+ req->req.actual, req->req.length);
+
+ /* don't modify queue heads during completion callback */
+ ep->stopped = 1;
+ spin_unlock(&ep->udc->lock);
+ req->req.complete(&ep->ep, &req->req);
+ spin_lock(&ep->udc->lock);
+ ep->stopped = stopped;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
+#define FIFO_UNWRITABLE (UDC_EP_HALTED | FIFO_FULL)
+
+#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
+#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
+
+static inline int
+write_packet(u8 *buf, struct omap_req *req, unsigned max)
+{
+ unsigned len;
+ u16 *wp;
+
+ len = min(req->req.length - req->req.actual, max);
+ req->req.actual += len;
+
+ max = len;
+ if (likely((((int)buf) & 1) == 0)) {
+ wp = (u16 *)buf;
+ while (max >= 2) {
+ UDC_DATA_REG = *wp++;
+ max -= 2;
+ }
+ buf = (u8 *)wp;
+ }
+ while (max--)
+ *(volatile u8 *)&UDC_DATA_REG = *buf++;
+ return len;
+}
+
+// FIXME change r/w fifo calling convention
+
+
+// return: 0 = still running, 1 = completed, negative = errno
+static int write_fifo(struct omap_ep *ep, struct omap_req *req)
+{
+ u8 *buf;
+ unsigned count;
+ int is_last;
+ u16 ep_stat;
+
+ buf = req->req.buf + req->req.actual;
+ prefetch(buf);
+
+ /* PIO-IN isn't double buffered except for iso */
+ ep_stat = UDC_STAT_FLG_REG;
+ if (ep_stat & FIFO_UNWRITABLE)
+ return 0;
+
+ count = ep->ep.maxpacket;
+ count = write_packet(buf, req, count);
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ ep->ackwait = 1;
+
+ /* last packet is often short (sometimes a zlp) */
+ if (count != ep->ep.maxpacket)
+ is_last = 1;
+ else if (req->req.length == req->req.actual
+ && !req->req.zero)
+ is_last = 1;
+ else
+ is_last = 0;
+
+ /* NOTE: requests complete when all IN data is in a
+ * FIFO (or sometimes later, if a zlp was needed).
+ * Use usb_ep_fifo_status() where needed.
+ */
+ if (is_last)
+ done(ep, req, 0);
+ return is_last;
+}
+
+static inline int
+read_packet(u8 *buf, struct omap_req *req, unsigned avail)
+{
+ unsigned len;
+ u16 *wp;
+
+ len = min(req->req.length - req->req.actual, avail);
+ req->req.actual += len;
+ avail = len;
+
+ if (likely((((int)buf) & 1) == 0)) {
+ wp = (u16 *)buf;
+ while (avail >= 2) {
+ *wp++ = UDC_DATA_REG;
+ avail -= 2;
+ }
+ buf = (u8 *)wp;
+ }
+ while (avail--)
+ *buf++ = *(volatile u8 *)&UDC_DATA_REG;
+ return len;
+}
+
+// return: 0 = still running, 1 = queue empty, negative = errno
+static int read_fifo(struct omap_ep *ep, struct omap_req *req)
+{
+ u8 *buf;
+ unsigned count, avail;
+ int is_last;
+
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+
+ for (;;) {
+ u16 ep_stat = UDC_STAT_FLG_REG;
+
+ is_last = 0;
+ if (ep_stat & FIFO_UNREADABLE)
+ break;
+
+ if (ep_stat & (UDC_NON_ISO_FIFO_FULL|UDC_ISO_FIFO_FULL))
+ avail = ep->ep.maxpacket;
+ else
+ avail = UDC_RXFSTAT_REG;
+ count = read_packet(buf, req, avail);
+
+ // FIXME double buffered PIO OUT wasn't behaving...
+
+ /* partial packet reads may not be errors */
+ if (count < ep->ep.maxpacket) {
+ is_last = 1;
+ /* overflowed this request? flush extra data */
+ if (count != avail) {
+ req->req.status = -EOVERFLOW;
+ avail -= count;
+ while (avail--)
+ (void) *(volatile u8 *)&UDC_DATA_REG;
+ }
+ } else if (req->req.length == req->req.actual)
+ is_last = 1;
+ else
+ is_last = 0;
+
+ if (!ep->bEndpointAddress)
+ break;
+ if (!ep->double_buf) {
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ if (!is_last)
+ break;
+ }
+
+ if (is_last) {
+ done(ep, req, 0);
+ if (list_empty(&ep->queue) || !ep->double_buf)
+ break;
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ is_last = 0;
+ }
+ }
+ return is_last;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Each USB transfer request using DMA maps to one or more DMA transfers.
+ * When DMA completion isn't request completion, the UDC continues with
+ * the next DMA transfer for that USB transfer.
+ */
+
+static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
+{
+ u16 txdma_ctrl;
+ unsigned length = req->req.length - req->req.actual;
+
+ /* measure length in either bytes or packets */
+ if (length <= (UDC_TXN_TSC + 1)) {
+ txdma_ctrl = UDC_TXN_EOT | length;
+ omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
+ length, 1, OMAP_DMA_SYNC_ELEMENT);
+ } else {
+ length = max(length / ep->maxpacket,
+ (unsigned) UDC_TXN_TSC + 1);
+ txdma_ctrl = length;
+ omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
+ ep->ep.maxpacket, length,
+ OMAP_DMA_SYNC_ELEMENT);
+ length *= ep->maxpacket;
+ }
+
+ omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
+ OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
+
+ omap_start_dma(ep->lch);
+ UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
+ UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
+ req->dma_bytes = length;
+}
+
+static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
+{
+ if (status == 0) {
+ req->req.actual += req->dma_bytes;
+
+ /* return if this request needs to send data or zlp */
+ if (req->req.actual < req->req.length)
+ return;
+ if (req->req.zero
+ && req->dma_bytes != 0
+ && (req->req.actual % ep->maxpacket) == 0)
+ return;
+ } else {
+ u32 last;
+
+ // FIXME this surely isn't #bytes transferred
+ last = (omap_readw(OMAP_DMA_CSSA_U(ep->lch)) << 16)
+ | omap_readw(OMAP_DMA_CSSA_L(ep->lch));
+ req->req.actual = last - req->req.dma;
+ }
+
+ /* tx completion */
+ omap_stop_dma(ep->lch);
+ UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
+ done(ep, req, status);
+}
+
+static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
+{
+ unsigned packets;
+
+ /* NOTE: we filtered out "short reads" before, so we know
+ * the buffer has only whole numbers of packets.
+ */
+
+ /* set up this DMA transfer, enable the fifo, start */
+ packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
+ packets = min(packets, (unsigned)UDC_RXN_TC + 1);
+ req->dma_bytes = packets * ep->ep.maxpacket;
+ omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
+ ep->ep.maxpacket, packets,
+ OMAP_DMA_SYNC_ELEMENT);
+ omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
+ OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
+
+ UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
+ UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
+ UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+
+ omap_start_dma(ep->lch);
+}
+
+static void
+finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status)
+{
+ u16 count;
+
+ /* FIXME must be a better way to see how much dma
+ * happened, even when it never got going...
+ */
+ count = omap_readw(OMAP_DMA_CDAC(ep->lch));
+ count -= 0xffff & (req->req.dma + req->req.actual);
+ count += req->req.actual;
+ if (count <= req->req.length)
+ req->req.actual = count;
+
+ if (count != req->dma_bytes || status)
+ omap_stop_dma(ep->lch);
+
+ /* if this wasn't short, request may need another transfer */
+ else if (req->req.actual < req->req.length)
+ return;
+
+ /* rx completion */
+ UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
+ done(ep, req, status);
+}
+
+static void dma_irq(struct omap_udc *udc, u16 irq_src)
+{
+ u16 dman_stat = UDC_DMAN_STAT_REG;
+ struct omap_ep *ep;
+ struct omap_req *req;
+
+ /* IN dma: tx to host */
+ if (irq_src & UDC_TXN_DONE) {
+ ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
+ ep->irqs++;
+ /* can see TXN_DONE after dma abort */
+ if (!list_empty(&ep->queue)) {
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ finish_in_dma(ep, req, 0);
+ }
+ UDC_IRQ_SRC_REG = UDC_TXN_DONE;
+
+ if (!list_empty (&ep->queue)) {
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ next_in_dma(ep, req);
+ }
+ }
+
+ /* OUT dma: rx from host */
+ if (irq_src & UDC_RXN_EOT) {
+ ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
+ ep->irqs++;
+ /* can see RXN_EOT after dma abort */
+ if (!list_empty(&ep->queue)) {
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ finish_out_dma(ep, req, 0);
+ }
+ UDC_IRQ_SRC_REG = UDC_RXN_EOT;
+
+ if (!list_empty (&ep->queue)) {
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ next_out_dma(ep, req);
+ }
+ }
+
+ if (irq_src & UDC_RXN_CNT) {
+ ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
+ DBG("%s, RX_CNT irq?\n", ep->ep.name);
+ UDC_IRQ_SRC_REG = UDC_RXN_CNT;
+ }
+}
+
+static void dma_error(int lch, u16 ch_status, void *data)
+{
+ struct omap_ep *ep = data;
+
+ /* if ch_status & OMAP_DMA_DROP_IRQ ... */
+ /* if ch_status & OMAP_DMA_TOUT_IRQ ... */
+ ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
+
+ /* complete current transfer ... */
+}
+
+static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
+{
+ u16 reg;
+ int status, restart, is_in;
+
+ is_in = ep->bEndpointAddress & USB_DIR_IN;
+ if (is_in)
+ reg = UDC_TXDMA_CFG_REG;
+ else
+ reg = UDC_RXDMA_CFG_REG;
+ reg |= 1 << 12; /* "pulse" activated */
+
+ ep->dma_channel = 0;
+ ep->lch = -1;
+ if (channel == 0 || channel > 3) {
+ if ((reg & 0x0f00) == 0)
+ channel = 3;
+ else if ((reg & 0x00f0) == 0)
+ channel = 2;
+ else if ((reg & 0x000f) == 0) /* preferred for ISO */
+ channel = 1;
+ else {
+ status = -EMLINK;
+ goto just_restart;
+ }
+ }
+ reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
+ ep->dma_channel = channel;
+
+ if (is_in) {
+ status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
+ ep->ep.name, dma_error, ep, &ep->lch);
+ if (status == 0) {
+ UDC_TXDMA_CFG_REG = reg;
+ omap_set_dma_dest_params(ep->lch,
+ OMAP_DMA_PORT_TIPB,
+ OMAP_DMA_AMODE_CONSTANT,
+ (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
+ }
+ } else {
+ status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
+ ep->ep.name, dma_error, ep, &ep->lch);
+ if (status == 0) {
+ UDC_RXDMA_CFG_REG = reg;
+ omap_set_dma_src_params(ep->lch,
+ OMAP_DMA_PORT_TIPB,
+ OMAP_DMA_AMODE_CONSTANT,
+ (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
+ }
+ }
+ if (status)
+ ep->dma_channel = 0;
+ else {
+ ep->has_dma = 1;
+ omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
+
+ /* channel type P: hw synch (fifo) */
+ omap_writew(2, OMAP_DMA_LCH_CTRL(ep->lch));
+ }
+
+just_restart:
+ /* restart any queue, even if the claim failed */
+ restart = !ep->stopped && !list_empty(&ep->queue);
+
+ if (status)
+ DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
+ restart ? " (restart)" : "");
+ else
+ DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
+ is_in ? 't' : 'r',
+ ep->dma_channel - 1, ep->lch,
+ restart ? " (restart)" : "");
+
+ if (restart) {
+ struct omap_req *req;
+ req = container_of(ep->queue.next, struct omap_req, queue);
+ if (ep->has_dma)
+ (is_in ? next_in_dma : next_out_dma)(ep, req);
+ else {
+ use_ep(ep, UDC_EP_SEL);
+ (is_in ? write_fifo : read_fifo)(ep, req);
+ deselect_ep();
+ /* IN: 6 wait states before it'll tx */
+ }
+ }
+}
+
+static void dma_channel_release(struct omap_ep *ep)
+{
+ int shift = 4 * (ep->dma_channel - 1);
+ u16 mask = 0x0f << shift;
+ struct omap_req *req;
+ int active;
+
+ /* abort any active usb transfer request */
+ if (!list_empty(&ep->queue))
+ req = container_of(ep->queue.next, struct omap_req, queue);
+ else
+ req = 0;
+
+ active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0;
+
+ DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
+ active ? "active" : "idle",
+ (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
+ ep->dma_channel - 1, req);
+
+ /* wait till current packet DMA finishes, and fifo empties */
+ if (ep->bEndpointAddress & USB_DIR_IN) {
+ UDC_TXDMA_CFG_REG &= ~mask;
+
+ if (req) {
+ if (active)
+ udelay(50);
+ finish_in_dma(ep, req, -ECONNRESET);
+ if (UDC_TXDMA_CFG_REG & mask)
+ WARN("%s, SPIN abort TX dma\n", ep->ep.name);
+ }
+
+ /* host may empty the fifo (or not...) */
+ while (UDC_TXDMA_CFG_REG & mask)
+ udelay(10);
+
+ } else {
+ UDC_RXDMA_CFG_REG &= ~mask;
+
+ /* dma empties the fifo */
+ while (active && (UDC_RXDMA_CFG_REG & mask))
+ udelay(10);
+ omap_stop_dma(ep->lch);
+ if (req)
+ finish_out_dma(ep, req, -ECONNRESET);
+ }
+ omap_free_dma(ep->lch);
+ ep->dma_channel = 0;
+ ep->lch = -1;
+ /* has_dma still set, till endpoint is fully quiesced */
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int
+omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
+{
+ struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
+ struct omap_req *req = container_of(_req, struct omap_req, req);
+ struct omap_udc *udc;
+ unsigned long flags;
+ int is_iso = 0;
+
+ /* catch various bogus parameters */
+ if (!_req || !req->req.complete || !req->req.buf
+ || !list_empty(&req->queue)) {
+ DBG("%s, bad params\n", __FUNCTION__);
+ return -EINVAL;
+ }
+ if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
+ DBG("%s, bad ep\n", __FUNCTION__);
+ return -EINVAL;
+ }
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ if (req->req.length > ep->ep.maxpacket)
+ return -EMSGSIZE;
+ is_iso = 1;
+ }
+
+ /* this isn't bogus, but OMAP DMA isn't the only hardware to
+ * have a hard time with partial packet reads... reject it.
+ */
+ if (use_dma
+ && ep->has_dma
+ && ep->bEndpointAddress != 0
+ && (ep->bEndpointAddress & USB_DIR_IN) == 0
+ && (req->req.length % ep->ep.maxpacket) != 0) {
+ DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
+ return -EMSGSIZE;
+ }
+
+ udc = ep->udc;
+ if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ if (use_dma && ep->has_dma) {
+ if (req->req.dma == DMA_ADDR_INVALID) {
+ req->req.dma = dma_map_single(
+ ep->udc->gadget.dev.parent,
+ req->req.buf,
+ req->req.length,
+ (ep->bEndpointAddress & USB_DIR_IN)
+ ? DMA_TO_DEVICE
+ : DMA_FROM_DEVICE);
+ req->mapped = 1;
+ } else {
+ dma_sync_single_for_device(
+ ep->udc->gadget.dev.parent,
+ req->req.dma, req->req.length,
+ (ep->bEndpointAddress & USB_DIR_IN)
+ ? DMA_TO_DEVICE
+ : DMA_FROM_DEVICE);
+ req->mapped = 0;
+ }
+ }
+
+ VDBG("%s queue req %p, len %d buf %p\n",
+ ep->ep.name, _req, _req->length, _req->buf);
+
+ spin_lock_irqsave(&udc->lock, flags);
+
+ req->req.status = -EINPROGRESS;
+ req->req.actual = 0;
+
+ /* maybe kickstart non-iso i/o queues */
+ if (is_iso)
+ UDC_IRQ_EN_REG |= UDC_SOF_IE;
+ else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
+ int is_in;
+
+ if (ep->bEndpointAddress == 0) {
+ if (!udc->ep0_pending || !list_empty (&ep->queue)) {
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return -EL2HLT;
+ }
+
+ /* empty DATA stage? */
+ is_in = udc->ep0_in;
+ if (!req->req.length) {
+
+ /* chip became CONFIGURED or ADDRESSED
+ * earlier; drivers may already have queued
+ * requests to non-control endpoints
+ */
+ if (udc->ep0_set_config) {
+ u16 irq_en = UDC_IRQ_EN_REG;
+
+ irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
+ if (!udc->ep0_reset_config)
+ irq_en |= UDC_EPN_RX_IE
+ | UDC_EPN_TX_IE;
+ UDC_IRQ_EN_REG = irq_en;
+ }
+
+ /* STATUS is reverse direction */
+ UDC_EP_NUM_REG = is_in
+ ? UDC_EP_SEL
+ : (UDC_EP_SEL|UDC_EP_DIR);
+ UDC_CTRL_REG = UDC_CLR_EP;
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ UDC_EP_NUM_REG = udc->ep0_in ? 0 : UDC_EP_DIR;
+
+ /* cleanup */
+ udc->ep0_pending = 0;
+ done(ep, req, 0);
+ req = 0;
+
+ /* non-empty DATA stage */
+ } else if (is_in) {
+ UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+ } else {
+ if (udc->ep0_setup)
+ goto irq_wait;
+ UDC_EP_NUM_REG = UDC_EP_SEL;
+ }
+ } else {
+ is_in = ep->bEndpointAddress & USB_DIR_IN;
+ if (!ep->has_dma)
+ use_ep(ep, UDC_EP_SEL);
+ /* if ISO: SOF IRQs must be enabled/disabled! */
+ }
+
+ if (ep->has_dma)
+ (is_in ? next_in_dma : next_out_dma)(ep, req);
+ else if (req) {
+ if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
+ req = 0;
+ deselect_ep();
+ /* IN: 6 wait states before it'll tx */
+ }
+ }
+
+irq_wait:
+ /* irq handler advances the queue */
+ if (req != 0)
+ list_add_tail(&req->queue, &ep->queue);
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ return 0;
+}
+
+static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
+ struct omap_req *req;
+ unsigned long flags;
+
+ if (!_ep || !_req)
+ return -EINVAL;
+
+ spin_lock_irqsave(&ep->udc->lock, flags);
+
+ /* make sure it's actually queued on this endpoint */
+ list_for_each_entry (req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+ if (&req->req != _req) {
+ spin_unlock_irqrestore(&ep->udc->lock, flags);
+ return -EINVAL;
+ }
+
+ if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
+ int channel = ep->dma_channel;
+
+ /* releasing the dma completion cancels the request,
+ * reclaiming the channel restarts the queue
+ */
+ dma_channel_release(ep);
+ dma_channel_claim(ep, channel);
+ } else
+ done(ep, req, -ECONNRESET);
+ spin_unlock_irqrestore(&ep->udc->lock, flags);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int omap_ep_set_halt(struct usb_ep *_ep, int value)
+{
+ struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
+ unsigned long flags;
+ int status = -EOPNOTSUPP;
+
+ spin_lock_irqsave(&ep->udc->lock, flags);
+
+ /* just use protocol stalls for ep0; real halts are annoying */
+ if (ep->bEndpointAddress == 0) {
+ if (!ep->udc->ep0_pending)
+ status = -EINVAL;
+ else if (value) {
+ if (ep->udc->ep0_set_config) {
+ WARN("error changing config?\n");
+ UDC_SYSCON2_REG = UDC_CLR_CFG;
+ }
+ UDC_SYSCON2_REG = UDC_STALL_CMD;
+ ep->udc->ep0_pending = 0;
+ status = 0;
+ } else /* NOP */
+ status = 0;
+
+ /* otherwise, all active non-ISO endpoints can halt */
+ } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
+
+ /* IN endpoints must already be idle */
+ if ((ep->bEndpointAddress & USB_DIR_IN)
+ && !list_empty(&ep->queue)) {
+ status = -EAGAIN;
+ goto done;
+ }
+
+ if (value) {
+ int channel;
+
+ if (use_dma && ep->dma_channel
+ && !list_empty(&ep->queue)) {
+ channel = ep->dma_channel;
+ dma_channel_release(ep);
+ } else
+ channel = 0;
+
+ use_ep(ep, UDC_EP_SEL);
+ if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
+ UDC_CTRL_REG = UDC_SET_HALT;
+ status = 0;
+ } else
+ status = -EAGAIN;
+ deselect_ep();
+
+ if (channel)
+ dma_channel_claim(ep, channel);
+ } else {
+ use_ep(ep, 0);
+ UDC_CTRL_REG = UDC_RESET_EP;
+ ep->ackwait = 0;
+ if (!(ep->bEndpointAddress & USB_DIR_IN))
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ }
+ }
+done:
+ VDBG("%s %s halt stat %d\n", ep->ep.name,
+ value ? "set" : "clear", status);
+
+ spin_unlock_irqrestore(&ep->udc->lock, flags);
+ return status;
+}
+
+static struct usb_ep_ops omap_ep_ops = {
+ .enable = omap_ep_enable,
+ .disable = omap_ep_disable,
+
+ .alloc_request = omap_alloc_request,
+ .free_request = omap_free_request,
+
+ .alloc_buffer = omap_alloc_buffer,
+ .free_buffer = omap_free_buffer,
+
+ .queue = omap_ep_queue,
+ .dequeue = omap_ep_dequeue,
+
+ .set_halt = omap_ep_set_halt,
+ // fifo_status ... report bytes in fifo
+ // fifo_flush ... flush fifo
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int omap_get_frame(struct usb_gadget *gadget)
+{
+ u16 sof = UDC_SOF_REG;
+ return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
+}
+
+static int omap_wakeup(struct usb_gadget *gadget)
+{
+ struct omap_udc *udc;
+ unsigned long flags;
+ int retval = -EHOSTUNREACH;
+
+ udc = container_of(gadget, struct omap_udc, gadget);
+
+ spin_lock_irqsave(&udc->lock, flags);
+ if (udc->devstat & UDC_SUS) {
+ /* NOTE: OTG spec erratum says that OTG devices may
+ * issue wakeups without host enable.
+ */
+ if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
+ DBG("remote wakeup...\n");
+ UDC_SYSCON2_REG = UDC_RMT_WKP;
+ retval = 0;
+ }
+
+ /* NOTE: non-OTG systems may use SRP TOO... */
+ } else if (!(udc->devstat & UDC_ATT)) {
+ if (udc->transceiver)
+ retval = otg_start_srp(udc->transceiver);
+ }
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ return retval;
+}
+
+static int
+omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
+{
+ struct omap_udc *udc;
+ unsigned long flags;
+ u16 syscon1;
+
+ udc = container_of(gadget, struct omap_udc, gadget);
+ spin_lock_irqsave(&udc->lock, flags);
+ syscon1 = UDC_SYSCON1_REG;
+ if (is_selfpowered)
+ syscon1 |= UDC_SELF_PWR;
+ else
+ syscon1 &= ~UDC_SELF_PWR;
+ UDC_SYSCON1_REG = syscon1;
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ return 0;
+}
+
+static int can_pullup(struct omap_udc *udc)
+{
+ return udc->driver && udc->softconnect && udc->vbus_active;
+}
+
+static void pullup_enable(struct omap_udc *udc)
+{
+ UDC_SYSCON1_REG |= UDC_PULLUP_EN;
+#ifndef CONFIG_USB_OTG
+ OTG_CTRL_REG |= OTG_BSESSVLD;
+#endif
+ UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
+}
+
+static void pullup_disable(struct omap_udc *udc)
+{
+#ifndef CONFIG_USB_OTG
+ OTG_CTRL_REG &= ~OTG_BSESSVLD;
+#endif
+ UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
+ UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
+}
+
+/*
+ * Called by whatever detects VBUS sessions: external transceiver
+ * driver, or maybe GPIO0 VBUS IRQ.
+ */
+static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+ struct omap_udc *udc;
+ unsigned long flags;
+
+ udc = container_of(gadget, struct omap_udc, gadget);
+ spin_lock_irqsave(&udc->lock, flags);
+ VDBG("VBUS %s\n", is_active ? "on" : "off");
+ udc->vbus_active = (is_active != 0);
+ if (can_pullup(udc))
+ pullup_enable(udc);
+ else
+ pullup_disable(udc);
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return 0;
+}
+
+static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
+{
+ struct omap_udc *udc;
+
+ udc = container_of(gadget, struct omap_udc, gadget);
+ if (udc->transceiver)
+ return otg_set_power(udc->transceiver, mA);
+ return -EOPNOTSUPP;
+}
+
+static int omap_pullup(struct usb_gadget *gadget, int is_on)
+{
+ struct omap_udc *udc;
+ unsigned long flags;
+
+ udc = container_of(gadget, struct omap_udc, gadget);
+ spin_lock_irqsave(&udc->lock, flags);
+ udc->softconnect = (is_on != 0);
+ if (can_pullup(udc))
+ pullup_enable(udc);
+ else
+ pullup_disable(udc);
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return 0;
+}
+
+static struct usb_gadget_ops omap_gadget_ops = {
+ .get_frame = omap_get_frame,
+ .wakeup = omap_wakeup,
+ .set_selfpowered = omap_set_selfpowered,
+ .vbus_session = omap_vbus_session,
+ .vbus_draw = omap_vbus_draw,
+ .pullup = omap_pullup,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* dequeue ALL requests; caller holds udc->lock */
+static void nuke(struct omap_ep *ep, int status)
+{
+ struct omap_req *req;
+
+ ep->stopped = 1;
+
+ if (use_dma && ep->dma_channel)
+ dma_channel_release(ep);
+
+ use_ep(ep, 0);
+ UDC_CTRL_REG = UDC_CLR_EP;
+ if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
+ UDC_CTRL_REG = UDC_SET_HALT;
+
+ while (!list_empty(&ep->queue)) {
+ req = list_entry(ep->queue.next, struct omap_req, queue);
+ done(ep, req, status);
+ }
+}
+
+/* caller holds udc->lock */
+static void udc_quiesce(struct omap_udc *udc)
+{
+ struct omap_ep *ep;
+
+ udc->gadget.speed = USB_SPEED_UNKNOWN;
+ nuke(&udc->ep[0], -ESHUTDOWN);
+ list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
+ nuke(ep, -ESHUTDOWN);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void update_otg(struct omap_udc *udc)
+{
+ u16 devstat;
+
+ if (!udc->gadget.is_otg)
+ return;
+
+ if (OTG_CTRL_REG & OTG_ID)
+ devstat = UDC_DEVSTAT_REG;
+ else
+ devstat = 0;
+
+ udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
+ udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
+ udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
+
+ /* Enable HNP early, avoiding races on suspend irq path.
+ * ASSUMES OTG state machine B_BUS_REQ input is true.
+ */
+ if (udc->gadget.b_hnp_enable)
+ OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
+ & ~OTG_PULLUP;
+}
+
+static void ep0_irq(struct omap_udc *udc, u16 irq_src)
+{
+ struct omap_ep *ep0 = &udc->ep[0];
+ struct omap_req *req = 0;
+
+ ep0->irqs++;
+
+ /* Clear any pending requests and then scrub any rx/tx state
+ * before starting to handle the SETUP request.
+ */
+ if (irq_src & UDC_SETUP)
+ nuke(ep0, 0);
+
+ /* IN/OUT packets mean we're in the DATA or STATUS stage.
+ * This driver uses only uses protocol stalls (ep0 never halts),
+ * and if we got this far the gadget driver already had a
+ * chance to stall. Tries to be forgiving of host oddities.
+ *
+ * NOTE: the last chance gadget drivers have to stall control
+ * requests is during their request completion callback.
+ */
+ if (!list_empty(&ep0->queue))
+ req = container_of(ep0->queue.next, struct omap_req, queue);
+
+ /* IN == TX to host */
+ if (irq_src & UDC_EP0_TX) {
+ int stat;
+
+ UDC_IRQ_SRC_REG = UDC_EP0_TX;
+ UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+ stat = UDC_STAT_FLG_REG;
+ if (stat & UDC_ACK) {
+ if (udc->ep0_in) {
+ /* write next IN packet from response,
+ * or set up the status stage.
+ */
+ if (req)
+ stat = write_fifo(ep0, req);
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ if (!req && udc->ep0_pending) {
+ UDC_EP_NUM_REG = UDC_EP_SEL;
+ UDC_CTRL_REG = UDC_CLR_EP;
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ UDC_EP_NUM_REG = 0;
+ udc->ep0_pending = 0;
+ } /* else: 6 wait states before it'll tx */
+ } else {
+ /* ack status stage of OUT transfer */
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ if (req)
+ done(ep0, req, 0);
+ }
+ req = 0;
+ } else if (stat & UDC_STALL) {
+ UDC_CTRL_REG = UDC_CLR_HALT;
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ } else {
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ }
+ }
+
+ /* OUT == RX from host */
+ if (irq_src & UDC_EP0_RX) {
+ int stat;
+
+ UDC_IRQ_SRC_REG = UDC_EP0_RX;
+ UDC_EP_NUM_REG = UDC_EP_SEL;
+ stat = UDC_STAT_FLG_REG;
+ if (stat & UDC_ACK) {
+ if (!udc->ep0_in) {
+ stat = 0;
+ /* read next OUT packet of request, maybe
+ * reactiviting the fifo; stall on errors.
+ */
+ if (!req || (stat = read_fifo(ep0, req)) < 0) {
+ UDC_SYSCON2_REG = UDC_STALL_CMD;
+ udc->ep0_pending = 0;
+ stat = 0;
+ } else if (stat == 0)
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ UDC_EP_NUM_REG = 0;
+
+ /* activate status stage */
+ if (stat == 1) {
+ done(ep0, req, 0);
+ /* that may have STALLed ep0... */
+ UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+ UDC_CTRL_REG = UDC_CLR_EP;
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ udc->ep0_pending = 0;
+ }
+ } else {
+ /* ack status stage of IN transfer */
+ UDC_EP_NUM_REG = 0;
+ if (req)
+ done(ep0, req, 0);
+ }
+ } else if (stat & UDC_STALL) {
+ UDC_CTRL_REG = UDC_CLR_HALT;
+ UDC_EP_NUM_REG = 0;
+ } else {
+ UDC_EP_NUM_REG = 0;
+ }
+ }
+
+ /* SETUP starts all control transfers */
+ if (irq_src & UDC_SETUP) {
+ union u {
+ u16 word[4];
+ struct usb_ctrlrequest r;
+ } u;
+ int status = -EINVAL;
+ struct omap_ep *ep;
+
+ /* read the (latest) SETUP message */
+ do {
+ UDC_EP_NUM_REG = UDC_SETUP_SEL;
+ /* two bytes at a time */
+ u.word[0] = UDC_DATA_REG;
+ u.word[1] = UDC_DATA_REG;
+ u.word[2] = UDC_DATA_REG;
+ u.word[3] = UDC_DATA_REG;
+ UDC_EP_NUM_REG = 0;
+ } while (UDC_IRQ_SRC_REG & UDC_SETUP);
+ le16_to_cpus (&u.r.wValue);
+ le16_to_cpus (&u.r.wIndex);
+ le16_to_cpus (&u.r.wLength);
+
+ /* Delegate almost all control requests to the gadget driver,
+ * except for a handful of ch9 status/feature requests that
+ * hardware doesn't autodecode _and_ the gadget API hides.
+ */
+ udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
+ udc->ep0_set_config = 0;
+ udc->ep0_pending = 1;
+ ep0->stopped = 0;
+ ep0->ackwait = 0;
+ switch (u.r.bRequest) {
+ case USB_REQ_SET_CONFIGURATION:
+ /* udc needs to know when ep != 0 is valid */
+ if (u.r.bRequestType != USB_RECIP_DEVICE)
+ goto delegate;
+ if (u.r.wLength != 0)
+ goto do_stall;
+ udc->ep0_set_config = 1;
+ udc->ep0_reset_config = (u.r.wValue == 0);
+ VDBG("set config %d\n", u.r.wValue);
+
+ /* update udc NOW since gadget driver may start
+ * queueing requests immediately; clear config
+ * later if it fails the request.
+ */
+ if (udc->ep0_reset_config)
+ UDC_SYSCON2_REG = UDC_CLR_CFG;
+ else
+ UDC_SYSCON2_REG = UDC_DEV_CFG;
+ update_otg(udc);
+ goto delegate;
+ case USB_REQ_CLEAR_FEATURE:
+ /* clear endpoint halt */
+ if (u.r.bRequestType != USB_RECIP_ENDPOINT)
+ goto delegate;
+ if (u.r.wValue != USB_ENDPOINT_HALT
+ || u.r.wLength != 0)
+ goto do_stall;
+ ep = &udc->ep[u.r.wIndex & 0xf];
+ if (ep != ep0) {
+ if (u.r.wIndex & USB_DIR_IN)
+ ep += 16;
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ || !ep->desc)
+ goto do_stall;
+ use_ep(ep, 0);
+ UDC_CTRL_REG = UDC_RESET_EP;
+ ep->ackwait = 0;
+ if (!(ep->bEndpointAddress & USB_DIR_IN))
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ }
+ VDBG("%s halt cleared by host\n", ep->name);
+ goto ep0out_status_stage;
+ case USB_REQ_SET_FEATURE:
+ /* set endpoint halt */
+ if (u.r.bRequestType != USB_RECIP_ENDPOINT)
+ goto delegate;
+ if (u.r.wValue != USB_ENDPOINT_HALT
+ || u.r.wLength != 0)
+ goto do_stall;
+ ep = &udc->ep[u.r.wIndex & 0xf];
+ if (u.r.wIndex & USB_DIR_IN)
+ ep += 16;
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ || ep == ep0 || !ep->desc)
+ goto do_stall;
+ if (use_dma && ep->has_dma) {
+ /* this has rude side-effects (aborts) and
+ * can't really work if DMA-IN is active
+ */
+ DBG("%s host set_halt, NYET \n", ep->name);
+ goto do_stall;
+ }
+ use_ep(ep, 0);
+ /* can't halt if fifo isn't empty... */
+ UDC_CTRL_REG = UDC_CLR_EP;
+ UDC_CTRL_REG = UDC_SET_HALT;
+ VDBG("%s halted by host\n", ep->name);
+ep0out_status_stage:
+ status = 0;
+ UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+ UDC_CTRL_REG = UDC_CLR_EP;
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ udc->ep0_pending = 0;
+ break;
+ case USB_REQ_GET_STATUS:
+ /* return interface status. if we were pedantic,
+ * we'd detect non-existent interfaces, and stall.
+ */
+ if (u.r.bRequestType
+ != (USB_DIR_IN|USB_RECIP_INTERFACE))
+ goto delegate;
+ /* return two zero bytes */
+ UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+ UDC_DATA_REG = 0;
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ UDC_EP_NUM_REG = UDC_EP_DIR;
+ status = 0;
+ VDBG("GET_STATUS, interface %d\n", u.r.wIndex);
+ /* next, status stage */
+ break;
+ default:
+delegate:
+ /* activate the ep0out fifo right away */
+ if (!udc->ep0_in && u.r.wLength) {
+ UDC_EP_NUM_REG = 0;
+ UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ }
+
+ /* gadget drivers see class/vendor specific requests,
+ * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
+ * and more
+ */
+ VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
+ u.r.bRequestType, u.r.bRequest,
+ u.r.wValue, u.r.wIndex, u.r.wLength);
+
+ /* The gadget driver may return an error here,
+ * causing an immediate protocol stall.
+ *
+ * Else it must issue a response, either queueing a
+ * response buffer for the DATA stage, or halting ep0
+ * (causing a protocol stall, not a real halt). A
+ * zero length buffer means no DATA stage.
+ *
+ * It's fine to issue that response after the setup()
+ * call returns, and this IRQ was handled.
+ */
+ udc->ep0_setup = 1;
+ spin_unlock(&udc->lock);
+ status = udc->driver->setup (&udc->gadget, &u.r);
+ spin_lock(&udc->lock);
+ udc->ep0_setup = 0;
+ }
+
+ if (status < 0) {
+do_stall:
+ VDBG("req %02x.%02x protocol STALL; stat %d\n",
+ u.r.bRequestType, u.r.bRequest, status);
+ if (udc->ep0_set_config) {
+ if (udc->ep0_reset_config)
+ WARN("error resetting config?\n");
+ else
+ UDC_SYSCON2_REG = UDC_CLR_CFG;
+ }
+ UDC_SYSCON2_REG = UDC_STALL_CMD;
+ udc->ep0_pending = 0;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
+
+static void devstate_irq(struct omap_udc *udc, u16 irq_src)
+{
+ u16 devstat, change;
+
+ devstat = UDC_DEVSTAT_REG;
+ change = devstat ^ udc->devstat;
+ udc->devstat = devstat;
+
+ if (change & (UDC_USB_RESET|UDC_ATT)) {
+ udc_quiesce(udc);
+
+ if (change & UDC_ATT) {
+ /* driver for any external transceiver will
+ * have called omap_vbus_session() already
+ */
+ if (devstat & UDC_ATT) {
+ udc->gadget.speed = USB_SPEED_FULL;
+ VDBG("connect\n");
+ if (!udc->transceiver)
+ pullup_enable(udc);
+ // if (driver->connect) call it
+ } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
+ udc->gadget.speed = USB_SPEED_UNKNOWN;
+ if (!udc->transceiver)
+ pullup_disable(udc);
+ DBG("disconnect, gadget %s\n",
+ udc->driver->driver.name);
+ if (udc->driver->disconnect) {
+ spin_unlock(&udc->lock);
+ udc->driver->disconnect(&udc->gadget);
+ spin_lock(&udc->lock);
+ }
+ }
+ change &= ~UDC_ATT;
+ }
+
+ if (change & UDC_USB_RESET) {
+ if (devstat & UDC_USB_RESET) {
+ VDBG("RESET=1\n");
+ } else {
+ udc->gadget.speed = USB_SPEED_FULL;
+ INFO("USB reset done, gadget %s\n",
+ udc->driver->driver.name);
+ /* ep0 traffic is legal from now on */
+ UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
+ }
+ change &= ~UDC_USB_RESET;
+ }
+ }
+ if (change & UDC_SUS) {
+ if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
+ // FIXME tell isp1301 to suspend/resume (?)
+ if (devstat & UDC_SUS) {
+ VDBG("suspend\n");
+ update_otg(udc);
+ /* HNP could be under way already */
+ if (udc->gadget.speed == USB_SPEED_FULL
+ && udc->driver->suspend) {
+ spin_unlock(&udc->lock);
+ udc->driver->suspend(&udc->gadget);
+ spin_lock(&udc->lock);
+ }
+ } else {
+ VDBG("resume\n");
+ if (udc->gadget.speed == USB_SPEED_FULL
+ && udc->driver->resume) {
+ spin_unlock(&udc->lock);
+ udc->driver->resume(&udc->gadget);
+ spin_lock(&udc->lock);
+ }
+ }
+ }
+ change &= ~UDC_SUS;
+ }
+ if (change & OTG_FLAGS) {
+ update_otg(udc);
+ change &= ~OTG_FLAGS;
+ }
+
+ change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
+ if (change)
+ VDBG("devstat %03x, ignore change %03x\n",
+ devstat, change);
+
+ UDC_IRQ_SRC_REG = UDC_DS_CHG;
+}
+
+static irqreturn_t
+omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
+{
+ struct omap_udc *udc = _udc;
+ u16 irq_src;
+ irqreturn_t status = IRQ_NONE;
+ unsigned long flags;
+
+ spin_lock_irqsave(&udc->lock, flags);
+ irq_src = UDC_IRQ_SRC_REG;
+
+ /* Device state change (usb ch9 stuff) */
+ if (irq_src & UDC_DS_CHG) {
+ devstate_irq(_udc, irq_src);
+ status = IRQ_HANDLED;
+ irq_src &= ~UDC_DS_CHG;
+ }
+
+ /* EP0 control transfers */
+ if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
+ ep0_irq(_udc, irq_src);
+ status = IRQ_HANDLED;
+ irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
+ }
+
+ /* DMA transfer completion */
+ if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
+ dma_irq(_udc, irq_src);
+ status = IRQ_HANDLED;
+ irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
+ }
+
+ irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
+ if (irq_src)
+ DBG("udc_irq, unhandled %03x\n", irq_src);
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ return status;
+}
+
+static irqreturn_t
+omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
+{
+ u16 epn_stat, irq_src;
+ irqreturn_t status = IRQ_NONE;
+ struct omap_ep *ep;
+ int epnum;
+ struct omap_udc *udc = _dev;
+ struct omap_req *req;
+ unsigned long flags;
+
+ spin_lock_irqsave(&udc->lock, flags);
+ epn_stat = UDC_EPN_STAT_REG;
+ irq_src = UDC_IRQ_SRC_REG;
+
+ /* handle OUT first, to avoid some wasteful NAKs */
+ if (irq_src & UDC_EPN_RX) {
+ epnum = (epn_stat >> 8) & 0x0f;
+ UDC_IRQ_SRC_REG = UDC_EPN_RX;
+ status = IRQ_HANDLED;
+ ep = &udc->ep[epnum];
+ ep->irqs++;
+
+ if (!list_empty(&ep->queue)) {
+ UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
+ if ((UDC_STAT_FLG_REG & UDC_ACK)) {
+ int stat;
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ stat = read_fifo(ep, req);
+ // FIXME double buffered PIO OUT should work
+ }
+ UDC_EP_NUM_REG = epnum;
+ }
+ }
+
+ /* then IN transfers */
+ if (irq_src & UDC_EPN_TX) {
+ epnum = epn_stat & 0x0f;
+ UDC_IRQ_SRC_REG = UDC_EPN_TX;
+ status = IRQ_HANDLED;
+ ep = &udc->ep[16 + epnum];
+ ep->irqs++;
+ ep->ackwait = 0;
+
+ if (!list_empty(&ep->queue)) {
+ UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
+ if ((UDC_STAT_FLG_REG & UDC_ACK)) {
+ req = container_of(ep->queue.next,
+ struct omap_req, queue);
+ (void) write_fifo(ep, req);
+ }
+ UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
+ /* 6 wait states before it'll tx */
+ }
+ }
+
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return status;
+}
+
+#ifdef USE_ISO
+static irqreturn_t
+omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
+{
+ struct omap_udc *udc = _dev;
+ struct omap_ep *ep;
+ int pending = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&udc->lock, flags);
+
+ /* handle all non-DMA ISO transfers */
+ list_for_each_entry (ep, &udc->iso, iso) {
+ u16 stat;
+ struct omap_req *req;
+
+ if (ep->has_dma || list_empty(&ep->queue))
+ continue;
+ req = list_entry(ep->queue.next, struct omap_req, queue);
+
+ use_ep(ep, UDC_EP_SEL);
+ stat = UDC_STAT_FLG_REG;
+
+ /* NOTE: like the other controller drivers, this isn't
+ * currently reporting lost or damaged frames.
+ */
+ if (ep->bEndpointAddress & USB_DIR_IN) {
+ if (stat & UDC_MISS_IN)
+ /* done(ep, req, -EPROTO) */;
+ else
+ write_fifo(ep, req);
+ } else {
+ int status = 0;
+
+ if (stat & UDC_NO_RXPACKET)
+ status = -EREMOTEIO;
+ else if (stat & UDC_ISO_ERR)
+ status = -EILSEQ;
+ else if (stat & UDC_DATA_FLUSH)
+ status = -ENOSR;
+
+ if (status)
+ /* done(ep, req, status) */;
+ else
+ read_fifo(ep, req);
+ }
+ deselect_ep();
+ /* 6 wait states before next EP */
+
+ ep->irqs++;
+ if (!list_empty(&ep->queue))
+ pending = 1;
+ }
+ if (!pending)
+ UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
+ UDC_IRQ_SRC_REG = UDC_SOF;
+
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return IRQ_HANDLED;
+}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+static struct omap_udc *udc;
+
+int usb_gadget_register_driver (struct usb_gadget_driver *driver)
+{
+ int status = -ENODEV;
+ struct omap_ep *ep;
+ unsigned long flags;
+
+ /* basic sanity tests */
+ if (!udc)
+ return -ENODEV;
+ if (!driver
+ // FIXME if otg, check: driver->is_otg
+ || driver->speed < USB_SPEED_FULL
+ || !driver->bind
+ || !driver->unbind
+ || !driver->setup)
+ return -EINVAL;
+
+ spin_lock_irqsave(&udc->lock, flags);
+ if (udc->driver) {
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return -EBUSY;
+ }
+
+ /* reset state */
+ list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
+ ep->irqs = 0;
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
+ continue;
+ use_ep(ep, 0);
+ UDC_CTRL_REG = UDC_SET_HALT;
+ }
+ udc->ep0_pending = 0;
+ udc->ep[0].irqs = 0;
+ udc->softconnect = 1;
+
+ /* hook up the driver */
+ driver->driver.bus = 0;
+ udc->driver = driver;
+ udc->gadget.dev.driver = &driver->driver;
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ status = driver->bind (&udc->gadget);
+ if (status) {
+ DBG("bind to %s --> %d\n", driver->driver.name, status);
+ udc->gadget.dev.driver = 0;
+ udc->driver = 0;
+ goto done;
+ }
+ DBG("bound to driver %s\n", driver->driver.name);
+
+ UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
+
+ /* connect to bus through transceiver */
+ if (udc->transceiver) {
+ status = otg_set_peripheral(udc->transceiver, &udc->gadget);
+ if (status < 0) {
+ ERR("can't bind to transceiver\n");
+ driver->unbind (&udc->gadget);
+ udc->gadget.dev.driver = 0;
+ udc->driver = 0;
+ goto done;
+ }
+ } else {
+ if (can_pullup(udc))
+ pullup_enable (udc);
+ else
+ pullup_disable (udc);
+ }
+
+done:
+ return status;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
+{
+ unsigned long flags;
+ int status = -ENODEV;
+
+ if (!udc)
+ return -ENODEV;
+ if (!driver || driver != udc->driver)
+ return -EINVAL;
+
+ if (udc->transceiver)
+ (void) otg_set_peripheral(udc->transceiver, 0);
+ else
+ pullup_disable(udc);
+
+ spin_lock_irqsave(&udc->lock, flags);
+ udc_quiesce(udc);
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ driver->unbind(&udc->gadget);
+ udc->gadget.dev.driver = 0;
+ udc->driver = 0;
+
+
+ DBG("unregistered driver '%s'\n", driver->driver.name);
+ return status;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USB_OMAP_PROC
+
+#include <linux/seq_file.h>
+
+static const char proc_filename[] = "driver/udc";
+
+#define FOURBITS "%s%s%s%s"
+#define EIGHTBITS FOURBITS FOURBITS
+
+static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
+{
+ u16 stat_flg;
+ struct omap_req *req;
+ char buf[20];
+
+ use_ep(ep, 0);
+
+ if (use_dma && ep->has_dma)
+ snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
+ (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
+ ep->dma_channel - 1, ep->lch);
+ else
+ buf[0] = 0;
+
+ stat_flg = UDC_STAT_FLG_REG;
+ seq_printf(s,
+ "\n%s %sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
+ ep->name, buf, ep->irqs, stat_flg,
+ (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
+ (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
+ (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
+ (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
+ (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
+ (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
+ (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
+ (stat_flg & UDC_STALL) ? "STALL " : "",
+ (stat_flg & UDC_NAK) ? "NAK " : "",
+ (stat_flg & UDC_ACK) ? "ACK " : "",
+ (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
+ (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
+ (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
+
+ if (list_empty (&ep->queue))
+ seq_printf(s, "\t(queue empty)\n");
+ else
+ list_for_each_entry (req, &ep->queue, queue)
+ seq_printf(s, "\treq %p len %d/%d buf %p\n",
+ &req->req, req->req.actual,
+ req->req.length, req->req.buf);
+}
+
+static char *trx_mode(unsigned m)
+{
+ switch (m) {
+ case 3:
+ case 0: return "6wire";
+ case 1: return "4wire";
+ case 2: return "3wire";
+ default: return "unknown";
+ }
+}
+
+static int proc_udc_show(struct seq_file *s, void *_)
+{
+ u32 tmp;
+ struct omap_ep *ep;
+ unsigned long flags;
+
+ spin_lock_irqsave(&udc->lock, flags);
+
+ seq_printf(s, "%s, version: " DRIVER_VERSION
+#ifdef USE_ISO
+ " (iso)"
+#endif
+ "%s\n",
+ driver_desc,
+ use_dma ? " (dma)" : "");
+
+ tmp = UDC_REV_REG & 0xff;
+ seq_printf(s,
+ "UDC rev %d.%d, OTG rev %d.%d, fifo mode %d, gadget %s\n"
+ "hmc %d, transceiver %08x %s\n",
+ tmp >> 4, tmp & 0xf,
+ OTG_REV_REG >> 4, OTG_REV_REG & 0xf,
+ fifo_mode,
+ udc->driver ? udc->driver->driver.name : "(none)",
+ HMC, USB_TRANSCEIVER_CTRL_REG,
+ udc->transceiver ? udc->transceiver->label : "");
+
+ /* OTG controller registers */
+ tmp = OTG_SYSCON_1_REG;
+ seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
+ FOURBITS "\n", tmp,
+ trx_mode(USB2_TRX_MODE(tmp)),
+ trx_mode(USB1_TRX_MODE(tmp)),
+ trx_mode(USB0_TRX_MODE(tmp)),
+ (tmp & OTG_IDLE_EN) ? " !otg" : "",
+ (tmp & HST_IDLE_EN) ? " !host" : "",
+ (tmp & DEV_IDLE_EN) ? " !dev" : "",
+ (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
+ tmp = OTG_SYSCON_2_REG;
+ seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
+ " b_ase_brst=%d hmc=%d\n", tmp,
+ (tmp & OTG_EN) ? " otg_en" : "",
+ (tmp & USBX_SYNCHRO) ? " synchro" : "",
+ // much more SRP stuff
+ (tmp & SRP_DATA) ? " srp_data" : "",
+ (tmp & SRP_VBUS) ? " srp_vbus" : "",
+ (tmp & OTG_PADEN) ? " otg_paden" : "",
+ (tmp & HMC_PADEN) ? " hmc_paden" : "",
+ (tmp & UHOST_EN) ? " uhost_en" : "",
+ (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
+ (tmp & HMC_TLLATTACH) ? " tllattach" : "",
+ B_ASE_BRST(tmp),
+ OTG_HMC(tmp));
+ tmp = OTG_CTRL_REG;
+ seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
+ (tmp & OTG_ASESSVLD) ? " asess" : "",
+ (tmp & OTG_BSESSEND) ? " bsess_end" : "",
+ (tmp & OTG_BSESSVLD) ? " bsess" : "",
+ (tmp & OTG_VBUSVLD) ? " vbus" : "",
+ (tmp & OTG_ID) ? " id" : "",
+ (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
+ (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
+ (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
+ (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
+ (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
+ (tmp & OTG_BUSDROP) ? " busdrop" : "",
+ (tmp & OTG_PULLDOWN) ? " down" : "",
+ (tmp & OTG_PULLUP) ? " up" : "",
+ (tmp & OTG_DRV_VBUS) ? " drv" : "",
+ (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
+ (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
+ (tmp & OTG_PU_ID) ? " pu_id" : ""
+ );
+ tmp = OTG_IRQ_EN_REG;
+ seq_printf(s, "otg_irq_en %04x" "\n", tmp);
+ tmp = OTG_IRQ_SRC_REG;
+ seq_printf(s, "otg_irq_src %04x" "\n", tmp);
+ tmp = OTG_OUTCTRL_REG;
+ seq_printf(s, "otg_outctrl %04x" "\n", tmp);
+ tmp = OTG_TEST_REG;
+ seq_printf(s, "otg_test %04x" "\n", tmp);
+
+ tmp = UDC_SYSCON1_REG;
+ seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
+ (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
+ (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
+ (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
+ (tmp & UDC_NAK_EN) ? " nak" : "",
+ (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
+ (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
+ (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
+ (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
+ // syscon2 is write-only
+
+ /* UDC controller registers */
+ if (!(tmp & UDC_PULLUP_EN)) {
+ seq_printf(s, "(suspended)\n");
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return 0;
+ }
+
+ tmp = UDC_DEVSTAT_REG;
+ seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
+ (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
+ (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
+ (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
+ (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
+ (tmp & UDC_USB_RESET) ? " usb_reset" : "",
+ (tmp & UDC_SUS) ? " SUS" : "",
+ (tmp & UDC_CFG) ? " CFG" : "",
+ (tmp & UDC_ADD) ? " ADD" : "",
+ (tmp & UDC_DEF) ? " DEF" : "",
+ (tmp & UDC_ATT) ? " ATT" : "");
+ seq_printf(s, "sof %04x\n", UDC_SOF_REG);
+ tmp = UDC_IRQ_EN_REG;
+ seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
+ (tmp & UDC_SOF_IE) ? " sof" : "",
+ (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
+ (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
+ (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
+ (tmp & UDC_EP0_IE) ? " ep0" : "");
+ tmp = UDC_IRQ_SRC_REG;
+ seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
+ (tmp & UDC_TXN_DONE) ? " txn_done" : "",
+ (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
+ (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
+ (tmp & UDC_SOF) ? " sof" : "",
+ (tmp & UDC_EPN_RX) ? " epn_rx" : "",
+ (tmp & UDC_EPN_TX) ? " epn_tx" : "",
+ (tmp & UDC_DS_CHG) ? " ds_chg" : "",
+ (tmp & UDC_SETUP) ? " setup" : "",
+ (tmp & UDC_EP0_RX) ? " ep0out" : "",
+ (tmp & UDC_EP0_TX) ? " ep0in" : "");
+ if (use_dma) {
+ unsigned i;
+
+ tmp = UDC_DMA_IRQ_EN_REG;
+ seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
+ (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
+ (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
+ (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
+
+ (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
+ (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
+ (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
+
+ (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
+ (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
+ (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
+
+ tmp = UDC_RXDMA_CFG_REG;
+ seq_printf(s, "rxdma_cfg %04x\n", tmp);
+ if (tmp) {
+ for (i = 0; i < 3; i++) {
+ if ((tmp & (0x0f << (i * 4))) == 0)
+ continue;
+ seq_printf(s, "rxdma[%d] %04x\n", i,
+ UDC_RXDMA_REG(i + 1));
+ }
+ }
+ tmp = UDC_TXDMA_CFG_REG;
+ seq_printf(s, "txdma_cfg %04x\n", tmp);
+ if (tmp) {
+ for (i = 0; i < 3; i++) {
+ if (!(tmp & (0x0f << (i * 4))))
+ continue;
+ seq_printf(s, "txdma[%d] %04x\n", i,
+ UDC_TXDMA_REG(i + 1));
+ }
+ }
+ }
+
+ tmp = UDC_DEVSTAT_REG;
+ if (tmp & UDC_ATT) {
+ proc_ep_show(s, &udc->ep[0]);
+ if (tmp & UDC_ADD) {
+ list_for_each_entry (ep, &udc->gadget.ep_list,
+ ep.ep_list) {
+ if (ep->desc)
+ proc_ep_show(s, ep);
+ }
+ }
+ }
+ spin_unlock_irqrestore(&udc->lock, flags);
+ return 0;
+}
+
+static int proc_udc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, proc_udc_show, 0);
+}
+
+static struct file_operations proc_ops = {
+ .open = proc_udc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static void create_proc_file(void)
+{
+ struct proc_dir_entry *pde;
+
+ pde = create_proc_entry (proc_filename, 0, NULL);
+ if (pde)
+ pde->proc_fops = &proc_ops;
+}
+
+static void remove_proc_file(void)
+{
+ remove_proc_entry(proc_filename, 0);
+}
+
+#else
+
+static inline void create_proc_file(void) {}
+static inline void remove_proc_file(void) {}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/* Before this controller can enumerate, we need to pick an endpoint
+ * configuration, or "fifo_mode" That involves allocating 2KB of packet
+ * buffer space among the endpoints we'll be operating.
+ */
+static unsigned __init
+omap_ep_setup(char *name, u8 addr, u8 type,
+ unsigned buf, unsigned maxp, int dbuf)
+{
+ struct omap_ep *ep;
+ u16 epn_rxtx = 0;
+
+ /* OUT endpoints first, then IN */
+ ep = &udc->ep[addr & 0xf];
+ if (addr & USB_DIR_IN)
+ ep += 16;
+
+ /* in case of ep init table bugs */
+ BUG_ON(ep->name[0]);
+
+ /* chip setup ... bit values are same for IN, OUT */
+ if (type == USB_ENDPOINT_XFER_ISOC) {
+ switch (maxp) {
+ case 8: epn_rxtx = 0 << 12; break;
+ case 16: epn_rxtx = 1 << 12; break;
+ case 32: epn_rxtx = 2 << 12; break;
+ case 64: epn_rxtx = 3 << 12; break;
+ case 128: epn_rxtx = 4 << 12; break;
+ case 256: epn_rxtx = 5 << 12; break;
+ case 512: epn_rxtx = 6 << 12; break;
+ default: BUG();
+ }
+ epn_rxtx |= UDC_EPN_RX_ISO;
+ dbuf = 1;
+ } else {
+ /* pio-out could potentially double-buffer,
+ * as can (should!) DMA-IN
+ */
+ if (!use_dma || (addr & USB_DIR_IN))
+ dbuf = 0;
+
+ switch (maxp) {
+ case 8: epn_rxtx = 0 << 12; break;
+ case 16: epn_rxtx = 1 << 12; break;
+ case 32: epn_rxtx = 2 << 12; break;
+ case 64: epn_rxtx = 3 << 12; break;
+ default: BUG();
+ }
+ if (dbuf && addr)
+ epn_rxtx |= UDC_EPN_RX_DB;
+ }
+ if (addr)
+ epn_rxtx |= UDC_EPN_RX_VALID;
+ BUG_ON(buf & 0x07);
+ epn_rxtx |= buf >> 3;
+
+ DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
+ name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
+
+ if (addr & USB_DIR_IN)
+ UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
+ else
+ UDC_EP_RX_REG(addr) = epn_rxtx;
+
+ /* next endpoint's buffer starts after this one's */
+ buf += maxp;
+ if (dbuf)
+ buf += maxp;
+ BUG_ON(buf > 2048);
+
+ /* set up driver data structures */
+ BUG_ON(strlen(name) >= sizeof ep->name);
+ strlcpy(ep->name, name, sizeof ep->name);
+ INIT_LIST_HEAD(&ep->queue);
+ INIT_LIST_HEAD(&ep->iso);
+ ep->bEndpointAddress = addr;
+ ep->bmAttributes = type;
+ ep->double_buf = dbuf;
+ ep->udc = udc;
+
+ ep->ep.name = ep->name;
+ ep->ep.ops = &omap_ep_ops;
+ ep->ep.maxpacket = ep->maxpacket = maxp;
+ list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
+
+ return buf;
+}
+
+static void omap_udc_release(struct device *dev)
+{
+ complete(udc->done);
+ kfree (udc);
+ udc = 0;
+}
+
+static int __init
+omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
+{
+ unsigned tmp, buf;
+
+ /* abolish any previous hardware state */
+ UDC_SYSCON1_REG = 0;
+ UDC_IRQ_EN_REG = 0;
+ UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
+ UDC_DMA_IRQ_EN_REG = 0;
+ UDC_RXDMA_CFG_REG = 0;
+ UDC_TXDMA_CFG_REG = 0;
+
+ /* UDC_PULLUP_EN gates the chip clock */
+ // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
+
+ udc = kmalloc (sizeof *udc, SLAB_KERNEL);
+ if (!udc)
+ return -ENOMEM;
+
+ memset(udc, 0, sizeof *udc);
+ spin_lock_init (&udc->lock);
+
+ udc->gadget.ops = &omap_gadget_ops;
+ udc->gadget.ep0 = &udc->ep[0].ep;
+ INIT_LIST_HEAD(&udc->gadget.ep_list);
+ INIT_LIST_HEAD(&udc->iso);
+ udc->gadget.speed = USB_SPEED_UNKNOWN;
+ udc->gadget.name = driver_name;
+
+ device_initialize(&udc->gadget.dev);
+ strcpy (udc->gadget.dev.bus_id, "gadget");
+ udc->gadget.dev.release = omap_udc_release;
+ udc->gadget.dev.parent = &odev->dev;
+ if (use_dma)
+ udc->gadget.dev.dma_mask = odev->dev.dma_mask;
+
+ udc->transceiver = xceiv;
+
+ /* ep0 is special; put it right after the SETUP buffer */
+ buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
+ 8 /* after SETUP */, 64 /* maxpacket */, 0);
+ list_del_init(&udc->ep[0].ep.ep_list);
+
+ /* initially disable all non-ep0 endpoints */
+ for (tmp = 1; tmp < 15; tmp++) {
+ UDC_EP_RX_REG(tmp) = 0;
+ UDC_EP_TX_REG(tmp) = 0;
+ }
+
+#define OMAP_BULK_EP(name,addr) \
+ buf = omap_ep_setup(name "-bulk", addr, \
+ USB_ENDPOINT_XFER_BULK, buf, 64, 1);
+#define OMAP_INT_EP(name,addr, maxp) \
+ buf = omap_ep_setup(name "-int", addr, \
+ USB_ENDPOINT_XFER_INT, buf, maxp, 0);
+#define OMAP_ISO_EP(name,addr, maxp) \
+ buf = omap_ep_setup(name "-iso", addr, \
+ USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
+
+ switch (fifo_mode) {
+ case 0:
+ OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
+ OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
+ OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
+ break;
+ case 1:
+ OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
+ OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
+ OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
+ OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
+
+ OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
+ OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
+ OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
+ OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
+
+ OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
+ OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
+ OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
+ OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
+
+ OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
+ OMAP_INT_EP("ep10out", USB_DIR_IN | 10, 16);
+ OMAP_INT_EP("ep11in", USB_DIR_IN | 9, 16);
+ OMAP_INT_EP("ep12out", USB_DIR_IN | 10, 16);
+ break;
+
+#ifdef USE_ISO
+ case 2: /* mixed iso/bulk */
+ OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
+ OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
+ OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
+ OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
+
+ OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
+
+ OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
+ OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
+ OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
+ break;
+ case 3: /* mixed bulk/iso */
+ OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
+ OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
+ OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
+
+ OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
+ OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
+ OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
+
+ OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
+ OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
+ OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
+ break;
+#endif
+
+ /* add more modes as needed */
+
+ default:
+ ERR("unsupported fifo_mode #%d\n", fifo_mode);
+ return -ENODEV;
+ }
+ UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
+ INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
+ return 0;
+}
+
+static int __init omap_udc_probe(struct device *dev)
+{
+ struct platform_device *odev = to_platform_device(dev);
+ int status = -ENODEV;
+ int hmc;
+ struct otg_transceiver *xceiv = 0;
+ const char *type = 0;
+ struct omap_usb_config *config = dev->platform_data;
+
+ /* NOTE: "knows" the order of the resources! */
+ if (!request_mem_region(odev->resource[0].start,
+ odev->resource[0].end - odev->resource[0].start + 1,
+ driver_name)) {
+ DBG("request_mem_region failed\n");
+ return -EBUSY;
+ }
+
+ INFO("OMAP UDC rev %d.%d, OTG rev %d.%d, %s receptacle\n",
+ UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
+ OTG_REV_REG >> 4, OTG_REV_REG & 0xf,
+ config->otg ? "Mini-AB" : "B/Mini-B");
+
+ /* use the mode given to us by board init code */
+ hmc = HMC;
+ switch (hmc) {
+ case 3:
+ case 11:
+ case 19:
+ case 25:
+ xceiv = otg_get_transceiver();
+ if (!xceiv) {
+ DBG("external transceiver not registered!\n");
+ goto cleanup0;
+ }
+ type = xceiv->label;
+ break;
+ case 0: /* POWERUP DEFAULT == 0 */
+ case 4:
+ case 12:
+ case 20:
+ type = "INTEGRATED";
+ break;
+ case 21: /* internal loopback */
+ type = "(loopback)";
+ break;
+ case 14: /* transceiverless */
+ type = "(none)";
+ break;
+
+ default:
+ ERR("unrecognized UDC HMC mode %d\n", hmc);
+ return -ENODEV;
+ }
+ INFO("hmc mode %d, transceiver %s\n", hmc, type);
+
+ /* a "gadget" abstracts/virtualizes the controller */
+ status = omap_udc_setup(odev, xceiv);
+ if (status) {
+ goto cleanup0;
+ }
+ xceiv = 0;
+ // "udc" is now valid
+ pullup_disable(udc);
+ udc->gadget.is_otg = (config->otg != 0);
+
+ /* USB general purpose IRQ: ep0, state changes, dma, etc */
+ status = request_irq(odev->resource[1].start, omap_udc_irq,
+ SA_SAMPLE_RANDOM, driver_name, udc);
+ if (status != 0) {
+ ERR( "can't get irq %ld, err %d\n",
+ odev->resource[1].start, status);
+ goto cleanup1;
+ }
+
+ /* USB "non-iso" IRQ (PIO for all but ep0) */
+ status = request_irq(odev->resource[2].start, omap_udc_pio_irq,
+ SA_SAMPLE_RANDOM, "omap_udc pio", udc);
+ if (status != 0) {
+ ERR( "can't get irq %ld, err %d\n",
+ odev->resource[2].start, status);
+ goto cleanup2;
+ }
+#ifdef USE_ISO
+ status = request_irq(odev->resource[3].start, omap_udc_iso_irq,
+ SA_INTERRUPT, "omap_udc iso", udc);
+ if (status != 0) {
+ ERR("can't get irq %ld, err %d\n",
+ odev->resource[3].start, status);
+ goto cleanup3;
+ }
+#endif
+
+ create_proc_file();
+ device_add(&udc->gadget.dev);
+ return 0;
+
+#ifdef USE_ISO
+cleanup3:
+ free_irq(odev->resource[2].start, udc);
+#endif
+
+cleanup2:
+ free_irq(odev->resource[1].start, udc);
+
+cleanup1:
+ kfree (udc);
+ udc = 0;
+
+cleanup0:
+ if (xceiv)
+ put_device(xceiv->dev);
+ release_mem_region(odev->resource[0].start,
+ odev->resource[0].end - odev->resource[0].start + 1);
+ return status;
+}
+
+static int __exit omap_udc_remove(struct device *dev)
+{
+ struct platform_device *odev = to_platform_device(dev);
+ DECLARE_COMPLETION(done);
+
+ if (!udc)
+ return -ENODEV;
+
+ udc->done = &done;
+
+ pullup_disable(udc);
+ if (udc->transceiver) {
+ put_device(udc->transceiver->dev);
+ udc->transceiver = 0;
+ }
+ UDC_SYSCON1_REG = 0;
+
+ remove_proc_file();
+
+#ifdef USE_ISO
+ free_irq(odev->resource[3].start, udc);
+#endif
+ free_irq(odev->resource[2].start, udc);
+ free_irq(odev->resource[1].start, udc);
+
+ release_mem_region(odev->resource[0].start,
+ odev->resource[0].end - odev->resource[0].start + 1);
+
+ device_unregister(&udc->gadget.dev);
+ wait_for_completion(&done);
+
+ return 0;
+}
+
+/* suspend/resume/wakeup from sysfs (echo > power/state) */
+
+static int omap_udc_suspend(struct device *dev, u32 state, u32 level)
+{
+ if (level != 0)
+ return 0;
+
+ DBG("suspend, state %d\n", state);
+ omap_pullup(&udc->gadget, 0);
+ udc->gadget.dev.power.power_state = 3;
+ udc->gadget.dev.parent->power.power_state = 3;
+ return 0;
+}
+
+static int omap_udc_resume(struct device *dev, u32 level)
+{
+ if (level != 0)
+ return 0;
+
+ DBG("resume + wakeup/SRP\n");
+ udc->gadget.dev.parent->power.power_state = 0;
+ udc->gadget.dev.power.power_state = 0;
+ omap_pullup(&udc->gadget, 1);
+
+ /* maybe the host would enumerate us if we nudged it */
+ msleep(100);
+ return omap_wakeup(&udc->gadget);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static struct device_driver udc_driver = {
+ .name = (char *) driver_name,
+ .bus = &platform_bus_type,
+ .probe = omap_udc_probe,
+ .remove = __exit_p(omap_udc_remove),
+ .suspend = omap_udc_suspend,
+ .resume = omap_udc_resume,
+};
+
+static int __init udc_init(void)
+{
+ /* should work on many OMAP systems with at most minor changes,
+ * but the 1510 doesn't have an OTG controller.
+ */
+ if (cpu_is_omap1510()) {
+ DBG("no OMAP1510 support yet\n");
+ return -ENODEV;
+ }
+ INFO("%s, version: " DRIVER_VERSION "%s\n", driver_desc,
+ use_dma ? " (dma)" : "");
+ return driver_register(&udc_driver);
+}
+module_init(udc_init);
+
+static void __exit udc_exit(void)
+{
+ driver_unregister(&udc_driver);
+}
+module_exit(udc_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
+
--- /dev/null
+/*
+ * omap_udc.h -- for omap 3.2 udc, with OTG support
+ *
+ * 2004 (C) Texas Instruments, Inc.
+ * 2004 (C) David Brownell
+ */
+
+/*
+ * USB device/endpoint management registers
+ */
+#define UDC_REG(offset) __REG16(UDC_BASE + (offset))
+
+#define UDC_REV_REG UDC_REG(0x0) /* Revision */
+#define UDC_EP_NUM_REG UDC_REG(0x4) /* Which endpoint */
+# define UDC_SETUP_SEL (1 << 6)
+# define UDC_EP_SEL (1 << 5)
+# define UDC_EP_DIR (1 << 4)
+ /* low 4 bits for endpoint number */
+#define UDC_DATA_REG UDC_REG(0x08) /* Endpoint FIFO */
+#define UDC_CTRL_REG UDC_REG(0x0C) /* Endpoint control */
+# define UDC_CLR_HALT (1 << 7)
+# define UDC_SET_HALT (1 << 6)
+# define UDC_SET_FIFO_EN (1 << 2)
+# define UDC_CLR_EP (1 << 1)
+# define UDC_RESET_EP (1 << 0)
+#define UDC_STAT_FLG_REG UDC_REG(0x10) /* Endpoint status */
+# define UDC_NO_RXPACKET (1 << 15)
+# define UDC_MISS_IN (1 << 14)
+# define UDC_DATA_FLUSH (1 << 13)
+# define UDC_ISO_ERR (1 << 12)
+# define UDC_ISO_FIFO_EMPTY (1 << 9)
+# define UDC_ISO_FIFO_FULL (1 << 8)
+# define UDC_EP_HALTED (1 << 6)
+# define UDC_STALL (1 << 5)
+# define UDC_NAK (1 << 4)
+# define UDC_ACK (1 << 3)
+# define UDC_FIFO_EN (1 << 2)
+# define UDC_NON_ISO_FIFO_EMPTY (1 << 1)
+# define UDC_NON_ISO_FIFO_FULL (1 << 0)
+#define UDC_RXFSTAT_REG UDC_REG(0x14) /* OUT bytecount */
+#define UDC_SYSCON1_REG UDC_REG(0x18) /* System config 1 */
+# define UDC_CFG_LOCK (1 << 8)
+# define UDC_DATA_ENDIAN (1 << 7)
+# define UDC_DMA_ENDIAN (1 << 6)
+# define UDC_NAK_EN (1 << 4)
+# define UDC_AUTODECODE_DIS (1 << 3)
+# define UDC_SELF_PWR (1 << 2)
+# define UDC_SOFF_DIS (1 << 1)
+# define UDC_PULLUP_EN (1 << 0)
+#define UDC_SYSCON2_REG UDC_REG(0x1C) /* System config 2 */
+# define UDC_RMT_WKP (1 << 6)
+# define UDC_STALL_CMD (1 << 5)
+# define UDC_DEV_CFG (1 << 3)
+# define UDC_CLR_CFG (1 << 2)
+#define UDC_DEVSTAT_REG UDC_REG(0x20) /* Device status */
+# define UDC_B_HNP_ENABLE (1 << 9)
+# define UDC_A_HNP_SUPPORT (1 << 8)
+# define UDC_A_ALT_HNP_SUPPORT (1 << 7)
+# define UDC_R_WK_OK (1 << 6)
+# define UDC_USB_RESET (1 << 5)
+# define UDC_SUS (1 << 4)
+# define UDC_CFG (1 << 3)
+# define UDC_ADD (1 << 2)
+# define UDC_DEF (1 << 1)
+# define UDC_ATT (1 << 0)
+#define UDC_SOF_REG UDC_REG(0x24) /* Start of frame */
+# define UDC_FT_LOCK (1 << 12)
+# define UDC_TS_OK (1 << 11)
+# define UDC_TS 0x03ff
+#define UDC_IRQ_EN_REG UDC_REG(0x28) /* Interrupt enable */
+# define UDC_SOF_IE (1 << 7)
+# define UDC_EPN_RX_IE (1 << 5)
+# define UDC_EPN_TX_IE (1 << 4)
+# define UDC_DS_CHG_IE (1 << 3)
+# define UDC_EP0_IE (1 << 0)
+#define UDC_DMA_IRQ_EN_REG UDC_REG(0x2C) /* DMA irq enable */
+ /* rx/tx dma channels numbered 1-3 not 0-2 */
+# define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2))
+# define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3))
+# define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4))
+#define UDC_IRQ_SRC_REG UDC_REG(0x30) /* Interrupt source */
+# define UDC_TXN_DONE (1 << 10)
+# define UDC_RXN_CNT (1 << 9)
+# define UDC_RXN_EOT (1 << 8)
+# define UDC_SOF (1 << 7)
+# define UDC_EPN_RX (1 << 5)
+# define UDC_EPN_TX (1 << 4)
+# define UDC_DS_CHG (1 << 3)
+# define UDC_SETUP (1 << 2)
+# define UDC_EP0_RX (1 << 1)
+# define UDC_EP0_TX (1 << 0)
+# define UDC_IRQ_SRC_MASK 0x7bf
+#define UDC_EPN_STAT_REG UDC_REG(0x34) /* EP irq status */
+#define UDC_DMAN_STAT_REG UDC_REG(0x38) /* DMA irq status */
+# define UDC_DMA_RX_SB (1 << 12)
+# define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf)
+# define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf)
+
+
+/* DMA configuration registers: up to three channels in each direction. */
+#define UDC_RXDMA_CFG_REG UDC_REG(0x40) /* 3 eps for RX DMA */
+#define UDC_TXDMA_CFG_REG UDC_REG(0x44) /* 3 eps for TX DMA */
+#define UDC_DATA_DMA_REG UDC_REG(0x48) /* rx/tx fifo addr */
+
+/* rx/tx dma control, numbering channels 1-3 not 0-2 */
+#define UDC_TXDMA_REG(chan) UDC_REG(0x50 - 4 + 4 * (chan))
+# define UDC_TXN_EOT (1 << 15) /* bytes vs packets */
+# define UDC_TXN_START (1 << 14) /* start transfer */
+# define UDC_TXN_TSC 0x03ff /* units in xfer */
+#define UDC_RXDMA_REG(chan) UDC_REG(0x60 - 4 + 4 * (chan))
+# define UDC_RXN_STOP (1 << 15) /* enable EOT irq */
+# define UDC_RXN_TC 0x00ff /* packets in xfer */
+
+
+/*
+ * Endpoint configuration registers (used before CFG_LOCK is set)
+ * UDC_EP_TX_REG(0) is unused
+ */
+#define UDC_EP_RX_REG(endpoint) UDC_REG(0x80 + (endpoint)*4)
+# define UDC_EPN_RX_VALID (1 << 15)
+# define UDC_EPN_RX_DB (1 << 14)
+ /* buffer size in bits 13, 12 */
+# define UDC_EPN_RX_ISO (1 << 11)
+ /* buffer pointer in low 11 bits */
+#define UDC_EP_TX_REG(endpoint) UDC_REG(0xc0 + (endpoint)*4)
+ /* same bitfields as in RX_REG */
+
+/*-------------------------------------------------------------------------*/
+
+struct omap_req {
+ struct usb_request req;
+ struct list_head queue;
+ unsigned dma_bytes;
+ unsigned mapped:1;
+};
+
+struct omap_ep {
+ struct usb_ep ep;
+ struct list_head queue;
+ unsigned long irqs;
+ struct list_head iso;
+ const struct usb_endpoint_descriptor *desc;
+ char name[14];
+ u16 maxpacket;
+ u8 bEndpointAddress;
+ u8 bmAttributes;
+ unsigned double_buf:1;
+ unsigned stopped:1;
+ unsigned ackwait:1;
+ unsigned has_dma:1;
+ u8 dma_channel;
+ int lch;
+ struct omap_udc *udc;
+};
+
+struct omap_udc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ spinlock_t lock;
+ struct omap_ep ep[32];
+ u16 devstat;
+ struct otg_transceiver *transceiver;
+ struct list_head iso;
+ unsigned softconnect:1;
+ unsigned vbus_active:1;
+ unsigned ep0_pending:1;
+ unsigned ep0_in:1;
+ unsigned ep0_set_config:1;
+ unsigned ep0_reset_config:1;
+ unsigned ep0_setup:1;
+ unsigned hmc:6;
+
+ struct completion *done;
+};
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+#define DBG(stuff...) printk(KERN_DEBUG "udc: " stuff)
+#else
+#define DBG(stuff...) do{}while(0)
+#endif
+
+#ifdef VERBOSE
+# define VDBG DBG
+#else
+# define VDBG(stuff...) do{}while(0)
+#endif
+
+#define ERR(stuff...) printk(KERN_ERR "udc: " stuff)
+#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
+#define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
+
+/*-------------------------------------------------------------------------*/
+
+// #define HMC_1510 ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f)
+#define HMC_1610 (OTG_SYSCON_2_REG & 0x3f)
+#define HMC HMC_1610
+
--- /dev/null
+/***************************************************************************
+ * Driver for PAS202BCB image sensor connected to the SN9C10[12] PC Camera *
+ * Controllers *
+ * *
+ * Copyright (C) 2004 by Carlos Eduardo Medaglia Dyonisio *
+ * <medaglia@undl.org.br> *
+ * http://cadu.homelinux.com:8080/ *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the Free Software *
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
+ ***************************************************************************/
+
+#include <linux/delay.h>
+#include "sn9c102_sensor.h"
+
+
+static struct sn9c102_sensor pas202bcb;
+
+
+static int pas202bcb_init(struct sn9c102_device* cam)
+{
+ int err = 0;
+
+ err += sn9c102_write_reg(cam, 0x00, 0x10);
+ err += sn9c102_write_reg(cam, 0x00, 0x11);
+ err += sn9c102_write_reg(cam, 0x00, 0x14);
+ err += sn9c102_write_reg(cam, 0x20, 0x17);
+ err += sn9c102_write_reg(cam, 0x20, 0x19);
+ err += sn9c102_write_reg(cam, 0x09, 0x18);
+
+ err += sn9c102_i2c_write(cam, 0x02, 0x0c);
+ err += sn9c102_i2c_write(cam, 0x03, 0x40);
+ err += sn9c102_i2c_write(cam, 0x04, 0x07);
+ err += sn9c102_i2c_write(cam, 0x05, 0x25);
+ err += sn9c102_i2c_write(cam, 0x0d, 0x2c);
+ err += sn9c102_i2c_write(cam, 0x0e, 0x01);
+ err += sn9c102_i2c_write(cam, 0x0f, 0xa9);
+ err += sn9c102_i2c_write(cam, 0x08, 0x01);
+ err += sn9c102_i2c_write(cam, 0x0b, 0x01);
+ err += sn9c102_i2c_write(cam, 0x13, 0x63);
+ err += sn9c102_i2c_write(cam, 0x15, 0x70);
+ err += sn9c102_i2c_write(cam, 0x11, 0x01);
+
+ msleep(400);
+
+ return err;
+}
+
+
+static int pas202bcb_get_ctrl(struct sn9c102_device* cam,
+ struct v4l2_control* ctrl)
+{
+ switch (ctrl->id) {
+ case V4L2_CID_RED_BALANCE:
+ if ((ctrl->value = sn9c102_i2c_read(cam, 0x09)) < 0)
+ return -EIO;
+ ctrl->value &= 0x0f;
+ return 0;
+ case V4L2_CID_BLUE_BALANCE:
+ if ((ctrl->value = sn9c102_i2c_read(cam, 0x07)) < 0)
+ return -EIO;
+ ctrl->value &= 0x0f;
+ return 0;
+ case V4L2_CID_GAIN:
+ if ((ctrl->value = sn9c102_i2c_read(cam, 0x10)) < 0)
+ return -EIO;
+ ctrl->value &= 0x1f;
+ return 0;
+ case V4L2_CID_BRIGHTNESS:
+ if ((ctrl->value = sn9c102_i2c_read(cam, 0x06)) < 0)
+ return -EIO;
+ ctrl->value &= 0x0f;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+
+static int pas202bcb_set_ctrl(struct sn9c102_device* cam,
+ const struct v4l2_control* ctrl)
+{
+ int err = 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_RED_BALANCE:
+ err += sn9c102_i2c_write(cam, 0x09, ctrl->value & 0x0f);
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ err += sn9c102_i2c_write(cam, 0x07, ctrl->value & 0x0f);
+ break;
+ case V4L2_CID_GAIN:
+ err += sn9c102_i2c_write(cam, 0x10, ctrl->value & 0x1f);
+ break;
+ case V4L2_CID_BRIGHTNESS:
+ err += sn9c102_i2c_write(cam, 0x06, 0x0f-(ctrl->value & 0x0f));
+ break;
+ default:
+ return -EINVAL;
+ }
+ err += sn9c102_i2c_write(cam, 0x11, 0x01);
+
+ return err;
+}
+
+
+static int pas202bcb_set_crop(struct sn9c102_device* cam,
+ const struct v4l2_rect* rect)
+{
+ struct sn9c102_sensor* s = &pas202bcb;
+ int err = 0;
+ u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 4,
+ v_start = (u8)(rect->top - s->cropcap.bounds.top) + 3;
+
+ err += sn9c102_write_reg(cam, h_start, 0x12);
+ err += sn9c102_write_reg(cam, v_start, 0x13);
+
+ return err;
+}
+
+
+static struct sn9c102_sensor pas202bcb = {
+ .name = "PAS202BCB",
+ .maintainer = "Carlos Eduardo Medaglia Dyonisio "
+ "<medaglia@undl.org.br>",
+ .frequency = SN9C102_I2C_400KHZ | SN9C102_I2C_100KHZ,
+ .interface = SN9C102_I2C_2WIRES,
+ .slave_read_id = 0x40,
+ .slave_write_id = 0x40,
+ .init = &pas202bcb_init,
+ .qctrl = {
+ {
+ .id = V4L2_CID_RED_BALANCE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "red balance",
+ .minimum = 0x00,
+ .maximum = 0x0f,
+ .step = 0x01,
+ .default_value = 0x01,
+ .flags = 0,
+ },
+ {
+ .id = V4L2_CID_BLUE_BALANCE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "blue balance",
+ .minimum = 0x00,
+ .maximum = 0x0f,
+ .step = 0x01,
+ .default_value = 0x05,
+ .flags = 0,
+ },
+ {
+ .id = V4L2_CID_GAIN,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "global gain",
+ .minimum = 0x00,
+ .maximum = 0x1f,
+ .step = 0x01,
+ .default_value = 0x0c,
+ .flags = 0,
+ },
+ {
+ .id = V4L2_CID_BRIGHTNESS,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "brightness",
+ .minimum = 0x00,
+ .maximum = 0x0f,
+ .step = 0x01,
+ .default_value = 0x0f,
+ .flags = 0,
+ },
+ },
+ .get_ctrl = &pas202bcb_get_ctrl,
+ .set_ctrl = &pas202bcb_set_ctrl,
+ .cropcap = {
+ .bounds = {
+ .left = 0,
+ .top = 0,
+ .width = 640,
+ .height = 480,
+ },
+ .defrect = {
+ .left = 0,
+ .top = 0,
+ .width = 640,
+ .height = 480,
+ },
+ },
+ .set_crop = &pas202bcb_set_crop,
+ .pix_format = {
+ .width = 640,
+ .height = 480,
+ .pixelformat = V4L2_PIX_FMT_SBGGR8,
+ .priv = 8,
+ }
+};
+
+
+int sn9c102_probe_pas202bcb(struct sn9c102_device* cam)
+{
+ int r0 = 0, r1 = 0, err = 0;
+ unsigned int pid = 0;
+
+ /*
+ * Minimal initialization to enable the I2C communication
+ * NOTE: do NOT change the values!
+ */
+ err += sn9c102_write_reg(cam, 0x01, 0x01); /* sensor power down */
+ err += sn9c102_write_reg(cam, 0x00, 0x01); /* sensor power on */
+ err += sn9c102_write_reg(cam, 0x28, 0x17); /* sensor clock at 24 MHz */
+ if (err)
+ return -EIO;
+
+ r0 = sn9c102_i2c_try_read(cam, &pas202bcb, 0x00);
+ r1 = sn9c102_i2c_try_read(cam, &pas202bcb, 0x01);
+
+ if (r0 < 0 || r1 < 0)
+ return -EIO;
+
+ pid = (r0 << 4) | ((r1 & 0xf0) >> 4);
+ if (pid != 0x017)
+ return -ENODEV;
+
+ sn9c102_attach_sensor(cam, &pas202bcb);
+
+ return 0;
+}
--- /dev/null
+/*
+ * linux/drivers/video/amba-clcd.c
+ *
+ * Copyright (C) 2001 ARM Limited, by David A Rusling
+ * Updated to 2.5, Deep Blue Solutions Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * ARM PrimeCell PL110 Color LCD Controller
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+
+#include <asm/hardware/amba.h>
+#include <asm/hardware/clock.h>
+
+#include <asm/hardware/amba_clcd.h>
+
+#define to_clcd(info) container_of(info, struct clcd_fb, fb)
+
+/* This is limited to 16 characters when displayed by X startup */
+static const char *clcd_name = "CLCD FB";
+
+/*
+ * Unfortunately, the enable/disable functions may be called either from
+ * process or IRQ context, and we _need_ to delay. This is _not_ good.
+ */
+static inline void clcdfb_sleep(unsigned int ms)
+{
+ if (in_atomic()) {
+ mdelay(ms);
+ } else {
+ msleep(ms);
+ }
+}
+
+static inline void clcdfb_set_start(struct clcd_fb *fb)
+{
+ unsigned long ustart = fb->fb.fix.smem_start;
+ unsigned long lstart;
+
+ ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
+ lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
+
+ writel(ustart, fb->regs + CLCD_UBAS);
+ writel(lstart, fb->regs + CLCD_LBAS);
+}
+
+static void clcdfb_disable(struct clcd_fb *fb)
+{
+ u32 val;
+
+ if (fb->board->disable)
+ fb->board->disable(fb);
+
+ val = readl(fb->regs + CLCD_CNTL);
+ if (val & CNTL_LCDPWR) {
+ val &= ~CNTL_LCDPWR;
+ writel(val, fb->regs + CLCD_CNTL);
+
+ clcdfb_sleep(20);
+ }
+ if (val & CNTL_LCDEN) {
+ val &= ~CNTL_LCDEN;
+ writel(val, fb->regs + CLCD_CNTL);
+ }
+
+ /*
+ * Disable CLCD clock source.
+ */
+ clk_disable(fb->clk);
+}
+
+static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
+{
+ /*
+ * Enable the CLCD clock source.
+ */
+ clk_enable(fb->clk);
+
+ /*
+ * Bring up by first enabling..
+ */
+ cntl |= CNTL_LCDEN;
+ writel(cntl, fb->regs + CLCD_CNTL);
+
+ clcdfb_sleep(20);
+
+ /*
+ * and now apply power.
+ */
+ cntl |= CNTL_LCDPWR;
+ writel(cntl, fb->regs + CLCD_CNTL);
+
+ /*
+ * finally, enable the interface.
+ */
+ if (fb->board->enable)
+ fb->board->enable(fb);
+}
+
+static int
+clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
+{
+ int ret = 0;
+
+ memset(&var->transp, 0, sizeof(var->transp));
+ memset(&var->red, 0, sizeof(var->red));
+ memset(&var->green, 0, sizeof(var->green));
+ memset(&var->blue, 0, sizeof(var->blue));
+
+ switch (var->bits_per_pixel) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ var->red.length = 8;
+ var->red.offset = 0;
+ var->green.length = 8;
+ var->green.offset = 0;
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ break;
+ case 16:
+ var->red.length = 5;
+ var->green.length = 5;
+ var->blue.length = 5;
+ if (fb->panel->cntl & CNTL_BGR) {
+ var->red.offset = 10;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ } else {
+ var->red.offset = 0;
+ var->green.offset = 5;
+ var->blue.offset = 10;
+ }
+ break;
+ case 24:
+ if (fb->panel->cntl & CNTL_LCDTFT) {
+ var->red.length = 8;
+ var->green.length = 8;
+ var->blue.length = 8;
+
+ if (fb->panel->cntl & CNTL_BGR) {
+ var->red.offset = 16;
+ var->green.offset = 8;
+ var->blue.offset = 0;
+ } else {
+ var->red.offset = 0;
+ var->green.offset = 8;
+ var->blue.offset = 16;
+ }
+ break;
+ }
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ struct clcd_fb *fb = to_clcd(info);
+ int ret = -EINVAL;
+
+ if (fb->board->check)
+ ret = fb->board->check(fb, var);
+ if (ret == 0)
+ ret = clcdfb_set_bitfields(fb, var);
+
+ return ret;
+}
+
+static int clcdfb_set_par(struct fb_info *info)
+{
+ struct clcd_fb *fb = to_clcd(info);
+ struct clcd_regs regs;
+
+ fb->fb.fix.line_length = fb->fb.var.xres_virtual *
+ fb->fb.var.bits_per_pixel / 8;
+
+ if (fb->fb.var.bits_per_pixel <= 8)
+ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ else
+ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
+
+ fb->board->decode(fb, ®s);
+
+ clcdfb_disable(fb);
+
+ writel(regs.tim0, fb->regs + CLCD_TIM0);
+ writel(regs.tim1, fb->regs + CLCD_TIM1);
+ writel(regs.tim2, fb->regs + CLCD_TIM2);
+ writel(regs.tim3, fb->regs + CLCD_TIM3);
+
+ clcdfb_set_start(fb);
+
+ clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
+
+ fb->clcd_cntl = regs.cntl;
+
+ clcdfb_enable(fb, regs.cntl);
+
+#ifdef DEBUG
+ printk(KERN_INFO "CLCD: Registers set to\n"
+ KERN_INFO " %08x %08x %08x %08x\n"
+ KERN_INFO " %08x %08x %08x %08x\n",
+ readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
+ readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
+ readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
+ readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL));
+#endif
+
+ return 0;
+}
+
+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
+{
+ unsigned int mask = (1 << bf->length) - 1;
+
+ return (val >> (16 - bf->length) & mask) << bf->offset;
+}
+
+/*
+ * Set a single color register. The values supplied have a 16 bit
+ * magnitude. Return != 0 for invalid regno.
+ */
+static int
+clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
+ unsigned int blue, unsigned int transp, struct fb_info *info)
+{
+ struct clcd_fb *fb = to_clcd(info);
+
+ if (regno < 16)
+ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
+ convert_bitfield(blue, &fb->fb.var.blue) |
+ convert_bitfield(green, &fb->fb.var.green) |
+ convert_bitfield(red, &fb->fb.var.red);
+
+ if (fb->fb.var.bits_per_pixel == 8 && regno < 256) {
+ int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
+ u32 val, mask, newval;
+
+ newval = (red >> 11) & 0x001f;
+ newval |= (green >> 6) & 0x03e0;
+ newval |= (blue >> 1) & 0x7c00;
+
+ /*
+ * 3.2.11: if we're configured for big endian
+ * byte order, the palette entries are swapped.
+ */
+ if (fb->clcd_cntl & CNTL_BEBO)
+ regno ^= 1;
+
+ if (regno & 1) {
+ newval <<= 16;
+ mask = 0x0000ffff;
+ } else {
+ mask = 0xffff0000;
+ }
+
+ val = readl(fb->regs + hw_reg) & mask;
+ writel(val | newval, fb->regs + hw_reg);
+ }
+
+ return regno > 255;
+}
+
+/*
+ * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
+ * then the caller blanks by setting the CLUT (Color Look Up Table) to all
+ * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
+ * to e.g. a video mode which doesn't support it. Implements VESA suspend
+ * and powerdown modes on hardware that supports disabling hsync/vsync:
+ * blank_mode == 2: suspend vsync
+ * blank_mode == 3: suspend hsync
+ * blank_mode == 4: powerdown
+ */
+static int clcdfb_blank(int blank_mode, struct fb_info *info)
+{
+ struct clcd_fb *fb = to_clcd(info);
+
+ if (blank_mode != 0) {
+ clcdfb_disable(fb);
+ } else {
+ clcdfb_enable(fb, fb->clcd_cntl);
+ }
+ return 0;
+}
+
+static struct fb_ops clcdfb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = clcdfb_check_var,
+ .fb_set_par = clcdfb_set_par,
+ .fb_setcolreg = clcdfb_setcolreg,
+ .fb_blank = clcdfb_blank,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_cursor = soft_cursor,
+};
+
+static int clcdfb_register(struct clcd_fb *fb)
+{
+ int ret;
+
+ fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
+ if (IS_ERR(fb->clk)) {
+ ret = PTR_ERR(fb->clk);
+ goto out;
+ }
+
+ ret = clk_use(fb->clk);
+ if (ret)
+ goto free_clk;
+
+ fb->fb.fix.mmio_start = fb->dev->res.start;
+ fb->fb.fix.mmio_len = SZ_4K;
+
+ fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
+ if (!fb->regs) {
+ printk(KERN_ERR "CLCD: unable to remap registers\n");
+ ret = -ENOMEM;
+ goto unuse_clk;
+ }
+
+ fb->fb.fbops = &clcdfb_ops;
+ fb->fb.flags = FBINFO_FLAG_DEFAULT;
+ fb->fb.pseudo_palette = fb->cmap;
+
+ strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
+ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
+ fb->fb.fix.type_aux = 0;
+ fb->fb.fix.xpanstep = 0;
+ fb->fb.fix.ypanstep = 0;
+ fb->fb.fix.ywrapstep = 0;
+ fb->fb.fix.accel = FB_ACCEL_NONE;
+
+ fb->fb.var.xres = fb->panel->mode.xres;
+ fb->fb.var.yres = fb->panel->mode.yres;
+ fb->fb.var.xres_virtual = fb->panel->mode.xres;
+ fb->fb.var.yres_virtual = fb->panel->mode.yres;
+ fb->fb.var.bits_per_pixel = fb->panel->bpp;
+ fb->fb.var.grayscale = fb->panel->grayscale;
+ fb->fb.var.pixclock = fb->panel->mode.pixclock;
+ fb->fb.var.left_margin = fb->panel->mode.left_margin;
+ fb->fb.var.right_margin = fb->panel->mode.right_margin;
+ fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
+ fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
+ fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
+ fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
+ fb->fb.var.sync = fb->panel->mode.sync;
+ fb->fb.var.vmode = fb->panel->mode.vmode;
+ fb->fb.var.activate = FB_ACTIVATE_NOW;
+ fb->fb.var.nonstd = 0;
+ fb->fb.var.height = fb->panel->height;
+ fb->fb.var.width = fb->panel->width;
+ fb->fb.var.accel_flags = 0;
+
+ fb->fb.monspecs.hfmin = 0;
+ fb->fb.monspecs.hfmax = 100000;
+ fb->fb.monspecs.vfmin = 0;
+ fb->fb.monspecs.vfmax = 400;
+ fb->fb.monspecs.dclkmin = 1000000;
+ fb->fb.monspecs.dclkmax = 100000000;
+
+ /*
+ * Make sure that the bitfields are set appropriately.
+ */
+ clcdfb_set_bitfields(fb, &fb->fb.var);
+
+ /*
+ * Allocate colourmap.
+ */
+ fb_alloc_cmap(&fb->fb.cmap, 256, 0);
+
+ /*
+ * Ensure interrupts are disabled.
+ */
+ writel(0, fb->regs + CLCD_IENB);
+
+ fb_set_var(&fb->fb, &fb->fb.var);
+
+ printk(KERN_INFO "CLCD: %s hardware, %s display\n",
+ fb->board->name, fb->panel->mode.name);
+
+ ret = register_framebuffer(&fb->fb);
+ if (ret == 0)
+ goto out;
+
+ printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
+
+ iounmap(fb->regs);
+ unuse_clk:
+ clk_unuse(fb->clk);
+ free_clk:
+ clk_put(fb->clk);
+ out:
+ return ret;
+}
+
+static int clcdfb_probe(struct amba_device *dev, void *id)
+{
+ struct clcd_board *board = dev->dev.platform_data;
+ struct clcd_fb *fb;
+ int ret;
+
+ if (!board)
+ return -EINVAL;
+
+ ret = amba_request_regions(dev, NULL);
+ if (ret) {
+ printk(KERN_ERR "CLCD: unable to reserve regs region\n");
+ goto out;
+ }
+
+ fb = (struct clcd_fb *) kmalloc(sizeof(struct clcd_fb), GFP_KERNEL);
+ if (!fb) {
+ printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
+ ret = -ENOMEM;
+ goto free_region;
+ }
+ memset(fb, 0, sizeof(struct clcd_fb));
+
+ fb->dev = dev;
+ fb->board = board;
+
+ ret = fb->board->setup(fb);
+ if (ret)
+ goto free_fb;
+
+ ret = clcdfb_register(fb);
+ if (ret == 0) {
+ amba_set_drvdata(dev, fb);
+ goto out;
+ }
+
+ fb->board->remove(fb);
+ free_fb:
+ kfree(fb);
+ free_region:
+ amba_release_regions(dev);
+ out:
+ return ret;
+}
+
+static int clcdfb_remove(struct amba_device *dev)
+{
+ struct clcd_fb *fb = amba_get_drvdata(dev);
+
+ amba_set_drvdata(dev, NULL);
+
+ clcdfb_disable(fb);
+ unregister_framebuffer(&fb->fb);
+ iounmap(fb->regs);
+ clk_unuse(fb->clk);
+ clk_put(fb->clk);
+
+ fb->board->remove(fb);
+
+ kfree(fb);
+
+ amba_release_regions(dev);
+
+ return 0;
+}
+
+static struct amba_id clcdfb_id_table[] = {
+ {
+ .id = 0x00041110,
+ .mask = 0x000fffff,
+ },
+ { 0, 0 },
+};
+
+static struct amba_driver clcd_driver = {
+ .drv = {
+ .name = "clcd-pl110",
+ },
+ .probe = clcdfb_probe,
+ .remove = clcdfb_remove,
+ .id_table = clcdfb_id_table,
+};
+
+int __init amba_clcdfb_init(void)
+{
+ if (fb_get_options("ambafb", NULL))
+ return -ENODEV;
+
+ return amba_driver_register(&clcd_driver);
+}
+
+module_init(amba_clcdfb_init);
+
+static void __exit amba_clcdfb_exit(void)
+{
+ amba_driver_unregister(&clcd_driver);
+}
+
+module_exit(amba_clcdfb_exit);
+
+MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * ds_w1_bridge.c
+ *
+ * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+
+#include "../w1/w1.h"
+#include "../w1/w1_int.h"
+#include "dscore.h"
+
+static struct ds_device *ds_dev;
+static struct w1_bus_master *ds_bus_master;
+
+static u8 ds9490r_touch_bit(unsigned long data, u8 bit)
+{
+ u8 ret;
+ struct ds_device *dev = (struct ds_device *)data;
+
+ if (ds_touch_bit(dev, bit, &ret))
+ return 0;
+
+ return ret;
+}
+
+static void ds9490r_write_bit(unsigned long data, u8 bit)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+
+ ds_write_bit(dev, bit);
+}
+
+static void ds9490r_write_byte(unsigned long data, u8 byte)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+
+ ds_write_byte(dev, byte);
+}
+
+static u8 ds9490r_read_bit(unsigned long data)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+ int err;
+ u8 bit = 0;
+
+ err = ds_touch_bit(dev, 1, &bit);
+ if (err)
+ return 0;
+ //err = ds_read_bit(dev, &bit);
+ //if (err)
+ // return 0;
+
+ return bit & 1;
+}
+
+static u8 ds9490r_read_byte(unsigned long data)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+ int err;
+ u8 byte = 0;
+
+ err = ds_read_byte(dev, &byte);
+ if (err)
+ return 0;
+
+ return byte;
+}
+
+static void ds9490r_write_block(unsigned long data, u8 *buf, int len)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+
+ ds_write_block(dev, buf, len);
+}
+
+static u8 ds9490r_read_block(unsigned long data, u8 *buf, int len)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+ int err;
+
+ err = ds_read_block(dev, buf, len);
+ if (err < 0)
+ return 0;
+
+ return len;
+}
+
+static u8 ds9490r_reset(unsigned long data)
+{
+ struct ds_device *dev = (struct ds_device *)data;
+ struct ds_status st;
+ int err;
+
+ memset(&st, 0, sizeof(st));
+
+ err = ds_reset(dev, &st);
+ if (err)
+ return 1;
+
+ return 0;
+}
+
+static int __devinit ds_w1_init(void)
+{
+ int err;
+
+ ds_bus_master = kmalloc(sizeof(*ds_bus_master), GFP_KERNEL);
+ if (!ds_bus_master) {
+ printk(KERN_ERR "Failed to allocate DS9490R USB<->W1 bus_master structure.\n");
+ return -ENOMEM;
+ }
+
+ ds_dev = ds_get_device();
+ if (!ds_dev) {
+ printk(KERN_ERR "DS9490R is not registered.\n");
+ err = -ENODEV;
+ goto err_out_free_bus_master;
+ }
+
+ memset(ds_bus_master, 0, sizeof(*ds_bus_master));
+
+ ds_bus_master->data = (unsigned long)ds_dev;
+ ds_bus_master->touch_bit = &ds9490r_touch_bit;
+ ds_bus_master->read_bit = &ds9490r_read_bit;
+ ds_bus_master->write_bit = &ds9490r_write_bit;
+ ds_bus_master->read_byte = &ds9490r_read_byte;
+ ds_bus_master->write_byte = &ds9490r_write_byte;
+ ds_bus_master->read_block = &ds9490r_read_block;
+ ds_bus_master->write_block = &ds9490r_write_block;
+ ds_bus_master->reset_bus = &ds9490r_reset;
+
+ err = w1_add_master_device(ds_bus_master);
+ if (err)
+ goto err_out_put_device;
+
+ return 0;
+
+err_out_put_device:
+ ds_put_device(ds_dev);
+err_out_free_bus_master:
+ kfree(ds_bus_master);
+
+ return err;
+}
+
+static void __devexit ds_w1_fini(void)
+{
+ w1_remove_master_device(ds_bus_master);
+ ds_put_device(ds_dev);
+ kfree(ds_bus_master);
+}
+
+module_init(ds_w1_init);
+module_exit(ds_w1_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
--- /dev/null
+/*
+ * dscore.c
+ *
+ * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/usb.h>
+
+#include "dscore.h"
+
+static struct usb_device_id ds_id_table [] = {
+ { USB_DEVICE(0x04fa, 0x2490) },
+ { },
+};
+MODULE_DEVICE_TABLE(usb, ds_id_table);
+
+int ds_probe(struct usb_interface *, const struct usb_device_id *);
+void ds_disconnect(struct usb_interface *);
+
+inline int ds_touch_bit(struct ds_device *, u8, u8 *);
+inline int ds_read_byte(struct ds_device *, u8 *);
+inline int ds_read_bit(struct ds_device *, u8 *);
+inline int ds_write_byte(struct ds_device *, u8);
+inline int ds_write_bit(struct ds_device *, u8);
+inline int ds_start_pulse(struct ds_device *, int);
+inline int ds_set_speed(struct ds_device *, int);
+inline int ds_reset(struct ds_device *, struct ds_status *);
+inline int ds_detect(struct ds_device *, struct ds_status *);
+inline int ds_stop_pulse(struct ds_device *, int);
+inline int ds_send_data(struct ds_device *, unsigned char *, int);
+inline int ds_recv_data(struct ds_device *, unsigned char *, int);
+inline int ds_recv_status(struct ds_device *, struct ds_status *);
+inline struct ds_device * ds_get_device(void);
+inline void ds_put_device(struct ds_device *);
+
+static inline void ds_dump_status(unsigned char *, unsigned char *, int);
+static inline int ds_send_control(struct ds_device *, u16, u16);
+static inline int ds_send_control_mode(struct ds_device *, u16, u16);
+static inline int ds_send_control_cmd(struct ds_device *, u16, u16);
+
+
+static struct usb_driver ds_driver = {
+ .owner = THIS_MODULE,
+ .name = "DS9490R",
+ .probe = ds_probe,
+ .disconnect = ds_disconnect,
+ .id_table = ds_id_table,
+};
+
+static struct ds_device *ds_dev;
+
+struct ds_device * ds_get_device(void)
+{
+ if (ds_dev)
+ atomic_inc(&ds_dev->refcnt);
+ return ds_dev;
+}
+
+void ds_put_device(struct ds_device *dev)
+{
+ atomic_dec(&dev->refcnt);
+}
+
+static int ds_send_control_cmd(struct ds_device *dev, u16 value, u16 index)
+{
+ int err;
+
+ err = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, dev->ep[EP_CONTROL]),
+ CONTROL_CMD, 0x40, value, index, NULL, 0, HZ);
+ if (err < 0) {
+ printk(KERN_ERR "Failed to send command control message %x.%x: err=%d.\n",
+ value, index, err);
+ return err;
+ }
+
+ return err;
+}
+
+static int ds_send_control_mode(struct ds_device *dev, u16 value, u16 index)
+{
+ int err;
+
+ err = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, dev->ep[EP_CONTROL]),
+ MODE_CMD, 0x40, value, index, NULL, 0, HZ);
+ if (err < 0) {
+ printk(KERN_ERR "Failed to send mode control message %x.%x: err=%d.\n",
+ value, index, err);
+ return err;
+ }
+
+ return err;
+}
+
+static int ds_send_control(struct ds_device *dev, u16 value, u16 index)
+{
+ int err;
+
+ err = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, dev->ep[EP_CONTROL]),
+ COMM_CMD, 0x40, value, index, NULL, 0, HZ);
+ if (err < 0) {
+ printk(KERN_ERR "Failed to send control message %x.%x: err=%d.\n",
+ value, index, err);
+ return err;
+ }
+
+ return err;
+}
+
+static inline void ds_dump_status(unsigned char *buf, unsigned char *str, int off)
+{
+ printk("%45s: %8x\n", str, buf[off]);
+}
+
+int ds_recv_status_nodump(struct ds_device *dev, struct ds_status *st, unsigned char *buf, int size)
+{
+ int count, err;
+
+ memset(st, 0, sizeof(st));
+
+ count = 0;
+ err = usb_bulk_msg(dev->udev, usb_rcvbulkpipe(dev->udev, dev->ep[EP_STATUS]), buf, size, &count, 100);
+ if (err < 0) {
+ printk(KERN_ERR "Failed to read 1-wire data from 0x%x: err=%d.\n", dev->ep[EP_STATUS], err);
+ return err;
+ }
+
+ if (count >= sizeof(*st))
+ memcpy(st, buf, sizeof(*st));
+
+ return count;
+}
+
+int ds_recv_status(struct ds_device *dev, struct ds_status *st)
+{
+ unsigned char buf[64];
+ int count, err = 0, i;
+
+ memcpy(st, buf, sizeof(*st));
+
+ count = ds_recv_status_nodump(dev, st, buf, sizeof(buf));
+ if (count < 0)
+ return err;
+
+ printk("0x%x: count=%d, status: ", dev->ep[EP_STATUS], count);
+ for (i=0; i<count; ++i)
+ printk("%02x ", buf[i]);
+ printk("\n");
+
+ if (count >= 16) {
+ ds_dump_status(buf, "enable flag", 0);
+ ds_dump_status(buf, "1-wire speed", 1);
+ ds_dump_status(buf, "strong pullup duration", 2);
+ ds_dump_status(buf, "programming pulse duration", 3);
+ ds_dump_status(buf, "pulldown slew rate control", 4);
+ ds_dump_status(buf, "write-1 low time", 5);
+ ds_dump_status(buf, "data sample offset/write-0 recovery time", 6);
+ ds_dump_status(buf, "reserved (test register)", 7);
+ ds_dump_status(buf, "device status flags", 8);
+ ds_dump_status(buf, "communication command byte 1", 9);
+ ds_dump_status(buf, "communication command byte 2", 10);
+ ds_dump_status(buf, "communication command buffer status", 11);
+ ds_dump_status(buf, "1-wire data output buffer status", 12);
+ ds_dump_status(buf, "1-wire data input buffer status", 13);
+ ds_dump_status(buf, "reserved", 14);
+ ds_dump_status(buf, "reserved", 15);
+ }
+
+ memcpy(st, buf, sizeof(*st));
+
+ if (st->status & ST_EPOF) {
+ printk(KERN_INFO "Resetting device after ST_EPOF.\n");
+ err = ds_send_control_cmd(dev, CTL_RESET_DEVICE, 0);
+ if (err)
+ return err;
+ count = ds_recv_status_nodump(dev, st, buf, sizeof(buf));
+ if (count < 0)
+ return err;
+ }
+#if 0
+ if (st->status & ST_IDLE) {
+ printk(KERN_INFO "Resetting pulse after ST_IDLE.\n");
+ err = ds_start_pulse(dev, PULLUP_PULSE_DURATION);
+ if (err)
+ return err;
+ }
+#endif
+
+ return err;
+}
+
+int ds_recv_data(struct ds_device *dev, unsigned char *buf, int size)
+{
+ int count, err;
+ struct ds_status st;
+
+ count = 0;
+ err = usb_bulk_msg(dev->udev, usb_rcvbulkpipe(dev->udev, dev->ep[EP_DATA_IN]),
+ buf, size, &count, HZ);
+ if (err < 0) {
+ printk(KERN_INFO "Clearing ep0x%x.\n", dev->ep[EP_DATA_IN]);
+ usb_clear_halt(dev->udev, usb_rcvbulkpipe(dev->udev, dev->ep[EP_DATA_IN]));
+ ds_recv_status(dev, &st);
+ return err;
+ }
+
+#if 0
+ {
+ int i;
+
+ printk("%s: count=%d: ", __func__, count);
+ for (i=0; i<count; ++i)
+ printk("%02x ", buf[i]);
+ printk("\n");
+ }
+#endif
+ return count;
+}
+
+int ds_send_data(struct ds_device *dev, unsigned char *buf, int len)
+{
+ int count, err;
+
+ count = 0;
+ err = usb_bulk_msg(dev->udev, usb_sndbulkpipe(dev->udev, dev->ep[EP_DATA_OUT]), buf, len, &count, HZ);
+ if (err < 0) {
+ printk(KERN_ERR "Failed to read 1-wire data from 0x02: err=%d.\n", err);
+ return err;
+ }
+
+ return err;
+}
+
+int ds_stop_pulse(struct ds_device *dev, int limit)
+{
+ struct ds_status st;
+ int count = 0, err = 0;
+ u8 buf[0x20];
+
+ do {
+ err = ds_send_control(dev, CTL_HALT_EXE_IDLE, 0);
+ if (err)
+ break;
+ err = ds_send_control(dev, CTL_RESUME_EXE, 0);
+ if (err)
+ break;
+ err = ds_recv_status_nodump(dev, &st, buf, sizeof(buf));
+ if (err)
+ break;
+
+ if ((st.status & ST_SPUA) == 0) {
+ err = ds_send_control_mode(dev, MOD_PULSE_EN, 0);
+ if (err)
+ break;
+ }
+ } while(++count < limit);
+
+ return err;
+}
+
+int ds_detect(struct ds_device *dev, struct ds_status *st)
+{
+ int err;
+
+ err = ds_send_control_cmd(dev, CTL_RESET_DEVICE, 0);
+ if (err)
+ return err;
+
+ err = ds_send_control(dev, COMM_SET_DURATION | COMM_IM, 0);
+ if (err)
+ return err;
+
+ err = ds_send_control(dev, COMM_SET_DURATION | COMM_IM | COMM_TYPE, 0x40);
+ if (err)
+ return err;
+
+ err = ds_send_control_mode(dev, MOD_PULSE_EN, PULSE_PROG);
+ if (err)
+ return err;
+
+ err = ds_recv_status(dev, st);
+
+ return err;
+}
+
+int ds_wait_status(struct ds_device *dev, struct ds_status *st)
+{
+ u8 buf[0x20];
+ int err, count = 0;
+
+ do {
+ err = ds_recv_status_nodump(dev, st, buf, sizeof(buf));
+#if 0
+ if (err >= 0) {
+ int i;
+ printk("0x%x: count=%d, status: ", dev->ep[EP_STATUS], err);
+ for (i=0; i<err; ++i)
+ printk("%02x ", buf[i]);
+ printk("\n");
+ }
+#endif
+ } while(!(buf[0x08] & 0x20) && !(err < 0) && ++count < 100);
+
+
+ if (((err > 16) && (buf[0x10] & 0x01)) || count >= 100 || err < 0) {
+ ds_recv_status(dev, st);
+ return -1;
+ }
+ else {
+ return 0;
+ }
+}
+
+int ds_reset(struct ds_device *dev, struct ds_status *st)
+{
+ int err;
+
+ //err = ds_send_control(dev, COMM_1_WIRE_RESET | COMM_F | COMM_IM | COMM_SE, SPEED_FLEXIBLE);
+ err = ds_send_control(dev, 0x43, SPEED_NORMAL);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, st);
+#if 0
+ if (st->command_buffer_status) {
+ printk(KERN_INFO "Short circuit.\n");
+ return -EIO;
+ }
+#endif
+
+ return 0;
+}
+
+int ds_set_speed(struct ds_device *dev, int speed)
+{
+ int err;
+
+ if (speed != SPEED_NORMAL && speed != SPEED_FLEXIBLE && speed != SPEED_OVERDRIVE)
+ return -EINVAL;
+
+ if (speed != SPEED_OVERDRIVE)
+ speed = SPEED_FLEXIBLE;
+
+ speed &= 0xff;
+
+ err = ds_send_control_mode(dev, MOD_1WIRE_SPEED, speed);
+ if (err)
+ return err;
+
+ return err;
+}
+
+int ds_start_pulse(struct ds_device *dev, int delay)
+{
+ int err;
+ u8 del = 1 + (u8)(delay >> 4);
+ struct ds_status st;
+
+#if 0
+ err = ds_stop_pulse(dev, 10);
+ if (err)
+ return err;
+
+ err = ds_send_control_mode(dev, MOD_PULSE_EN, PULSE_SPUE);
+ if (err)
+ return err;
+#endif
+ err = ds_send_control(dev, COMM_SET_DURATION | COMM_IM, del);
+ if (err)
+ return err;
+
+ err = ds_send_control(dev, COMM_PULSE | COMM_IM | COMM_F, 0);
+ if (err)
+ return err;
+
+ mdelay(delay);
+
+ ds_wait_status(dev, &st);
+
+ return err;
+}
+
+int ds_touch_bit(struct ds_device *dev, u8 bit, u8 *tbit)
+{
+ int err, count;
+ struct ds_status st;
+ u16 value = (COMM_BIT_IO | COMM_IM) | ((bit) ? COMM_D : 0);
+ u16 cmd;
+
+ err = ds_send_control(dev, value, 0);
+ if (err)
+ return err;
+
+ count = 0;
+ do {
+ err = ds_wait_status(dev, &st);
+ if (err)
+ return err;
+
+ cmd = st.command0 | (st.command1 << 8);
+ } while (cmd != value && ++count < 10);
+
+ if (err < 0 || count >= 10) {
+ printk(KERN_ERR "Failed to obtain status.\n");
+ return -EINVAL;
+ }
+
+ err = ds_recv_data(dev, tbit, sizeof(*tbit));
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+int ds_write_bit(struct ds_device *dev, u8 bit)
+{
+ int err;
+ struct ds_status st;
+
+ err = ds_send_control(dev, COMM_BIT_IO | COMM_IM | (bit) ? COMM_D : 0, 0);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ return 0;
+}
+
+int ds_write_byte(struct ds_device *dev, u8 byte)
+{
+ int err;
+ struct ds_status st;
+ u8 rbyte;
+
+ err = ds_send_control(dev, COMM_BYTE_IO | COMM_IM | COMM_SPU, byte);
+ if (err)
+ return err;
+
+ err = ds_wait_status(dev, &st);
+ if (err)
+ return err;
+
+ err = ds_recv_data(dev, &rbyte, sizeof(rbyte));
+ if (err < 0)
+ return err;
+
+ ds_start_pulse(dev, PULLUP_PULSE_DURATION);
+
+ return !(byte == rbyte);
+}
+
+int ds_read_bit(struct ds_device *dev, u8 *bit)
+{
+ int err;
+
+ err = ds_send_control_mode(dev, MOD_PULSE_EN, PULSE_SPUE);
+ if (err)
+ return err;
+
+ err = ds_send_control(dev, COMM_BIT_IO | COMM_IM | COMM_SPU | COMM_D, 0);
+ if (err)
+ return err;
+
+ err = ds_recv_data(dev, bit, sizeof(*bit));
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+int ds_read_byte(struct ds_device *dev, u8 *byte)
+{
+ int err;
+ struct ds_status st;
+
+ err = ds_send_control(dev, COMM_BYTE_IO | COMM_IM , 0xff);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ err = ds_recv_data(dev, byte, sizeof(*byte));
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
+inline int ds_read_block(struct ds_device *dev, u8 *buf, int len)
+{
+ struct ds_status st;
+ int err;
+
+ if (len > 64*1024)
+ return -E2BIG;
+
+ memset(buf, 0xFF, len);
+
+ err = ds_send_data(dev, buf, len);
+ if (err < 0)
+ return err;
+
+ err = ds_send_control(dev, COMM_BLOCK_IO | COMM_IM | COMM_SPU, len);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ memset(buf, 0x00, len);
+ err = ds_recv_data(dev, buf, len);
+
+ return err;
+}
+
+inline int ds_write_block(struct ds_device *dev, u8 *buf, int len)
+{
+ int err;
+ struct ds_status st;
+
+ err = ds_send_data(dev, buf, len);
+ if (err < 0)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ err = ds_send_control(dev, COMM_BLOCK_IO | COMM_IM | COMM_SPU, len);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ err = ds_recv_data(dev, buf, len);
+ if (err < 0)
+ return err;
+
+ ds_start_pulse(dev, PULLUP_PULSE_DURATION);
+
+ return !(err == len);
+}
+
+int ds_search(struct ds_device *dev, u64 init, u64 *buf, u8 id_number, int conditional_search)
+{
+ int err;
+ u16 value, index;
+ struct ds_status st;
+
+ memset(buf, 0, sizeof(buf));
+
+ err = ds_send_data(ds_dev, (unsigned char *)&init, 8);
+ if (err)
+ return err;
+
+ ds_wait_status(ds_dev, &st);
+
+ value = COMM_SEARCH_ACCESS | COMM_IM | COMM_SM | COMM_F | COMM_RTS;
+ index = (conditional_search ? 0xEC : 0xF0) | (id_number << 8);
+ err = ds_send_control(ds_dev, value, index);
+ if (err)
+ return err;
+
+ ds_wait_status(ds_dev, &st);
+
+ err = ds_recv_data(ds_dev, (unsigned char *)buf, 8*id_number);
+ if (err < 0)
+ return err;
+
+ return err/8;
+}
+
+int ds_match_access(struct ds_device *dev, u64 init)
+{
+ int err;
+ struct ds_status st;
+
+ err = ds_send_data(dev, (unsigned char *)&init, sizeof(init));
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ err = ds_send_control(dev, COMM_MATCH_ACCESS | COMM_IM | COMM_RST, 0x0055);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ return 0;
+}
+
+int ds_set_path(struct ds_device *dev, u64 init)
+{
+ int err;
+ struct ds_status st;
+ u8 buf[9];
+
+ memcpy(buf, &init, 8);
+ buf[8] = BRANCH_MAIN;
+
+ err = ds_send_data(dev, buf, sizeof(buf));
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ err = ds_send_control(dev, COMM_SET_PATH | COMM_IM | COMM_RST, 0);
+ if (err)
+ return err;
+
+ ds_wait_status(dev, &st);
+
+ return 0;
+}
+
+int ds_probe(struct usb_interface *intf, const struct usb_device_id *udev_id)
+{
+ struct usb_device *udev = interface_to_usbdev(intf);
+ struct usb_endpoint_descriptor *endpoint;
+ struct usb_host_interface *iface_desc;
+ int i, err;
+
+ ds_dev = kmalloc(sizeof(struct ds_device), GFP_KERNEL);
+ if (!ds_dev) {
+ printk(KERN_INFO "Failed to allocate new DS9490R structure.\n");
+ return -ENOMEM;
+ }
+
+ ds_dev->udev = usb_get_dev(udev);
+ usb_set_intfdata(intf, ds_dev);
+
+ err = usb_set_interface(ds_dev->udev, intf->altsetting[0].desc.bInterfaceNumber, 3);
+ if (err) {
+ printk(KERN_ERR "Failed to set alternative setting 3 for %d interface: err=%d.\n",
+ intf->altsetting[0].desc.bInterfaceNumber, err);
+ return err;
+ }
+
+ err = usb_reset_configuration(ds_dev->udev);
+ if (err) {
+ printk(KERN_ERR "Failed to reset configuration: err=%d.\n", err);
+ return err;
+ }
+
+ iface_desc = &intf->altsetting[0];
+ if (iface_desc->desc.bNumEndpoints != NUM_EP-1) {
+ printk(KERN_INFO "Num endpoints=%d. It is not DS9490R.\n", iface_desc->desc.bNumEndpoints);
+ return -ENODEV;
+ }
+
+ atomic_set(&ds_dev->refcnt, 0);
+ memset(ds_dev->ep, 0, sizeof(ds_dev->ep));
+
+ /*
+ * This loop doesn'd show control 0 endpoint,
+ * so we will fill only 1-3 endpoints entry.
+ */
+ for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
+ endpoint = &iface_desc->endpoint[i].desc;
+
+ ds_dev->ep[i+1] = endpoint->bEndpointAddress;
+
+ printk("%d: addr=%x, size=%d, dir=%s, type=%x\n",
+ i, endpoint->bEndpointAddress, endpoint->wMaxPacketSize,
+ (endpoint->bEndpointAddress & USB_DIR_IN)?"IN":"OUT",
+ endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK);
+ }
+
+#if 0
+ {
+ int err, i;
+ u64 buf[3];
+ u64 init=0xb30000002078ee81ull;
+ struct ds_status st;
+
+ ds_reset(ds_dev, &st);
+ err = ds_search(ds_dev, init, buf, 3, 0);
+ if (err < 0)
+ return err;
+ for (i=0; i<err; ++i)
+ printk("%d: %llx\n", i, buf[i]);
+
+ printk("Resetting...\n");
+ ds_reset(ds_dev, &st);
+ printk("Setting path for %llx.\n", init);
+ err = ds_set_path(ds_dev, init);
+ if (err)
+ return err;
+ printk("Calling MATCH_ACCESS.\n");
+ err = ds_match_access(ds_dev, init);
+ if (err)
+ return err;
+
+ printk("Searching the bus...\n");
+ err = ds_search(ds_dev, init, buf, 3, 0);
+
+ printk("ds_search() returned %d\n", err);
+
+ if (err < 0)
+ return err;
+ for (i=0; i<err; ++i)
+ printk("%d: %llx\n", i, buf[i]);
+
+ return 0;
+ }
+#endif
+
+ return 0;
+}
+
+void ds_disconnect(struct usb_interface *intf)
+{
+ struct ds_device *dev;
+
+ dev = usb_get_intfdata (intf);
+ usb_set_intfdata (intf, NULL);
+
+ while(atomic_read(&dev->refcnt))
+ schedule_timeout(HZ);
+
+ usb_put_dev(dev->udev);
+ kfree(dev);
+ ds_dev = NULL;
+}
+
+int ds_init(void)
+{
+ int err;
+
+ err = usb_register(&ds_driver);
+ if (err) {
+ printk(KERN_INFO "Failed to register DS9490R USB device: err=%d.\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void ds_fini(void)
+{
+ usb_deregister(&ds_driver);
+}
+
+module_init(ds_init);
+module_exit(ds_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
+
+EXPORT_SYMBOL(ds_touch_bit);
+EXPORT_SYMBOL(ds_read_byte);
+EXPORT_SYMBOL(ds_read_bit);
+EXPORT_SYMBOL(ds_read_block);
+EXPORT_SYMBOL(ds_write_byte);
+EXPORT_SYMBOL(ds_write_bit);
+EXPORT_SYMBOL(ds_write_block);
+EXPORT_SYMBOL(ds_start_pulse);
+EXPORT_SYMBOL(ds_set_speed);
+EXPORT_SYMBOL(ds_reset);
+EXPORT_SYMBOL(ds_detect);
+EXPORT_SYMBOL(ds_stop_pulse);
+EXPORT_SYMBOL(ds_send_data);
+EXPORT_SYMBOL(ds_recv_data);
+EXPORT_SYMBOL(ds_recv_status);
+EXPORT_SYMBOL(ds_search);
+EXPORT_SYMBOL(ds_get_device);
+EXPORT_SYMBOL(ds_put_device);
+
--- /dev/null
+/*
+ * dscore.h
+ *
+ * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __DSCORE_H
+#define __DSCORE_H
+
+#include <linux/usb.h>
+#include <asm/atomic.h>
+
+/* COMMAND TYPE CODES */
+#define CONTROL_CMD 0x00
+#define COMM_CMD 0x01
+#define MODE_CMD 0x02
+
+/* CONTROL COMMAND CODES */
+#define CTL_RESET_DEVICE 0x0000
+#define CTL_START_EXE 0x0001
+#define CTL_RESUME_EXE 0x0002
+#define CTL_HALT_EXE_IDLE 0x0003
+#define CTL_HALT_EXE_DONE 0x0004
+#define CTL_FLUSH_COMM_CMDS 0x0007
+#define CTL_FLUSH_RCV_BUFFER 0x0008
+#define CTL_FLUSH_XMT_BUFFER 0x0009
+#define CTL_GET_COMM_CMDS 0x000A
+
+/* MODE COMMAND CODES */
+#define MOD_PULSE_EN 0x0000
+#define MOD_SPEED_CHANGE_EN 0x0001
+#define MOD_1WIRE_SPEED 0x0002
+#define MOD_STRONG_PU_DURATION 0x0003
+#define MOD_PULLDOWN_SLEWRATE 0x0004
+#define MOD_PROG_PULSE_DURATION 0x0005
+#define MOD_WRITE1_LOWTIME 0x0006
+#define MOD_DSOW0_TREC 0x0007
+
+/* COMMUNICATION COMMAND CODES */
+#define COMM_ERROR_ESCAPE 0x0601
+#define COMM_SET_DURATION 0x0012
+#define COMM_BIT_IO 0x0020
+#define COMM_PULSE 0x0030
+#define COMM_1_WIRE_RESET 0x0042
+#define COMM_BYTE_IO 0x0052
+#define COMM_MATCH_ACCESS 0x0064
+#define COMM_BLOCK_IO 0x0074
+#define COMM_READ_STRAIGHT 0x0080
+#define COMM_DO_RELEASE 0x6092
+#define COMM_SET_PATH 0x00A2
+#define COMM_WRITE_SRAM_PAGE 0x00B2
+#define COMM_WRITE_EPROM 0x00C4
+#define COMM_READ_CRC_PROT_PAGE 0x00D4
+#define COMM_READ_REDIRECT_PAGE_CRC 0x21E4
+#define COMM_SEARCH_ACCESS 0x00F4
+
+/* Communication command bits */
+#define COMM_TYPE 0x0008
+#define COMM_SE 0x0008
+#define COMM_D 0x0008
+#define COMM_Z 0x0008
+#define COMM_CH 0x0008
+#define COMM_SM 0x0008
+#define COMM_R 0x0008
+#define COMM_IM 0x0001
+
+#define COMM_PS 0x4000
+#define COMM_PST 0x4000
+#define COMM_CIB 0x4000
+#define COMM_RTS 0x4000
+#define COMM_DT 0x2000
+#define COMM_SPU 0x1000
+#define COMM_F 0x0800
+#define COMM_NTP 0x0400
+#define COMM_ICP 0x0200
+#define COMM_RST 0x0100
+
+#define PULSE_PROG 0x01
+#define PULSE_SPUE 0x02
+
+#define BRANCH_MAIN 0xCC
+#define BRANCH_AUX 0x33
+
+/*
+ * Duration of the strong pull-up pulse in milliseconds.
+ */
+#define PULLUP_PULSE_DURATION 750
+
+/* Status flags */
+#define ST_SPUA 0x01 /* Strong Pull-up is active */
+#define ST_PRGA 0x02 /* 12V programming pulse is being generated */
+#define ST_12VP 0x04 /* external 12V programming voltage is present */
+#define ST_PMOD 0x08 /* DS2490 powered from USB and external sources */
+#define ST_HALT 0x10 /* DS2490 is currently halted */
+#define ST_IDLE 0x20 /* DS2490 is currently idle */
+#define ST_EPOF 0x80
+
+#define SPEED_NORMAL 0x00
+#define SPEED_FLEXIBLE 0x01
+#define SPEED_OVERDRIVE 0x02
+
+#define NUM_EP 4
+#define EP_CONTROL 0
+#define EP_STATUS 1
+#define EP_DATA_OUT 2
+#define EP_DATA_IN 3
+
+struct ds_device
+{
+ struct usb_device *udev;
+ struct usb_interface *intf;
+
+ int ep[NUM_EP];
+
+ atomic_t refcnt;
+};
+
+struct ds_status
+{
+ u8 enable;
+ u8 speed;
+ u8 pullup_dur;
+ u8 ppuls_dur;
+ u8 pulldown_slew;
+ u8 write1_time;
+ u8 write0_time;
+ u8 reserved0;
+ u8 status;
+ u8 command0;
+ u8 command1;
+ u8 command_buffer_status;
+ u8 data_out_buffer_status;
+ u8 data_in_buffer_status;
+ u8 reserved1;
+ u8 reserved2;
+
+};
+
+inline int ds_touch_bit(struct ds_device *, u8, u8 *);
+inline int ds_read_byte(struct ds_device *, u8 *);
+inline int ds_read_bit(struct ds_device *, u8 *);
+inline int ds_write_byte(struct ds_device *, u8);
+inline int ds_write_bit(struct ds_device *, u8);
+inline int ds_start_pulse(struct ds_device *, int);
+inline int ds_set_speed(struct ds_device *, int);
+inline int ds_reset(struct ds_device *, struct ds_status *);
+inline int ds_detect(struct ds_device *, struct ds_status *);
+inline int ds_stop_pulse(struct ds_device *, int);
+inline int ds_send_data(struct ds_device *, unsigned char *, int);
+inline int ds_recv_data(struct ds_device *, unsigned char *, int);
+inline int ds_recv_status(struct ds_device *, struct ds_status *);
+inline struct ds_device * ds_get_device(void);
+inline void ds_put_device(struct ds_device *);
+inline int ds_write_block(struct ds_device *, u8 *, int);
+inline int ds_read_block(struct ds_device *, u8 *, int);
+
+#endif /* __DSCORE_H */
+
--- /dev/null
+/*
+ * w1_smem.c
+ *
+ * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the smems of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <asm/types.h>
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/types.h>
+
+#include "w1.h"
+#include "w1_io.h"
+#include "w1_int.h"
+#include "w1_family.h"
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
+MODULE_DESCRIPTION("Driver for 1-wire Dallas network protocol, 64bit memory family.");
+
+static ssize_t w1_smem_read_name(struct device *, char *);
+static ssize_t w1_smem_read_val(struct device *, char *);
+static ssize_t w1_smem_read_bin(struct kobject *, char *, loff_t, size_t);
+
+static struct w1_family_ops w1_smem_fops = {
+ .rname = &w1_smem_read_name,
+ .rbin = &w1_smem_read_bin,
+ .rval = &w1_smem_read_val,
+ .rvalname = "id",
+};
+
+static ssize_t w1_smem_read_name(struct device *dev, char *buf)
+{
+ struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
+
+ return sprintf(buf, "%s\n", sl->name);
+}
+
+static ssize_t w1_smem_read_val(struct device *dev, char *buf)
+{
+ struct w1_slave *sl = container_of(dev, struct w1_slave, dev);
+ int i;
+ ssize_t count = 0;
+
+ for (i = 0; i < 9; ++i)
+ count += sprintf(buf + count, "%02x ", ((u8 *)&sl->reg_num)[i]);
+ count += sprintf(buf + count, "\n");
+
+ return count;
+}
+
+static ssize_t w1_smem_read_bin(struct kobject *kobj, char *buf, loff_t off, size_t count)
+{
+ struct w1_slave *sl = container_of(container_of(kobj, struct device, kobj),
+ struct w1_slave, dev);
+ int i;
+
+ atomic_inc(&sl->refcnt);
+ if (down_interruptible(&sl->master->mutex)) {
+ count = 0;
+ goto out_dec;
+ }
+
+ if (off > W1_SLAVE_DATA_SIZE) {
+ count = 0;
+ goto out;
+ }
+ if (off + count > W1_SLAVE_DATA_SIZE) {
+ count = 0;
+ goto out;
+ }
+ for (i = 0; i < 9; ++i)
+ count += sprintf(buf + count, "%02x ", ((u8 *)&sl->reg_num)[i]);
+ count += sprintf(buf + count, "\n");
+
+out:
+ up(&sl->master->mutex);
+out_dec:
+ atomic_dec(&sl->refcnt);
+
+ return count;
+}
+
+static struct w1_family w1_smem_family = {
+ .fid = W1_FAMILY_SMEM,
+ .fops = &w1_smem_fops,
+};
+
+static int __init w1_smem_init(void)
+{
+ return w1_register_family(&w1_smem_family);
+}
+
+static void __exit w1_smem_fini(void)
+{
+ w1_unregister_family(&w1_smem_family);
+}
+
+module_init(w1_smem_init);
+module_exit(w1_smem_fini);
--- /dev/null
+/*
+ * linux/fs/nfs/callback.c
+ *
+ * Copyright (C) 2004 Trond Myklebust
+ *
+ * NFSv4 callback handling
+ */
+
+#include <linux/config.h>
+#include <linux/completion.h>
+#include <linux/ip.h>
+#include <linux/module.h>
+#include <linux/smp_lock.h>
+#include <linux/sunrpc/svc.h>
+#include <linux/sunrpc/svcsock.h>
+#include <linux/nfs_fs.h>
+#include "callback.h"
+
+#define NFSDBG_FACILITY NFSDBG_CALLBACK
+
+struct nfs_callback_data {
+ unsigned int users;
+ struct svc_serv *serv;
+ pid_t pid;
+ struct completion started;
+ struct completion stopped;
+};
+
+static struct nfs_callback_data nfs_callback_info;
+static DECLARE_MUTEX(nfs_callback_sema);
+static struct svc_program nfs4_callback_program;
+
+unsigned short nfs_callback_tcpport;
+
+/*
+ * This is the callback kernel thread.
+ */
+static void nfs_callback_svc(struct svc_rqst *rqstp)
+{
+ struct svc_serv *serv = rqstp->rq_server;
+ int err;
+
+ __module_get(THIS_MODULE);
+ lock_kernel();
+
+ nfs_callback_info.pid = current->pid;
+ daemonize("nfsv4-svc");
+ /* Process request with signals blocked, but allow SIGKILL. */
+ allow_signal(SIGKILL);
+
+ complete(&nfs_callback_info.started);
+
+ while (nfs_callback_info.users != 0 || !signalled()) {
+ /*
+ * Listen for a request on the socket
+ */
+ err = svc_recv(serv, rqstp, MAX_SCHEDULE_TIMEOUT);
+ if (err == -EAGAIN || err == -EINTR)
+ continue;
+ if (err < 0) {
+ printk(KERN_WARNING
+ "%s: terminating on error %d\n",
+ __FUNCTION__, -err);
+ break;
+ }
+ dprintk("%s: request from %u.%u.%u.%u\n", __FUNCTION__,
+ NIPQUAD(rqstp->rq_addr.sin_addr.s_addr));
+ svc_process(serv, rqstp);
+ }
+
+ nfs_callback_info.pid = 0;
+ complete(&nfs_callback_info.stopped);
+ unlock_kernel();
+ module_put_and_exit(0);
+}
+
+/*
+ * Bring up the server process if it is not already up.
+ */
+int nfs_callback_up(void)
+{
+ struct svc_serv *serv;
+ struct svc_sock *svsk;
+ int ret = 0;
+
+ lock_kernel();
+ down(&nfs_callback_sema);
+ if (nfs_callback_info.users++ || nfs_callback_info.pid != 0)
+ goto out;
+ init_completion(&nfs_callback_info.started);
+ init_completion(&nfs_callback_info.stopped);
+ serv = svc_create(&nfs4_callback_program, NFS4_CALLBACK_BUFSIZE);
+ ret = -ENOMEM;
+ if (!serv)
+ goto out_err;
+ /* FIXME: We don't want to register this socket with the portmapper */
+ ret = svc_makesock(serv, IPPROTO_TCP, 0);
+ if (ret < 0)
+ goto out_destroy;
+ if (!list_empty(&serv->sv_permsocks)) {
+ svsk = list_entry(serv->sv_permsocks.next,
+ struct svc_sock, sk_list);
+ nfs_callback_tcpport = ntohs(inet_sk(svsk->sk_sk)->sport);
+ dprintk ("Callback port = 0x%x\n", nfs_callback_tcpport);
+ } else
+ BUG();
+ ret = svc_create_thread(nfs_callback_svc, serv);
+ if (ret < 0)
+ goto out_destroy;
+ nfs_callback_info.serv = serv;
+ wait_for_completion(&nfs_callback_info.started);
+out:
+ up(&nfs_callback_sema);
+ unlock_kernel();
+ return ret;
+out_destroy:
+ svc_destroy(serv);
+out_err:
+ nfs_callback_info.users--;
+ goto out;
+}
+
+/*
+ * Kill the server process if it is not already up.
+ */
+int nfs_callback_down(void)
+{
+ int ret = 0;
+
+ lock_kernel();
+ down(&nfs_callback_sema);
+ if (--nfs_callback_info.users || nfs_callback_info.pid == 0)
+ goto out;
+ kill_proc(nfs_callback_info.pid, SIGKILL, 1);
+ wait_for_completion(&nfs_callback_info.stopped);
+out:
+ up(&nfs_callback_sema);
+ unlock_kernel();
+ return ret;
+}
+
+/*
+ * AUTH_NULL authentication
+ */
+static int nfs_callback_null_accept(struct svc_rqst *rqstp, u32 *authp)
+{
+ struct kvec *argv = &rqstp->rq_arg.head[0];
+ struct kvec *resv = &rqstp->rq_res.head[0];
+
+ if (argv->iov_len < 3*4)
+ return SVC_GARBAGE;
+
+ if (svc_getu32(argv) != 0) {
+ dprintk("svc: bad null cred\n");
+ *authp = rpc_autherr_badcred;
+ return SVC_DENIED;
+ }
+ if (svc_getu32(argv) != RPC_AUTH_NULL || svc_getu32(argv) != 0) {
+ dprintk("svc: bad null verf\n");
+ *authp = rpc_autherr_badverf;
+ return SVC_DENIED;
+ }
+
+ /* Signal that mapping to nobody uid/gid is required */
+ rqstp->rq_cred.cr_uid = (uid_t) -1;
+ rqstp->rq_cred.cr_gid = (gid_t) -1;
+ rqstp->rq_cred.cr_group_info = groups_alloc(0);
+ if (rqstp->rq_cred.cr_group_info == NULL)
+ return SVC_DROP; /* kmalloc failure - client must retry */
+
+ /* Put NULL verifier */
+ svc_putu32(resv, RPC_AUTH_NULL);
+ svc_putu32(resv, 0);
+ dprintk("%s: success, returning %d!\n", __FUNCTION__, SVC_OK);
+ return SVC_OK;
+}
+
+static int nfs_callback_null_release(struct svc_rqst *rqstp)
+{
+ if (rqstp->rq_cred.cr_group_info)
+ put_group_info(rqstp->rq_cred.cr_group_info);
+ rqstp->rq_cred.cr_group_info = NULL;
+ return 0; /* don't drop */
+}
+
+static struct auth_ops nfs_callback_auth_null = {
+ .name = "null",
+ .flavour = RPC_AUTH_NULL,
+ .accept = nfs_callback_null_accept,
+ .release = nfs_callback_null_release,
+};
+
+/*
+ * AUTH_SYS authentication
+ */
+static int nfs_callback_unix_accept(struct svc_rqst *rqstp, u32 *authp)
+{
+ struct kvec *argv = &rqstp->rq_arg.head[0];
+ struct kvec *resv = &rqstp->rq_res.head[0];
+ struct svc_cred *cred = &rqstp->rq_cred;
+ u32 slen, i;
+ int len = argv->iov_len;
+
+ dprintk("%s: start\n", __FUNCTION__);
+ cred->cr_group_info = NULL;
+ rqstp->rq_client = NULL;
+ if ((len -= 3*4) < 0)
+ return SVC_GARBAGE;
+
+ /* Get length, time stamp and machine name */
+ svc_getu32(argv);
+ svc_getu32(argv);
+ slen = XDR_QUADLEN(ntohl(svc_getu32(argv)));
+ if (slen > 64 || (len -= (slen + 3)*4) < 0)
+ goto badcred;
+ argv->iov_base = (void*)((u32*)argv->iov_base + slen);
+ argv->iov_len -= slen*4;
+
+ cred->cr_uid = ntohl(svc_getu32(argv));
+ cred->cr_gid = ntohl(svc_getu32(argv));
+ slen = ntohl(svc_getu32(argv));
+ if (slen > 16 || (len -= (slen + 2)*4) < 0)
+ goto badcred;
+ cred->cr_group_info = groups_alloc(slen);
+ if (cred->cr_group_info == NULL)
+ return SVC_DROP;
+ for (i = 0; i < slen; i++)
+ GROUP_AT(cred->cr_group_info, i) = ntohl(svc_getu32(argv));
+
+ if (svc_getu32(argv) != RPC_AUTH_NULL || svc_getu32(argv) != 0) {
+ *authp = rpc_autherr_badverf;
+ return SVC_DENIED;
+ }
+ /* Put NULL verifier */
+ svc_putu32(resv, RPC_AUTH_NULL);
+ svc_putu32(resv, 0);
+ dprintk("%s: success, returning %d!\n", __FUNCTION__, SVC_OK);
+ return SVC_OK;
+badcred:
+ *authp = rpc_autherr_badcred;
+ return SVC_DENIED;
+}
+
+static int nfs_callback_unix_release(struct svc_rqst *rqstp)
+{
+ if (rqstp->rq_cred.cr_group_info)
+ put_group_info(rqstp->rq_cred.cr_group_info);
+ rqstp->rq_cred.cr_group_info = NULL;
+ return 0;
+}
+
+static struct auth_ops nfs_callback_auth_unix = {
+ .name = "unix",
+ .flavour = RPC_AUTH_UNIX,
+ .accept = nfs_callback_unix_accept,
+ .release = nfs_callback_unix_release,
+};
+
+/*
+ * Hook the authentication protocol
+ */
+static int nfs_callback_auth(struct svc_rqst *rqstp, u32 *authp)
+{
+ struct in_addr *addr = &rqstp->rq_addr.sin_addr;
+ struct nfs4_client *clp;
+ struct kvec *argv = &rqstp->rq_arg.head[0];
+ int flavour;
+ int retval;
+
+ /* Don't talk to strangers */
+ clp = nfs4_find_client(addr);
+ if (clp == NULL)
+ return SVC_DROP;
+ dprintk("%s: %u.%u.%u.%u NFSv4 callback!\n", __FUNCTION__, NIPQUAD(addr));
+ nfs4_put_client(clp);
+ flavour = ntohl(svc_getu32(argv));
+ switch(flavour) {
+ case RPC_AUTH_NULL:
+ if (rqstp->rq_proc != CB_NULL) {
+ *authp = rpc_autherr_tooweak;
+ retval = SVC_DENIED;
+ break;
+ }
+ rqstp->rq_authop = &nfs_callback_auth_null;
+ retval = nfs_callback_null_accept(rqstp, authp);
+ break;
+ case RPC_AUTH_UNIX:
+ /* Eat the authentication flavour */
+ rqstp->rq_authop = &nfs_callback_auth_unix;
+ retval = nfs_callback_unix_accept(rqstp, authp);
+ break;
+ default:
+ /* FIXME: need to add RPCSEC_GSS upcalls */
+#if 0
+ svc_ungetu32(argv);
+ retval = svc_authenticate(rqstp, authp);
+#else
+ *authp = rpc_autherr_rejectedcred;
+ retval = SVC_DENIED;
+#endif
+ }
+ dprintk("%s: flavour %d returning error %d\n", __FUNCTION__, flavour, retval);
+ return retval;
+}
+
+/*
+ * Define NFS4 callback program
+ */
+extern struct svc_version nfs4_callback_version1;
+
+static struct svc_version *nfs4_callback_version[] = {
+ [1] = &nfs4_callback_version1,
+};
+
+static struct svc_stat nfs4_callback_stats;
+
+static struct svc_program nfs4_callback_program = {
+ .pg_prog = NFS4_CALLBACK, /* RPC service number */
+ .pg_nvers = ARRAY_SIZE(nfs4_callback_version), /* Number of entries */
+ .pg_vers = nfs4_callback_version, /* version table */
+ .pg_name = "NFSv4 callback", /* service name */
+ .pg_class = "nfs", /* authentication class */
+ .pg_stats = &nfs4_callback_stats,
+ .pg_authenticate = nfs_callback_auth,
+};
--- /dev/null
+/*
+ * linux/fs/nfs/callback.h
+ *
+ * Copyright (C) 2004 Trond Myklebust
+ *
+ * NFSv4 callback definitions
+ */
+#ifndef __LINUX_FS_NFS_CALLBACK_H
+#define __LINUX_FS_NFS_CALLBACK_H
+
+#define NFS4_CALLBACK 0x40000000
+#define NFS4_CALLBACK_XDRSIZE 2048
+#define NFS4_CALLBACK_BUFSIZE (1024 + NFS4_CALLBACK_XDRSIZE)
+
+enum nfs4_callback_procnum {
+ CB_NULL = 0,
+ CB_COMPOUND = 1,
+};
+
+enum nfs4_callback_opnum {
+ OP_CB_GETATTR = 3,
+ OP_CB_RECALL = 4,
+ OP_CB_ILLEGAL = 10044,
+};
+
+struct cb_compound_hdr_arg {
+ int taglen;
+ const char *tag;
+ unsigned int callback_ident;
+ unsigned nops;
+};
+
+struct cb_compound_hdr_res {
+ uint32_t *status;
+ int taglen;
+ const char *tag;
+ uint32_t *nops;
+};
+
+struct cb_getattrargs {
+ struct sockaddr_in *addr;
+ struct nfs_fh fh;
+ uint32_t bitmap[2];
+};
+
+struct cb_getattrres {
+ uint32_t status;
+ uint32_t bitmap[2];
+ uint64_t size;
+ uint64_t change_attr;
+ struct timespec ctime;
+ struct timespec mtime;
+};
+
+struct cb_recallargs {
+ struct sockaddr_in *addr;
+ struct nfs_fh fh;
+ nfs4_stateid stateid;
+ uint32_t truncate;
+};
+
+extern unsigned nfs4_callback_getattr(struct cb_getattrargs *args, struct cb_getattrres *res);
+extern unsigned nfs4_callback_recall(struct cb_recallargs *args, void *dummy);
+
+extern int nfs_callback_up(void);
+extern int nfs_callback_down(void);
+
+extern unsigned short nfs_callback_tcpport;
+
+#endif /* __LINUX_FS_NFS_CALLBACK_H */
--- /dev/null
+/*
+ * linux/fs/nfs/callback_proc.c
+ *
+ * Copyright (C) 2004 Trond Myklebust
+ *
+ * NFSv4 callback procedures
+ */
+#include <linux/config.h>
+#include <linux/nfs4.h>
+#include <linux/nfs_fs.h>
+#include "callback.h"
+#include "delegation.h"
+
+#define NFSDBG_FACILITY NFSDBG_CALLBACK
+
+unsigned nfs4_callback_getattr(struct cb_getattrargs *args, struct cb_getattrres *res)
+{
+ struct nfs4_client *clp;
+ struct nfs_delegation *delegation;
+ struct nfs_inode *nfsi;
+ struct inode *inode;
+
+ res->bitmap[0] = res->bitmap[1] = 0;
+ res->status = htonl(NFS4ERR_BADHANDLE);
+ clp = nfs4_find_client(&args->addr->sin_addr);
+ if (clp == NULL)
+ goto out;
+ inode = nfs_delegation_find_inode(clp, &args->fh);
+ if (inode == NULL)
+ goto out_putclient;
+ nfsi = NFS_I(inode);
+ down_read(&nfsi->rwsem);
+ delegation = nfsi->delegation;
+ if (delegation == NULL || (delegation->type & FMODE_WRITE) == 0)
+ goto out_iput;
+ res->size = i_size_read(inode);
+ res->change_attr = NFS_CHANGE_ATTR(inode);
+ res->ctime = inode->i_ctime;
+ res->mtime = inode->i_mtime;
+ res->bitmap[0] = (FATTR4_WORD0_CHANGE|FATTR4_WORD0_SIZE) &
+ args->bitmap[0];
+ res->bitmap[1] = (FATTR4_WORD1_TIME_METADATA|FATTR4_WORD1_TIME_MODIFY) &
+ args->bitmap[1];
+ res->status = 0;
+out_iput:
+ up_read(&nfsi->rwsem);
+ iput(inode);
+out_putclient:
+ nfs4_put_client(clp);
+out:
+ dprintk("%s: exit with status = %d\n", __FUNCTION__, ntohl(res->status));
+ return res->status;
+}
+
+unsigned nfs4_callback_recall(struct cb_recallargs *args, void *dummy)
+{
+ struct nfs4_client *clp;
+ struct inode *inode;
+ unsigned res;
+
+ res = htonl(NFS4ERR_BADHANDLE);
+ clp = nfs4_find_client(&args->addr->sin_addr);
+ if (clp == NULL)
+ goto out;
+ inode = nfs_delegation_find_inode(clp, &args->fh);
+ if (inode == NULL)
+ goto out_putclient;
+ /* Set up a helper thread to actually return the delegation */
+ switch(nfs_async_inode_return_delegation(inode, &args->stateid)) {
+ case 0:
+ res = 0;
+ break;
+ case -ENOENT:
+ res = htonl(NFS4ERR_BAD_STATEID);
+ break;
+ default:
+ res = htonl(NFS4ERR_RESOURCE);
+ }
+ iput(inode);
+out_putclient:
+ nfs4_put_client(clp);
+out:
+ dprintk("%s: exit with status = %d\n", __FUNCTION__, ntohl(res));
+ return res;
+}
--- /dev/null
+/*
+ * linux/fs/nfs/callback_xdr.c
+ *
+ * Copyright (C) 2004 Trond Myklebust
+ *
+ * NFSv4 callback encode/decode procedures
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sunrpc/svc.h>
+#include <linux/nfs4.h>
+#include <linux/nfs_fs.h>
+#include "callback.h"
+
+#define CB_OP_TAGLEN_MAXSZ (512)
+#define CB_OP_HDR_RES_MAXSZ (2 + CB_OP_TAGLEN_MAXSZ)
+#define CB_OP_GETATTR_BITMAP_MAXSZ (4)
+#define CB_OP_GETATTR_RES_MAXSZ (CB_OP_HDR_RES_MAXSZ + \
+ CB_OP_GETATTR_BITMAP_MAXSZ + \
+ 2 + 2 + 3 + 3)
+#define CB_OP_RECALL_RES_MAXSZ (CB_OP_HDR_RES_MAXSZ)
+
+#define NFSDBG_FACILITY NFSDBG_CALLBACK
+
+typedef unsigned (*callback_process_op_t)(void *, void *);
+typedef unsigned (*callback_decode_arg_t)(struct svc_rqst *, struct xdr_stream *, void *);
+typedef unsigned (*callback_encode_res_t)(struct svc_rqst *, struct xdr_stream *, void *);
+
+
+struct callback_op {
+ callback_process_op_t process_op;
+ callback_decode_arg_t decode_args;
+ callback_encode_res_t encode_res;
+ long res_maxsize;
+};
+
+static struct callback_op callback_ops[];
+
+static int nfs4_callback_null(struct svc_rqst *rqstp, void *argp, void *resp)
+{
+ return htonl(NFS4_OK);
+}
+
+static int nfs4_decode_void(struct svc_rqst *rqstp, uint32_t *p, void *dummy)
+{
+ return xdr_argsize_check(rqstp, p);
+}
+
+static int nfs4_encode_void(struct svc_rqst *rqstp, uint32_t *p, void *dummy)
+{
+ return xdr_ressize_check(rqstp, p);
+}
+
+static uint32_t *read_buf(struct xdr_stream *xdr, int nbytes)
+{
+ uint32_t *p;
+
+ p = xdr_inline_decode(xdr, nbytes);
+ if (unlikely(p == NULL))
+ printk(KERN_WARNING "NFSv4 callback reply buffer overflowed!\n");
+ return p;
+}
+
+static unsigned decode_string(struct xdr_stream *xdr, unsigned int *len, const char **str)
+{
+ uint32_t *p;
+
+ p = read_buf(xdr, 4);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *len = ntohl(*p);
+
+ if (*len != 0) {
+ p = read_buf(xdr, *len);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *str = (const char *)p;
+ } else
+ *str = NULL;
+
+ return 0;
+}
+
+static unsigned decode_fh(struct xdr_stream *xdr, struct nfs_fh *fh)
+{
+ uint32_t *p;
+
+ p = read_buf(xdr, 4);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ fh->size = ntohl(*p);
+ if (fh->size > NFS4_FHSIZE)
+ return htonl(NFS4ERR_BADHANDLE);
+ p = read_buf(xdr, fh->size);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ memcpy(&fh->data[0], p, fh->size);
+ memset(&fh->data[fh->size], 0, sizeof(fh->data) - fh->size);
+ return 0;
+}
+
+static unsigned decode_bitmap(struct xdr_stream *xdr, uint32_t *bitmap)
+{
+ uint32_t *p;
+ unsigned int attrlen;
+
+ p = read_buf(xdr, 4);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ attrlen = ntohl(*p);
+ p = read_buf(xdr, attrlen << 2);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ if (likely(attrlen > 0))
+ bitmap[0] = ntohl(*p++);
+ if (attrlen > 1)
+ bitmap[1] = ntohl(*p);
+ return 0;
+}
+
+static unsigned decode_stateid(struct xdr_stream *xdr, nfs4_stateid *stateid)
+{
+ uint32_t *p;
+
+ p = read_buf(xdr, 16);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ memcpy(stateid->data, p, 16);
+ return 0;
+}
+
+static unsigned decode_compound_hdr_arg(struct xdr_stream *xdr, struct cb_compound_hdr_arg *hdr)
+{
+ uint32_t *p;
+ unsigned int minor_version;
+ unsigned status;
+
+ status = decode_string(xdr, &hdr->taglen, &hdr->tag);
+ if (unlikely(status != 0))
+ return status;
+ /* We do not like overly long tags! */
+ if (hdr->taglen > CB_OP_TAGLEN_MAXSZ-12 || hdr->taglen < 0) {
+ printk("NFSv4 CALLBACK %s: client sent tag of length %u\n",
+ __FUNCTION__, hdr->taglen);
+ return htonl(NFS4ERR_RESOURCE);
+ }
+ p = read_buf(xdr, 12);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ minor_version = ntohl(*p++);
+ /* Check minor version is zero. */
+ if (minor_version != 0) {
+ printk(KERN_WARNING "%s: NFSv4 server callback with illegal minor version %u!\n",
+ __FUNCTION__, minor_version);
+ return htonl(NFS4ERR_MINOR_VERS_MISMATCH);
+ }
+ hdr->callback_ident = ntohl(*p++);
+ hdr->nops = ntohl(*p);
+ return 0;
+}
+
+static unsigned decode_op_hdr(struct xdr_stream *xdr, unsigned int *op)
+{
+ uint32_t *p;
+ p = read_buf(xdr, 4);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *op = ntohl(*p);
+ return 0;
+}
+
+static unsigned decode_getattr_args(struct svc_rqst *rqstp, struct xdr_stream *xdr, struct cb_getattrargs *args)
+{
+ unsigned status;
+
+ status = decode_fh(xdr, &args->fh);
+ if (unlikely(status != 0))
+ goto out;
+ args->addr = &rqstp->rq_addr;
+ status = decode_bitmap(xdr, args->bitmap);
+out:
+ dprintk("%s: exit with status = %d\n", __FUNCTION__, status);
+ return status;
+}
+
+static unsigned decode_recall_args(struct svc_rqst *rqstp, struct xdr_stream *xdr, struct cb_recallargs *args)
+{
+ uint32_t *p;
+ unsigned status;
+
+ args->addr = &rqstp->rq_addr;
+ status = decode_stateid(xdr, &args->stateid);
+ if (unlikely(status != 0))
+ goto out;
+ p = read_buf(xdr, 4);
+ if (unlikely(p == NULL)) {
+ status = htonl(NFS4ERR_RESOURCE);
+ goto out;
+ }
+ args->truncate = ntohl(*p);
+ status = decode_fh(xdr, &args->fh);
+out:
+ dprintk("%s: exit with status = %d\n", __FUNCTION__, status);
+ return 0;
+}
+
+static unsigned encode_string(struct xdr_stream *xdr, unsigned int len, const char *str)
+{
+ uint32_t *p;
+
+ p = xdr_reserve_space(xdr, 4 + len);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ xdr_encode_opaque(p, str, len);
+ return 0;
+}
+
+#define CB_SUPPORTED_ATTR0 (FATTR4_WORD0_CHANGE|FATTR4_WORD0_SIZE)
+#define CB_SUPPORTED_ATTR1 (FATTR4_WORD1_TIME_METADATA|FATTR4_WORD1_TIME_MODIFY)
+static unsigned encode_attr_bitmap(struct xdr_stream *xdr, const uint32_t *bitmap, uint32_t **savep)
+{
+ uint32_t bm[2];
+ uint32_t *p;
+
+ bm[0] = htonl(bitmap[0] & CB_SUPPORTED_ATTR0);
+ bm[1] = htonl(bitmap[1] & CB_SUPPORTED_ATTR1);
+ if (bm[1] != 0) {
+ p = xdr_reserve_space(xdr, 16);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *p++ = htonl(2);
+ *p++ = bm[0];
+ *p++ = bm[1];
+ } else if (bm[0] != 0) {
+ p = xdr_reserve_space(xdr, 12);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *p++ = htonl(1);
+ *p++ = bm[0];
+ } else {
+ p = xdr_reserve_space(xdr, 8);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *p++ = htonl(0);
+ }
+ *savep = p;
+ return 0;
+}
+
+static unsigned encode_attr_change(struct xdr_stream *xdr, const uint32_t *bitmap, uint64_t change)
+{
+ uint32_t *p;
+
+ if (!(bitmap[0] & FATTR4_WORD0_CHANGE))
+ return 0;
+ p = xdr_reserve_space(xdr, 8);
+ if (unlikely(p == 0))
+ return htonl(NFS4ERR_RESOURCE);
+ p = xdr_encode_hyper(p, change);
+ return 0;
+}
+
+static unsigned encode_attr_size(struct xdr_stream *xdr, const uint32_t *bitmap, uint64_t size)
+{
+ uint32_t *p;
+
+ if (!(bitmap[0] & FATTR4_WORD0_SIZE))
+ return 0;
+ p = xdr_reserve_space(xdr, 8);
+ if (unlikely(p == 0))
+ return htonl(NFS4ERR_RESOURCE);
+ p = xdr_encode_hyper(p, size);
+ return 0;
+}
+
+static unsigned encode_attr_time(struct xdr_stream *xdr, const struct timespec *time)
+{
+ uint32_t *p;
+
+ p = xdr_reserve_space(xdr, 12);
+ if (unlikely(p == 0))
+ return htonl(NFS4ERR_RESOURCE);
+ p = xdr_encode_hyper(p, time->tv_sec);
+ *p = htonl(time->tv_nsec);
+ return 0;
+}
+
+static unsigned encode_attr_ctime(struct xdr_stream *xdr, const uint32_t *bitmap, const struct timespec *time)
+{
+ if (!(bitmap[1] & FATTR4_WORD1_TIME_METADATA))
+ return 0;
+ return encode_attr_time(xdr,time);
+}
+
+static unsigned encode_attr_mtime(struct xdr_stream *xdr, const uint32_t *bitmap, const struct timespec *time)
+{
+ if (!(bitmap[1] & FATTR4_WORD1_TIME_MODIFY))
+ return 0;
+ return encode_attr_time(xdr,time);
+}
+
+static unsigned encode_compound_hdr_res(struct xdr_stream *xdr, struct cb_compound_hdr_res *hdr)
+{
+ unsigned status;
+
+ hdr->status = xdr_reserve_space(xdr, 4);
+ if (unlikely(hdr->status == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ status = encode_string(xdr, hdr->taglen, hdr->tag);
+ if (unlikely(status != 0))
+ return status;
+ hdr->nops = xdr_reserve_space(xdr, 4);
+ if (unlikely(hdr->nops == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ return 0;
+}
+
+static unsigned encode_op_hdr(struct xdr_stream *xdr, uint32_t op, uint32_t res)
+{
+ uint32_t *p;
+
+ p = xdr_reserve_space(xdr, 8);
+ if (unlikely(p == NULL))
+ return htonl(NFS4ERR_RESOURCE);
+ *p++ = htonl(op);
+ *p = res;
+ return 0;
+}
+
+static unsigned encode_getattr_res(struct svc_rqst *rqstp, struct xdr_stream *xdr, const struct cb_getattrres *res)
+{
+ uint32_t *savep;
+ unsigned status = res->status;
+
+ if (unlikely(status != 0))
+ goto out;
+ status = encode_attr_bitmap(xdr, res->bitmap, &savep);
+ if (unlikely(status != 0))
+ goto out;
+ status = encode_attr_change(xdr, res->bitmap, res->change_attr);
+ if (unlikely(status != 0))
+ goto out;
+ status = encode_attr_size(xdr, res->bitmap, res->size);
+ if (unlikely(status != 0))
+ goto out;
+ status = encode_attr_ctime(xdr, res->bitmap, &res->ctime);
+ if (unlikely(status != 0))
+ goto out;
+ status = encode_attr_mtime(xdr, res->bitmap, &res->mtime);
+ *savep = htonl((unsigned int)((char *)xdr->p - (char *)(savep+1)));
+out:
+ dprintk("%s: exit with status = %d\n", __FUNCTION__, status);
+ return status;
+}
+
+static unsigned process_op(struct svc_rqst *rqstp,
+ struct xdr_stream *xdr_in, void *argp,
+ struct xdr_stream *xdr_out, void *resp)
+{
+ struct callback_op *op;
+ unsigned int op_nr;
+ unsigned int status = 0;
+ long maxlen;
+ unsigned res;
+
+ dprintk("%s: start\n", __FUNCTION__);
+ status = decode_op_hdr(xdr_in, &op_nr);
+ if (unlikely(status != 0)) {
+ op_nr = OP_CB_ILLEGAL;
+ op = &callback_ops[0];
+ } else if (unlikely(op_nr != OP_CB_GETATTR && op_nr != OP_CB_RECALL)) {
+ op_nr = OP_CB_ILLEGAL;
+ op = &callback_ops[0];
+ status = htonl(NFS4ERR_OP_ILLEGAL);
+ } else
+ op = &callback_ops[op_nr];
+
+ maxlen = xdr_out->end - xdr_out->p;
+ if (maxlen > 0 && maxlen < PAGE_SIZE) {
+ if (likely(status == 0 && op->decode_args != NULL))
+ status = op->decode_args(rqstp, xdr_in, argp);
+ if (likely(status == 0 && op->process_op != NULL))
+ status = op->process_op(argp, resp);
+ } else
+ status = htonl(NFS4ERR_RESOURCE);
+
+ res = encode_op_hdr(xdr_out, op_nr, status);
+ if (status == 0)
+ status = res;
+ if (op->encode_res != NULL && status == 0)
+ status = op->encode_res(rqstp, xdr_out, resp);
+ dprintk("%s: done, status = %d\n", __FUNCTION__, status);
+ return status;
+}
+
+/*
+ * Decode, process and encode a COMPOUND
+ */
+static int nfs4_callback_compound(struct svc_rqst *rqstp, void *argp, void *resp)
+{
+ struct cb_compound_hdr_arg hdr_arg;
+ struct cb_compound_hdr_res hdr_res;
+ struct xdr_stream xdr_in, xdr_out;
+ uint32_t *p;
+ unsigned int status;
+ unsigned int nops = 1;
+
+ dprintk("%s: start\n", __FUNCTION__);
+
+ xdr_init_decode(&xdr_in, &rqstp->rq_arg, rqstp->rq_arg.head[0].iov_base);
+
+ p = (uint32_t*)((char *)rqstp->rq_res.head[0].iov_base + rqstp->rq_res.head[0].iov_len);
+ rqstp->rq_res.head[0].iov_len = PAGE_SIZE;
+ xdr_init_encode(&xdr_out, &rqstp->rq_res, p);
+
+ decode_compound_hdr_arg(&xdr_in, &hdr_arg);
+ hdr_res.taglen = hdr_arg.taglen;
+ hdr_res.tag = hdr_arg.tag;
+ encode_compound_hdr_res(&xdr_out, &hdr_res);
+
+ for (;;) {
+ status = process_op(rqstp, &xdr_in, argp, &xdr_out, resp);
+ if (status != 0)
+ break;
+ if (nops == hdr_arg.nops)
+ break;
+ nops++;
+ }
+ *hdr_res.status = status;
+ *hdr_res.nops = htonl(nops);
+ dprintk("%s: done, status = %u\n", __FUNCTION__, status);
+ return rpc_success;
+}
+
+/*
+ * Define NFS4 callback COMPOUND ops.
+ */
+static struct callback_op callback_ops[] = {
+ [0] = {
+ .res_maxsize = CB_OP_HDR_RES_MAXSZ,
+ },
+ [OP_CB_GETATTR] = {
+ .process_op = (callback_process_op_t)nfs4_callback_getattr,
+ .decode_args = (callback_decode_arg_t)decode_getattr_args,
+ .encode_res = (callback_encode_res_t)encode_getattr_res,
+ .res_maxsize = CB_OP_GETATTR_RES_MAXSZ,
+ },
+ [OP_CB_RECALL] = {
+ .process_op = (callback_process_op_t)nfs4_callback_recall,
+ .decode_args = (callback_decode_arg_t)decode_recall_args,
+ .res_maxsize = CB_OP_RECALL_RES_MAXSZ,
+ }
+};
+
+/*
+ * Define NFS4 callback procedures
+ */
+static struct svc_procedure nfs4_callback_procedures1[] = {
+ [CB_NULL] = {
+ .pc_func = nfs4_callback_null,
+ .pc_decode = (kxdrproc_t)nfs4_decode_void,
+ .pc_encode = (kxdrproc_t)nfs4_encode_void,
+ .pc_xdrressize = 1,
+ },
+ [CB_COMPOUND] = {
+ .pc_func = nfs4_callback_compound,
+ .pc_encode = (kxdrproc_t)nfs4_encode_void,
+ .pc_argsize = 256,
+ .pc_ressize = 256,
+ .pc_xdrressize = NFS4_CALLBACK_BUFSIZE,
+ }
+};
+
+struct svc_version nfs4_callback_version1 = {
+ .vs_vers = 1,
+ .vs_nproc = ARRAY_SIZE(nfs4_callback_procedures1),
+ .vs_proc = nfs4_callback_procedures1,
+ .vs_xdrsize = NFS4_CALLBACK_XDRSIZE,
+ .vs_dispatch = NULL,
+};
+
--- /dev/null
+/*
+ * linux/fs/nfs/delegation.c
+ *
+ * Copyright (C) 2004 Trond Myklebust
+ *
+ * NFS file delegation management
+ *
+ */
+#include <linux/config.h>
+#include <linux/completion.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+
+#include <linux/nfs4.h>
+#include <linux/nfs_fs.h>
+#include <linux/nfs_xdr.h>
+
+#include "delegation.h"
+
+static struct nfs_delegation *nfs_alloc_delegation(void)
+{
+ return (struct nfs_delegation *)kmalloc(sizeof(struct nfs_delegation), GFP_KERNEL);
+}
+
+static void nfs_free_delegation(struct nfs_delegation *delegation)
+{
+ if (delegation->cred)
+ put_rpccred(delegation->cred);
+ kfree(delegation);
+}
+
+static void nfs_delegation_claim_opens(struct inode *inode)
+{
+ struct nfs_inode *nfsi = NFS_I(inode);
+ struct nfs_open_context *ctx;
+ struct nfs4_state *state;
+
+again:
+ spin_lock(&inode->i_lock);
+ list_for_each_entry(ctx, &nfsi->open_files, list) {
+ state = ctx->state;
+ if (state == NULL)
+ continue;
+ if (!test_bit(NFS_DELEGATED_STATE, &state->flags))
+ continue;
+ get_nfs_open_context(ctx);
+ spin_unlock(&inode->i_lock);
+ if (nfs4_open_delegation_recall(ctx->dentry, state) < 0)
+ return;
+ put_nfs_open_context(ctx);
+ goto again;
+ }
+ spin_unlock(&inode->i_lock);
+}
+
+/*
+ * Set up a delegation on an inode
+ */
+void nfs_inode_reclaim_delegation(struct inode *inode, struct rpc_cred *cred, struct nfs_openres *res)
+{
+ struct nfs_delegation *delegation = NFS_I(inode)->delegation;
+
+ if (delegation == NULL)
+ return;
+ memcpy(delegation->stateid.data, res->delegation.data,
+ sizeof(delegation->stateid.data));
+ delegation->type = res->delegation_type;
+ delegation->maxsize = res->maxsize;
+ put_rpccred(cred);
+ delegation->cred = get_rpccred(cred);
+ delegation->flags &= ~NFS_DELEGATION_NEED_RECLAIM;
+ NFS_I(inode)->delegation_state = delegation->type;
+ smp_wmb();
+}
+
+/*
+ * Set up a delegation on an inode
+ */
+int nfs_inode_set_delegation(struct inode *inode, struct rpc_cred *cred, struct nfs_openres *res)
+{
+ struct nfs4_client *clp = NFS_SERVER(inode)->nfs4_state;
+ struct nfs_inode *nfsi = NFS_I(inode);
+ struct nfs_delegation *delegation;
+ int status = 0;
+
+ delegation = nfs_alloc_delegation();
+ if (delegation == NULL)
+ return -ENOMEM;
+ memcpy(delegation->stateid.data, res->delegation.data,
+ sizeof(delegation->stateid.data));
+ delegation->type = res->delegation_type;
+ delegation->maxsize = res->maxsize;
+ delegation->cred = get_rpccred(cred);
+ delegation->inode = inode;
+
+ spin_lock(&clp->cl_lock);
+ if (nfsi->delegation == NULL) {
+ list_add(&delegation->super_list, &clp->cl_delegations);
+ nfsi->delegation = delegation;
+ nfsi->delegation_state = delegation->type;
+ delegation = NULL;
+ } else {
+ if (memcmp(&delegation->stateid, &nfsi->delegation->stateid,
+ sizeof(delegation->stateid)) != 0 ||
+ delegation->type != nfsi->delegation->type) {
+ printk("%s: server %u.%u.%u.%u, handed out a duplicate delegation!\n",
+ __FUNCTION__, NIPQUAD(clp->cl_addr));
+ status = -EIO;
+ }
+ }
+ spin_unlock(&clp->cl_lock);
+ if (delegation != NULL)
+ kfree(delegation);
+ return status;
+}
+
+static int nfs_do_return_delegation(struct inode *inode, struct nfs_delegation *delegation)
+{
+ int res = 0;
+
+ __nfs_revalidate_inode(NFS_SERVER(inode), inode);
+
+ res = nfs4_proc_delegreturn(inode, delegation->cred, &delegation->stateid);
+ nfs_free_delegation(delegation);
+ return res;
+}
+
+/* Sync all data to disk upon delegation return */
+static void nfs_msync_inode(struct inode *inode)
+{
+ filemap_fdatawrite(inode->i_mapping);
+ nfs_wb_all(inode);
+ filemap_fdatawait(inode->i_mapping);
+}
+
+/*
+ * Basic procedure for returning a delegation to the server
+ */
+int nfs_inode_return_delegation(struct inode *inode)
+{
+ struct nfs4_client *clp = NFS_SERVER(inode)->nfs4_state;
+ struct nfs_inode *nfsi = NFS_I(inode);
+ struct nfs_delegation *delegation;
+ int res = 0;
+
+ nfs_msync_inode(inode);
+ down_read(&clp->cl_sem);
+ /* Guard against new delegated open calls */
+ down_write(&nfsi->rwsem);
+ spin_lock(&clp->cl_lock);
+ delegation = nfsi->delegation;
+ if (delegation != NULL) {
+ list_del_init(&delegation->super_list);
+ nfsi->delegation = NULL;
+ nfsi->delegation_state = 0;
+ }
+ spin_unlock(&clp->cl_lock);
+ nfs_delegation_claim_opens(inode);
+ up_write(&nfsi->rwsem);
+ up_read(&clp->cl_sem);
+ nfs_msync_inode(inode);
+
+ if (delegation != NULL)
+ res = nfs_do_return_delegation(inode, delegation);
+ return res;
+}
+
+/*
+ * Return all delegations associated to a super block
+ */
+void nfs_return_all_delegations(struct super_block *sb)
+{
+ struct nfs4_client *clp = NFS_SB(sb)->nfs4_state;
+ struct nfs_delegation *delegation;
+ struct inode *inode;
+
+ if (clp == NULL)
+ return;
+restart:
+ spin_lock(&clp->cl_lock);
+ list_for_each_entry(delegation, &clp->cl_delegations, super_list) {
+ if (delegation->inode->i_sb != sb)
+ continue;
+ inode = igrab(delegation->inode);
+ if (inode == NULL)
+ continue;
+ spin_unlock(&clp->cl_lock);
+ nfs_inode_return_delegation(inode);
+ iput(inode);
+ goto restart;
+ }
+ spin_unlock(&clp->cl_lock);
+}
+
+/*
+ * Return all delegations following an NFS4ERR_CB_PATH_DOWN error.
+ */
+void nfs_handle_cb_pathdown(struct nfs4_client *clp)
+{
+ struct nfs_delegation *delegation;
+ struct inode *inode;
+
+ if (clp == NULL)
+ return;
+restart:
+ spin_lock(&clp->cl_lock);
+ list_for_each_entry(delegation, &clp->cl_delegations, super_list) {
+ inode = igrab(delegation->inode);
+ if (inode == NULL)
+ continue;
+ spin_unlock(&clp->cl_lock);
+ nfs_inode_return_delegation(inode);
+ iput(inode);
+ goto restart;
+ }
+ spin_unlock(&clp->cl_lock);
+}
+
+struct recall_threadargs {
+ struct inode *inode;
+ struct nfs4_client *clp;
+ const nfs4_stateid *stateid;
+
+ struct completion started;
+ int result;
+};
+
+static int recall_thread(void *data)
+{
+ struct recall_threadargs *args = (struct recall_threadargs *)data;
+ struct inode *inode = igrab(args->inode);
+ struct nfs4_client *clp = NFS_SERVER(inode)->nfs4_state;
+ struct nfs_inode *nfsi = NFS_I(inode);
+ struct nfs_delegation *delegation;
+
+ daemonize("nfsv4-delegreturn");
+
+ nfs_msync_inode(inode);
+ down_read(&clp->cl_sem);
+ down_write(&nfsi->rwsem);
+ spin_lock(&clp->cl_lock);
+ delegation = nfsi->delegation;
+ if (delegation != NULL && memcmp(delegation->stateid.data,
+ args->stateid->data,
+ sizeof(delegation->stateid.data)) == 0) {
+ list_del_init(&delegation->super_list);
+ nfsi->delegation = NULL;
+ nfsi->delegation_state = 0;
+ args->result = 0;
+ } else {
+ delegation = NULL;
+ args->result = -ENOENT;
+ }
+ spin_unlock(&clp->cl_lock);
+ complete(&args->started);
+ nfs_delegation_claim_opens(inode);
+ up_write(&nfsi->rwsem);
+ up_read(&clp->cl_sem);
+ nfs_msync_inode(inode);
+
+ if (delegation != NULL)
+ nfs_do_return_delegation(inode, delegation);
+ iput(inode);
+ module_put_and_exit(0);
+}
+
+/*
+ * Asynchronous delegation recall!
+ */
+int nfs_async_inode_return_delegation(struct inode *inode, const nfs4_stateid *stateid)
+{
+ struct recall_threadargs data = {
+ .inode = inode,
+ .stateid = stateid,
+ };
+ int status;
+
+ init_completion(&data.started);
+ __module_get(THIS_MODULE);
+ status = kernel_thread(recall_thread, &data, CLONE_KERNEL);
+ if (status < 0)
+ goto out_module_put;
+ wait_for_completion(&data.started);
+ return data.result;
+out_module_put:
+ module_put(THIS_MODULE);
+ return status;
+}
+
+/*
+ * Retrieve the inode associated with a delegation
+ */
+struct inode *nfs_delegation_find_inode(struct nfs4_client *clp, const struct nfs_fh *fhandle)
+{
+ struct nfs_delegation *delegation;
+ struct inode *res = NULL;
+ spin_lock(&clp->cl_lock);
+ list_for_each_entry(delegation, &clp->cl_delegations, super_list) {
+ if (nfs_compare_fh(fhandle, &NFS_I(delegation->inode)->fh) == 0) {
+ res = igrab(delegation->inode);
+ break;
+ }
+ }
+ spin_unlock(&clp->cl_lock);
+ return res;
+}
+
+/*
+ * Mark all delegations as needing to be reclaimed
+ */
+void nfs_delegation_mark_reclaim(struct nfs4_client *clp)
+{
+ struct nfs_delegation *delegation;
+ spin_lock(&clp->cl_lock);
+ list_for_each_entry(delegation, &clp->cl_delegations, super_list)
+ delegation->flags |= NFS_DELEGATION_NEED_RECLAIM;
+ spin_unlock(&clp->cl_lock);
+}
+
+/*
+ * Reap all unclaimed delegations after reboot recovery is done
+ */
+void nfs_delegation_reap_unclaimed(struct nfs4_client *clp)
+{
+ struct nfs_delegation *delegation, *n;
+ LIST_HEAD(head);
+ spin_lock(&clp->cl_lock);
+ list_for_each_entry_safe(delegation, n, &clp->cl_delegations, super_list) {
+ if ((delegation->flags & NFS_DELEGATION_NEED_RECLAIM) == 0)
+ continue;
+ list_move(&delegation->super_list, &head);
+ NFS_I(delegation->inode)->delegation = NULL;
+ NFS_I(delegation->inode)->delegation_state = 0;
+ }
+ spin_unlock(&clp->cl_lock);
+ while(!list_empty(&head)) {
+ delegation = list_entry(head.next, struct nfs_delegation, super_list);
+ list_del(&delegation->super_list);
+ nfs_free_delegation(delegation);
+ }
+}
--- /dev/null
+/*
+ * linux/fs/nfs/delegation.h
+ *
+ * Copyright (c) Trond Myklebust
+ *
+ * Definitions pertaining to NFS delegated files
+ */
+#ifndef FS_NFS_DELEGATION_H
+#define FS_NFS_DELEGATION_H
+
+#if defined(CONFIG_NFS_V4)
+/*
+ * NFSv4 delegation
+ */
+struct nfs_delegation {
+ struct list_head super_list;
+ struct rpc_cred *cred;
+ struct inode *inode;
+ nfs4_stateid stateid;
+ int type;
+#define NFS_DELEGATION_NEED_RECLAIM 1
+ long flags;
+ loff_t maxsize;
+};
+
+int nfs_inode_set_delegation(struct inode *inode, struct rpc_cred *cred, struct nfs_openres *res);
+void nfs_inode_reclaim_delegation(struct inode *inode, struct rpc_cred *cred, struct nfs_openres *res);
+int nfs_inode_return_delegation(struct inode *inode);
+int nfs_async_inode_return_delegation(struct inode *inode, const nfs4_stateid *stateid);
+
+struct inode *nfs_delegation_find_inode(struct nfs4_client *clp, const struct nfs_fh *fhandle);
+void nfs_return_all_delegations(struct super_block *sb);
+void nfs_handle_cb_pathdown(struct nfs4_client *clp);
+
+void nfs_delegation_mark_reclaim(struct nfs4_client *clp);
+void nfs_delegation_reap_unclaimed(struct nfs4_client *clp);
+
+/* NFSv4 delegation-related procedures */
+int nfs4_proc_delegreturn(struct inode *inode, struct rpc_cred *cred, const nfs4_stateid *stateid);
+int nfs4_open_delegation_recall(struct dentry *dentry, struct nfs4_state *state);
+
+static inline int nfs_have_delegation(struct inode *inode, int flags)
+{
+ flags &= FMODE_READ|FMODE_WRITE;
+ smp_rmb();
+ if ((NFS_I(inode)->delegation_state & flags) == flags)
+ return 1;
+ return 0;
+}
+#else
+static inline int nfs_have_delegation(struct inode *inode, int flags)
+{
+ return 0;
+}
+#endif
+
+#endif
--- /dev/null
+/*
+ * fs/nfs4acl/acl.c
+ *
+ * Common NFSv4 ACL handling code.
+ *
+ * Copyright (c) 2002, 2003 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Marius Aamodt Eriksen <marius@umich.edu>
+ * Jeff Sedlak <jsedlak@umich.edu>
+ * J. Bruce Fields <bfields@umich.edu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/module.h>
+#include <linux/nfs_fs.h>
+#include <linux/posix_acl.h>
+#include <linux/nfs4.h>
+#include <linux/nfs4_acl.h>
+
+
+/* mode bit translations: */
+#define NFS4_READ_MODE (NFS4_ACE_READ_DATA | NFS4_ACE_READ_NAMED_ATTRS)
+#define NFS4_WRITE_MODE (NFS4_ACE_WRITE_DATA | NFS4_ACE_WRITE_NAMED_ATTRS | NFS4_ACE_APPEND_DATA)
+#define NFS4_EXECUTE_MODE NFS4_ACE_EXECUTE
+#define NFS4_ANYONE_MODE (NFS4_ACE_READ_ATTRIBUTES | NFS4_ACE_READ_ACL | NFS4_ACE_SYNCHRONIZE)
+#define NFS4_OWNER_MODE (NFS4_ACE_WRITE_ATTRIBUTES | NFS4_ACE_WRITE_ACL)
+
+/* flags used to simulate posix default ACLs */
+#define NFS4_INHERITANCE_FLAGS (NFS4_ACE_FILE_INHERIT_ACE \
+ | NFS4_ACE_DIRECTORY_INHERIT_ACE | NFS4_ACE_INHERIT_ONLY_ACE)
+
+#define MASK_EQUAL(mask1, mask2) \
+ ( ((mask1) & NFS4_ACE_MASK_ALL) == ((mask2) & NFS4_ACE_MASK_ALL) )
+
+static u32
+mask_from_posix(unsigned short perm, unsigned int flags)
+{
+ int mask = NFS4_ANYONE_MODE;
+
+ if (flags & NFS4_ACL_OWNER)
+ mask |= NFS4_OWNER_MODE;
+ if (perm & ACL_READ)
+ mask |= NFS4_READ_MODE;
+ if (perm & ACL_WRITE)
+ mask |= NFS4_WRITE_MODE;
+ if ((perm & ACL_WRITE) && (flags & NFS4_ACL_DIR))
+ mask |= NFS4_ACE_DELETE_CHILD;
+ if (perm & ACL_EXECUTE)
+ mask |= NFS4_EXECUTE_MODE;
+ return mask;
+}
+
+static u32
+deny_mask(u32 allow_mask, unsigned int flags)
+{
+ u32 ret = ~allow_mask & ~NFS4_ACE_DELETE;
+ if (!(flags & NFS4_ACL_DIR))
+ ret &= ~NFS4_ACE_DELETE_CHILD;
+ return ret;
+}
+
+static int
+mode_from_nfs4(u32 perm, unsigned short *mode, unsigned int flags)
+{
+ u32 ignore = 0;
+
+ if (!(flags & NFS4_ACL_DIR))
+ ignore |= NFS4_ACE_DELETE_CHILD; /* ignore it */
+ perm |= ignore;
+ *mode = 0;
+ if ((perm & NFS4_READ_MODE) == NFS4_READ_MODE)
+ *mode |= ACL_READ;
+ if ((perm & NFS4_WRITE_MODE) == NFS4_WRITE_MODE)
+ *mode |= ACL_WRITE;
+ if ((perm & NFS4_EXECUTE_MODE) == NFS4_EXECUTE_MODE)
+ *mode |= ACL_EXECUTE;
+ if (!MASK_EQUAL(perm, ignore|mask_from_posix(*mode, flags)))
+ return -EINVAL;
+ return 0;
+}
+
+struct ace_container {
+ struct nfs4_ace *ace;
+ struct list_head ace_l;
+};
+
+static short ace2type(struct nfs4_ace *);
+static int _posix_to_nfsv4_one(struct posix_acl *, struct nfs4_acl *, unsigned int);
+static struct posix_acl *_nfsv4_to_posix_one(struct nfs4_acl *, unsigned int);
+int nfs4_acl_add_ace(struct nfs4_acl *, u32, u32, u32, int, uid_t);
+int nfs4_acl_split(struct nfs4_acl *, struct nfs4_acl *);
+
+struct nfs4_acl *
+nfs4_acl_posix_to_nfsv4(struct posix_acl *pacl, struct posix_acl *dpacl,
+ unsigned int flags)
+{
+ struct nfs4_acl *acl;
+ int error = -EINVAL;
+
+ if ((pacl != NULL &&
+ (posix_acl_valid(pacl) < 0 || pacl->a_count == 0)) ||
+ (dpacl != NULL &&
+ (posix_acl_valid(dpacl) < 0 || dpacl->a_count == 0)))
+ goto out_err;
+
+ acl = nfs4_acl_new();
+ if (acl == NULL) {
+ error = -ENOMEM;
+ goto out_err;
+ }
+
+ if (pacl != NULL) {
+ error = _posix_to_nfsv4_one(pacl, acl,
+ flags & ~NFS4_ACL_TYPE_DEFAULT);
+ if (error < 0)
+ goto out_acl;
+ }
+
+ if (dpacl != NULL) {
+ error = _posix_to_nfsv4_one(dpacl, acl,
+ flags | NFS4_ACL_TYPE_DEFAULT);
+ if (error < 0)
+ goto out_acl;
+ }
+
+ return acl;
+
+out_acl:
+ nfs4_acl_free(acl);
+out_err:
+ acl = ERR_PTR(error);
+
+ return acl;
+}
+
+static int
+nfs4_acl_add_pair(struct nfs4_acl *acl, int eflag, u32 mask, int whotype,
+ uid_t owner, unsigned int flags)
+{
+ int error;
+
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE,
+ eflag, mask, whotype, owner);
+ if (error < 0)
+ return error;
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_DENIED_ACE_TYPE,
+ eflag, deny_mask(mask, flags), whotype, owner);
+ return error;
+}
+
+/* We assume the acl has been verified with posix_acl_valid. */
+static int
+_posix_to_nfsv4_one(struct posix_acl *pacl, struct nfs4_acl *acl,
+ unsigned int flags)
+{
+ struct posix_acl_entry *pa, *pe, *group_owner_entry;
+ int error = -EINVAL;
+ u32 mask, mask_mask;
+ int eflag = ((flags & NFS4_ACL_TYPE_DEFAULT) ?
+ NFS4_INHERITANCE_FLAGS : 0);
+
+ BUG_ON(pacl->a_count < 3);
+ pe = pacl->a_entries + pacl->a_count;
+ pa = pe - 2; /* if mask entry exists, it's second from the last. */
+ if (pa->e_tag == ACL_MASK)
+ mask_mask = deny_mask(mask_from_posix(pa->e_perm, flags), flags);
+ else
+ mask_mask = 0;
+
+ pa = pacl->a_entries;
+ BUG_ON(pa->e_tag != ACL_USER_OBJ);
+ mask = mask_from_posix(pa->e_perm, flags | NFS4_ACL_OWNER);
+ error = nfs4_acl_add_pair(acl, eflag, mask, NFS4_ACL_WHO_OWNER, 0, flags);
+ if (error < 0)
+ goto out;
+ pa++;
+
+ while (pa->e_tag == ACL_USER) {
+ mask = mask_from_posix(pa->e_perm, flags);
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_DENIED_ACE_TYPE,
+ eflag, mask_mask, NFS4_ACL_WHO_NAMED, pa->e_id);
+ if (error < 0)
+ goto out;
+
+
+ error = nfs4_acl_add_pair(acl, eflag, mask,
+ NFS4_ACL_WHO_NAMED, pa->e_id, flags);
+ if (error < 0)
+ goto out;
+ pa++;
+ }
+
+ /* In the case of groups, we apply allow ACEs first, then deny ACEs,
+ * since a user can be in more than one group. */
+
+ /* allow ACEs */
+
+ if (pacl->a_count > 3) {
+ BUG_ON(pa->e_tag != ACL_GROUP_OBJ);
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_DENIED_ACE_TYPE,
+ NFS4_ACE_IDENTIFIER_GROUP | eflag, mask_mask,
+ NFS4_ACL_WHO_GROUP, 0);
+ if (error < 0)
+ goto out;
+ }
+ group_owner_entry = pa;
+ mask = mask_from_posix(pa->e_perm, flags);
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE,
+ NFS4_ACE_IDENTIFIER_GROUP | eflag, mask,
+ NFS4_ACL_WHO_GROUP, 0);
+ if (error < 0)
+ goto out;
+ pa++;
+
+ while (pa->e_tag == ACL_GROUP) {
+ mask = mask_from_posix(pa->e_perm, flags);
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_DENIED_ACE_TYPE,
+ NFS4_ACE_IDENTIFIER_GROUP | eflag, mask_mask,
+ NFS4_ACL_WHO_NAMED, pa->e_id);
+ if (error < 0)
+ goto out;
+
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE,
+ NFS4_ACE_IDENTIFIER_GROUP | eflag, mask,
+ NFS4_ACL_WHO_NAMED, pa->e_id);
+ if (error < 0)
+ goto out;
+ pa++;
+ }
+
+ /* deny ACEs */
+
+ pa = group_owner_entry;
+ mask = mask_from_posix(pa->e_perm, flags);
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_DENIED_ACE_TYPE,
+ NFS4_ACE_IDENTIFIER_GROUP | eflag,
+ deny_mask(mask, flags), NFS4_ACL_WHO_GROUP, 0);
+ if (error < 0)
+ goto out;
+ pa++;
+ while (pa->e_tag == ACL_GROUP) {
+ mask = mask_from_posix(pa->e_perm, flags);
+ error = nfs4_acl_add_ace(acl, NFS4_ACE_ACCESS_DENIED_ACE_TYPE,
+ NFS4_ACE_IDENTIFIER_GROUP | eflag,
+ deny_mask(mask, flags), NFS4_ACL_WHO_NAMED, pa->e_id);
+ if (error < 0)
+ goto out;
+ pa++;
+ }
+
+ if (pa->e_tag == ACL_MASK)
+ pa++;
+ BUG_ON(pa->e_tag != ACL_OTHER);
+ mask = mask_from_posix(pa->e_perm, flags);
+ error = nfs4_acl_add_pair(acl, eflag, mask, NFS4_ACL_WHO_EVERYONE, 0, flags);
+
+out:
+ return error;
+}
+
+static void
+sort_pacl_range(struct posix_acl *pacl, int start, int end) {
+ int sorted = 0, i;
+ struct posix_acl_entry tmp;
+
+ /* We just do a bubble sort; easy to do in place, and we're not
+ * expecting acl's to be long enough to justify anything more. */
+ while (!sorted) {
+ sorted = 1;
+ for (i = start; i < end; i++) {
+ if (pacl->a_entries[i].e_id
+ > pacl->a_entries[i+1].e_id) {
+ sorted = 0;
+ tmp = pacl->a_entries[i];
+ pacl->a_entries[i] = pacl->a_entries[i+1];
+ pacl->a_entries[i+1] = tmp;
+ }
+ }
+ }
+}
+
+static void
+sort_pacl(struct posix_acl *pacl)
+{
+ /* posix_acl_valid requires that users and groups be in order
+ * by uid/gid. */
+ int i, j;
+
+ if (pacl->a_count <= 4)
+ return; /* no users or groups */
+ i = 1;
+ while (pacl->a_entries[i].e_tag == ACL_USER)
+ i++;
+ sort_pacl_range(pacl, 1, i-1);
+
+ BUG_ON(pacl->a_entries[i].e_tag != ACL_GROUP_OBJ);
+ j = i++;
+ while (pacl->a_entries[j].e_tag == ACL_GROUP)
+ j++;
+ sort_pacl_range(pacl, i, j-1);
+ return;
+}
+
+static int
+write_pace(struct nfs4_ace *ace, struct posix_acl *pacl,
+ struct posix_acl_entry **pace, short tag, unsigned int flags)
+{
+ struct posix_acl_entry *this = *pace;
+
+ if (*pace == pacl->a_entries + pacl->a_count)
+ return -EINVAL; /* fell off the end */
+ (*pace)++;
+ this->e_tag = tag;
+ if (tag == ACL_USER_OBJ)
+ flags |= NFS4_ACL_OWNER;
+ if (mode_from_nfs4(ace->access_mask, &this->e_perm, flags))
+ return -EINVAL;
+ this->e_id = (tag == ACL_USER || tag == ACL_GROUP ?
+ ace->who : ACL_UNDEFINED_ID);
+ return 0;
+}
+
+static struct nfs4_ace *
+get_next_v4_ace(struct list_head **p, struct list_head *head)
+{
+ struct nfs4_ace *ace;
+
+ *p = (*p)->next;
+ if (*p == head)
+ return NULL;
+ ace = list_entry(*p, struct nfs4_ace, l_ace);
+
+ return ace;
+}
+
+int
+nfs4_acl_nfsv4_to_posix(struct nfs4_acl *acl, struct posix_acl **pacl,
+ struct posix_acl **dpacl, unsigned int flags)
+{
+ struct nfs4_acl *dacl;
+ int error = -ENOMEM;
+
+ *pacl = NULL;
+ *dpacl = NULL;
+
+ dacl = nfs4_acl_new();
+ if (dacl == NULL)
+ goto out;
+
+ error = nfs4_acl_split(acl, dacl);
+ if (error < 0)
+ goto out_acl;
+
+ if (pacl != NULL) {
+ if (acl->naces == 0) {
+ error = -ENODATA;
+ goto try_dpacl;
+ }
+
+ *pacl = _nfsv4_to_posix_one(acl, flags);
+ if (IS_ERR(*pacl)) {
+ error = PTR_ERR(*pacl);
+ *pacl = NULL;
+ goto out_acl;
+ }
+ }
+
+try_dpacl:
+ if (dpacl != NULL) {
+ if (dacl->naces == 0) {
+ if (pacl == NULL || *pacl == NULL)
+ error = -ENODATA;
+ goto out_acl;
+ }
+
+ error = 0;
+ *dpacl = _nfsv4_to_posix_one(dacl, flags);
+ if (IS_ERR(*dpacl)) {
+ error = PTR_ERR(*dpacl);
+ *dpacl = NULL;
+ goto out_acl;
+ }
+ }
+
+out_acl:
+ if (error && pacl) {
+ posix_acl_release(*pacl);
+ *pacl = NULL;
+ }
+ nfs4_acl_free(dacl);
+out:
+ return error;
+}
+
+static int
+same_who(struct nfs4_ace *a, struct nfs4_ace *b)
+{
+ return a->whotype == b->whotype &&
+ (a->whotype != NFS4_ACL_WHO_NAMED || a->who == b->who);
+}
+
+static int
+complementary_ace_pair(struct nfs4_ace *allow, struct nfs4_ace *deny,
+ unsigned int flags)
+{
+ int ignore = 0;
+ if (!(flags & NFS4_ACL_DIR))
+ ignore |= NFS4_ACE_DELETE_CHILD;
+ return MASK_EQUAL(ignore|deny_mask(allow->access_mask, flags),
+ ignore|deny->access_mask) &&
+ allow->type == NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE &&
+ deny->type == NFS4_ACE_ACCESS_DENIED_ACE_TYPE &&
+ allow->flag == deny->flag &&
+ same_who(allow, deny);
+}
+
+static inline int
+user_obj_from_v4(struct nfs4_acl *n4acl, struct list_head **p,
+ struct posix_acl *pacl, struct posix_acl_entry **pace,
+ unsigned int flags)
+{
+ int error = -EINVAL;
+ struct nfs4_ace *ace, *ace2;
+
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ if (ace2type(ace) != ACL_USER_OBJ)
+ goto out;
+ error = write_pace(ace, pacl, pace, ACL_USER_OBJ, flags);
+ if (error < 0)
+ goto out;
+ error = -EINVAL;
+ ace2 = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace2 == NULL)
+ goto out;
+ if (!complementary_ace_pair(ace, ace2, flags))
+ goto out;
+ error = 0;
+out:
+ return error;
+}
+
+static inline int
+users_from_v4(struct nfs4_acl *n4acl, struct list_head **p,
+ struct nfs4_ace **mask_ace,
+ struct posix_acl *pacl, struct posix_acl_entry **pace,
+ unsigned int flags)
+{
+ int error = -EINVAL;
+ struct nfs4_ace *ace, *ace2;
+
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ while (ace2type(ace) == ACL_USER) {
+ if (ace->type != NFS4_ACE_ACCESS_DENIED_ACE_TYPE)
+ goto out;
+ if (*mask_ace &&
+ !MASK_EQUAL(ace->access_mask, (*mask_ace)->access_mask))
+ goto out;
+ *mask_ace = ace;
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ if (ace->type != NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE)
+ goto out;
+ error = write_pace(ace, pacl, pace, ACL_USER, flags);
+ if (error < 0)
+ goto out;
+ error = -EINVAL;
+ ace2 = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace2 == NULL)
+ goto out;
+ if (!complementary_ace_pair(ace, ace2, flags))
+ goto out;
+ if ((*mask_ace)->flag != ace2->flag ||
+ !same_who(*mask_ace, ace2))
+ goto out;
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ }
+ error = 0;
+out:
+ return error;
+}
+
+static inline int
+group_obj_and_groups_from_v4(struct nfs4_acl *n4acl, struct list_head **p,
+ struct nfs4_ace **mask_ace,
+ struct posix_acl *pacl, struct posix_acl_entry **pace,
+ unsigned int flags)
+{
+ int error = -EINVAL;
+ struct nfs4_ace *ace, *ace2;
+ struct ace_container *ac;
+ struct list_head group_l;
+
+ INIT_LIST_HEAD(&group_l);
+ ace = list_entry(*p, struct nfs4_ace, l_ace);
+
+ /* group owner (mask and allow aces) */
+
+ if (pacl->a_count != 3) {
+ /* then the group owner should be preceded by mask */
+ if (ace->type != NFS4_ACE_ACCESS_DENIED_ACE_TYPE)
+ goto out;
+ if (*mask_ace &&
+ !MASK_EQUAL(ace->access_mask, (*mask_ace)->access_mask))
+ goto out;
+ *mask_ace = ace;
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+
+ if ((*mask_ace)->flag != ace->flag || !same_who(*mask_ace, ace))
+ goto out;
+ }
+
+ if (ace2type(ace) != ACL_GROUP_OBJ)
+ goto out;
+
+ ac = kmalloc(sizeof(*ac), GFP_KERNEL);
+ error = -ENOMEM;
+ if (ac == NULL)
+ goto out;
+ ac->ace = ace;
+ list_add_tail(&ac->ace_l, &group_l);
+
+ error = -EINVAL;
+ if (ace->type != NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE)
+ goto out;
+
+ error = write_pace(ace, pacl, pace, ACL_GROUP_OBJ, flags);
+ if (error < 0)
+ goto out;
+
+ error = -EINVAL;
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+
+ /* groups (mask and allow aces) */
+
+ while (ace2type(ace) == ACL_GROUP) {
+ if (*mask_ace == NULL)
+ goto out;
+
+ if (ace->type != NFS4_ACE_ACCESS_DENIED_ACE_TYPE ||
+ !MASK_EQUAL(ace->access_mask, (*mask_ace)->access_mask))
+ goto out;
+ *mask_ace = ace;
+
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ ac = kmalloc(sizeof(*ac), GFP_KERNEL);
+ error = -ENOMEM;
+ if (ac == NULL)
+ goto out;
+ error = -EINVAL;
+ if (ace->type != NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE ||
+ !same_who(ace, *mask_ace))
+ goto out;
+
+ ac->ace = ace;
+ list_add_tail(&ac->ace_l, &group_l);
+
+ error = write_pace(ace, pacl, pace, ACL_GROUP, flags);
+ if (error < 0)
+ goto out;
+ error = -EINVAL;
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ }
+
+ /* group owner (deny ace) */
+
+ if (ace2type(ace) != ACL_GROUP_OBJ)
+ goto out;
+ ac = list_entry(group_l.next, struct ace_container, ace_l);
+ ace2 = ac->ace;
+ if (!complementary_ace_pair(ace2, ace, flags))
+ goto out;
+ list_del(group_l.next);
+ kfree(ac);
+
+ /* groups (deny aces) */
+
+ while (!list_empty(&group_l)) {
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ if (ace2type(ace) != ACL_GROUP)
+ goto out;
+ ac = list_entry(group_l.next, struct ace_container, ace_l);
+ ace2 = ac->ace;
+ if (!complementary_ace_pair(ace2, ace, flags))
+ goto out;
+ list_del(group_l.next);
+ kfree(ac);
+ }
+
+ ace = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace == NULL)
+ goto out;
+ if (ace2type(ace) != ACL_OTHER)
+ goto out;
+ error = 0;
+out:
+ while (!list_empty(&group_l)) {
+ ac = list_entry(group_l.next, struct ace_container, ace_l);
+ list_del(group_l.next);
+ kfree(ac);
+ }
+ return error;
+}
+
+static inline int
+mask_from_v4(struct nfs4_acl *n4acl, struct list_head **p,
+ struct nfs4_ace **mask_ace,
+ struct posix_acl *pacl, struct posix_acl_entry **pace,
+ unsigned int flags)
+{
+ int error = -EINVAL;
+ struct nfs4_ace *ace;
+
+ ace = list_entry(*p, struct nfs4_ace, l_ace);
+ if (pacl->a_count != 3) {
+ if (*mask_ace == NULL)
+ goto out;
+ (*mask_ace)->access_mask = deny_mask((*mask_ace)->access_mask, flags);
+ write_pace(*mask_ace, pacl, pace, ACL_MASK, flags);
+ }
+ error = 0;
+out:
+ return error;
+}
+
+static inline int
+other_from_v4(struct nfs4_acl *n4acl, struct list_head **p,
+ struct posix_acl *pacl, struct posix_acl_entry **pace,
+ unsigned int flags)
+{
+ int error = -EINVAL;
+ struct nfs4_ace *ace, *ace2;
+
+ ace = list_entry(*p, struct nfs4_ace, l_ace);
+ if (ace->type != NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE)
+ goto out;
+ error = write_pace(ace, pacl, pace, ACL_OTHER, flags);
+ if (error < 0)
+ goto out;
+ error = -EINVAL;
+ ace2 = get_next_v4_ace(p, &n4acl->ace_head);
+ if (ace2 == NULL)
+ goto out;
+ if (!complementary_ace_pair(ace, ace2, flags))
+ goto out;
+ error = 0;
+out:
+ return error;
+}
+
+static int
+calculate_posix_ace_count(struct nfs4_acl *n4acl)
+{
+ if (n4acl->naces == 6) /* owner, owner group, and other only */
+ return 3;
+ else { /* Otherwise there must be a mask entry. */
+ /* Also, the remaining entries are for named users and
+ * groups, and come in threes (mask, allow, deny): */
+ if (n4acl->naces < 7)
+ return -1;
+ if ((n4acl->naces - 7) % 3)
+ return -1;
+ return 4 + (n4acl->naces - 7)/3;
+ }
+}
+
+
+static struct posix_acl *
+_nfsv4_to_posix_one(struct nfs4_acl *n4acl, unsigned int flags)
+{
+ struct posix_acl *pacl;
+ int error = -EINVAL, nace = 0;
+ struct list_head *p;
+ struct nfs4_ace *mask_ace = NULL;
+ struct posix_acl_entry *pace;
+
+ nace = calculate_posix_ace_count(n4acl);
+ if (nace < 0)
+ goto out_err;
+
+ pacl = posix_acl_alloc(nace, GFP_KERNEL);
+ error = -ENOMEM;
+ if (pacl == NULL)
+ goto out_err;
+
+ pace = &pacl->a_entries[0];
+ p = &n4acl->ace_head;
+
+ error = user_obj_from_v4(n4acl, &p, pacl, &pace, flags);
+ if (error)
+ goto out_acl;
+
+ error = users_from_v4(n4acl, &p, &mask_ace, pacl, &pace, flags);
+ if (error)
+ goto out_acl;
+
+ error = group_obj_and_groups_from_v4(n4acl, &p, &mask_ace, pacl, &pace,
+ flags);
+ if (error)
+ goto out_acl;
+
+ error = mask_from_v4(n4acl, &p, &mask_ace, pacl, &pace, flags);
+ if (error)
+ goto out_acl;
+ error = other_from_v4(n4acl, &p, pacl, &pace, flags);
+ if (error)
+ goto out_acl;
+
+ error = -EINVAL;
+ if (p->next != &n4acl->ace_head)
+ goto out_acl;
+ if (pace != pacl->a_entries + pacl->a_count)
+ goto out_acl;
+
+ sort_pacl(pacl);
+
+ return pacl;
+out_acl:
+ posix_acl_release(pacl);
+out_err:
+ pacl = ERR_PTR(error);
+ return pacl;
+}
+
+int
+nfs4_acl_split(struct nfs4_acl *acl, struct nfs4_acl *dacl)
+{
+ struct list_head *h, *n;
+ struct nfs4_ace *ace;
+ int error = 0;
+
+ list_for_each_safe(h, n, &acl->ace_head) {
+ ace = list_entry(h, struct nfs4_ace, l_ace);
+
+ if ((ace->flag & NFS4_INHERITANCE_FLAGS)
+ != NFS4_INHERITANCE_FLAGS)
+ continue;
+
+ error = nfs4_acl_add_ace(dacl, ace->type, ace->flag,
+ ace->access_mask, ace->whotype, ace->who) == -1;
+ if (error < 0)
+ goto out;
+
+ list_del(h);
+ kfree(ace);
+ acl->naces--;
+ }
+
+out:
+ return error;
+}
+
+static short
+ace2type(struct nfs4_ace *ace)
+{
+ switch (ace->whotype) {
+ case NFS4_ACL_WHO_NAMED:
+ return (ace->flag & NFS4_ACE_IDENTIFIER_GROUP ?
+ ACL_GROUP : ACL_USER);
+ case NFS4_ACL_WHO_OWNER:
+ return ACL_USER_OBJ;
+ case NFS4_ACL_WHO_GROUP:
+ return ACL_GROUP_OBJ;
+ case NFS4_ACL_WHO_EVERYONE:
+ return ACL_OTHER;
+ }
+ BUG();
+ return -1;
+}
+
+EXPORT_SYMBOL(nfs4_acl_posix_to_nfsv4);
+EXPORT_SYMBOL(nfs4_acl_nfsv4_to_posix);
+
+struct nfs4_acl *
+nfs4_acl_new(void)
+{
+ struct nfs4_acl *acl;
+
+ if ((acl = kmalloc(sizeof(*acl), GFP_KERNEL)) == NULL)
+ return NULL;
+
+ acl->naces = 0;
+ INIT_LIST_HEAD(&acl->ace_head);
+
+ return acl;
+}
+
+void
+nfs4_acl_free(struct nfs4_acl *acl)
+{
+ struct list_head *h;
+ struct nfs4_ace *ace;
+
+ if (!acl)
+ return;
+
+ while (!list_empty(&acl->ace_head)) {
+ h = acl->ace_head.next;
+ list_del(h);
+ ace = list_entry(h, struct nfs4_ace, l_ace);
+ kfree(ace);
+ }
+
+ kfree(acl);
+
+ return;
+}
+
+int
+nfs4_acl_add_ace(struct nfs4_acl *acl, u32 type, u32 flag, u32 access_mask,
+ int whotype, uid_t who)
+{
+ struct nfs4_ace *ace;
+
+ if ((ace = kmalloc(sizeof(*ace), GFP_KERNEL)) == NULL)
+ return -1;
+
+ ace->type = type;
+ ace->flag = flag;
+ ace->access_mask = access_mask;
+ ace->whotype = whotype;
+ ace->who = who;
+
+ list_add_tail(&ace->l_ace, &acl->ace_head);
+ acl->naces++;
+
+ return 0;
+}
+
+static struct {
+ char *string;
+ int stringlen;
+ int type;
+} s2t_map[] = {
+ {
+ .string = "OWNER@",
+ .stringlen = sizeof("OWNER@") - 1,
+ .type = NFS4_ACL_WHO_OWNER,
+ },
+ {
+ .string = "GROUP@",
+ .stringlen = sizeof("GROUP@") - 1,
+ .type = NFS4_ACL_WHO_GROUP,
+ },
+ {
+ .string = "EVERYONE@",
+ .stringlen = sizeof("EVERYONE@") - 1,
+ .type = NFS4_ACL_WHO_EVERYONE,
+ },
+};
+
+int
+nfs4_acl_get_whotype(char *p, u32 len)
+{
+ int i;
+
+ for (i=0; i < sizeof(s2t_map) / sizeof(*s2t_map); i++) {
+ if (s2t_map[i].stringlen == len &&
+ 0 == memcmp(s2t_map[i].string, p, len))
+ return s2t_map[i].type;
+ }
+ return NFS4_ACL_WHO_NAMED;
+}
+
+int
+nfs4_acl_write_who(int who, char *p)
+{
+ int i;
+
+ for (i=0; i < sizeof(s2t_map) / sizeof(*s2t_map); i++) {
+ if (s2t_map[i].type == who) {
+ memcpy(p, s2t_map[i].string, s2t_map[i].stringlen);
+ return s2t_map[i].stringlen;
+ }
+ }
+ BUG();
+ return -1;
+}
+
+static inline int
+match_who(struct nfs4_ace *ace, uid_t owner, gid_t group, uid_t who)
+{
+ switch (ace->whotype) {
+ case NFS4_ACL_WHO_NAMED:
+ return who == ace->who;
+ case NFS4_ACL_WHO_OWNER:
+ return who == owner;
+ case NFS4_ACL_WHO_GROUP:
+ return who == group;
+ case NFS4_ACL_WHO_EVERYONE:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+/* 0 = granted, -EACCES = denied; mask is an nfsv4 mask, not mode bits */
+int
+nfs4_acl_permission(struct nfs4_acl *acl, uid_t owner, gid_t group,
+ uid_t who, u32 mask)
+{
+ struct nfs4_ace *ace;
+ u32 allowed = 0;
+
+ list_for_each_entry(ace, &acl->ace_head, l_ace) {
+ if (!match_who(ace, group, owner, who))
+ continue;
+ switch (ace->type) {
+ case NFS4_ACE_ACCESS_ALLOWED_ACE_TYPE:
+ allowed |= ace->access_mask;
+ if ((allowed & mask) == mask)
+ return 0;
+ break;
+ case NFS4_ACE_ACCESS_DENIED_ACE_TYPE:
+ if (ace->access_mask & mask)
+ return -EACCES;
+ break;
+ }
+ }
+ return -EACCES;
+}
+
+EXPORT_SYMBOL(nfs4_acl_new);
+EXPORT_SYMBOL(nfs4_acl_free);
+EXPORT_SYMBOL(nfs4_acl_add_ace);
+EXPORT_SYMBOL(nfs4_acl_get_whotype);
+EXPORT_SYMBOL(nfs4_acl_write_who);
+EXPORT_SYMBOL(nfs4_acl_permission);
--- /dev/null
+/*
+ * bitmap.c - NTFS kernel bitmap handling. Part of the Linux-NTFS project.
+ *
+ * Copyright (c) 2004 Anton Altaparmakov
+ *
+ * This program/include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program/include file is distributed in the hope that it will be
+ * useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program (in the main directory of the Linux-NTFS
+ * distribution in the file COPYING); if not, write to the Free Software
+ * Foundation,Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifdef NTFS_RW
+
+#include <linux/pagemap.h>
+
+#include "bitmap.h"
+#include "debug.h"
+#include "ntfs.h"
+
+/**
+ * __ntfs_bitmap_set_bits_in_run - set a run of bits in a bitmap to a value
+ * @vi: vfs inode describing the bitmap
+ * @start_bit: first bit to set
+ * @count: number of bits to set
+ * @value: value to set the bits to (i.e. 0 or 1)
+ * @is_rollback: if TRUE this is a rollback operation
+ *
+ * Set @count bits starting at bit @start_bit in the bitmap described by the
+ * vfs inode @vi to @value, where @value is either 0 or 1.
+ *
+ * @is_rollback should always be FALSE, it is for internal use to rollback
+ * errors. You probably want to use ntfs_bitmap_set_bits_in_run() instead.
+ *
+ * Return 0 on success and -errno on error.
+ */
+int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit,
+ const s64 count, const u8 value, const BOOL is_rollback)
+{
+ s64 cnt = count;
+ pgoff_t index, end_index;
+ struct address_space *mapping;
+ struct page *page;
+ u8 *kaddr;
+ int pos, len;
+ u8 bit;
+
+ BUG_ON(!vi);
+ ntfs_debug("Entering for i_ino 0x%lx, start_bit 0x%llx, count 0x%llx, "
+ "value %u.%s", vi->i_ino, (unsigned long long)start_bit,
+ (unsigned long long)cnt, (unsigned int)value,
+ is_rollback ? " (rollback)" : "");
+ BUG_ON(start_bit < 0);
+ BUG_ON(cnt < 0);
+ BUG_ON(value > 1);
+ /*
+ * Calculate the indices for the pages containing the first and last
+ * bits, i.e. @start_bit and @start_bit + @cnt - 1, respectively.
+ */
+ index = start_bit >> (3 + PAGE_CACHE_SHIFT);
+ end_index = (start_bit + cnt - 1) >> (3 + PAGE_CACHE_SHIFT);
+
+ /* Get the page containing the first bit (@start_bit). */
+ mapping = vi->i_mapping;
+ page = ntfs_map_page(mapping, index);
+ if (IS_ERR(page)) {
+ if (!is_rollback)
+ ntfs_error(vi->i_sb, "Failed to map first page (error "
+ "%li), aborting.", PTR_ERR(page));
+ return PTR_ERR(page);
+ }
+ kaddr = page_address(page);
+
+ /* Set @pos to the position of the byte containing @start_bit. */
+ pos = (start_bit >> 3) & ~PAGE_CACHE_MASK;
+
+ /* Calculate the position of @start_bit in the first byte. */
+ bit = start_bit & 7;
+
+ /* If the first byte is partial, modify the appropriate bits in it. */
+ if (bit) {
+ u8 *byte = kaddr + pos;
+ while ((bit & 7) && cnt--) {
+ if (value)
+ *byte |= 1 << bit++;
+ else
+ *byte &= ~(1 << bit++);
+ }
+ /* If we are done, unmap the page and return success. */
+ if (!cnt)
+ goto done;
+
+ /* Update @pos to the new position. */
+ pos++;
+ }
+ /*
+ * Depending on @value, modify all remaining whole bytes in the page up
+ * to @cnt.
+ */
+ len = min_t(s64, cnt >> 3, PAGE_CACHE_SIZE - pos);
+ memset(kaddr + pos, value ? 0xff : 0, len);
+ cnt -= len << 3;
+
+ /* Update @len to point to the first not-done byte in the page. */
+ if (cnt < 8)
+ len += pos;
+
+ /* If we are not in the last page, deal with all subsequent pages. */
+ while (index < end_index) {
+ BUG_ON(cnt <= 0);
+
+ /* Update @index and get the next page. */
+ flush_dcache_page(page);
+ set_page_dirty(page);
+ ntfs_unmap_page(page);
+ page = ntfs_map_page(mapping, ++index);
+ if (IS_ERR(page))
+ goto rollback;
+ kaddr = page_address(page);
+ /*
+ * Depending on @value, modify all remaining whole bytes in the
+ * page up to @cnt.
+ */
+ len = min_t(s64, cnt >> 3, PAGE_CACHE_SIZE);
+ memset(kaddr, value ? 0xff : 0, len);
+ cnt -= len << 3;
+ }
+ /*
+ * The currently mapped page is the last one. If the last byte is
+ * partial, modify the appropriate bits in it. Note, @len is the
+ * position of the last byte inside the page.
+ */
+ if (cnt) {
+ u8 *byte;
+
+ BUG_ON(cnt > 7);
+
+ bit = cnt;
+ byte = kaddr + len;
+ while (bit--) {
+ if (value)
+ *byte |= 1 << bit;
+ else
+ *byte &= ~(1 << bit);
+ }
+ }
+done:
+ /* We are done. Unmap the page and return success. */
+ flush_dcache_page(page);
+ set_page_dirty(page);
+ ntfs_unmap_page(page);
+ ntfs_debug("Done.");
+ return 0;
+rollback:
+ /*
+ * Current state:
+ * - no pages are mapped
+ * - @count - @cnt is the number of bits that have been modified
+ */
+ if (is_rollback)
+ return PTR_ERR(page);
+ if (count != cnt)
+ pos = __ntfs_bitmap_set_bits_in_run(vi, start_bit, count - cnt,
+ value ? 0 : 1, TRUE);
+ else
+ pos = 0;
+ if (!pos) {
+ /* Rollback was successful. */
+ ntfs_error(vi->i_sb, "Failed to map subsequent page (error "
+ "%li), aborting.", PTR_ERR(page));
+ } else {
+ /* Rollback failed. */
+ ntfs_error(vi->i_sb, "Failed to map subsequent page (error "
+ "%li) and rollback failed (error %i). "
+ "Aborting and leaving inconsistent metadata. "
+ "Unmount and run chkdsk.", PTR_ERR(page), pos);
+ NVolSetErrors(NTFS_SB(vi->i_sb));
+ }
+ return PTR_ERR(page);
+}
+
+#endif /* NTFS_RW */
--- /dev/null
+/*
+ * bitmap.h - Defines for NTFS kernel bitmap handling. Part of the Linux-NTFS
+ * project.
+ *
+ * Copyright (c) 2004 Anton Altaparmakov
+ *
+ * This program/include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program/include file is distributed in the hope that it will be
+ * useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program (in the main directory of the Linux-NTFS
+ * distribution in the file COPYING); if not, write to the Free Software
+ * Foundation,Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _LINUX_NTFS_BITMAP_H
+#define _LINUX_NTFS_BITMAP_H
+
+#ifdef NTFS_RW
+
+#include <linux/fs.h>
+
+#include "types.h"
+
+extern int __ntfs_bitmap_set_bits_in_run(struct inode *vi, const s64 start_bit,
+ const s64 count, const u8 value, const BOOL is_rollback);
+
+/**
+ * ntfs_bitmap_set_bits_in_run - set a run of bits in a bitmap to a value
+ * @vi: vfs inode describing the bitmap
+ * @start_bit: first bit to set
+ * @count: number of bits to set
+ * @value: value to set the bits to (i.e. 0 or 1)
+ *
+ * Set @count bits starting at bit @start_bit in the bitmap described by the
+ * vfs inode @vi to @value, where @value is either 0 or 1.
+ *
+ * Return 0 on success and -errno on error.
+ */
+static inline int ntfs_bitmap_set_bits_in_run(struct inode *vi,
+ const s64 start_bit, const s64 count, const u8 value)
+{
+ return __ntfs_bitmap_set_bits_in_run(vi, start_bit, count, value,
+ FALSE);
+}
+
+/**
+ * ntfs_bitmap_set_run - set a run of bits in a bitmap
+ * @vi: vfs inode describing the bitmap
+ * @start_bit: first bit to set
+ * @count: number of bits to set
+ *
+ * Set @count bits starting at bit @start_bit in the bitmap described by the
+ * vfs inode @vi.
+ *
+ * Return 0 on success and -errno on error.
+ */
+static inline int ntfs_bitmap_set_run(struct inode *vi, const s64 start_bit,
+ const s64 count)
+{
+ return ntfs_bitmap_set_bits_in_run(vi, start_bit, count, 1);
+}
+
+/**
+ * ntfs_bitmap_clear_run - clear a run of bits in a bitmap
+ * @vi: vfs inode describing the bitmap
+ * @start_bit: first bit to clear
+ * @count: number of bits to clear
+ *
+ * Clear @count bits starting at bit @start_bit in the bitmap described by the
+ * vfs inode @vi.
+ *
+ * Return 0 on success and -errno on error.
+ */
+static inline int ntfs_bitmap_clear_run(struct inode *vi, const s64 start_bit,
+ const s64 count)
+{
+ return ntfs_bitmap_set_bits_in_run(vi, start_bit, count, 0);
+}
+
+/**
+ * ntfs_bitmap_set_bit - set a bit in a bitmap
+ * @vi: vfs inode describing the bitmap
+ * @bit: bit to set
+ *
+ * Set bit @bit in the bitmap described by the vfs inode @vi.
+ *
+ * Return 0 on success and -errno on error.
+ */
+static inline int ntfs_bitmap_set_bit(struct inode *vi, const s64 bit)
+{
+ return ntfs_bitmap_set_run(vi, bit, 1);
+}
+
+/**
+ * ntfs_bitmap_clear_bit - clear a bit in a bitmap
+ * @vi: vfs inode describing the bitmap
+ * @bit: bit to clear
+ *
+ * Clear bit @bit in the bitmap described by the vfs inode @vi.
+ *
+ * Return 0 on success and -errno on error.
+ */
+static inline int ntfs_bitmap_clear_bit(struct inode *vi, const s64 bit)
+{
+ return ntfs_bitmap_clear_run(vi, bit, 1);
+}
+
+#endif /* NTFS_RW */
+
+#endif /* defined _LINUX_NTFS_BITMAP_H */
--- /dev/null
+/*
+ * lcnalloc.c - Cluster (de)allocation code. Part of the Linux-NTFS project.
+ *
+ * Copyright (c) 2004 Anton Altaparmakov
+ *
+ * This program/include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program/include file is distributed in the hope that it will be
+ * useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program (in the main directory of the Linux-NTFS
+ * distribution in the file COPYING); if not, write to the Free Software
+ * Foundation,Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifdef NTFS_RW
+
+#include <linux/pagemap.h>
+
+#include "lcnalloc.h"
+#include "debug.h"
+#include "bitmap.h"
+#include "inode.h"
+#include "volume.h"
+#include "attrib.h"
+#include "malloc.h"
+#include "ntfs.h"
+
+/**
+ * ntfs_cluster_free_from_rl_nolock - free clusters from runlist
+ * @vol: mounted ntfs volume on which to free the clusters
+ * @rl: runlist describing the clusters to free
+ *
+ * Free all the clusters described by the runlist @rl on the volume @vol. In
+ * the case of an error being returned, at least some of the clusters were not
+ * freed.
+ *
+ * Return 0 on success and -errno on error.
+ *
+ * Locking: - The volume lcn bitmap must be locked for writing on entry and is
+ * left locked on return.
+ */
+static int ntfs_cluster_free_from_rl_nolock(ntfs_volume *vol,
+ const runlist_element *rl)
+{
+ struct inode *lcnbmp_vi = vol->lcnbmp_ino;
+ int ret = 0;
+
+ ntfs_debug("Entering.");
+ for (; rl->length; rl++) {
+ int err;
+
+ if (rl->lcn < 0)
+ continue;
+ err = ntfs_bitmap_clear_run(lcnbmp_vi, rl->lcn, rl->length);
+ if (unlikely(err && (!ret || ret == ENOMEM) && ret != err))
+ ret = err;
+ }
+ ntfs_debug("Done.");
+ return ret;
+}
+
+/**
+ * ntfs_cluster_alloc - allocate clusters on an ntfs volume
+ * @vol: mounted ntfs volume on which to allocate the clusters
+ * @start_vcn: vcn to use for the first allocated cluster
+ * @count: number of clusters to allocate
+ * @start_lcn: starting lcn at which to allocate the clusters (or -1 if none)
+ * @zone: zone from which to allocate the clusters
+ *
+ * Allocate @count clusters preferably starting at cluster @start_lcn or at the
+ * current allocator position if @start_lcn is -1, on the mounted ntfs volume
+ * @vol. @zone is either DATA_ZONE for allocation of normal clusters or
+ * MFT_ZONE for allocation of clusters for the master file table, i.e. the
+ * $MFT/$DATA attribute.
+ *
+ * @start_vcn specifies the vcn of the first allocated cluster. This makes
+ * merging the resulting runlist with the old runlist easier.
+ *
+ * You need to check the return value with IS_ERR(). If this is false, the
+ * function was successful and the return value is a runlist describing the
+ * allocated cluster(s). If IS_ERR() is true, the function failed and
+ * PTR_ERR() gives you the error code.
+ *
+ * Notes on the allocation algorithm
+ * =================================
+ *
+ * There are two data zones. First is the area between the end of the mft zone
+ * and the end of the volume, and second is the area between the start of the
+ * volume and the start of the mft zone. On unmodified/standard NTFS 1.x
+ * volumes, the second data zone does not exist due to the mft zone being
+ * expanded to cover the start of the volume in order to reserve space for the
+ * mft bitmap attribute.
+ *
+ * This is not the prettiest function but the complexity stems from the need of
+ * implementing the mft vs data zoned approach and from the fact that we have
+ * access to the lcn bitmap in portions of up to 8192 bytes at a time, so we
+ * need to cope with crossing over boundaries of two buffers. Further, the
+ * fact that the allocator allows for caller supplied hints as to the location
+ * of where allocation should begin and the fact that the allocator keeps track
+ * of where in the data zones the next natural allocation should occur,
+ * contribute to the complexity of the function. But it should all be
+ * worthwhile, because this allocator should: 1) be a full implementation of
+ * the MFT zone approach used by Windows NT, 2) cause reduction in
+ * fragmentation, and 3) be speedy in allocations (the code is not optimized
+ * for speed, but the algorithm is, so further speed improvements are probably
+ * possible).
+ *
+ * FIXME: We should be monitoring cluster allocation and increment the MFT zone
+ * size dynamically but this is something for the future. We will just cause
+ * heavier fragmentation by not doing it and I am not even sure Windows would
+ * grow the MFT zone dynamically, so it might even be correct not to do this.
+ * The overhead in doing dynamic MFT zone expansion would be very large and
+ * unlikely worth the effort. (AIA)
+ *
+ * TODO: I have added in double the required zone position pointer wrap around
+ * logic which can be optimized to having only one of the two logic sets.
+ * However, having the double logic will work fine, but if we have only one of
+ * the sets and we get it wrong somewhere, then we get into trouble, so
+ * removing the duplicate logic requires _very_ careful consideration of _all_
+ * possible code paths. So at least for now, I am leaving the double logic -
+ * better safe than sorry... (AIA)
+ *
+ * Locking: - The volume lcn bitmap must be unlocked on entry and is unlocked
+ * on return.
+ * - This function takes the volume lcn bitmap lock for writing and
+ * modifies the bitmap contents.
+ */
+runlist_element *ntfs_cluster_alloc(ntfs_volume *vol, const VCN start_vcn,
+ const s64 count, const LCN start_lcn,
+ const NTFS_CLUSTER_ALLOCATION_ZONES zone)
+{
+ LCN zone_start, zone_end, bmp_pos, bmp_initial_pos, last_read_pos, lcn;
+ LCN prev_lcn = 0, prev_run_len = 0, mft_zone_size;
+ s64 clusters;
+ struct inode *lcnbmp_vi;
+ runlist_element *rl = NULL;
+ struct address_space *mapping;
+ struct page *page = NULL;
+ u8 *buf, *byte;
+ int err = 0, rlpos, rlsize, buf_size;
+ u8 pass, done_zones, search_zone, need_writeback = 0, bit;
+
+ ntfs_debug("Entering for start_vcn 0x%llx, count 0x%llx, start_lcn "
+ "0x%llx, zone %s_ZONE.", (unsigned long long)start_vcn,
+ (unsigned long long)count,
+ (unsigned long long)start_lcn,
+ zone == MFT_ZONE ? "MFT" : "DATA");
+ BUG_ON(!vol);
+ lcnbmp_vi = vol->lcnbmp_ino;
+ BUG_ON(!lcnbmp_vi);
+ BUG_ON(start_vcn < 0);
+ BUG_ON(count < 0);
+ BUG_ON(start_lcn < -1);
+ BUG_ON(zone < FIRST_ZONE);
+ BUG_ON(zone > LAST_ZONE);
+
+ /* Return empty runlist if @count == 0 */
+ // FIXME: Do we want to just return NULL instead? (AIA)
+ if (!count) {
+ rl = ntfs_malloc_nofs(PAGE_SIZE);
+ if (!rl)
+ return ERR_PTR(-ENOMEM);
+ rl[0].vcn = start_vcn;
+ rl[0].lcn = LCN_RL_NOT_MAPPED;
+ rl[0].length = 0;
+ return rl;
+ }
+ /* Take the lcnbmp lock for writing. */
+ down_write(&vol->lcnbmp_lock);
+ /*
+ * If no specific @start_lcn was requested, use the current data zone
+ * position, otherwise use the requested @start_lcn but make sure it
+ * lies outside the mft zone. Also set done_zones to 0 (no zones done)
+ * and pass depending on whether we are starting inside a zone (1) or
+ * at the beginning of a zone (2). If requesting from the MFT_ZONE,
+ * we either start at the current position within the mft zone or at
+ * the specified position. If the latter is out of bounds then we start
+ * at the beginning of the MFT_ZONE.
+ */
+ done_zones = 0;
+ pass = 1;
+ /*
+ * zone_start and zone_end are the current search range. search_zone
+ * is 1 for mft zone, 2 for data zone 1 (end of mft zone till end of
+ * volume) and 4 for data zone 2 (start of volume till start of mft
+ * zone).
+ */
+ zone_start = start_lcn;
+ if (zone_start < 0) {
+ if (zone == DATA_ZONE)
+ zone_start = vol->data1_zone_pos;
+ else
+ zone_start = vol->mft_zone_pos;
+ if (!zone_start) {
+ /*
+ * Zone starts at beginning of volume which means a
+ * single pass is sufficient.
+ */
+ pass = 2;
+ }
+ } else if (zone == DATA_ZONE && zone_start >= vol->mft_zone_start &&
+ zone_start < vol->mft_zone_end) {
+ zone_start = vol->mft_zone_end;
+ /*
+ * Starting at beginning of data1_zone which means a single
+ * pass in this zone is sufficient.
+ */
+ pass = 2;
+ } else if (zone == MFT_ZONE && (zone_start < vol->mft_zone_start ||
+ zone_start >= vol->mft_zone_end)) {
+ zone_start = vol->mft_lcn;
+ if (!vol->mft_zone_end)
+ zone_start = 0;
+ /*
+ * Starting at beginning of volume which means a single pass
+ * is sufficient.
+ */
+ pass = 2;
+ }
+ if (zone == MFT_ZONE) {
+ zone_end = vol->mft_zone_end;
+ search_zone = 1;
+ } else /* if (zone == DATA_ZONE) */ {
+ /* Skip searching the mft zone. */
+ done_zones |= 1;
+ if (zone_start >= vol->mft_zone_end) {
+ zone_end = vol->nr_clusters;
+ search_zone = 2;
+ } else {
+ zone_end = vol->mft_zone_start;
+ search_zone = 4;
+ }
+ }
+ /*
+ * bmp_pos is the current bit position inside the bitmap. We use
+ * bmp_initial_pos to determine whether or not to do a zone switch.
+ */
+ bmp_pos = bmp_initial_pos = zone_start;
+
+ /* Loop until all clusters are allocated, i.e. clusters == 0. */
+ clusters = count;
+ rlpos = rlsize = 0;
+ mapping = lcnbmp_vi->i_mapping;
+ while (1) {
+ ntfs_debug("Start of outer while loop: done_zones 0x%x, "
+ "search_zone %i, pass %i, zone_start 0x%llx, "
+ "zone_end 0x%llx, bmp_initial_pos 0x%llx, "
+ "bmp_pos 0x%llx, rlpos %i, rlsize %i.",
+ done_zones, search_zone, pass,
+ (unsigned long long)zone_start,
+ (unsigned long long)zone_end,
+ (unsigned long long)bmp_initial_pos,
+ (unsigned long long)bmp_pos, rlpos, rlsize);
+ /* Loop until we run out of free clusters. */
+ last_read_pos = bmp_pos >> 3;
+ ntfs_debug("last_read_pos 0x%llx.",
+ (unsigned long long)last_read_pos);
+ if (last_read_pos > lcnbmp_vi->i_size) {
+ ntfs_debug("End of attribute reached. "
+ "Skipping to zone_pass_done.");
+ goto zone_pass_done;
+ }
+ if (likely(page)) {
+ if (need_writeback) {
+ ntfs_debug("Marking page dirty.");
+ flush_dcache_page(page);
+ set_page_dirty(page);
+ need_writeback = 0;
+ }
+ ntfs_unmap_page(page);
+ }
+ page = ntfs_map_page(mapping, last_read_pos >>
+ PAGE_CACHE_SHIFT);
+ if (IS_ERR(page)) {
+ err = PTR_ERR(page);
+ ntfs_error(vol->sb, "Failed to map page.");
+ goto out;
+ }
+ buf_size = last_read_pos & ~PAGE_CACHE_MASK;
+ buf = page_address(page) + buf_size;
+ buf_size = PAGE_CACHE_SIZE - buf_size;
+ if (unlikely(last_read_pos + buf_size > lcnbmp_vi->i_size))
+ buf_size = lcnbmp_vi->i_size - last_read_pos;
+ buf_size <<= 3;
+ lcn = bmp_pos & 7;
+ bmp_pos &= ~7;
+ ntfs_debug("Before inner while loop: buf_size %i, lcn 0x%llx, "
+ "bmp_pos 0x%llx, need_writeback %i.", buf_size,
+ (unsigned long long)lcn,
+ (unsigned long long)bmp_pos, need_writeback);
+ while (lcn < buf_size && lcn + bmp_pos < zone_end) {
+ byte = buf + (lcn >> 3);
+ ntfs_debug("In inner while loop: buf_size %i, "
+ "lcn 0x%llx, bmp_pos 0x%llx, "
+ "need_writeback %i, byte ofs 0x%x, "
+ "*byte 0x%x.", buf_size,
+ (unsigned long long)lcn,
+ (unsigned long long)bmp_pos,
+ need_writeback,
+ (unsigned int)(lcn >> 3),
+ (unsigned int)*byte);
+ /* Skip full bytes. */
+ if (*byte == 0xff) {
+ lcn = (lcn + 8) & ~7;
+ ntfs_debug("Continuing while loop 1.");
+ continue;
+ }
+ bit = 1 << (lcn & 7);
+ ntfs_debug("bit %i.", bit);
+ /* If the bit is already set, go onto the next one. */
+ if (*byte & bit) {
+ lcn++;
+ ntfs_debug("Continuing while loop 2.");
+ continue;
+ }
+ /*
+ * Allocate more memory if needed, including space for
+ * the terminator element.
+ * ntfs_malloc_nofs() operates on whole pages only.
+ */
+ if ((rlpos + 2) * sizeof(*rl) > rlsize) {
+ runlist_element *rl2;
+
+ ntfs_debug("Reallocating memory.");
+ if (!rl)
+ ntfs_debug("First free bit is at LCN "
+ "0x%llx.",
+ (unsigned long long)
+ (lcn + bmp_pos));
+ rl2 = ntfs_malloc_nofs(rlsize + (int)PAGE_SIZE);
+ if (unlikely(!rl2)) {
+ err = -ENOMEM;
+ ntfs_error(vol->sb, "Failed to "
+ "allocate memory.");
+ goto out;
+ }
+ memcpy(rl2, rl, rlsize);
+ ntfs_free(rl);
+ rl = rl2;
+ rlsize += PAGE_SIZE;
+ ntfs_debug("Reallocated memory, rlsize 0x%x.",
+ rlsize);
+ }
+ /* Allocate the bitmap bit. */
+ *byte |= bit;
+ /* We need to write this bitmap page to disk. */
+ need_writeback = 1;
+ ntfs_debug("*byte 0x%x, need_writeback is set.",
+ (unsigned int)*byte);
+ /*
+ * Coalesce with previous run if adjacent LCNs.
+ * Otherwise, append a new run.
+ */
+ ntfs_debug("Adding run (lcn 0x%llx, len 0x%llx), "
+ "prev_lcn 0x%llx, lcn 0x%llx, "
+ "bmp_pos 0x%llx, prev_run_len 0x%llx, "
+ "rlpos %i.",
+ (unsigned long long)(lcn + bmp_pos),
+ 1ULL, (unsigned long long)prev_lcn,
+ (unsigned long long)lcn,
+ (unsigned long long)bmp_pos,
+ (unsigned long long)prev_run_len,
+ rlpos);
+ if (prev_lcn == lcn + bmp_pos - prev_run_len && rlpos) {
+ ntfs_debug("Coalescing to run (lcn 0x%llx, "
+ "len 0x%llx).",
+ (unsigned long long)
+ rl[rlpos - 1].lcn,
+ (unsigned long long)
+ rl[rlpos - 1].length);
+ rl[rlpos - 1].length = ++prev_run_len;
+ ntfs_debug("Run now (lcn 0x%llx, len 0x%llx), "
+ "prev_run_len 0x%llx.",
+ (unsigned long long)
+ rl[rlpos - 1].lcn,
+ (unsigned long long)
+ rl[rlpos - 1].length,
+ (unsigned long long)
+ prev_run_len);
+ } else {
+ if (likely(rlpos)) {
+ ntfs_debug("Adding new run, (previous "
+ "run lcn 0x%llx, "
+ "len 0x%llx).",
+ (unsigned long long)
+ rl[rlpos - 1].lcn,
+ (unsigned long long)
+ rl[rlpos - 1].length);
+ rl[rlpos].vcn = rl[rlpos - 1].vcn +
+ prev_run_len;
+ } else {
+ ntfs_debug("Adding new run, is first "
+ "run.");
+ rl[rlpos].vcn = start_vcn;
+ }
+ rl[rlpos].lcn = prev_lcn = lcn + bmp_pos;
+ rl[rlpos].length = prev_run_len = 1;
+ rlpos++;
+ }
+ /* Done? */
+ if (!--clusters) {
+ LCN tc;
+ /*
+ * Update the current zone position. Positions
+ * of already scanned zones have been updated
+ * during the respective zone switches.
+ */
+ tc = lcn + bmp_pos + 1;
+ ntfs_debug("Done. Updating current zone "
+ "position, tc 0x%llx, "
+ "search_zone %i.",
+ (unsigned long long)tc,
+ search_zone);
+ switch (search_zone) {
+ case 1:
+ ntfs_debug("Before checks, "
+ "vol->mft_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->mft_zone_pos);
+ if (tc >= vol->mft_zone_end) {
+ vol->mft_zone_pos =
+ vol->mft_lcn;
+ if (!vol->mft_zone_end)
+ vol->mft_zone_pos = 0;
+ } else if ((bmp_initial_pos >=
+ vol->mft_zone_pos ||
+ tc > vol->mft_zone_pos)
+ && tc >= vol->mft_lcn)
+ vol->mft_zone_pos = tc;
+ ntfs_debug("After checks, "
+ "vol->mft_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->mft_zone_pos);
+ break;
+ case 2:
+ ntfs_debug("Before checks, "
+ "vol->data1_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data1_zone_pos);
+ if (tc >= vol->nr_clusters)
+ vol->data1_zone_pos =
+ vol->mft_zone_end;
+ else if ((bmp_initial_pos >=
+ vol->data1_zone_pos ||
+ tc > vol->data1_zone_pos)
+ && tc >= vol->mft_zone_end)
+ vol->data1_zone_pos = tc;
+ ntfs_debug("After checks, "
+ "vol->data1_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data1_zone_pos);
+ break;
+ case 4:
+ ntfs_debug("Before checks, "
+ "vol->data2_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data2_zone_pos);
+ if (tc >= vol->mft_zone_start)
+ vol->data2_zone_pos = 0;
+ else if (bmp_initial_pos >=
+ vol->data2_zone_pos ||
+ tc > vol->data2_zone_pos)
+ vol->data2_zone_pos = tc;
+ ntfs_debug("After checks, "
+ "vol->data2_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data2_zone_pos);
+ break;
+ default:
+ BUG();
+ }
+ ntfs_debug("Finished. Going to out.");
+ goto out;
+ }
+ lcn++;
+ }
+ bmp_pos += buf_size;
+ ntfs_debug("After inner while loop: buf_size 0x%x, lcn "
+ "0x%llx, bmp_pos 0x%llx, need_writeback %i.",
+ buf_size, (unsigned long long)lcn,
+ (unsigned long long)bmp_pos, need_writeback);
+ if (bmp_pos < zone_end) {
+ ntfs_debug("Continuing outer while loop, "
+ "bmp_pos 0x%llx, zone_end 0x%llx.",
+ (unsigned long long)bmp_pos,
+ (unsigned long long)zone_end);
+ continue;
+ }
+zone_pass_done: /* Finished with the current zone pass. */
+ ntfs_debug("At zone_pass_done, pass %i.", pass);
+ if (pass == 1) {
+ /*
+ * Now do pass 2, scanning the first part of the zone
+ * we omitted in pass 1.
+ */
+ pass = 2;
+ zone_end = zone_start;
+ switch (search_zone) {
+ case 1: /* mft_zone */
+ zone_start = vol->mft_zone_start;
+ break;
+ case 2: /* data1_zone */
+ zone_start = vol->mft_zone_end;
+ break;
+ case 4: /* data2_zone */
+ zone_start = 0;
+ break;
+ default:
+ BUG();
+ }
+ /* Sanity check. */
+ if (zone_end < zone_start)
+ zone_end = zone_start;
+ bmp_pos = zone_start;
+ ntfs_debug("Continuing outer while loop, pass 2, "
+ "zone_start 0x%llx, zone_end 0x%llx, "
+ "bmp_pos 0x%llx.",
+ (unsigned long long)zone_start,
+ (unsigned long long)zone_end,
+ (unsigned long long)bmp_pos);
+ continue;
+ } /* pass == 2 */
+done_zones_check:
+ ntfs_debug("At done_zones_check, search_zone %i, done_zones "
+ "before 0x%x, done_zones after 0x%x.",
+ search_zone, done_zones,
+ done_zones | search_zone);
+ done_zones |= search_zone;
+ if (done_zones < 7) {
+ ntfs_debug("Switching zone.");
+ /* Now switch to the next zone we haven't done yet. */
+ pass = 1;
+ switch (search_zone) {
+ case 1:
+ ntfs_debug("Switching from mft zone to data1 "
+ "zone.");
+ /* Update mft zone position. */
+ if (rlpos) {
+ LCN tc;
+
+ ntfs_debug("Before checks, "
+ "vol->mft_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->mft_zone_pos);
+ tc = rl[rlpos - 1].lcn +
+ rl[rlpos - 1].length;
+ if (tc >= vol->mft_zone_end) {
+ vol->mft_zone_pos =
+ vol->mft_lcn;
+ if (!vol->mft_zone_end)
+ vol->mft_zone_pos = 0;
+ } else if ((bmp_initial_pos >=
+ vol->mft_zone_pos ||
+ tc > vol->mft_zone_pos)
+ && tc >= vol->mft_lcn)
+ vol->mft_zone_pos = tc;
+ ntfs_debug("After checks, "
+ "vol->mft_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->mft_zone_pos);
+ }
+ /* Switch from mft zone to data1 zone. */
+switch_to_data1_zone: search_zone = 2;
+ zone_start = bmp_initial_pos =
+ vol->data1_zone_pos;
+ zone_end = vol->nr_clusters;
+ if (zone_start == vol->mft_zone_end)
+ pass = 2;
+ if (zone_start >= zone_end) {
+ vol->data1_zone_pos = zone_start =
+ vol->mft_zone_end;
+ pass = 2;
+ }
+ break;
+ case 2:
+ ntfs_debug("Switching from data1 zone to "
+ "data2 zone.");
+ /* Update data1 zone position. */
+ if (rlpos) {
+ LCN tc;
+
+ ntfs_debug("Before checks, "
+ "vol->data1_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data1_zone_pos);
+ tc = rl[rlpos - 1].lcn +
+ rl[rlpos - 1].length;
+ if (tc >= vol->nr_clusters)
+ vol->data1_zone_pos =
+ vol->mft_zone_end;
+ else if ((bmp_initial_pos >=
+ vol->data1_zone_pos ||
+ tc > vol->data1_zone_pos)
+ && tc >= vol->mft_zone_end)
+ vol->data1_zone_pos = tc;
+ ntfs_debug("After checks, "
+ "vol->data1_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data1_zone_pos);
+ }
+ /* Switch from data1 zone to data2 zone. */
+ search_zone = 4;
+ zone_start = bmp_initial_pos =
+ vol->data2_zone_pos;
+ zone_end = vol->mft_zone_start;
+ if (!zone_start)
+ pass = 2;
+ if (zone_start >= zone_end) {
+ vol->data2_zone_pos = zone_start =
+ bmp_initial_pos = 0;
+ pass = 2;
+ }
+ break;
+ case 4:
+ ntfs_debug("Switching from data2 zone to "
+ "data1 zone.");
+ /* Update data2 zone position. */
+ if (rlpos) {
+ LCN tc;
+
+ ntfs_debug("Before checks, "
+ "vol->data2_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data2_zone_pos);
+ tc = rl[rlpos - 1].lcn +
+ rl[rlpos - 1].length;
+ if (tc >= vol->mft_zone_start)
+ vol->data2_zone_pos = 0;
+ else if (bmp_initial_pos >=
+ vol->data2_zone_pos ||
+ tc > vol->data2_zone_pos)
+ vol->data2_zone_pos = tc;
+ ntfs_debug("After checks, "
+ "vol->data2_zone_pos "
+ "0x%llx.",
+ (unsigned long long)
+ vol->data2_zone_pos);
+ }
+ /* Switch from data2 zone to data1 zone. */
+ goto switch_to_data1_zone;
+ default:
+ BUG();
+ }
+ ntfs_debug("After zone switch, search_zone %i, "
+ "pass %i, bmp_initial_pos 0x%llx, "
+ "zone_start 0x%llx, zone_end 0x%llx.",
+ search_zone, pass,
+ (unsigned long long)bmp_initial_pos,
+ (unsigned long long)zone_start,
+ (unsigned long long)zone_end);
+ bmp_pos = zone_start;
+ if (zone_start == zone_end) {
+ ntfs_debug("Empty zone, going to "
+ "done_zones_check.");
+ /* Empty zone. Don't bother searching it. */
+ goto done_zones_check;
+ }
+ ntfs_debug("Continuing outer while loop.");
+ continue;
+ } /* done_zones == 7 */
+ ntfs_debug("All zones are finished.");
+ /*
+ * All zones are finished! If DATA_ZONE, shrink mft zone. If
+ * MFT_ZONE, we have really run out of space.
+ */
+ mft_zone_size = vol->mft_zone_end - vol->mft_zone_start;
+ ntfs_debug("vol->mft_zone_start 0x%llx, vol->mft_zone_end "
+ "0x%llx, mft_zone_size 0x%llx.",
+ (unsigned long long)vol->mft_zone_start,
+ (unsigned long long)vol->mft_zone_end,
+ (unsigned long long)mft_zone_size);
+ if (zone == MFT_ZONE || mft_zone_size <= 0) {
+ ntfs_debug("No free clusters left, going to out.");
+ /* Really no more space left on device. */
+ err = ENOSPC;
+ goto out;
+ } /* zone == DATA_ZONE && mft_zone_size > 0 */
+ ntfs_debug("Shrinking mft zone.");
+ zone_end = vol->mft_zone_end;
+ mft_zone_size >>= 1;
+ if (mft_zone_size > 0)
+ vol->mft_zone_end = vol->mft_zone_start + mft_zone_size;
+ else /* mft zone and data2 zone no longer exist. */
+ vol->data2_zone_pos = vol->mft_zone_start =
+ vol->mft_zone_end = 0;
+ if (vol->mft_zone_pos >= vol->mft_zone_end) {
+ vol->mft_zone_pos = vol->mft_lcn;
+ if (!vol->mft_zone_end)
+ vol->mft_zone_pos = 0;
+ }
+ bmp_pos = zone_start = bmp_initial_pos =
+ vol->data1_zone_pos = vol->mft_zone_end;
+ search_zone = 2;
+ pass = 2;
+ done_zones &= ~2;
+ ntfs_debug("After shrinking mft zone, mft_zone_size 0x%llx, "
+ "vol->mft_zone_start 0x%llx, "
+ "vol->mft_zone_end 0x%llx, "
+ "vol->mft_zone_pos 0x%llx, search_zone 2, "
+ "pass 2, dones_zones 0x%x, zone_start 0x%llx, "
+ "zone_end 0x%llx, vol->data1_zone_pos 0x%llx, "
+ "continuing outer while loop.",
+ (unsigned long long)mft_zone_size,
+ (unsigned long long)vol->mft_zone_start,
+ (unsigned long long)vol->mft_zone_end,
+ (unsigned long long)vol->mft_zone_pos,
+ done_zones, (unsigned long long)zone_start,
+ (unsigned long long)zone_end,
+ (unsigned long long)vol->data1_zone_pos);
+ }
+ ntfs_debug("After outer while loop.");
+out:
+ ntfs_debug("At out.");
+ /* Add runlist terminator element. */
+ if (likely(rl)) {
+ rl[rlpos].vcn = rl[rlpos - 1].vcn + rl[rlpos - 1].length;
+ rl[rlpos].lcn = LCN_RL_NOT_MAPPED;
+ rl[rlpos].length = 0;
+ }
+ if (likely(page && !IS_ERR(page))) {
+ if (need_writeback) {
+ ntfs_debug("Marking page dirty.");
+ flush_dcache_page(page);
+ set_page_dirty(page);
+ need_writeback = 0;
+ }
+ ntfs_unmap_page(page);
+ }
+ if (likely(!err)) {
+ up_write(&vol->lcnbmp_lock);
+ ntfs_debug("Done.");
+ return rl;
+ }
+ ntfs_error(vol->sb, "Failed to allocate clusters, aborting "
+ "(error %i).", err);
+ if (rl) {
+ int err2;
+
+ if (err == ENOSPC)
+ ntfs_debug("Not enough space to complete allocation, "
+ "err ENOSPC, first free lcn 0x%llx, "
+ "could allocate up to 0x%llx "
+ "clusters.",
+ (unsigned long long)rl[0].lcn,
+ (unsigned long long)count - clusters);
+ /* Deallocate all allocated clusters. */
+ ntfs_debug("Attempting rollback...");
+ err2 = ntfs_cluster_free_from_rl_nolock(vol, rl);
+ if (err2) {
+ ntfs_error(vol->sb, "Failed to rollback (error %i). "
+ "Leaving inconsistent metadata! "
+ "Unmount and run chkdsk.", err2);
+ NVolSetErrors(vol);
+ }
+ /* Free the runlist. */
+ ntfs_free(rl);
+ } else if (err == ENOSPC)
+ ntfs_debug("No space left at all, err = ENOSPC, "
+ "first free lcn = 0x%llx.",
+ (unsigned long long)vol->data1_zone_pos);
+ up_write(&vol->lcnbmp_lock);
+ return ERR_PTR(err);
+}
+
+/**
+ * __ntfs_cluster_free - free clusters on an ntfs volume
+ * @vi: vfs inode whose runlist describes the clusters to free
+ * @start_vcn: vcn in the runlist of @vi at which to start freeing clusters
+ * @count: number of clusters to free or -1 for all clusters
+ * @is_rollback: if TRUE this is a rollback operation
+ *
+ * Free @count clusters starting at the cluster @start_vcn in the runlist
+ * described by the vfs inode @vi.
+ *
+ * If @count is -1, all clusters from @start_vcn to the end of the runlist are
+ * deallocated. Thus, to completely free all clusters in a runlist, use
+ * @start_vcn = 0 and @count = -1.
+ *
+ * @is_rollback should always be FALSE, it is for internal use to rollback
+ * errors. You probably want to use ntfs_cluster_free() instead.
+ *
+ * Note, ntfs_cluster_free() does not modify the runlist at all, so the caller
+ * has to deal with it later.
+ *
+ * Return the number of deallocated clusters (not counting sparse ones) on
+ * success and -errno on error.
+ *
+ * Locking: - The runlist described by @vi must be unlocked on entry and is
+ * unlocked on return.
+ * - This function takes the runlist lock of @vi for reading and
+ * sometimes for writing and sometimes modifies the runlist.
+ * - The volume lcn bitmap must be unlocked on entry and is unlocked
+ * on return.
+ * - This function takes the volume lcn bitmap lock for writing and
+ * modifies the bitmap contents.
+ */
+s64 __ntfs_cluster_free(struct inode *vi, const VCN start_vcn, s64 count,
+ const BOOL is_rollback)
+{
+ s64 delta, to_free, total_freed, real_freed;
+ ntfs_inode *ni;
+ ntfs_volume *vol;
+ struct inode *lcnbmp_vi;
+ runlist_element *rl;
+ int err;
+
+ BUG_ON(!vi);
+ ntfs_debug("Entering for i_ino 0x%lx, start_vcn 0x%llx, count "
+ "0x%llx.%s", vi->i_ino, (unsigned long long)start_vcn,
+ (unsigned long long)count,
+ is_rollback ? " (rollback)" : "");
+ ni = NTFS_I(vi);
+ vol = ni->vol;
+ lcnbmp_vi = vol->lcnbmp_ino;
+ BUG_ON(!lcnbmp_vi);
+ BUG_ON(start_vcn < 0);
+ BUG_ON(count < -1);
+ /*
+ * Lock the lcn bitmap for writing but only if not rolling back. We
+ * must hold the lock all the way including through rollback otherwise
+ * rollback is not possible because once we have cleared a bit and
+ * dropped the lock, anyone could have set the bit again, thus
+ * allocating the cluster for another use.
+ */
+ if (likely(!is_rollback))
+ down_write(&vol->lcnbmp_lock);
+
+ total_freed = real_freed = 0;
+
+ /* This returns with ni->runlist locked for reading on success. */
+ rl = ntfs_find_vcn(ni, start_vcn, FALSE);
+ if (IS_ERR(rl)) {
+ if (!is_rollback)
+ ntfs_error(vol->sb, "Failed to find first runlist "
+ "element (error %li), aborting.",
+ PTR_ERR(rl));
+ err = PTR_ERR(rl);
+ goto err_out;
+ }
+ if (unlikely(rl->lcn < (LCN)LCN_HOLE)) {
+ if (!is_rollback)
+ ntfs_error(vol->sb, "First runlist element has "
+ "invalid lcn, aborting.");
+ err = -EIO;
+ goto unl_err_out;
+ }
+ /* Find the starting cluster inside the run that needs freeing. */
+ delta = start_vcn - rl->vcn;
+
+ /* The number of clusters in this run that need freeing. */
+ to_free = rl->length - delta;
+ if (count >= 0 && to_free > count)
+ to_free = count;
+
+ if (likely(rl->lcn >= 0)) {
+ /* Do the actual freeing of the clusters in this run. */
+ err = ntfs_bitmap_set_bits_in_run(lcnbmp_vi, rl->lcn + delta,
+ to_free, likely(!is_rollback) ? 0 : 1);
+ if (unlikely(err)) {
+ if (!is_rollback)
+ ntfs_error(vol->sb, "Failed to clear first run "
+ "(error %i), aborting.", err);
+ goto unl_err_out;
+ }
+ /* We have freed @to_free real clusters. */
+ real_freed = to_free;
+ };
+ /* Go to the next run and adjust the number of clusters left to free. */
+ ++rl;
+ if (count >= 0)
+ count -= to_free;
+
+ /* Keep track of the total "freed" clusters, including sparse ones. */
+ total_freed = to_free;
+ /*
+ * Loop over the remaining runs, using @count as a capping value, and
+ * free them.
+ */
+ for (; rl->length && count != 0; ++rl) {
+ if (unlikely(rl->lcn < (LCN)LCN_HOLE)) {
+ VCN vcn;
+
+ /*
+ * Attempt to map runlist, dropping runlist lock for
+ * the duration.
+ */
+ up_read(&ni->runlist.lock);
+ vcn = rl->vcn;
+ err = ntfs_map_runlist(ni, vcn);
+ if (err) {
+ if (!is_rollback)
+ ntfs_error(vol->sb, "Failed to map "
+ "runlist fragment.");
+ if (err == -EINVAL || err == -ENOENT)
+ err = -EIO;
+ goto err_out;
+ }
+ /*
+ * This returns with ni->runlist locked for reading on
+ * success.
+ */
+ rl = ntfs_find_vcn(ni, vcn, FALSE);
+ if (IS_ERR(rl)) {
+ err = PTR_ERR(rl);
+ if (!is_rollback)
+ ntfs_error(vol->sb, "Failed to find "
+ "subsequent runlist "
+ "element.");
+ goto err_out;
+ }
+ if (unlikely(rl->lcn < (LCN)LCN_HOLE)) {
+ if (!is_rollback)
+ ntfs_error(vol->sb, "Runlist element "
+ "has invalid lcn "
+ "(0x%llx).",
+ (unsigned long long)
+ rl->lcn);
+ err = -EIO;
+ goto unl_err_out;
+ }
+ }
+ /* The number of clusters in this run that need freeing. */
+ to_free = rl->length;
+ if (count >= 0 && to_free > count)
+ to_free = count;
+
+ if (likely(rl->lcn >= 0)) {
+ /* Do the actual freeing of the clusters in the run. */
+ err = ntfs_bitmap_set_bits_in_run(lcnbmp_vi, rl->lcn,
+ to_free, likely(!is_rollback) ? 0 : 1);
+ if (unlikely(err)) {
+ if (!is_rollback)
+ ntfs_error(vol->sb, "Failed to clear "
+ "subsequent run.");
+ goto unl_err_out;
+ }
+ /* We have freed @to_free real clusters. */
+ real_freed += to_free;
+ }
+ /* Adjust the number of clusters left to free. */
+ if (count >= 0)
+ count -= to_free;
+
+ /* Update the total done clusters. */
+ total_freed += to_free;
+ }
+ up_read(&ni->runlist.lock);
+ if (likely(!is_rollback))
+ up_write(&vol->lcnbmp_lock);
+
+ BUG_ON(count > 0);
+
+ /* We are done. Return the number of actually freed clusters. */
+ ntfs_debug("Done.");
+ return real_freed;
+unl_err_out:
+ up_read(&ni->runlist.lock);
+err_out:
+ if (is_rollback)
+ return err;
+ /* If no real clusters were freed, no need to rollback. */
+ if (!real_freed) {
+ up_write(&vol->lcnbmp_lock);
+ return err;
+ }
+ /*
+ * Attempt to rollback and if that succeeds just return the error code.
+ * If rollback fails, set the volume errors flag, emit an error
+ * message, and return the error code.
+ */
+ delta = __ntfs_cluster_free(vi, start_vcn, total_freed, TRUE);
+ if (delta < 0) {
+ ntfs_error(vol->sb, "Failed to rollback (error %i). Leaving "
+ "inconsistent metadata! Unmount and run "
+ "chkdsk.", (int)delta);
+ NVolSetErrors(vol);
+ }
+ up_write(&vol->lcnbmp_lock);
+ ntfs_error(vol->sb, "Aborting (error %i).", err);
+ return err;
+}
+
+#endif /* NTFS_RW */
--- /dev/null
+/*
+ * lcnalloc.h - Exports for NTFS kernel cluster (de)allocation. Part of the
+ * Linux-NTFS project.
+ *
+ * Copyright (c) 2004 Anton Altaparmakov
+ *
+ * This program/include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program/include file is distributed in the hope that it will be
+ * useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program (in the main directory of the Linux-NTFS
+ * distribution in the file COPYING); if not, write to the Free Software
+ * Foundation,Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _LINUX_NTFS_LCNALLOC_H
+#define _LINUX_NTFS_LCNALLOC_H
+
+#ifdef NTFS_RW
+
+#include <linux/fs.h>
+
+#include "types.h"
+#include "volume.h"
+
+typedef enum {
+ FIRST_ZONE = 0, /* For sanity checking. */
+ MFT_ZONE = 0, /* Allocate from $MFT zone. */
+ DATA_ZONE = 1, /* Allocate from $DATA zone. */
+ LAST_ZONE = 1, /* For sanity checking. */
+} NTFS_CLUSTER_ALLOCATION_ZONES;
+
+extern runlist_element *ntfs_cluster_alloc(ntfs_volume *vol,
+ const VCN start_vcn, const s64 count, const LCN start_lcn,
+ const NTFS_CLUSTER_ALLOCATION_ZONES zone);
+
+extern s64 __ntfs_cluster_free(struct inode *vi, const VCN start_vcn,
+ s64 count, const BOOL is_rollback);
+
+/**
+ * ntfs_cluster_free - free clusters on an ntfs volume
+ * @vi: vfs inode whose runlist describes the clusters to free
+ * @start_vcn: vcn in the runlist of @vi at which to start freeing clusters
+ * @count: number of clusters to free or -1 for all clusters
+ *
+ * Free @count clusters starting at the cluster @start_vcn in the runlist
+ * described by the vfs inode @vi.
+ *
+ * If @count is -1, all clusters from @start_vcn to the end of the runlist are
+ * deallocated. Thus, to completely free all clusters in a runlist, use
+ * @start_vcn = 0 and @count = -1.
+ *
+ * Note, ntfs_cluster_free() does not modify the runlist at all, so the caller
+ * has to deal with it later.
+ *
+ * Return the number of deallocated clusters (not counting sparse ones) on
+ * success and -errno on error.
+ *
+ * Locking: - The runlist described by @vi must be unlocked on entry and is
+ * unlocked on return.
+ * - This function takes the runlist lock of @vi for reading and
+ * sometimes for writing and sometimes modifies the runlist.
+ * - The volume lcn bitmap must be unlocked on entry and is unlocked
+ * on return.
+ * - This function takes the volume lcn bitmap lock for writing and
+ * modifies the bitmap contents.
+ */
+static inline s64 ntfs_cluster_free(struct inode *vi, const VCN start_vcn,
+ s64 count)
+{
+ return __ntfs_cluster_free(vi, start_vcn, count, FALSE);
+}
+
+#endif /* NTFS_RW */
+
+#endif /* defined _LINUX_NTFS_LCNALLOC_H */
--- /dev/null
+/*
+ * Copyright (c) 2004 Silicon Graphics, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like. Any license provided herein, whether implied or
+ * otherwise, applies only to this software file. Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
+ * Mountain View, CA 94043, or:
+ *
+ * http://www.sgi.com
+ *
+ * For further information regarding this notice, see:
+ *
+ * http://oss.sgi.com/projects/GenInfo/SGIGPLNoticeExplan/
+ */
+
+#include <linux/config.h>
+#include <linux/compat.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <linux/ioctl32.h>
+#include <linux/syscalls.h>
+#include <linux/types.h>
+#include <asm/uaccess.h>
+
+#include "xfs_types.h"
+#include "xfs_fs.h"
+#include "xfs_dfrag.h"
+
+#if defined(CONFIG_IA64) || defined(CONFIG_X86_64)
+#define BROKEN_X86_ALIGNMENT
+#else
+
+typedef struct xfs_fsop_bulkreq32 {
+ compat_uptr_t lastip; /* last inode # pointer */
+ __s32 icount; /* count of entries in buffer */
+ compat_uptr_t ubuffer; /* user buffer for inode desc. */
+ __s32 ocount; /* output count pointer */
+} xfs_fsop_bulkreq32_t;
+
+static int
+xfs_ioctl32_bulkstat(
+ unsigned int fd,
+ unsigned int cmd,
+ unsigned long arg,
+ struct file * file)
+{
+ xfs_fsop_bulkreq32_t __user *p32 = (void __user *)arg;
+ xfs_fsop_bulkreq_t __user *p = compat_alloc_user_space(sizeof(*p));
+ u32 addr;
+
+ if (get_user(addr, &p32->lastip) ||
+ put_user(compat_ptr(addr), &p->lastip) ||
+ copy_in_user(&p->icount, &p32->icount, sizeof(s32)) ||
+ get_user(addr, &p32->ubuffer) ||
+ put_user(compat_ptr(addr), &p->ubuffer) ||
+ get_user(addr, &p32->ocount) ||
+ put_user(compat_ptr(addr), &p->ocount))
+ return -EFAULT;
+
+ return sys_ioctl(fd, cmd, (unsigned long)p);
+}
+#endif
+
+struct ioctl_trans xfs_ioctl32_trans[] = {
+ { XFS_IOC_DIOINFO, },
+ { XFS_IOC_FSGEOMETRY_V1, },
+ { XFS_IOC_FSGEOMETRY, },
+ { XFS_IOC_GETVERSION, },
+ { XFS_IOC_GETXFLAGS, },
+ { XFS_IOC_SETXFLAGS, },
+ { XFS_IOC_FSGETXATTR, },
+ { XFS_IOC_FSSETXATTR, },
+ { XFS_IOC_FSGETXATTRA, },
+ { XFS_IOC_FSSETDM, },
+ { XFS_IOC_GETBMAP, },
+ { XFS_IOC_GETBMAPA, },
+ { XFS_IOC_GETBMAPX, },
+/* not handled
+ { XFS_IOC_FD_TO_HANDLE, },
+ { XFS_IOC_PATH_TO_HANDLE, },
+ { XFS_IOC_PATH_TO_HANDLE, },
+ { XFS_IOC_PATH_TO_FSHANDLE, },
+ { XFS_IOC_OPEN_BY_HANDLE, },
+ { XFS_IOC_FSSETDM_BY_HANDLE, },
+ { XFS_IOC_READLINK_BY_HANDLE, },
+ { XFS_IOC_ATTRLIST_BY_HANDLE, },
+ { XFS_IOC_ATTRMULTI_BY_HANDLE, },
+*/
+ { XFS_IOC_FSCOUNTS, NULL, },
+ { XFS_IOC_SET_RESBLKS, NULL, },
+ { XFS_IOC_GET_RESBLKS, NULL, },
+ { XFS_IOC_FSGROWFSDATA, NULL, },
+ { XFS_IOC_FSGROWFSLOG, NULL, },
+ { XFS_IOC_FSGROWFSRT, NULL, },
+ { XFS_IOC_FREEZE, NULL, },
+ { XFS_IOC_THAW, NULL, },
+ { XFS_IOC_GOINGDOWN, NULL, },
+ { XFS_IOC_ERROR_INJECTION, NULL, },
+ { XFS_IOC_ERROR_CLEARALL, NULL, },
+#ifndef BROKEN_X86_ALIGNMENT
+ /* xfs_flock_t and xfs_bstat_t have wrong u32 vs u64 alignment */
+ { XFS_IOC_ALLOCSP, },
+ { XFS_IOC_FREESP, },
+ { XFS_IOC_RESVSP, },
+ { XFS_IOC_UNRESVSP, },
+ { XFS_IOC_ALLOCSP64, },
+ { XFS_IOC_FREESP64, },
+ { XFS_IOC_RESVSP64, },
+ { XFS_IOC_UNRESVSP64, },
+ { XFS_IOC_SWAPEXT, },
+ { XFS_IOC_FSBULKSTAT_SINGLE, xfs_ioctl32_bulkstat },
+ { XFS_IOC_FSBULKSTAT, xfs_ioctl32_bulkstat},
+ { XFS_IOC_FSINUMBERS, xfs_ioctl32_bulkstat},
+#endif
+ { 0, },
+};
+
+int __init
+xfs_ioctl32_init(void)
+{
+ int error, i;
+
+ for (i = 0; xfs_ioctl32_trans[i].cmd != 0; i++) {
+ error = register_ioctl32_conversion(xfs_ioctl32_trans[i].cmd,
+ xfs_ioctl32_trans[i].handler);
+ if (error)
+ goto fail;
+ }
+
+ return 0;
+
+ fail:
+ while (--i)
+ unregister_ioctl32_conversion(xfs_ioctl32_trans[i].cmd);
+ return error;
+}
+
+void
+xfs_ioctl32_exit(void)
+{
+ int i;
+
+ for (i = 0; xfs_ioctl32_trans[i].cmd != 0; i++)
+ unregister_ioctl32_conversion(xfs_ioctl32_trans[i].cmd);
+}
--- /dev/null
+/*
+ * Copyright (c) 2004 Silicon Graphics, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like. Any license provided herein, whether implied or
+ * otherwise, applies only to this software file. Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
+ * Mountain View, CA 94043, or:
+ *
+ * http://www.sgi.com
+ *
+ * For further information regarding this notice, see:
+ *
+ * http://oss.sgi.com/projects/GenInfo/SGIGPLNoticeExplan/
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_COMPAT
+extern int xfs_ioctl32_init(void);
+extern void xfs_ioctl32_exit(void);
+#else
+static inline int xfs_ioctl32_init(void) { return 0; }
+static inline void xfs_ioctl32_exit(void) { }
+#endif
--- /dev/null
+/* Trivial implementations of basic i/o routines. Assumes that all
+ of the hard work has been done by ioremap and ioportmap, and that
+ access to i/o space is linear. */
+
+/* This file may be included multiple times. */
+
+#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
+__EXTERN_INLINE unsigned int
+IO_CONCAT(__IO_PREFIX,ioread8)(void __iomem *a)
+{
+ return __kernel_ldbu(*(volatile u8 __force *)a);
+}
+
+__EXTERN_INLINE unsigned int
+IO_CONCAT(__IO_PREFIX,ioread16)(void __iomem *a)
+{
+ return __kernel_ldwu(*(volatile u16 __force *)a);
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,iowrite8)(u8 b, void __iomem *a)
+{
+ __kernel_stb(b, *(volatile u8 __force *)a);
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,iowrite16)(u16 b, void __iomem *a)
+{
+ __kernel_stb(b, *(volatile u16 __force *)a);
+}
+#endif
+
+#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
+__EXTERN_INLINE unsigned int
+IO_CONCAT(__IO_PREFIX,ioread32)(void __iomem *a)
+{
+ return *(volatile u32 __force *)a;
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,iowrite32)(u32 b, void __iomem *a)
+{
+ *(volatile u32 __force *)a = b;
+}
+#endif
+
+#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
+__EXTERN_INLINE u8
+IO_CONCAT(__IO_PREFIX,readb)(const volatile void __iomem *a)
+{
+ return __kernel_ldbu(*(const volatile u8 __force *)a);
+}
+
+__EXTERN_INLINE u16
+IO_CONCAT(__IO_PREFIX,readw)(const volatile void __iomem *a)
+{
+ return __kernel_ldwu(*(const volatile u16 __force *)a);
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,writeb)(u8 b, volatile void __iomem *a)
+{
+ __kernel_stb(b, *(volatile u8 __force *)a);
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a)
+{
+ __kernel_stb(b, *(volatile u16 __force *)a);
+}
+#elif IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 2
+__EXTERN_INLINE u8
+IO_CONCAT(__IO_PREFIX,readb)(const volatile void __iomem *a)
+{
+ return IO_CONCAT(__IO_PREFIX,ioread8)((void __iomem *)a);
+}
+
+__EXTERN_INLINE u16
+IO_CONCAT(__IO_PREFIX,readw)(const volatile void __iomem *a)
+{
+ return IO_CONCAT(__IO_PREFIX,ioread16)((void __iomem *)a);
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,writeb)(u8 b, volatile void __iomem *a)
+{
+ IO_CONCAT(__IO_PREFIX,iowrite8)(b, (void __iomem *)a);
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a)
+{
+ IO_CONCAT(__IO_PREFIX,iowrite16)(b, (void __iomem *)a);
+}
+#endif
+
+#if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1
+__EXTERN_INLINE u32
+IO_CONCAT(__IO_PREFIX,readl)(const volatile void __iomem *a)
+{
+ return *(const volatile u32 __force *)a;
+}
+
+__EXTERN_INLINE u64
+IO_CONCAT(__IO_PREFIX,readq)(const volatile void __iomem *a)
+{
+ return *(const volatile u64 __force *)a;
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,writel)(u32 b, volatile void __iomem *a)
+{
+ *(volatile u32 __force *)a = b;
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,writeq)(u64 b, volatile void __iomem *a)
+{
+ *(volatile u64 __force *)a = b;
+}
+#endif
+
+#if IO_CONCAT(__IO_PREFIX,trivial_iounmap)
+__EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,iounmap)(volatile void __iomem *a)
+{
+}
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/boards.h
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This file contains the board specific defines for various devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
+#error Do not include this file directly. Include asm/hardware.h instead !
+#endif
+
+/* Hynix H7202 developer board specific device defines */
+#ifdef CONFIG_ARCH_H7202
+
+/* FLASH */
+#define FLASH_VIRT 0xd0000000
+#define FLASH_PHYS 0x00000000
+#define FLASH_SIZE 0x02000000
+
+/* onboard LAN controller */
+# define ETH0_PHYS 0x08000000
+
+/* Touch screen defines */
+/* GPIO Port */
+#define PEN_GPIO GPIO_B_VIRT
+/* Bitmask for pen down interrupt */
+#define PEN_INT_BIT (1<<7)
+/* Bitmask for pen up interrupt */
+#define PEN_ENA_BIT (1<<6)
+/* pen up interrupt */
+#define IRQ_PEN IRQ_MUX_GPIOB(7)
+
+#endif
+
+/* Hynix H7201 developer board specific device defines */
+#if defined (CONFIG_ARCH_H7201)
+/* ROM DISK SPACE */
+#define ROM_DISK_BASE 0xc1800000
+#define ROM_DISK_START 0x41800000
+#define ROM_DISK_SIZE 0x00700000
+
+/* SRAM DISK SPACE */
+#define SRAM_DISK_BASE 0xf1000000
+#define SRAM_DISK_START 0x04000000
+#define SRAM_DISK_SIZE 0x00400000
+#endif
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/dma.h
+ *
+ * Architecture DMA routes
+ *
+ * Copyright (C) 1997.1998 Russell King
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS 0xd0000000
+
+#if defined (CONFIG_CPU_H7201)
+#define MAX_DMA_CHANNELS 3
+#elif defined (CONFIG_CPU_H7202)
+#define MAX_DMA_CHANNELS 4
+#else
+#error processor definition missmatch
+#endif
+
+#endif /* __ASM_ARCH_DMA_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/h7201-regs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#define SERIAL2_VIRT (IO_VIRT + 0x50100)
+#define SERIAL3_VIRT (IO_VIRT + 0x50200)
+
+/*
+ * PCMCIA
+ */
+#define PCMCIA0_ATT_BASE 0xe5000000
+#define PCMCIA0_ATT_SIZE 0x00200000
+#define PCMCIA0_ATT_START 0x20000000
+#define PCMCIA0_MEM_BASE 0xe5200000
+#define PCMCIA0_MEM_SIZE 0x00200000
+#define PCMCIA0_MEM_START 0x24000000
+#define PCMCIA0_IO_BASE 0xe5400000
+#define PCMCIA0_IO_SIZE 0x00200000
+#define PCMCIA0_IO_START 0x28000000
+
+#define PCMCIA1_ATT_BASE 0xe5600000
+#define PCMCIA1_ATT_SIZE 0x00200000
+#define PCMCIA1_ATT_START 0x30000000
+#define PCMCIA1_MEM_BASE 0xe5800000
+#define PCMCIA1_MEM_SIZE 0x00200000
+#define PCMCIA1_MEM_START 0x34000000
+#define PCMCIA1_IO_BASE 0xe5a00000
+#define PCMCIA1_IO_SIZE 0x00200000
+#define PCMCIA1_IO_START 0x38000000
+
+#define PRIME3C_BASE 0xf0050000
+#define PRIME3C_SIZE 0x00001000
+#define PRIME3C_START 0x10000000
+
+/* VGA Controller */
+#define VGA_RAMBASE 0x50
+#define VGA_TIMING0 0x60
+#define VGA_TIMING1 0x64
+#define VGA_TIMING2 0x68
+#define VGA_TIMING3 0x6c
+
+#define LCD_CTRL_VGA_ENABLE 0x00000100
+#define LCD_CTRL_VGA_BPP_MASK 0x00000600
+#define LCD_CTRL_VGA_4BPP 0x00000000
+#define LCD_CTRL_VGA_8BPP 0x00000200
+#define LCD_CTRL_VGA_16BPP 0x00000300
+#define LCD_CTRL_SHARE_DMA 0x00000800
+#define LCD_CTRL_VDE 0x00100000
+#define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */
+#define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */
+
+#define VGA_PALETTE_BASE (IO_VIRT + 0x10800)
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/h7202-regs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#define SERIAL2_VIRT (IO_VIRT + 0x2d000)
+#define SERIAL3_VIRT (IO_VIRT + 0x2e000)
+
+/* Matrix Keyboard Controller */
+#define KBD_VIRT (IO_VIRT + 0x22000)
+#define KBD_KBCR 0x00
+#define KBD_KBSC 0x04
+#define KBD_KBTR 0x08
+#define KBD_KBVR0 0x0C
+#define KBD_KBVR1 0x10
+#define KBD_KBSR 0x18
+
+#define KBD_KBCR_SCANENABLE (1 << 7)
+#define KBD_KBCR_NPOWERDOWN (1 << 2)
+#define KBD_KBCR_CLKSEL_MASK (3)
+#define KBD_KBCR_CLKSEL_PCLK2 0x0
+#define KBD_KBCR_CLKSEL_PCLK128 0x1
+#define KBD_KBCR_CLKSEL_PCLK256 0x2
+#define KBD_KBCR_CLKSEL_PCLK512 0x3
+
+#define KBD_KBSR_INTR (1 << 0)
+#define KBD_KBSR_WAKEUP (1 << 1)
+
+/* USB device controller */
+
+#define USBD_BASE (IO_VIRT + 0x12000)
+#define USBD_LENGTH 0x3C
+
+#define USBD_GCTRL 0x00
+#define USBD_EPCTRL 0x04
+#define USBD_INTMASK 0x08
+#define USBD_INTSTAT 0x0C
+#define USBD_PWR 0x10
+#define USBD_DMARXTX 0x14
+#define USBD_DEVID 0x18
+#define USBD_DEVCLASS 0x1C
+#define USBD_INTCLASS 0x20
+#define USBD_SETUP0 0x24
+#define USBD_SETUP1 0x28
+#define USBD_ENDP0RD 0x2C
+#define USBD_ENDP0WT 0x30
+#define USBD_ENDP1RD 0x34
+#define USBD_ENDP2WT 0x38
+
+/* PS/2 port */
+#define PSDATA 0x00
+#define PSSTAT 0x04
+#define PSSTAT_TXEMPTY (1<<0)
+#define PSSTAT_TXBUSY (1<<1)
+#define PSSTAT_RXFULL (1<<2)
+#define PSSTAT_RXBUSY (1<<3)
+#define PSSTAT_CLKIN (1<<4)
+#define PSSTAT_DATAIN (1<<5)
+#define PSSTAT_PARITY (1<<6)
+
+#define PSCONF 0x08
+#define PSCONF_ENABLE (1<<0)
+#define PSCONF_TXINTEN (1<<2)
+#define PSCONF_RXINTEN (1<<3)
+#define PSCONF_FORCECLKLOW (1<<4)
+#define PSCONF_FORCEDATLOW (1<<5)
+#define PSCONF_LCE (1<<6)
+
+#define PSINTR 0x0C
+#define PSINTR_TXINT (1<<0)
+#define PSINTR_RXINT (1<<1)
+#define PSINTR_PAR (1<<2)
+#define PSINTR_RXTO (1<<3)
+#define PSINTR_TXTO (1<<4)
+
+#define PSTDLO 0x10 /* clk low before start transmission */
+#define PSTPRI 0x14 /* PRI clock */
+#define PSTXMT 0x18 /* maximum transmission time */
+#define PSTREC 0x20 /* maximum receive time */
+#define PSPWDN 0x3c
+
+/* ADC converter */
+#define ADC_BASE (IO_VIRT + 0x29000)
+#define ADC_CR 0x00
+#define ADC_TSCTRL 0x04
+#define ADC_BT_CTRL 0x08
+#define ADC_MC_CTRL 0x0C
+#define ADC_STATUS 0x10
+
+/* ADC control register bits */
+#define ADC_CR_PW_CTRL 0x80
+#define ADC_CR_DIRECTC 0x04
+#define ADC_CR_CONTIME_NO 0x00
+#define ADC_CR_CONTIME_2 0x04
+#define ADC_CR_CONTIME_4 0x08
+#define ADC_CR_CONTIME_ADE 0x0c
+#define ADC_CR_LONGCALTIME 0x01
+
+/* ADC touch panel register bits */
+#define ADC_TSCTRL_ENABLE 0x80
+#define ADC_TSCTRL_INTR 0x40
+#define ADC_TSCTRL_SWBYPSS 0x20
+#define ADC_TSCTRL_SWINVT 0x10
+#define ADC_TSCTRL_S400 0x03
+#define ADC_TSCTRL_S200 0x02
+#define ADC_TSCTRL_S100 0x01
+#define ADC_TSCTRL_S50 0x00
+
+/* ADC Interrupt Status Register bits */
+#define ADC_STATUS_TS_BIT 0x80
+#define ADC_STATUS_MBT_BIT 0x40
+#define ADC_STATUS_BBT_BIT 0x20
+#define ADC_STATUS_MIC_BIT 0x10
+
+/* Touch data registers */
+#define ADC_TS_X0X1 0x30
+#define ADC_TS_X2X3 0x34
+#define ADC_TS_Y0Y1 0x38
+#define ADC_TS_Y2Y3 0x3c
+#define ADC_TS_X4X5 0x40
+#define ADC_TS_X6X7 0x44
+#define ADC_TS_Y4Y5 0x48
+#define ADC_TS_Y6Y7 0x50
+
+/* battery data */
+#define ADC_MB_DATA 0x54
+#define ADC_BB_DATA 0x58
+
+/* Sound data register */
+#define ADC_SD_DAT0 0x60
+#define ADC_SD_DAT1 0x64
+#define ADC_SD_DAT2 0x68
+#define ADC_SD_DAT3 0x6c
+#define ADC_SD_DAT4 0x70
+#define ADC_SD_DAT5 0x74
+#define ADC_SD_DAT6 0x78
+#define ADC_SD_DAT7 0x7c
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/hardware.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define IOCLK (3686400L)
+
+/* Onchip peripherals */
+
+#define IO_VIRT 0xf0000000 /* IO peripherals */
+#define IO_PHYS 0x80000000
+#define IO_SIZE 0x00050000
+
+#ifdef CONFIG_CPU_H7202
+#include "h7202-regs.h"
+#elif defined CONFIG_CPU_H7201
+#include "h7201-regs.h"
+#else
+#error machine definition mismatch
+#endif
+
+/* Macro to access the CPU IO */
+#define CPU_IO(x) (*(volatile u32*)(x))
+
+/* Macro to access general purpose regs (base, offset) */
+#define CPU_REG(x,y) CPU_IO(x+y)
+
+/* Macro to access irq related regs */
+#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
+
+/* CPU registers */
+/* general purpose I/O */
+#define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5))
+#define GPIO_A_VIRT (GPIO_VIRT(0))
+#define GPIO_B_VIRT (GPIO_VIRT(1))
+#define GPIO_C_VIRT (GPIO_VIRT(2))
+#define GPIO_D_VIRT (GPIO_VIRT(3))
+#define GPIO_E_VIRT (GPIO_VIRT(4))
+#define GPIO_AMULSEL (GPIO_VIRT + 0xA4)
+/* Register offsets general purpose I/O */
+#define GPIO_DATA 0x00
+#define GPIO_DIR 0x04
+#define GPIO_MASK 0x08
+#define GPIO_STAT 0x0C
+#define GPIO_EDGE 0x10
+#define GPIO_CLR 0x14
+#define GPIO_POL 0x18
+#define GPIO_EN 0x1C
+
+/*interrupt controller */
+#define IRQC_VIRT (IO_VIRT + 0x24000)
+/* register offset interrupt controller */
+#define IRQC_IER 0x00
+#define IRQC_ISR 0x04
+
+/* timer unit */
+#define TIMER_VIRT (IO_VIRT + 0x25000)
+/* Register offsets timer unit */
+#define TM0_PERIOD 0x00
+#define TM0_COUNT 0x08
+#define TM0_CTRL 0x10
+#define TM1_PERIOD 0x20
+#define TM1_COUNT 0x28
+#define TM1_CTRL 0x30
+#define TM2_PERIOD 0x40
+#define TM2_COUNT 0x48
+#define TM2_CTRL 0x50
+#define TIMER_TOPCTRL 0x60
+#define TIMER_TOPSTAT 0x64
+#define T64_COUNTL 0x80
+#define T64_COUNTH 0x84
+#define T64_CTRL 0x88
+#define T64_BASEL 0x94
+#define T64_BASEH 0x98
+/* Bitmaks timer unit TOPSTAT reg */
+#define TSTAT_T0INT 0x1
+#define TSTAT_T1INT 0x2
+#define TSTAT_T2INT 0x4
+#define TSTAT_T3INT 0x8
+/* Bit description of TMx_CTRL register */
+#define TM_START 0x1
+#define TM_REPEAT 0x2
+#define TM_RESET 0x4
+/* Bit description of TIMER_CTRL register */
+#define ENABLE_TM0_INTR 0x1
+#define ENABLE_TM1_INTR 0x2
+#define ENABLE_TM2_INTR 0x4
+#define TIMER_ENABLE_BIT 0x8
+#define ENABLE_TIMER64 0x10
+#define ENABLE_TIMER64_INT 0x20
+
+/* PMU & PLL */
+#define PMU_BASE (IO_VIRT + 0x1000)
+#define PMU_MODE 0x00
+#define PMU_STAT 0x20
+#define PMU_PLL_CTRL 0x28
+
+/* PMU Mode bits */
+#define PMU_MODE_SLOW 0x00
+#define PMU_MODE_RUN 0x01
+#define PMU_MODE_IDLE 0x02
+#define PMU_MODE_SLEEP 0x03
+#define PMU_MODE_INIT 0x04
+#define PMU_MODE_DEEPSLEEP 0x07
+#define PMU_MODE_WAKEUP 0x08
+
+/* PMU ... */
+#define PLL_2_EN 0x8000
+#define PLL_1_EN 0x4000
+#define PLL_3_MUTE 0x0080
+
+/* Control bits for PMU/ PLL */
+#define PMU_WARMRESET 0x00010000
+#define PLL_CTRL_MASK23 0x000080ff
+
+/* LCD Controller */
+#define LCD_BASE (IO_VIRT + 0x10000)
+#define LCD_CTRL 0x00
+#define LCD_STATUS 0x04
+#define LCD_STATUS_M 0x08
+#define LCD_INTERRUPT 0x0C
+#define LCD_DBAR 0x10
+#define LCD_DCAR 0x14
+#define LCD_TIMING0 0x20
+#define LCD_TIMING1 0x24
+#define LCD_TIMING2 0x28
+#define LCD_TEST 0x40
+
+/* LCD Control Bits */
+#define LCD_CTRL_LCD_ENABLE 0x00000001
+/* Bits per pixel */
+#define LCD_CTRL_LCD_BPP_MASK 0x00000006
+#define LCD_CTRL_LCD_4BPP 0x00000000
+#define LCD_CTRL_LCD_8BPP 0x00000002
+#define LCD_CTRL_LCD_16BPP 0x00000004
+#define LCD_CTRL_LCD_BW 0x00000008
+#define LCD_CTRL_LCD_TFT 0x00000010
+#define LCD_CTRL_BGR 0x00001000
+#define LCD_CTRL_LCD_VCOMP 0x00080000
+#define LCD_CTRL_LCD_MONO8 0x00200000
+#define LCD_CTRL_LCD_PWR 0x00400000
+#define LCD_CTRL_LCD_BLE 0x00800000
+#define LCD_CTRL_LDBUSEN 0x01000000
+
+/* Palette */
+#define LCD_PALETTE_BASE (IO_VIRT + 0x10400)
+
+/* Serial ports */
+#define SERIAL0_VIRT (IO_VIRT + 0x20000)
+#define SERIAL1_VIRT (IO_VIRT + 0x21000)
+
+#define SERIAL0_BASE SERIAL0_VIRT
+#define SERIAL1_BASE SERIAL1_VIRT
+#define SERIAL2_BASE SERIAL2_VIRT
+#define SERIAL3_BASE SERIAL3_VIRT
+
+
+/* General defines to pacify gcc */
+#define PCIO_BASE (0) /* for inb, outb and friends */
+#define PCIO_VIRT PCIO_BASE
+
+#define __ASM_ARCH_HARDWARE_INCMACH_H
+#include "boards.h"
+#undef __ASM_ARCH_HARDWARE_INCMACH_H
+
+#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/io.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *
+ * 09-19-2001 JJKIM
+ * Created from linux/include/asm-arm/arch-l7200/io.h
+ *
+ * 03-27-2003 Robert Schwebel <r.schwebel@pengutronix.de>:
+ * re-unified header files for h720x
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/arch/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a) (a)
+#define __mem_pci(a) (a)
+
+#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-h720x/irq.h
+ *
+ * Copyright (C) 2000-2002 Jungjun Kim
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ */
+
+#ifndef __ASM_ARCH_IRQ_H
+#define __ASM_ARCH_IRQ_H
+
+extern void __init h720x_init_irq (void);
+
+#endif /* __ASM_ARCH_IRQ_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/irqs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#if defined (CONFIG_CPU_H7201)
+
+#define IRQ_PMU 0 /* 0x000001 */
+#define IRQ_DMA 1 /* 0x000002 */
+#define IRQ_LCD 2 /* 0x000004 */
+#define IRQ_VGA 3 /* 0x000008 */
+#define IRQ_PCMCIA1 4 /* 0x000010 */
+#define IRQ_PCMCIA2 5 /* 0x000020 */
+#define IRQ_AFE 6 /* 0x000040 */
+#define IRQ_AIC 7 /* 0x000080 */
+#define IRQ_KEYBOARD 8 /* 0x000100 */
+#define IRQ_TIMER0 9 /* 0x000200 */
+#define IRQ_RTC 10 /* 0x000400 */
+#define IRQ_SOUND 11 /* 0x000800 */
+#define IRQ_USB 12 /* 0x001000 */
+#define IRQ_IrDA 13 /* 0x002000 */
+#define IRQ_UART0 14 /* 0x004000 */
+#define IRQ_UART1 15 /* 0x008000 */
+#define IRQ_SPI 16 /* 0x010000 */
+#define IRQ_GPIOA 17 /* 0x020000 */
+#define IRQ_GPIOB 18 /* 0x040000 */
+#define IRQ_GPIOC 19 /* 0x080000 */
+#define IRQ_GPIOD 20 /* 0x100000 */
+#define IRQ_CommRX 21 /* 0x200000 */
+#define IRQ_CommTX 22 /* 0x400000 */
+#define IRQ_Soft 23 /* 0x800000 */
+
+#define NR_GLBL_IRQS 24
+
+#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
+#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
+#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
+#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
+#define NR_IRQS IRQ_CHAINED_GPIOD(32)
+
+/* Enable mask for multiplexed interrupts */
+#define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
+ | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
+
+
+#elif defined (CONFIG_CPU_H7202)
+
+#define IRQ_PMU 0 /* 0x00000001 */
+#define IRQ_DMA 1 /* 0x00000002 */
+#define IRQ_LCD 2 /* 0x00000004 */
+#define IRQ_SOUND 3 /* 0x00000008 */
+#define IRQ_I2S 4 /* 0x00000010 */
+#define IRQ_USB 5 /* 0x00000020 */
+#define IRQ_MMC 6 /* 0x00000040 */
+#define IRQ_RTC 7 /* 0x00000080 */
+#define IRQ_UART0 8 /* 0x00000100 */
+#define IRQ_UART1 9 /* 0x00000200 */
+#define IRQ_UART2 10 /* 0x00000400 */
+#define IRQ_UART3 11 /* 0x00000800 */
+#define IRQ_KBD 12 /* 0x00001000 */
+#define IRQ_PS2 13 /* 0x00002000 */
+#define IRQ_AIC 14 /* 0x00004000 */
+#define IRQ_TIMER0 15 /* 0x00008000 */
+#define IRQ_TIMERX 16 /* 0x00010000 */
+#define IRQ_WDT 17 /* 0x00020000 */
+#define IRQ_CAN0 18 /* 0x00040000 */
+#define IRQ_CAN1 19 /* 0x00080000 */
+#define IRQ_EXT0 20 /* 0x00100000 */
+#define IRQ_EXT1 21 /* 0x00200000 */
+#define IRQ_GPIOA 22 /* 0x00400000 */
+#define IRQ_GPIOB 23 /* 0x00800000 */
+#define IRQ_GPIOC 24 /* 0x01000000 */
+#define IRQ_GPIOD 25 /* 0x02000000 */
+#define IRQ_GPIOE 26 /* 0x04000000 */
+#define IRQ_COMMRX 27 /* 0x08000000 */
+#define IRQ_COMMTX 28 /* 0x10000000 */
+#define IRQ_SMC 29 /* 0x20000000 */
+#define IRQ_Soft 30 /* 0x40000000 */
+#define IRQ_RESERVED1 31 /* 0x80000000 */
+#define NR_GLBL_IRQS 32
+
+#define NR_TIMERX_IRQS 3
+
+#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
+#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
+#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
+#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
+#define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x)
+#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
+#define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0))
+#define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1))
+#define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2))
+
+#define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
+
+/* Enable mask for multiplexed interrupts */
+#define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
+ (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
+ (1<<IRQ_TIMERX)
+
+#else
+#error cpu definition mismatch
+#endif
+
+/* decode irq number to register number */
+#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
+#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/memory.h
+ *
+ * Copyright (c) 2000 Jungjun Kim
+ *
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Page offset:
+ * ( 0xc0000000UL )
+ */
+#define PHYS_OFFSET (0x40000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ * address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ * to an address that the kernel can use.
+ *
+ * There is something to do here later !, Mar 2000, Jungjun Kim
+ */
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/param.h
+ *
+ * Copyright (C) 2000 Jungjun Kim
+ */
+
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h72x/serial.h
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * Serial port setup for Hynix boards
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <asm/arch/irqs.h>
+
+/*
+ * Standard COM flags
+ */
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define RS_TABLE_SIZE
+
+/* Base clock is 3.6864 MHz */
+#define BASE_BAUD (115200*2)
+#define EXTRA_SERIAL_PORT_DEFNS
+
+/*
+ * Board dependend defines
+ */
+#if defined (CONFIG_CPU_H7201)
+#define BASE_BAUD_P3C (115200)
+
+#define STD_SERIAL_PORT_DEFNS \
+ { \
+ .baud_base = BASE_BAUD, \
+ .port = SERIAL0_BASE, \
+ .iomem_base = (u8*)SERIAL0_BASE, \
+ .io_type = UPIO_MEM, \
+ .irq = IRQ_UART0, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_reg_shift = 2,\
+ }, \
+ { \
+ .baud_base = BASE_BAUD, \
+ .port = SERIAL1_BASE, \
+ .iomem_base = (u8*)SERIAL1_BASE, \
+ .io_type = UPIO_MEM, \
+ .irq = IRQ_UART1, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_reg_shift = 2,\
+ }
+
+#elif defined (CONFIG_CPU_H7202)
+
+#define STD_SERIAL_PORT_DEFNS \
+ { \
+ .baud_base = BASE_BAUD, \
+ .port = SERIAL0_BASE, \
+ .iomem_base = (u8*)SERIAL0_BASE, \
+ .io_type = UPIO_MEM, \
+ .irq = IRQ_UART0, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_reg_shift = 2,\
+ }, \
+ { \
+ .baud_base = BASE_BAUD, \
+ .port = SERIAL1_BASE, \
+ .iomem_base = (u8*)SERIAL1_BASE, \
+ .io_type = UPIO_MEM, \
+ .irq = IRQ_UART1, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_reg_shift = 2,\
+ }, \
+ { \
+ .baud_base = BASE_BAUD, \
+ .port = SERIAL2_BASE, \
+ .iomem_base = (u8*)SERIAL2_BASE, \
+ .io_type = UPIO_MEM, \
+ .irq = IRQ_UART2, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_reg_shift = 2,\
+ }, \
+ { \
+ .baud_base = BASE_BAUD, \
+ .port = SERIAL3_BASE, \
+ .iomem_base = (u8*)SERIAL3_BASE, \
+ .io_type = UPIO_MEM, \
+ .irq = IRQ_UART3, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_reg_shift = 2,\
+ }
+
+#else
+#error machine definition mismatch
+#endif
+
+/* __ASM_ARCH_SERIAL_H */
+#endif
--- /dev/null
+/*
+ * linux/arch/arm/mach-h720x/system.h
+ *
+ * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * linux/include/asm-arm/arch-h720x/system.h
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
+
+static void arch_idle(void)
+{
+ CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
+ __asm__ __volatile__(
+ "mov r0, r0\n\t"
+ "mov r0, r0");
+}
+
+
+static __inline__ void arch_reset(char mode)
+{
+ CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
+}
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/timex.h
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX
+#define __ASM_ARCH_TIMEX
+
+#define CLOCK_TICK_RATE 3686400
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/uncompress.h
+ *
+ * Copyright (C) 2001-2002 Jungjun Kim
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/arch/hardware.h>
+
+#define LSR 0x14
+#define TEMPTY 0x40
+
+static void putstr(const char *s)
+{
+ char c;
+ volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
+
+ while ( (c = *s++) != '\0') {
+ /* wait until transmit buffer is empty */
+ while((p[LSR] & TEMPTY) == 0x0);
+ /* write next character */
+ *p = c;
+
+ if(c == '\n') {
+ while((p[LSR] & TEMPTY) == 0x0);
+ *p = '\r';
+ }
+ }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-h720x/vmalloc.h
+ */
+
+#ifndef __ARCH_ARM_VMALLOC_H
+#define __ARCH_ARM_VMALLOC_H
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET (8*1024*1024)
+#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/imxads/dma.h
+ *
+ * Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS 0xffffffff
+
+#define MAX_DMA_CHANNELS 0
+
+/*
+ * DMA registration
+ */
+
+typedef enum {
+ DMA_PRIO_HIGH = 0,
+ DMA_PRIO_MEDIUM = 3,
+ DMA_PRIO_LOW = 6
+} imx_dma_prio;
+
+int imx_request_dma(char *name, imx_dma_prio prio,
+ void (*irq_handler) (int, void *, struct pt_regs *),
+ void (*err_handler) (int, void *, struct pt_regs *),
+ void *data);
+
+void imx_free_dma(int dma_ch);
+
+
+#define DMA_REQ_UART3_T 2
+#define DMA_REQ_UART3_R 3
+#define DMA_REQ_SSI2_T 4
+#define DMA_REQ_SSI2_R 5
+#define DMA_REQ_CSI_STAT 6
+#define DMA_REQ_CSI_R 7
+#define DMA_REQ_MSHC 8
+#define DMA_REQ_DSPA_DCT_DOUT 9
+#define DMA_REQ_DSPA_DCT_DIN 10
+#define DMA_REQ_DSPA_MAC 11
+#define DMA_REQ_EXT 12
+#define DMA_REQ_SDHC 13
+#define DMA_REQ_SPI1_R 14
+#define DMA_REQ_SPI1_T 15
+#define DMA_REQ_SSI_T 16
+#define DMA_REQ_SSI_R 17
+#define DMA_REQ_ASP_DAC 18
+#define DMA_REQ_ASP_ADC 19
+#define DMA_REQ_USP_EP(x) (20+(x))
+#define DMA_REQ_SPI2_R 26
+#define DMA_REQ_SPI2_T 27
+#define DMA_REQ_UART2_T 28
+#define DMA_REQ_UART2_R 29
+#define DMA_REQ_UART1_T 30
+#define DMA_REQ_UART1_R 31
+
+#endif /* _ASM_ARCH_DMA_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imx/hardware.h
+ *
+ * Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include "imx-regs.h"
+
+#ifndef __ASSEMBLY__
+# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
+
+# define __REG2(x,y) \
+ ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+ : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+#endif
+
+/*
+ * Memory map
+ */
+
+#define IMX_IO_PHYS 0x00200000
+#define IMX_IO_SIZE 0x00100000
+#define IMX_IO_BASE 0xe0000000
+
+#define IMX_CS0_PHYS 0x10000000
+#define IMX_CS0_SIZE 0x02000000
+#define IMX_CS0_VIRT 0xe8000000
+
+#define IMX_CS1_PHYS 0x12000000
+#define IMX_CS1_SIZE 0x01000000
+#define IMX_CS1_VIRT 0xea000000
+
+#define IMX_CS2_PHYS 0x13000000
+#define IMX_CS2_SIZE 0x01000000
+#define IMX_CS2_VIRT 0xeb000000
+
+#define IMX_CS3_PHYS 0x14000000
+#define IMX_CS3_SIZE 0x01000000
+#define IMX_CS3_VIRT 0xec000000
+
+#define IMX_CS4_PHYS 0x15000000
+#define IMX_CS4_SIZE 0x01000000
+#define IMX_CS4_VIRT 0xed000000
+
+#define IMX_CS5_PHYS 0x16000000
+#define IMX_CS5_SIZE 0x01000000
+#define IMX_CS5_VIRT 0xee000000
+
+#define IMX_FB_VIRT 0xF1000000
+#define IMX_FB_SIZE (256*1024)
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
+
+#ifndef __ASSEMBLY__
+/*
+ * Handy routine to set GPIO functions
+ */
+extern void imx_gpio_mode( int gpio_mode );
+
+/* get frequencies in Hz */
+extern unsigned int imx_get_system_clk(void);
+extern unsigned int imx_get_mcu_clk(void);
+extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
+extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */
+extern unsigned int imx_get_perclk3(void); /* SSI */
+extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/
+ /* I2C, DMA */
+#endif
+
+#define MAXIRQNUM 62
+#define MAXFIQNUM 62
+#define MAXSWINUM 62
+
+/*
+ * Use SDRAM for memory
+ */
+#define MEM_SIZE 0x01000000
+
+#ifdef CONFIG_ARCH_MX1ADS
+#include "mx1ads.h"
+#endif
+
+#endif
--- /dev/null
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+/* ------------------------------------------------------------------------
+ * Motorola IMX system registers
+ * ------------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Register BASEs, based on OFFSETs
+ *
+ */
+#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
+#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
+#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
+#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
+#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
+#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
+#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
+#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
+#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
+#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
+#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
+#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
+#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
+#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
+#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
+#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
+#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
+#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
+#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
+#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
+#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
+#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
+#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
+
+/* PLL registers */
+#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
+#define CSCR_SYSTEM_SEL (1<<16)
+
+#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
+#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
+#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
+#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
+
+#define CSCR_MPLL_RESTART (1<<21)
+
+/*
+ * GPIO Module and I/O Multiplexer
+ * x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
+#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
+#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
+#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
+#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
+#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
+#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
+#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
+#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
+#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
+#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
+#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
+#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_MASK (0x3 << 5)
+
+#define GPIO_PORTA (0<<5)
+#define GPIO_PORTB (1<<5)
+#define GPIO_PORTC (2<<5)
+#define GPIO_PORTD (3<<5)
+
+#define GPIO_OUT (1<<7)
+#define GPIO_IN (0<<7)
+#define GPIO_PUEN (1<<8)
+
+#define GPIO_PF (0<<9)
+#define GPIO_AF (1<<9)
+
+#define GPIO_OCR_MASK (3<<10)
+#define GPIO_AIN (0<<10)
+#define GPIO_BIN (1<<10)
+#define GPIO_CIN (2<<10)
+#define GPIO_GPIO (3<<10)
+
+#define GPIO_AOUT (1<<12)
+#define GPIO_BOUT (1<<13)
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
+#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
+#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
+#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
+#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
+#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ * DMA Controller
+ */
+#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
+#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
+#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
+#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
+#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
+#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
+#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
+#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
+#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
+#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
+#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
+#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
+#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
+#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
+#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
+#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
+#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
+#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
+#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
+#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
+#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
+#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
+
+#define DCR_DRST (1<<1)
+#define DCR_DEN (1<<0)
+#define DBTOCR_EN (1<<15)
+#define DBTOCR_CNT(x) ((x) & 0x7fff )
+#define CNTR_CNT(x) ((x) & 0xffffff )
+#define CCR_DMOD_LINEAR ( 0x0 << 12 )
+#define CCR_DMOD_2D ( 0x1 << 12 )
+#define CCR_DMOD_FIFO ( 0x2 << 12 )
+#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
+#define CCR_SMOD_LINEAR ( 0x0 << 10 )
+#define CCR_SMOD_2D ( 0x1 << 10 )
+#define CCR_SMOD_FIFO ( 0x2 << 10 )
+#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
+#define CCR_MDIR_DEC (1<<9)
+#define CCR_MSEL_B (1<<8)
+#define CCR_DSIZ_32 ( 0x0 << 6 )
+#define CCR_DSIZ_8 ( 0x1 << 6 )
+#define CCR_DSIZ_16 ( 0x2 << 6 )
+#define CCR_SSIZ_32 ( 0x0 << 4 )
+#define CCR_SSIZ_8 ( 0x1 << 4 )
+#define CCR_SSIZ_16 ( 0x2 << 4 )
+#define CCR_REN (1<<3)
+#define CCR_RPT (1<<2)
+#define CCR_FRC (1<<1)
+#define CCR_CEN (1<<0)
+#define RTOR_EN (1<<15)
+#define RTOR_CLK (1<<14)
+#define RTOR_PSC (1<<13)
+
+/*
+ * Interrupt controller
+ */
+
+#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00)
+#define INTCNTL_FIAD (1<<19)
+#define INTCNTL_NIAD (1<<20)
+
+#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04)
+#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08)
+#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c)
+#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10)
+#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14)
+
+/*
+ * General purpose timers
+ */
+#define IMX_TCTL(x) __REG( 0x00 + (x))
+#define TCTL_SWR (1<<15)
+#define TCTL_FRR (1<<8)
+#define TCTL_CAP_RIS (1<<6)
+#define TCTL_CAP_FAL (2<<6)
+#define TCTL_CAP_RIS_FAL (3<<6)
+#define TCTL_OM (1<<5)
+#define TCTL_IRQEN (1<<4)
+#define TCTL_CLK_PCLK1 (1<<1)
+#define TCTL_CLK_PCLK1_16 (2<<1)
+#define TCTL_CLK_TIN (3<<1)
+#define TCTL_CLK_32 (4<<1)
+#define TCTL_TEN (1<<0)
+
+#define IMX_TPRER(x) __REG( 0x04 + (x))
+#define IMX_TCMP(x) __REG( 0x08 + (x))
+#define IMX_TCR(x) __REG( 0x0C + (x))
+#define IMX_TCN(x) __REG( 0x10 + (x))
+#define IMX_TSTAT(x) __REG( 0x14 + (x))
+#define TSTAT_CAPT (1<<1)
+#define TSTAT_COMP (1<<0)
+
+/*
+ * LCD Controller
+ */
+
+#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
+
+#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
+#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y) ( (y) & 0x1ff )
+
+#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
+#define VPW_VPW(x) ( (x) & 0x3ff )
+
+#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
+#define CPOS_CC1 (1<<31)
+#define CPOS_CC0 (1<<30)
+#define CPOS_OP (1<<28)
+#define CPOS_CXP(x) (((x) & 3ff) << 16)
+#define CPOS_CYP(y) ((y) & 0x1ff)
+
+#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
+#define LCWHB_BK_EN (1<<31)
+#define LCWHB_CW(w) (((w) & 0x1f) << 24)
+#define LCWHB_CH(h) (((h) & 0x1f) << 16)
+#define LCWHB_BD(x) ((x) & 0xff)
+
+#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
+#define PCR_TFT (1<<31)
+#define PCR_COLOR (1<<30)
+#define PCR_PBSIZ_1 (0<<28)
+#define PCR_PBSIZ_2 (1<<28)
+#define PCR_PBSIZ_4 (2<<28)
+#define PCR_PBSIZ_8 (3<<28)
+#define PCR_BPIX_1 (0<<25)
+#define PCR_BPIX_2 (1<<25)
+#define PCR_BPIX_4 (2<<25)
+#define PCR_BPIX_8 (3<<25)
+#define PCR_BPIX_12 (4<<25)
+#define PCR_BPIX_16 (4<<25)
+#define PCR_PIXPOL (1<<24)
+#define PCR_FLMPOL (1<<23)
+#define PCR_LPPOL (1<<22)
+#define PCR_CLKPOL (1<<21)
+#define PCR_OEPOL (1<<20)
+#define PCR_SCLKIDLE (1<<19)
+#define PCR_END_SEL (1<<18)
+#define PCR_END_BYTE_SWAP (1<<17)
+#define PCR_REV_VS (1<<16)
+#define PCR_ACD_SEL (1<<15)
+#define PCR_ACD(x) (((x) & 0x7f) << 8)
+#define PCR_SCLK_SEL (1<<7)
+#define PCR_SHARP (1<<6)
+#define PCR_PCD(x) ((x) & 0x3f)
+
+#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
+#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
+#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
+#define POS_POS(x) ((x) & 1f)
+
+#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
+#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
+#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
+#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
+#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
+#define LSCR1_GRAY1(x) (((x) & 0xf))
+
+#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
+#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
+#define PWMR_LDMSK (1<<15)
+#define PWMR_SCR1 (1<<10)
+#define PWMR_SCR0 (1<<9)
+#define PWMR_CC_EN (1<<8)
+#define PWMR_PW(x) ((x) & 0xff)
+
+#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
+#define DMACR_BURST (1<<31)
+#define DMACR_HM(x) (((x) & 0xf) << 16)
+#define DMACR_TM(x) ((x) &0xf)
+
+#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
+#define RMCR_LCDC_EN (1<<1)
+#define RMCR_SELF_REF (1<<0)
+
+#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
+#define LCDICR_INT_SYN (1<<2)
+#define LCDICR_INT_CON (1)
+
+#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
+#define LCDISR_UDR_ERR (1<<3)
+#define LCDISR_ERR_RES (1<<2)
+#define LCDISR_EOF (1<<1)
+#define LCDISR_BOF (1<<0)
+
+/*
+ * UART Module. Takes the UART base address as argument
+ */
+#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
+#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
+#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
+#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
+#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
+#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
+#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
+#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
+#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
+#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
+#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
+#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
+#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
+#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
+#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
+#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
+#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
+#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
+#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
+#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
+#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
+#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
+#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */
+
+/* UART Control Register Bit Fields.*/
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRST (1<<0) /* Software reset */
+
+#endif // _IMX_REGS_H
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imxads/io.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a) (a)
+#define __mem_pci(a) (a)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imxads/irq.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define fixup_irq(i) (i)
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imxads/irqs.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ARM_IRQS_H__
+#define __ARM_IRQS_H__
+
+/* Use the imx definitions */
+#include <asm/arch/hardware.h>
+
+/*
+ * IMX Interrupt numbers
+ *
+ */
+#define INT_SOFTINT 0
+#define CSI_INT 6
+#define DSPA_MAC_INT 7
+#define DSPA_INT 8
+#define COMP_INT 9
+#define MSHC_XINT 10
+#define GPIO_INT_PORTA 11
+#define GPIO_INT_PORTB 12
+#define GPIO_INT_PORTC 13
+#define LCDC_INT 14
+#define SIM_INT 15
+#define SIM_DATA_INT 16
+#define RTC_INT 17
+#define RTC_SAMINT 18
+#define UART2_MINT_PFERR 19
+#define UART2_MINT_RTS 20
+#define UART2_MINT_DTR 21
+#define UART2_MINT_UARTC 22
+#define UART2_MINT_TX 23
+#define UART2_MINT_RX 24
+#define UART1_MINT_PFERR 25
+#define UART1_MINT_RTS 26
+#define UART1_MINT_DTR 27
+#define UART1_MINT_UARTC 28
+#define UART1_MINT_TX 29
+#define UART1_MINT_RX 30
+#define VOICE_DAC_INT 31
+#define VOICE_ADC_INT 32
+#define PEN_DATA_INT 33
+#define PWM_INT 34
+#define SDHC_INT 35
+#define I2C_INT 39
+#define CSPI_INT 41
+#define SSI_TX_INT 42
+#define SSI_TX_ERR_INT 43
+#define SSI_RX_INT 44
+#define SSI_RX_ERR_INT 45
+#define TOUCH_INT 46
+#define USBD_INT0 47
+#define USBD_INT1 48
+#define USBD_INT2 49
+#define USBD_INT3 50
+#define USBD_INT4 51
+#define USBD_INT5 52
+#define USBD_INT6 53
+#define BTSYS_INT 55
+#define BTTIM_INT 56
+#define BTWUI_INT 57
+#define TIM2_INT 58
+#define TIM1_INT 59
+#define DMA_ERR 60
+#define DMA_INT 61
+#define GPIO_INT_PORTD 62
+
+#define IMX_IRQS (64)
+
+/* note: the IMX has four gpio ports (A-D), but only
+ * the following pins are connected to the outside
+ * world:
+ *
+ * PORT A: bits 0-31
+ * PORT B: bits 8-31
+ * PORT C: bits 3-17
+ * PORT D: bits 6-31
+ *
+ * We map these interrupts straight on. As a result we have
+ * several holes in the interrupt mapping. We do this for two
+ * reasons:
+ * - mapping the interrupts without holes would get
+ * far more complicated
+ * - Motorola could well decide to bring some processor
+ * with more pins connected
+ */
+
+#define IRQ_GPIOA(x) (IMX_IRQS + x)
+#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
+
+#define NR_IRQS (IRQ_GPIOD(32) + 1)
+#define IRQ_GPIO(x)
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imx/memory.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#define PHYS_OFFSET (0x08000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ * address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ * to an address that the kernel can use.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imx/mx1ads.h
+ *
+ * Copyright (C) 2004 Robert Schwebel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MX1ADS_H
+#define __ASM_ARCH_MX1ADS_H
+
+/* ------------------------------------------------------------------------ */
+/* Memory Map for the M9328MX1ADS (MX1ADS) Board */
+/* ------------------------------------------------------------------------ */
+
+#define MX1ADS_FLASH_PHYS 0x10000000
+#define MX1ADS_FLASH_SIZE (16*1024*1024)
+
+#define IMX_FB_PHYS (0x0C000000 - 0x40000)
+
+#define CLK32 32000
+
+#endif /* __ASM_ARCH_MX1ADS_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imx/param.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imx/serial.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#define STD_SERIAL_PORT_DEFNS
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif /* __ASM_ARCH_SERIAL_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imxads/system.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void
+arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void
+arch_reset(char mode)
+{
+ cpu_reset(0);
+}
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/imx/timex.h
+ *
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#include <asm/arch/hardware.h>
+#define CLOCK_TICK_RATE (CLK32)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imxads/uncompress.h
+ *
+ *
+ *
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define UART1_BASE 0x206000
+#define UART2_BASE 0x207000
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR 0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader. We search for the first enabled
+ * port in the most probable order. If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void
+putstr(const char *s)
+{
+ unsigned long serial_port;
+
+ do {
+ serial_port = UART1_BASE;
+ if ( UART(UCR1) & UCR1_UARTEN )
+ break;
+ serial_port = UART2_BASE;
+ if ( UART(UCR1) & UCR1_UARTEN )
+ break;
+ return;
+ } while(0);
+
+ while (*s) {
+ while ( !(UART(USR2) & USR2_TXFE) )
+ barrier();
+
+ UART(TXR) = *s;
+
+ if (*s == '\n') {
+ while ( !(UART(USR2) & USR2_TXFE) )
+ barrier();
+
+ UART(TXR) = '\r';
+ }
+ s++;
+ }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-imx/vmalloc.h
+ *
+ * Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET (8*1024*1024)
+#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-iop3xx/irqs.h
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright: (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _IOP331_IRQS_H_
+#define _IOP331_IRQS_H_
+
+/*
+ * IOP80331 chipset interrupts
+ */
+#define IOP331_IRQ_OFS 0
+#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x))
+
+/*
+ * On IRQ or FIQ register
+ */
+#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
+#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
+#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
+#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
+#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
+#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
+#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
+#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
+#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
+#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
+#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
+#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
+#define IRQ_IOP331_MSG IOP331_IRQ(12)
+#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
+#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
+#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
+#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
+#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
+#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
+#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
+#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
+#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
+#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
+#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
+#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
+#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
+#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
+#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
+#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
+#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
+#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
+#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
+#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
+#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
+#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
+#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
+#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
+#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
+#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
+#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
+#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
+#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
+#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
+#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
+#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
+#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
+#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
+#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
+#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
+#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
+#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
+#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
+#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
+#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
+#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
+#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
+#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
+#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
+#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
+#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
+#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
+#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
+#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
+#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
+
+#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1)
+
+#define NR_IRQS NR_IOP331_IRQS
+
+
+/*
+ * Interrupts available on the IQ80331 board
+ */
+
+/*
+ * On board devices
+ */
+#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
+#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
+#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
+
+/*
+ * PCI interrupts
+ */
+#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
+#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
+#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
+#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
+
+#endif // _IOP331_IRQ_H_
--- /dev/null
+/*
+ * linux/include/asm/arch-iop3xx/iop331.h
+ *
+ * Intel IOP331 Chip definitions
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP331_HW_H_
+#define _IOP331_HW_H_
+
+
+/*
+ * This is needed for mixed drivers that need to work on all
+ * IOP3xx variants but behave slightly differently on each.
+ */
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_ARCH_IOP331
+#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090)
+#else
+#define iop_is_331() 0
+#endif
+#endif
+
+/*
+ * IOP331 I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP331_PCI_LOWER_IO 0x90000000
+#define IOP331_PCI_UPPER_IO 0x900fffff
+#define IOP331_PCI_LOWER_MEM 0x80000000
+#define IOP331_PCI_UPPER_MEM 0x87ffffff
+
+#define IOP331_PCI_WINDOW_SIZE 128 * 0x100000
+
+
+/*
+ * IOP331 chipset registers
+ */
+#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
+// #define IOP331_VIRT_MEM_BASE 0xfff00000 /* chip virtual mem address*/
+
+#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
+#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
+
+/* Reserved 0x00000000 through 0x000000FF */
+
+/* Address Translation Unit 0x00000100 through 0x000001FF */
+#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
+#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
+#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
+#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
+#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
+#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
+#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
+#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
+#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
+#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
+#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
+#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
+#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
+#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
+#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
+#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
+#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
+#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
+#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
+#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
+/* Reserved 0x00000138 through 0x0000013B */
+#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
+#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
+#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
+#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
+#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
+#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
+#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
+#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
+#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
+#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
+#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
+#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
+#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
+#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
+#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
+#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
+/* Reserved 0x00000170 through 0x00000177*/
+#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
+/* Reserved 0x0000017C through 0x0000017F*/
+#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
+#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
+#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
+#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
+#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
+#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
+#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
+#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
+/* Reserved 0x000001A0 through 0x000001A3*/
+#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
+/* Reserved 0x000001A8 through 0x000001AB*/
+#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
+/* Reserved 0x000001B0 through 0x000001BB*/
+#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
+#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
+#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
+#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
+#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
+#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
+#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
+#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
+/* Reserved 0x000001C6 through 0x000001CF */
+#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
+#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
+#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
+#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
+#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
+#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
+#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
+#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
+#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
+#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
+#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
+
+/* Messaging Unit 0x00000300 through 0x000003FF */
+
+/* Reserved 0x00000300 through 0x0000030c */
+#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310)
+#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314)
+#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318)
+#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
+#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320)
+#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324)
+#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328)
+#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
+#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330)
+#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334)
+/* Reserved 0x00000338 through 0x0000034F */
+#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350)
+#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354)
+/* Reserved 0x00000358 through 0x0000035C */
+#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360)
+#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364)
+#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368)
+#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
+#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370)
+#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374)
+#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378)
+#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
+#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380)
+/* Reserved 0x00000384 through 0x000003FF */
+
+/* DMA Controller 0x00000400 through 0x000004FF */
+#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400)
+#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404)
+#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
+#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410)
+#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414)
+#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
+#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
+#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420)
+#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424)
+/* Reserved 0x00000428 through 0x0000043C */
+#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440)
+#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444)
+#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
+#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450)
+#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454)
+#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
+#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
+#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460)
+#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464)
+/* Reserved 0x00000468 through 0x000004FF */
+
+/* Memory controller 0x00000500 through 0x0005FF */
+
+/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
+#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680)
+#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684)
+#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688)
+#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
+#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690)
+#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694)
+#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698)
+#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
+#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
+#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
+#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
+#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
+#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
+#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
+#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
+/* Reserved 0x000006BC */
+#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
+/* Reserved 0x000006C4 through 0x000006DC */
+#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
+#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
+
+#define IOP331_PBCR_EN 0x1
+
+#define IOP331_PBISR_BOOR_ERR 0x1
+
+
+
+/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
+/* Internal arbitration unit 0x00000780 through 0x0007BF */
+
+/* Interrupt Controller */
+#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
+#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
+#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
+#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
+#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
+#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
+#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
+#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
+#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
+#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
+#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
+#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
+#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
+#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
+#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
+#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
+
+
+/* Timers */
+
+#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
+#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
+
+#define IOP331_TMR_TC 0x01
+#define IOP331_TMR_EN 0x02
+#define IOP331_TMR_RELOAD 0x04
+#define IOP331_TMR_PRIVILEGED 0x09
+
+#define IOP331_TMR_RATIO_1_1 0x00
+#define IOP331_TMR_RATIO_4_1 0x10
+#define IOP331_TMR_RATIO_8_1 0x20
+#define IOP331_TMR_RATIO_16_1 0x30
+
+#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
+#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
+#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
+#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
+#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
+#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
+
+#define IOP331_TICK_RATE 266000000 /* 266 MHz clock */
+
+
+/* Application accelerator unit 0x00000800 - 0x000008FF */
+#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
+#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
+#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808)
+#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
+#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810)
+#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814)
+#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818)
+#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
+#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
+#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830)
+#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834)
+#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838)
+#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840)
+#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844)
+#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848)
+#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
+#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850)
+#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854)
+#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858)
+#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
+#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864)
+#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868)
+#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
+#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870)
+#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874)
+#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878)
+#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
+#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880)
+#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888)
+#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
+#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890)
+#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894)
+#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898)
+#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
+#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
+#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
+#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820)
+#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824)
+#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828)
+#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
+#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860)
+#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884)
+
+
+#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
+#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
+/* SSP serial port unit 0x00001600 - 0x0000167F */
+
+/* I2C bus interface unit 0x00001680 - 0x000016FF */
+/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
+
+#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680)
+#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684)
+#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688)
+#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
+/* Reserved 0x00001690 */
+#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694)
+/* Reserved 0x00001698 */
+/* Reserved 0x0000169C */
+#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
+#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
+#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
+#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
+#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
+/* Reserved 0x000016B8 through 0x000016FF */
+
+/* 0x00001700 through 0x0000172C UART 0 */
+
+/* Reserved 0x00001730 through 0x0000173F */
+
+/* 0x00001740 through 0x0000176C UART 1 */
+
+/* Reserved 0x00001770 through 0x0000177F */
+
+/* General Purpose I/O Registers */
+#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
+#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
+#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
+
+/* Reserved 0x0000178c through 0x000019ff */
+
+#ifndef __ASSEMBLY__
+extern void iop331_map_io(void);
+extern void iop331_init_irq(void);
+extern void iop331_time_init(void);
+#endif
+
+#endif // _IOP331_HW_H_
--- /dev/null
+/*
+ * linux/include/asm/arch-iop3xx/iq31244.h
+ *
+ * Intel IQ31244 evaluation board registers
+ */
+
+#ifndef _IQ31244_H_
+#define _IQ31244_H_
+
+#define IQ31244_RAMBASE 0xa0000000
+
+#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
+#define IQ31244_FLASHSIZE 0x00800000
+#define IQ31244_FLASHWIDTH 2
+
+#define IQ31244_UART 0xfe800000 /* UART #1 */
+#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
+#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
+#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
+#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
+
+/*
+ * IQ31244 PCI I/O and Mem space regions
+ */
+#define IQ31244_PCI_IO_BASE 0x90000000
+#define IQ31244_PCI_IO_SIZE 0x00010000
+#define IQ31244_PCI_MEM_BASE 0x80000000
+//#define IQ31244_PCI_MEM_SIZE 0x04000000
+#define IQ31244_PCI_MEM_SIZE 0x08000000
+#define IQ31244_PCI_IO_OFFSET 0x6e000000
+
+#ifndef __ASSEMBLY__
+extern void iq31244_map_io(void);
+#endif
+
+#endif // _IQ31244_H_
--- /dev/null
+/*
+ * linux/include/asm/arch-iop3xx/iq80331.h
+ *
+ * Intel IQ80331 evaluation board registers
+ */
+
+#ifndef _IQ80331_H_
+#define _IQ80331_H_
+
+#define IQ80331_RAMBASE 0x00000000
+
+#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
+#define IQ80331_FLASHSIZE 0x00800000
+#define IQ80331_FLASHWIDTH 1
+
+#define IQ80331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
+#define IQ80331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
+#define IQ80331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
+#define IQ80331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
+#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
+#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
+#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
+#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
+
+/*
+ * IQ80331 PCI I/O and Mem space regions
+ */
+#define IQ80331_PCI_IO_BASE 0x90000000
+#define IQ80331_PCI_IO_SIZE 0x00010000
+#define IQ80331_PCI_MEM_BASE 0x80000000
+#define IQ80331_PCI_MEM_SIZE 0x08000000
+#define IQ80331_PCI_IO_OFFSET 0x6e000000
+
+#ifndef __ASSEMBLY__
+extern void iq80331_map_io(void);
+#endif
+
+#endif // _IQ80331_H_
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixdp2400/dma.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS 0xffffffff
+
+/* No DMA */
+#define MAX_DMA_CHANNELS 0
+
+#endif /* _ASM_ARCH_DMA_H */
--- /dev/null
+/*
+ * include/asm-arm/arch-ixp2000/enp2611.h
+ *
+ * Register and other defines for Radisys ENP-2611
+ *
+ * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
+ * original version carries the following notices:
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ENP2611_H
+#define __ENP2611_H
+
+#define ENP2611_GPIO_SCL 0x07
+#define ENP2611_GPIO_SDA 0x06
+
+
+#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-ixp2000/ixp2000-gpio.h
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software, you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * IXP2000 GPIO in/out, edge/level detection for IRQs:
+ * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
+ * or both Falling-edge and Rising-edge.
+ * This must be called *before* the corresponding IRQ is registerd.
+ * Use this instead of directly setting the GPIO registers.
+ * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
+ */
+#ifndef _ASM_ARCH_IXP2000_GPIO_H_
+#define _ASM_ARCH_IXP2000_GPIO_H_
+
+#ifndef __ASSEMBLY__
+#define GPIO_OUT 0x0
+#define GPIO_IN 0x80
+
+#define IXP2000_GPIO_LOW 0
+#define IXP2000_GPIO_HIGH 1
+
+#define GPIO_NO_EDGES 0
+#define GPIO_FALLING_EDGE 1
+#define GPIO_RISING_EDGE 2
+#define GPIO_BOTH_EDGES 3
+#define GPIO_LEVEL_LOW 4
+#define GPIO_LEVEL_HIGH 8
+
+extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
+extern void set_GPIO_IRQ_level(int gpio_nr, int level);
+extern void gpio_line_config(int line, int style);
+
+static inline int gpio_line_get(int line)
+{
+ return (((*IXP2000_GPIO_PLR) >> line) & 1);
+}
+
+static inline void gpio_line_set(int line, int value)
+{
+ if (value == IXP2000_GPIO_HIGH) {
+ ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
+ } else if (value == IXP2000_GPIO_LOW)
+ ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/hardware.h
+ *
+ * Hardware definitions for IXP2400/2800 based systems
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2001-2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+/*
+ * This needs to be platform-specific?
+ */
+#define PCIBIOS_MIN_IO 0x00000000
+#define PCIBIOS_MIN_MEM 0x00000000
+
+#include "ixp2000-regs.h" /* Chipset Registers */
+
+#define pcibios_assign_all_busses() 0
+
+/*
+ * Platform helper functions
+ */
+#include "platform.h"
+
+/*
+ * Platform-specific bits
+ */
+#include "enp2611.h" /* ENP-2611 */
+#include "ixdp2x00.h" /* IXDP2400/2800 */
+#include "ixdp2x01.h" /* IXDP2401/2801 */
+
+#endif /* _ASM_ARCH_HARDWARE_H__ */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixdp2000/io.h
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+#define __mem_pci(a) ((unsigned long)(a))
+
+/*
+ * Pick up VMALLOC_END
+ */
+#define ___io(p) ((unsigned long)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
+/*
+ * IXP200 does not do proper byte-lane conversion for PCI addresses,
+ * so we need to override standard functions.
+ */
+#define alignb(addr) ((addr & ~3) + (3 - (addr & 3)))
+#define alignw(addr) ((addr & ~2) + (2 - (addr & 2)))
+
+#define outb(v,p) __raw_writeb(v,alignb(___io(p)))
+#define outw(v,p) __raw_writew((v),alignw(___io(p)))
+#define outl(v,p) __raw_writel((v),___io(p))
+
+#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
+#define inw(p) \
+ ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
+#define inl(p) \
+ ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
+
+#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
+#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
+#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
+
+#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
+#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
+#define insl(p,d,l) __raw_readsl(___io(p),d,l)
+
+
+#ifdef CONFIG_ARCH_IXDP2X01
+/*
+ * This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
+ * of "I/O space" and is just direct mapped into a 32-bit-only addressable
+ * bus. The address space for this bus is such that we can't really easilly
+ * make it contigous to the PCI I/O address range, and it also does not
+ * need swapping like PCI addresses do (IXDP2x01 is a BE platform).
+ * B/C of this we can't use the standard in/out functions and need to
+ * runtime check if the incoming address is a PCI address or for
+ * the CS89x0.
+ */
+#undef inw
+#undef outw
+#undef insw
+#undef outsw
+
+#include <asm/mach-types.h>
+
+static inline void insw(u32 ptr, void *buf, int length)
+{
+ register volatile u32 *port = (volatile u32 *)ptr;
+
+ /*
+ * Is this cycle meant for the CS8900?
+ */
+ if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
+ ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
+ (port <= IXDP2X01_CS8900_VIRT_END))) {
+ u8 *buf8 = (u8*)buf;
+ register u32 tmp32;
+
+ do {
+ tmp32 = *port;
+ *buf8++ = (u8)tmp32;
+ *buf8++ = (u8)(tmp32 >> 8);
+ } while(--length);
+
+ return;
+ }
+
+ __raw_readsw(alignw(___io(ptr)),buf,length);
+}
+
+static inline void outsw(u32 ptr, void *buf, int length)
+{
+ register volatile u32 *port = (volatile u32 *)ptr;
+
+ /*
+ * Is this cycle meant for the CS8900?
+ */
+ if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
+ ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
+ (port <= IXDP2X01_CS8900_VIRT_END))) {
+ register u32 tmp32;
+ u8 *buf8 = (u8*)buf;
+ do {
+ tmp32 = *buf8++;
+ tmp32 |= (*buf8++) << 8;
+ *port = tmp32;
+ } while(--length);
+ return;
+ }
+
+ __raw_writesw(alignw(___io(ptr)),buf,length);
+}
+
+
+static inline u16 inw(u32 ptr)
+{
+ register volatile u32 *port = (volatile u32 *)ptr;
+
+ /*
+ * Is this cycle meant for the CS8900?
+ */
+ if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
+ ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
+ (port <= IXDP2X01_CS8900_VIRT_END))) {
+ return (u16)(*port);
+ }
+
+ return __raw_readw(alignw(___io(ptr)));
+}
+
+static inline void outw(u16 value, u32 ptr)
+{
+ register volatile u32 *port = (volatile u32 *)ptr;
+
+ if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
+ ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
+ (port <= IXDP2X01_CS8900_VIRT_END))) {
+ *port = value;
+ return;
+ }
+
+ __raw_writew((value),alignw(___io(ptr)));
+}
+#endif /* IXDP2x01 */
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/irq.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define fixup_irq(irq) (irq)
+
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/irqs.h
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IRQS_H
+#define _IRQS_H
+
+/*
+ * Do NOT add #ifdef MACHINE_FOO in here.
+ * Simpy add your machine IRQs here and increase NR_IRQS if needed to
+ * hold your machine's IRQ table.
+ */
+
+/*
+ * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
+ * register has those bit reserved. We just mark those interrupts
+ * as invalid and this allows us to do mask/unmask with a single
+ * shift operation instead of having to map the IRQ number to
+ * a HW IRQ number.
+ */
+#define IRQ_IXP2000_SWI 0 /* soft interrupt */
+#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
+#define IRQ_IXP2000_UART 2
+#define IRQ_IXP2000_GPIO 3
+#define IRQ_IXP2000_TIMER1 4
+#define IRQ_IXP2000_TIMER2 5
+#define IRQ_IXP2000_TIMER3 6
+#define IRQ_IXP2000_TIMER4 7
+#define IRQ_IXP2000_PMU 8
+#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
+#define IRQ_IXP2000_DMA1 10
+#define IRQ_IXP2000_DMA2 11
+#define IRQ_IXP2000_DMA3 12
+#define IRQ_IXP2000_PCI_DOORBELL 13
+#define IRQ_IXP2000_ME_ATTN 14
+#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
+#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
+#define IRQ_IXP2000_THDA1 17 /* thread 32-63A */
+#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
+#define IRQ_IXP2000_THDA3 19 /* thread 96-127A */
+#define IRQ_IXP2000_THDB0 24 /* thread 0-31 B */
+#define IRQ_IXP2000_THDB1 25 /* thread 32-63B */
+/* only 64 threads supported for IXP2400, rest or for IXP2800*/
+#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
+#define IRQ_IXP2000_THDB3 27 /* thread 96-127B */
+
+/* define generic GPIOs */
+#define IRQ_IXP2000_GPIO0 32
+#define IRQ_IXP2000_GPIO1 33
+#define IRQ_IXP2000_GPIO2 34
+#define IRQ_IXP2000_GPIO3 35
+#define IRQ_IXP2000_GPIO4 36
+#define IRQ_IXP2000_GPIO5 37
+#define IRQ_IXP2000_GPIO6 38
+#define IRQ_IXP2000_GPIO7 39
+
+/* split off the 2 PCI sources */
+#define IRQ_IXP2000_PCIA 40
+#define IRQ_IXP2000_PCIB 41
+
+/* Int sources from IRQ_ERROR_STATUS */
+#define IRQ_IXP2000_DRAM0_MIN_ERR 42
+#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
+#define IRQ_IXP2000_DRAM1_MIN_ERR 44
+#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
+#define IRQ_IXP2000_DRAM2_MIN_ERR 46
+#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
+#define IRQ_IXP2000_SRAM0_ERR 48
+#define IRQ_IXP2000_SRAM1_ERR 49
+#define IRQ_IXP2000_SRAM2_ERR 50
+#define IRQ_IXP2000_SRAM3_ERR 51
+#define IRQ_IXP2000_MEDIA_ERR 52
+#define IRQ_IXP2000_PCI_ERR 53
+#define IRQ_IXP2000_SP_INT 54
+
+#define NR_IXP2000_IRQS 55
+
+#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
+
+#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
+
+/*
+ * This allows for all the on-chip sources plus up to 32 CPLD based
+ * IRQs. Should be more than enough.
+ */
+#define IXP2000_BOARD_IRQS 32
+#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
+
+
+/*
+ * IXDP2400 specific IRQs
+ */
+#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
+#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
+#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
+#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
+
+#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
+#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
+
+/* IXDP2800 specific IRQs */
+#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
+#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
+
+#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
+#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
+
+/*
+ * IRQs on both IXDP2x01 boards
+ */
+#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
+#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
+#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
+#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
+#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
+#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
+#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
+#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
+#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
+#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
+#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
+#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
+#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
+
+#define IXDP2X01_VALID_IRQ_MASK ( \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
+
+/*
+ * IXDP2401 specific IRQs
+ */
+#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
+
+#define IXDP2401_VALID_IRQ_MASK ( \
+ IXDP2X01_VALID_IRQ_MASK | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
+
+/*
+ * IXDP2801-specific IRQs
+ */
+#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
+#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
+
+#define IXDP2801_VALID_IRQ_MASK ( \
+ IXDP2X01_VALID_IRQ_MASK | \
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
+ IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
+
+#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
+
+#endif /*_IRQS_H*/
--- /dev/null
+/*
+ * include/asm-arm/arch-ixp2000/ixdp2x00.h
+ *
+ * Register and other defines for IXDP2[48]00 platforms
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _IXDP2X00_H_
+#define _IXDP2X00_H_
+
+/*
+ * On board CPLD memory map
+ */
+#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
+#define IXDP2X00_VIRT_CPLD_BASE 0xfefdd000
+#define IXDP2X00_CPLD_SIZE 0x00001000
+
+
+#define IXDP2X00_CPLD_REG(x) \
+ (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
+
+/*
+ * IXDP2400 CPLD registers
+ */
+#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0)
+#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4)
+#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8)
+#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc)
+#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10)
+#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14)
+#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18)
+#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48)
+
+/*
+ * IXDP2800 CPLD registers
+ */
+#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0)
+#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140)
+
+
+#define IXDP2X00_GPIO_I2C_ENABLE 0x02
+#define IXDP2X00_GPIO_SCL 0x07
+#define IXDP2X00_GPIO_SDA 0x06
+
+/*
+ * PCI devfns for on-board devices. We need these to be able to
+ * properly translte IRQs and for device removal.
+ */
+#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */
+#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */
+#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */
+#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
+
+#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */
+#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */
+#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
+
+#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */
+#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */
+#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */
+#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */
+#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */
+
+#ifndef __ASSEMBLY__
+/*
+ * Master NPU will always have flash and be PCI master.
+ * Slave NPU may or may not have flash but will never be PCI master.
+ */
+static inline unsigned int ixdp2x00_master_npu(void)
+{
+ return ((ixp2000_has_flash()) && (ixp2000_is_pcimaster()));
+}
+
+/*
+ * Helper functions used by ixdp2400 and ixdp2800 specific code
+ */
+void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
+void ixdp2x00_slave_pci_postinit(void);
+void ixdp2x00_init_machine(void);
+void ixdp2x00_map_io(void);
+
+#endif
+
+#endif /*_IXDP2X00_H_ */
--- /dev/null
+/*
+ * include/asm/arch/ixdp2x01.h
+ *
+ * Platform definitions for IXDP2X01 && IXDP2801 systems
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc.
+ *
+ * Based on original code Copyright (c) 2002-2003 Intel Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __IXDP2X01_H__
+#define __IXDP2X01_H__
+
+#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
+#define IXDP2X01_VIRT_CPLD_BASE 0xfefdd000
+#define IXDP2X01_CPLD_REGION_SIZE 0x1000
+
+#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile u32*)(IXDP2X01_VIRT_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
+
+#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
+#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
+
+#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
+#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
+
+#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
+#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
+
+#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
+#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
+#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
+#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
+#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
+#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
+
+#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
+
+#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
+#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
+#define IXDP2X01_FLASH_WINDOW_BITS 25
+#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
+#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
+
+#define IXDP2X01_UART_CLK 1843200
+
+#endif /* __IXDP2x01_H__ */
--- /dev/null
+/*
+ * include/asm-arm/arch-ixp2000/ixp2000-regs.h
+ *
+ * Chipset register definitions for IXP2400/2800 based systems.
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _IXP2000_REGS_H_
+#define _IXP2000_REGS_H_
+
+/*
+ * Static I/O regions. The manual defines each region as being several
+ * MB in size, but all the registers are within the first 4K, so there's
+ * no purpose in mapping the whole region in.
+ */
+#define IXP2000_SLOWPORT_CSR_PHYS_BASE 0xc0080000
+#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfefff000
+#define IXP2000_SLOWPORT_CSR_SIZE 0x1000
+
+#define IXP2000_GLOBAL_REG_PHYS_BASE 0xc0004000
+#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfeffe000
+#define IXP2000_GLOBAL_REG_SIZE 0x1000
+
+#define IXP2000_UART_PHYS_BASE 0xc0030000
+#define IXP2000_UART_VIRT_BASE 0xfef30000
+#define IXP2000_UART_SIZE 0x1000
+
+#define IXP2000_TIMER_PHYS_BASE 0xc0020000
+#define IXP2000_TIMER_VIRT_BASE 0xfeffc000
+#define IXP2000_TIMER_SIZE 0x1000
+
+#define IXP2000_GPIO_PHYS_BASE 0xc0010000
+#define IXP2000_GPIO_VIRT_BASE 0xfeffb000
+#define IXP2000_GPIO_SIZE 0x1000
+
+#define IXP2000_INTCTL_PHYS_BASE 0xd6000000
+#define IXP2000_INTCTL_VIRT_BASE 0xfeffa000
+#define IXP2000_INTCTL_SIZE 0x01000
+
+#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
+#define IXP2000_PCI_CREG_VIRT_BASE 0xfeff0000
+#define IXP2000_PCI_CREG_SIZE 0x1000
+
+#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
+#define IXP2000_PCI_CSR_VIRT_BASE 0xfefde000
+#define IXP2000_PCI_CSR_SIZE 0x1000
+
+#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
+#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
+#define IXP2000_PCI_IO_SIZE 0x01000000
+
+#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
+#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
+#define IXP2000_PCI_CFG0_SIZE 0x01000000
+
+#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
+#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
+#define IXP2000_PCI_CFG1_SIZE 0x01000000
+
+
+/*
+ * Timers
+ */
+#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
+/* Timer control */
+#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
+#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
+#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
+#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
+/* Store initial value */
+#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
+#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
+#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
+#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
+/* Read current value */
+#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
+#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
+#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
+#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
+/* Clear associated timer interrupt */
+#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
+#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
+#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
+#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
+/* Timer watchdog enable for T4 */
+#define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
+
+#define WDT_ENABLE 0x00000001
+#define TIMER_DIVIDER_256 0x00000008
+#define TIMER_ENABLE 0x00000080
+
+/*
+ * Interrupt controller registers
+ */
+#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
+#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
+#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
+#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
+#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
+#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
+#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
+#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
+#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
+#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
+
+/*
+ * Mask of valid IRQs in the 32-bit IRQ register. We use
+ * this to mark certain IRQs as being in-valid.
+ */
+#define IXP2000_VALID_IRQ_MASK 0x0f0fffff
+
+/*
+ * PCI config register access from core
+ */
+#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
+#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
+#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
+#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
+#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
+
+/*
+ * PCI CSRs
+ */
+#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
+
+/*
+ * PCI outbound interrupts
+ */
+#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
+#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
+/*
+ * PCI communications
+ */
+#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
+#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
+#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
+#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
+#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
+#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
+#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
+#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
+
+/*
+ * DMA engines
+ */
+#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
+#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
+#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
+#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
+#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
+#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
+#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
+#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
+#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
+#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
+#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
+#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
+#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
+#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
+#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
+#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
+#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
+#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
+#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
+/*
+ * Size masks for BARs
+ */
+#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
+#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
+/*
+ * Control and uEngine related
+ */
+#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
+#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
+#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
+#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
+#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
+#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
+/*
+ * Inbound PCI interrupt control
+ */
+#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
+#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
+
+#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
+#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
+
+/* These are from the IRQ register in the PCI ISR register */
+#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
+#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
+#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
+#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
+#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */
+
+#define IXP2000_PCI_RST_REL (1 << 2)
+#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
+#define CFG_PCI_BOOT_HOST (1 << 2)
+#define CFG_BOOT_PROM (1 << 1)
+
+/*
+ * SlowPort CSRs
+ *
+ * The slowport is used to access things like flash, SONET framer control
+ * ports, slave microprocessors, CPLDs, and others of chip memory mapped
+ * peripherals.
+ */
+#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
+
+#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
+#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
+#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
+#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
+#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
+#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
+#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
+#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
+#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
+#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
+#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
+
+/*
+ * CCR values.
+ * The CCR configures the clock division for the slowport interface.
+ */
+#define SLOWPORT_CCR_DIV_1 0x00
+#define SLOWPORT_CCR_DIV_2 0x01
+#define SLOWPORT_CCR_DIV_4 0x02
+#define SLOWPORT_CCR_DIV_6 0x03
+#define SLOWPORT_CCR_DIV_8 0x04
+#define SLOWPORT_CCR_DIV_10 0x05
+#define SLOWPORT_CCR_DIV_12 0x06
+#define SLOWPORT_CCR_DIV_14 0x07
+#define SLOWPORT_CCR_DIV_16 0x08
+#define SLOWPORT_CCR_DIV_18 0x09
+#define SLOWPORT_CCR_DIV_20 0x0a
+#define SLOWPORT_CCR_DIV_22 0x0b
+#define SLOWPORT_CCR_DIV_24 0x0c
+#define SLOWPORT_CCR_DIV_26 0x0d
+#define SLOWPORT_CCR_DIV_28 0x0e
+#define SLOWPORT_CCR_DIV_30 0x0f
+
+/*
+ * PCR values. PCR configure the mode of the interfac3
+ */
+#define SLOWPORT_MODE_FLASH 0x00
+#define SLOWPORT_MODE_LUCENT 0x01
+#define SLOWPORT_MODE_PMC_SIERRA 0x02
+#define SLOWPORT_MODE_INTEL_UP 0x03
+#define SLOWPORT_MODE_MOTOROLA_UP 0x04
+
+/*
+ * ADC values. Defines data and address bus widths
+ */
+#define SLOWPORT_ADDR_WIDTH_8 0x00
+#define SLOWPORT_ADDR_WIDTH_16 0x01
+#define SLOWPORT_ADDR_WIDTH_24 0x02
+#define SLOWPORT_ADDR_WIDTH_32 0x03
+#define SLOWPORT_DATA_WIDTH_8 0x00
+#define SLOWPORT_DATA_WIDTH_16 0x10
+#define SLOWPORT_DATA_WIDTH_24 0x20
+#define SLOWPORT_DATA_WIDTH_32 0x30
+
+/*
+ * Masks and shifts for various fields in the WTC and RTC registers
+ */
+#define SLOWPORT_WRTC_MASK_HD 0x0003
+#define SLOWPORT_WRTC_MASK_SU 0x003c
+#define SLOWPORT_WRTC_MASK_PW 0x03c0
+
+#define SLOWPORT_WRTC_SHIFT_HD 0x00
+#define SLOWPORT_WRTC_SHIFT_SU 0x02
+#define SLOWPORT_WRTC_SHFIT_PW 0x06
+
+
+/*
+ * GPIO registers & GPIO interface
+ */
+#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
+#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
+#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
+#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
+#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
+#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
+#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
+#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
+#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
+#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
+#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
+#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
+#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
+#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
+#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
+#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
+#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
+#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
+
+/*
+ * "Global" registers...whatever that's supposed to mean.
+ */
+#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
+#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
+
+#define IXP2000_PROD_ID GLOBAL_REG(0x00)
+
+#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
+#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
+#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
+#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
+#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
+#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
+#define IXP2000_MAJ_REV_MASK 0x000000F0
+#define IXP2000_MIN_REV_MASK 0x0000000F
+#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
+
+#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
+#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
+#define IXP2000_RESET0 GLOBAL_REG(0x0c)
+#define IXP2000_RESET1 GLOBAL_REG(0x10)
+#define IXP2000_CCR GLOBAL_REG(0x14)
+#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
+
+#define RSTALL (1 << 16)
+#define WDT_RESET_ENABLE 0x01000000
+
+
+#endif /* _IXP2000_H_ */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/memory.h
+ *
+ * Copyright (c) 2002 Intel Corp.
+ * Copyright (c) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET (0x00000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ * address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ * to an address that the kernel can use.
+ */
+#include <asm/arch/ixp2000-regs.h>
+
+#define __virt_to_bus(v) \
+ (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
+
+#define __bus_to_virt(b) \
+ __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
+
+#endif
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/param.h
+ */
--- /dev/null
+/*
+ * include/asm-arh/arch-ixp2000/platform.h
+ *
+ * Various bits of code used by platform-level code.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * The IXP2400 B0 silicon contains an errata that causes writes to
+ * on-chip I/O register to not complete fully. What this means is
+ * that if you have a write to on-chip I/O followed by a back-to-back
+ * read or write, the first write will happend twice. OR...if it's
+ * not a back-to-back trasaction, the read or write will generate
+ * incorrect data.
+ *
+ * The official work around for this is to set the on-chip I/O regions
+ * as XCB=101 and then force a read-back from the register.
+ *
+ */
+#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
+
+#include <asm/system.h> /* Pickup local_irq_ functions */
+
+static inline void ixp2000_reg_write(volatile unsigned long *reg, unsigned long val)
+{
+ volatile unsigned long dummy;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ *reg = val;
+ barrier();
+ dummy = *reg;
+ local_irq_restore(flags);
+}
+#else
+#define ixp2000_reg_write(reg, val) (*reg = val)
+#endif /* IXDP2400 || IXDP2401 */
+
+/*
+ * Boards may multiplex different devices on the 2nd channel of
+ * the slowport interface that each need different configuration
+ * settings. For example, the IXDP2400 uses channel 2 on the interface
+ * to access the CPLD, the switch fabric card, and te media card. Each
+ * one needs a different mode so drivers must save/restore the mode
+ * before and after each operation.
+ *
+ * acquire_slowport(&your_config);
+ * ...
+ * do slowport operations
+ * ...
+ * release_slowport();
+ *
+ * Note that while you have the slowport, you are holding a spinlock,
+ * so your code should be written as if you explicitly acquired a lock.
+ *
+ * The configuration only affects device 2 on the slowport, so the
+ * MTD map driver does not acquire/release the slowport.
+ */
+struct slowport_cfg {
+ unsigned long CCR; /* Clock divide */
+ unsigned long WTC; /* Write Timing Control */
+ unsigned long RTC; /* Read Timing Control */
+ unsigned long PCR; /* Protocol Control Register */
+ unsigned long ADC; /* Address/Data Width Control */
+};
+
+
+void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
+void ixp2000_release_slowport(struct slowport_cfg *);
+
+/*
+ * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires
+ * tweaking of addresses in the MTD driver.
+ */
+static inline unsigned ixp2000_has_broken_slowport(void)
+{
+ unsigned long id = *IXP2000_PROD_ID;
+ unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
+ IXP2000_MIN_PROD_TYPE_MASK);
+ return (((id_prod ==
+ /* fixed in IXP2400-B0 */
+ (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+ IXP2000_MIN_PROD_TYPE_IXP2400)) &&
+ ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
+ ((id_prod ==
+ /* fixed in IXP2800-B0 */
+ (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+ IXP2000_MIN_PROD_TYPE_IXP2800)) &&
+ ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
+ ((id_prod ==
+ /* fixed in IXP2850-B0 */
+ (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+ IXP2000_MIN_PROD_TYPE_IXP2850)) &&
+ ((id & IXP2000_MAJ_REV_MASK) == 0)));
+}
+
+static inline unsigned int ixp2000_has_flash(void)
+{
+ return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
+}
+
+static inline unsigned int ixp2000_is_pcimaster(void)
+{
+ return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
+}
+
+void ixp2000_map_io(void);
+void ixp2000_init_irq(void);
+void ixp2000_init_time(unsigned long);
+
+struct pci_sys_data;
+
+void ixp2000_pci_preinit(void);
+int ixp2000_pci_setup(int, struct pci_sys_data*);
+struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
+int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
+int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
+
+/*
+ * Several of the IXP2000 systems have banked flash so we need to extend the
+ * flash_platform_data structure with some private pointers
+ */
+struct ixp2000_flash_data {
+ struct flash_platform_data *platform_data;
+ int nr_banks;
+ unsigned long (*bank_setup)(unsigned long);
+};
+
+/*
+ * GPIO helper functions
+ */
+#define GPIO_IN 0
+#define GPIO_OUT 1
+
+extern void gpio_line_config(int line, int style);
+
+static inline int gpio_line_get(int line)
+{
+ return (((*IXP2000_GPIO_PLR) >> line) & 1);
+}
+
+static inline void gpio_line_set(int line, int value)
+{
+ if (value)
+ ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
+ else
+ ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
+}
+
+struct ixp2000_i2c_pins {
+ unsigned long sda_pin;
+ unsigned long scl_pin;
+};
+
+#endif /* !__ASSEMBLY__ */
--- /dev/null
+/*
+ * include/asm-arm/arch-ixp2000/serial.h
+ *
+ * Serial port defn for ixp2000 based systems.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (c) 2002-2004 MontaVista Software, Inc.
+ *
+ * We do not register serial ports staticly b/c there is no easy way
+ * to autodetect an XScale port. Instead we register them at runtime
+ * via early_serial_init().
+ */
+
+#ifndef _ARCH_SERIAL_H_
+#define _ARCH_SERIAL_H_
+
+#define BASE_BAUD (50000000/ 16)
+
+/*
+ * Currently no IXP2000 systems with > 3 serial ports.
+ * If you add a system that does, just up this.
+ */
+#define STD_SERIAL_PORT_DEFNS
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif // __ARCH_SERIAL_H_
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2400/system.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+ cli();
+
+ if (machine_is_ixdp2401() || machine_is_ixdp2801()) {
+ *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN);
+ *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
+ }
+
+ /*
+ * We do a reset all if we are PCI master. We could be a slave and we
+ * don't want to do anything funky on the PCI bus.
+ */
+ if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
+ *(IXP2000_RESET0) |= (RSTALL);
+ }
+}
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/timex.h
+ *
+ * IXP2000 architecture timex specifications
+ */
+
+
+/*
+ * Default clock is 50MHz APB, but platform code can override this
+ */
+#define CLOCK_TICK_RATE 50000000
+
+
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/uncompress.h
+ *
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/serial_reg.h>
+
+#define UART_BASE 0xc0030000
+
+#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x))
+
+#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */
+#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/
+#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/
+#define UARTIER PHYS(0x04) /* Interrupt enable reg */
+#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/
+#define UARTLCR PHYS(0x0c) /* Control reg */
+#define UARTSR PHYS(0x14) /* Status reg */
+
+
+static __inline__ void putc(char c)
+{
+ int j = 0x1000;
+
+ while (--j && !(*UARTSR & UART_LSR_THRE));
+ *UARTDR = c;
+}
+
+static void putstr(const char *s)
+{
+ while (*s)
+ {
+ putc(*s);
+ if (*s == '\n')
+ putc('\r');
+ s++;
+ }
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-ixp2000/vmalloc.h
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Copyright 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET (8*1024*1024)
+#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END 0xfb000000
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-omap/gpio.h
+ *
+ * Defines for Multi-Channel Buffered Serial Port
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_OMAP_MCBSP_H
+#define __ASM_ARCH_OMAP_MCBSP_H
+
+#include <asm/arch/hardware.h>
+
+#define OMAP730_MCBSP1_BASE 0xfffb1000
+#define OMAP730_MCBSP2_BASE 0xfffb1800
+
+#define OMAP1510_MCBSP1_BASE 0xe1011000
+#define OMAP1510_MCBSP2_BASE 0xfffb1000
+#define OMAP1510_MCBSP3_BASE 0xe1017000
+
+#define OMAP1610_MCBSP1_BASE 0xe1011800
+#define OMAP1610_MCBSP2_BASE 0xfffb1000
+#define OMAP1610_MCBSP3_BASE 0xe1017000
+
+#define OMAP_MCBSP_REG_DRR2 0x00
+#define OMAP_MCBSP_REG_DRR1 0x02
+#define OMAP_MCBSP_REG_DXR2 0x04
+#define OMAP_MCBSP_REG_DXR1 0x06
+#define OMAP_MCBSP_REG_SPCR2 0x08
+#define OMAP_MCBSP_REG_SPCR1 0x0a
+#define OMAP_MCBSP_REG_RCR2 0x0c
+#define OMAP_MCBSP_REG_RCR1 0x0e
+#define OMAP_MCBSP_REG_XCR2 0x10
+#define OMAP_MCBSP_REG_XCR1 0x12
+#define OMAP_MCBSP_REG_SRGR2 0x14
+#define OMAP_MCBSP_REG_SRGR1 0x16
+#define OMAP_MCBSP_REG_MCR2 0x18
+#define OMAP_MCBSP_REG_MCR1 0x1a
+#define OMAP_MCBSP_REG_RCERA 0x1c
+#define OMAP_MCBSP_REG_RCERB 0x1e
+#define OMAP_MCBSP_REG_XCERA 0x20
+#define OMAP_MCBSP_REG_XCERB 0x22
+#define OMAP_MCBSP_REG_PCR0 0x24
+#define OMAP_MCBSP_REG_RCERC 0x26
+#define OMAP_MCBSP_REG_RCERD 0x28
+#define OMAP_MCBSP_REG_XCERC 0x2A
+#define OMAP_MCBSP_REG_XCERD 0x2C
+#define OMAP_MCBSP_REG_RCERE 0x2E
+#define OMAP_MCBSP_REG_RCERF 0x30
+#define OMAP_MCBSP_REG_XCERE 0x32
+#define OMAP_MCBSP_REG_XCERF 0x34
+#define OMAP_MCBSP_REG_RCERG 0x36
+#define OMAP_MCBSP_REG_RCERH 0x38
+#define OMAP_MCBSP_REG_XCERG 0x3A
+#define OMAP_MCBSP_REG_XCERH 0x3C
+
+#define OMAP_MAX_MCBSP_COUNT 3
+
+#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
+#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
+
+/************************** McBSP SPCR1 bit definitions ***********************/
+#define RRST 0x0001
+#define RRDY 0x0002
+#define RFULL 0x0004
+#define RSYNC_ERR 0x0008
+#define RINTM(value) ((value)<<4) /* bits 4:5 */
+#define ABIS 0x0040
+#define DXENA 0x0080
+#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
+#define RJUST(value) ((value)<<13) /* bits 13:14 */
+#define DLB 0x8000
+
+/************************** McBSP SPCR2 bit definitions ***********************/
+#define XRST 0x0001
+#define XRDY 0x0002
+#define XEMPTY 0x0004
+#define XSYNC_ERR 0x0008
+#define XINTM(value) ((value)<<4) /* bits 4:5 */
+#define GRST 0x0040
+#define FRST 0x0080
+#define SOFT 0x0100
+#define FREE 0x0200
+
+/************************** McBSP PCR bit definitions *************************/
+#define CLKRP 0x0001
+#define CLKXP 0x0002
+#define FSRP 0x0004
+#define FSXP 0x0008
+#define DR_STAT 0x0010
+#define DX_STAT 0x0020
+#define CLKS_STAT 0x0040
+#define SCLKME 0x0080
+#define CLKRM 0x0100
+#define CLKXM 0x0200
+#define FSRM 0x0400
+#define FSXM 0x0800
+#define RIOEN 0x1000
+#define XIOEN 0x2000
+#define IDLE_EN 0x4000
+
+/************************** McBSP RCR1 bit definitions ************************/
+#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
+#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
+
+/************************** McBSP XCR1 bit definitions ************************/
+#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
+#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
+
+/*************************** McBSP RCR2 bit definitions ***********************/
+#define RDATDLY(value) (value) /* Bits 0:1 */
+#define RFIG 0x0004
+#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
+#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
+#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
+#define RPHASE 0x8000
+
+/*************************** McBSP XCR2 bit definitions ***********************/
+#define XDATDLY(value) (value) /* Bits 0:1 */
+#define XFIG 0x0004
+#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
+#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
+#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
+#define XPHASE 0x8000
+
+/************************* McBSP SRGR1 bit definitions ************************/
+#define CLKGDV(value) (value) /* Bits 0:7 */
+#define FWID(value) ((value)<<8) /* Bits 8:15 */
+
+/************************* McBSP SRGR2 bit definitions ************************/
+#define FPER(value) (value) /* Bits 0:11 */
+#define FSGM 0x1000
+#define CLKSM 0x2000
+#define CLKSP 0x4000
+#define GSYNC 0x8000
+
+/************************* McBSP MCR1 bit definitions *************************/
+#define RMCM 0x0001
+#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
+#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
+#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
+
+/************************* McBSP MCR2 bit definitions *************************/
+#define XMCM(value) (value) /* Bits 0:1 */
+#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
+#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
+#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
+
+
+/* we don't do multichannel for now */
+struct omap_mcbsp_reg_cfg {
+ u16 spcr2;
+ u16 spcr1;
+ u16 rcr2;
+ u16 rcr1;
+ u16 xcr2;
+ u16 xcr1;
+ u16 srgr2;
+ u16 srgr1;
+ u16 mcr2;
+ u16 mcr1;
+ u16 pcr0;
+ u16 rcerc;
+ u16 rcerd;
+ u16 xcerc;
+ u16 xcerd;
+ u16 rcere;
+ u16 rcerf;
+ u16 xcere;
+ u16 xcerf;
+ u16 rcerg;
+ u16 rcerh;
+ u16 xcerg;
+ u16 xcerh;
+};
+
+typedef enum {
+ OMAP_MCBSP1 = 0,
+ OMAP_MCBSP2,
+ OMAP_MCBSP3,
+} omap_mcbsp_id;
+
+typedef enum {
+ OMAP_MCBSP_WORD_8 = 0,
+ OMAP_MCBSP_WORD_12,
+ OMAP_MCBSP_WORD_16,
+ OMAP_MCBSP_WORD_20,
+ OMAP_MCBSP_WORD_24,
+ OMAP_MCBSP_WORD_32,
+} omap_mcbsp_word_length;
+
+typedef enum {
+ OMAP_MCBSP_CLK_RISING = 0,
+ OMAP_MCBSP_CLK_FALLING,
+} omap_mcbsp_clk_polarity;
+
+typedef enum {
+ OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
+ OMAP_MCBSP_FS_ACTIVE_LOW,
+} omap_mcbsp_fs_polarity;
+
+typedef enum {
+ OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
+ OMAP_MCBSP_CLK_STP_MODE_DELAY,
+} omap_mcbsp_clk_stp_mode;
+
+
+/******* SPI specific mode **********/
+typedef enum {
+ OMAP_MCBSP_SPI_MASTER = 0,
+ OMAP_MCBSP_SPI_SLAVE,
+} omap_mcbsp_spi_mode;
+
+struct omap_mcbsp_spi_cfg {
+ omap_mcbsp_spi_mode spi_mode;
+ omap_mcbsp_clk_polarity rx_clock_polarity;
+ omap_mcbsp_clk_polarity tx_clock_polarity;
+ omap_mcbsp_fs_polarity fsx_polarity;
+ u8 clk_div;
+ omap_mcbsp_clk_stp_mode clk_stp_mode;
+ omap_mcbsp_word_length word_length;
+};
+
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+int omap_mcbsp_request(unsigned int id);
+void omap_mcbsp_free(unsigned int id);
+void omap_mcbsp_start(unsigned int id);
+void omap_mcbsp_stop(unsigned int id);
+void omap_mcbsp_xmit_word(unsigned int id, u32 word);
+u32 omap_mcbsp_recv_word(unsigned int id);
+
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+
+/* SPI specific API */
+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
+
+#endif
--- /dev/null
+/* linux/include/asm-arm/arch-omap/tps65010.h
+ *
+ * Functions to access TPS65010 power management device.
+ *
+ * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_TPS65010_H
+#define __ASM_ARCH_TPS65010_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Macros used by exported functions
+ * ----------------------------------------------------------------------------
+ */
+
+#define LED1 1
+#define LED2 2
+#define OFF 0
+#define ON 1
+#define BLINK 2
+#define GPIO1 1
+#define GPIO2 2
+#define GPIO3 3
+#define GPIO4 4
+#define LOW 0
+#define HIGH 1
+
+/*
+ * ----------------------------------------------------------------------------
+ * Exported functions
+ * ----------------------------------------------------------------------------
+ */
+
+/* Draw from VBUS:
+ * 0 mA -- DON'T DRAW (might supply power instead)
+ * 100 mA -- usb unit load (slowest charge rate)
+ * 500 mA -- usb high power (fast battery charge)
+ */
+extern int tps65010_set_vbus_draw(unsigned mA);
+
+/* tps65010_set_gpio_out_value parameter:
+ * gpio: GPIO1, GPIO2, GPIO3 or GPIO4
+ * value: LOW or HIGH
+ */
+extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
+
+/* tps65010_set_led parameter:
+ * led: LED1 or LED2
+ * mode: ON, OFF or BLINK
+ */
+extern int tps65010_set_led(unsigned led, unsigned mode);
+
+/* tps65010_set_low_pwr parameter:
+ * mode: ON or OFF
+ */
+extern int tps65010_set_low_pwr(unsigned mode);
+
+#endif /* __ASM_ARCH_TPS65010_H */
+
--- /dev/null
+// include/asm-arm/mach-omap/usb.h
+
+#ifndef __ASM_ARCH_OMAP_USB_H
+#define __ASM_ARCH_OMAP_USB_H
+
+#include <asm/arch/board.h>
+
+/*-------------------------------------------------------------------------*/
+
+#define OTG_BASE 0xfffb0400
+#define UDC_BASE 0xfffb4000
+#define OMAP_OHCI_BASE 0xfffba000
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * OTG and transceiver registers, for OMAPs starting with ARM926
+ */
+#define OTG_REG32(offset) __REG32(OTG_BASE + (offset))
+#define OTG_REG16(offset) __REG16(OTG_BASE + (offset))
+
+#define OTG_REV_REG OTG_REG32(0x00)
+#define OTG_SYSCON_1_REG OTG_REG32(0x04)
+# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
+# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
+# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
+# define OTG_IDLE_EN (1 << 15)
+# define HST_IDLE_EN (1 << 14)
+# define DEV_IDLE_EN (1 << 13)
+# define OTG_RESET_DONE (1 << 2)
+#define OTG_SYSCON_2_REG OTG_REG32(0x08)
+# define OTG_EN (1 << 31)
+# define USBX_SYNCHRO (1 << 30)
+# define OTG_MST16 (1 << 29)
+# define SRP_GPDATA (1 << 28)
+# define SRP_GPDVBUS (1 << 27)
+# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
+# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
+# define B_ASE_BRST(w) (((w)>>16)&0x07)
+# define SRP_DPW (1 << 14)
+# define SRP_DATA (1 << 13)
+# define SRP_VBUS (1 << 12)
+# define OTG_PADEN (1 << 10)
+# define HMC_PADEN (1 << 9)
+# define UHOST_EN (1 << 8)
+# define HMC_TLLSPEED (1 << 7)
+# define HMC_TLLATTACH (1 << 6)
+# define OTG_HMC(w) (((w)>>0)&0x3f)
+#define OTG_CTRL_REG OTG_REG32(0x0c)
+# define OTG_ASESSVLD (1 << 20)
+# define OTG_BSESSEND (1 << 19)
+# define OTG_BSESSVLD (1 << 18)
+# define OTG_VBUSVLD (1 << 17)
+# define OTG_ID (1 << 16)
+# define OTG_DRIVER_SEL (1 << 15)
+# define OTG_A_SETB_HNPEN (1 << 12)
+# define OTG_A_BUSREQ (1 << 11)
+# define OTG_B_HNPEN (1 << 9)
+# define OTG_B_BUSREQ (1 << 8)
+# define OTG_BUSDROP (1 << 7)
+# define OTG_PULLDOWN (1 << 5)
+# define OTG_PULLUP (1 << 4)
+# define OTG_DRV_VBUS (1 << 3)
+# define OTG_PD_VBUS (1 << 2)
+# define OTG_PU_VBUS (1 << 1)
+# define OTG_PU_ID (1 << 0)
+#define OTG_IRQ_EN_REG OTG_REG16(0x10)
+# define DRIVER_SWITCH (1 << 15)
+# define A_VBUS_ERR (1 << 13)
+# define A_REQ_TMROUT (1 << 12)
+# define A_SRP_DETECT (1 << 11)
+# define B_HNP_FAIL (1 << 10)
+# define B_SRP_TMROUT (1 << 9)
+# define B_SRP_DONE (1 << 8)
+# define B_SRP_STARTED (1 << 7)
+# define OPRT_CHG (1 << 0)
+#define OTG_IRQ_SRC_REG OTG_REG16(0x14)
+ // same bits as in IRQ_EN
+#define OTG_OUTCTRL_REG OTG_REG16(0x18)
+# define OTGVPD (1 << 14)
+# define OTGVPU (1 << 13)
+# define OTGPUID (1 << 12)
+# define USB2VDR (1 << 10)
+# define USB2PDEN (1 << 9)
+# define USB2PUEN (1 << 8)
+# define USB1VDR (1 << 6)
+# define USB1PDEN (1 << 5)
+# define USB1PUEN (1 << 4)
+# define USB0VDR (1 << 2)
+# define USB0PDEN (1 << 1)
+# define USB0PUEN (1 << 0)
+#define OTG_TEST_REG OTG_REG16(0x20)
+#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc)
+
+/*-------------------------------------------------------------------------*/
+
+#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064)
+# define CONF_USB2_UNI_R (1 << 8)
+# define CONF_USB1_UNI_R (1 << 7)
+# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
+# define CONF_USB0_ISOLATE_R (1 << 3)
+# define CONF_USB_PWRDN_DM_R (1 << 2)
+# define CONF_USB_PWRDN_DP_R (1 << 1)
+
+
+
+
+#endif /* __ASM_ARCH_OMAP_USB_H */
--- /dev/null
+#ifndef ASMARM_ARCH_MMC_H
+#define ASMARM_ARCH_MMC_H
+
+#include <linux/mmc/protocol.h>
+#include <linux/interrupt.h>
+
+struct device;
+struct mmc_host;
+
+struct pxamci_platform_data {
+ unsigned int ocr_mask; /* available voltages */
+ int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
+ void (*setpower)(struct device *, unsigned int);
+ void (*exit)(struct device *, void *);
+};
+
+extern void pxa_set_mci_info(struct pxamci_platform_data *info);
+
+#endif
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/nand.h
+ *
+ * (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - NAND device controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ * 23-Sep-2004 BJD Created file
+*/
+
+/* struct s3c2410_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name = name of set (optional)
+ * nr_map = map for low-layer logical to physical chip numbers (option)
+ * partitions = mtd partition list
+*/
+
+struct s3c2410_nand_set {
+ int nr_chips;
+ int nr_partitions;
+ char *name;
+ int *nr_map;
+ struct mtd_partition *partitions;
+};
+
+struct s3c2410_platform_nand {
+ /* timing information for controller, all times in nanoseconds */
+
+ int tacls; /* time for active CLE/ALE to nWE/nOE */
+ int twrph0; /* active time for nWE/nOE */
+ int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
+
+ int nr_sets;
+ struct s3c2410_nand_set *sets;
+
+ void (*select_chip)(struct s3c2410_nand_set *,
+ int chip);
+};
+
--- /dev/null
+/* linux/include/asm/hardware/s3c2410/regs-dsc.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 Signal Drive Strength Control
+ *
+ * Changelog:
+ * 11-Aug-2004 BJD Created file
+ * 25-Aug-2004 BJD Added the _SELECT_* defs for using with functions
+*/
+
+
+#ifndef __ASM_ARCH_REGS_DSC_H
+#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
+
+#ifdef CONFIG_CPU_S3C2440
+
+#define S3C2440_DSC0 S3C2410_GPIOREG(0xc0)
+#define S3C2440_DSC1 S3C2410_GPIOREG(0xc4)
+
+#define S3C2440_SELECT_DSC0 (0)
+#define S3C2440_SELECT_DSC1 (1<<31)
+
+#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
+
+#define S3C2440_DSC0_ENABLE (1<<31)
+
+#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
+#define S3C2440_DSC0_ADDR_12mA (0<<8)
+#define S3C2440_DSC0_ADDR_10mA (1<<8)
+#define S3C2440_DSC0_ADDR_8mA (2<<8)
+#define S3C2440_DSC0_ADDR_6mA (3<<8)
+#define S3C2440_DSC0_ADDR_MASK (3<<8)
+
+/* D24..D31 */
+#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6)
+#define S3C2440_DSC0_DATA3_12mA (0<<6)
+#define S3C2440_DSC0_DATA3_10mA (1<<6)
+#define S3C2440_DSC0_DATA3_8mA (2<<6)
+#define S3C2440_DSC0_DATA3_6mA (3<<6)
+#define S3C2440_DSC0_DATA3_MASK (3<<6)
+
+/* D16..D23 */
+#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4)
+#define S3C2440_DSC0_DATA2_12mA (0<<4)
+#define S3C2440_DSC0_DATA2_10mA (1<<4)
+#define S3C2440_DSC0_DATA2_8mA (2<<4)
+#define S3C2440_DSC0_DATA2_6mA (3<<4)
+#define S3C2440_DSC0_DATA2_MASK (3<<4)
+
+/* D8..D15 */
+#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2)
+#define S3C2440_DSC0_DATA1_12mA (0<<2)
+#define S3C2440_DSC0_DATA1_10mA (1<<2)
+#define S3C2440_DSC0_DATA1_8mA (2<<2)
+#define S3C2440_DSC0_DATA1_6mA (3<<2)
+#define S3C2440_DSC0_DATA1_MASK (3<<2)
+
+/* D0..D7 */
+#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0)
+#define S3C2440_DSC0_DATA0_12mA (0<<0)
+#define S3C2440_DSC0_DATA0_10mA (1<<0)
+#define S3C2440_DSC0_DATA0_8mA (2<<0)
+#define S3C2440_DSC0_DATA0_6mA (3<<0)
+#define S3C2440_DSC0_DATA0_MASK (3<<0)
+
+#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 28)
+#define S3C2440_DSC1_SCK0_12mA (0<<28)
+#define S3C2440_DSC1_SCK0_10mA (1<<28)
+#define S3C2440_DSC1_SCK0_8mA (2<<28)
+#define S3C2440_DSC1_SCK0_6mA (3<<28)
+#define S3C2440_DSC1_SCK0_MASK (3<<28)
+
+#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 26)
+#define S3C2440_DSC1_SCK1_12mA (0<<26)
+#define S3C2440_DSC1_SCK1_10mA (1<<26)
+#define S3C2440_DSC1_SCK1_8mA (2<<26)
+#define S3C2440_DSC1_SCK1_6mA (3<<26)
+#define S3C2440_DSC1_SCK1_MASK (3<<26)
+
+#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
+#define S3C2440_DSC1_SCKE_10mA (0<<24)
+#define S3C2440_DSC1_SCKE_8mA (1<<24)
+#define S3C2440_DSC1_SCKE_6mA (2<<24)
+#define S3C2440_DSC1_SCKE_4mA (3<<24)
+#define S3C2440_DSC1_SCKE_MASK (3<<24)
+
+/* SDRAM nRAS/nCAS */
+#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22)
+#define S3C2440_DSC1_SDR_10mA (0<<22)
+#define S3C2440_DSC1_SDR_8mA (1<<22)
+#define S3C2440_DSC1_SDR_6mA (2<<22)
+#define S3C2440_DSC1_SDR_4mA (3<<22)
+#define S3C2440_DSC1_SDR_MASK (3<<22)
+
+/* NAND Flash Controller */
+#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20)
+#define S3C2440_DSC1_NFC_10mA (0<<20)
+#define S3C2440_DSC1_NFC_8mA (1<<20)
+#define S3C2440_DSC1_NFC_6mA (2<<20)
+#define S3C2440_DSC1_NFC_4mA (3<<20)
+#define S3C2440_DSC1_NFC_MASK (3<<20)
+
+/* nBE[0..3] */
+#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18)
+#define S3C2440_DSC1_nBE_10mA (0<<18)
+#define S3C2440_DSC1_nBE_8mA (1<<18)
+#define S3C2440_DSC1_nBE_6mA (2<<18)
+#define S3C2440_DSC1_nBE_4mA (3<<18)
+#define S3C2440_DSC1_nBE_MASK (3<<18)
+
+#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16)
+#define S3C2440_DSC1_WOE_10mA (0<<16)
+#define S3C2440_DSC1_WOE_8mA (1<<16)
+#define S3C2440_DSC1_WOE_6mA (2<<16)
+#define S3C2440_DSC1_WOE_4mA (3<<16)
+#define S3C2440_DSC1_WOE_MASK (3<<16)
+
+#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14)
+#define S3C2440_DSC1_CS7_10mA (0<<14)
+#define S3C2440_DSC1_CS7_8mA (1<<14)
+#define S3C2440_DSC1_CS7_6mA (2<<14)
+#define S3C2440_DSC1_CS7_4mA (3<<14)
+#define S3C2440_DSC1_CS7_MASK (3<<14)
+
+#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12)
+#define S3C2440_DSC1_CS6_10mA (0<<12)
+#define S3C2440_DSC1_CS6_8mA (1<<12)
+#define S3C2440_DSC1_CS6_6mA (2<<12)
+#define S3C2440_DSC1_CS6_4mA (3<<12)
+#define S3C2440_DSC1_CS6_MASK (3<<12)
+
+#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10)
+#define S3C2440_DSC1_CS5_10mA (0<<10)
+#define S3C2440_DSC1_CS5_8mA (1<<10)
+#define S3C2440_DSC1_CS5_6mA (2<<10)
+#define S3C2440_DSC1_CS5_4mA (3<<10)
+#define S3C2440_DSC1_CS5_MASK (3<<10)
+
+#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8)
+#define S3C2440_DSC1_CS4_10mA (0<<8)
+#define S3C2440_DSC1_CS4_8mA (1<<8)
+#define S3C2440_DSC1_CS4_6mA (2<<8)
+#define S3C2440_DSC1_CS4_4mA (3<<8)
+#define S3C2440_DSC1_CS4_MASK (3<<8)
+
+#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6)
+#define S3C2440_DSC1_CS3_10mA (0<<6)
+#define S3C2440_DSC1_CS3_8mA (1<<6)
+#define S3C2440_DSC1_CS3_6mA (2<<6)
+#define S3C2440_DSC1_CS3_4mA (3<<6)
+#define S3C2440_DSC1_CS3_MASK (3<<6)
+
+#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4)
+#define S3C2440_DSC1_CS2_10mA (0<<4)
+#define S3C2440_DSC1_CS2_8mA (1<<4)
+#define S3C2440_DSC1_CS2_6mA (2<<4)
+#define S3C2440_DSC1_CS2_4mA (3<<4)
+#define S3C2440_DSC1_CS2_MASK (3<<4)
+
+#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2)
+#define S3C2440_DSC1_CS1_10mA (0<<2)
+#define S3C2440_DSC1_CS1_8mA (1<<2)
+#define S3C2440_DSC1_CS1_6mA (2<<2)
+#define S3C2440_DSC1_CS1_4mA (3<<2)
+#define S3C2440_DSC1_CS1_MASK (3<<2)
+
+#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0
+#define S3C2440_DSC1_CS0_10mA (0<<0)
+#define S3C2440_DSC1_CS0_8mA (1<<0)
+#define S3C2440_DSC1_CS0_6mA (2<<0)
+#define S3C2440_DSC1_CS0_4mA (3<<0)
+#define S3C2440_DSC1_CS0_MASK (3<<0)
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+#endif /* __ASM_ARCH_REGS_DSC_H */
+
--- /dev/null
+/* linux/include/asm/hardware/s3c2410/regs-gpioj.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 GPIO J register definitions
+ *
+ * Changelog:
+ * 11-Aug-2004 BJD Created file
+*/
+
+
+#ifndef __ASM_ARCH_REGS_GPIOJ_H
+#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
+
+/* Port J consists of 13 GPIO/Camera pins
+ *
+ * GPJCON has 2 bits for each of the input pins on port F
+ * 00 = 0 input, 1 output, 2 Camera
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2440_GPIO_BANKJ (416)
+
+#define S3C2440_GPJCON S3C2410_GPIOREG(0xd0)
+#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
+#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
+
+#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
+#define S3C2440_GPJ0_INP (0x00 << 0)
+#define S3C2440_GPJ0_OUTP (0x01 << 0)
+#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0)
+
+#define S3C2440_GPJ1 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
+#define S3C2440_GPJ1_INP (0x00 << 2)
+#define S3C2440_GPJ1_OUTP (0x01 << 2)
+#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2)
+
+#define S3C2440_GPJ2 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
+#define S3C2440_GPJ2_INP (0x00 << 4)
+#define S3C2440_GPJ2_OUTP (0x01 << 4)
+#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4)
+
+#define S3C2440_GPJ3 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
+#define S3C2440_GPJ3_INP (0x00 << 6)
+#define S3C2440_GPJ3_OUTP (0x01 << 6)
+#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6)
+
+#define S3C2440_GPJ4 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
+#define S3C2440_GPJ4_INP (0x00 << 8)
+#define S3C2440_GPJ4_OUTP (0x01 << 8)
+#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8)
+
+#define S3C2440_GPJ5 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
+#define S3C2440_GPJ5_INP (0x00 << 10)
+#define S3C2440_GPJ5_OUTP (0x01 << 10)
+#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10)
+
+#define S3C2440_GPJ6 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
+#define S3C2440_GPJ6_INP (0x00 << 12)
+#define S3C2440_GPJ6_OUTP (0x01 << 12)
+#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12)
+
+#define S3C2440_GPJ7 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
+#define S3C2440_GPJ7_INP (0x00 << 14)
+#define S3C2440_GPJ7_OUTP (0x01 << 14)
+#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14)
+
+#define S3C2440_GPJ8 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
+#define S3C2440_GPJ8_INP (0x00 << 16)
+#define S3C2440_GPJ8_OUTP (0x01 << 16)
+#define S3C2440_GPJ8_CAMPCLK (0x02 << 16)
+
+#define S3C2440_GPJ9 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
+#define S3C2440_GPJ9_INP (0x00 << 18)
+#define S3C2440_GPJ9_OUTP (0x01 << 18)
+#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18)
+
+#define S3C2440_GPJ10 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
+#define S3C2440_GPJ10_INP (0x00 << 20)
+#define S3C2440_GPJ10_OUTP (0x01 << 20)
+#define S3C2440_GPJ10_CAMHREF (0x02 << 20)
+
+#define S3C2440_GPJ11 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
+#define S3C2440_GPJ11_INP (0x00 << 22)
+#define S3C2440_GPJ11_OUTP (0x01 << 22)
+#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
+
+#define S3C2440_GPJ12 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
+#define S3C2440_GPJ12_INP (0x00 << 24)
+#define S3C2440_GPJ12_OUTP (0x01 << 24)
+#define S3C2440_GPJ12_CAMCLKOUT (0x02 << 24)
+
+#endif /* __ASM_ARCH_REGS_GPIOJ_H */
+
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 I2C Controller
+ *
+ * Changelog:
+ * 03-Oct-2004 BJD Initial include for Linux
+*/
+
+#ifndef __ASM_ARCH_IIC_H
+#define __ASM_ARCH_IIC_H __FILE__
+
+/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
+#define S3C2410_IICREG(x) (x)
+
+#define S3C2410_IICCON S3C2410_IICREG(0x00)
+#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
+#define S3C2410_IICADD S3C2410_IICREG(0x08)
+#define S3C2410_IICDS S3C2410_IICREG(0x0C)
+
+#define S3C2410_IICCON_ACKEN (1<<7)
+#define S3C2410_IICCON_TXDIV_16 (0<<6)
+#define S3C2410_IICCON_TXDIV_512 (1<<6)
+#define S3C2410_IICCON_IRQEN (1<<5)
+#define S3C2410_IICCON_IRQPEND (1<<4)
+#define S3C2410_IICCON_SCALE(x) ((x)&15)
+#define S3C2410_IICCON_SCALEMASK (0xf)
+
+#define S3C2410_IICSTAT_MASTER_RX (2<<6)
+#define S3C2410_IICSTAT_MASTER_TX (3<<6)
+#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
+#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
+#define S3C2410_IICSTAT_MODEMASK (3<<6)
+
+#define S3C2410_IICSTAT_START (1<<5)
+#define S3C2410_IICSTAT_BUSBUSY (1<<5)
+#define S3C2410_IICSTAT_TXRXEN (1<<4)
+#define S3C2410_IICSTAT_ARBITR (1<<3)
+#define S3C2410_IICSTAT_ASSLAVE (1<<2)
+#define S3C2410_IICSTAT_ADDR0 (1<<1)
+#define S3C2410_IICSTAT_LASTBIT (1<<0)
+
+#endif /* __ASM_ARCH_IIC_H */
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Memory Control register definitions
+ *
+ * Changelog:
+ * 29-Sep-2004 BJD Initial include for Linux
+ *
+*/
+
+#ifndef __ASM_ARM_MEMREGS_H
+#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
+
+#ifndef S3C2410_MEMREG
+#define S3C2410_MEMREG(x) (S3C2410_VA_MEMCTRL + (x))
+#endif
+
+/* bus width, and wait state control */
+#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
+
+/* bank zero config - note, pinstrapped from OM pins! */
+#define S3C2410_BWSCON_DW0_16 (1<<1)
+#define S3C2410_BWSCON_DW0_32 (2<<1)
+
+/* bank one configs */
+#define S3C2410_BWSCON_DW1_8 (0<<4)
+#define S3C2410_BWSCON_DW1_16 (1<<4)
+#define S3C2410_BWSCON_DW1_32 (2<<4)
+#define S3C2410_BWSCON_WS1 (1<<6)
+#define S3C2410_BWSCON_ST1 (1<<7)
+
+/* bank 2 configurations */
+#define S3C2410_BWSCON_DW2_8 (0<<8)
+#define S3C2410_BWSCON_DW2_16 (1<<8)
+#define S3C2410_BWSCON_DW2_32 (2<<8)
+#define S3C2410_BWSCON_WS2 (1<<10)
+#define S3C2410_BWSCON_ST2 (1<<11)
+
+/* bank 3 configurations */
+#define S3C2410_BWSCON_DW3_8 (0<<12)
+#define S3C2410_BWSCON_DW3_16 (1<<12)
+#define S3C2410_BWSCON_DW3_32 (2<<12)
+#define S3C2410_BWSCON_WS3 (1<<14)
+#define S3C2410_BWSCON_ST3 (1<<15)
+
+/* bank 4 configurations */
+#define S3C2410_BWSCON_DW4_8 (0<<16)
+#define S3C2410_BWSCON_DW4_16 (1<<16)
+#define S3C2410_BWSCON_DW4_32 (2<<16)
+#define S3C2410_BWSCON_WS4 (1<<18)
+#define S3C2410_BWSCON_ST4 (1<<19)
+
+/* bank 5 configurations */
+#define S3C2410_BWSCON_DW5_8 (0<<20)
+#define S3C2410_BWSCON_DW5_16 (1<<20)
+#define S3C2410_BWSCON_DW5_32 (2<<20)
+#define S3C2410_BWSCON_WS5 (1<<22)
+#define S3C2410_BWSCON_ST5 (1<<23)
+
+/* bank 6 configurations */
+#define S3C2410_BWSCON_DW6_8 (0<<24)
+#define S3C2410_BWSCON_DW6_16 (1<<24)
+#define S3C2410_BWSCON_DW6_32 (2<<24)
+#define S3C2410_BWSCON_WS6 (1<<26)
+#define S3C2410_BWSCON_ST6 (1<<27)
+
+/* bank 7 configurations */
+#define S3C2410_BWSCON_DW7_8 (0<<28)
+#define S3C2410_BWSCON_DW7_16 (1<<28)
+#define S3C2410_BWSCON_DW7_32 (2<<28)
+#define S3C2410_BWSCON_WS7 (1<<30)
+#define S3C2410_BWSCON_ST7 (1<<31)
+
+/* memory set (rom, ram) */
+#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
+#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
+#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
+#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
+#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
+#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
+#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
+#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
+
+/* bank configuration registers */
+
+#define S3C2410_BANKCON_PMCnorm (0x00)
+#define S3C2410_BANKCON_PMC4 (0x01)
+#define S3C2410_BANKCON_PMC8 (0x02)
+#define S3C2410_BANKCON_PMC16 (0x03)
+
+/* bank configurations for banks 0..7, note banks
+ * 6 and 7 have differnt configurations depending on
+ * the memory type bits */
+
+#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
+#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
+#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
+#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
+
+#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
+#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
+#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
+#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
+
+#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
+#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
+#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
+#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
+
+#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
+#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
+#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
+#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
+#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
+#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
+#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
+#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
+
+#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
+#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
+#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
+#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
+
+#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
+#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
+#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
+#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
+
+#define S3C2410_BANKCON_SRAM (0x0 << 15)
+#define S3C2410_BANKCON_SDRAM (0x3 << 15)
+
+/* next bits only for SDRAM in 6,7 */
+#define S3C2410_BANKCON_Trdc2 (0x00 << 2)
+#define S3C2410_BANKCON_Trdc3 (0x01 << 2)
+#define S3C2410_BANKCON_Trdc4 (0x02 << 2)
+
+/* control column address select */
+#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
+#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
+#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
+
+#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
+#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
+#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
+#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
+
+/* refresh control */
+
+#define S3C2410_REFRESH_REFEN (1<<23)
+#define S3C2410_REFRESH_SELF (1<<22)
+#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
+
+#define S3C2410_REFRESH_TRP_MASK (3<<20)
+#define S3C2410_REFRESH_TRP_2clk (0<<20)
+#define S3C2410_REFRESH_TRP_3clk (1<<20)
+#define S3C2410_REFRESH_TRP_4clk (2<<20)
+
+#define S3C2410_REFRESH_TSRC_MASK (3<<18)
+#define S3C2410_REFRESH_TSRC_4clk (0<<18)
+#define S3C2410_REFRESH_TSRC_5clk (1<<18)
+#define S3C2410_REFRESH_TSRC_6clk (2<<18)
+#define S3C2410_REFRESH_TSRC_7clk (3<<18)
+
+
+/* mode select register(s) */
+
+#define S3C2410_MRSRB_CL1 (0x00 << 4)
+#define S3C2410_MRSRB_CL2 (0x02 << 4)
+#define S3C2410_MRSRB_CL3 (0x03 << 4)
+
+/* bank size register */
+#define S3C2410_BANKSIZE_128M (0x2 << 0)
+#define S3C2410_BANKSIZE_64M (0x1 << 0)
+#define S3C2410_BANKSIZE_32M (0x0 << 0)
+#define S3C2410_BANKSIZE_16M (0x7 << 0)
+#define S3C2410_BANKSIZE_8M (0x6 << 0)
+#define S3C2410_BANKSIZE_4M (0x5 << 0)
+#define S3C2410_BANKSIZE_2M (0x4 << 0)
+#define S3C2410_BANKSIZE_MASK (0x7 << 0)
+#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
+#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
+#define S3C2410_BANKSIZE_BURST (1<<7)
+
+#endif /* __ASM_ARM_MEMREGS_H */
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 clock register definitions
+ *
+ * Changelog:
+ * 18-Aug-2004 BJD Copied file from 2.4 and updated
+*/
+
+#ifndef __ASM_ARM_REGS_NAND
+#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
+
+
+#define S3C2410_NFREG(x) (x)
+
+#define S3C2410_NFCONF S3C2410_NFREG(0x00)
+#define S3C2410_NFCMD S3C2410_NFREG(0x04)
+#define S3C2410_NFADDR S3C2410_NFREG(0x08)
+#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
+#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
+#define S3C2410_NFECC S3C2410_NFREG(0x14)
+
+#define S3C2410_NFCONF_EN (1<<15)
+#define S3C2410_NFCONF_512BYTE (1<<14)
+#define S3C2410_NFCONF_4STEP (1<<13)
+#define S3C2410_NFCONF_INITECC (1<<12)
+#define S3C2410_NFCONF_nFCE (1<<11)
+#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
+
+#define S3C2410_NFSTAT_BUSY (1<<0)
+
+/* think ECC can only be 8bit read? */
+
+#endif /* __ASM_ARM_REGS_NAND */
+
--- /dev/null
+/* linux/include/asm/arch-s3c2410/regs-sdi.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 MMC/SDIO register definitions
+ *
+ * Changelog:
+ * 18-Aug-2004 Ben Dooks Created initial file
+*/
+
+#ifndef __ASM_ARM_REGS_SDI
+#define __ASM_ARM_REGS_SDI "regs-sdi.h"
+
+#define S3C2410_SDICON (0x00)
+#define S3C2410_SDIPRE (0x04)
+#define S3C2410_SDICMDARG (0x08)
+#define S3C2410_SDICMDCON (0x0C)
+#define S3C2410_SDICMDSTAT (0x10)
+#define S3C2410_SDIRSP0 (0x14)
+#define S3C2410_SDIRSP1 (0x18)
+#define S3C2410_SDIRSP2 (0x1C)
+#define S3C2410_SDIRSP3 (0x20)
+#define S3C2410_SDITIMER (0x24)
+#define S3C2410_SDIBSIZE (0x28)
+#define S3C2410_SDIDCON (0x2C)
+#define S3C2410_SDIDCNT (0x30)
+#define S3C2410_SDIDSTA (0x34)
+#define S3C2410_SDIFSTA (0x38)
+#define S3C2410_SDIDATA (0x3C)
+#define S3C2410_SDIIMSK (0x40)
+
+#define S3C2410_SDICON_BYTEORDER (1<<4)
+#define S3C2410_SDICON_SDIOIRQ (1<<3)
+#define S3C2410_SDICON_RWAITEN (1<<2)
+#define S3C2410_SDICON_FIFORESET (1<<1)
+#define S3C2410_SDICON_CLOCKTYPE (1<<0)
+
+#define S3C2410_SDICMDCON_ABORT (1<<12)
+#define S3C2410_SDICMDCON_WITHDATA (1<<11)
+#define S3C2410_SDICMDCON_LONGRSP (1<<10)
+#define S3C2410_SDICMDCON_WAITRSP (1<<9)
+#define S3C2410_SDICMDCON_CMDSTART (1<<8)
+#define S3C2410_SDICMDCON_INDEX (0xff)
+
+#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
+#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
+#define S3C2410_SDICMDSTAT_RSPFIN (1<<9)
+#define S3C2410_SDICMDSTAT_XFERING (1<<8)
+#define S3C2410_SDICMDSTAT_INDEX (0xff)
+
+#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
+#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
+#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
+#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18)
+#define S3C2410_SDIDCON_BLOCKMODE (1<<17)
+#define S3C2410_SDIDCON_WIDEBUS (1<<16)
+#define S3C2410_SDIDCON_DMAEN (1<<15)
+#define S3C2410_SDIDCON_STOP (1<<14)
+
+#define S3C2410_SDIDCON_XFER_MASK (3<<12)
+#define S3C2410_SDIDCON_XFER_READY (0<<12)
+#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
+#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
+#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
+
+#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
+
+#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
+#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
+#define S3C2410_SDIDSTA_FIFOFAIL (1<<8)
+#define S3C2410_SDIDSTA_CRCFAIL (1<<7)
+#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6)
+#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5)
+#define S3C2410_SDIDSTA_XFERFINISH (1<<4)
+#define S3C2410_SDIDSTA_BUSYFINISH (1<<3)
+#define S3C2410_SDIDSTA_TXDATAON (1<<1)
+#define S3C2410_SDIDSTA_RXDATAON (1<<0)
+
+#define S3C2410_SDIFSTA_TXFULL (1<<13)
+#define S3C2410_SDIFSTA_RXFULL (1<<12)
+#define S3C2410_SDIFSTA_TXHALF (1<<11)
+#define S3C2410_SDIFSTA_TXEMPTY (1<<10)
+#define S3C2410_SDIFSTA_RXLAST (1<<9)
+#define S3C2410_SDIFSTA_RXFULL (1<<8)
+#define S3C2410_SDIFSTA_RXHALF (1<<7)
+#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
+
+#define S3C2410_SDIIMSK_RESPONSECRC (1<<17)
+#define S3C2410_SDIIMSK_CMDSENT (1<<16)
+#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15)
+#define S3C2410_SDIIMSK_RESPONSEND (1<<14)
+#define S3C2410_SDIIMSK_READWAIT (1<<13)
+#define S3C2410_SDIIMSK_SDIOIRQ (1<<12)
+#define S3C2410_SDIIMSK_FIFOFAIL (1<<11)
+#define S3C2410_SDIIMSK_CRCSTATUS (1<<10)
+#define S3C2410_SDIIMSK_DATACRC (1<<9)
+#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8)
+#define S3C2410_SDIIMSK_DATAFINISH (1<<7)
+#define S3C2410_SDIIMSK_BUSYFINISH (1<<6)
+#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4)
+#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3)
+#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2)
+#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1)
+#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0)
+
+#endif /* __ASM_ARM_REGS_SDI */
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
+ *
+ * Copyright (c) 2004 Fetron GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 SPI register definition
+ *
+ * Changelog:
+ * 20-04-2004 KF Created file
+ * 04-10-2004 BJD Removed VA address (no longer mapped)
+ * tidied file for submission
+ */
+
+#ifndef __ASM_ARCH_REGS_SPI_H
+#define __ASM_ARCH_REGS_SPI_H
+
+
+#define S3C2410_SPCON (0x00)
+
+#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
+#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
+#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
+#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
+#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
+ 0: slave, 1: master */
+#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
+#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
+
+#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
+#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
+
+#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
+
+
+#define S3C2410_SPSTA (0x04)
+
+#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
+#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
+#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
+
+
+#define S3C2410_SPPIN (0x08)
+
+#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
+#define S3C2410_SPPIN_RESERVED (1<<1)
+#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
+
+
+#define S3C2410_SPPRE (0x0C)
+#define S3C2410_SPTDAT (0x10)
+#define S3C2410_SPRDAT (0x14)
+
+#endif /* __ASM_ARCH_REGS_SPI_H */
--- /dev/null
+/* linux/include/asm/arch-s3c2410/regs-udc.h
+ *
+ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * Changelog:
+ * 01-08-2004 initial creation
+ * 12-09-2004 cleanup for submission
+ */
+
+#ifndef __ASM_ARCH_REGS_UDC_H
+#define __ASM_ARCH_REGS_UDC_H
+
+
+#define S3C2410_USBDREG(x) ((x) + S3C2410_VA_USBDEV)
+
+#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
+#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
+#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
+
+#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
+#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
+
+#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
+
+#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
+#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
+
+#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
+#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
+#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
+#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
+#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
+
+#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
+#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
+#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
+#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
+#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
+#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
+
+#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
+#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
+#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
+#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
+#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
+#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
+
+#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
+#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
+#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
+#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
+#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
+#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
+
+#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
+#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
+#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
+#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
+#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
+#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
+
+#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
+
+/* indexed registers */
+
+#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x018c)
+
+#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
+
+#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
+#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
+
+#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
+#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
+#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
+#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
+
+
+
+#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
+#define S3C2410_UDC_PWR_RESET (1<<3) // R
+#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
+#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
+#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
+
+#define S3C2410_UDC_PWR_DEFAULT 0x00
+
+#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
+#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
+#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
+#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
+#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
+#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
+#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
+#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
+#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
+#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
+#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
+
+#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
+#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
+
+
+#define S3C2410_UDC_INDEX_EP0 (0x00)
+#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
+#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
+#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
+#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
+
+#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
+#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
+#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
+#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
+
+#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
+#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
+#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
+#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
+
+#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
+#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
+#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
+#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
+#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
+#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
+#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
+
+#define S3C2410_UDC_SETIX(x) \
+ __raw_writel(S3C2410_UDC_INDEX_ ## x, S3C2410_UDC_INDEX_REG);
+
+
+#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
+#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
+#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
+#define S3C2410_UDC_EP0_CSR_DE (1<<3)
+#define S3C2410_UDC_EP0_CSR_SE (1<<4)
+#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
+#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
+#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
+
+#define S3C2410_UDC_MAXP_8 (1<<0)
+#define S3C2410_UDC_MAXP_16 (1<<1)
+#define S3C2410_UDC_MAXP_32 (1<<2)
+#define S3C2410_UDC_MAXP_64 (1<<3)
+
+
+#endif
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/usb-control.h
+ *
+ * (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - usb port information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ * 11-Sep-2004 BJD Created file
+ * 21-Sep-2004 BJD Updated port info
+*/
+
+#ifndef __ASM_ARCH_USBCONTROL_H
+#define __ASM_ARCH_USBCONTROL_H "include/asm-arm/arch-s3c2410/usb-control.h"
+
+#define S3C_HCDFLG_USED (1)
+
+struct s3c2410_hcd_port {
+ unsigned char flags;
+ unsigned char power;
+ unsigned char oc_status;
+ unsigned char oc_changed;
+};
+
+struct s3c2410_hcd_info {
+ struct usb_hcd *hcd;
+ struct s3c2410_hcd_port port[2];
+
+ void (*power_control)(int port, int to);
+ void (*enable_oc)(struct s3c2410_hcd_info *, int on);
+ void (*report_oc)(struct s3c2410_hcd_info *, int ports);
+};
+
+static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports)
+{
+ if (info->report_oc != NULL) {
+ (info->report_oc)(info, ports);
+ }
+}
+
+#endif /*__ASM_ARCH_USBCONTROL_H */
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
+ *
+ * David A Rusling
+ *
+ * Copyright (C) 2001 ARM Limited
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+#include <linux/config.h>
+#include <linux/fb.h>
+
+/*
+ * CLCD Controller Internal Register addresses
+ */
+#define CLCD_TIM0 0x00000000
+#define CLCD_TIM1 0x00000004
+#define CLCD_TIM2 0x00000008
+#define CLCD_TIM3 0x0000000c
+#define CLCD_UBAS 0x00000010
+#define CLCD_LBAS 0x00000014
+
+#ifndef CONFIG_ARCH_VERSATILE_PB
+#define CLCD_IENB 0x00000018
+#define CLCD_CNTL 0x0000001c
+#else
+/*
+ * Someone rearranged these two registers on the Versatile
+ * platform...
+ */
+#define CLCD_IENB 0x0000001c
+#define CLCD_CNTL 0x00000018
+#endif
+
+#define CLCD_STAT 0x00000020
+#define CLCD_INTR 0x00000024
+#define CLCD_UCUR 0x00000028
+#define CLCD_LCUR 0x0000002C
+#define CLCD_PALL 0x00000200
+#define CLCD_PALETTE 0x00000200
+
+#define TIM2_CLKSEL (1 << 5)
+#define TIM2_IVS (1 << 11)
+#define TIM2_IHS (1 << 12)
+#define TIM2_IPC (1 << 13)
+#define TIM2_IOE (1 << 14)
+#define TIM2_BCD (1 << 26)
+
+#define CNTL_LCDEN (1 << 0)
+#define CNTL_LCDBPP1 (0 << 1)
+#define CNTL_LCDBPP2 (1 << 1)
+#define CNTL_LCDBPP4 (2 << 1)
+#define CNTL_LCDBPP8 (3 << 1)
+#define CNTL_LCDBPP16 (4 << 1)
+#define CNTL_LCDBPP24 (5 << 1)
+#define CNTL_LCDBW (1 << 4)
+#define CNTL_LCDTFT (1 << 5)
+#define CNTL_LCDMONO8 (1 << 6)
+#define CNTL_LCDDUAL (1 << 7)
+#define CNTL_BGR (1 << 8)
+#define CNTL_BEBO (1 << 9)
+#define CNTL_BEPO (1 << 10)
+#define CNTL_LCDPWR (1 << 11)
+#define CNTL_LCDVCOMP(x) ((x) << 12)
+#define CNTL_LDMAFIFOTIME (1 << 15)
+#define CNTL_WATERMARK (1 << 16)
+
+struct clcd_panel {
+ struct fb_videomode mode;
+ signed short width; /* width in mm */
+ signed short height; /* height in mm */
+ u32 tim2;
+ u32 tim3;
+ u32 cntl;
+ unsigned int bpp:8,
+ fixedtimings:1,
+ grayscale:1;
+ unsigned int connector;
+};
+
+struct clcd_regs {
+ u32 tim0;
+ u32 tim1;
+ u32 tim2;
+ u32 tim3;
+ u32 cntl;
+ unsigned long pixclock;
+};
+
+struct clcd_fb;
+
+/*
+ * the board-type specific routines
+ */
+struct clcd_board {
+ const char *name;
+
+ /*
+ * Optional. Check whether the var structure is acceptable
+ * for this display.
+ */
+ int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
+
+ /*
+ * Compulsary. Decode fb->fb.var into regs->*. In the case of
+ * fixed timing, set regs->* to the register values required.
+ */
+ void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
+
+ /*
+ * Optional. Disable any extra display hardware.
+ */
+ void (*disable)(struct clcd_fb *);
+
+ /*
+ * Optional. Enable any extra display hardware.
+ */
+ void (*enable)(struct clcd_fb *);
+
+ /*
+ * Setup platform specific parts of CLCD driver
+ */
+ int (*setup)(struct clcd_fb *);
+
+ /*
+ * Remove platform specific parts of CLCD driver
+ */
+ void (*remove)(struct clcd_fb *);
+};
+
+struct amba_device;
+struct clk;
+
+/* this data structure describes each frame buffer device we find */
+struct clcd_fb {
+ struct fb_info fb;
+ struct amba_device *dev;
+ struct clk *clk;
+ struct clcd_panel *panel;
+ struct clcd_board *board;
+ void *board_data;
+ void *regs;
+ u32 clcd_cntl;
+ u32 cmap[16];
+};
+
+static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
+{
+ u32 val;
+
+ /*
+ * Program the CLCD controller registers and start the CLCD
+ */
+ val = ((fb->fb.var.xres / 16) - 1) << 2;
+ val |= (fb->fb.var.hsync_len - 1) << 8;
+ val |= (fb->fb.var.right_margin - 1) << 16;
+ val |= (fb->fb.var.left_margin - 1) << 24;
+ regs->tim0 = val;
+
+ val = fb->fb.var.yres - 1;
+ val |= (fb->fb.var.vsync_len - 1) << 10;
+ val |= fb->fb.var.lower_margin << 16;
+ val |= fb->fb.var.upper_margin << 24;
+ regs->tim1 = val;
+
+ val = fb->panel->tim2;
+ val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
+ val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
+
+ if (fb->panel->cntl & CNTL_LCDTFT)
+ val |= (fb->fb.var.xres_virtual - 1) << 16;
+ else if (fb->panel->cntl & CNTL_LCDBW)
+ printk("what value for CPL for stnmono panels?");
+ else
+ val |= ((fb->fb.var.xres_virtual * 8 / 3) - 1) << 16;
+ regs->tim2 = val;
+
+ regs->tim3 = fb->panel->tim3;
+
+ val = fb->panel->cntl;
+ if (fb->fb.var.grayscale)
+ val |= CNTL_LCDBW;
+
+ switch (fb->fb.var.bits_per_pixel) {
+ case 1:
+ val |= CNTL_LCDBPP1;
+ break;
+ case 2:
+ val |= CNTL_LCDBPP2;
+ break;
+ case 4:
+ val |= CNTL_LCDBPP4;
+ break;
+ case 8:
+ val |= CNTL_LCDBPP8;
+ break;
+ case 16:
+ val |= CNTL_LCDBPP16;
+ break;
+ case 24:
+ val |= CNTL_LCDBPP24;
+ break;
+ }
+
+ regs->cntl = val;
+ regs->pixclock = fb->fb.var.pixclock;
+}
+
+static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
+{
+ var->xres_virtual = var->xres = (var->xres + 7) & ~7;
+ var->yres_virtual = var->yres;
+
+#define CHECK(e,l,h) (var->e < l || var->e > h)
+ if (CHECK(right_margin, (5+1), 256) || /* back porch */
+ CHECK(left_margin, (5+1), 256) || /* front porch */
+ CHECK(hsync_len, (5+1), 256) ||
+ var->xres > 4096 ||
+ var->lower_margin > 255 || /* back porch */
+ var->upper_margin > 255 || /* front porch */
+ var->vsync_len > 32 ||
+ var->yres > 1024)
+ return -EINVAL;
+#undef CHECK
+
+ /* single panel mode: PCD = max(PCD, 1) */
+ /* dual panel mode: PCD = max(PCD, 5) */
+
+ /*
+ * You can't change the grayscale setting, and
+ * we can only do non-interlaced video.
+ */
+ if (var->grayscale != fb->fb.var.grayscale ||
+ (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
+ return -EINVAL;
+
+#define CHECK(e) (var->e != fb->fb.var.e)
+ if (fb->panel->fixedtimings &&
+ (CHECK(xres) ||
+ CHECK(yres) ||
+ CHECK(bits_per_pixel) ||
+ CHECK(pixclock) ||
+ CHECK(left_margin) ||
+ CHECK(right_margin) ||
+ CHECK(upper_margin) ||
+ CHECK(lower_margin) ||
+ CHECK(hsync_len) ||
+ CHECK(vsync_len) ||
+ CHECK(sync)))
+ return -EINVAL;
+#undef CHECK
+
+ var->nonstd = 0;
+ var->accel_flags = 0;
+
+ return 0;
+}
--- /dev/null
+/*
+ * linux/include/asm-arm/mach/mmc.h
+ */
+#ifndef ASMARM_MACH_MMC_H
+#define ASMARM_MACH_MMC_H
+
+#include <linux/mmc/protocol.h>
+
+struct mmc_platform_data {
+ unsigned int mclk; /* mmc base clock rate */
+ unsigned int ocr_mask; /* available voltages */
+ u32 (*translate_vdd)(struct device *, unsigned int);
+ unsigned int (*status)(struct device *);
+};
+
+#endif
--- /dev/null
+#ifndef _ASM_GENERIC_BUG_H
+#define _ASM_GENERIC_BUG_H
+
+#include <linux/compiler.h>
+#include <linux/config.h>
+
+#ifndef HAVE_ARCH_BUG
+#define BUG() do { \
+ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+ panic("BUG!"); \
+} while (0)
+#endif
+
+#ifndef HAVE_ARCH_PAGE_BUG
+#define PAGE_BUG(page) do { \
+ printk("page BUG for page at %p\n", page); \
+ BUG(); \
+} while (0)
+#endif
+
+#ifndef HAVE_ARCH_BUG_ON
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+#endif
+
+#ifndef HAVE_ARCH_WARN_ON
+#define WARN_ON(condition) do { \
+ if (unlikely((condition)!=0)) { \
+ printk("Badness in %s at %s:%d\n", __FUNCTION__, __FILE__, __LINE__); \
+ dump_stack(); \
+ } \
+} while (0)
+#endif
+
+#endif
--- /dev/null
+#ifndef __GENERIC_IO_H
+#define __GENERIC_IO_H
+
+#include <linux/linkage.h>
+
+/*
+ * These are the "generic" interfaces for doing new-style
+ * memory-mapped or PIO accesses. Architectures may do
+ * their own arch-optimized versions, these just act as
+ * wrappers around the old-style IO register access functions:
+ * read[bwl]/write[bwl]/in[bwl]/out[bwl]
+ *
+ * Don't include this directly, include it from <asm/io.h>.
+ */
+
+/*
+ * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
+ * access or a MMIO access, these functions don't care. The info is
+ * encoded in the hardware mapping set up by the mapping functions
+ * (or the cookie itself, depending on implementation and hw).
+ *
+ * The generic routines just encode the PIO/MMIO as part of the
+ * cookie, and coldly assume that the MMIO IO mappings are not
+ * in the low address range. Architectures for which this is not
+ * true can't use this generic implementation.
+ */
+extern unsigned int fastcall ioread8(void __iomem *);
+extern unsigned int fastcall ioread16(void __iomem *);
+extern unsigned int fastcall ioread32(void __iomem *);
+
+extern void fastcall iowrite8(u8, void __iomem *);
+extern void fastcall iowrite16(u16, void __iomem *);
+extern void fastcall iowrite32(u32, void __iomem *);
+
+/*
+ * "string" versions of the above. Note that they
+ * use native byte ordering for the accesses (on
+ * the assumption that IO and memory agree on a
+ * byte order, and CPU byteorder is irrelevant).
+ *
+ * They do _not_ update the port address. If you
+ * want MMIO that copies stuff laid out in MMIO
+ * memory across multiple ports, use "memcpy_toio()"
+ * and friends.
+ */
+extern void fastcall ioread8_rep(void __iomem *port, void *buf, unsigned long count);
+extern void fastcall ioread16_rep(void __iomem *port, void *buf, unsigned long count);
+extern void fastcall ioread32_rep(void __iomem *port, void *buf, unsigned long count);
+
+extern void fastcall iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
+extern void fastcall iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
+extern void fastcall iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+#endif
--- /dev/null
+#ifndef _ASM_GENERIC_UACCESS_H_
+#define _ASM_GENERIC_UACCESS_H_
+
+/*
+ * This macro should be used instead of __get_user() when accessing
+ * values at locations that are not known to be aligned.
+ */
+#define __get_user_unaligned(x, ptr) \
+({ \
+ __typeof__ (*(ptr)) __x; \
+ __copy_from_user(&__x, (ptr), sizeof(*(ptr))) ? -EFAULT : 0; \
+ (x) = __x; \
+})
+
+
+/*
+ * This macro should be used instead of __put_user() when accessing
+ * values at locations that are not known to be aligned.
+ */
+#define __put_user_unaligned(x, ptr) \
+({ \
+ __typeof__ (*(ptr)) __x = (x); \
+ __copy_to_user((ptr), &__x, sizeof(*(ptr))) ? -EFAULT : 0; \
+})
+
+#endif /* _ASM_GENERIC_UACCESS_H */
--- /dev/null
+#ifndef _I386_KDEBUG_H
+#define _I386_KDEBUG_H 1
+
+/*
+ * Aug-05 2004 Ported by Prasanna S Panchamukhi <prasanna@in.ibm.com>
+ * from x86_64 architecture.
+ */
+#include <linux/notifier.h>
+
+struct pt_regs;
+
+struct die_args {
+ struct pt_regs *regs;
+ const char *str;
+ long err;
+ int trapnr;
+ int signr;
+};
+
+/* Note - you should never unregister because that can race with NMIs.
+ If you really want to do it first unregister - then synchronize_kernel - then free.
+ */
+int register_die_notifier(struct notifier_block *nb);
+extern struct notifier_block *i386die_chain;
+
+
+/* Grossly misnamed. */
+enum die_val {
+ DIE_OOPS = 1,
+ DIE_INT3,
+ DIE_DEBUG,
+ DIE_PANIC,
+ DIE_NMI,
+ DIE_DIE,
+ DIE_NMIWATCHDOG,
+ DIE_KERNELDEBUG,
+ DIE_TRAP,
+ DIE_GPF,
+ DIE_CALL,
+ DIE_NMI_IPI,
+ DIE_PAGE_FAULT,
+};
+
+static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
+{
+ struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
+ return notifier_call_chain(&i386die_chain, val, &args);
+}
+
+#endif
--- /dev/null
+#ifndef _I386_KEXEC_H
+#define _I386_KEXEC_H
+
+#include <asm/fixmap.h>
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ *
+ * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
+ * calculation for the amount of memory directly mappable into the
+ * kernel memory space.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+#endif /* _I386_KEXEC_H */
--- /dev/null
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+/*
+ * Kernel Probes (KProbes)
+ * include/asm-i386/kprobes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ *
+ * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
+ * Probes initial implementation ( includes suggestions from
+ * Rusty Russell).
+ */
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+struct pt_regs;
+
+typedef u8 kprobe_opcode_t;
+#define BREAKPOINT_INSTRUCTION 0xcc
+#define MAX_INSN_SIZE 16
+#define MAX_STACK_SIZE 64
+#define MIN_STACK_SIZE(ADDR) (((MAX_STACK_SIZE) < \
+ (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) \
+ ? (MAX_STACK_SIZE) \
+ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
+
+/* trap3/1 are intr gates for kprobes. So, restore the status of IF,
+ * if necessary, before executing the original int3/1 (trap) handler.
+ */
+static inline void restore_interrupts(struct pt_regs *regs)
+{
+ if (regs->eflags & IF_MASK)
+ local_irq_enable();
+}
+
+#ifdef CONFIG_KPROBES
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data);
+#else /* !CONFIG_KPROBES */
+static inline int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ return 0;
+}
+#endif
+#endif /* _ASM_KPROBES_H */
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
+ * SGI Altix node and router hardware
+ *
+ * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
+ */
+
+#ifndef SN_HWPERF_H
+#define SN_HWPERF_H
+
+/*
+ * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
+ * return an array of these. Do not change this without also
+ * changing the corresponding SAL code.
+ */
+#define SN_HWPERF_MAXSTRING 128
+struct sn_hwperf_object_info {
+ u32 id;
+ union {
+ struct {
+ u64 this_part:1;
+ u64 is_shared:1;
+ } fields;
+ struct {
+ u64 flags;
+ u64 reserved;
+ } b;
+ } f;
+ char name[SN_HWPERF_MAXSTRING];
+ char location[SN_HWPERF_MAXSTRING];
+ u32 ports;
+};
+
+#define sn_hwp_this_part f.fields.this_part
+#define sn_hwp_is_shared f.fields.is_shared
+#define sn_hwp_flags f.b.flags
+
+#define SN_HWPERF_FOREIGN(x) (!(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
+
+/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
+struct sn_hwperf_port_info {
+ u32 port;
+ u32 conn_id;
+ u32 conn_port;
+};
+
+/* for HWPERF_{GET,SET}_MMRS */
+struct sn_hwperf_data {
+ u64 addr;
+ u64 data;
+};
+
+/* user ioctl() argument, see below */
+struct sn_hwperf_ioctl_args {
+ u64 arg; /* argument, usually an object id */
+ u64 sz; /* size of transfer */
+ void *ptr; /* pointer to source/target */
+ u32 v0; /* second return value */
+};
+
+/*
+ * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
+ * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
+ * to call SAL, and whether to use an interprocessor interrupt
+ * or task migration in order to do so. If the CPU specified is
+ * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
+ */
+#define SN_HWPERF_ARG_ANY_CPU 0x7fffffffUL
+#define SN_HWPERF_ARG_CPU_MASK 0x7fffffff00000000ULL
+#define SN_HWPERF_ARG_USE_IPI_MASK 0x8000000000000000ULL
+#define SN_HWPERF_ARG_OBJID_MASK 0x00000000ffffffffULL
+
+/*
+ * ioctl requests on the "sn_hwperf" misc device that call SAL.
+ */
+#define SN_HWPERF_OP_MEM_COPYIN 0x1000
+#define SN_HWPERF_OP_MEM_COPYOUT 0x2000
+#define SN_HWPERF_OP_MASK 0x0fff
+
+/*
+ * Determine mem requirement.
+ * arg don't care
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_GET_HEAPSIZE 1
+
+/*
+ * Install mem for SAL drvr
+ * arg don't care
+ * sz sizeof buffer pointed to by p
+ * p pointer to buffer for scratch area
+ */
+#define SN_HWPERF_INSTALL_HEAP 2
+
+/*
+ * Determine number of objects
+ * arg don't care
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_COUNT (10|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Determine object "distance", relative to a cpu. This operation can
+ * execute on a designated logical cpu number, using either an IPI or
+ * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg bitmap of IPI flag, cpu number and object id
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_DISTANCE (11|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate objects. Special case if sz == 8, returns the required
+ * buffer size.
+ * arg don't care
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_ENUM_OBJECTS (12|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate NumaLink ports for an object. Special case if sz == 8,
+ * returns the required buffer size.
+ * arg object id
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_port_info
+ */
+#define SN_HWPERF_ENUM_PORTS (13|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * SET/GET memory mapped registers. These operations can execute
+ * on a designated logical cpu number, using either an IPI or via
+ * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg bitmap of ipi flag, cpu number and object id
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_data
+ */
+#define SN_HWPERF_SET_MMRS (14|SN_HWPERF_OP_MEM_COPYIN)
+#define SN_HWPERF_GET_MMRS (15|SN_HWPERF_OP_MEM_COPYOUT| \
+ SN_HWPERF_OP_MEM_COPYIN)
+/*
+ * Lock a shared object
+ * arg object id
+ * sz don't care
+ * p don't care
+ */
+#define SN_HWPERF_ACQUIRE 16
+
+/*
+ * Unlock a shared object
+ * arg object id
+ * sz don't care
+ * p don't care
+ */
+#define SN_HWPERF_RELEASE 17
+
+/*
+ * Break a lock on a shared object
+ * arg object id
+ * sz don't care
+ * p don't care
+ */
+#define SN_HWPERF_FORCE_RELEASE 18
+
+/*
+ * ioctl requests on "sn_hwperf" that do not call SAL
+ */
+
+/*
+ * get cpu info as an array of hwperf_object_info_t.
+ * id is logical CPU number, name is description, location
+ * is geoid (e.g. 001c04#1c). Special case if sz == 8,
+ * returns the required buffer size.
+ *
+ * arg don't care
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_GET_CPU_INFO (100|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given an object id, return it's node number (aka cnode).
+ * arg object id
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_GET_OBJ_NODE (101|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given a node number (cnode), return it's nasid.
+ * arg ordinal node number (aka cnodeid)
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
+
+/* return codes */
+#define SN_HWPERF_OP_OK 0
+#define SN_HWPERF_OP_NOMEM 1
+#define SN_HWPERF_OP_NO_PERM 2
+#define SN_HWPERF_OP_IO_ERROR 3
+#define SN_HWPERF_OP_BUSY 4
+#define SN_HWPERF_OP_RECONFIGURE 253
+#define SN_HWPERF_OP_INVAL 254
+
+#endif /* SN_HWPERF_H */
--- /dev/null
+#ifndef _ASM_M32R_A_OUT_H
+#define _ASM_M32R_A_OUT_H
+
+/* orig : i386 2.4.18 */
+
+struct exec
+{
+ unsigned long a_info; /* Use macros N_MAGIC, etc for access */
+ unsigned a_text; /* length of text, in bytes */
+ unsigned a_data; /* length of data, in bytes */
+ unsigned a_bss; /* length of uninitialized data area for file, in bytes */
+ unsigned a_syms; /* length of symbol table data in file, in bytes */
+ unsigned a_entry; /* start address */
+ unsigned a_trsize; /* length of relocation info for text, in bytes */
+ unsigned a_drsize; /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a) ((a).a_trsize)
+#define N_DRSIZE(a) ((a).a_drsize)
+#define N_SYMSIZE(a) ((a).a_syms)
+
+#ifdef __KERNEL__
+
+#define STACK_TOP TASK_SIZE
+
+#endif
+
+#endif /* _ASM_M32R_A_OUT_H */
--- /dev/null
+/* $Id$ */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 by Hiroyuki Kondo
+ *
+ * Defitions for the address spaces of the M32R CPUs.
+ */
+#ifndef __ASM_M32R_ADDRSPACE_H
+#define __ASM_M32R_ADDRSPACE_H
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ */
+#define KUSEG 0x00000000
+#define KSEG0 0x80000000
+#define KSEG1 0xa0000000
+#define KSEG2 0xc0000000
+#define KSEG3 0xe0000000
+
+#define K0BASE KSEG0
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#ifndef __ASSEMBLY__
+#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000)
+#else
+#define KSEGX(a) ((a) & 0xe0000000)
+#endif
+
+/*
+ * Returns the physical address of a KSEG0/KSEG1 address
+ */
+#ifndef __ASSEMBLY__
+#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
+#else
+#define PHYSADDR(a) ((a) & 0x1fffffff)
+#endif
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#ifndef __ASSEMBLY__
+#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
+#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1))
+#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
+#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3))
+#else
+#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
+#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
+#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
+#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
+#endif
+
+#endif /* __ASM_M32R_ADDRSPACE_H */
--- /dev/null
+#ifndef _ASM_M32R_ASSEMBLER_H
+#define _ASM_M32R_ASSEMBLER_H
+
+/* $Id$ */
+
+/*
+ * linux/asm-m32r/assembler.h
+ *
+ * This file contains M32R architecture specific defines.
+ *
+ * Do not include any C declarations in this file - it is included by
+ * assembler source.
+ */
+
+#include <linux/config.h>
+
+
+#undef ENTRY
+#define ENTRY(name) ENTRY_M name
+ .macro ENTRY_M name
+ .global \name
+ ALIGN
+\name:
+ .endm
+
+/*
+ * LDIMM: load immediate value
+ *
+ * STI: enable interruption
+ * CLI: disable interruption
+ */
+
+#ifdef __ASSEMBLY__
+
+#define LDIMM(reg,x) LDIMM reg x
+ .macro LDIMM reg x
+ seth \reg, #high(\x)
+ or3 \reg, \reg, #low(\x)
+ .endm
+
+#if !defined(CONFIG_CHIP_M32102)
+#define STI(reg) STI_M reg
+ .macro STI_M reg
+ setpsw #0x40 -> nop
+ ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
+ .endm
+
+#define CLI(reg) CLI_M reg
+ .macro CLI_M reg
+ clrpsw #0x40 -> nop
+ ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
+ .endm
+#else /* CONFIG_CHIP_M32102 */
+#define STI(reg) STI_M reg
+ .macro STI_M reg
+ mvfc \reg, psw
+ or3 \reg, \reg, #0x0040
+ mvtc \reg, psw
+ .endm
+
+#define CLI(reg) CLI_M reg
+ .macro CLI_M reg
+ mvfc \reg, psw
+ and3 \reg, \reg, #0xffbf
+ mvtc \reg, psw
+ .endm
+#endif /* CONFIG_CHIP_M32102 */
+
+ .macro SAVE_ALL
+ push r0 ; orig_r0
+ push sp ; spi (r15)
+ push lr ; r14
+ push r13
+ mvfc r13, cr3 ; spu
+ push r13
+ mvfc r13, bbpc
+ push r13
+ mvfc r13, bbpsw
+ push r13
+ mvfc r13, bpc
+ push r13
+ mvfc r13, psw
+ push r13
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ mvfaclo r13, a1
+ push r13
+ mvfachi r13, a1
+ push r13
+ mvfaclo r13, a0
+ push r13
+ mvfachi r13, a0
+ push r13
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ mvfaclo r13
+ push r13
+ mvfachi r13
+ push r13
+#else
+#error unknown isa configuration
+#endif
+ ldi r13, #-1
+ push r13 ; syscall_nr (default: -1)
+ push r12
+ push r11
+ push r10
+ push r9
+ push r8
+ push r7
+ push r3
+ push r2
+ push r1
+ push r0
+ addi sp, #-4 ; room for implicit pt_regs parameter
+ push r6
+ push r5
+ push r4
+ .endm
+
+ .macro RESTORE_ALL
+ pop r4
+ pop r5
+ pop r6
+ addi sp, #4
+ pop r0
+ pop r1
+ pop r2
+ pop r3
+ pop r7
+ pop r8
+ pop r9
+ pop r10
+ pop r11
+ pop r12
+ addi r15, #4 ; Skip syscall number
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ pop r13
+ mvtachi r13, a0
+ pop r13
+ mvtaclo r13, a0
+ pop r13
+ mvtachi r13, a1
+ pop r13
+ mvtaclo r13, a1
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ pop r13
+ mvtachi r13
+ pop r13
+ mvtaclo r13
+#else
+#error unknown isa configuration
+#endif
+ pop r14
+ mvtc r14, psw
+ pop r14
+ mvtc r14, bpc
+ addi sp, #8 ; Skip bbpsw, bbpc
+ pop r14
+ mvtc r14, cr3 ; spu
+ pop r13
+ pop lr ; r14
+ pop sp ; spi (r15)
+ addi sp, #4 ; Skip orig_r0
+ .fillinsn
+1: rte
+ .section .fixup,"ax"
+2: bl do_exit
+ .previous
+ .section __ex_table,"a"
+ ALIGN
+ .long 1b, 2b
+ .previous
+ .endm
+
+#define GET_CURRENT(reg) get_current reg
+ .macro get_current reg
+ ldi \reg, #-8192
+ and \reg, sp
+ .endm
+
+#if !defined(CONFIG_CHIP_M32102)
+ .macro SWITCH_TO_KERNEL_STACK
+ ; switch to kernel stack (spi)
+ clrpsw #0x80 -> nop
+ .endm
+#else /* CONFIG_CHIP_M32102 */
+ .macro SWITCH_TO_KERNEL_STACK
+ push r0 ; save r0 for working
+ mvfc r0, psw
+ and3 r0, r0, #0x00ff7f
+ mvtc r0, psw
+ slli r0, #16
+ bltz r0, 1f ; check BSM-bit
+;
+ ;; called from kernel context: previous stack = spi
+ pop r0 ; retrieve r0
+ bra 2f
+ .fillinsn
+1:
+ ;; called from user context: previous stack = spu
+ mvfc r0, cr3 ; spu
+ addi r0, #4
+ mvtc r0, cr3 ; spu
+ ld r0, @(-4,r0) ; retrieve r0
+ .fillinsn
+2:
+ .endm
+#endif /* CONFIG_CHIP_M32102 */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_M32R_ASSEMBLER_H */
+
--- /dev/null
+#ifndef _ASM_M32R_ATOMIC_H
+#define _ASM_M32R_ATOMIC_H
+
+/*
+ * linux/include/asm-m32r/atomic.h
+ *
+ * M32R version:
+ * Copyright (C) 2001, 2002 Hitoshi Yamamoto
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <linux/config.h>
+#include <asm/system.h>
+
+/*
+ * Atomic operations that C can't guarantee us. Useful for
+ * resource counting etc..
+ */
+
+#undef LOAD
+#undef STORE
+#ifdef CONFIG_SMP
+#define LOAD "lock"
+#define STORE "unlock"
+#else
+#define LOAD "ld"
+#define STORE "st"
+#endif
+
+/*
+ * Make sure gcc doesn't try to be clever and move things around
+ * on us. We need to use _exactly_ the address the user gave us,
+ * not some alias that contains the same information.
+ */
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i) { (i) }
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+#define atomic_read(v) ((v)->counter)
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+#define atomic_set(v,i) (((v)->counter) = (i))
+
+/**
+ * atomic_add_return - add integer to atomic variable and return it
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v and return (@i + @v).
+ */
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+ unsigned long flags;
+ int result;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# atomic_add_return \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "add %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (result)
+ : "r" (&v->counter), "r" (i)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ return result;
+}
+
+/**
+ * atomic_sub_return - subtract integer from atomic variable and return it
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and return (@v - @i).
+ */
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+ unsigned long flags;
+ int result;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# atomic_sub_return \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "sub %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (result)
+ : "r" (&v->counter), "r" (i)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ return result;
+}
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+#define atomic_add(i,v) ((void) atomic_add_return((i), (v)))
+
+/**
+ * atomic_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+#define atomic_sub(i,v) ((void) atomic_sub_return((i), (v)))
+
+/**
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
+
+/**
+ * atomic_inc_return - increment atomic variable and return it
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1 and returns the result.
+ */
+static inline int atomic_inc_return(atomic_t *v)
+{
+ unsigned long flags;
+ int result;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# atomic_inc_return \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "addi %0, #1; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (result)
+ : "r" (&v->counter)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ return result;
+}
+
+/**
+ * atomic_dec_return - decrement atomic variable and return it
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1 and returns the result.
+ */
+static inline int atomic_dec_return(atomic_t *v)
+{
+ unsigned long flags;
+ int result;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# atomic_dec_return \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "addi %0, #-1; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (result)
+ : "r" (&v->counter)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ return result;
+}
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc(v) ((void)atomic_inc_return(v))
+
+/**
+ * atomic_dec - decrement atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic_dec(v) ((void)atomic_dec_return(v))
+
+/**
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+/**
+ * atomic_dec_and_test - decrement and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all
+ * other cases.
+ */
+#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
+
+/**
+ * atomic_add_negative - add and test if negative
+ * @v: pointer of type atomic_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0)
+
+static inline void atomic_clear_mask(unsigned long mask, atomic_t *addr)
+{
+ unsigned long flags;
+ unsigned long tmp;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# atomic_clear_mask \n\t"
+ DCACHE_CLEAR("%0", "r5", "%1")
+ LOAD" %0, @%1; \n\t"
+ "and %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (tmp)
+ : "r" (addr), "r" (~mask)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r5"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+}
+
+static inline void atomic_set_mask(unsigned long mask, atomic_t *addr)
+{
+ unsigned long flags;
+ unsigned long tmp;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# atomic_set_mask \n\t"
+ DCACHE_CLEAR("%0", "r5", "%1")
+ LOAD" %0, @%1; \n\t"
+ "or %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (tmp)
+ : "r" (addr), "r" (mask)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r5"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+}
+
+/* Atomic operations are already serializing on m32r */
+#define smp_mb__before_atomic_dec() barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc() barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#endif /* _ASM_M32R_ATOMIC_H */
+
--- /dev/null
+#ifndef _ASM_M32R_BITOPS_H
+#define _ASM_M32R_BITOPS_H
+
+/*
+ * linux/include/asm-m32r/bitops.h
+ *
+ * Copyright 1992, Linus Torvalds.
+ *
+ * M32R version:
+ * Copyright (C) 2001, 2002 Hitoshi Yamamoto
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <asm/system.h>
+#include <asm/byteorder.h>
+#include <asm/types.h>
+
+/*
+ * These have to be done with inline assembly: that way the bit-setting
+ * is guaranteed to be atomic. All bit operations return 0 if the bit
+ * was cleared before the operation and != 0 if it was not.
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ */
+
+#undef LOAD
+#undef STORE
+#ifdef CONFIG_SMP
+#define LOAD "lock"
+#define STORE "unlock"
+#else
+#define LOAD "ld"
+#define STORE "st"
+#endif
+
+/* #define ADDR (*(volatile long *) addr) */
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered. See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(int nr, volatile void * addr)
+{
+ __u32 mask;
+ volatile __u32 *a = addr;
+ unsigned long flags;
+ unsigned long tmp;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "r6", "%1")
+ LOAD" %0, @%1; \n\t"
+ "or %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (tmp)
+ : "r" (a), "r" (mask)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+}
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __set_bit(int nr, volatile void * addr)
+{
+ __u32 mask;
+ volatile __u32 *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+ *a |= mask;
+}
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered. However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(int nr, volatile void * addr)
+{
+ __u32 mask;
+ volatile __u32 *a = addr;
+ unsigned long flags;
+ unsigned long tmp;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ local_irq_save(flags);
+
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "r6", "%1")
+ LOAD" %0, @%1; \n\t"
+ "and %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (tmp)
+ : "r" (a), "r" (~mask)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+}
+
+static inline void __clear_bit(int nr, volatile unsigned long * addr)
+{
+ unsigned long mask;
+ volatile unsigned long *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+ *a &= ~mask;
+}
+
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit() barrier()
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __change_bit(int nr, volatile void * addr)
+{
+ __u32 mask;
+ volatile __u32 *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+ *a ^= mask;
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(int nr, volatile void * addr)
+{
+ __u32 mask;
+ volatile __u32 *a = addr;
+ unsigned long flags;
+ unsigned long tmp;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "r6", "%1")
+ LOAD" %0, @%1; \n\t"
+ "xor %0, %2; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (tmp)
+ : "r" (a), "r" (mask)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+ __u32 mask, oldbit;
+ volatile __u32 *a = addr;
+ unsigned long flags;
+ unsigned long tmp;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "%1", "%2")
+ LOAD" %0, @%2; \n\t"
+ "mv %1, %0; \n\t"
+ "and %0, %3; \n\t"
+ "or %1, %3; \n\t"
+ STORE" %1, @%2; \n\t"
+ : "=&r" (oldbit), "=&r" (tmp)
+ : "r" (a), "r" (mask)
+ : "memory"
+ );
+ local_irq_restore(flags);
+
+ return (oldbit != 0);
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_set_bit(int nr, volatile void * addr)
+{
+ __u32 mask, oldbit;
+ volatile __u32 *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+ oldbit = (*a & mask);
+ *a |= mask;
+
+ return (oldbit != 0);
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+ __u32 mask, oldbit;
+ volatile __u32 *a = addr;
+ unsigned long flags;
+ unsigned long tmp;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ local_irq_save(flags);
+
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "%1", "%3")
+ LOAD" %0, @%3; \n\t"
+ "mv %1, %0; \n\t"
+ "and %0, %2; \n\t"
+ "not %2, %2; \n\t"
+ "and %1, %2; \n\t"
+ STORE" %1, @%3; \n\t"
+ : "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
+ : "r" (a)
+ : "memory"
+ );
+ local_irq_restore(flags);
+
+ return (oldbit != 0);
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_clear_bit(int nr, volatile void * addr)
+{
+ __u32 mask, oldbit;
+ volatile __u32 *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+ oldbit = (*a & mask);
+ *a &= ~mask;
+
+ return (oldbit != 0);
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static inline int __test_and_change_bit(int nr, volatile void * addr)
+{
+ __u32 mask, oldbit;
+ volatile __u32 *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+ oldbit = (*a & mask);
+ *a ^= mask;
+
+ return (oldbit != 0);
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+ __u32 mask, oldbit;
+ volatile __u32 *a = addr;
+ unsigned long flags;
+ unsigned long tmp;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "%1", "%2")
+ LOAD" %0, @%2; \n\t"
+ "mv %1, %0; \n\t"
+ "and %0, %3; \n\t"
+ "xor %1, %3; \n\t"
+ STORE" %1, @%2; \n\t"
+ : "=&r" (oldbit), "=&r" (tmp)
+ : "r" (a), "r" (mask)
+ : "memory"
+ );
+ local_irq_restore(flags);
+
+ return (oldbit != 0);
+}
+
+#if 0 /* Fool kernel-doc since it doesn't do macros yet */
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static int test_bit(int nr, const volatile void * addr);
+#endif
+
+static inline int test_bit(int nr, const volatile void * addr)
+{
+ __u32 mask;
+ const volatile __u32 *a = addr;
+
+ a += (nr >> 5);
+ mask = (1 << (nr & 0x1F));
+
+ return ((*a & mask) != 0);
+}
+
+/**
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+ int k;
+
+ word = ~word;
+ k = 0;
+ if (!(word & 0x0000ffff)) { k += 16; word >>= 16; }
+ if (!(word & 0x000000ff)) { k += 8; word >>= 8; }
+ if (!(word & 0x0000000f)) { k += 4; word >>= 4; }
+ if (!(word & 0x00000003)) { k += 2; word >>= 2; }
+ if (!(word & 0x00000001)) { k += 1; }
+
+ return k;
+}
+
+/**
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
+/**
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+ unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+ unsigned long result = offset & ~31UL;
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (32-offset);
+ if (size < 32)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size & ~31UL) {
+ if (~(tmp = *(p++)))
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp |= ~0UL << size;
+found_middle:
+ return result + ffz(tmp);
+}
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+ int k = 0;
+
+ if (!(word & 0x0000ffff)) { k += 16; word >>= 16; }
+ if (!(word & 0x000000ff)) { k += 8; word >>= 8; }
+ if (!(word & 0x0000000f)) { k += 4; word >>= 4; }
+ if (!(word & 0x00000003)) { k += 2; word >>= 2; }
+ if (!(word & 0x00000001)) { k += 1;}
+
+ return k;
+}
+
+/*
+ * fls: find last bit set.
+ */
+#define fls(x) generic_fls(x)
+
+#ifdef __KERNEL__
+
+/*
+ * Every architecture must define this function. It's the fastest
+ * way of searching a 140-bit bitmap where the first 100 bits are
+ * unlikely to be set. It's guaranteed that at least one of the 140
+ * bits is cleared.
+ */
+static inline int sched_find_first_bit(unsigned long *b)
+{
+ if (unlikely(b[0]))
+ return __ffs(b[0]);
+ if (unlikely(b[1]))
+ return __ffs(b[1]) + 32;
+ if (unlikely(b[2]))
+ return __ffs(b[2]) + 64;
+ if (b[3])
+ return __ffs(b[3]) + 96;
+ return __ffs(b[4]) + 128;
+}
+
+/**
+ * find_next_bit - find the first set bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static inline unsigned long find_next_bit(const unsigned long *addr,
+ unsigned long size, unsigned long offset)
+{
+ unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+ unsigned int result = offset & ~31UL;
+ unsigned int tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = *p++;
+ tmp &= ~0UL << offset;
+ if (size < 32)
+ goto found_first;
+ if (tmp)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size >= 32) {
+ if ((tmp = *p++) != 0)
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp &= ~0UL >> (32 - size);
+ if (tmp == 0UL) /* Are any bits set? */
+ return result + size; /* Nope. */
+found_middle:
+ return result + __ffs(tmp);
+}
+
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+#define find_first_bit(addr, size) \
+ find_next_bit((addr), (size), 0)
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+#define ffs(x) generic_ffs(x)
+
+/**
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#ifdef __KERNEL__
+
+/*
+ * ext2_XXXX function
+ * orig: include/asm-sh/bitops.h
+ */
+
+#ifdef __LITTLE_ENDIAN__
+#define ext2_set_bit test_and_set_bit
+#define ext2_clear_bit __test_and_clear_bit
+#define ext2_test_bit test_bit
+#define ext2_find_first_zero_bit find_first_zero_bit
+#define ext2_find_next_zero_bit find_next_zero_bit
+#else
+static inline int ext2_set_bit(int nr, volatile void * addr)
+{
+ __u8 mask, oldbit;
+ volatile __u8 *a = addr;
+
+ a += (nr >> 3);
+ mask = (1 << (nr & 0x07));
+ oldbit = (*a & mask);
+ *a |= mask;
+
+ return (oldbit != 0);
+}
+
+static inline int ext2_clear_bit(int nr, volatile void * addr)
+{
+ __u8 mask, oldbit;
+ volatile __u8 *a = addr;
+
+ a += (nr >> 3);
+ mask = (1 << (nr & 0x07));
+ oldbit = (*a & mask);
+ *a &= ~mask;
+
+ return (oldbit != 0);
+}
+
+static inline int ext2_test_bit(int nr, const volatile void * addr)
+{
+ __u32 mask;
+ const volatile __u8 *a = addr;
+
+ a += (nr >> 3);
+ mask = (1 << (nr & 0x07));
+
+ return ((mask & *a) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+ ext2_find_next_zero_bit((addr), (size), 0)
+
+static inline unsigned long ext2_find_next_zero_bit(void *addr,
+ unsigned long size, unsigned long offset)
+{
+ unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+ unsigned long result = offset & ~31UL;
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if(offset) {
+ /* We hold the little endian value in tmp, but then the
+ * shift is illegal. So we could keep a big endian value
+ * in tmp, like this:
+ *
+ * tmp = __swab32(*(p++));
+ * tmp |= ~0UL >> (32-offset);
+ *
+ * but this would decrease preformance, so we change the
+ * shift:
+ */
+ tmp = *(p++);
+ tmp |= __swab32(~0UL >> (32-offset));
+ if(size < 32)
+ goto found_first;
+ if(~tmp)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while(size & ~31UL) {
+ if(~(tmp = *(p++)))
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if(!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ /* tmp is little endian, so we would have to swab the shift,
+ * see above. But then we have to swab tmp below for ffz, so
+ * we might as well do this here.
+ */
+ return result + ffz(__swab32(tmp) | (~0UL << size));
+found_middle:
+ return result + ffz(__swab32(tmp));
+}
+#endif
+
+#define ext2_set_bit_atomic(lock, nr, addr) \
+ ({ \
+ int ret; \
+ spin_lock(lock); \
+ ret = ext2_set_bit((nr), (addr)); \
+ spin_unlock(lock); \
+ ret; \
+ })
+
+#define ext2_clear_bit_atomic(lock, nr, addr) \
+ ({ \
+ int ret; \
+ spin_lock(lock); \
+ ret = ext2_clear_bit((nr), (addr)); \
+ spin_unlock(lock); \
+ ret; \
+ })
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) __set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_BITOPS_H */
--- /dev/null
+#ifndef _M32R_BUG_H
+#define _M32R_BUG_H
+
+#define BUG() do { \
+ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+} while (0)
+
+#define PAGE_BUG(page) do { BUG(); } while (0)
+
+#define BUG_ON(condition) \
+ do { if (unlikely((condition)!=0)) BUG(); } while(0)
+
+#define WARN_ON(condition) do { \
+ if (unlikely((condition)!=0)) { \
+ printk("Badness in %s at %s:%d\n", __FUNCTION__, \
+ __FILE__, __LINE__); \
+ dump_stack(); \
+ } \
+} while (0)
+
+#endif /* _M32R_BUG_H */
+
--- /dev/null
+#ifndef _ASM_M32R_BUGS_H
+#define _ASM_M32R_BUGS_H
+
+/* $Id$ */
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ * void check_bugs(void);
+ */
+#include <asm/processor.h>
+
+static void __init check_bugs(void)
+{
+ extern unsigned long loops_per_jiffy;
+
+ current_cpu_data.loops_per_jiffy = loops_per_jiffy;
+}
+
+#endif /* _ASM_M32R_BUGS_H */
--- /dev/null
+#ifndef _ASM_M32R_BYTEORDER_H
+#define _ASM_M32R_BYTEORDER_H
+
+/* $Id$ */
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#if defined(__LITTLE_ENDIAN__)
+# include <linux/byteorder/little_endian.h>
+#else
+# include <linux/byteorder/big_endian.h>
+#endif
+
+#endif /* _ASM_M32R_BYTEORDER_H */
--- /dev/null
+#ifndef _ASM_M32R_CACHE_H
+#define _ASM_M32R_CACHE_H
+
+/* $Id$ */
+
+/* L1 cache line size */
+#define L1_CACHE_SHIFT 4
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#define L1_CACHE_SHIFT_MAX 4
+
+#endif /* _ASM_M32R_CACHE_H */
--- /dev/null
+/*
+ * cachectl.h -- defines for M32R cache control system calls
+ *
+ * Copyright (C) 2003 by Kazuhiro Inaoka
+ */
+#ifndef __ASM_M32R_CACHECTL
+#define __ASM_M32R_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ *
+ * cacheflush() is currently fluch_cache_all().
+ */
+#define ICACHE (1<<0) /* flush instruction cache */
+#define DCACHE (1<<1) /* writeback and flush data cache */
+#define BCACHE (ICACHE|DCACHE) /* flush both caches */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE 0 /* make pages cacheable */
+#define UNCACHEABLE 1 /* make pages uncacheable */
+
+#endif /* __ASM_M32R_CACHECTL */
--- /dev/null
+#ifndef _ASM_M32R_CACHEFLUSH_H
+#define _ASM_M32R_CACHEFLUSH_H
+
+#include <linux/config.h>
+#include <linux/mm.h>
+
+extern void _flush_cache_all(void);
+extern void _flush_cache_copyback_all(void);
+
+#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP)
+#define flush_cache_all() do { } while (0)
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_range(vma, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr) do { } while (0)
+#define flush_dcache_page(page) do { } while (0)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#ifndef CONFIG_SMP
+#define flush_icache_range(start, end) _flush_cache_copyback_all()
+#define flush_icache_page(vma,pg) _flush_cache_copyback_all()
+#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_copyback_all()
+#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
+#else /* CONFIG_SMP */
+extern void smp_flush_cache_all(void);
+#define flush_icache_range(start, end) smp_flush_cache_all()
+#define flush_icache_page(vma,pg) smp_flush_cache_all()
+#define flush_icache_user_range(vma,pg,adr,len) smp_flush_cache_all()
+#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
+#endif /* CONFIG_SMP */
+#elif defined(CONFIG_CHIP_M32102)
+#define flush_cache_all() do { } while (0)
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_range(vma, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr) do { } while (0)
+#define flush_dcache_page(page) do { } while (0)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_range(start, end) _flush_cache_all()
+#define flush_icache_page(vma,pg) _flush_cache_all()
+#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_all()
+#define flush_cache_sigtramp(addr) _flush_cache_all()
+#else
+#define flush_cache_all() do { } while (0)
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_range(vma, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr) do { } while (0)
+#define flush_dcache_page(page) do { } while (0)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_range(start, end) do { } while (0)
+#define flush_icache_page(vma,pg) do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_sigtramp(addr) do { } while (0)
+#endif /* CONFIG_CHIP_* */
+
+#define flush_cache_vmap(start, end) do { } while (0)
+#define flush_cache_vunmap(start, end) do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do { \
+ memcpy(dst, src, len); \
+ flush_icache_user_range(vma, page, vaddr, len); \
+} while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+
+#endif /* _ASM_M32R_CACHEFLUSH_H */
+
--- /dev/null
+#ifdef __KERNEL__
+#ifndef _ASM_M32R_CHECKSUM_H
+#define _ASM_M32R_CHECKSUM_H
+
+/*
+ * include/asm-m32r/checksum.h
+ *
+ * IP/TCP/UDP checksum routines
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Some code taken from mips and parisc architecture.
+ *
+ * Copyright (C) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <linux/in6.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+asmlinkage unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
+
+/*
+ * The same as csum_partial, but copies from src while it checksums.
+ *
+ * Here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+extern unsigned int csum_partial_copy_nocheck(const char *src, char *dst,
+ int len, unsigned int sum);
+
+/*
+ * This is a new version of the above that records errors it finds in *errp,
+ * but continues and zeros thre rest of the buffer.
+ */
+extern unsigned int csum_partial_copy_from_user(const char __user *src,
+ char *dst,
+ int len, unsigned int sum,
+ int *err_ptr);
+
+/*
+ * Fold a partial checksum
+ */
+
+static inline unsigned int csum_fold(unsigned int sum)
+{
+ unsigned long tmpreg;
+ __asm__(
+ " sll3 %1, %0, #16 \n"
+ " cmp %0, %0 \n"
+ " addx %0, %1 \n"
+ " ldi %1, #0 \n"
+ " srli %0, #16 \n"
+ " addx %0, %1 \n"
+ " xor3 %0, %0, #0x0000ffff \n"
+ : "=r" (sum), "=&r" (tmpreg)
+ : "0" (sum)
+ : "cbit"
+ );
+ return sum;
+}
+
+/*
+ * This is a version of ip_compute_csum() optimized for IP headers,
+ * which always checksum on 4 octet boundaries.
+ */
+static inline unsigned short ip_fast_csum(unsigned char * iph,
+ unsigned int ihl) {
+ unsigned long sum, tmpreg0, tmpreg1;
+
+ __asm__ __volatile__(
+ " ld %0, @%1+ \n"
+ " addi %2, #-4 \n"
+ "# bgez %2, 2f \n"
+ " cmp %0, %0 \n"
+ " ld %3, @%1+ \n"
+ " ld %4, @%1+ \n"
+ " addx %0, %3 \n"
+ " ld %3, @%1+ \n"
+ " addx %0, %4 \n"
+ " addx %0, %3 \n"
+ " .fillinsn\n"
+ "1: \n"
+ " ld %4, @%1+ \n"
+ " addi %2, #-1 \n"
+ " addx %0, %4 \n"
+ " bgtz %2, 1b \n"
+ "\n"
+ " ldi %3, #0 \n"
+ " addx %0, %3 \n"
+ " .fillinsn\n"
+ "2: \n"
+ /* Since the input registers which are loaded with iph and ipl
+ are modified, we must also specify them as outputs, or gcc
+ will assume they contain their original values. */
+ : "=&r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmpreg0), "=&r" (tmpreg1)
+ : "1" (iph), "2" (ihl)
+ : "cbit", "memory");
+
+ return csum_fold(sum);
+}
+
+static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
+ unsigned long daddr,
+ unsigned short len,
+ unsigned short proto,
+ unsigned int sum)
+{
+#if defined(__LITTLE_ENDIAN)
+ unsigned long len_proto = (ntohs(len)<<16)+proto*256;
+#else
+ unsigned long len_proto = (proto<<16)+len;
+#endif
+ unsigned long tmpreg;
+
+ __asm__(
+ " cmp %0, %0 \n"
+ " addx %0, %2 \n"
+ " addx %0, %3 \n"
+ " addx %0, %4 \n"
+ " ldi %1, #0 \n"
+ " addx %0, %1 \n"
+ : "=r" (sum), "=&r" (tmpreg)
+ : "r" (daddr), "r" (saddr), "r" (len_proto), "0" (sum)
+ : "cbit"
+ );
+
+ return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline unsigned short int csum_tcpudp_magic(unsigned long saddr,
+ unsigned long daddr,
+ unsigned short len,
+ unsigned short proto,
+ unsigned int sum)
+{
+ return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+
+static inline unsigned short ip_compute_csum(unsigned char * buff, int len) {
+ return csum_fold (csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static inline unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
+ struct in6_addr *daddr,
+ __u16 len,
+ unsigned short proto,
+ unsigned int sum)
+{
+ unsigned long tmpreg0, tmpreg1, tmpreg2, tmpreg3;
+ __asm__(
+ " ld %1, @(%5) \n"
+ " ld %2, @(4,%5) \n"
+ " ld %3, @(8,%5) \n"
+ " ld %4, @(12,%5) \n"
+ " add %0, %1 \n"
+ " addx %0, %2 \n"
+ " addx %0, %3 \n"
+ " addx %0, %4 \n"
+ " ld %1, @(%6) \n"
+ " ld %2, @(4,%6) \n"
+ " ld %3, @(8,%6) \n"
+ " ld %4, @(12,%6) \n"
+ " addx %0, %1 \n"
+ " addx %0, %2 \n"
+ " addx %0, %3 \n"
+ " addx %0, %4 \n"
+ " addx %0, %7 \n"
+ " addx %0, %8 \n"
+ " ldi %1, #0 \n"
+ " addx %0, %1 \n"
+ : "=&r" (sum), "=&r" (tmpreg0), "=&r" (tmpreg1),
+ "=&r" (tmpreg2), "=&r" (tmpreg3)
+ : "r" (saddr), "r" (daddr),
+ "r" (htonl((__u32) (len))), "r" (htonl(proto)), "0" (sum)
+ : "cbit"
+ );
+
+ return csum_fold(sum);
+}
+
+#endif /* _ASM_M32R_CHECKSUM_H */
+#endif /* __KERNEL__ */
--- /dev/null
+#ifndef _ASM_M32R_CURRENT_H
+#define _ASM_M32R_CURRENT_H
+
+/* $Id$ */
+
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static __inline__ struct task_struct *get_current(void)
+{
+ return current_thread_info()->task;
+}
+
+#define current (get_current())
+
+#endif /* _ASM_M32R_CURRENT_H */
+
--- /dev/null
+#ifndef _ASM_M32R_DELAY_H
+#define _ASM_M32R_DELAY_H
+
+/* $Id$ */
+
+/*
+ * Copyright (C) 1993 Linus Torvalds
+ *
+ * Delay routines calling functions in arch/m32r/lib/delay.c
+ */
+
+extern void __bad_udelay(void);
+extern void __bad_ndelay(void);
+
+extern void __udelay(unsigned long usecs);
+extern void __ndelay(unsigned long nsecs);
+extern void __const_udelay(unsigned long usecs);
+extern void __delay(unsigned long loops);
+
+#define udelay(n) (__builtin_constant_p(n) ? \
+ ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c7ul)) : \
+ __udelay(n))
+
+#define ndelay(n) (__builtin_constant_p(n) ? \
+ ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
+ __ndelay(n))
+
+#endif /* _ASM_M32R_DELAY_H */
--- /dev/null
+#ifndef _ASM_M32R_DIV64
+#define _ASM_M32R_DIV64
+
+/* $Id$ */
+
+/* unsigned long long division.
+ * Input:
+ * unsigned long long n
+ * unsigned long base
+ * Output:
+ * n = n / base;
+ * return value = n % base;
+ */
+#define do_div(n, base) \
+({ \
+ unsigned long _res, _high, _mid, _low; \
+ \
+ _low = (n) & 0xffffffffUL; \
+ _high = (n) >> 32; \
+ if (_high) { \
+ _mid = (_high % (unsigned long)(base)) << 16; \
+ _high = _high / (unsigned long)(base); \
+ _mid += _low >> 16; \
+ _low &= 0x0000ffffUL; \
+ _low += (_mid % (unsigned long)(base)) << 16; \
+ _mid = _mid / (unsigned long)(base); \
+ _res = _low % (unsigned long)(base); \
+ _low = _low / (unsigned long)(base); \
+ n = _low + ((long long)_mid << 16) + \
+ ((long long)_high << 32); \
+ } else { \
+ _res = _low % (unsigned long)(base); \
+ n = (_low / (unsigned long)(base)); \
+ } \
+ _res; \
+})
+
+#endif /* _ASM_M32R_DIV64 */
--- /dev/null
+#ifndef _ASM_M32R_DMA_MAPPING_H
+#define _ASM_M32R_DMA_MAPPING_H
+
+/*
+ * NOTE: Do not include <asm-generic/dma-mapping.h>
+ * Because it requires PCI stuffs, but current M32R don't provide these.
+ */
+
+static inline void *
+dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
+ int flag)
+{
+ return (void *)NULL;
+}
+
+static inline void
+dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
+ dma_addr_t dma_handle)
+{
+ return;
+}
+
+#endif /* _ASM_M32R_DMA_MAPPING_H */
--- /dev/null
+#ifndef _ASM_M32R_DMA_H
+#define _ASM_M32R_DMA_H
+
+/* $Id$ */
+
+#include <asm/io.h>
+
+/*
+ * The maximum address that we can perform a DMA transfer
+ * to on this platform
+ */
+#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x20000000)
+
+#endif /* _ASM_M32R_DMA_H */
--- /dev/null
+#ifndef _ASM_M32R__ELF_H
+#define _ASM_M32R__ELF_H
+
+/*
+ * ELF-specific definitions.
+ *
+ * Copyright (C) 1999-2004, Renesas Technology Corp.
+ * Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <asm/ptrace.h>
+#include <asm/user.h>
+#include <asm/page.h>
+
+/* M32R relocation types */
+#define R_M32R_NONE 0
+#define R_M32R_16 1
+#define R_M32R_32 2
+#define R_M32R_24 3
+#define R_M32R_10_PCREL 4
+#define R_M32R_18_PCREL 5
+#define R_M32R_26_PCREL 6
+#define R_M32R_HI16_ULO 7
+#define R_M32R_HI16_SLO 8
+#define R_M32R_LO16 9
+#define R_M32R_SDA16 10
+#ifdef OLD_TYPE
+#define R_M32R_GOT24 11
+#define R_M32R_26_PLTREL 12
+#define R_M32R_GOT16_HI_ULO 13
+#define R_M32R_GOT16_HI_SLO 14
+#define R_M32R_GOT16_LO 15
+#define R_M32R_GOTPC24 16
+#define R_M32R_COPY 17
+#define R_M32R_GLOB_DAT 18
+#define R_M32R_JMP_SLOT 19
+#define R_M32R_RELATIVE 20
+#define R_M32R_GNU_VTINHERIT 21
+#define R_M32R_GNU_VTENTRY 22
+
+#define R_M32R_16_RELA R_M32R_16
+#define R_M32R_32_RELA R_M32R_32
+#define R_M32R_24_RELA R_M32R_24
+#define R_M32R_10_PCREL_RELA R_M32R_10_PCREL
+#define R_M32R_18_PCREL_RELA R_M32R_18_PCREL
+#define R_M32R_26_PCREL_RELA R_M32R_26_PCREL
+#define R_M32R_HI16_ULO_RELA R_M32R_HI16_ULO
+#define R_M32R_HI16_SLO_RELA R_M32R_HI16_SLO
+#define R_M32R_LO16_RELA R_M32R_LO16
+#define R_M32R_SDA16_RELA R_M32R_SDA16
+#else /* not OLD_TYPE */
+#define R_M32R_GNU_VTINHERIT 11
+#define R_M32R_GNU_VTENTRY 12
+
+#define R_M32R_GOT24_SAMPLE 11 /* comflict */
+#define R_M32R_26_PLTREL_SAMPLE 12 /* comflict */
+#define R_M32R_GOT16_HI_ULO_SAMPLE 13
+#define R_M32R_GOT16_HI_SLO_SAMPLE 14
+#define R_M32R_GOT16_LO_SAMPLE 15
+#define R_M32R_GOTPC24_SAMPLE 16
+#define R_M32R_COPY_SAMPLE 17
+#define R_M32R_GLOB_DAT_SAMPLE 18
+#define R_M32R_JMP_SLOT_SAMPLE 19
+#define R_M32R_RELATIVE_SAMPLE 20
+#define R_M32R_GNU_VTINHERIT_SAMPLE 21
+#define R_M32R_GNU_VTENTRY_SAMPLE 22
+
+#define R_M32R_16_RELA 33
+#define R_M32R_32_RELA 34
+#define R_M32R_24_RELA 35
+#define R_M32R_10_PCREL_RELA 36
+#define R_M32R_18_PCREL_RELA 37
+#define R_M32R_26_PCREL_RELA 38
+#define R_M32R_HI16_ULO_RELA 39
+#define R_M32R_HI16_SLO_RELA 40
+#define R_M32R_LO16_RELA 41
+#define R_M32R_SDA16_RELA 42
+#define R_M32R_RELA_GNU_VTINHERIT 43
+#define R_M32R_RELA_GNU_VTENTRY 44
+
+#define R_M32R_GOT24 48
+#define R_M32R_26_PLTREL 49
+#define R_M32R_COPY 50
+#define R_M32R_GLOB_DAT 51
+#define R_M32R_JMP_SLOT 52
+#define R_M32R_RELATIVE 53
+#define R_M32R_GOTOFF 54
+#define R_M32R_GOTPC24 55
+#define R_M32R_GOT16_HI_ULO 56
+#define R_M32R_GOT16_HI_SLO 57
+#define R_M32R_GOT16_LO 58
+#define R_M32R_GOTPC_HI_ULO 59
+#define R_M32R_GOTPC_HI_SLO 60
+#define R_M32R_GOTPC_LO 61
+#endif /* not OLD_TYPE */
+
+#define R_M32R_NUM 256
+
+/*
+ * ELF register definitions..
+ */
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* We have no FP mumumu. */
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) \
+ (((x)->e_machine == EM_M32R) || ((x)->e_machine == EM_CYGNUS_M32R))
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS ELFCLASS32
+#if defined(__LITTLE_ENDIAN)
+#define ELF_DATA ELFDATA2LSB
+#elif defined(__BIG_ENDIAN)
+#define ELF_DATA ELFDATA2MSB
+#else
+#error no endian defined
+#endif
+#define ELF_ARCH EM_M32R
+
+/* r0 is set by ld.so to a pointer to a function which might be
+ * registered using 'atexit'. This provides a mean for the dynamic
+ * linker to call DT_FINI functions for shared libraries that have
+ * been loaded before the code runs.
+ *
+ * So that we can use the same startup file with static executables,
+ * we start programs with a value of 0 to indicate that there is no
+ * such function.
+ */
+#define ELF_PLAT_INIT(_r, load_addr) (_r)->r0 = 0
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE PAGE_SIZE
+
+/*
+ * This is the location that an ET_DYN program is loaded if exec'ed.
+ * Typical use of this is to invoke "./ld.so someprog" to test out a
+ * new version of the loader. We need to make sure that it is out of
+ * the way of the program that it will "exec", and that there is
+ * sufficient room for the brk.
+ */
+#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
+
+/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
+ now struct_user_regs, they are different) */
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs) \
+ memcpy((char *)&pr_reg, (char *)®s, sizeof (struct pt_regs));
+
+/* This yields a mask that user programs can use to figure out what
+ instruction set this CPU supports. */
+#define ELF_HWCAP (0)
+
+/* This yields a string that ld.so will use to load implementation
+ specific libraries for optimization. This is more specific in
+ intent than poking at uname or /proc/cpuinfo. */
+#define ELF_PLATFORM (NULL)
+
+#ifdef __KERNEL__
+#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#endif
+
+#endif /* _ASM_M32R__ELF_H */
--- /dev/null
+#ifndef _ASM_M32R_ERRNO_H
+#define _ASM_M32R_ERRNO_H
+
+/* $Id$ */
+
+#include <asm-generic/errno.h>
+
+#endif /* _ASM_M32R_ERRNO_H */
+
--- /dev/null
+#ifndef _ASM_M32R_FCNTL_H
+#define _ASM_M32R_FCNTL_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+ located on an ext2 file system */
+#define O_ACCMODE 0003
+#define O_RDONLY 00
+#define O_WRONLY 01
+#define O_RDWR 02
+#define O_CREAT 0100 /* not fcntl */
+#define O_EXCL 0200 /* not fcntl */
+#define O_NOCTTY 0400 /* not fcntl */
+#define O_TRUNC 01000 /* not fcntl */
+#define O_APPEND 02000
+#define O_NONBLOCK 04000
+#define O_NDELAY O_NONBLOCK
+#define O_SYNC 010000
+#define FASYNC 020000 /* fcntl, for BSD compatibility */
+#define O_DIRECT 040000 /* direct disk access hint */
+#define O_LARGEFILE 0100000
+#define O_DIRECTORY 0200000 /* must be a directory */
+#define O_NOFOLLOW 0400000 /* don't follow links */
+#define O_NOATIME 01000000
+
+#define F_DUPFD 0 /* dup */
+#define F_GETFD 1 /* get close_on_exec */
+#define F_SETFD 2 /* set/clear close_on_exec */
+#define F_GETFL 3 /* get file->f_flags */
+#define F_SETFL 4 /* set file->f_flags */
+#define F_GETLK 5
+#define F_SETLK 6
+#define F_SETLKW 7
+
+#define F_SETOWN 8 /* for sockets. */
+#define F_GETOWN 9 /* for sockets. */
+#define F_SETSIG 10 /* for sockets. */
+#define F_GETSIG 11 /* for sockets. */
+
+#define F_GETLK64 12 /* using 'struct flock64' */
+#define F_SETLK64 13
+#define F_SETLKW64 14
+
+/* for F_[GET|SET]FL */
+#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK 0
+#define F_WRLCK 1
+#define F_UNLCK 2
+
+/* for old implementation of bsd flock () */
+#define F_EXLCK 4 /* or 3 */
+#define F_SHLCK 8 /* or 4 */
+
+/* for leases */
+#define F_INPROGRESS 16
+
+/* operations for bsd flock(), also used by the kernel implementation */
+#define LOCK_SH 1 /* shared lock */
+#define LOCK_EX 2 /* exclusive lock */
+#define LOCK_NB 4 /* or'd with one of the above to prevent
+ blocking */
+#define LOCK_UN 8 /* remove lock */
+
+#define LOCK_MAND 32 /* This is a mandatory flock */
+#define LOCK_READ 64 /* ... Which allows concurrent read operations */
+#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */
+#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */
+
+struct flock {
+ short l_type;
+ short l_whence;
+ off_t l_start;
+ off_t l_len;
+ pid_t l_pid;
+};
+
+struct flock64 {
+ short l_type;
+ short l_whence;
+ loff_t l_start;
+ loff_t l_len;
+ pid_t l_pid;
+};
+
+#define F_LINUX_SPECIFIC_BASE 1024
+
+#endif /* _ASM_M32R_FCNTL_H */
--- /dev/null
+/*
+ * include/asm-m32r/flat.h
+ *
+ * uClinux flat-format executables
+ *
+ * Copyright (C) 2004 Kazuhiro Inaoka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive for
+ * more details.
+ */
+#ifndef __ASM_M32R_FLAT_H
+#define __ASM_M32R_FLAT_H
+
+#define flat_stack_align(sp) (*sp += (*sp & 3 ? (4 - (*sp & 3)): 0))
+#define flat_argvp_envp_on_stack() 0
+#define flat_old_ram_flag(flags) (flags)
+#define flat_reloc_valid(reloc, size) \
+ (((reloc) - textlen_for_m32r_lo16_data) <= (size))
+#define flat_get_addr_from_rp(rp, relval, flags) \
+ m32r_flat_get_addr_from_rp(rp, relval, (text_len) )
+
+#define flat_put_addr_at_rp(rp, addr, relval) \
+ m32r_flat_put_addr_at_rp(rp, addr, relval)
+
+/* Convert a relocation entry into an address. */
+static inline unsigned long
+flat_get_relocate_addr (unsigned long relval)
+{
+ return relval & 0x00ffffff; /* Mask out top 8-bits */
+}
+
+#define flat_m32r_get_reloc_type(relval) ((relval) >> 24)
+
+#define M32R_SETH_OPCODE 0xd0c00000 /* SETH instruction code */
+
+#define FLAT_M32R_32 0x00 /* 32bits reloc */
+#define FLAT_M32R_24 0x01 /* unsigned 24bits reloc */
+#define FLAT_M32R_16 0x02 /* 16bits reloc */
+#define FLAT_M32R_LO16 0x03 /* signed low 16bits reloc (low()) */
+#define FLAT_M32R_LO16_DATA 0x04 /* signed low 16bits reloc (low())
+ for a symbol in .data section */
+ /* High 16bits of an address used
+ when the lower 16bbits are treated
+ as unsigned.
+ To create SETH instruction only.
+ 0x1X: X means a number of register.
+ 0x10 - 0x3F are reserved. */
+#define FLAT_M32R_HI16_ULO 0x10 /* reloc for SETH Rn,#high(imm16) */
+ /* High 16bits of an address used
+ when the lower 16bbits are treated
+ as signed.
+ To create SETH instruction only.
+ 0x2X: X means a number of register.
+ 0x20 - 0x4F are reserved. */
+#define FLAT_M32R_HI16_SLO 0x20 /* reloc for SETH Rn,#shigh(imm16) */
+
+static unsigned long textlen_for_m32r_lo16_data = 0;
+
+static inline unsigned long m32r_flat_get_addr_from_rp (unsigned long *rp,
+ unsigned long relval,
+ unsigned long textlen)
+{
+ unsigned int reloc = flat_m32r_get_reloc_type (relval);
+ textlen_for_m32r_lo16_data = 0;
+ if (reloc & 0xf0) {
+ unsigned long addr = htonl(*rp);
+ switch (reloc & 0xf0)
+ {
+ case FLAT_M32R_HI16_ULO:
+ case FLAT_M32R_HI16_SLO:
+ if (addr == 0) {
+ /* put "seth Rn,#0x0" instead of 0 (addr). */
+ *rp = (M32R_SETH_OPCODE | ((reloc & 0x0f)<<24));
+ }
+ return addr;
+ default:
+ break;
+ }
+ } else {
+ switch (reloc)
+ {
+ case FLAT_M32R_LO16:
+ return htonl(*rp) & 0xFFFF;
+ case FLAT_M32R_LO16_DATA:
+ /* FIXME: The return value will decrease by textlen
+ at m32r_flat_put_addr_at_rp () */
+ textlen_for_m32r_lo16_data = textlen;
+ return (htonl(*rp) & 0xFFFF) + textlen;
+ case FLAT_M32R_16:
+ return htons(*(unsigned short *)rp) & 0xFFFF;
+ case FLAT_M32R_24:
+ return htonl(*rp) & 0xFFFFFF;
+ case FLAT_M32R_32:
+ return htonl(*rp);
+ default:
+ break;
+ }
+ }
+ return ~0; /* bogus value */
+}
+
+static inline void m32r_flat_put_addr_at_rp (unsigned long *rp,
+ unsigned long addr,
+ unsigned long relval)
+{
+ unsigned int reloc = flat_m32r_get_reloc_type (relval);
+ if (reloc & 0xf0) {
+ unsigned long Rn = reloc & 0x0f; /* get a number of register */
+ Rn <<= 24; /* 0x0R000000 */
+ reloc &= 0xf0;
+ switch (reloc)
+ {
+ case FLAT_M32R_HI16_ULO: /* To create SETH Rn,#high(imm16) */
+ *rp = (M32R_SETH_OPCODE | Rn
+ | ((addr >> 16) & 0xFFFF));
+ break;
+ case FLAT_M32R_HI16_SLO: /* To create SETH Rn,#shigh(imm16) */
+ *rp = (M32R_SETH_OPCODE | Rn
+ | (((addr >> 16) + ((addr & 0x8000) ? 1 : 0))
+ & 0xFFFF));
+ break;
+ }
+ } else {
+ switch (reloc) {
+ case FLAT_M32R_LO16_DATA:
+ addr -= textlen_for_m32r_lo16_data;
+ textlen_for_m32r_lo16_data = 0;
+ case FLAT_M32R_LO16:
+ *rp = (htonl(*rp) & 0xFFFF0000) | (addr & 0xFFFF);
+ break;
+ case FLAT_M32R_16:
+ *(unsigned short *)rp = addr & 0xFFFF;
+ break;
+ case FLAT_M32R_24:
+ *rp = (htonl(*rp) & 0xFF000000) | (addr & 0xFFFFFF);
+ break;
+ case FLAT_M32R_32:
+ *rp = addr;
+ break;
+ }
+ }
+}
+
+#endif /* __ASM_M32R_FLAT_H */
--- /dev/null
+#ifndef __ASM_HARDIRQ_H
+#define __ASM_HARDIRQ_H
+
+#include <linux/config.h>
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+typedef struct {
+ unsigned int __softirq_pending;
+ unsigned int __syscall_count;
+ struct task_struct * __ksoftirqd_task; /* waitqueue is too large */
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
+
+/*
+ * We put the hardirq and softirq counter into the preemption
+ * counter. The bitmask has the following meaning:
+ *
+ * - bits 0-7 are the preemption count (max preemption depth: 256)
+ * - bits 8-15 are the softirq count (max # of softirqs: 256)
+ * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
+ *
+ * - ( bit 26 is the PREEMPT_ACTIVE flag. )
+ *
+ * PREEMPT_MASK: 0x000000ff
+ * SOFTIRQ_MASK: 0x0000ff00
+ * HARDIRQ_MASK: 0x00ff0000
+ */
+
+#define PREEMPT_BITS 8
+#define SOFTIRQ_BITS 8
+
+#if NR_IRQS > 256
+#define HARDIRQ_BITS 9
+#else
+#define HARDIRQ_BITS 8
+#endif
+
+#define PREEMPT_SHIFT 0
+#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS)
+#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS)
+
+/*
+ * The hardirq mask has to be large enough to have
+ * space for potentially all IRQ sources in the system
+ * nesting on a single CPU:
+ */
+#if (1 << HARDIRQ_BITS) < NR_IRQS
+# error HARDIRQ_BITS is too low!
+#endif
+
+#define irq_enter() (preempt_count() += HARDIRQ_OFFSET)
+#define nmi_enter() (irq_enter())
+#define nmi_exit() (preempt_count() -= HARDIRQ_OFFSET)
+
+#define irq_exit() \
+do { \
+ preempt_count() -= IRQ_EXIT_OFFSET; \
+ if (!in_interrupt() && softirq_pending(smp_processor_id())) \
+ do_softirq(); \
+ preempt_enable_no_resched(); \
+} while (0)
+
+#endif /* __ASM_HARDIRQ_H */
--- /dev/null
+#include <asm-generic/hdreg.h>
--- /dev/null
+#ifndef _ASM_M32R_HW_IRQ_H
+#define _ASM_M32R_HW_IRQ_H
+
+static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
+{
+ /* Nothing to do */
+}
+
+#endif /* _ASM_M32R_HW_IRQ_H */
--- /dev/null
+#ifndef _ASM_M32R_IDE_H
+#define _ASM_M32R_IDE_H
+
+/* $Id$ */
+
+/*
+ * linux/include/asm-m32r/ide.h
+ *
+ * Copyright (C) 1994-1996 Linus Torvalds & authors
+ */
+
+/*
+ * This file contains the i386 architecture specific IDE code.
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#ifndef MAX_HWIFS
+# ifdef CONFIG_BLK_DEV_IDEPCI
+#define MAX_HWIFS 10
+# else
+#define MAX_HWIFS 2
+# endif
+#endif
+
+#if defined(CONFIG_PLAT_M32700UT)
+#include <asm/irq.h>
+#include <asm/m32700ut/m32700ut_pld.h>
+#endif
+
+#define IDE_ARCH_OBSOLETE_DEFAULTS
+
+static __inline__ int ide_default_irq(unsigned long base)
+{
+ switch (base) {
+#if defined(CONFIG_PLAT_M32700UT)
+ case 0x1f0: return PLD_IRQ_CFIREQ;
+ default:
+ return 0;
+#else
+ case 0x1f0: return 14;
+ case 0x170: return 15;
+ case 0x1e8: return 11;
+ case 0x168: return 10;
+ case 0x1e0: return 8;
+ case 0x160: return 12;
+ default:
+ return 0;
+#endif
+ }
+}
+
+static __inline__ unsigned long ide_default_io_base(int index)
+{
+ switch (index) {
+ case 0: return 0x1f0;
+ case 1: return 0x170;
+ case 2: return 0x1e8;
+ case 3: return 0x168;
+ case 4: return 0x1e0;
+ case 5: return 0x160;
+ default:
+ return 0;
+ }
+}
+
+#define IDE_ARCH_OBSOLETE_INIT
+#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
+
+#ifdef CONFIG_BLK_DEV_IDEPCI
+#define ide_init_default_irq(base) (0)
+#else
+#define ide_init_default_irq(base) ide_default_irq(base)
+#endif
+
+#include <asm-generic/ide_iops.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_IDE_H */
--- /dev/null
+#ifndef _ASM_M32R_IO_H
+#define _ASM_M32R_IO_H
+
+#include <linux/string.h>
+#include <linux/compiler.h>
+#include <asm/page.h> /* __va */
+
+#ifdef __KERNEL__
+
+#define IO_SPACE_LIMIT 0xFFFFFFFF
+
+/**
+ * virt_to_phys - map virtual addresses to physical
+ * @address: address to remap
+ *
+ * The returned physical address is the physical (CPU) mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses directly mapped or allocated via kmalloc.
+ *
+ * This function does not give bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+
+static inline unsigned long virt_to_phys(volatile void * address)
+{
+ return __pa(address);
+}
+
+/**
+ * phys_to_virt - map physical address to virtual
+ * @address: address to remap
+ *
+ * The returned virtual address is a current CPU mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses that have a kernel mapping
+ *
+ * This function does not handle bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+
+static inline void *phys_to_virt(unsigned long address)
+{
+ return __va(address);
+}
+
+extern void __iomem *
+__ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+
+/**
+ * ioremap - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ */
+
+static inline void * ioremap(unsigned long offset, unsigned long size)
+{
+ return __ioremap(offset, size, 0);
+}
+
+extern void iounmap(volatile void __iomem *addr);
+#define ioremap_nocache(off,size) ioremap(off,size)
+
+/*
+ * IO bus memory addresses are also 1:1 with the physical address
+ */
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
+#define page_to_bus page_to_phys
+#define virt_to_bus virt_to_phys
+
+extern unsigned char _inb(unsigned long);
+extern unsigned short _inw(unsigned long);
+extern unsigned long _inl(unsigned long);
+extern unsigned char _inb_p(unsigned long);
+extern unsigned short _inw_p(unsigned long);
+extern unsigned long _inl_p(unsigned long);
+extern void _outb(unsigned char, unsigned long);
+extern void _outw(unsigned short, unsigned long);
+extern void _outl(unsigned long, unsigned long);
+extern void _outb_p(unsigned char, unsigned long);
+extern void _outw_p(unsigned short, unsigned long);
+extern void _outl_p(unsigned long, unsigned long);
+extern void _insb(unsigned int, void *, unsigned long);
+extern void _insw(unsigned int, void *, unsigned long);
+extern void _insl(unsigned int, void *, unsigned long);
+extern void _outsb(unsigned int, const void *, unsigned long);
+extern void _outsw(unsigned int, const void *, unsigned long);
+extern void _outsl(unsigned int, const void *, unsigned long);
+
+static inline unsigned char _readb(unsigned long addr)
+{
+ return *(volatile unsigned char __force *)addr;
+}
+
+static inline unsigned short _readw(unsigned long addr)
+{
+ return *(volatile unsigned short __force *)addr;
+}
+
+static inline unsigned long _readl(unsigned long addr)
+{
+ return *(volatile unsigned long __force *)addr;
+}
+
+static inline void _writeb(unsigned char b, unsigned long addr)
+{
+ *(volatile unsigned char __force *)addr = b;
+}
+
+static inline void _writew(unsigned short w, unsigned long addr)
+{
+ *(volatile unsigned short __force *)addr = w;
+}
+
+static inline void _writel(unsigned long l, unsigned long addr)
+{
+ *(volatile unsigned long __force *)addr = l;
+}
+
+#define inb _inb
+#define inw _inw
+#define inl _inl
+#define outb _outb
+#define outw _outw
+#define outl _outl
+
+#define inb_p _inb_p
+#define inw_p _inw_p
+#define inl_p _inl_p
+#define outb_p _outb_p
+#define outw_p _outw_p
+#define outl_p _outl_p
+
+#define insb _insb
+#define insw _insw
+#define insl _insl
+#define outsb _outsb
+#define outsw _outsw
+#define outsl _outsl
+
+#define readb(addr) _readb((unsigned long)(addr))
+#define readw(addr) _readw((unsigned long)(addr))
+#define readl(addr) _readl((unsigned long)(addr))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+
+#define writeb(val, addr) _writeb((val), (unsigned long)(addr))
+#define writew(val, addr) _writew((val), (unsigned long)(addr))
+#define writel(val, addr) _writel((val), (unsigned long)(addr))
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+#define flush_write_buffers() do { } while (0) /* M32R_FIXME */
+
+/**
+ * isa_check_signature - find BIOS signatures
+ * @io_addr: mmio address to check
+ * @signature: signature block
+ * @length: length of signature
+ *
+ * Perform a signature comparison with the ISA mmio address io_addr.
+ * Returns 1 on a match.
+ *
+ * This function is deprecated. New drivers should use ioremap and
+ * check_signature.
+ */
+
+static inline int isa_check_signature(unsigned long io_addr,
+ const unsigned char *signature, int length)
+{
+ int retval = 0;
+#if 0
+printk("isa_check_signature\n");
+ do {
+ if (isa_readb(io_addr) != *signature)
+ goto out;
+ io_addr++;
+ signature++;
+ length--;
+ } while (length);
+ retval = 1;
+out:
+#endif
+ return retval;
+}
+
+static inline void
+memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+ memset((void __force *) addr, val, count);
+}
+
+static inline void
+memcpy_fromio(void *dst, volatile void __iomem *src, int count)
+{
+ memcpy(dst, (void __force *) src, count);
+}
+
+static inline void
+memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+ memcpy((void __force *) dst, src, count);
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_IO_H */
--- /dev/null
+#ifndef _ASM_M32R_IOCTL_H
+#define _ASM_M32R_IOCTL_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * linux/ioctl.h for Linux by H.H. Bergman.
+ */
+
+/* ioctl command encoding: 32 bits total, command in lower 16 bits,
+ * size of the parameter structure in the lower 14 bits of the
+ * upper 16 bits.
+ * Encoding the size of the parameter structure in the ioctl request
+ * is useful for catching programs compiled with old versions
+ * and to avoid overwriting user space outside the user buffer area.
+ * The highest 2 bits are reserved for indicating the ``access mode''.
+ * NOTE: This limits the max parameter size to 16kB -1 !
+ */
+
+/*
+ * The following is for compatibility across the various Linux
+ * platforms. The i386 ioctl numbering scheme doesn't really enforce
+ * a type field. De facto, however, the top 8 bits of the lower 16
+ * bits are indeed used as a type field, so we might just as well make
+ * this explicit here. Please be sure to use the decoding macros
+ * below from now on.
+ */
+#define _IOC_NRBITS 8
+#define _IOC_TYPEBITS 8
+#define _IOC_SIZEBITS 14
+#define _IOC_DIRBITS 2
+
+#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT 0
+#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits.
+ */
+#define _IOC_NONE 0U
+#define _IOC_WRITE 1U
+#define _IOC_READ 2U
+
+#define _IOC(dir,type,nr,size) \
+ (((dir) << _IOC_DIRSHIFT) | \
+ ((type) << _IOC_TYPESHIFT) | \
+ ((nr) << _IOC_NRSHIFT) | \
+ ((size) << _IOC_SIZESHIFT))
+
+/* used to create numbers */
+#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode ioctl numbers.. */
+#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
+
+#endif /* _ASM_M32R_IOCTL_H */
--- /dev/null
+#ifndef __ARCH_M32R_IOCTLS_H__
+#define __ARCH_M32R_IOCTLS_H__
+
+/* $Id$ */
+
+/* orig : i386 2.5.67 */
+
+#include <asm/ioctl.h>
+
+/* 0x54 is just a magic number to make these relatively unique ('T') */
+
+#define TCGETS 0x5401
+#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define TCSETSW 0x5403
+#define TCSETSF 0x5404
+#define TCGETA 0x5405
+#define TCSETA 0x5406
+#define TCSETAW 0x5407
+#define TCSETAF 0x5408
+#define TCSBRK 0x5409
+#define TCXONC 0x540A
+#define TCFLSH 0x540B
+#define TIOCEXCL 0x540C
+#define TIOCNXCL 0x540D
+#define TIOCSCTTY 0x540E
+#define TIOCGPGRP 0x540F
+#define TIOCSPGRP 0x5410
+#define TIOCOUTQ 0x5411
+#define TIOCSTI 0x5412
+#define TIOCGWINSZ 0x5413
+#define TIOCSWINSZ 0x5414
+#define TIOCMGET 0x5415
+#define TIOCMBIS 0x5416
+#define TIOCMBIC 0x5417
+#define TIOCMSET 0x5418
+#define TIOCGSOFTCAR 0x5419
+#define TIOCSSOFTCAR 0x541A
+#define FIONREAD 0x541B
+#define TIOCINQ FIONREAD
+#define TIOCLINUX 0x541C
+#define TIOCCONS 0x541D
+#define TIOCGSERIAL 0x541E
+#define TIOCSSERIAL 0x541F
+#define TIOCPKT 0x5420
+#define FIONBIO 0x5421
+#define TIOCNOTTY 0x5422
+#define TIOCSETD 0x5423
+#define TIOCGETD 0x5424
+#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
+/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */
+#define TIOCSBRK 0x5427 /* BSD compatibility */
+#define TIOCCBRK 0x5428 /* BSD compatibility */
+#define TIOCGSID 0x5429 /* Return the session ID of FD */
+#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
+
+#define FIONCLEX 0x5450
+#define FIOCLEX 0x5451
+#define FIOASYNC 0x5452
+#define TIOCSERCONFIG 0x5453
+#define TIOCSERGWILD 0x5454
+#define TIOCSERSWILD 0x5455
+#define TIOCGLCKTRMIOS 0x5456
+#define TIOCSLCKTRMIOS 0x5457
+#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
+#define TIOCSERGETLSR 0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
+#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
+#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
+#define FIOQSIZE 0x5460
+
+/* Used for packet mode */
+#define TIOCPKT_DATA 0
+#define TIOCPKT_FLUSHREAD 1
+#define TIOCPKT_FLUSHWRITE 2
+#define TIOCPKT_STOP 4
+#define TIOCPKT_START 8
+#define TIOCPKT_NOSTOP 16
+#define TIOCPKT_DOSTOP 32
+
+#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
+
+#endif /* __ARCH_M32R_IOCTLS_H__ */
+
--- /dev/null
+#ifndef __M32R_IPC_H__
+#define __M32R_IPC_H__
+
+/* orig : i386/ipc.h 2.6.0-test3 */
+
+/*
+ * These are used to wrap system calls on x86.
+ *
+ * See arch/i386/kernel/sys_i386.c for ugly details..
+ */
+struct ipc_kludge {
+ struct msgbuf __user *msgp;
+ long msgtyp;
+};
+
+#define SEMOP 1
+#define SEMGET 2
+#define SEMCTL 3
+#define SEMTIMEDOP 4
+#define MSGSND 11
+#define MSGRCV 12
+#define MSGGET 13
+#define MSGCTL 14
+#define SHMAT 21
+#define SHMDT 22
+#define SHMGET 23
+#define SHMCTL 24
+
+/* Used by the DIPC package, try and avoid reusing it */
+#define DIPC 25
+
+#define IPCCALL(version,op) ((version)<<16 | (op))
+
+#endif /* __M32R_IPC_H__ */
+
--- /dev/null
+#ifndef _ASM_M32R_IPCBUF_H
+#define _ASM_M32R_IPCBUF_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * The ipc64_perm structure for m32r architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+ __kernel_key_t key;
+ __kernel_uid32_t uid;
+ __kernel_gid32_t gid;
+ __kernel_uid32_t cuid;
+ __kernel_gid32_t cgid;
+ __kernel_mode_t mode;
+ unsigned short __pad1;
+ unsigned short seq;
+ unsigned short __pad2;
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+#endif /* _ASM_M32R_IPCBUF_H */
--- /dev/null
+#ifndef _ASM_M32R_IRQ_H
+#define _ASM_M32R_IRQ_H
+
+/* $Id$ */
+
+#include <linux/config.h>
+
+#if defined(CONFIG_PLAT_M32700UT_Alpha) || defined(CONFIG_PLAT_USRV)
+/*
+ * IRQ definitions for M32700UT
+ * M32700 Chip: 64 interrupts
+ * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
+ */
+#define M32700UT_NUM_CPU_IRQ (64)
+#define M32700UT_NUM_PLD_IRQ (32)
+#define M32700UT_IRQ_BASE 0
+#define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
+#define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
+
+#define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
+#elif defined(CONFIG_PLAT_M32700UT)
+/*
+ * IRQ definitions for M32700UT(Rev.C) + M32R-LAN
+ * M32700 Chip: 64 interrupts
+ * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
+ * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
+ * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
+ */
+#define M32700UT_NUM_CPU_IRQ (64)
+#define M32700UT_NUM_PLD_IRQ (32)
+#define M32700UT_NUM_LCD_PLD_IRQ (32)
+#define M32700UT_NUM_LAN_PLD_IRQ (32)
+#define M32700UT_IRQ_BASE 0
+#define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
+#define M32700UT_PLD_IRQ_BASE \
+ (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
+#define M32700UT_LCD_PLD_IRQ_BASE \
+ (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
+#define M32700UT_LAN_PLD_IRQ_BASE \
+ (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
+
+#define NR_IRQS \
+ (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
+ + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
+#elif defined(CONFIG_PLAT_OPSPUT)
+/*
+ * IRQ definitions for OPSPUT + M32R-LAN
+ * OPSP Chip: 64 interrupts
+ * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
+ * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
+ * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
+ */
+#define OPSPUT_NUM_CPU_IRQ (64)
+#define OPSPUT_NUM_PLD_IRQ (32)
+#define OPSPUT_NUM_LCD_PLD_IRQ (32)
+#define OPSPUT_NUM_LAN_PLD_IRQ (32)
+#define OPSPUT_IRQ_BASE 0
+#define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
+#define OPSPUT_PLD_IRQ_BASE \
+ (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
+#define OPSPUT_LCD_PLD_IRQ_BASE \
+ (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
+#define OPSPUT_LAN_PLD_IRQ_BASE \
+ (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
+
+#define NR_IRQS \
+ (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
+ + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
+#else
+#define NR_IRQS 64
+#endif
+
+#define irq_canonicalize(irq) (irq)
+
+#ifndef __ASSEMBLY__
+extern void disable_irq(unsigned int);
+extern void disable_irq_nosync(unsigned int);
+extern void enable_irq(unsigned int);
+
+struct irqaction;
+struct pt_regs;
+int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+#endif
+
+#endif /* _ASM_M32R_IRQ_H */
+
--- /dev/null
+#ifndef __M32R_KMAP_TYPES_H
+#define __M32R_KMAP_TYPES_H
+
+/* Dummy header just to define km_type. */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+# define D(n) __KM_FENCE_##n ,
+#else
+# define D(n)
+#endif
+
+enum km_type {
+D(0) KM_BOUNCE_READ,
+D(1) KM_SKB_SUNRPC_DATA,
+D(2) KM_SKB_DATA_SOFTIRQ,
+D(3) KM_USER0,
+D(4) KM_USER1,
+D(5) KM_BIO_SRC_IRQ,
+D(6) KM_BIO_DST_IRQ,
+D(7) KM_PTE0,
+D(8) KM_PTE1,
+D(9) KM_IRQ0,
+D(10) KM_IRQ1,
+D(11) KM_SOFTIRQ0,
+D(12) KM_SOFTIRQ1,
+D(13) KM_TYPE_NR
+};
+
+#undef D
+
+#endif /* __M32R_KMAP_TYPES_H */
+
--- /dev/null
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .balign 4
+#define __ALIGN_STR ".balign 4"
+
+#endif /* __ASM_LINKAGE_H */
--- /dev/null
+#ifndef __M32R_LOCAL_H
+#define __M32R_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* __M32R_LOCAL_H */
--- /dev/null
+#ifndef _M32102_H_
+#define _M32102_H_
+
+/*
+ * Renesas M32R 32102 group
+ *
+ * Copyright (c) 2001 Hitoshi Yamamoto
+ * Copyright (c) 2003, 2004 Renesas Technology Corp.
+ */
+
+/*======================================================================*
+ * Special Function Register
+ *======================================================================*/
+#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
+
+/*
+ * Clock and Power Management registers.
+ */
+#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
+
+#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
+#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
+#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
+
+/*
+ * Multi Function Timer registers.
+ */
+#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
+
+#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
+#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
+
+#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
+#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
+#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
+#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
+#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
+#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
+
+#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
+#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
+#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
+#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
+#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
+#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
+
+#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
+#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
+#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
+#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
+#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
+#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
+
+#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
+#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
+#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
+#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
+#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
+#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
+
+#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
+#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
+#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
+#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
+#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
+#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
+
+#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
+#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
+#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
+#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
+#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
+#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
+
+#ifdef CONFIG_CHIP_M32700
+#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
+#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
+#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
+#define M32R_MFTCR_MFT3MSK (1UL<<28) /* b3 */
+#define M32R_MFTCR_MFT4MSK (1UL<<27) /* b4 */
+#define M32R_MFTCR_MFT5MSK (1UL<<26) /* b5 */
+#define M32R_MFTCR_MFT0EN (1UL<<23) /* b8 */
+#define M32R_MFTCR_MFT1EN (1UL<<22) /* b9 */
+#define M32R_MFTCR_MFT2EN (1UL<<21) /* b10 */
+#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
+#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
+#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
+#else /* not CONFIG_CHIP_M32700 */
+#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
+#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
+#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
+#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
+#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
+#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
+#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
+#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
+#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
+#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
+#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
+#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
+#endif /* not CONFIG_CHIP_M32700 */
+
+#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
+#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
+#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
+#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
+#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
+#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
+#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
+#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
+#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
+#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
+#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
+#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
+#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
+#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
+#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
+
+/*
+ * Serial I/O registers.
+ */
+#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
+
+#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
+#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
+#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
+#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
+#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
+#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
+#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
+#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
+#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
+
+/*
+ * Interrupt Control Unit registers.
+ */
+#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
+#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
+#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
+#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
+#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
+#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
+#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
+#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
+#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
+#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
+#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
+#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
+#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
+#define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
+#define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
+#define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
+#define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
+#define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
+#define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
+#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
+#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
+#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
+#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
+#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
+#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
+#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
+#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
+#define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
+#define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
+#define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
+#define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
+
+#ifdef CONFIG_SMP
+#define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
+#define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
+#define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
+#define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
+#define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
+#define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
+#define M32R_ICU_IPICR6_PORTL (0x2f4+M32R_ICU_OFFSET) /* IPI6 */
+#define M32R_ICU_IPICR7_PORTL (0x2f8+M32R_ICU_OFFSET) /* IPI7 */
+#endif /* CONFIG_SMP */
+
+#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
+#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
+#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
+#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
+#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
+#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
+#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
+#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
+
+#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
+#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
+#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
+#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
+#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
+#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
+#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
+#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
+#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
+#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
+#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
+#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
+#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
+#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
+
+#define M32R_IRQ_INT0 (1) /* INT0 */
+#define M32R_IRQ_INT1 (2) /* INT1 */
+#define M32R_IRQ_INT2 (3) /* INT2 */
+#define M32R_IRQ_INT3 (4) /* INT3 */
+#define M32R_IRQ_INT4 (5) /* INT4 */
+#define M32R_IRQ_INT5 (6) /* INT5 */
+#define M32R_IRQ_INT6 (7) /* INT6 */
+#define M32R_IRQ_MFT0 (16) /* MFT0 */
+#define M32R_IRQ_MFT1 (17) /* MFT1 */
+#define M32R_IRQ_MFT2 (18) /* MFT2 */
+#define M32R_IRQ_MFT3 (19) /* MFT3 */
+#define M32R_IRQ_MFT4 (20) /* MFT4 */
+#define M32R_IRQ_MFT5 (21) /* MFT5 */
+#define M32R_IRQ_DMA0 (32) /* DMA0 */
+#define M32R_IRQ_DMA1 (33) /* DMA1 */
+#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
+#define M32R_IRQ_SIO0_S (49) /* SIO0 receive */
+#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
+#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
+#define M32R_IRQ_SIO2_R (52) /* SIO2 send */
+#define M32R_IRQ_SIO2_S (53) /* SIO2 receive */
+#define M32R_IRQ_SIO3_R (54) /* SIO3 send */
+#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
+#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
+#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
+
+#ifdef CONFIG_SMP
+#define M32R_IRQ_IPI0 (56)
+#define M32R_IRQ_IPI1 (57)
+#define M32R_IRQ_IPI2 (58)
+#define M32R_IRQ_IPI3 (59)
+#define M32R_IRQ_IPI4 (60)
+#define M32R_IRQ_IPI5 (61)
+#define M32R_IRQ_IPI6 (62)
+#define M32R_IRQ_IPI7 (63)
+#define M32R_CPUID_PORTL (0xffffffe0)
+
+#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
+
+#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME3_PORTL (0x1c+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID3_PORTL (0x2c+M32R_FPGA_TOP)
+#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
+#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
+
+#ifndef __ASSEMBLY__
+/* For NETDEV WATCHDOG */
+typedef struct {
+ unsigned long icucr; /* ICU Control Register */
+} icu_data_t;
+
+extern icu_data_t icu_data[];
+#endif
+
+#endif /* CONFIG_SMP */
+
+#endif /* _M32102_H_ */
--- /dev/null
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000,2001 by Hiroyuki Kondo
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef void V;
+typedef char B;
+typedef short S;
+typedef int W;
+typedef long L;
+typedef float F;
+typedef double D;
+typedef unsigned char UB;
+typedef unsigned short US;
+typedef unsigned int UW;
+typedef unsigned long UL;
+typedef const unsigned int CUW;
+
+/*********************************
+
+M32102 ICU
+
+*********************************/
+#define ICUISTS (UW *)0xa0EFF004
+#define ICUIREQ0 (UW *)0xa0EFF008
+#define ICUIREQ1 (UW *)0xa0EFF00C
+
+#define ICUSBICR (UW *)0xa0EFF018
+#define ICUIMASK (UW *)0xa0EFF01C
+
+#define ICUCR1 (UW *)0xa0EFF200 /* INT0 */
+#define ICUCR2 (UW *)0xa0EFF204 /* INT1 */
+#define ICUCR3 (UW *)0xa0EFF208 /* INT2 */
+#define ICUCR4 (UW *)0xa0EFF20C /* INT3 */
+#define ICUCR5 (UW *)0xa0EFF210 /* INT4 */
+#define ICUCR6 (UW *)0xa0EFF214 /* INT5 */
+#define ICUCR7 (UW *)0xa0EFF218 /* INT6 */
+
+#define ICUCR16 (UW *)0xa0EFF23C /* MFT0 */
+#define ICUCR17 (UW *)0xa0EFF240 /* MFT1 */
+#define ICUCR18 (UW *)0xa0EFF244 /* MFT2 */
+#define ICUCR19 (UW *)0xa0EFF248 /* MFT3 */
+#define ICUCR20 (UW *)0xa0EFF24C /* MFT4 */
+#define ICUCR21 (UW *)0xa0EFF250 /* MFT5 */
+
+#define ICUCR32 (UW *)0xa0EFF27C /* DMA0 */
+#define ICUCR33 (UW *)0xa0EFF280 /* DMA1 */
+
+#define ICUCR48 (UW *)0xa0EFF2BC /* SIO0R */
+#define ICUCR49 (UW *)0xa0EFF2C0 /* SIO0S */
+#define ICUCR50 (UW *)0xa0EFF2C4 /* SIO1R */
+#define ICUCR51 (UW *)0xa0EFF2C8 /* SIO1S */
+#define ICUCR52 (UW *)0xa0EFF2CC /* SIO2R */
+#define ICUCR53 (UW *)0xa0EFF2D0 /* SIO2S */
+#define ICUCR54 (UW *)0xa0EFF2D4 /* SIO3R */
+#define ICUCR55 (UW *)0xa0EFF2D8 /* SIO3S */
+#define ICUCR56 (UW *)0xa0EFF2DC /* SIO4R */
+#define ICUCR57 (UW *)0xa0EFF2E0 /* SIO4S */
+
+/*********************************
+
+M32102 MFT
+
+*********************************/
+#define MFTCR (US *)0xa0EFC002
+#define MFTRPR (UB *)0xa0EFC006
+
+#define MFT0MOD (US *)0xa0EFC102
+#define MFT0BOS (US *)0xa0EFC106
+#define MFT0CUT (US *)0xa0EFC10A
+#define MFT0RLD (US *)0xa0EFC10E
+#define MFT0CRLD (US *)0xa0EFC112
+
+#define MFT1MOD (US *)0xa0EFC202
+#define MFT1BOS (US *)0xa0EFC206
+#define MFT1CUT (US *)0xa0EFC20A
+#define MFT1RLD (US *)0xa0EFC20E
+#define MFT1CRLD (US *)0xa0EFC212
+
+#define MFT2MOD (US *)0xa0EFC302
+#define MFT2BOS (US *)0xa0EFC306
+#define MFT2CUT (US *)0xa0EFC30A
+#define MFT2RLD (US *)0xa0EFC30E
+#define MFT2CRLD (US *)0xa0EFC312
+
+#define MFT3MOD (US *)0xa0EFC402
+#define MFT3CUT (US *)0xa0EFC40A
+#define MFT3RLD (US *)0xa0EFC40E
+#define MFT3CRLD (US *)0xa0EFC412
+
+#define MFT4MOD (US *)0xa0EFC502
+#define MFT4CUT (US *)0xa0EFC50A
+#define MFT4RLD (US *)0xa0EFC50E
+#define MFT4CRLD (US *)0xa0EFC512
+
+#define MFT5MOD (US *)0xa0EFC602
+#define MFT5CUT (US *)0xa0EFC60A
+#define MFT5RLD (US *)0xa0EFC60E
+#define MFT5CRLD (US *)0xa0EFC612
+
+/*********************************
+
+M32102 SIO
+
+*********************************/
+
+#define SIO0CR (volatile int *)0xa0efd000
+#define SIO0MOD0 (volatile int *)0xa0efd004
+#define SIO0MOD1 (volatile int *)0xa0efd008
+#define SIO0STS (volatile int *)0xa0efd00c
+#define SIO0IMASK (volatile int *)0xa0efd010
+#define SIO0BAUR (volatile int *)0xa0efd014
+#define SIO0RBAUR (volatile int *)0xa0efd018
+#define SIO0TXB (volatile int *)0xa0efd01c
+#define SIO0RXB (volatile int *)0xa0efd020
+
+#define SIO1CR (volatile int *)0xa0efd100
+#define SIO1MOD0 (volatile int *)0xa0efd104
+#define SIO1MOD1 (volatile int *)0xa0efd108
+#define SIO1STS (volatile int *)0xa0efd10c
+#define SIO1IMASK (volatile int *)0xa0efd110
+#define SIO1BAUR (volatile int *)0xa0efd114
+#define SIO1RBAUR (volatile int *)0xa0efd118
+#define SIO1TXB (volatile int *)0xa0efd11c
+#define SIO1RXB (volatile int *)0xa0efd120
+/*********************************
+
+M32102 PORT
+
+*********************************/
+#define PIEN (UB *)0xa0EF1003 /* input enable */
+
+#define P0DATA (UB *)0xa0EF1020 /* data */
+#define P1DATA (UB *)0xa0EF1021
+#define P2DATA (UB *)0xa0EF1022
+#define P3DATA (UB *)0xa0EF1023
+#define P4DATA (UB *)0xa0EF1024
+#define P5DATA (UB *)0xa0EF1025
+#define P6DATA (UB *)0xa0EF1026
+#define P7DATA (UB *)0xa0EF1027
+
+#define P0DIR (UB *)0xa0EF1040 /* direction */
+#define P1DIR (UB *)0xa0EF1041
+#define P2DIR (UB *)0xa0EF1042
+#define P3DIR (UB *)0xa0EF1043
+#define P4DIR (UB *)0xa0EF1044
+#define P5DIR (UB *)0xa0EF1045
+#define P6DIR (UB *)0xa0EF1046
+#define P7DIR (UB *)0xa0EF1047
+
+#define P0MOD (US *)0xa0EF1060 /* mode control */
+#define P1MOD (US *)0xa0EF1062
+#define P2MOD (US *)0xa0EF1064
+#define P3MOD (US *)0xa0EF1066
+#define P4MOD (US *)0xa0EF1068
+#define P5MOD (US *)0xa0EF106A
+#define P6MOD (US *)0xa0EF106C
+#define P7MOD (US *)0xa0EF106E
+
+#define P0ODCR (UB *)0xa0EF1080 /* open-drain control */
+#define P1ODCR (UB *)0xa0EF1081
+#define P2ODCR (UB *)0xa0EF1082
+#define P3ODCR (UB *)0xa0EF1083
+#define P4ODCR (UB *)0xa0EF1084
+#define P5ODCR (UB *)0xa0EF1085
+#define P6ODCR (UB *)0xa0EF1086
+#define P7ODCR (UB *)0xa0EF1087
+
+/*********************************
+
+M32102 Cache
+
+********************************/
+
+#define MCCR (US *)0xFFFFFFFE
+
+
+#else /* __ASSEMBLY__ */
+
+;;
+;; PIO 0x80ef1000
+;;
+
+#define PIEN 0xa0ef1000
+
+#define P0DATA 0xa0ef1020
+#define P1DATA 0xa0ef1021
+#define P2DATA 0xa0ef1022
+#define P3DATA 0xa0ef1023
+#define P4DATA 0xa0ef1024
+#define P5DATA 0xa0ef1025
+#define P6DATA 0xa0ef1026
+#define P7DATA 0xa0ef1027
+
+#define P0DIR 0xa0ef1040
+#define P1DIR 0xa0ef1041
+#define P2DIR 0xa0ef1042
+#define P3DIR 0xa0ef1043
+#define P4DIR 0xa0ef1044
+#define P5DIR 0xa0ef1045
+#define P6DIR 0xa0ef1046
+#define P7DIR 0xa0ef1047
+
+#define P0MOD 0xa0ef1060
+#define P1MOD 0xa0ef1062
+#define P2MOD 0xa0ef1064
+#define P3MOD 0xa0ef1066
+#define P4MOD 0xa0ef1068
+#define P5MOD 0xa0ef106a
+#define P6MOD 0xa0ef106c
+#define P7MOD 0xa0ef106e
+;
+#define P0ODCR 0xa0ef1080
+#define P1ODCR 0xa0ef1081
+#define P2ODCR 0xa0ef1082
+#define P3ODCR 0xa0ef1083
+#define P4ODCR 0xa0ef1084
+#define P5ODCR 0xa0ef1085
+#define P6ODCR 0xa0ef1086
+#define P7ODCR 0xa0ef1087
+
+;;
+;; WDT 0xa0ef2000
+;;
+
+#define WDTCR 0xa0ef2000
+
+
+;;
+;; CLK 0xa0ef4000
+;;
+
+#define CPUCLKCR 0xa0ef4000
+#define CLKMOD 0xa0ef4004
+#define PLLCR 0xa0ef4008
+
+
+;;
+;; BSEL 0xa0ef5000
+;;
+
+#define BSEL0CR 0xa0ef5000
+#define BSEL1CR 0xa0ef5004
+#define BSEL2CR 0xa0ef5008
+#define BSEL3CR 0xa0ef500c
+#define BSEL4CR 0xa0ef5010
+#define BSEL5CR 0xa0ef5014
+
+
+;;
+;; SDRAMC 0xa0ef6000
+;;
+
+#define SDRF0 0xa0ef6000
+#define SDRF1 0xa0ef6004
+#define SDIR0 0xa0ef6008
+#define SDIR1 0xa0ef600c
+#define SDBR 0xa0ef6010
+
+;; CH0
+#define SD0ADR 0xa0ef6020
+#define SD0SZ 0xa0ef6022
+#define SD0ER 0xa0ef6024
+#define SD0TR 0xa0ef6028
+#define SD0MOD 0xa0ef602c
+
+;; CH1
+#define SD1ADR 0xa0ef6040
+#define SD1SZ 0xa0ef6042
+#define SD1ER 0xa0ef6044
+#define SD1TR 0xa0ef6048
+#define SD1MOD 0xa0ef604c
+
+
+;;
+;; DMAC 0xa0ef8000
+;;
+
+#define DMAEN 0xa0ef8000
+#define DMAISTS 0xa0ef8004
+#define DMAEDET 0xa0ef8008
+#define DMAASTS 0xa0ef800c
+
+;; CH0
+#define DMA0CR0 0xa0ef8100
+#define DMA0CR1 0xa0ef8104
+#define DMA0CSA 0xa0ef8108
+#define DMA0RSA 0xa0ef810c
+#define DMA0CDA 0xa0ef8110
+#define DMA0RDA 0xa0ef8114
+#define DMA0CBCUT 0xa0ef8118
+#define DMA0RBCUT 0xa0ef811c
+
+;; CH1
+#define DMA1CR0 0xa0ef8200
+#define DMA1CR1 0xa0ef8204
+#define DMA1CSA 0xa0ef8208
+#define DMA1RSA 0xa0ef820c
+#define DMA1CDA 0xa0ef8210
+#define DMA1RDA 0xa0ef8214
+#define DMA1CBCUT 0xa0ef8218
+#define DMA1RBCUT 0xa0ef821c
+
+
+;;
+;; MFT 0xa0efc000
+;;
+
+#define MFTCR 0xa0efc000
+#define MFTRPR 0xa0efc004
+
+;; CH0
+#define MFT0MOD 0xa0efc100
+#define MFT0BOS 0xa0efc104
+#define MFT0CUT 0xa0efc108
+#define MFT0RLD 0xa0efc10c
+#define MFT0CMPRLD 0xa0efc110
+
+;; CH1
+#define MFT1MOD 0xa0efc200
+#define MFT1BOS 0xa0efc204
+#define MFT1CUT 0xa0efc208
+#define MFT1RLD 0xa0efc20c
+#define MFT1CMPRLD 0xa0efc210
+
+;; CH2
+#define MFT2MOD 0xa0efc300
+#define MFT2BOS 0xa0efc304
+#define MFT2CUT 0xa0efc308
+#define MFT2RLD 0xa0efc30c
+#define MFT2CMPRLD 0xa0efc310
+
+;; CH3
+#define MFT3MOD 0xa0efc400
+#define MFT3BOS 0xa0efc404
+#define MFT3CUT 0xa0efc408
+#define MFT3RLD 0xa0efc40c
+#define MFT3CMPRLD 0xa0efc410
+
+;; CH4
+#define MFT4MOD 0xa0efc500
+#define MFT4BOS 0xa0efc504
+#define MFT4CUT 0xa0efc508
+#define MFT4RLD 0xa0efc50c
+#define MFT4CMPRLD 0xa0efc510
+
+;; CH5
+#define MFT5MOD 0xa0efc600
+#define MFT5BOS 0xa0efc604
+#define MFT5CUT 0xa0efc608
+#define MFT5RLD 0xa0efc60c
+#define MFT5CMPRLD 0xa0efc610
+
+
+;;
+;; SIO 0xa0efd000
+;;
+
+;; CH0
+#define SIO0CR 0xa0efd000
+#define SIO0MOD0 0xa0efd004
+#define SIO0MOD1 0xa0efd008
+#define SIO0STS 0xa0efd00c
+#define SIO0IMASK 0xa0efd010
+#define SIO0BAUR 0xa0efd014
+#define SIO0RBAUR 0xa0efd018
+#define SIO0TXB 0xa0efd01c
+#define SIO0RXB 0xa0efd020
+
+;; CH1
+#define SIO1CR 0xa0efd100
+#define SIO1MOD0 0xa0efd104
+#define SIO1MOD1 0xa0efd108
+#define SIO1STS 0xa0efd10c
+#define SIO1IMASK 0xa0efd110
+#define SIO1BAUR 0xa0efd114
+#define SIO1RBAUR 0xa0efd118
+#define SIO1TXB 0xa0efd11c
+#define SIO1RXB 0xa0efd120
+
+;; CH2
+#define SIO2CR 0xa0efd200
+#define SIO2MOD0 0xa0efd204
+#define SIO2MOD1 0xa0efd208
+#define SIO2STS 0xa0efd20c
+#define SIO2IMASK 0xa0efd210
+#define SIO2BAUR 0xa0efd214
+#define SIO2RBAUR 0xa0efd218
+#define SIO2TXB 0xa0efd21c
+#define SIO2RXB 0xa0efd220
+
+;; CH3
+#define SIO3CR 0xa0efd300
+#define SIO3MOD0 0xa0efd304
+#define SIO3MOD1 0xa0efd308
+#define SIO3STS 0xa0efd30c
+#define SIO3IMASK 0xa0efd310
+#define SIO3BAUR 0xa0efd314
+#define SIO3RBAUR 0xa0efd318
+#define SIO3TXB 0xa0efd31c
+#define SIO3RXB 0xa0efd320
+
+;; CH4
+#define SIO4CR 0xa0efd400
+#define SIO4MOD0 0xa0efd404
+#define SIO4MOD1 0xa0efd408
+#define SIO4STS 0xa0efd40c
+#define SIO4IMASK 0xa0efd410
+#define SIO4BAUR 0xa0efd414
+#define SIO4RBAUR 0xa0efd418
+#define SIO4TXB 0xa0efd41c
+#define SIO4RXB 0xa0efd420
+
+
+;;
+;; ICU 0xa0eff000
+;;
+
+#define ICUISTS 0xa0eff004
+#define ICUIREQ0 0xa0eff008
+#define ICUIREQ1 0xa0eff00c
+
+#define ICUSBICR 0xa0eff018
+#define ICUIMASK 0xa0eff01c
+
+#define ICUCR1 0xa0eff200
+#define ICUCR2 0xa0eff204
+#define ICUCR3 0xa0eff208
+#define ICUCR4 0xa0eff20c
+#define ICUCR5 0xa0eff210
+#define ICUCR6 0xa0eff214
+#define ICUCR7 0xa0eff218
+
+#define ICUCR16 0xa0eff23c
+#define ICUCR17 0xa0eff240
+#define ICUCR18 0xa0eff244
+#define ICUCR19 0xa0eff248
+#define ICUCR20 0xa0eff24c
+#define ICUCR21 0xa0eff250
+
+#define ICUCR32 0xa0eff27c
+#define ICUCR33 0xa0eff280
+
+#define ICUCR48 0xa0eff2bc
+#define ICUCR49 0xa0eff2c0
+#define ICUCR50 0xa0eff2c4
+#define ICUCR51 0xa0eff2c8
+#define ICUCR52 0xa0eff2cc
+#define ICUCR53 0xa0eff2d0
+#define ICUCR54 0xa0eff2d4
+#define ICUCR55 0xa0eff2d8
+#define ICUCR56 0xa0eff2dc
+#define ICUCR57 0xa0eff2e0
+
+;;
+;; CACHE
+;;
+
+#define MCCR 0xfffffffc
+
+
+#endif /* __ASSEMBLY__ */
--- /dev/null
+/*
+ * include/asm/m32700ut_lan.h
+ *
+ * M32700UT-LAN board
+ *
+ * Copyright (c) 2002 Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * $Id$
+ */
+
+#ifndef _M32700UT_M32700UT_LAN_H
+#define _M32700UT_M32700UT_LAN_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * C functions use non-cache address.
+ */
+#define M32700UT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
+#else
+#define M32700UT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
+#endif /* __ASSEMBLY__ */
+
+/* ICU
+ * ICUISTS: status register
+ * ICUIREQ0: request register
+ * ICUIREQ1: request register
+ * ICUCR3: control register for CFIREQ# interrupt
+ * ICUCR4: control register for CFC Card insert interrupt
+ * ICUCR5: control register for CFC Card eject interrupt
+ * ICUCR6: control register for external interrupt
+ * ICUCR11: control register for MMC Card insert/eject interrupt
+ * ICUCR13: control register for SC error interrupt
+ * ICUCR14: control register for SC receive interrupt
+ * ICUCR15: control register for SC send interrupt
+ * ICUCR16: control register for SIO0 receive interrupt
+ * ICUCR17: control register for SIO0 send interrupt
+ */
+#define M32700UT_LAN_IRQ_LAN (M32700UT_LAN_PLD_IRQ_BASE + 1) /* LAN */
+#define M32700UT_LAN_IRQ_I2C (M32700UT_LAN_PLD_IRQ_BASE + 3) /* I2C */
+
+#define M32700UT_LAN_ICUISTS __reg16(M32700UT_LAN_BASE + 0xc0002)
+#define M32700UT_LAN_ICUISTS_VECB_MASK (0xf000)
+#define M32700UT_LAN_VECB(x) ((x) & M32700UT_LAN_ICUISTS_VECB_MASK)
+#define M32700UT_LAN_ICUISTS_ISN_MASK (0x07c0)
+#define M32700UT_LAN_ICUISTS_ISN(x) ((x) & M32700UT_LAN_ICUISTS_ISN_MASK)
+#define M32700UT_LAN_ICUIREQ0 __reg16(M32700UT_LAN_BASE + 0xc0004)
+#define M32700UT_LAN_ICUCR1 __reg16(M32700UT_LAN_BASE + 0xc0010)
+#define M32700UT_LAN_ICUCR3 __reg16(M32700UT_LAN_BASE + 0xc0014)
+
+/*
+ * AR register on PLD
+ */
+#define ARVCR0 __reg32(M32700UT_LAN_BASE + 0x40000)
+#define ARVCR0_VDS 0x00080000
+#define ARVCR0_RST 0x00010000
+#define ARVCR1 __reg32(M32700UT_LAN_BASE + 0x40004)
+#define ARVCR1_QVGA 0x02000000
+#define ARVCR1_NORMAL 0x01000000
+#define ARVCR1_HIEN 0x00010000
+#define ARVHCOUNT __reg32(M32700UT_LAN_BASE + 0x40008)
+#define ARDATA __reg32(M32700UT_LAN_BASE + 0x40010)
+#define ARINTSEL __reg32(M32700UT_LAN_BASE + 0x40014)
+#define ARINTSEL_INT3 0x10000000 /* CPU INT3 */
+#define ARDATA32 __reg32(M32700UT_LAN_BASE + 0x04040010) // Block 5
+/*
+#define ARINTSEL_SEL2 0x00002000
+#define ARINTSEL_SEL3 0x00001000
+#define ARINTSEL_SEL6 0x00000200
+#define ARINTSEL_SEL7 0x00000100
+#define ARINTSEL_SEL9 0x00000040
+#define ARINTSEL_SEL10 0x00000020
+#define ARINTSEL_SEL11 0x00000010
+#define ARINTSEL_SEL12 0x00000008
+*/
+
+/*
+ * I2C register on PLD
+ */
+#define PLDI2CCR __reg32(M32700UT_LAN_BASE + 0x40040)
+#define PLDI2CCR_ES0 0x00000001 /* enable I2C interface */
+#define PLDI2CMOD __reg32(M32700UT_LAN_BASE + 0x40044)
+#define PLDI2CMOD_ACKCLK 0x00000200
+#define PLDI2CMOD_DTWD 0x00000100
+#define PLDI2CMOD_10BT 0x00000004
+#define PLDI2CMOD_ATM_NORMAL 0x00000000
+#define PLDI2CMOD_ATM_AUTO 0x00000003
+#define PLDI2CACK __reg32(M32700UT_LAN_BASE + 0x40048)
+#define PLDI2CACK_ACK 0x00000001
+#define PLDI2CFREQ __reg32(M32700UT_LAN_BASE + 0x4004c)
+#define PLDI2CCND __reg32(M32700UT_LAN_BASE + 0x40050)
+#define PLDI2CCND_START 0x00000001
+#define PLDI2CCND_STOP 0x00000002
+#define PLDI2CSTEN __reg32(M32700UT_LAN_BASE + 0x40054)
+#define PLDI2CSTEN_STEN 0x00000001
+#define PLDI2CDATA __reg32(M32700UT_LAN_BASE + 0x40060)
+#define PLDI2CSTS __reg32(M32700UT_LAN_BASE + 0x40064)
+#define PLDI2CSTS_TRX 0x00000020
+#define PLDI2CSTS_BB 0x00000010
+#define PLDI2CSTS_NOACK 0x00000001 /* 0:ack, 1:noack */
+
+#endif /* _M32700UT_M32700UT_LAN_H */
--- /dev/null
+/*
+ * include/asm/m32700ut_lcd.h
+ *
+ * M32700UT-LCD board
+ *
+ * Copyright (c) 2002 Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * $Id$
+ */
+
+#ifndef _M32700UT_M32700UT_LCD_H
+#define _M32700UT_M32700UT_LCD_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * C functions use non-cache address.
+ */
+#define M32700UT_LCD_BASE (0x10000000 /* + NONCACHE_OFFSET */)
+#else
+#define M32700UT_LCD_BASE (0x10000000 + NONCACHE_OFFSET)
+#endif /* __ASSEMBLY__ */
+
+/*
+ * ICU
+ */
+#define M32700UT_LCD_IRQ_BAT_INT (M32700UT_LCD_PLD_IRQ_BASE + 1)
+#define M32700UT_LCD_IRQ_USB_INT1 (M32700UT_LCD_PLD_IRQ_BASE + 2)
+#define M32700UT_LCD_IRQ_AUDT0 (M32700UT_LCD_PLD_IRQ_BASE + 3)
+#define M32700UT_LCD_IRQ_AUDT2 (M32700UT_LCD_PLD_IRQ_BASE + 4)
+#define M32700UT_LCD_IRQ_BATSIO_RCV (M32700UT_LCD_PLD_IRQ_BASE + 16)
+#define M32700UT_LCD_IRQ_BATSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 17)
+#define M32700UT_LCD_IRQ_ASNDSIO_RCV (M32700UT_LCD_PLD_IRQ_BASE + 18)
+#define M32700UT_LCD_IRQ_ASNDSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 19)
+#define M32700UT_LCD_IRQ_ACNLSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 21)
+
+#define M32700UT_LCD_ICUISTS __reg16(M32700UT_LCD_BASE + 0x300002)
+#define M32700UT_LCD_ICUISTS_VECB_MASK (0xf000)
+#define M32700UT_LCD_VECB(x) ((x) & M32700UT_LCD_ICUISTS_VECB_MASK)
+#define M32700UT_LCD_ICUISTS_ISN_MASK (0x07c0)
+#define M32700UT_LCD_ICUISTS_ISN(x) ((x) & M32700UT_LCD_ICUISTS_ISN_MASK)
+#define M32700UT_LCD_ICUIREQ0 __reg16(M32700UT_LCD_BASE + 0x300004)
+#define M32700UT_LCD_ICUIREQ1 __reg16(M32700UT_LCD_BASE + 0x300006)
+#define M32700UT_LCD_ICUCR1 __reg16(M32700UT_LCD_BASE + 0x300020)
+#define M32700UT_LCD_ICUCR2 __reg16(M32700UT_LCD_BASE + 0x300022)
+#define M32700UT_LCD_ICUCR3 __reg16(M32700UT_LCD_BASE + 0x300024)
+#define M32700UT_LCD_ICUCR4 __reg16(M32700UT_LCD_BASE + 0x300026)
+#define M32700UT_LCD_ICUCR16 __reg16(M32700UT_LCD_BASE + 0x300030)
+#define M32700UT_LCD_ICUCR17 __reg16(M32700UT_LCD_BASE + 0x300032)
+#define M32700UT_LCD_ICUCR18 __reg16(M32700UT_LCD_BASE + 0x300034)
+#define M32700UT_LCD_ICUCR19 __reg16(M32700UT_LCD_BASE + 0x300036)
+#define M32700UT_LCD_ICUCR21 __reg16(M32700UT_LCD_BASE + 0x30003a)
+
+#endif /* _M32700UT_M32700UT_LCD_H */
--- /dev/null
+/*
+ * include/asm/m32700ut/m32700ut_pld.h
+ *
+ * Definitions for Programable Logic Device(PLD) on M32700UT board.
+ *
+ * Copyright (c) 2002 Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * $Id$
+ */
+
+#ifndef _M32700UT_M32700UT_PLD_H
+#define _M32700UT_M32700UT_PLD_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_PLAT_M32700UT_Alpha)
+#define PLD_PLAT_BASE 0x08c00000
+#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV)
+#define PLD_PLAT_BASE 0x04c00000
+#else
+#error "no platform configuration"
+#endif
+
+#ifndef __ASSEMBLY__
+/*
+ * C functions use non-cache address.
+ */
+#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
+#define __reg8 (volatile unsigned char *)
+#define __reg16 (volatile unsigned short *)
+#define __reg32 (volatile unsigned int *)
+#else
+#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
+#define __reg8
+#define __reg16
+#define __reg32
+#endif /* __ASSEMBLY__ */
+
+/* CFC */
+#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
+#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
+#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
+#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
+#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
+#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
+#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
+#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
+
+/* MMC */
+#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
+#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
+#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
+#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
+#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
+#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
+#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
+#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
+#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
+#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
+#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
+#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
+
+/* ICU
+ * ICUISTS: status register
+ * ICUIREQ0: request register
+ * ICUIREQ1: request register
+ * ICUCR3: control register for CFIREQ# interrupt
+ * ICUCR4: control register for CFC Card insert interrupt
+ * ICUCR5: control register for CFC Card eject interrupt
+ * ICUCR6: control register for external interrupt
+ * ICUCR11: control register for MMC Card insert/eject interrupt
+ * ICUCR13: control register for SC error interrupt
+ * ICUCR14: control register for SC receive interrupt
+ * ICUCR15: control register for SC send interrupt
+ * ICUCR16: control register for SIO0 receive interrupt
+ * ICUCR17: control register for SIO0 send interrupt
+ */
+#if !defined(CONFIG_PLAT_USRV)
+#define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
+#define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
+#define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
+#define PLD_IRQ_CFIREQ (M32700UT_PLD_IRQ_BASE + 3) /* CF IREQ */
+#define PLD_IRQ_CFC_INSERT (M32700UT_PLD_IRQ_BASE + 4) /* CF Insert */
+#define PLD_IRQ_CFC_EJECT (M32700UT_PLD_IRQ_BASE + 5) /* CF Eject */
+#define PLD_IRQ_EXINT (M32700UT_PLD_IRQ_BASE + 6) /* EXINT */
+#define PLD_IRQ_INT7 (M32700UT_PLD_IRQ_BASE + 7) /* reserved */
+#define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
+#define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
+#define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
+#define PLD_IRQ_MMCCARD (M32700UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
+#define PLD_IRQ_INT12 (M32700UT_PLD_IRQ_BASE + 12) /* reserved */
+#define PLD_IRQ_SC_ERROR (M32700UT_PLD_IRQ_BASE + 13) /* SC error */
+#define PLD_IRQ_SC_RCV (M32700UT_PLD_IRQ_BASE + 14) /* SC receive */
+#define PLD_IRQ_SC_SND (M32700UT_PLD_IRQ_BASE + 15) /* SC send */
+#define PLD_IRQ_SIO0_RCV (M32700UT_PLD_IRQ_BASE + 16) /* SIO receive */
+#define PLD_IRQ_SIO0_SND (M32700UT_PLD_IRQ_BASE + 17) /* SIO send */
+#define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
+#define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
+#define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
+#define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
+#define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
+#define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
+#define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
+#define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
+#define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
+#define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
+#define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
+#define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
+#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
+#define PLD_IRQ_INT31 (M32700UT_PLD_IRQ_BASE + 31) /* reserved */
+
+#else /* CONFIG_PLAT_USRV */
+
+#define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
+#define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
+#define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
+#define PLD_IRQ_CF0 (M32700UT_PLD_IRQ_BASE + 3) /* CF0# */
+#define PLD_IRQ_CF1 (M32700UT_PLD_IRQ_BASE + 4) /* CF1# */
+#define PLD_IRQ_CF2 (M32700UT_PLD_IRQ_BASE + 5) /* CF2# */
+#define PLD_IRQ_CF3 (M32700UT_PLD_IRQ_BASE + 6) /* CF3# */
+#define PLD_IRQ_CF4 (M32700UT_PLD_IRQ_BASE + 7) /* CF4# */
+#define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
+#define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
+#define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
+#define PLD_IRQ_INT11 (M32700UT_PLD_IRQ_BASE + 11) /* reserved */
+#define PLD_IRQ_UART0 (M32700UT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
+#define PLD_IRQ_UART1 (M32700UT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
+#define PLD_IRQ_INT14 (M32700UT_PLD_IRQ_BASE + 14) /* reserved */
+#define PLD_IRQ_INT15 (M32700UT_PLD_IRQ_BASE + 15) /* reserved */
+#define PLD_IRQ_SNDINT (M32700UT_PLD_IRQ_BASE + 16) /* SNDINT# */
+#define PLD_IRQ_INT17 (M32700UT_PLD_IRQ_BASE + 17) /* reserved */
+#define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
+#define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
+#define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
+#define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
+#define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
+#define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
+#define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
+#define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
+#define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
+#define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
+#define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
+#define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
+#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
+
+#endif /* CONFIG_PLAT_USRV */
+
+#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
+#define PLD_ICUISTS_VECB_MASK (0xf000)
+#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
+#define PLD_ICUISTS_ISN_MASK (0x07c0)
+#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
+#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
+#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
+#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
+#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
+#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
+#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
+#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
+#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
+#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
+#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
+#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
+#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
+#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
+#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
+#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
+#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
+#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
+#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
+#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
+#define PLD_ICUCR_IEN (0x1000)
+#define PLD_ICUCR_IREQ (0x0100)
+#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
+#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
+#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
+#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
+#define PLD_ICUCR_ILEVEL0 (0x0000)
+#define PLD_ICUCR_ILEVEL1 (0x0001)
+#define PLD_ICUCR_ILEVEL2 (0x0002)
+#define PLD_ICUCR_ILEVEL3 (0x0003)
+#define PLD_ICUCR_ILEVEL4 (0x0004)
+#define PLD_ICUCR_ILEVEL5 (0x0005)
+#define PLD_ICUCR_ILEVEL6 (0x0006)
+#define PLD_ICUCR_ILEVEL7 (0x0007)
+
+/* Power Control of MMC and CF */
+#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
+#define PLD_CPCR_CF 0x0001
+#define PLD_CPCR_MMC 0x0002
+
+/* LED Control
+ *
+ * 1: DIP swich side
+ * 2: Reset switch side
+ */
+#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
+#define PLD_IOLED_1_ON 0x001
+#define PLD_IOLED_1_OFF 0x000
+#define PLD_IOLED_2_ON 0x002
+#define PLD_IOLED_2_OFF 0x000
+
+/* DIP Switch
+ * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
+ * 1: -
+ * 2: -
+ * 3: -
+ */
+#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
+#define PLD_IOSWSTS_IOSW2 0x0200
+#define PLD_IOSWSTS_IOSW1 0x0100
+#define PLD_IOSWSTS_IOWP0 0x0001
+
+/* CRC */
+#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
+#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
+#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
+#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
+#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
+#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
+
+/* RTC */
+#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
+#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
+#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
+#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
+#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
+
+/* SIO0 */
+#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
+#define PLD_ESIO0CR_TXEN 0x0001
+#define PLD_ESIO0CR_RXEN 0x0002
+#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
+#define PLD_ESIO0MOD0_CTSS 0x0040
+#define PLD_ESIO0MOD0_RTSS 0x0080
+#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
+#define PLD_ESIO0MOD1_LMFS 0x0010
+#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
+#define PLD_ESIO0STS_TEMP 0x0001
+#define PLD_ESIO0STS_TXCP 0x0002
+#define PLD_ESIO0STS_RXCP 0x0004
+#define PLD_ESIO0STS_TXSC 0x0100
+#define PLD_ESIO0STS_RXSC 0x0200
+#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
+#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
+#define PLD_ESIO0INTCR_TXIEN 0x0002
+#define PLD_ESIO0INTCR_RXCEN 0x0004
+#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
+#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
+#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
+
+/* SIM Card */
+#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
+#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
+#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
+#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
+#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
+#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
+#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
+
+#endif /* _M32700UT_M32700UT_PLD.H */
--- /dev/null
+#ifndef _ASM_M32R_M32R_H_
+#define _ASM_M32R_M32R_H_
+
+/*
+ * Renesas M32R processor
+ *
+ * Copyright (C) 2003, 2004 Renesas Technology Corp.
+ */
+
+#include <linux/config.h>
+
+/* Chip type */
+#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
+#include <asm/m32r_mp_fpga.h>
+#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
+ || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
+ || defined(CONFIG_CHIP_OPSP)
+#include <asm/m32102.h>
+#include <asm/m32102peri.h>
+#endif
+
+/* Platform type */
+#if defined(CONFIG_PLAT_M32700UT)
+#include <asm/m32700ut/m32700ut_pld.h>
+#include <asm/m32700ut/m32700ut_lan.h>
+#include <asm/m32700ut/m32700ut_lcd.h>
+#endif /* CONFIG_PLAT_M32700UT */
+
+#if defined(CONFIG_PLAT_OPSPUT)
+#include <asm/opsput/opsput_pld.h>
+#include <asm/opsput/opsput_lan.h>
+#include <asm/opsput/opsput_lcd.h>
+#endif /* CONFIG_PLAT_OPSPUT */
+
+#if defined(CONFIG_PLAT_MAPPI2)
+#include <asm/mappi2/mappi2_pld.h>
+#endif /* CONFIG_PLAT_MAPPI2 */
+
+#if defined(CONFIG_PLAT_USRV)
+#include <asm/m32700ut/m32700ut_pld.h>
+#endif
+
+/*
+ * M32R Register
+ */
+
+/*
+ * MMU Register
+ */
+
+#define MMU_REG_BASE (0xffff0000)
+#define ITLB_BASE (0xfe000000)
+#define DTLB_BASE (0xfe000800)
+
+#define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
+
+#define MATM MMU_REG_BASE /* MMU Address Translation Mode
+ Register */
+#define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
+#define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
+#define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
+#define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
+ Address Register */
+#define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
+ Number Register */
+#define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
+#define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
+ Register */
+#define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
+#define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
+ Instruciton */
+#define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
+
+#define MATM_offset (MATM - MMU_REG_BASE)
+#define MPSZ_offset (MPSZ - MMU_REG_BASE)
+#define MASID_offset (MASID - MMU_REG_BASE)
+#define MESTS_offset (MESTS - MMU_REG_BASE)
+#define MDEVA_offset (MDEVA - MMU_REG_BASE)
+#define MDEVP_offset (MDEVP - MMU_REG_BASE)
+#define MPTB_offset (MPTB - MMU_REG_BASE)
+#define MSVA_offset (MSVA - MMU_REG_BASE)
+#define MTOP_offset (MTOP - MMU_REG_BASE)
+#define MIDXI_offset (MIDXI - MMU_REG_BASE)
+#define MIDXD_offset (MIDXD - MMU_REG_BASE)
+
+#define MESTS_IT (1 << 0) /* Instruction TLB miss */
+#define MESTS_IA (1 << 1) /* Instruction Access Exception */
+#define MESTS_DT (1 << 4) /* Operand TLB miss */
+#define MESTS_DA (1 << 5) /* Operand Access Exception */
+#define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
+
+/*
+ * PSW (Processor Status Word)
+ */
+
+/* PSW bit */
+#define M32R_PSW_BIT_SM (7) /* Stack Mode */
+#define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
+#define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
+#define M32R_PSW_BIT_C (0) /* Condition */
+#define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
+#define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
+#define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
+#define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
+
+/* PSW bit map */
+#define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
+#define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
+#define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
+#define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
+#define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
+#define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
+#define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
+#define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
+
+/*
+ * Direct address to SFR
+ */
+
+#include <asm/page.h>
+#ifdef CONFIG_MMU
+#define NONCACHE_OFFSET __PAGE_OFFSET+0x20000000
+#else
+#define NONCACHE_OFFSET __PAGE_OFFSET
+#endif /* CONFIG_MMU */
+
+#define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
+#define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
+#define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
+#define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
+#define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
+#define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
+
+#endif /* _ASM_M32R_M32R_H_ */
--- /dev/null
+#ifndef _ASM_M32R_M32R_MP_FPGA_
+#define _ASM_M32R_M32R_MP_FPGA_
+
+/*
+ * Renesas M32R-MP-FPGA
+ *
+ * Copyright (c) 2002 Hitoshi Yamamoto
+ * Copyright (c) 2003, 2004 Renesas Technology Corp.
+ */
+
+/*
+ * ========================================================
+ * M32R-MP-FPGA Memory Map
+ * ========================================================
+ * 0x00000000 : Block#0 : 64[MB]
+ * 0x03E00000 : SFR
+ * 0x03E00000 : reserved
+ * 0x03EF0000 : FPGA
+ * 0x03EF1000 : reserved
+ * 0x03EF4000 : CKM
+ * 0x03EF4000 : BSELC
+ * 0x03EF5000 : reserved
+ * 0x03EFC000 : MFT
+ * 0x03EFD000 : SIO
+ * 0x03EFE000 : reserved
+ * 0x03EFF000 : ICU
+ * 0x03F00000 : Internal SRAM 64[KB]
+ * 0x03F10000 : reserved
+ * --------------------------------------------------------
+ * 0x04000000 : Block#1 : 64[MB]
+ * 0x04000000 : Debug board SRAM 4[MB]
+ * 0x04400000 : reserved
+ * --------------------------------------------------------
+ * 0x08000000 : Block#2 : 64[MB]
+ * --------------------------------------------------------
+ * 0x0C000000 : Block#3 : 64[MB]
+ * --------------------------------------------------------
+ * 0x10000000 : Block#4 : 64[MB]
+ * --------------------------------------------------------
+ * 0x14000000 : Block#5 : 64[MB]
+ * --------------------------------------------------------
+ * 0x18000000 : Block#6 : 64[MB]
+ * --------------------------------------------------------
+ * 0x1C000000 : Block#7 : 64[MB]
+ * --------------------------------------------------------
+ * 0xFE000000 : TLB
+ * 0xFE000000 : ITLB
+ * 0xFE000080 : reserved
+ * 0xFE000800 : DTLB
+ * 0xFE000880 : reserved
+ * --------------------------------------------------------
+ * 0xFF000000 : System area
+ * 0xFFFF0000 : MMU
+ * 0xFFFF0030 : reserved
+ * 0xFFFF8000 : Debug function
+ * 0xFFFFA000 : reserved
+ * 0xFFFFC000 : CPU control
+ * 0xFFFFFFFF
+ * ========================================================
+ */
+
+/*======================================================================*
+ * Special Function Register
+ *======================================================================*/
+#define M32R_SFR_OFFSET (0x00E00000) /* 0x03E00000-0x03EFFFFF 1[MB] */
+
+/*
+ * FPGA registers.
+ */
+#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
+
+#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
+#define M32R_FPGA_CPU_NAME3_PORTL (0x1C+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
+#define M32R_FPGA_MODEL_ID3_PORTL (0x2C+M32R_FPGA_TOP)
+#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
+#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
+
+/*
+ * Clock and Power Manager registers.
+ */
+#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
+
+#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
+#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
+#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
+
+/*
+ * Block SELect Controller registers.
+ */
+#define M32R_BSELC_OFFSET (0x000F5000+M32R_SFR_OFFSET)
+
+#define M32R_BSEL0_CR0_PORTL (0x000+M32R_BSELC_OFFSET)
+#define M32R_BSEL0_CR1_PORTL (0x004+M32R_BSELC_OFFSET)
+#define M32R_BSEL1_CR0_PORTL (0x100+M32R_BSELC_OFFSET)
+#define M32R_BSEL1_CR1_PORTL (0x104+M32R_BSELC_OFFSET)
+#define M32R_BSEL2_CR0_PORTL (0x200+M32R_BSELC_OFFSET)
+#define M32R_BSEL2_CR1_PORTL (0x204+M32R_BSELC_OFFSET)
+#define M32R_BSEL3_CR0_PORTL (0x300+M32R_BSELC_OFFSET)
+#define M32R_BSEL3_CR1_PORTL (0x304+M32R_BSELC_OFFSET)
+#define M32R_BSEL4_CR0_PORTL (0x400+M32R_BSELC_OFFSET)
+#define M32R_BSEL4_CR1_PORTL (0x404+M32R_BSELC_OFFSET)
+#define M32R_BSEL5_CR0_PORTL (0x500+M32R_BSELC_OFFSET)
+#define M32R_BSEL5_CR1_PORTL (0x504+M32R_BSELC_OFFSET)
+#define M32R_BSEL6_CR0_PORTL (0x600+M32R_BSELC_OFFSET)
+#define M32R_BSEL6_CR1_PORTL (0x604+M32R_BSELC_OFFSET)
+#define M32R_BSEL7_CR0_PORTL (0x700+M32R_BSELC_OFFSET)
+#define M32R_BSEL7_CR1_PORTL (0x704+M32R_BSELC_OFFSET)
+
+/*
+ * Multi Function Timer registers.
+ */
+#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
+
+#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
+#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
+
+#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
+#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
+#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
+#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
+#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
+#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
+
+#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
+#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
+#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
+#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
+#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
+#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
+
+#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
+#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
+#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
+#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
+#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
+#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
+
+#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
+#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
+#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
+#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
+#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
+#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
+
+#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
+#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
+#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
+#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
+#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
+#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
+
+#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
+#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
+#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
+#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
+#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
+#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
+
+#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
+#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
+#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
+#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
+#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
+#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
+#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
+#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
+#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
+#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
+#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
+#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
+
+#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
+#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
+#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
+#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
+#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
+#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
+#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
+#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
+#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
+#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
+#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
+#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
+#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
+#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
+#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
+
+/*
+ * Serial I/O registers.
+ */
+#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
+
+#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
+#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
+#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
+#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
+#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
+#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
+#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
+#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
+#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
+
+/*
+ * Interrupt Control Unit registers.
+ */
+#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
+
+#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
+#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
+#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
+#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
+#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
+#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
+#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
+#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
+#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
+#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
+#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
+#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
+#define M32R_ICU_CR8_PORTL (0x218+M32R_ICU_OFFSET) /* INT7 */
+#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* SIO0 RX */
+#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* SIO0 TX */
+#define M32R_ICU_CR40_PORTL (0x29C+M32R_ICU_OFFSET) /* DMAC0 */
+#define M32R_ICU_CR41_PORTL (0x2A0+M32R_ICU_OFFSET) /* DMAC1 */
+#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* MFT0 */
+#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* MFT1 */
+#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* MFT2 */
+#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* MFT3 */
+#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* MFT4 */
+#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* MFT5 */
+#define M32R_ICU_IPICR0_PORTL (0x2DC+M32R_ICU_OFFSET) /* IPI0 */
+#define M32R_ICU_IPICR1_PORTL (0x2E0+M32R_ICU_OFFSET) /* IPI1 */
+#define M32R_ICU_IPICR2_PORTL (0x2E4+M32R_ICU_OFFSET) /* IPI2 */
+#define M32R_ICU_IPICR3_PORTL (0x2E8+M32R_ICU_OFFSET) /* IPI3 */
+#define M32R_ICU_IPICR4_PORTL (0x2EC+M32R_ICU_OFFSET) /* IPI4 */
+#define M32R_ICU_IPICR5_PORTL (0x2F0+M32R_ICU_OFFSET) /* IPI5 */
+#define M32R_ICU_IPICR6_PORTL (0x2F4+M32R_ICU_OFFSET) /* IPI6 */
+#define M32R_ICU_IPICR7_PORTL (0x2FC+M32R_ICU_OFFSET) /* IPI7 */
+
+#define M32R_ICUISTS_VECB(val) ((val>>28) & 0xF)
+#define M32R_ICUISTS_ISN(val) ((val>>22) & 0x3F)
+#define M32R_ICUISTS_PIML(val) ((val>>16) & 0x7)
+
+#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
+#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
+#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
+#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
+#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
+#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
+#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
+#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
+
+#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
+#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
+#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
+#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
+#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
+#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
+#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
+#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
+#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
+#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
+#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
+#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
+#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
+#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
+#define M32R_ICUCR_ILEVEL_MASK (7UL)
+
+#define M32R_IRQ_INT0 (1) /* INT0 */
+#define M32R_IRQ_INT1 (2) /* INT1 */
+#define M32R_IRQ_INT2 (3) /* INT2 */
+#define M32R_IRQ_INT3 (4) /* INT3 */
+#define M32R_IRQ_INT4 (5) /* INT4 */
+#define M32R_IRQ_INT5 (6) /* INT5 */
+#define M32R_IRQ_INT6 (7) /* INT6 */
+#define M32R_IRQ_INT7 (8) /* INT7 */
+#define M32R_IRQ_MFT0 (16) /* MFT0 */
+#define M32R_IRQ_MFT1 (17) /* MFT1 */
+#define M32R_IRQ_MFT2 (18) /* MFT2 */
+#define M32R_IRQ_MFT3 (19) /* MFT3 */
+#define M32R_IRQ_MFT4 (20) /* MFT4 */
+#define M32R_IRQ_MFT5 (21) /* MFT5 */
+#define M32R_IRQ_DMAC0 (32) /* DMAC0 */
+#define M32R_IRQ_DMAC1 (33) /* DMAC1 */
+#define M32R_IRQ_SIO0_R (48) /* SIO0 receive */
+#define M32R_IRQ_SIO0_S (49) /* SIO0 send */
+#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
+#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
+#define M32R_IRQ_IPI0 (56) /* IPI0 */
+#define M32R_IRQ_IPI1 (57) /* IPI1 */
+#define M32R_IRQ_IPI2 (58) /* IPI2 */
+#define M32R_IRQ_IPI3 (59) /* IPI3 */
+#define M32R_IRQ_IPI4 (60) /* IPI4 */
+#define M32R_IRQ_IPI5 (61) /* IPI5 */
+#define M32R_IRQ_IPI6 (62) /* IPI6 */
+#define M32R_IRQ_IPI7 (63) /* IPI7 */
+
+/*======================================================================*
+ * CPU
+ *======================================================================*/
+
+#define M32R_CPUID_PORTL (0xFFFFFFE0)
+#define M32R_MCICAR_PORTL (0xFFFFFFF0)
+#define M32R_MCDCAR_PORTL (0xFFFFFFF4)
+#define M32R_MCCR_PORTL (0xFFFFFFFC)
+
+#endif /* _ASM_M32R_M32R_MP_FPGA_ */
--- /dev/null
+/*
+ * include/asm/mappi2/mappi2_pld.h
+ *
+ * Definitions for Extended IO Logic on MAPPI2 board.
+ * based on m32700ut_pld.h by
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ */
+
+#ifndef _MAPPI2_PLD_H
+#define _MAPPI2_PLD_H
+
+#ifndef __ASSEMBLY__
+/* FIXME:
+ * Some C functions use non-cache address, so can't define non-cache address.
+ */
+#define PLD_BASE (0x10c00000 /* + NONCACHE_OFFSET */)
+#define __reg8 (volatile unsigned char *)
+#define __reg16 (volatile unsigned short *)
+#define __reg32 (volatile unsigned int *)
+#else
+#define PLD_BASE (0x10c00000 + NONCACHE_OFFSET)
+#define __reg8
+#define __reg16
+#define __reg32
+#endif /* __ASSEMBLY__ */
+
+/* CFC */
+#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
+#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
+#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
+#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
+#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
+#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
+
+/* MMC */
+#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
+#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
+#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
+#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
+#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
+#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
+#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
+#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
+#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
+#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
+#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
+#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
+
+/* Power Control of MMC and CF */
+#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
+
+
+/*==== ICU ====*/
+#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
+#define M32R_IRQ_I2C (28) /* I2C-BUS */
+#if 1
+#define PLD_IRQ_CFIREQ (40) /* CFC Card Interrupt */
+#define PLD_IRQ_CFC_INSERT (41) /* CFC Card Insert */
+#define PLD_IRQ_CFC_EJECT (42) /* CFC Card Eject */
+#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
+#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
+#else
+#define PLD_IRQ_CFIREQ (34) /* CFC Card Interrupt */
+#define PLD_IRQ_CFC_INSERT (35) /* CFC Card Insert */
+#define PLD_IRQ_CFC_EJECT (36) /* CFC Card Eject */
+#define PLD_IRQ_MMCCARD (37) /* MMC Card Insert */
+#define PLD_IRQ_MMCIRQ (38) /* MMC Transfer Done */
+#endif
+
+
+#if 0
+/* LED Control
+ *
+ * 1: DIP swich side
+ * 2: Reset switch side
+ */
+#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
+#define PLD_IOLED_1_ON 0x001
+#define PLD_IOLED_1_OFF 0x000
+#define PLD_IOLED_2_ON 0x002
+#define PLD_IOLED_2_OFF 0x000
+
+/* DIP Switch
+ * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
+ * 1: -
+ * 2: -
+ * 3: -
+ */
+#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
+#define PLD_IOSWSTS_IOSW2 0x0200
+#define PLD_IOSWSTS_IOSW1 0x0100
+#define PLD_IOSWSTS_IOWP0 0x0001
+
+#endif
+
+/* CRC */
+#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
+#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
+#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
+#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
+#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
+#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
+
+
+#if 0
+/* RTC */
+#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
+#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
+#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
+#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
+#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
+
+/* SIO0 */
+#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
+#define PLD_ESIO0CR_TXEN 0x0001
+#define PLD_ESIO0CR_RXEN 0x0002
+#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
+#define PLD_ESIO0MOD0_CTSS 0x0040
+#define PLD_ESIO0MOD0_RTSS 0x0080
+#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
+#define PLD_ESIO0MOD1_LMFS 0x0010
+#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
+#define PLD_ESIO0STS_TEMP 0x0001
+#define PLD_ESIO0STS_TXCP 0x0002
+#define PLD_ESIO0STS_RXCP 0x0004
+#define PLD_ESIO0STS_TXSC 0x0100
+#define PLD_ESIO0STS_RXSC 0x0200
+#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
+#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
+#define PLD_ESIO0INTCR_TXIEN 0x0002
+#define PLD_ESIO0INTCR_RXCEN 0x0004
+#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
+#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
+#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
+
+/* SIM Card */
+#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
+#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
+#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
+#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
+#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
+#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
+#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
+
+#endif
+
+#endif /* _MAPPI2_PLD.H */
--- /dev/null
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+// #define RTC_PORT(x) (0x70 + (x))
+#define RTC_PORT(x) ((x))
+#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#define RTC_IRQ 8
+#if 0
+#endif
+
+#endif /* _ASM_MC146818RTC_H */
--- /dev/null
+#ifndef __M32R_MMAN_H__
+#define __M32R_MMAN_H__
+
+/* orig : i386 2.6.0-test6 */
+
+#define PROT_READ 0x1 /* page can be read */
+#define PROT_WRITE 0x2 /* page can be written */
+#define PROT_EXEC 0x4 /* page can be executed */
+#define PROT_SEM 0x8 /* page may be used for atomic ops */
+#define PROT_NONE 0x0 /* page can not be accessed */
+#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
+
+#define MAP_SHARED 0x01 /* Share changes */
+#define MAP_PRIVATE 0x02 /* Changes are private */
+#define MAP_TYPE 0x0f /* Mask for type of mapping */
+#define MAP_FIXED 0x10 /* Interpret addr exactly */
+#define MAP_ANONYMOUS 0x20 /* don't use a file */
+
+#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
+#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
+#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
+#define MAP_LOCKED 0x2000 /* pages are locked */
+#define MAP_NORESERVE 0x4000 /* don't check for reservations */
+#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
+#define MAP_NONBLOCK 0x10000 /* do not block on IO */
+
+#define MS_ASYNC 1 /* sync memory asynchronously */
+#define MS_INVALIDATE 2 /* invalidate the caches */
+#define MS_SYNC 4 /* synchronous memory sync */
+
+#define MCL_CURRENT 1 /* lock all current mappings */
+#define MCL_FUTURE 2 /* lock all future mappings */
+
+#define MADV_NORMAL 0x0 /* default page-in behavior */
+#define MADV_RANDOM 0x1 /* page-in minimum required */
+#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
+#define MADV_WILLNEED 0x3 /* pre-fault pages */
+#define MADV_DONTNEED 0x4 /* discard these pages */
+
+/* compatibility flags */
+#define MAP_ANON MAP_ANONYMOUS
+#define MAP_FILE 0
+
+#endif /* __M32R_MMAN_H__ */
--- /dev/null
+#ifndef _ASM_M32R_MMU_H
+#define _ASM_M32R_MMU_H
+
+/* $Id$ */
+
+#include <linux/config.h>
+
+#if !defined(CONFIG_MMU)
+struct mm_rblock_struct {
+ int size;
+ int refcount;
+ void *kblock;
+};
+
+struct mm_tblock_struct {
+ struct mm_rblock_struct *rblock;
+ struct mm_tblock_struct *next;
+};
+
+typedef struct {
+ struct mm_tblock_struct tblock;
+ unsigned long end_brk;
+} mm_context_t;
+#else
+
+/* Default "unsigned long" context */
+#ifndef CONFIG_SMP
+typedef unsigned long mm_context_t;
+#else
+typedef unsigned long mm_context_t[NR_CPUS];
+#endif
+
+#endif /* CONFIG_MMU */
+#endif /* _ASM_M32R_MMU_H */
+
--- /dev/null
+#ifndef _ASM_M32R_MMU_CONTEXT_H
+#define _ASM_M32R_MMU_CONTEXT_H
+
+/* $Id */
+
+#include <linux/config.h>
+
+#include <asm/m32r.h>
+
+#define MMU_CONTEXT_ASID_MASK (0x000000FF)
+#define MMU_CONTEXT_VERSION_MASK (0xFFFFFF00)
+#define MMU_CONTEXT_FIRST_VERSION (0x00000100)
+#define NO_CONTEXT (0x00000000)
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+#include <asm/atomic.h>
+#include <asm/pgalloc.h>
+#include <asm/mmu.h>
+#include <asm/tlbflush.h>
+
+/*
+ * Cache of MMU context last used.
+ */
+#ifndef CONFIG_SMP
+extern unsigned long mmu_context_cache_dat;
+#define mmu_context_cache mmu_context_cache_dat
+#define mm_context(mm) mm->context
+#else /* not CONFIG_SMP */
+extern unsigned long mmu_context_cache_dat[];
+#define mmu_context_cache mmu_context_cache_dat[smp_processor_id()]
+#define mm_context(mm) mm->context[smp_processor_id()]
+#endif /* not CONFIG_SMP */
+
+#define set_tlb_tag(entry, tag) (*entry = (tag & PAGE_MASK)|get_asid())
+#define set_tlb_data(entry, data) (*entry = (data | _PAGE_PRESENT))
+
+#ifdef CONFIG_MMU
+#define enter_lazy_tlb(mm, tsk) do { } while (0)
+
+static __inline__ void get_new_mmu_context(struct mm_struct *mm)
+{
+ unsigned long mc = ++mmu_context_cache;
+
+ if (!(mc & MMU_CONTEXT_ASID_MASK)) {
+ /* We exhaust ASID of this version.
+ Flush all TLB and start new cycle. */
+ local_flush_tlb_all();
+ /* Fix version if needed.
+ Note that we avoid version #0 to distingush NO_CONTEXT. */
+ if (!mc)
+ mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
+ }
+ mm_context(mm) = mc;
+}
+
+/*
+ * Get MMU context if needed.
+ */
+static __inline__ void get_mmu_context(struct mm_struct *mm)
+{
+ if (mm) {
+ unsigned long mc = mmu_context_cache;
+
+ /* Check if we have old version of context.
+ If it's old, we need to get new context with new version. */
+ if ((mm_context(mm) ^ mc) & MMU_CONTEXT_VERSION_MASK)
+ get_new_mmu_context(mm);
+ }
+}
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+static __inline__ int init_new_context(struct task_struct *tsk,
+ struct mm_struct *mm)
+{
+#ifndef CONFIG_SMP
+ mm->context = NO_CONTEXT;
+#else /* CONFIG_SMP */
+ int num_cpus = num_online_cpus();
+ int i;
+
+ for (i = 0 ; i < num_cpus ; i++)
+ mm->context[i] = NO_CONTEXT;
+#endif /* CONFIG_SMP */
+
+ return 0;
+}
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+#define destroy_context(mm) do { } while (0)
+
+static __inline__ void set_asid(unsigned long asid)
+{
+ *(volatile unsigned long *)MASID = (asid & MMU_CONTEXT_ASID_MASK);
+}
+
+static __inline__ unsigned long get_asid(void)
+{
+ unsigned long asid;
+
+ asid = *(volatile long *)MASID;
+ asid &= MMU_CONTEXT_ASID_MASK;
+
+ return asid;
+}
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static __inline__ void activate_context(struct mm_struct *mm)
+{
+ get_mmu_context(mm);
+ set_asid(mm_context(mm) & MMU_CONTEXT_ASID_MASK);
+}
+
+static __inline__ void switch_mm(struct mm_struct *prev,
+ struct mm_struct *next, struct task_struct *tsk)
+{
+#ifdef CONFIG_SMP
+ int cpu = smp_processor_id();
+#endif /* CONFIG_SMP */
+
+ if (prev != next) {
+#ifdef CONFIG_SMP
+ cpu_set(cpu, next->cpu_vm_mask);
+#endif /* CONFIG_SMP */
+ /* Set MPTB = next->pgd */
+ *(volatile unsigned long *)MPTB = (unsigned long)next->pgd;
+ activate_context(next);
+ }
+#ifdef CONFIG_SMP
+ else
+ if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
+ activate_context(next);
+#endif /* CONFIG_SMP */
+}
+
+#define deactivate_mm(tsk, mm) do { } while (0)
+
+#define activate_mm(prev, next) \
+ switch_mm((prev), (next), NULL)
+
+#else
+#define get_mmu_context(mm) do { } while (0)
+#define init_new_context(tsk,mm) (0)
+#define destroy_context(mm) do { } while (0)
+#define set_asid(asid) do { } while (0)
+#define get_asid() (0)
+#define activate_context(mm) do { } while (0)
+#define switch_mm(prev,next,tsk) do { } while (0)
+#define deactivate_mm(mm,tsk) do { } while (0)
+#define activate_mm(prev,next) do { } while (0)
+#define enter_lazy_tlb(mm,tsk) do { } while (0)
+#endif /* CONFIG_MMU */
+
+
+#endif /* not __ASSEMBLY__ */
+
+#endif /* _ASM_M32R_MMU_CONTEXT_H */
+
--- /dev/null
+/*
+ * Written by Pat Gaughen (gone@us.ibm.com) Mar 2002
+ *
+ */
+
+#ifndef _ASM_MMZONE_H_
+#define _ASM_MMZONE_H_
+
+#include <asm/smp.h>
+
+#ifdef CONFIG_DISCONTIGMEM
+
+extern struct pglist_data *node_data[];
+#define NODE_DATA(nid) (node_data[nid])
+
+#define node_localnr(pfn, nid) ((pfn) - NODE_DATA(nid)->node_start_pfn)
+#define node_mem_map(nid) (NODE_DATA(nid)->node_mem_map)
+#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid) \
+({ \
+ pg_data_t *__pgdat = NODE_DATA(nid); \
+ __pgdat->node_start_pfn + __pgdat->node_spanned_pages - 1; \
+})
+
+#define local_mapnr(kvaddr) \
+({ \
+ unsigned long __pfn = __pa(kvaddr) >> PAGE_SHIFT; \
+ (__pfn - node_start_pfn(pfn_to_nid(__pfn))); \
+})
+
+#define pfn_to_page(pfn) \
+({ \
+ unsigned long __pfn = pfn; \
+ int __node = pfn_to_nid(__pfn); \
+ &node_mem_map(__node)[node_localnr(__pfn,__node)]; \
+})
+
+#define page_to_pfn(pg) \
+({ \
+ struct page *__page = pg; \
+ struct zone *__zone = page_zone(__page); \
+ (unsigned long)(__page - __zone->zone_mem_map) \
+ + __zone->zone_start_pfn; \
+})
+#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
+/*
+ * pfn_valid should be made as fast as possible, and the current definition
+ * is valid for machines that are NUMA, but still contiguous, which is what
+ * is currently supported. A more generalised, but slower definition would
+ * be something like this - mbligh:
+ * ( pfn_to_pgdat(pfn) && ((pfn) < node_end_pfn(pfn_to_nid(pfn))) )
+ */
+#if 1 /* M32R_FIXME */
+#define pfn_valid(pfn) (1)
+#else
+#define pfn_valid(pfn) ((pfn) < num_physpages)
+#endif
+
+/*
+ * generic node memory support, the following assumptions apply:
+ */
+
+static __inline__ int pfn_to_nid(unsigned long pfn)
+{
+ int node;
+
+ for (node = 0 ; node < MAX_NUMNODES ; node++)
+ if (pfn >= node_start_pfn(node) && pfn <= node_end_pfn(node))
+ break;
+
+ return node;
+}
+
+static __inline__ struct pglist_data *pfn_to_pgdat(unsigned long pfn)
+{
+ return(NODE_DATA(pfn_to_nid(pfn)));
+}
+
+#endif /* CONFIG_DISCONTIGMEM */
+#endif /* _ASM_MMZONE_H_ */
--- /dev/null
+#ifndef _ASM_M32R_MODULE_H
+#define _ASM_M32R_MODULE_H
+
+/* $Id$ */
+
+struct mod_arch_specific { };
+
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+
+#endif /* _ASM_M32R_MODULE_H */
+
--- /dev/null
+#ifndef _ASM_M32R_MSGBUF_H
+#define _ASM_M32R_MSGBUF_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * The msqid64_ds structure for m32r architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+ struct ipc64_perm msg_perm;
+ __kernel_time_t msg_stime; /* last msgsnd time */
+ unsigned long __unused1;
+ __kernel_time_t msg_rtime; /* last msgrcv time */
+ unsigned long __unused2;
+ __kernel_time_t msg_ctime; /* last change time */
+ unsigned long __unused3;
+ unsigned long msg_cbytes; /* current number of bytes on queue */
+ unsigned long msg_qnum; /* number of messages in queue */
+ unsigned long msg_qbytes; /* max number of bytes on queue */
+ __kernel_pid_t msg_lspid; /* pid of last msgsnd */
+ __kernel_pid_t msg_lrpid; /* last receive pid */
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+#endif /* _ASM_M32R_MSGBUF_H */
--- /dev/null
+#ifndef _ASM_M32R_NAMEI_H
+#define _ASM_M32R_NAMEI_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * linux/include/asm-m32r/namei.h
+ *
+ * Included from linux/fs/namei.c
+ */
+
+/* This dummy routine maybe changed to something useful
+ * for /usr/gnemul/ emulation stuff.
+ * Look at asm-sparc/namei.h for details.
+ */
+
+#define __emul_prefix() NULL
+
+#endif /* _ASM_M32R_NAMEI_H */
--- /dev/null
+#ifndef _ASM_NUMNODES_H_
+#define _ASM_NUMNODES_H_
+
+#include <linux/config.h>
+
+#ifdef CONFIG_DISCONTIGMEM
+
+#if defined(CONFIG_CHIP_M32700)
+#define NODES_SHIFT 1 /* Max 2 Nodes */
+#endif /* CONFIG_CHIP_M32700 */
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#endif /* _ASM_NUMNODES_H_ */
+
--- /dev/null
+/*
+ * include/asm/opsput_lan.h
+ *
+ * OPSPUT-LAN board
+ *
+ * Copyright (c) 2002-2004 Takeo Takahashi, Mamoru Sakugawa
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * $Id: opsput_lan.h,v 1.1 2004/07/27 06:54:20 sakugawa Exp $
+ */
+
+#ifndef _OPSPUT_OPSPUT_LAN_H
+#define _OPSPUT_OPSPUT_LAN_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * C functions use non-cache address.
+ */
+#define OPSPUT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
+#else
+#define OPSPUT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
+#endif /* __ASSEMBLY__ */
+
+/* ICU
+ * ICUISTS: status register
+ * ICUIREQ0: request register
+ * ICUIREQ1: request register
+ * ICUCR3: control register for CFIREQ# interrupt
+ * ICUCR4: control register for CFC Card insert interrupt
+ * ICUCR5: control register for CFC Card eject interrupt
+ * ICUCR6: control register for external interrupt
+ * ICUCR11: control register for MMC Card insert/eject interrupt
+ * ICUCR13: control register for SC error interrupt
+ * ICUCR14: control register for SC receive interrupt
+ * ICUCR15: control register for SC send interrupt
+ * ICUCR16: control register for SIO0 receive interrupt
+ * ICUCR17: control register for SIO0 send interrupt
+ */
+#define OPSPUT_LAN_IRQ_LAN (OPSPUT_LAN_PLD_IRQ_BASE + 1) /* LAN */
+#define OPSPUT_LAN_IRQ_I2C (OPSPUT_LAN_PLD_IRQ_BASE + 3) /* I2C */
+
+#define OPSPUT_LAN_ICUISTS __reg16(OPSPUT_LAN_BASE + 0xc0002)
+#define OPSPUT_LAN_ICUISTS_VECB_MASK (0xf000)
+#define OPSPUT_LAN_VECB(x) ((x) & OPSPUT_LAN_ICUISTS_VECB_MASK)
+#define OPSPUT_LAN_ICUISTS_ISN_MASK (0x07c0)
+#define OPSPUT_LAN_ICUISTS_ISN(x) ((x) & OPSPUT_LAN_ICUISTS_ISN_MASK)
+#define OPSPUT_LAN_ICUIREQ0 __reg16(OPSPUT_LAN_BASE + 0xc0004)
+#define OPSPUT_LAN_ICUCR1 __reg16(OPSPUT_LAN_BASE + 0xc0010)
+#define OPSPUT_LAN_ICUCR3 __reg16(OPSPUT_LAN_BASE + 0xc0014)
+
+#endif /* _OPSPUT_OPSPUT_LAN_H */
--- /dev/null
+/*
+ * include/asm/opsput_lcd.h
+ *
+ * OPSPUT-LCD board
+ *
+ * Copyright (c) 2002 Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * $Id: opsput_lcd.h,v 1.1 2004/07/27 06:54:20 sakugawa Exp $
+ */
+
+#ifndef _OPSPUT_OPSPUT_LCD_H
+#define _OPSPUT_OPSPUT_LCD_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * C functions use non-cache address.
+ */
+#define OPSPUT_LCD_BASE (0x10000000 /* + NONCACHE_OFFSET */)
+#else
+#define OPSPUT_LCD_BASE (0x10000000 + NONCACHE_OFFSET)
+#endif /* __ASSEMBLY__ */
+
+/*
+ * ICU
+ */
+#define OPSPUT_LCD_IRQ_BAT_INT (OPSPUT_LCD_PLD_IRQ_BASE + 1)
+#define OPSPUT_LCD_IRQ_USB_INT1 (OPSPUT_LCD_PLD_IRQ_BASE + 2)
+#define OPSPUT_LCD_IRQ_AUDT0 (OPSPUT_LCD_PLD_IRQ_BASE + 3)
+#define OPSPUT_LCD_IRQ_AUDT2 (OPSPUT_LCD_PLD_IRQ_BASE + 4)
+#define OPSPUT_LCD_IRQ_BATSIO_RCV (OPSPUT_LCD_PLD_IRQ_BASE + 16)
+#define OPSPUT_LCD_IRQ_BATSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 17)
+#define OPSPUT_LCD_IRQ_ASNDSIO_RCV (OPSPUT_LCD_PLD_IRQ_BASE + 18)
+#define OPSPUT_LCD_IRQ_ASNDSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 19)
+#define OPSPUT_LCD_IRQ_ACNLSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 21)
+
+#define OPSPUT_LCD_ICUISTS __reg16(OPSPUT_LCD_BASE + 0x300002)
+#define OPSPUT_LCD_ICUISTS_VECB_MASK (0xf000)
+#define OPSPUT_LCD_VECB(x) ((x) & OPSPUT_LCD_ICUISTS_VECB_MASK)
+#define OPSPUT_LCD_ICUISTS_ISN_MASK (0x07c0)
+#define OPSPUT_LCD_ICUISTS_ISN(x) ((x) & OPSPUT_LCD_ICUISTS_ISN_MASK)
+#define OPSPUT_LCD_ICUIREQ0 __reg16(OPSPUT_LCD_BASE + 0x300004)
+#define OPSPUT_LCD_ICUIREQ1 __reg16(OPSPUT_LCD_BASE + 0x300006)
+#define OPSPUT_LCD_ICUCR1 __reg16(OPSPUT_LCD_BASE + 0x300020)
+#define OPSPUT_LCD_ICUCR2 __reg16(OPSPUT_LCD_BASE + 0x300022)
+#define OPSPUT_LCD_ICUCR3 __reg16(OPSPUT_LCD_BASE + 0x300024)
+#define OPSPUT_LCD_ICUCR4 __reg16(OPSPUT_LCD_BASE + 0x300026)
+#define OPSPUT_LCD_ICUCR16 __reg16(OPSPUT_LCD_BASE + 0x300030)
+#define OPSPUT_LCD_ICUCR17 __reg16(OPSPUT_LCD_BASE + 0x300032)
+#define OPSPUT_LCD_ICUCR18 __reg16(OPSPUT_LCD_BASE + 0x300034)
+#define OPSPUT_LCD_ICUCR19 __reg16(OPSPUT_LCD_BASE + 0x300036)
+#define OPSPUT_LCD_ICUCR21 __reg16(OPSPUT_LCD_BASE + 0x30003a)
+
+#endif /* _OPSPUT_OPSPUT_LCD_H */
--- /dev/null
+/*
+ * include/asm/opsput/opsput_pld.h
+ *
+ * Definitions for Programable Logic Device(PLD) on OPSPUT board.
+ *
+ * Copyright (c) 2002 Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * $Id: opsput_pld.h,v 1.1 2004/07/27 06:54:20 sakugawa Exp $
+ */
+
+#ifndef _OPSPUT_OPSPUT_PLD_H
+#define _OPSPUT_OPSPUT_PLD_H
+
+#include <linux/config.h>
+
+#define PLD_PLAT_BASE 0x1cc00000
+
+#ifndef __ASSEMBLY__
+/*
+ * C functions use non-cache address.
+ */
+#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
+#define __reg8 (volatile unsigned char *)
+#define __reg16 (volatile unsigned short *)
+#define __reg32 (volatile unsigned int *)
+#else
+#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
+#define __reg8
+#define __reg16
+#define __reg32
+#endif /* __ASSEMBLY__ */
+
+/* CFC */
+#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
+#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
+#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
+#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
+#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
+#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
+#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
+#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
+
+/* MMC */
+#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
+#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
+#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
+#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
+#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
+#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
+#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
+#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
+#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
+#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
+#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
+#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
+
+/* ICU
+ * ICUISTS: status register
+ * ICUIREQ0: request register
+ * ICUIREQ1: request register
+ * ICUCR3: control register for CFIREQ# interrupt
+ * ICUCR4: control register for CFC Card insert interrupt
+ * ICUCR5: control register for CFC Card eject interrupt
+ * ICUCR6: control register for external interrupt
+ * ICUCR11: control register for MMC Card insert/eject interrupt
+ * ICUCR13: control register for SC error interrupt
+ * ICUCR14: control register for SC receive interrupt
+ * ICUCR15: control register for SC send interrupt
+ * ICUCR16: control register for SIO0 receive interrupt
+ * ICUCR17: control register for SIO0 send interrupt
+ */
+#if !defined(CONFIG_PLAT_USRV)
+#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
+#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
+#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
+#define PLD_IRQ_CFIREQ (OPSPUT_PLD_IRQ_BASE + 3) /* CF IREQ */
+#define PLD_IRQ_CFC_INSERT (OPSPUT_PLD_IRQ_BASE + 4) /* CF Insert */
+#define PLD_IRQ_CFC_EJECT (OPSPUT_PLD_IRQ_BASE + 5) /* CF Eject */
+#define PLD_IRQ_EXINT (OPSPUT_PLD_IRQ_BASE + 6) /* EXINT */
+#define PLD_IRQ_INT7 (OPSPUT_PLD_IRQ_BASE + 7) /* reserved */
+#define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */
+#define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */
+#define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */
+#define PLD_IRQ_MMCCARD (OPSPUT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
+#define PLD_IRQ_INT12 (OPSPUT_PLD_IRQ_BASE + 12) /* reserved */
+#define PLD_IRQ_SC_ERROR (OPSPUT_PLD_IRQ_BASE + 13) /* SC error */
+#define PLD_IRQ_SC_RCV (OPSPUT_PLD_IRQ_BASE + 14) /* SC receive */
+#define PLD_IRQ_SC_SND (OPSPUT_PLD_IRQ_BASE + 15) /* SC send */
+#define PLD_IRQ_SIO0_RCV (OPSPUT_PLD_IRQ_BASE + 16) /* SIO receive */
+#define PLD_IRQ_SIO0_SND (OPSPUT_PLD_IRQ_BASE + 17) /* SIO send */
+#define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */
+#define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */
+#define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */
+#define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */
+#define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */
+#define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */
+#define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */
+#define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */
+#define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */
+#define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */
+#define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */
+#define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */
+#define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */
+#define PLD_IRQ_INT31 (OPSPUT_PLD_IRQ_BASE + 31) /* reserved */
+
+#else /* CONFIG_PLAT_USRV */
+
+#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
+#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
+#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
+#define PLD_IRQ_CF0 (OPSPUT_PLD_IRQ_BASE + 3) /* CF0# */
+#define PLD_IRQ_CF1 (OPSPUT_PLD_IRQ_BASE + 4) /* CF1# */
+#define PLD_IRQ_CF2 (OPSPUT_PLD_IRQ_BASE + 5) /* CF2# */
+#define PLD_IRQ_CF3 (OPSPUT_PLD_IRQ_BASE + 6) /* CF3# */
+#define PLD_IRQ_CF4 (OPSPUT_PLD_IRQ_BASE + 7) /* CF4# */
+#define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */
+#define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */
+#define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */
+#define PLD_IRQ_INT11 (OPSPUT_PLD_IRQ_BASE + 11) /* reserved */
+#define PLD_IRQ_UART0 (OPSPUT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
+#define PLD_IRQ_UART1 (OPSPUT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
+#define PLD_IRQ_INT14 (OPSPUT_PLD_IRQ_BASE + 14) /* reserved */
+#define PLD_IRQ_INT15 (OPSPUT_PLD_IRQ_BASE + 15) /* reserved */
+#define PLD_IRQ_SNDINT (OPSPUT_PLD_IRQ_BASE + 16) /* SNDINT# */
+#define PLD_IRQ_INT17 (OPSPUT_PLD_IRQ_BASE + 17) /* reserved */
+#define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */
+#define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */
+#define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */
+#define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */
+#define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */
+#define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */
+#define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */
+#define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */
+#define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */
+#define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */
+#define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */
+#define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */
+#define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */
+
+#endif /* CONFIG_PLAT_USRV */
+
+#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
+#define PLD_ICUISTS_VECB_MASK (0xf000)
+#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
+#define PLD_ICUISTS_ISN_MASK (0x07c0)
+#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
+#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
+#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
+#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
+#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
+#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
+#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
+#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
+#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
+#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
+#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
+#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
+#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
+#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
+#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
+#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
+#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
+#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
+#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
+#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
+#define PLD_ICUCR_IEN (0x1000)
+#define PLD_ICUCR_IREQ (0x0100)
+#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
+#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
+#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
+#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
+#define PLD_ICUCR_ILEVEL0 (0x0000)
+#define PLD_ICUCR_ILEVEL1 (0x0001)
+#define PLD_ICUCR_ILEVEL2 (0x0002)
+#define PLD_ICUCR_ILEVEL3 (0x0003)
+#define PLD_ICUCR_ILEVEL4 (0x0004)
+#define PLD_ICUCR_ILEVEL5 (0x0005)
+#define PLD_ICUCR_ILEVEL6 (0x0006)
+#define PLD_ICUCR_ILEVEL7 (0x0007)
+
+/* Power Control of MMC and CF */
+#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
+#define PLD_CPCR_CF 0x0001
+#define PLD_CPCR_MMC 0x0002
+
+/* LED Control
+ *
+ * 1: DIP swich side
+ * 2: Reset switch side
+ */
+#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
+#define PLD_IOLED_1_ON 0x001
+#define PLD_IOLED_1_OFF 0x000
+#define PLD_IOLED_2_ON 0x002
+#define PLD_IOLED_2_OFF 0x000
+
+/* DIP Switch
+ * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
+ * 1: -
+ * 2: -
+ * 3: -
+ */
+#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
+#define PLD_IOSWSTS_IOSW2 0x0200
+#define PLD_IOSWSTS_IOSW1 0x0100
+#define PLD_IOSWSTS_IOWP0 0x0001
+
+/* CRC */
+#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
+#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
+#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
+#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
+#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
+#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
+
+/* RTC */
+#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
+#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
+#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
+#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
+#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
+
+/* SIO0 */
+#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
+#define PLD_ESIO0CR_TXEN 0x0001
+#define PLD_ESIO0CR_RXEN 0x0002
+#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
+#define PLD_ESIO0MOD0_CTSS 0x0040
+#define PLD_ESIO0MOD0_RTSS 0x0080
+#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
+#define PLD_ESIO0MOD1_LMFS 0x0010
+#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
+#define PLD_ESIO0STS_TEMP 0x0001
+#define PLD_ESIO0STS_TXCP 0x0002
+#define PLD_ESIO0STS_RXCP 0x0004
+#define PLD_ESIO0STS_TXSC 0x0100
+#define PLD_ESIO0STS_RXSC 0x0200
+#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
+#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
+#define PLD_ESIO0INTCR_TXIEN 0x0002
+#define PLD_ESIO0INTCR_RXCEN 0x0004
+#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
+#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
+#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
+
+/* SIM Card */
+#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
+#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
+#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
+#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
+#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
+#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
+#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
+
+#endif /* _OPSPUT_OPSPUT_PLD.H */
--- /dev/null
+#ifndef _ASM_M32R_PAGE_H
+#define _ASM_M32R_PAGE_H
+
+#include <linux/config.h>
+
+/* PAGE_SHIFT determines the page size */
+#define PAGE_SHIFT 12
+#define PAGE_SIZE (1UL << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+extern void clear_page(void *to);
+extern void copy_page(void *to, void *from);
+
+#define clear_user_page(page, vaddr, pg) clear_page(page)
+#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long pmd; } pmd_t;
+typedef struct { unsigned long pgd; } pgd_t;
+#define pte_val(x) ((x).pte)
+#define PTE_MASK PAGE_MASK
+
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pmd_val(x) ((x).pmd)
+#define pgd_val(x) ((x).pgd)
+#define pgprot_val(x) ((x).pgprot)
+
+#define __pte(x) ((pte_t) { (x) } )
+#define __pmd(x) ((pmd_t) { (x) } )
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __pgprot(x) ((pgprot_t) { (x) } )
+
+#endif /* !__ASSEMBLY__ */
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
+
+/*
+ * This handles the memory map.. We could make this a config
+ * option, but too many people screw it up, and too few need
+ * it.
+ *
+ * A __PAGE_OFFSET of 0xC0000000 means that the kernel has
+ * a virtual address space of one gigabyte, which limits the
+ * amount of physical memory you can use to about 950MB.
+ *
+ * If you want more physical memory than this then see the CONFIG_HIGHMEM4G
+ * and CONFIG_HIGHMEM64G options in the kernel configuration.
+ */
+
+
+/* This handles the memory map.. */
+
+#ifndef __ASSEMBLY__
+
+/* Pure 2^n version of get_order */
+static __inline__ int get_order(unsigned long size)
+{
+ int order;
+
+ size = (size - 1) >> (PAGE_SHIFT - 1);
+ order = -1;
+ do {
+ size >>= 1;
+ order++;
+ } while (size);
+
+ return order;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#define __MEMORY_START CONFIG_MEMORY_START
+#define __MEMORY_SIZE CONFIG_MEMORY_SIZE
+
+#ifdef CONFIG_MMU
+#define __PAGE_OFFSET (0x80000000)
+#else
+#define __PAGE_OFFSET (0x00000000)
+#endif
+
+#define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET)
+#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
+#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
+
+#ifndef CONFIG_DISCONTIGMEM
+#define PFN_BASE (CONFIG_MEMORY_START >> PAGE_SHIFT)
+#define pfn_to_page(pfn) (mem_map + ((pfn) - PFN_BASE))
+#define page_to_pfn(page) \
+ ((unsigned long)((page) - mem_map) + PFN_BASE)
+#define pfn_valid(pfn) (((pfn) - PFN_BASE) < max_mapnr)
+#endif /* !CONFIG_DISCONTIGMEM */
+
+#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC )
+
+#define devmem_is_allowed(x) 1
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_PAGE_H */
+
--- /dev/null
+#ifndef _ASM_M32R_PARAM_H
+#define _ASM_M32R_PARAM_H
+
+/* $Id$ */
+
+/* orig : i386 2.5.67 */
+
+#ifdef __KERNEL__
+# define HZ 100 /* Internal kernel timer frequency */
+# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE 4096
+
+#ifndef NOGROUP
+#define NOGROUP (-1)
+#endif
+
+#define MAXHOSTNAMELEN 64 /* max length of hostname */
+
+#endif /* _ASM_M32R_PARAM_H */
+
--- /dev/null
+#ifndef _ASM_M32R_PCI_H
+#define _ASM_M32R_PCI_H
+
+/* $Id$ */
+
+#include <asm-generic/pci.h>
+
+#define PCI_DMA_BUS_IS_PHYS (1)
+
+#endif /* _ASM_M32R_PCI_H */
--- /dev/null
+#ifndef __ARCH_M32R_PERCPU__
+#define __ARCH_M32R_PERCPU__
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_M32R_PERCPU__ */
--- /dev/null
+#ifndef _ASM_M32R_PGALLOC_H
+#define _ASM_M32R_PGALLOC_H
+
+/* $Id$ */
+
+#include <linux/config.h>
+#include <linux/mm.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+
+#define pmd_populate_kernel(mm, pmd, pte) \
+ set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
+
+static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+ struct page *pte)
+{
+ set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
+}
+
+/*
+ * Allocate and free page tables.
+ */
+static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL);
+
+ if (pgd)
+ clear_page(pgd);
+
+ return pgd;
+}
+
+static __inline__ void pgd_free(pgd_t *pgd)
+{
+ free_page((unsigned long)pgd);
+}
+
+static __inline__ pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+{
+ pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL);
+
+ if (pte)
+ clear_page(pte);
+
+ return pte;
+}
+
+static __inline__ struct page *pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+{
+ struct page *pte = alloc_page(GFP_KERNEL);
+
+ if (pte)
+ clear_page(page_address(pte));
+
+ return pte;
+}
+
+static __inline__ void pte_free_kernel(pte_t *pte)
+{
+ free_page((unsigned long)pte);
+}
+
+static __inline__ void pte_free(struct page *pte)
+{
+ __free_page(pte);
+}
+
+#define __pte_free_tlb(tlb, pte) pte_free((pte))
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ * (In the PAE case we free the pmds as part of the pgd.)
+ */
+
+#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(x) do { } while (0)
+#define __pmd_free_tlb(tlb, x) do { } while (0)
+#define pgd_populate(mm, pmd, pte) BUG()
+
+#define check_pgt_cache() do { } while (0)
+
+#endif /* _ASM_M32R_PGALLOC_H */
+
--- /dev/null
+#ifndef _ASM_M32R_PGTABLE_2LEVEL_H
+#define _ASM_M32R_PGTABLE_2LEVEL_H
+
+/* $Id$ */
+
+#include <linux/config.h>
+
+/*
+ * traditional M32R two-level paging structure:
+ */
+
+#define PGDIR_SHIFT 22
+#define PTRS_PER_PGD 1024
+
+/*
+ * the M32R is two-level, so we don't really have any
+ * PMD directory physically.
+ */
+#define PMD_SHIFT 22
+#define PTRS_PER_PMD 1
+
+#define PTRS_PER_PTE 1024
+
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+static __inline__ int pgd_none(pgd_t pgd) { return 0; }
+static __inline__ int pgd_bad(pgd_t pgd) { return 0; }
+static __inline__ int pgd_present(pgd_t pgd) { return 1; }
+#define pgd_clear(xp) do { } while (0)
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified. Thus, the following
+ * hook is made available.
+ */
+#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval)
+/*
+ * (pmds are folded into pgds so this doesnt get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
+#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
+
+#define pgd_page(pgd) \
+((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
+
+static __inline__ pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
+{
+ return (pmd_t *) dir;
+}
+
+#define ptep_get_and_clear(xp) __pte(xchg(&(xp)->pte, 0))
+#define pte_same(a, b) (pte_val(a) == pte_val(b))
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+#define pte_none(x) (!pte_val(x))
+#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
+#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+/* M32R_FIXME : PTE_FILE_MAX_BITS, pte_to_pgoff, pgoff_to_pte */
+#define PTE_FILE_MAX_BITS 31
+#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
+#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
+
+#endif /* _ASM_M32R_PGTABLE_2LEVEL_H */
+
--- /dev/null
+#ifndef _ASM_M32R_PGTABLE_H
+#define _ASM_M32R_PGTABLE_H
+
+/* $Id$ */
+
+/*
+ * The Linux memory management assumes a three-level page table setup. On
+ * the M32R, we use that, but "fold" the mid level into the top-level page
+ * table, so that we physically have the same two-level page table as the
+ * M32R mmu expects.
+ *
+ * This file contains the functions and defines necessary to modify and use
+ * the M32R page table tree.
+ */
+
+/* CAUTION!: If you change macro definitions in this file, you might have to
+ * change arch/m32r/mmu.S manually.
+ */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+#include <linux/threads.h>
+#include <asm/processor.h>
+#include <asm/addrspace.h>
+#include <asm/bitops.h>
+#include <asm/page.h>
+
+extern pgd_t swapper_pg_dir[1024];
+extern void paging_init(void);
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[1024];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The Linux x86 paging architecture is 'compile-time dual-mode', it
+ * implements both the traditional 2-level x86 page tables and the
+ * newer 3-level PAE-mode page tables.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/pgtable-2level.h>
+#endif
+
+#define pgtable_cache_init() do { } while (0)
+
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE - 1))
+#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE - 1))
+
+#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_PGD_NR 0
+
+#ifndef __ASSEMBLY__
+/* Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_START KSEG2
+#define VMALLOC_END KSEG3
+
+/*
+ * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
+ * of the Pentium details, but assuming intel did the straightforward
+ * thing, this bit set in the page directory entry just means that
+ * the page directory entry points directly to a 4MB-aligned block of
+ * memory.
+ */
+
+/*
+ * M32R TLB format
+ *
+ * [0] [1:19] [20:23] [24:31]
+ * +-----------------------+----+-------------+
+ * | VPN |0000| ASID |
+ * +-----------------------+----+-------------+
+ * +-+---------------------+----+-+---+-+-+-+-+
+ * |0 PPN |0000|N|AC |L|G|V| |
+ * +-+---------------------+----+-+---+-+-+-+-+
+ * RWX
+ */
+
+#define _PAGE_BIT_DIRTY 0 /* software */
+#define _PAGE_BIT_FILE 0 /* when !present: nonlinear file
+ mapping */
+#define _PAGE_BIT_PRESENT 1 /* Valid */
+#define _PAGE_BIT_GLOBAL 2 /* Global */
+#define _PAGE_BIT_LARGE 3 /* Large */
+#define _PAGE_BIT_EXEC 4 /* Execute */
+#define _PAGE_BIT_WRITE 5 /* Write */
+#define _PAGE_BIT_READ 6 /* Read */
+#define _PAGE_BIT_NONCACHABLE 7 /* Non cachable */
+#define _PAGE_BIT_USER 8 /* software */
+#define _PAGE_BIT_ACCESSED 9 /* software */
+
+#define _PAGE_DIRTY \
+ (1UL << _PAGE_BIT_DIRTY) /* software : page changed */
+#define _PAGE_FILE \
+ (1UL << _PAGE_BIT_FILE) /* when !present: nonlinear file
+ mapping */
+#define _PAGE_PRESENT \
+ (1UL << _PAGE_BIT_PRESENT) /* Valid : Page is Valid */
+#define _PAGE_GLOBAL \
+ (1UL << _PAGE_BIT_GLOBAL) /* Global */
+#define _PAGE_LARGE \
+ (1UL << _PAGE_BIT_LARGE) /* Large */
+#define _PAGE_EXEC \
+ (1UL << _PAGE_BIT_EXEC) /* Execute */
+#define _PAGE_WRITE \
+ (1UL << _PAGE_BIT_WRITE) /* Write */
+#define _PAGE_READ \
+ (1UL << _PAGE_BIT_READ) /* Read */
+#define _PAGE_NONCACHABLE \
+ (1UL<<_PAGE_BIT_NONCACHABLE) /* Non cachable */
+#define _PAGE_USER \
+ (1UL << _PAGE_BIT_USER) /* software : user space access
+ allowed */
+#define _PAGE_ACCESSED \
+ (1UL << _PAGE_BIT_ACCESSED) /* software : page referenced */
+
+#define _PAGE_TABLE \
+ ( _PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_USER \
+ | _PAGE_ACCESSED | _PAGE_DIRTY )
+#define _KERNPG_TABLE \
+ ( _PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED \
+ | _PAGE_DIRTY )
+#define _PAGE_CHG_MASK \
+ ( PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY )
+
+#ifdef CONFIG_MMU
+#define PAGE_NONE \
+ __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+#define PAGE_SHARED \
+ __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_USER \
+ | _PAGE_ACCESSED)
+#define PAGE_SHARED_X \
+ __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_WRITE | _PAGE_READ \
+ | _PAGE_USER | _PAGE_ACCESSED)
+#define PAGE_COPY \
+ __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_USER \
+ | _PAGE_ACCESSED)
+#define PAGE_COPY_X \
+ __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_USER \
+ | _PAGE_ACCESSED)
+#define PAGE_READONLY \
+ __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_USER | _PAGE_ACCESSED)
+#define PAGE_READONLY_X \
+ __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_USER \
+ | _PAGE_ACCESSED)
+
+#define __PAGE_KERNEL \
+ ( _PAGE_PRESENT | _PAGE_EXEC | _PAGE_WRITE | _PAGE_READ | _PAGE_DIRTY \
+ | _PAGE_ACCESSED )
+#define __PAGE_KERNEL_RO ( __PAGE_KERNEL & ~_PAGE_WRITE )
+#define __PAGE_KERNEL_NOCACHE ( __PAGE_KERNEL | _PAGE_NONCACHABLE)
+
+#define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
+
+#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
+#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
+#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
+
+#else
+#define PAGE_NONE __pgprot(0)
+#define PAGE_SHARED __pgprot(0)
+#define PAGE_SHARED_X __pgprot(0)
+#define PAGE_COPY __pgprot(0)
+#define PAGE_COPY_X __pgprot(0)
+#define PAGE_READONLY __pgprot(0)
+#define PAGE_READONLY_X __pgprot(0)
+
+#define PAGE_KERNEL __pgprot(0)
+#define PAGE_KERNEL_RO __pgprot(0)
+#define PAGE_KERNEL_NOCACHE __pgprot(0)
+#endif /* CONFIG_MMU */
+
+/*
+ * The i386 can't do page protection for execute, and considers that
+ * the same are read. Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ */
+ /* rwx */
+#define __P000 PAGE_NONE
+#define __P001 PAGE_READONLY_X
+#define __P010 PAGE_COPY_X
+#define __P011 PAGE_COPY_X
+#define __P100 PAGE_READONLY
+#define __P101 PAGE_READONLY_X
+#define __P110 PAGE_COPY_X
+#define __P111 PAGE_COPY_X
+
+#define __S000 PAGE_NONE
+#define __S001 PAGE_READONLY_X
+#define __S010 PAGE_SHARED
+#define __S011 PAGE_SHARED_X
+#define __S100 PAGE_READONLY
+#define __S101 PAGE_READONLY_X
+#define __S110 PAGE_SHARED
+#define __S111 PAGE_SHARED_X
+
+/* page table for 0-4MB for everybody */
+
+#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
+#define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
+
+#define pmd_none(x) (!pmd_val(x))
+#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
+#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
+#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) \
+ != _KERNPG_TABLE)
+
+#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static __inline__ int pte_user(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_USER;
+}
+
+static __inline__ int pte_read(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_READ;
+}
+
+static __inline__ int pte_exec(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_EXEC;
+}
+
+static __inline__ int pte_dirty(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_DIRTY;
+}
+
+static __inline__ int pte_young(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_ACCESSED;
+}
+
+static __inline__ int pte_write(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_WRITE;
+}
+
+/*
+ * The following only works if pte_present() is not true.
+ */
+static __inline__ int pte_file(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_FILE;
+}
+
+static __inline__ pte_t pte_rdprotect(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_READ;
+ return pte;
+}
+
+static __inline__ pte_t pte_exprotect(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_EXEC;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkclean(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_DIRTY;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkold(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_ACCESSED;return pte;}
+
+static __inline__ pte_t pte_wrprotect(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_WRITE;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkread(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_READ;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkexec(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_EXEC;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkdirty(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_DIRTY;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkyoung(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_ACCESSED;
+ return pte;
+}
+
+static __inline__ pte_t pte_mkwrite(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_WRITE;
+ return pte;
+}
+
+static __inline__ int ptep_test_and_clear_dirty(pte_t *ptep)
+{
+ return test_and_clear_bit(_PAGE_BIT_DIRTY, ptep);
+}
+
+static __inline__ int ptep_test_and_clear_young(pte_t *ptep)
+{
+ return test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep);
+}
+
+static __inline__ void ptep_set_wrprotect(pte_t *ptep)
+{
+ clear_bit(_PAGE_BIT_WRITE, ptep);
+}
+
+static __inline__ void ptep_mkdirty(pte_t *ptep)
+{
+ set_bit(_PAGE_BIT_DIRTY, ptep);
+}
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), pgprot)
+
+static __inline__ pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) \
+ | pgprot_val(newprot)));
+
+ return pte;
+}
+
+#define page_pte(page) page_pte_prot(page, __pgprot(0))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+
+static __inline__ void pmd_set(pmd_t * pmdp, pte_t * ptep)
+{
+ pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
+}
+
+#define pmd_page_kernel(pmd) \
+ ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+
+#ifndef CONFIG_DISCONTIGMEM
+#define pmd_page(pmd) (mem_map + ((pmd_val(pmd) >> PAGE_SHIFT) - PFN_BASE))
+#endif /* !CONFIG_DISCONTIGMEM */
+
+/* to find an entry in a page-table-directory. */
+#define pgd_index(address) \
+ (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+#define pmd_index(address) \
+ (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
+
+#define pte_index(address) \
+ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, address) \
+ ((pte_t *)pmd_page_kernel(*(dir)) + pte_index(address))
+#define pte_offset_map(dir, address) \
+ ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
+#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
+#define pte_unmap(pte) do { } while (0)
+#define pte_unmap_nested(pte) do { } while (0)
+
+/* Encode and de-code a swap entry */
+#define __swp_type(x) (((x).val >> 1) & 0x3f)
+#define __swp_offset(x) ((x).val >> 8)
+#define __swp_entry(type, offset) \
+ ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+
+#endif /* !__ASSEMBLY__ */
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) (1)
+
+#define io_remap_page_range remap_page_range
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+#define __HAVE_ARCH_PTEP_MKDIRTY
+#define __HAVE_ARCH_PTE_SAME
+#include <asm-generic/pgtable.h>
+
+#endif /* _ASM_M32R_PGTABLE_H */
+
--- /dev/null
+#ifndef _ASM_M32R_POLL_H
+#define _ASM_M32R_POLL_H
+
+/*
+ * poll(2) bit definitions. Based on <asm-i386/poll.h>.
+ *
+ * Modified 2004
+ * Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#define POLLIN 0x0001
+#define POLLPRI 0x0002
+#define POLLOUT 0x0004
+#define POLLERR 0x0008
+#define POLLHUP 0x0010
+#define POLLNVAL 0x0020
+
+#define POLLRDNORM 0x0040
+#define POLLRDBAND 0x0080
+#define POLLWRNORM 0x0100
+#define POLLWRBAND 0x0200
+#define POLLMSG 0x0400
+#define POLLREMOVE 0x1000
+
+struct pollfd {
+ int fd;
+ short events;
+ short revents;
+};
+
+#endif /* _ASM_M32R_POLL_H */
--- /dev/null
+#ifndef _ASM_M32R_POSIX_TYPES_H
+#define _ASM_M32R_POSIX_TYPES_H
+
+/* $Id$ */
+
+/* orig : i386, sh 2.4.18 */
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+ unsigned long *__tmp = __p->fds_bits;
+ int __i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 16:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ __tmp[ 8] = 0; __tmp[ 9] = 0;
+ __tmp[10] = 0; __tmp[11] = 0;
+ __tmp[12] = 0; __tmp[13] = 0;
+ __tmp[14] = 0; __tmp[15] = 0;
+ return;
+
+ case 8:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ return;
+
+ case 4:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ return;
+ }
+ }
+ __i = __FDSET_LONGS;
+ while (__i) {
+ __i--;
+ *__tmp = 0;
+ __tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* _ASM_M32R_POSIX_TYPES_H */
--- /dev/null
+#ifndef _ASM_M32R_PROCESSOR_H
+#define _ASM_M32R_PROCESSOR_H
+
+/* $Id$ */
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 by Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
+ */
+
+/*
+ * include/asm-m32r/processor.h
+ *
+ * Copyright (C) 1994 Linus Torvalds
+ */
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h> /* pt_regs */
+
+#include <asm/cachectl.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l; })
+
+/*
+ * CPU type and hardware bug flags. Kept separately for each CPU.
+ * Members of this structure are referenced in head.S, so think twice
+ * before touching them. [mj]
+ */
+
+struct cpuinfo_m32r {
+ unsigned long pgtable_cache_sz;
+ unsigned long cpu_clock;
+ unsigned long bus_clock;
+ unsigned long timer_divide;
+ unsigned long loops_per_jiffy;
+};
+
+/*
+ * capabilities of CPUs
+ */
+
+extern struct cpuinfo_m32r boot_cpu_data;
+
+#ifdef CONFIG_SMP
+extern struct cpuinfo_m32r cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data &boot_cpu_data
+#define current_cpu_data boot_cpu_data
+#endif
+
+/*
+ * User space process size: 2GB (default).
+ */
+#ifdef CONFIG_MMU
+#define TASK_SIZE (0x80000000UL)
+#else
+#define TASK_SIZE (0x00400000UL)
+#endif
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
+
+typedef struct {
+ unsigned long seg;
+} mm_segment_t;
+
+struct debug_trap {
+ int nr_trap;
+ unsigned long addr;
+ unsigned long insn;
+};
+
+struct thread_struct {
+ unsigned long address;
+ unsigned long trap_no; /* Trap number */
+ unsigned long error_code; /* Error code of trap */
+ unsigned long lr; /* saved pc */
+ unsigned long sp; /* user stack pointer */
+ struct debug_trap debug_trap;
+};
+
+#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
+
+#define INIT_THREAD { \
+ .sp = INIT_SP, \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+
+/* User process Backup PSW */
+#define USERPS_BPSW (M32R_PSW_BSM|M32R_PSW_BIE|M32R_PSW_BPM)
+
+#define start_thread(regs, new_pc, new_spu) \
+ do { \
+ set_fs(USER_DS); \
+ regs->psw = (regs->psw | USERPS_BPSW) & 0x0000FFFFUL; \
+ regs->bpc = new_pc; \
+ regs->spu = new_spu; \
+ } while (0)
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+#define prepare_to_copy(tsk) do { } while (0)
+
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Copy and release all segment info associated with a VM */
+extern void copy_segments(struct task_struct *p, struct mm_struct * mm);
+extern void release_segments(struct mm_struct * mm);
+
+extern unsigned long thread_saved_pc(struct task_struct *);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(p, mm) do { } while (0)
+#define release_segments(mm) do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+#define KSTK_EIP(tsk) ((tsk)->thread.lr)
+#define KSTK_ESP(tsk) ((tsk)->thread.sp)
+
+#define THREAD_SIZE (2*PAGE_SIZE)
+
+/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
+static __inline__ void rep_nop(void)
+{
+ __asm__ __volatile__(
+ "nop \n\t"
+ "nop \n\t"
+ :
+ :
+ : "memory");
+}
+
+#define cpu_relax() rep_nop()
+
+#endif /* _ASM_M32R_PROCESSOR_H */
--- /dev/null
+#ifndef _ASM_M32R_PTRACE_H
+#define _ASM_M32R_PTRACE_H
+
+/*
+ * linux/include/asm-m32r/ptrace.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * M32R version:
+ * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <linux/config.h>
+#include <asm/m32r.h> /* M32R_PSW_BSM, M32R_PSW_BPM */
+
+/* 0 - 13 are integer registers (general purpose registers). */
+#define PT_R4 0
+#define PT_R5 1
+#define PT_R6 2
+#define PT_REGS 3
+#define PT_R0 4
+#define PT_R1 5
+#define PT_R2 6
+#define PT_R3 7
+#define PT_R7 8
+#define PT_R8 9
+#define PT_R9 10
+#define PT_R10 11
+#define PT_R11 12
+#define PT_R12 13
+#define PT_SYSCNR 14
+#define PT_R13 PT_FP
+#define PT_R14 PT_LR
+#define PT_R15 PT_SP
+
+/* processor status and miscellaneous context registers. */
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+#define PT_ACC0H 15
+#define PT_ACC0L 16
+#define PT_ACC1H 17
+#define PT_ACC1L 18
+#define PT_ACCH PT_ACC0H
+#define PT_ACCL PT_ACC0L
+#define PT_PSW 19
+#define PT_BPC 20
+#define PT_BBPSW 21
+#define PT_BBPC 22
+#define PT_SPU 23
+#define PT_FP 24
+#define PT_LR 25
+#define PT_SPI 26
+#define PT_ORIGR0 27
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+#define PT_ACCH 15
+#define PT_ACCL 16
+#define PT_PSW 17
+#define PT_BPC 18
+#define PT_BBPSW 19
+#define PT_BBPC 20
+#define PT_SPU 21
+#define PT_FP 22
+#define PT_LR 23
+#define PT_SPI 24
+#define PT_ORIGR0 25
+#else
+#error unknown isa conifiguration
+#endif
+
+/* virtual pt_reg entry for gdb */
+#define PT_PC 30
+#define PT_CBR 31
+#define PT_EVB 32
+
+
+/* Control registers. */
+#define SPR_CR0 PT_PSW
+#define SPR_CR1 PT_CBR /* read only */
+#define SPR_CR2 PT_SPI
+#define SPR_CR3 PT_SPU
+#define SPR_CR4
+#define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */
+#define SPR_CR6 PT_BPC
+#define SPR_CR7
+#define SPR_CR8 PT_BBPSW
+#define SPR_CR9
+#define SPR_CR10
+#define SPR_CR11
+#define SPR_CR12
+#define SPR_CR13 PT_WR
+#define SPR_CR14 PT_BBPC
+#define SPR_CR15
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+struct pt_regs {
+ /* Saved main processor registers. */
+ unsigned long r4;
+ unsigned long r5;
+ unsigned long r6;
+ struct pt_regs *pt_regs;
+ unsigned long r0;
+ unsigned long r1;
+ unsigned long r2;
+ unsigned long r3;
+ unsigned long r7;
+ unsigned long r8;
+ unsigned long r9;
+ unsigned long r10;
+ unsigned long r11;
+ unsigned long r12;
+ long syscall_nr;
+
+ /* Saved main processor status and miscellaneous context registers. */
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ unsigned long acc0h;
+ unsigned long acc0l;
+ unsigned long acc1h;
+ unsigned long acc1l;
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ unsigned long acch;
+ unsigned long accl;
+#else
+#error unknown isa configuration
+#endif
+ unsigned long psw;
+ unsigned long bpc; /* saved PC for TRAP syscalls */
+ unsigned long bbpsw;
+ unsigned long bbpc;
+ unsigned long spu; /* saved user stack */
+ unsigned long fp;
+ unsigned long lr; /* saved PC for JL syscalls */
+ unsigned long spi; /* saved kernel stack */
+ unsigned long orig_r0;
+};
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+
+#define PTRACE_OLDSETOPTIONS 21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD 0x00000001
+
+#ifdef __KERNEL__
+#if defined(CONFIG_ISA_M32R2) || defined(CONFIG_CHIP_VDEC2)
+#define user_mode(regs) ((M32R_PSW_BPM & (regs)->psw) != 0)
+#elif defined(CONFIG_ISA_M32R)
+#define user_mode(regs) ((M32R_PSW_BSM & (regs)->psw) != 0)
+#else
+#error unknown isa configuration
+#endif
+
+#define instruction_pointer(regs) ((regs)->bpc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+extern void show_regs(struct pt_regs *);
+
+extern void withdraw_debug_trap(struct pt_regs *regs);
+
+#endif /* __KERNEL */
+
+#endif /* _ASM_M32R_PTRACE_H */
--- /dev/null
+#ifndef _ASM_M32R_RESOURCE_H
+#define _ASM_M32R_RESOURCE_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * Resource limits
+ */
+
+#define RLIMIT_CPU 0 /* CPU time in ms */
+#define RLIMIT_FSIZE 1 /* Maximum filesize */
+#define RLIMIT_DATA 2 /* max data size */
+#define RLIMIT_STACK 3 /* max stack size */
+#define RLIMIT_CORE 4 /* max core file size */
+#define RLIMIT_RSS 5 /* max resident set size */
+#define RLIMIT_NPROC 6 /* max number of processes */
+#define RLIMIT_NOFILE 7 /* max number of open files */
+#define RLIMIT_MEMLOCK 8 /* max locked-in-memory address space */
+#define RLIMIT_AS 9 /* address space limit */
+#define RLIMIT_LOCKS 10 /* maximum file locks held */
+#define RLIMIT_SIGPENDING 11 /* max number of pending signals */
+#define RLIMIT_MSGQUEUE 12 /* maximum bytes in POSIX mqueues */
+
+#define RLIM_NLIMITS 13
+
+/*
+ * SuS says limits have to be unsigned.
+ * Which makes a ton more sense anyway.
+ */
+#define RLIM_INFINITY (~0UL)
+
+#ifdef __KERNEL__
+
+#define INIT_RLIMITS \
+{ \
+ { RLIM_INFINITY, RLIM_INFINITY }, \
+ { RLIM_INFINITY, RLIM_INFINITY }, \
+ { RLIM_INFINITY, RLIM_INFINITY }, \
+ { _STK_LIM, RLIM_INFINITY }, \
+ { 0, RLIM_INFINITY }, \
+ { RLIM_INFINITY, RLIM_INFINITY }, \
+ { 0, 0 }, \
+ { INR_OPEN, INR_OPEN }, \
+ { MLOCK_LIMIT, MLOCK_LIMIT }, \
+ { RLIM_INFINITY, RLIM_INFINITY }, \
+ { RLIM_INFINITY, RLIM_INFINITY }, \
+ { MAX_SIGPENDING, MAX_SIGPENDING }, \
+ { MQ_BYTES_MAX, MQ_BYTES_MAX }, \
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_RESOURCE_H */
--- /dev/null
+/* $Id: rtc.h,v 1.1.1.1 2004/03/25 04:29:22 hitoshiy Exp $ */
+
+#ifndef __RTC_H__
+#define __RTC_H__
+
+
+#include <linux/config.h>
+
+ /* Dallas DS1302 clock/calendar register numbers. */
+# define RTC_SECONDS 0
+# define RTC_MINUTES 1
+# define RTC_HOURS 2
+# define RTC_DAY_OF_MONTH 3
+# define RTC_MONTH 4
+# define RTC_WEEKDAY 5
+# define RTC_YEAR 6
+# define RTC_CONTROL 7
+
+ /* Bits in CONTROL register. */
+# define RTC_CONTROL_WRITEPROTECT 0x80
+# define RTC_TRICKLECHARGER 8
+
+ /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */
+# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */
+# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */
+# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */
+# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */
+# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */
+# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */
+# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */
+
+#ifdef CONFIG_M32700UT_DS1302
+extern unsigned char ds1302_readreg(int reg);
+extern void ds1302_writereg(int reg, unsigned char val);
+extern int ds1302_init(void);
+# define CMOS_READ(x) ds1302_readreg(x)
+# define CMOS_WRITE(val,reg) ds1302_writereg(reg,val)
+# define RTC_INIT() ds1302_init()
+#else
+ /* No RTC configured so we shouldn't try to access any. */
+# define CMOS_READ(x) 42
+# define CMOS_WRITE(x,y)
+# define RTC_INIT() (-1)
+#endif
+
+/*
+ * The struct used to pass data via the following ioctl. Similar to the
+ * struct tm in <time.h>, but it needs to be here so that the kernel
+ * source is self contained, allowing cross-compiles, etc. etc.
+ */
+struct rtc_time {
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+ int tm_mday;
+ int tm_mon;
+ int tm_year;
+ int tm_wday;
+ int tm_yday;
+ int tm_isdst;
+};
+
+/* ioctl() calls that are permitted to the /dev/rtc interface. */
+#define RTC_MAGIC 'p'
+#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */
+#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */
+#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int)
+#define RTC_MAX_IOCTL 0x0b
+
+#endif /* __RTC_H__ */
--- /dev/null
+#ifndef _ASM_M32R_SCATTERLIST_H
+#define _ASM_M32R_SCATTERLIST_H
+
+/* $Id$ */
+
+struct scatterlist {
+ char * address; /* Location data is to be transferred to, NULL for
+ * highmem page */
+ struct page * page; /* Location for highmem page, if any */
+ unsigned int offset;/* for highmem, page offset */
+
+ dma_addr_t dma_address;
+ unsigned int length;
+};
+
+#define ISA_DMA_THRESHOLD (0x1fffffff)
+
+#endif /* _ASM_M32R_SCATTERLIST_H */
--- /dev/null
+#ifndef _M32R_SECTIONS_H
+#define _M32R_SECTIONS_H
+
+/* nothing to see, move along */
+#include <asm-generic/sections.h>
+
+#endif /* _M32R_SECTIONS_H */
+
--- /dev/null
+#ifndef _ASM_M32R_SEGMENT_H
+#define _ASM_M32R_SEGMENT_H
+
+/* $Id$ */
+
+/* orig : i386 (2.4.18) */
+
+#define __KERNEL_CS 0x10
+#define __KERNEL_DS 0x18
+
+#define __USER_CS 0x23
+#define __USER_DS 0x2B
+
+#endif /* _ASM_M32R_SEGMENT_H */
--- /dev/null
+#ifndef _ASM_M32R_SEMAPHORE_H
+#define _ASM_M32R_SEMAPHORE_H
+
+#include <linux/linkage.h>
+
+#ifdef __KERNEL__
+
+/*
+ * SMP- and interrupt-safe semaphores..
+ *
+ * Copyright (C) 1996 Linus Torvalds
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <linux/config.h>
+#include <linux/wait.h>
+#include <linux/rwsem.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+
+#undef LOAD
+#undef STORE
+#ifdef CONFIG_SMP
+#define LOAD "lock"
+#define STORE "unlock"
+#else
+#define LOAD "ld"
+#define STORE "st"
+#endif
+
+struct semaphore {
+ atomic_t count;
+ int sleepers;
+ wait_queue_head_t wait;
+};
+
+#define __SEMAPHORE_INITIALIZER(name, n) \
+{ \
+ .count = ATOMIC_INIT(n), \
+ .sleepers = 0, \
+ .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
+}
+
+#define __MUTEX_INITIALIZER(name) \
+ __SEMAPHORE_INITIALIZER(name,1)
+
+#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
+ struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
+
+#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
+#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
+
+static inline void sema_init (struct semaphore *sem, int val)
+{
+/*
+ * *sem = (struct semaphore)__SEMAPHORE_INITIALIZER((*sem),val);
+ *
+ * i'd rather use the more flexible initialization above, but sadly
+ * GCC 2.7.2.3 emits a bogus warning. EGCS doesnt. Oh well.
+ */
+ atomic_set(&sem->count, val);
+ sem->sleepers = 0;
+ init_waitqueue_head(&sem->wait);
+}
+
+static inline void init_MUTEX (struct semaphore *sem)
+{
+ sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED (struct semaphore *sem)
+{
+ sema_init(sem, 0);
+}
+
+asmlinkage void __down_failed(void /* special register calling convention */);
+asmlinkage int __down_failed_interruptible(void /* params in registers */);
+asmlinkage int __down_failed_trylock(void /* params in registers */);
+asmlinkage void __up_wakeup(void /* special register calling convention */);
+
+asmlinkage void __down(struct semaphore * sem);
+asmlinkage int __down_interruptible(struct semaphore * sem);
+asmlinkage int __down_trylock(struct semaphore * sem);
+asmlinkage void __up(struct semaphore * sem);
+
+/*
+ * Atomically decrement the semaphore's count. If it goes negative,
+ * block the calling thread in the TASK_UNINTERRUPTIBLE state.
+ */
+static inline void down(struct semaphore * sem)
+{
+ unsigned long flags;
+ long count;
+
+ might_sleep();
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# down \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "addi %0, #-1; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (count)
+ : "r" (&sem->count)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ if (unlikely(count < 0))
+ __down(sem);
+}
+
+/*
+ * Interruptible try to acquire a semaphore. If we obtained
+ * it, return zero. If we were interrupted, returns -EINTR
+ */
+static inline int down_interruptible(struct semaphore * sem)
+{
+ unsigned long flags;
+ long count;
+ int result = 0;
+
+ might_sleep();
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# down_interruptible \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "addi %0, #-1; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (count)
+ : "r" (&sem->count)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ if (unlikely(count < 0))
+ result = __down_interruptible(sem);
+
+ return result;
+}
+
+/*
+ * Non-blockingly attempt to down() a semaphore.
+ * Returns zero if we acquired it
+ */
+static inline int down_trylock(struct semaphore * sem)
+{
+ unsigned long flags;
+ long count;
+ int result = 0;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# down_trylock \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "addi %0, #-1; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (count)
+ : "r" (&sem->count)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ if (unlikely(count < 0))
+ result = __down_trylock(sem);
+
+ return result;
+}
+
+/*
+ * Note! This is subtle. We jump to wake people up only if
+ * the semaphore was negative (== somebody was waiting on it).
+ * The default case (no contention) will result in NO
+ * jumps for both down() and up().
+ */
+static inline void up(struct semaphore * sem)
+{
+ unsigned long flags;
+ long count;
+
+ local_irq_save(flags);
+ __asm__ __volatile__ (
+ "# up \n\t"
+ DCACHE_CLEAR("%0", "r4", "%1")
+ LOAD" %0, @%1; \n\t"
+ "addi %0, #1; \n\t"
+ STORE" %0, @%1; \n\t"
+ : "=&r" (count)
+ : "r" (&sem->count)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ local_irq_restore(flags);
+
+ if (unlikely(count <= 0))
+ __up(sem);
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_SEMAPHORE_H */
--- /dev/null
+#ifndef _ASM_M32R_SEMBUF_H
+#define _ASM_M32R_SEMBUF_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * The semid64_ds structure for m32r architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+ struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
+ __kernel_time_t sem_otime; /* last semop time */
+ unsigned long __unused1;
+ __kernel_time_t sem_ctime; /* last change time */
+ unsigned long __unused2;
+ unsigned long sem_nsems; /* no. of semaphores in array */
+ unsigned long __unused3;
+ unsigned long __unused4;
+};
+
+#endif /* _ASM_M32R_SEMBUF_H */
--- /dev/null
+#ifndef _ASM_M32R_SERIAL_H
+#define _ASM_M32R_SERIAL_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * include/asm-m32r/serial.h
+ */
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define FOURPORT_FLAGS ASYNC_FOURPORT
+#define ACCENT_FLAGS 0
+#define BOCA_FLAGS 0
+#define HUB6_FLAGS 0
+#define RS_TABLE_SIZE 64
+#else
+#define RS_TABLE_SIZE
+#endif
+
+#define MCA_COM_FLAGS (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
+
+/*
+ * The following define the access methods for the HUB6 card. All
+ * access is through two ports for all 24 possible chips. The card is
+ * selected through the high 2 bits, the port on that card with the
+ * "middle" 3 bits, and the register on that port with the bottom
+ * 3 bits.
+ *
+ * While the access port and interrupt is configurable, the default
+ * port locations are 0x302 for the port control register, and 0x303
+ * for the data read/write register. Normally, the interrupt is at irq3
+ * but can be anything from 3 to 7 inclusive. Note that using 3 will
+ * require disabling com2.
+ */
+
+#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
+
+#define STD_SERIAL_PORT_DEFNS \
+ /* UART CLK PORT IRQ FLAGS */ \
+ { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
+ { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
+ { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
+ { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
+
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define EXTRA_SERIAL_PORT_DEFNS \
+ { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
+ { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
+ { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
+ { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
+ { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
+ { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
+ { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
+ { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
+ { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
+ { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
+ { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
+ { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
+ { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
+ { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
+ { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
+ { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
+ { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
+ { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
+ { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
+ { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
+ { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
+ { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
+ { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
+ { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
+ { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
+ { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
+ { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
+ { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
+#else
+#define EXTRA_SERIAL_PORT_DEFNS
+#endif
+
+/* You can have up to four HUB6's in the system, but I've only
+ * included two cards here for a total of twelve ports.
+ */
+#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
+#define HUB6_SERIAL_PORT_DFNS \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
+ { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
+#else
+#define HUB6_SERIAL_PORT_DFNS
+#endif
+
+#ifdef CONFIG_MCA
+#define MCA_SERIAL_PORT_DFNS \
+ { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS }, \
+ { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS }, \
+ { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS }, \
+ { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS }, \
+ { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS }, \
+ { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
+#else
+#define MCA_SERIAL_PORT_DFNS
+#endif
+
+#ifndef CONFIG_PLAT_USRV
+#define SERIAL_PORT_DFNS \
+ STD_SERIAL_PORT_DEFNS \
+ EXTRA_SERIAL_PORT_DEFNS \
+ HUB6_SERIAL_PORT_DFNS \
+ MCA_SERIAL_PORT_DFNS
+
+#else /* CONFIG_PLAT_USRV */
+
+#define SERIAL_PORT_DFNS \
+ /* UART CLK PORT IRQ FLAGS */ \
+ { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
+ { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
+#endif /* CONFIG_PLAT_USRV */
+
+#endif /* _ASM_M32R_SERIAL_H */
--- /dev/null
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+#define PARAM ((unsigned char *)empty_zero_page)
+
+#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
+#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
+#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
+#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
+#define INITRD_START (*(unsigned long *) (PARAM+0x010))
+#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
+
+#define M32R_CPUCLK (*(unsigned long *) (PARAM+0x018))
+#define M32R_BUSCLK (*(unsigned long *) (PARAM+0x01c))
+#define M32R_TIMER_DIVIDE (*(unsigned long *) (PARAM+0x020))
+
+#define COMMAND_LINE ((char *) (PARAM+0x100))
+
+#define SCREEN_INFO (*(struct screen_info *) (PARAM+0x200))
+
+#define COMMAND_LINE_SIZE (512)
+
+#define RAMDISK_IMAGE_START_MASK (0x07FF)
+#define RAMDISK_PROMPT_FLAG (0x8000)
+#define RAMDISK_LOAD_FLAG (0x4000)
+
+#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
+#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
+#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
+
+extern unsigned long memory_start;
+extern unsigned long memory_end;
+
--- /dev/null
+#ifndef _ASM_M32R_SHMBUF_H
+#define _ASM_M32R_SHMBUF_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+/*
+ * The shmid64_ds structure for M32R architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+ struct ipc64_perm shm_perm; /* operation perms */
+ size_t shm_segsz; /* size of segment (bytes) */
+ __kernel_time_t shm_atime; /* last attach time */
+ unsigned long __unused1;
+ __kernel_time_t shm_dtime; /* last detach time */
+ unsigned long __unused2;
+ __kernel_time_t shm_ctime; /* last change time */
+ unsigned long __unused3;
+ __kernel_pid_t shm_cpid; /* pid of creator */
+ __kernel_pid_t shm_lpid; /* pid of last operator */
+ unsigned long shm_nattch; /* no. of current attaches */
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+struct shminfo64 {
+ unsigned long shmmax;
+ unsigned long shmmin;
+ unsigned long shmmni;
+ unsigned long shmseg;
+ unsigned long shmall;
+ unsigned long __unused1;
+ unsigned long __unused2;
+ unsigned long __unused3;
+ unsigned long __unused4;
+};
+
+#endif /* _ASM_M32R_SHMBUF_H */
--- /dev/null
+#ifndef _ASM_M32R_SHMPARAM_H
+#define _ASM_M32R_SHMPARAM_H
+
+/* $Id$ */
+
+#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
+
+#endif /* _ASM_M32R_SHMPARAM_H */
--- /dev/null
+#ifndef _ASM_M32R_SIGCONTEXT_H
+#define _ASM_M32R_SIGCONTEXT_H
+
+/* $Id$ */
+
+#include <linux/config.h>
+
+struct sigcontext {
+ /* CPU registers */
+ /* Saved main processor registers. */
+ unsigned long sc_r4;
+ unsigned long sc_r5;
+ unsigned long sc_r6;
+ struct pt_regs *sc_pt_regs;
+ unsigned long sc_r0;
+ unsigned long sc_r1;
+ unsigned long sc_r2;
+ unsigned long sc_r3;
+ unsigned long sc_r7;
+ unsigned long sc_r8;
+ unsigned long sc_r9;
+ unsigned long sc_r10;
+ unsigned long sc_r11;
+ unsigned long sc_r12;
+
+ /* Saved main processor status and miscellaneous context registers. */
+#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
+ unsigned long sc_acc0h;
+ unsigned long sc_acc0l;
+ unsigned long sc_acc1h;
+ unsigned long sc_acc1l;
+#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
+ unsigned long sc_acch;
+ unsigned long sc_accl;
+#else
+#error unknown isa configuration
+#endif
+ unsigned long sc_psw;
+ unsigned long sc_bpc; /* saved PC for TRAP syscalls */
+ unsigned long sc_bbpsw;
+ unsigned long sc_bbpc;
+ unsigned long sc_spu; /* saved user stack */
+ unsigned long sc_fp;
+ unsigned long sc_lr; /* saved PC for JL syscalls */
+ unsigned long sc_spi; /* saved kernel stack */
+
+ unsigned long oldmask;
+};
+
+#endif /* _ASM_M32R_SIGCONTEXT_H */
--- /dev/null
+#ifndef _M32R_SIGINFO_H
+#define _M32R_SIGINFO_H
+
+/* $Id$ */
+
+#include <asm-generic/siginfo.h>
+
+#endif /* _M32R_SIGINFO_H */
--- /dev/null
+#ifndef _ASM_M32R_SIGNAL_H
+#define _ASM_M32R_SIGNAL_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+#include <linux/types.h>
+#include <linux/linkage.h>
+#include <linux/time.h>
+#include <linux/compiler.h>
+
+/* Avoid too many header ordering problems. */
+struct siginfo;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+ is taken to make libc match. */
+
+#define _NSIG 64
+#define _NSIG_BPW 32
+#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t; /* at least 32 bits */
+
+typedef struct {
+ unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers. */
+
+#define NSIG 32
+typedef unsigned long sigset_t;
+
+#endif /* __KERNEL__ */
+
+#define SIGHUP 1
+#define SIGINT 2
+#define SIGQUIT 3
+#define SIGILL 4
+#define SIGTRAP 5
+#define SIGABRT 6
+#define SIGIOT 6
+#define SIGBUS 7
+#define SIGFPE 8
+#define SIGKILL 9
+#define SIGUSR1 10
+#define SIGSEGV 11
+#define SIGUSR2 12
+#define SIGPIPE 13
+#define SIGALRM 14
+#define SIGTERM 15
+#define SIGSTKFLT 16
+#define SIGCHLD 17
+#define SIGCONT 18
+#define SIGSTOP 19
+#define SIGTSTP 20
+#define SIGTTIN 21
+#define SIGTTOU 22
+#define SIGURG 23
+#define SIGXCPU 24
+#define SIGXFSZ 25
+#define SIGVTALRM 26
+#define SIGPROF 27
+#define SIGWINCH 28
+#define SIGIO 29
+#define SIGPOLL SIGIO
+/*
+#define SIGLOST 29
+*/
+#define SIGPWR 30
+#define SIGSYS 31
+#define SIGUNUSED 31
+
+/* These should not be considered constants from userland. */
+#define SIGRTMIN 32
+#define SIGRTMAX _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP 0x00000001u
+#define SA_NOCLDWAIT 0x00000002u
+#define SA_SIGINFO 0x00000004u
+#define SA_ONSTACK 0x08000000u
+#define SA_RESTART 0x10000000u
+#define SA_NODEFER 0x40000000u
+#define SA_RESETHAND 0x80000000u
+
+#define SA_NOMASK SA_NODEFER
+#define SA_ONESHOT SA_RESETHAND
+#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */
+
+#define SA_RESTORER 0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK 1
+#define SS_DISABLE 2
+
+#define MINSIGSTKSZ 2048
+#define SIGSTKSZ 8192
+
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE SA_ONESHOT
+#define SA_SAMPLE_RANDOM SA_RESTART
+#define SA_SHIRQ 0x04000000
+#endif
+
+#define SIG_BLOCK 0 /* for blocking signals */
+#define SIG_UNBLOCK 1 /* for unblocking signals */
+#define SIG_SETMASK 2 /* for setting the signal mask */
+
+/* Type of a signal handler. */
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+
+typedef void __restorefn_t(void);
+typedef __restorefn_t __user *__sigrestore_t;
+
+#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
+
+#ifdef __KERNEL__
+struct old_sigaction {
+ __sighandler_t sa_handler;
+ old_sigset_t sa_mask;
+ unsigned long sa_flags;
+ __sigrestore_t sa_restorer;
+};
+
+struct sigaction {
+ __sighandler_t sa_handler;
+ unsigned long sa_flags;
+ __sigrestore_t sa_restorer;
+ sigset_t sa_mask; /* mask last for extensibility */
+};
+
+struct k_sigaction {
+ struct sigaction sa;
+};
+#else
+/* Here we must cater to libcs that poke about in kernel headers. */
+
+struct sigaction {
+ union {
+ __sighandler_t _sa_handler;
+ void (*_sa_sigaction)(int, struct siginfo *, void *);
+ } _u;
+ sigset_t sa_mask;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void);
+};
+
+#define sa_handler _u._sa_handler
+#define sa_sigaction _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+ void __user *ss_sp;
+ int ss_flags;
+ size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+#undef __HAVE_ARCH_SIG_BITOPS
+
+struct pt_regs;
+extern int FASTCALL(do_signal(struct pt_regs *regs, sigset_t *oldset));
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_SIGNAL_H */
--- /dev/null
+#ifndef _ASM_M32R_SMP_H
+#define _ASM_M32R_SMP_H
+
+/* $Id$ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SMP
+#ifndef __ASSEMBLY__
+
+#include <linux/cpumask.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <asm/m32r.h>
+
+#define PHYSID_ARRAY_SIZE 1
+
+struct physid_mask
+{
+ unsigned long mask[PHYSID_ARRAY_SIZE];
+};
+
+typedef struct physid_mask physid_mask_t;
+
+#define physid_set(physid, map) set_bit(physid, (map).mask)
+#define physid_clear(physid, map) clear_bit(physid, (map).mask)
+#define physid_isset(physid, map) test_bit(physid, (map).mask)
+#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
+
+#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
+#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
+#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
+#define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS)
+#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
+#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
+#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
+#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
+#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
+#define physids_coerce(map) ((map).mask[0])
+
+#define physids_promote(physids) \
+ ({ \
+ physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
+ __physid_mask.mask[0] = physids; \
+ __physid_mask; \
+ })
+
+#define physid_mask_of_physid(physid) \
+ ({ \
+ physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
+ physid_set(physid, __physid_mask); \
+ __physid_mask; \
+ })
+
+#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
+#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
+
+extern physid_mask_t phys_cpu_present_map;
+
+/*
+ * Some lowlevel functions might want to know about
+ * the real CPU ID <-> CPU # mapping.
+ */
+extern volatile int physid_2_cpu[NR_CPUS];
+extern volatile int cpu_2_physid[NR_CPUS];
+#define physid_to_cpu(physid) physid_2_cpu[physid]
+#define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id]
+
+#define smp_processor_id() (current_thread_info()->cpu)
+
+extern cpumask_t cpu_callout_map;
+#define cpu_possible_map cpu_callout_map
+
+static __inline__ int hard_smp_processor_id(void)
+{
+ return (int)*(volatile long *)M32R_CPUID_PORTL;
+}
+
+static __inline__ int cpu_logical_map(int cpu)
+{
+ return cpu;
+}
+
+static __inline__ int cpu_number_map(int cpu)
+{
+ return cpu;
+}
+
+static __inline__ unsigned int num_booting_cpus(void)
+{
+ return cpus_weight(cpu_callout_map);
+}
+
+extern void smp_send_timer(void);
+extern void calibrate_delay(void);
+extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
+
+#endif /* not __ASSEMBLY__ */
+
+#define NO_PROC_ID (0xff) /* No processor magic marker */
+
+#define PROC_CHANGE_PENALTY (15) /* Schedule penalty */
+
+/*
+ * M32R-mp IPI
+ */
+#define RESCHEDULE_IPI (M32R_IRQ_IPI0-M32R_IRQ_IPI0)
+#define INVALIDATE_TLB_IPI (M32R_IRQ_IPI1-M32R_IRQ_IPI0)
+#define CALL_FUNCTION_IPI (M32R_IRQ_IPI2-M32R_IRQ_IPI0)
+#define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
+#define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
+#define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
+
+#define IPI_SHIFT (0)
+#define NR_IPIS (8)
+
+#endif /* CONFIG_SMP */
+
+#endif /* _ASM_M32R_SMP_H */
--- /dev/null
+#ifndef _ASM_M32R_SOCKET_H
+#define _ASM_M32R_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockoptions(2) */
+#define SOL_SOCKET 1
+
+#define SO_DEBUG 1
+#define SO_REUSEADDR 2
+#define SO_TYPE 3
+#define SO_ERROR 4
+#define SO_DONTROUTE 5
+#define SO_BROADCAST 6
+#define SO_SNDBUF 7
+#define SO_RCVBUF 8
+#define SO_KEEPALIVE 9
+#define SO_OOBINLINE 10
+#define SO_NO_CHECK 11
+#define SO_PRIORITY 12
+#define SO_LINGER 13
+#define SO_BSDCOMPAT 14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED 16
+#define SO_PEERCRED 17
+#define SO_RCVLOWAT 18
+#define SO_SNDLOWAT 19
+#define SO_RCVTIMEO 20
+#define SO_SNDTIMEO 21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION 22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
+#define SO_SECURITY_ENCRYPTION_NETWORK 24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER 26
+#define SO_DETACH_FILTER 27
+
+#define SO_PEERNAME 28
+#define SO_TIMESTAMP 29
+#define SCM_TIMESTAMP SO_TIMESTAMP
+
+#define SO_ACCEPTCONN 30
+
+#define SO_PEERSEC 31
+
+#endif /* _ASM_M32R_SOCKET_H */
--- /dev/null
+#ifndef _ASM_M32R_SOCKIOS_H
+#define _ASM_M32R_SOCKIOS_H
+
+/* $Id$ */
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN 0x8901
+#define SIOCSPGRP 0x8902
+#define FIOGETOWN 0x8903
+#define SIOCGPGRP 0x8904
+#define SIOCATMARK 0x8905
+#define SIOCGSTAMP 0x8906 /* Get stamp */
+
+#endif /* _ASM_M32R_SOCKIOS_H */
--- /dev/null
+#ifndef _ASM_M32R_SPINLOCK_H
+#define _ASM_M32R_SPINLOCK_H
+
+/*
+ * linux/include/asm-m32r/spinlock.h
+ *
+ * M32R version:
+ * Copyright (C) 2001, 2002 Hitoshi Yamamoto
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#include <linux/config.h> /* CONFIG_DEBUG_SPINLOCK, CONFIG_SMP */
+#include <linux/compiler.h>
+#include <asm/atomic.h>
+#include <asm/page.h>
+
+extern int printk(const char * fmt, ...)
+ __attribute__ ((format (printf, 1, 2)));
+
+#define RW_LOCK_BIAS 0x01000000
+#define RW_LOCK_BIAS_STR "0x01000000"
+
+/* It seems that people are forgetting to
+ * initialize their spinlocks properly, tsk tsk.
+ * Remember to turn this off in 2.4. -ben
+ */
+#if defined(CONFIG_DEBUG_SPINLOCK)
+#define SPINLOCK_DEBUG 1
+#else
+#define SPINLOCK_DEBUG 0
+#endif
+
+/*
+ * Your basic SMP spinlocks, allowing only a single CPU anywhere
+ */
+
+typedef struct {
+ volatile int lock;
+#if SPINLOCK_DEBUG
+ unsigned magic;
+#endif
+#ifdef CONFIG_PREEMPT
+ unsigned int break_lock;
+#endif
+} spinlock_t;
+
+#define SPINLOCK_MAGIC 0xdead4ead
+
+#if SPINLOCK_DEBUG
+#define SPINLOCK_MAGIC_INIT , SPINLOCK_MAGIC
+#else
+#define SPINLOCK_MAGIC_INIT /* */
+#endif
+
+#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 SPINLOCK_MAGIC_INIT }
+
+#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
+
+/*
+ * Simple spin lock operations. There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * We make no fairness assumptions. They have a cost.
+ */
+
+#define spin_is_locked(x) (*(volatile int *)(&(x)->lock) <= 0)
+#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x))
+#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
+
+/**
+ * _raw_spin_trylock - Try spin lock and return a result
+ * @lock: Pointer to the lock variable
+ *
+ * _raw_spin_trylock() tries to get the lock and returns a result.
+ * On the m32r, the result value is 1 (= Success) or 0 (= Failure).
+ */
+static inline int _raw_spin_trylock(spinlock_t *lock)
+{
+ int oldval;
+ unsigned long tmp1, tmp2;
+
+ /*
+ * lock->lock : =1 : unlock
+ * : <=0 : lock
+ * {
+ * oldval = lock->lock; <--+ need atomic operation
+ * lock->lock = 0; <--+
+ * }
+ */
+ __asm__ __volatile__ (
+ "# spin_trylock \n\t"
+ "ldi %1, #0; \n\t"
+ "mvfc %2, psw; \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r6", "%3")
+ "lock %0, @%3; \n\t"
+ "unlock %1, @%3; \n\t"
+ "mvtc %2, psw; \n\t"
+ : "=&r" (oldval), "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (&lock->lock)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+
+ return (oldval > 0);
+}
+
+static inline void _raw_spin_lock(spinlock_t *lock)
+{
+ unsigned long tmp0, tmp1;
+
+#if SPINLOCK_DEBUG
+ __label__ here;
+here:
+ if (lock->magic != SPINLOCK_MAGIC) {
+ printk("eip: %p\n", &&here);
+ BUG();
+ }
+#endif
+ /*
+ * lock->lock : =1 : unlock
+ * : <=0 : lock
+ *
+ * for ( ; ; ) {
+ * lock->lock -= 1; <-- need atomic operation
+ * if (lock->lock == 0) break;
+ * for ( ; lock->lock <= 0 ; );
+ * }
+ */
+ __asm__ __volatile__ (
+ "# spin_lock \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "mvfc %1, psw; \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r6", "%2")
+ "lock %0, @%2; \n\t"
+ "addi %0, #-1; \n\t"
+ "unlock %0, @%2; \n\t"
+ "mvtc %1, psw; \n\t"
+ "bltz %0, 2f; \n\t"
+ LOCK_SECTION_START(".balign 4 \n\t")
+ ".fillinsn \n"
+ "2: \n\t"
+ "ld %0, @%2; \n\t"
+ "bgtz %0, 1b; \n\t"
+ "bra 2b; \n\t"
+ LOCK_SECTION_END
+ : "=&r" (tmp0), "=&r" (tmp1)
+ : "r" (&lock->lock)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+}
+
+static inline void _raw_spin_unlock(spinlock_t *lock)
+{
+#if SPINLOCK_DEBUG
+ BUG_ON(lock->magic != SPINLOCK_MAGIC);
+ BUG_ON(!spin_is_locked(lock));
+#endif
+ mb();
+ lock->lock = 1;
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+typedef struct {
+ volatile int lock;
+#if SPINLOCK_DEBUG
+ unsigned magic;
+#endif
+#ifdef CONFIG_PREEMPT
+ unsigned int break_lock;
+#endif
+} rwlock_t;
+
+#define RWLOCK_MAGIC 0xdeaf1eed
+
+#if SPINLOCK_DEBUG
+#define RWLOCK_MAGIC_INIT , RWLOCK_MAGIC
+#else
+#define RWLOCK_MAGIC_INIT /* */
+#endif
+
+#define RW_LOCK_UNLOCKED (rwlock_t) { RW_LOCK_BIAS RWLOCK_MAGIC_INIT }
+
+#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
+
+#define rwlock_is_locked(x) ((x)->lock != RW_LOCK_BIAS)
+
+/*
+ * On x86, we implement read-write locks as a 32-bit counter
+ * with the high bit (sign) being the "contended" bit.
+ *
+ * The inline assembly is non-obvious. Think about it.
+ *
+ * Changed to use the same technique as rw semaphores. See
+ * semaphore.h for details. -ben
+ */
+/* the spinlock helpers are in arch/i386/kernel/semaphore.c */
+
+static inline void _raw_read_lock(rwlock_t *rw)
+{
+ unsigned long tmp0, tmp1;
+
+#if SPINLOCK_DEBUG
+ BUG_ON(rw->magic != RWLOCK_MAGIC);
+#endif
+ /*
+ * rw->lock : >0 : unlock
+ * : <=0 : lock
+ *
+ * for ( ; ; ) {
+ * rw->lock -= 1; <-- need atomic operation
+ * if (rw->lock >= 0) break;
+ * rw->lock += 1; <-- need atomic operation
+ * for ( ; rw->lock <= 0 ; );
+ * }
+ */
+ __asm__ __volatile__ (
+ "# read_lock \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "mvfc %1, psw; \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r6", "%2")
+ "lock %0, @%2; \n\t"
+ "addi %0, #-1; \n\t"
+ "unlock %0, @%2; \n\t"
+ "mvtc %1, psw; \n\t"
+ "bltz %0, 2f; \n\t"
+ LOCK_SECTION_START(".balign 4 \n\t")
+ ".fillinsn \n"
+ "2: \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r6", "%2")
+ "lock %0, @%2; \n\t"
+ "addi %0, #1; \n\t"
+ "unlock %0, @%2; \n\t"
+ "mvtc %1, psw; \n\t"
+ ".fillinsn \n"
+ "3: \n\t"
+ "ld %0, @%2; \n\t"
+ "bgtz %0, 1b; \n\t"
+ "bra 3b; \n\t"
+ LOCK_SECTION_END
+ : "=&r" (tmp0), "=&r" (tmp1)
+ : "r" (&rw->lock)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+}
+
+static inline void _raw_write_lock(rwlock_t *rw)
+{
+ unsigned long tmp0, tmp1, tmp2;
+
+#if SPINLOCK_DEBUG
+ BUG_ON(rw->magic != RWLOCK_MAGIC);
+#endif
+ /*
+ * rw->lock : =RW_LOCK_BIAS_STR : unlock
+ * : !=RW_LOCK_BIAS_STR : lock
+ *
+ * for ( ; ; ) {
+ * rw->lock -= RW_LOCK_BIAS_STR; <-- need atomic operation
+ * if (rw->lock == 0) break;
+ * rw->lock += RW_LOCK_BIAS_STR; <-- need atomic operation
+ * for ( ; rw->lock != RW_LOCK_BIAS_STR ; ) ;
+ * }
+ */
+ __asm__ __volatile__ (
+ "# write_lock \n\t"
+ "seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
+ "or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "mvfc %2, psw; \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r7", "%3")
+ "lock %0, @%3; \n\t"
+ "sub %0, %1; \n\t"
+ "unlock %0, @%3; \n\t"
+ "mvtc %2, psw; \n\t"
+ "bnez %0, 2f; \n\t"
+ LOCK_SECTION_START(".balign 4 \n\t")
+ ".fillinsn \n"
+ "2: \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r7", "%3")
+ "lock %0, @%3; \n\t"
+ "add %0, %1; \n\t"
+ "unlock %0, @%3; \n\t"
+ "mvtc %2, psw; \n\t"
+ ".fillinsn \n"
+ "3: \n\t"
+ "ld %0, @%3; \n\t"
+ "beq %0, %1, 1b; \n\t"
+ "bra 3b; \n\t"
+ LOCK_SECTION_END
+ : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (&rw->lock)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r7"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+}
+
+static inline void _raw_read_unlock(rwlock_t *rw)
+{
+ unsigned long tmp0, tmp1;
+
+ __asm__ __volatile__ (
+ "# read_unlock \n\t"
+ "mvfc %1, psw; \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r6", "%2")
+ "lock %0, @%2; \n\t"
+ "addi %0, #1; \n\t"
+ "unlock %0, @%2; \n\t"
+ "mvtc %1, psw; \n\t"
+ : "=&r" (tmp0), "=&r" (tmp1)
+ : "r" (&rw->lock)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r6"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+}
+
+static inline void _raw_write_unlock(rwlock_t *rw)
+{
+ unsigned long tmp0, tmp1, tmp2;
+
+ __asm__ __volatile__ (
+ "# write_unlock \n\t"
+ "seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
+ "or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
+ "mvfc %2, psw; \n\t"
+ "clrpsw #0x40 -> nop; \n\t"
+ DCACHE_CLEAR("%0", "r7", "%3")
+ "lock %0, @%3; \n\t"
+ "add %0, %1; \n\t"
+ "unlock %0, @%3; \n\t"
+ "mvtc %2, psw; \n\t"
+ : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (&rw->lock)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r7"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+}
+
+#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
+
+static inline int _raw_write_trylock(rwlock_t *lock)
+{
+ atomic_t *count = (atomic_t *)lock;
+ if (atomic_sub_and_test(RW_LOCK_BIAS, count))
+ return 1;
+ atomic_add(RW_LOCK_BIAS, count);
+ return 0;
+}
+
+#endif /* _ASM_M32R_SPINLOCK_H */
--- /dev/null
+#ifndef _ASM_M32R_STAT_H
+#define _ASM_M32R_STAT_H
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+#include <asm/byteorder.h>
+
+struct __old_kernel_stat {
+ unsigned short st_dev;
+ unsigned short st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned short st_rdev;
+ unsigned long st_size;
+ unsigned long st_atime;
+ unsigned long st_mtime;
+ unsigned long st_ctime;
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct stat {
+ unsigned short st_dev;
+ unsigned short __pad1;
+ unsigned long st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned short st_rdev;
+ unsigned short __pad2;
+ unsigned long st_size;
+ unsigned long st_blksize;
+ unsigned long st_blocks;
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+ unsigned long st_mtime;
+ unsigned long st_mtime_nsec;
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+ unsigned long long st_dev;
+ unsigned char __pad0[4];
+#define STAT64_HAS_BROKEN_ST_INO
+ unsigned long __st_ino;
+
+ unsigned int st_mode;
+ unsigned int st_nlink;
+
+ unsigned long st_uid;
+ unsigned long st_gid;
+
+ unsigned long long st_rdev;
+ unsigned char __pad3[4];
+
+ long long st_size;
+ unsigned long st_blksize;
+
+#if defined(__BIG_ENDIAN)
+ unsigned long __pad4; /* future possible st_blocks high bits */
+ unsigned long st_blocks; /* Number 512-byte blocks allocated. */
+#elif defined(__LITTLE_ENDIAN)
+ unsigned long st_blocks; /* Number 512-byte blocks allocated. */
+ unsigned long __pad4; /* future possible st_blocks high bits */
+#else
+#error no endian defined
+#endif
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+
+ unsigned long st_mtime;
+ unsigned long st_mtime_nsec;
+
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+
+ unsigned long long st_ino;
+};
+
+#endif /* _ASM_M32R_STAT_H */
--- /dev/null
+#ifndef _ASM_M32R_STATFS_H
+#define _ASM_M32R_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif /* _ASM_M32R_STATFS_H */
--- /dev/null
+#ifndef _ASM_M32R_STRING_H
+#define _ASM_M32R_STRING_H
+
+/* $Id$ */
+
+#define __HAVE_ARCH_STRLEN
+extern size_t strlen(const char * s);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#endif /* _ASM_M32R_STRING_H */
--- /dev/null
+#ifndef _ASM_M32R_SYSCALL_H
+#define _ASM_M32R_SYSCALL_H
+
+/* $Id$ */
+
+/* Definitions for the system call vector. */
+#define SYSCALL_VECTOR "2"
+#define SYSCALL_VECTOR_ADDRESS "0xa0"
+
+#endif /* _ASM_M32R_SYSCALL_H */
+
--- /dev/null
+#ifndef _ASM_M32R_SYSTEM_H
+#define _ASM_M32R_SYSTEM_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 by Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
+ */
+
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+
+/*
+ * switch_to(prev, next) should switch from task `prev' to `next'
+ * `prev' will never be the same as `next'.
+ *
+ * `next' and `prev' should be struct task_struct, but it isn't always defined
+ */
+
+#ifndef CONFIG_SMP
+#define prepare_to_switch() do { } while(0)
+#endif /* not CONFIG_SMP */
+
+#define switch_to(prev, next, last) do { \
+ register unsigned long arg0 __asm__ ("r0") = (unsigned long)prev; \
+ register unsigned long arg1 __asm__ ("r1") = (unsigned long)next; \
+ register unsigned long *oldsp __asm__ ("r2") = &(prev->thread.sp); \
+ register unsigned long *newsp __asm__ ("r3") = &(next->thread.sp); \
+ register unsigned long *oldlr __asm__ ("r4") = &(prev->thread.lr); \
+ register unsigned long *newlr __asm__ ("r5") = &(next->thread.lr); \
+ register struct task_struct *__last __asm__ ("r6"); \
+ __asm__ __volatile__ ( \
+ "st r8, @-r15 \n\t" \
+ "st r9, @-r15 \n\t" \
+ "st r10, @-r15 \n\t" \
+ "st r11, @-r15 \n\t" \
+ "st r12, @-r15 \n\t" \
+ "st r13, @-r15 \n\t" \
+ "st r14, @-r15 \n\t" \
+ "seth r14, #high(1f) \n\t" \
+ "or3 r14, r14, #low(1f) \n\t" \
+ "st r14, @r4 ; store old LR \n\t" \
+ "st r15, @r2 ; store old SP \n\t" \
+ "ld r15, @r3 ; load new SP \n\t" \
+ "st r0, @-r15 ; store 'prev' onto new stack \n\t" \
+ "ld r14, @r5 ; load new LR \n\t" \
+ "jmp r14 \n\t" \
+ ".fillinsn \n " \
+ "1: \n\t" \
+ "ld r6, @r15+ ; load 'prev' from new stack \n\t" \
+ "ld r14, @r15+ \n\t" \
+ "ld r13, @r15+ \n\t" \
+ "ld r12, @r15+ \n\t" \
+ "ld r11, @r15+ \n\t" \
+ "ld r10, @r15+ \n\t" \
+ "ld r9, @r15+ \n\t" \
+ "ld r8, @r15+ \n\t" \
+ : "=&r" (__last) \
+ : "r" (arg0), "r" (arg1), "r" (oldsp), "r" (newsp), \
+ "r" (oldlr), "r" (newlr) \
+ : "memory" \
+ ); \
+ last = __last; \
+} while(0)
+
+/* Interrupt Control */
+#if !defined(CONFIG_CHIP_M32102)
+#define local_irq_enable() \
+ __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
+#define local_irq_disable() \
+ __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
+#else /* CONFIG_CHIP_M32102 */
+static __inline__ void local_irq_enable(void)
+{
+ unsigned long tmpreg;
+ __asm__ __volatile__(
+ "mvfc %0, psw; \n\t"
+ "or3 %0, %0, #0x0040; \n\t"
+ "mvtc %0, psw; \n\t"
+ : "=&r" (tmpreg) : : "cbit", "memory");
+}
+
+static __inline__ void local_irq_disable(void)
+{
+ unsigned long tmpreg0, tmpreg1;
+ __asm__ __volatile__(
+ "ld24 %0, #0 ; Use 32-bit insn. \n\t"
+ "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
+ "mvtc %0, psw \n\t"
+ "and3 %0, %1, #0xffbf \n\t"
+ "mvtc %0, psw \n\t"
+ : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
+}
+#endif /* CONFIG_CHIP_M32102 */
+
+#define local_save_flags(x) \
+ __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
+
+#define local_irq_restore(x) \
+ __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
+ : "r" (x) : "cbit", "memory")
+
+#if !defined(CONFIG_CHIP_M32102)
+#define local_irq_save(x) \
+ __asm__ __volatile__( \
+ "mvfc %0, psw; \n\t" \
+ "clrpsw #0x40 -> nop; \n\t" \
+ : "=r" (x) : /* no input */ : "memory")
+#else /* CONFIG_CHIP_M32102 */
+#define local_irq_save(x) \
+ ({ \
+ unsigned long tmpreg; \
+ __asm__ __volatile__( \
+ "ld24 %1, #0 \n\t" \
+ "mvfc %0, psw \n\t" \
+ "mvtc %1, psw \n\t" \
+ "and3 %1, %0, #0xffbf \n\t" \
+ "mvtc %1, psw \n\t" \
+ : "=r" (x), "=&r" (tmpreg) \
+ : : "cbit", "memory"); \
+ })
+#endif /* CONFIG_CHIP_M32102 */
+
+#define irqs_disabled() \
+ ({ \
+ unsigned long flags; \
+ local_save_flags(flags); \
+ !(flags & 0x40); \
+ })
+
+#endif /* __KERNEL__ */
+
+#define nop() __asm__ __volatile__ ("nop" : : )
+
+#define xchg(ptr,x) \
+ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+#define tas(ptr) (xchg((ptr),1))
+
+#ifdef CONFIG_SMP
+extern void __xchg_called_with_bad_pointer(void);
+#endif
+
+#ifdef CONFIG_CHIP_M32700_TS1
+#define DCACHE_CLEAR(reg0, reg1, addr) \
+ "seth "reg1", #high(dcache_dummy); \n\t" \
+ "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
+ "lock "reg0", @"reg1"; \n\t" \
+ "add3 "reg0", "addr", #0x1000; \n\t" \
+ "ld "reg0", @"reg0"; \n\t" \
+ "add3 "reg0", "addr", #0x2000; \n\t" \
+ "ld "reg0", @"reg0"; \n\t" \
+ "unlock "reg0", @"reg1"; \n\t"
+ /* FIXME: This workaround code cannot handle kenrel modules
+ * correctly under SMP environment.
+ */
+#else /* CONFIG_CHIP_M32700_TS1 */
+#define DCACHE_CLEAR(reg0, reg1, addr)
+#endif /* CONFIG_CHIP_M32700_TS1 */
+
+static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr,
+ int size)
+{
+ unsigned long flags;
+ unsigned long tmp = 0;
+
+ local_irq_save(flags);
+
+ switch (size) {
+#ifndef CONFIG_SMP
+ case 1:
+ __asm__ __volatile__ (
+ "ldb %0, @%2 \n\t"
+ "stb %1, @%2 \n\t"
+ : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__ (
+ "ldh %0, @%2 \n\t"
+ "sth %1, @%2 \n\t"
+ : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__ (
+ "ld %0, @%2 \n\t"
+ "st %1, @%2 \n\t"
+ : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
+ break;
+#else /* CONFIG_SMP */
+ case 4:
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "r4", "%2")
+ "lock %0, @%2; \n\t"
+ "unlock %1, @%2; \n\t"
+ : "=&r" (tmp) : "r" (x), "r" (ptr)
+ : "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );
+ break;
+ default:
+ __xchg_called_with_bad_pointer();
+#endif /* CONFIG_SMP */
+ }
+
+ local_irq_restore(flags);
+
+ return (tmp);
+}
+
+/*
+ * Memory barrier.
+ *
+ * mb() prevents loads and stores being reordered across this point.
+ * rmb() prevents loads being reordered across this point.
+ * wmb() prevents stores being reordered across this point.
+ */
+#if 0
+#define mb() __asm__ __volatile__ ("push r0; \n\t pop r0;" : : : "memory")
+#else
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+#define rmb() mb()
+#define wmb() mb()
+
+/**
+ * read_barrier_depends - Flush all pending reads that subsequents reads
+ * depend on.
+ *
+ * No data-dependent reads from memory-like regions are ever reordered
+ * over this barrier. All reads preceding this primitive are guaranteed
+ * to access memory (but not necessarily other CPUs' caches) before any
+ * reads following this primitive that depend on the data return by
+ * any of the preceding reads. This primitive is much lighter weight than
+ * rmb() on most CPUs, and is never heavier weight than is
+ * rmb().
+ *
+ * These ordering constraints are respected by both the local CPU
+ * and the compiler.
+ *
+ * Ordering is not guaranteed by anything other than these primitives,
+ * not even by data dependencies. See the documentation for
+ * memory_barrier() for examples and URLs to more information.
+ *
+ * For example, the following code would force ordering (the initial
+ * value of "a" is zero, "b" is one, and "p" is "&a"):
+ *
+ * <programlisting>
+ * CPU 0 CPU 1
+ *
+ * b = 2;
+ * memory_barrier();
+ * p = &b; q = p;
+ * read_barrier_depends();
+ * d = *q;
+ * </programlisting>
+ *
+ *
+ * because the read of "*q" depends on the read of "p" and these
+ * two reads are separated by a read_barrier_depends(). However,
+ * the following code, with the same initial values for "a" and "b":
+ *
+ * <programlisting>
+ * CPU 0 CPU 1
+ *
+ * a = 2;
+ * memory_barrier();
+ * b = 3; y = b;
+ * read_barrier_depends();
+ * x = a;
+ * </programlisting>
+ *
+ * does not enforce ordering, since there is no data dependency between
+ * the read of "a" and the read of "b". Therefore, on some CPUs, such
+ * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
+ * in cases like thiswhere there are no data dependencies.
+ **/
+
+#define read_barrier_depends() do { } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb() mb()
+#define smp_rmb() rmb()
+#define smp_wmb() wmb()
+#define smp_read_barrier_depends() read_barrier_depends()
+#else
+#define smp_mb() barrier()
+#define smp_rmb() barrier()
+#define smp_wmb() barrier()
+#define smp_read_barrier_depends() do { } while (0)
+#endif
+
+#define set_mb(var, value) do { xchg(&var, value); } while (0)
+#define set_wmb(var, value) do { var = value; wmb(); } while (0)
+
+#endif /* _ASM_M32R_SYSTEM_H */
+
--- /dev/null
+#ifndef _ASM_M32R_TERMBITS_H
+#define _ASM_M32R_TERMBITS_H
+
+/* $Id$ */
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+#define NCCS 19
+struct termios {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK 0000001
+#define BRKINT 0000002
+#define IGNPAR 0000004
+#define PARMRK 0000010
+#define INPCK 0000020
+#define ISTRIP 0000040
+#define INLCR 0000100
+#define IGNCR 0000200
+#define ICRNL 0000400
+#define IUCLC 0001000
+#define IXON 0002000
+#define IXANY 0004000
+#define IXOFF 0010000
+#define IMAXBEL 0020000
+#define IUTF8 0040000
+
+/* c_oflag bits */
+#define OPOST 0000001
+#define OLCUC 0000002
+#define ONLCR 0000004
+#define OCRNL 0000010
+#define ONOCR 0000020
+#define ONLRET 0000040
+#define OFILL 0000100
+#define OFDEL 0000200
+#define NLDLY 0000400
+#define NL0 0000000
+#define NL1 0000400
+#define CRDLY 0003000
+#define CR0 0000000
+#define CR1 0001000
+#define CR2 0002000
+#define CR3 0003000
+#define TABDLY 0014000
+#define TAB0 0000000
+#define TAB1 0004000
+#define TAB2 0010000
+#define TAB3 0014000
+#define XTABS 0014000
+#define BSDLY 0020000
+#define BS0 0000000
+#define BS1 0020000
+#define VTDLY 0040000
+#define VT0 0000000
+#define VT1 0040000
+#define FFDLY 0100000
+#define FF0 0000000
+#define FF1 0100000
+
+/* c_cflag bit meaning */
+#define CBAUD 0010017
+#define B0 0000000 /* hang up */
+#define B50 0000001
+#define B75 0000002
+#define B110 0000003
+#define B134 0000004
+#define B150 0000005
+#define B200 0000006
+#define B300 0000007
+#define B600 0000010
+#define B1200 0000011
+#define B1800 0000012
+#define B2400 0000013
+#define B4800 0000014
+#define B9600 0000015
+#define B19200 0000016
+#define B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE 0000060
+#define CS5 0000000
+#define CS6 0000020
+#define CS7 0000040
+#define CS8 0000060
+#define CSTOPB 0000100
+#define CREAD 0000200
+#define PARENB 0000400
+#define PARODD 0001000
+#define HUPCL 0002000
+#define CLOCAL 0004000
+#define CBAUDEX 0010000
+#define B57600 0010001
+#define B115200 0010002
+#define B230400 0010003
+#define B460800 0010004
+#define B500000 0010005
+#define B576000 0010006
+#define B921600 0010007
+#define B1000000 0010010
+#define B1152000 0010011
+#define B1500000 0010012
+#define B2000000 0010013
+#define B2500000 0010014
+#define B3000000 0010015
+#define B3500000 0010016
+#define B4000000 0010017
+#define CIBAUD 002003600000 /* input baud rate (not used) */
+#define CMSPAR 010000000000 /* mark or space (stick) parity */
+#define CRTSCTS 020000000000 /* flow control */
+
+/* c_lflag bits */
+#define ISIG 0000001
+#define ICANON 0000002
+#define XCASE 0000004
+#define ECHO 0000010
+#define ECHOE 0000020
+#define ECHOK 0000040
+#define ECHONL 0000100
+#define NOFLSH 0000200
+#define TOSTOP 0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE 0004000
+#define FLUSHO 0010000
+#define PENDIN 0040000
+#define IEXTEN 0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF 0
+#define TCOON 1
+#define TCIOFF 2
+#define TCION 3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH 0
+#define TCOFLUSH 1
+#define TCIOFLUSH 2
+
+/* tcsetattr uses these */
+#define TCSANOW 0
+#define TCSADRAIN 1
+#define TCSAFLUSH 2
+
+#endif /* _ASM_M32R_TERMBITS_H */
--- /dev/null
+#ifndef _M32R_TERMIOS_H
+#define _M32R_TERMIOS_H
+
+/* orig : i386 2.6.0-test5 */
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+ unsigned short ws_row;
+ unsigned short ws_col;
+ unsigned short ws_xpixel;
+ unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+ unsigned short c_iflag; /* input mode flags */
+ unsigned short c_oflag; /* output mode flags */
+ unsigned short c_cflag; /* control mode flags */
+ unsigned short c_lflag; /* local mode flags */
+ unsigned char c_line; /* line discipline */
+ unsigned char c_cc[NCC]; /* control characters */
+};
+
+/* modem lines */
+#define TIOCM_LE 0x001
+#define TIOCM_DTR 0x002
+#define TIOCM_RTS 0x004
+#define TIOCM_ST 0x008
+#define TIOCM_SR 0x010
+#define TIOCM_CTS 0x020
+#define TIOCM_CAR 0x040
+#define TIOCM_RNG 0x080
+#define TIOCM_DSR 0x100
+#define TIOCM_CD TIOCM_CAR
+#define TIOCM_RI TIOCM_RNG
+#define TIOCM_OUT1 0x2000
+#define TIOCM_OUT2 0x4000
+#define TIOCM_LOOP 0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+/* line disciplines */
+#define N_TTY 0
+#define N_SLIP 1
+#define N_MOUSE 2
+#define N_PPP 3
+#define N_STRIP 4
+#define N_AX25 5
+#define N_X25 6 /* X.25 async */
+#define N_6PACK 7
+#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */
+#define N_R3964 9 /* Reserved for Simatic R3964 module */
+#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */
+#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */
+#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */
+#define N_HDLC 13 /* synchronous HDLC */
+#define N_SYNC_PPP 14 /* synchronous PPP */
+#define N_HCI 15 /* Bluetooth HCI UART */
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+
+/* intr=^C quit=^\ erase=del kill=^U
+ eof=^D vtime=\0 vmin=\1 sxtc=\0
+ start=^Q stop=^S susp=^Z eol=\0
+ reprint=^R discard=^U werase=^W lnext=^V
+ eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+ unsigned short __tmp; \
+ get_user(__tmp,&(termio)->x); \
+ *(unsigned short *) &(termios)->x = __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+ copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+ put_user((termios)->c_iflag, &(termio)->c_iflag); \
+ put_user((termios)->c_oflag, &(termio)->c_oflag); \
+ put_user((termios)->c_cflag, &(termio)->c_cflag); \
+ put_user((termios)->c_lflag, &(termio)->c_lflag); \
+ put_user((termios)->c_line, &(termio)->c_line); \
+ copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif /* __KERNEL__ */
+
+#endif /* _M32R_TERMIOS_H */
--- /dev/null
+/* thread_info.h: i386 low-level thread information
+ *
+ * Copyright (C) 2002 David Howells (dhowells@redhat.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+#endif
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants must also be changed
+ */
+#ifndef __ASSEMBLY__
+
+struct thread_info {
+ struct task_struct *task; /* main task structure */
+ struct exec_domain *exec_domain; /* execution domain */
+ unsigned long flags; /* low level flags */
+ unsigned long status; /* thread-synchronous flags */
+ __u32 cpu; /* current CPU */
+ __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
+
+ mm_segment_t addr_limit; /* thread address space:
+ 0-0xBFFFFFFF for user-thead
+ 0-0xFFFFFFFF for kernel-thread
+ */
+ struct restart_block restart_block;
+
+ __u8 supervisor_stack[0];
+};
+
+#else /* !__ASSEMBLY__ */
+
+/* offsets into the thread_info struct for assembly code access */
+#define TI_TASK 0x00000000
+#define TI_EXEC_DOMAIN 0x00000004
+#define TI_FLAGS 0x00000008
+#define TI_STATUS 0x0000000C
+#define TI_CPU 0x00000010
+#define TI_PRE_COUNT 0x00000014
+#define TI_ADDR_LIMIT 0x00000018
+#define TI_RESTART_BLOCK 0x000001C
+
+#endif
+
+#define PREEMPT_ACTIVE 0x4000000
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#ifndef __ASSEMBLY__
+
+#define INIT_THREAD_INFO(tsk) \
+{ \
+ .task = &tsk, \
+ .exec_domain = &default_exec_domain, \
+ .flags = 0, \
+ .cpu = 0, \
+ .preempt_count = 1, \
+ .addr_limit = KERNEL_DS, \
+ .restart_block = { \
+ .fn = do_no_restart_syscall, \
+ }, \
+}
+
+#define init_thread_info (init_thread_union.thread_info)
+#define init_stack (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+ struct thread_info *ti;
+
+ __asm__ __volatile__ (
+ "ldi %0, #0xffffe000; \n\t"
+ "and %0, sp; \n\t"
+ : "=r" (ti)
+ );
+
+ return ti;
+}
+
+/* thread information allocation */
+#define THREAD_SIZE (2*PAGE_SIZE)
+#define alloc_thread_info(task) \
+ ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
+#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
+#define get_thread_info(ti) get_task_struct((ti)->task)
+#define put_thread_info(ti) put_task_struct((ti)->task)
+
+#else /* !__ASSEMBLY__ */
+
+/* how to get the thread information struct from ASM */
+#define GET_THREAD_INFO(reg) GET_THREAD_INFO reg
+ .macro GET_THREAD_INFO reg
+ ldi \reg, #0xffffe000
+ and \reg, sp
+ .endm
+
+#endif
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
+#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
+#define TIF_SIGPENDING 2 /* signal pending */
+#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
+#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
+#define TIF_IRET 5 /* return with iret */
+#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
+
+#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
+#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
+#define _TIF_IRET (1<<TIF_IRET)
+#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
+#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
+
+/*
+ * Thread-synchronous status.
+ *
+ * This is different from the flags in that nobody else
+ * ever touches our thread-synchronous status, so we don't
+ * have to worry about atomic accesses.
+ */
+#define TS_USEDFPU 0x0001 /* FPU was used by this task this quantum (SMP) */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
--- /dev/null
+#ifndef _ASM_M32R_TIMEX_H
+#define _ASM_M32R_TIMEX_H
+
+/* $Id$ */
+
+/*
+ * linux/include/asm-m32r/timex.h
+ *
+ * m32r architecture timex specifications
+ */
+
+#include <linux/config.h>
+
+#define CLOCK_TICK_RATE (CONFIG_BUS_CLOCK / CONFIG_TIMER_DIVIDE)
+#define CLOCK_TICK_FACTOR 20 /* Factor of both 1000000 and CLOCK_TICK_RATE */
+#define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
+ (1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
+ << (SHIFT_SCALE-SHIFT_HZ)) / HZ)
+
+#ifdef __KERNEL__
+/*
+ * Standard way to access the cycle counter.
+ * Currently only used on SMP.
+ */
+
+typedef unsigned long long cycles_t;
+
+extern cycles_t cacheflush_time;
+
+static __inline__ cycles_t get_cycles (void)
+{
+ return 0;
+}
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_TIMEX_H */
--- /dev/null
+#ifndef _M32R_TLB_H
+#define _M32R_TLB_H
+
+/*
+ * x86 doesn't need any special per-pte or
+ * per-vma handling..
+ */
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it
+ * fills up.
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* _M32R_TLB_H */
--- /dev/null
+#ifndef _ASM_M32R_TLBFLUSH_H
+#define _ASM_M32R_TLBFLUSH_H
+
+#include <linux/config.h>
+#include <asm/m32r.h>
+
+/*
+ * TLB flushing:
+ *
+ * - flush_tlb() flushes the current mm struct TLBs
+ * - flush_tlb_all() flushes all processes TLBs
+ * - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ * - flush_tlb_page(vma, vmaddr) flushes one page
+ * - flush_tlb_range(vma, start, end) flushes a range of pages
+ * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
+ */
+
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_mm(struct mm_struct *);
+extern void local_flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void local_flush_tlb_range(struct vm_area_struct *, unsigned long,
+ unsigned long);
+
+#ifndef CONFIG_SMP
+#ifdef CONFIG_MMU
+#define flush_tlb_all() local_flush_tlb_all()
+#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
+#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
+#define flush_tlb_range(vma, start, end) \
+ local_flush_tlb_range(vma, start, end)
+#define flush_tlb_kernel_range(start, end) local_flush_tlb_all()
+#else /* CONFIG_MMU */
+#define flush_tlb_all() do { } while (0)
+#define flush_tlb_mm(mm) do { } while (0)
+#define flush_tlb_page(vma, vmaddr) do { } while (0)
+#define flush_tlb_range(vma, start, end) do { } while (0)
+#endif /* CONFIG_MMU */
+#else /* CONFIG_SMP */
+extern void smp_flush_tlb_all(void);
+extern void smp_flush_tlb_mm(struct mm_struct *);
+extern void smp_flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void smp_flush_tlb_range(struct vm_area_struct *, unsigned long,
+ unsigned long);
+
+#define flush_tlb_all() smp_flush_tlb_all()
+#define flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
+#define flush_tlb_page(vma, page) smp_flush_tlb_page(vma, page)
+#define flush_tlb_range(vma, start, end) \
+ smp_flush_tlb_range(vma, start, end)
+#define flush_tlb_kernel_range(start, end) smp_flush_tlb_all()
+#endif /* CONFIG_SMP */
+
+static __inline__ void __flush_tlb_page(unsigned long page)
+{
+ unsigned int tmpreg0, tmpreg1, tmpreg2;
+
+ __asm__ __volatile__ (
+ "seth %0, #high(%4) \n\t"
+ "st %3, @(%5, %0) \n\t"
+ "ldi %1, #1 \n\t"
+ "st %1, @(%6, %0) \n\t"
+ "add3 %1, %0, %7 \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "ld %2, @(%6, %0) \n\t"
+ "bnez %2, 1b \n\t"
+ "ld %0, @%1+ \n\t"
+ "ld %1, @%1 \n\t"
+ "st %2, @+%0 \n\t"
+ "st %2, @+%1 \n\t"
+ : "=&r" (tmpreg0), "=&r" (tmpreg1), "=&r" (tmpreg2)
+ : "r" (page), "i" (MMU_REG_BASE), "i" (MSVA_offset),
+ "i" (MTOP_offset), "i" (MIDXI_offset)
+ : "memory"
+ );
+}
+
+static __inline__ void __flush_tlb_all(void)
+{
+ unsigned int tmpreg0, tmpreg1;
+
+ __asm__ __volatile__ (
+ "seth %0, #high(%2) \n\t"
+ "or3 %0, %0, #low(%2) \n\t"
+ "ldi %1, #0xc \n\t"
+ "st %1, @%0 \n\t"
+ ".fillinsn \n"
+ "1: \n\t"
+ "ld %1, @%0 \n\t"
+ "bnez %1, 1b \n\t"
+ : "=&r" (tmpreg0), "=&r" (tmpreg1)
+ : "i" (MTOP) : "memory"
+ );
+}
+
+#define flush_tlb_pgtables(mm, start, end) do { } while (0)
+
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+
+#endif /* _ASM_M32R_TLBFLUSH_H */
+
--- /dev/null
+/*
+ * linux/include/asm-generic/topology.h
+ *
+ * Written by: Matthew Dobson, IBM Corporation
+ *
+ * Copyright (C) 2002, IBM Corp.
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Send feedback to <colpatch@us.ibm.com>
+ */
+#ifndef _ASM_M32R_TOPOLOGY_H
+#define _ASM_M32R_TOPOLOGY_H
+
+/* Other architectures wishing to use this simple topology API should fill
+ in the below functions as appropriate in their own <asm/topology.h> file. */
+
+#define cpu_to_node(cpu) (0)
+
+#ifndef parent_node
+#define parent_node(node) (0)
+#endif
+#ifndef node_to_cpumask
+#define node_to_cpumask(node) (cpu_online_map)
+#endif
+#ifndef node_to_first_cpu
+#define node_to_first_cpu(node) (0)
+#endif
+#ifndef pcibus_to_cpumask
+#define pcibus_to_cpumask(bus) (cpu_online_map)
+#endif
+
+/* Cross-node load balancing interval. */
+#ifndef NODE_BALANCE_RATE
+#define NODE_BALANCE_RATE 10
+#endif
+
+#endif /* _ASM_M32R_TOPOLOGY_H */
--- /dev/null
+#ifndef _ASM_M32R_TYPES_H
+#define _ASM_M32R_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+/* $Id$ */
+
+/* orig : i386 2.4.18 */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+/* DMA addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+typedef u64 dma64_addr_t;
+
+typedef unsigned short kmem_bufctl_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_M32R_TYPES_H */
--- /dev/null
+#ifndef _ASM_M32R_UACCESS_H
+#define _ASM_M32R_UACCESS_H
+
+/*
+ * linux/include/asm-m32r/uaccess.h
+ *
+ * M32R version.
+ * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
+ */
+
+#undef UACCESS_DEBUG
+
+#ifdef UACCESS_DEBUG
+#define UAPRINTK(args...) printk(args)
+#else
+#define UAPRINTK(args...)
+#endif /* UACCESS_DEBUG */
+
+/*
+ * User space memory access functions
+ */
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/thread_info.h>
+#include <asm/page.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not. If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+
+#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
+
+#ifdef CONFIG_MMU
+#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
+#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
+#else
+#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
+#define USER_DS MAKE_MM_SEG(0xFFFFFFFF)
+#endif /* CONFIG_MMU */
+
+#define get_ds() (KERNEL_DS)
+#ifdef CONFIG_MMU
+#define get_fs() (current_thread_info()->addr_limit)
+#define set_fs(x) (current_thread_info()->addr_limit = (x))
+#else
+static inline mm_segment_t get_fs(void)
+{
+ return USER_DS;
+}
+
+static inline void set_fs(mm_segment_t s)
+{
+}
+#endif /* CONFIG_MMU */
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+#define __addr_ok(addr) \
+ ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
+
+/*
+ * Test whether a block of memory is a valid user space address.
+ * Returns 0 if the range is valid, nonzero otherwise.
+ *
+ * This is equivalent to the following test:
+ * (u33)addr + (u33)size >= (u33)current->addr_limit.seg
+ *
+ * This needs 33-bit arithmetic. We have a carry...
+ */
+#define __range_ok(addr,size) ({ \
+ unsigned long flag, sum; \
+ __chk_user_ptr(addr); \
+ asm ( \
+ " cmpu %1, %1 ; clear cbit\n" \
+ " addx %1, %3 ; set cbit if overflow\n" \
+ " subx %0, %0\n" \
+ " cmpu %4, %1\n" \
+ " subx %0, %5\n" \
+ : "=&r"(flag), "=r"(sum) \
+ : "1"(addr), "r"((int)(size)), \
+ "r"(current_thread_info()->addr_limit.seg), "r"(0) \
+ : "cbit" ); \
+ flag; })
+
+/**
+ * access_ok: - Checks if a user space pointer is valid
+ * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
+ * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
+ * to write to a block, it is always safe to read from it.
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns true (nonzero) if the memory block may be valid, false (zero)
+ * if it is definitely invalid.
+ *
+ * Note that, depending on architecture, this function probably just
+ * checks that the pointer is in the user space range - after calling
+ * this function, memory access functions may still return -EFAULT.
+ */
+#ifdef CONFIG_MMU
+#define access_ok(type,addr,size) (likely(__range_ok(addr,size) == 0))
+#else
+static inline int access_ok(int type, const void *addr, unsigned long size)
+{
+ extern unsigned long memory_start, memory_end;
+ unsigned long val = (unsigned long)addr;
+
+ return ((val >= memory_start) && ((val + size) < memory_end));
+}
+#endif /* CONFIG_MMU */
+
+/**
+ * verify_area: - Obsolete, use access_ok()
+ * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * This function has been replaced by access_ok().
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns zero if the memory block may be valid, -EFAULT
+ * if it is definitely invalid.
+ *
+ * See access_ok() for more details.
+ */
+static inline int verify_area(int type, const void __user *addr,
+ unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+ unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the uglyness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ */
+
+extern void __get_user_1(void);
+extern void __get_user_2(void);
+extern void __get_user_4(void);
+
+#ifndef MODULE
+#define __get_user_x(size,ret,x,ptr) \
+ __asm__ __volatile__( \
+ " mv r0, %0\n" \
+ " mv r1, %1\n" \
+ " bl __get_user_" #size "\n" \
+ " mv %0, r0\n" \
+ " mv %1, r1\n" \
+ : "=r"(ret), "=r"(x) \
+ : "0"(ptr) \
+ : "r0", "r1", "r14" )
+#else /* MODULE */
+/*
+ * Use "jl" instead of "bl" for MODULE
+ */
+#define __get_user_x(size,ret,x,ptr) \
+ __asm__ __volatile__( \
+ " mv r0, %0\n" \
+ " mv r1, %1\n" \
+ " seth lr, #high(__get_user_" #size ")\n" \
+ " or3 lr, lr, #low(__get_user_" #size ")\n" \
+ " jl lr\n" \
+ " mv %0, r0\n" \
+ " mv %1, r1\n" \
+ : "=r"(ret), "=r"(x) \
+ : "0"(ptr) \
+ : "r0", "r1", "r14" )
+#endif
+
+/* Careful: we have to cast the result to the type of the pointer for sign
+ reasons */
+/**
+ * get_user: - Get a simple variable from user space.
+ * @x: Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space. It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define get_user(x,ptr) \
+({ int __ret_gu,__val_gu; \
+ __chk_user_ptr(ptr); \
+ switch(sizeof (*(ptr))) { \
+ case 1: __get_user_x(1,__ret_gu,__val_gu,ptr); break; \
+ case 2: __get_user_x(2,__ret_gu,__val_gu,ptr); break; \
+ case 4: __get_user_x(4,__ret_gu,__val_gu,ptr); break; \
+ default: __get_user_x(X,__ret_gu,__val_gu,ptr); break; \
+ } \
+ (x) = (__typeof__(*(ptr)))__val_gu; \
+ __ret_gu; \
+})
+
+extern void __put_user_bad(void);
+
+/**
+ * put_user: - Write a simple value into user space.
+ * @x: Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space. It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define put_user(x,ptr) \
+ __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
+
+
+/**
+ * __get_user: - Get a simple variable from user space, with less checking.
+ * @x: Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space. It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define __get_user(x,ptr) \
+ __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
+
+
+/**
+ * __put_user: - Write a simple value into user space, with less checking.
+ * @x: Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space. It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define __put_user(x,ptr) \
+ __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
+
+#define __put_user_nocheck(x,ptr,size) \
+({ \
+ long __pu_err; \
+ __put_user_size((x),(ptr),(size),__pu_err); \
+ __pu_err; \
+})
+
+
+#define __put_user_check(x,ptr,size) \
+({ \
+ long __pu_err = -EFAULT; \
+ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
+ might_sleep(); \
+ if (access_ok(VERIFY_WRITE,__pu_addr,size)) \
+ __put_user_size((x),__pu_addr,(size),__pu_err); \
+ __pu_err; \
+})
+
+#if defined(__LITTLE_ENDIAN__)
+#define __put_user_u64(x, addr, err) \
+ __asm__ __volatile__( \
+ " .fillinsn\n" \
+ "1: st %L1,@%2\n" \
+ " .fillinsn\n" \
+ "2: st %H1,@(4,%2)\n" \
+ " .fillinsn\n" \
+ "3:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "4: ldi %0,%3\n" \
+ " seth r14,#high(3b)\n" \
+ " or3 r14,r14,#low(3b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 1b,4b\n" \
+ " .long 2b,4b\n" \
+ ".previous" \
+ : "=r"(err) \
+ : "r"(x), "r"(addr), "i"(-EFAULT), "0"(err) \
+ : "r14", "memory")
+
+#elif defined(__BIG_ENDIAN__)
+#define __put_user_u64(x, addr, err) \
+ __asm__ __volatile__( \
+ " .fillinsn\n" \
+ "1: st %H1,@%2\n" \
+ " .fillinsn\n" \
+ "2: st %L1,@(4,%2)\n" \
+ " .fillinsn\n" \
+ "3:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "4: ldi %0,%3\n" \
+ " seth r14,#high(3b)\n" \
+ " or3 r14,r14,#low(3b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 1b,4b\n" \
+ " .long 2b,4b\n" \
+ ".previous" \
+ : "=r"(err) \
+ : "r"(x), "r"(addr), "i"(-EFAULT), "0"(err) \
+ : "r14", "memory")
+#else
+#error no endian defined
+#endif
+
+#define __put_user_size(x,ptr,size,retval) \
+do { \
+ retval = 0; \
+ __chk_user_ptr(ptr); \
+ switch (size) { \
+ case 1: __put_user_asm(x,ptr,retval,"b"); break; \
+ case 2: __put_user_asm(x,ptr,retval,"h"); break; \
+ case 4: __put_user_asm(x,ptr,retval,""); break; \
+ case 8: __put_user_u64((__typeof__(*ptr))(x),ptr,retval); break;\
+ default: __put_user_bad(); \
+ } \
+} while (0)
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+#define __put_user_asm(x, addr, err, itype) \
+ __asm__ __volatile__( \
+ " .fillinsn\n" \
+ "1: st"itype" %1,@%2\n" \
+ " .fillinsn\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "3: ldi %0,%3\n" \
+ " seth r14,#high(2b)\n" \
+ " or3 r14,r14,#low(2b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 1b,3b\n" \
+ ".previous" \
+ : "=r"(err) \
+ : "r"(x), "r"(addr), "i"(-EFAULT), "0"(err) \
+ : "r14", "memory")
+
+#define __get_user_nocheck(x,ptr,size) \
+({ \
+ long __gu_err, __gu_val; \
+ __get_user_size(__gu_val,(ptr),(size),__gu_err); \
+ (x) = (__typeof__(*(ptr)))__gu_val; \
+ __gu_err; \
+})
+
+extern long __get_user_bad(void);
+
+#define __get_user_size(x,ptr,size,retval) \
+do { \
+ retval = 0; \
+ __chk_user_ptr(ptr); \
+ switch (size) { \
+ case 1: __get_user_asm(x,ptr,retval,"ub"); break; \
+ case 2: __get_user_asm(x,ptr,retval,"uh"); break; \
+ case 4: __get_user_asm(x,ptr,retval,""); break; \
+ default: (x) = __get_user_bad(); \
+ } \
+} while (0)
+
+#define __get_user_asm(x, addr, err, itype) \
+ __asm__ __volatile__( \
+ " .fillinsn\n" \
+ "1: ld"itype" %1,@%2\n" \
+ " .fillinsn\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "3: ldi %0,%3\n" \
+ " seth r14,#high(2b)\n" \
+ " or3 r14,r14,#low(2b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 1b,3b\n" \
+ ".previous" \
+ : "=r"(err), "=&r"(x) \
+ : "r"(addr), "i"(-EFAULT), "0"(err) \
+ : "r14", "memory")
+
+/*
+ * Here we special-case 1, 2 and 4-byte copy_*_user invocations. On a fault
+ * we return the initial request size (1, 2 or 4), as copy_*_user should do.
+ * If a store crosses a page boundary and gets a fault, the m32r will not write
+ * anything, so this is accurate.
+ */
+
+
+/*
+ * Copy To/From Userspace
+ */
+
+/* Generic arbitrary sized copy. */
+/* Return the number of bytes NOT copied. */
+#define __copy_user(to,from,size) \
+do { \
+ unsigned long __dst, __src, __c; \
+ __asm__ __volatile__ ( \
+ " mv r14, %0\n" \
+ " or r14, %1\n" \
+ " beq %0, %1, 9f\n" \
+ " beqz %2, 9f\n" \
+ " and3 r14, r14, #3\n" \
+ " bnez r14, 2f\n" \
+ " and3 %2, %2, #3\n" \
+ " beqz %3, 2f\n" \
+ " addi %0, #-4 ; word_copy \n" \
+ " .fillinsn\n" \
+ "0: ld r14, @%1+\n" \
+ " addi %3, #-1\n" \
+ " .fillinsn\n" \
+ "1: st r14, @+%0\n" \
+ " bnez %3, 0b\n" \
+ " beqz %2, 9f\n" \
+ " addi %0, #4\n" \
+ " .fillinsn\n" \
+ "2: ldb r14, @%1 ; byte_copy \n" \
+ " .fillinsn\n" \
+ "3: stb r14, @%0\n" \
+ " addi %1, #1\n" \
+ " addi %2, #-1\n" \
+ " addi %0, #1\n" \
+ " bnez %2, 2b\n" \
+ " .fillinsn\n" \
+ "9:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "5: addi %3, #1\n" \
+ " addi %1, #-4\n" \
+ " .fillinsn\n" \
+ "6: slli %3, #2\n" \
+ " add %2, %3\n" \
+ " addi %0, #4\n" \
+ " .fillinsn\n" \
+ "7: seth r14, #high(9b)\n" \
+ " or3 r14, r14, #low(9b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,6b\n" \
+ " .long 1b,5b\n" \
+ " .long 2b,9b\n" \
+ " .long 3b,9b\n" \
+ ".previous\n" \
+ : "=&r"(__dst), "=&r"(__src), "=&r"(size), "=&r"(__c) \
+ : "0"(to), "1"(from), "2"(size), "3"(size / 4) \
+ : "r14", "memory"); \
+} while (0)
+
+#define __copy_user_zeroing(to,from,size) \
+do { \
+ unsigned long __dst, __src, __c; \
+ __asm__ __volatile__ ( \
+ " mv r14, %0\n" \
+ " or r14, %1\n" \
+ " beq %0, %1, 9f\n" \
+ " beqz %2, 9f\n" \
+ " and3 r14, r14, #3\n" \
+ " bnez r14, 2f\n" \
+ " and3 %2, %2, #3\n" \
+ " beqz %3, 2f\n" \
+ " addi %0, #-4 ; word_copy \n" \
+ " .fillinsn\n" \
+ "0: ld r14, @%1+\n" \
+ " addi %3, #-1\n" \
+ " .fillinsn\n" \
+ "1: st r14, @+%0\n" \
+ " bnez %3, 0b\n" \
+ " beqz %2, 9f\n" \
+ " addi %0, #4\n" \
+ " .fillinsn\n" \
+ "2: ldb r14, @%1 ; byte_copy \n" \
+ " .fillinsn\n" \
+ "3: stb r14, @%0\n" \
+ " addi %1, #1\n" \
+ " addi %2, #-1\n" \
+ " addi %0, #1\n" \
+ " bnez %2, 2b\n" \
+ " .fillinsn\n" \
+ "9:\n" \
+ ".section .fixup,\"ax\"\n" \
+ " .balign 4\n" \
+ "5: addi %3, #1\n" \
+ " addi %1, #-4\n" \
+ " .fillinsn\n" \
+ "6: slli %3, #2\n" \
+ " add %2, %3\n" \
+ " addi %0, #4\n" \
+ " .fillinsn\n" \
+ "7: ldi r14, #0 ; store zero \n" \
+ " .fillinsn\n" \
+ "8: addi %2, #-1\n" \
+ " stb r14, @%0 ; ACE? \n" \
+ " addi %0, #1\n" \
+ " bnez %2, 8b\n" \
+ " seth r14, #high(9b)\n" \
+ " or3 r14, r14, #low(9b)\n" \
+ " jmp r14\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,6b\n" \
+ " .long 1b,5b\n" \
+ " .long 2b,7b\n" \
+ " .long 3b,7b\n" \
+ ".previous\n" \
+ : "=&r"(__dst), "=&r"(__src), "=&r"(size), "=&r"(__c) \
+ : "0"(to), "1"(from), "2"(size), "3"(size / 4) \
+ : "r14", "memory"); \
+} while (0)
+
+
+/* We let the __ versions of copy_from/to_user inline, because they're often
+ * used in fast paths and have only a small space overhead.
+ */
+static inline unsigned long __generic_copy_from_user_nocheck(void *to,
+ const void __user *from, unsigned long n)
+{
+ __copy_user_zeroing(to,from,n);
+ return n;
+}
+
+static inline unsigned long __generic_copy_to_user_nocheck(void __user *to,
+ const void *from, unsigned long n)
+{
+ __copy_user(to,from,n);
+ return n;
+}
+
+unsigned long __generic_copy_to_user(void *, const void *, unsigned long);
+unsigned long __generic_copy_from_user(void *, const void *, unsigned long);
+
+/**
+ * __copy_to_user: - Copy a block of data into user space, with less checking.
+ * @to: Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n: Number of bytes to copy.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * Copy data from kernel space to user space. Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+#define __copy_to_user(to,from,n) \
+ __generic_copy_to_user_nocheck((to),(from),(n))
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+/**
+ * copy_to_user: - Copy a block of data into user space.
+ * @to: Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n: Number of bytes to copy.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * Copy data from kernel space to user space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+#define copy_to_user(to,from,n) \
+({ \
+ might_sleep(); \
+ __generic_copy_to_user((to),(from),(n)); \
+})
+
+/**
+ * __copy_from_user: - Copy a block of data from user space, with less checking. * @to: Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n: Number of bytes to copy.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * Copy data from user space to kernel space. Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+#define __copy_from_user(to,from,n) \
+ __generic_copy_from_user_nocheck((to),(from),(n))
+
+/**
+ * copy_from_user: - Copy a block of data from user space.
+ * @to: Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n: Number of bytes to copy.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * Copy data from user space to kernel space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+#define copy_from_user(to,from,n) \
+({ \
+ might_sleep(); \
+__generic_copy_from_user((to),(from),(n)); \
+})
+
+long __must_check strncpy_from_user(char *dst, const char __user *src,
+ long count);
+long __must_check __strncpy_from_user(char *dst,
+ const char __user *src, long count);
+
+/**
+ * __clear_user: - Zero a block of memory in user space, with less checking.
+ * @to: Destination address, in user space.
+ * @n: Number of bytes to zero.
+ *
+ * Zero a block of memory in user space. Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+unsigned long __clear_user(void __user *mem, unsigned long len);
+
+/**
+ * clear_user: - Zero a block of memory in user space.
+ * @to: Destination address, in user space.
+ * @n: Number of bytes to zero.
+ *
+ * Zero a block of memory in user space. Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+unsigned long clear_user(void __user *mem, unsigned long len);
+
+/**
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only. This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+#define strlen_user(str) strnlen_user(str, ~0UL >> 1)
+long strnlen_user(const char __user *str, long n);
+
+#endif /* _ASM_M32R_UACCESS_H */
--- /dev/null
+#ifndef _ASM_M32R_UCONTEXT_H
+#define _ASM_M32R_UCONTEXT_H
+
+/* orig : i386 2.4.18 */
+
+struct ucontext {
+ unsigned long uc_flags;
+ struct ucontext *uc_link;
+ stack_t uc_stack;
+ struct sigcontext uc_mcontext;
+ sigset_t uc_sigmask; /* mask last for extensibility */
+};
+
+#endif /* _ASM_M32R_UCONTEXT_H */
--- /dev/null
+#ifndef _ASM_M32R_UNALIGNED_H
+#define _ASM_M32R_UNALIGNED_H
+
+/* $Id$ */
+
+/* orig : generic 2.4.18 */
+
+/*
+ * For the benefit of those who are trying to port Linux to another
+ * architecture, here are some C-language equivalents.
+ */
+
+#include <asm/string.h>
+
+
+#define get_unaligned(ptr) \
+ ({ __typeof__(*(ptr)) __tmp; memmove(&__tmp, (ptr), sizeof(*(ptr))); __tmp; })
+
+#define put_unaligned(val, ptr) \
+ ({ __typeof__(*(ptr)) __tmp = (val); \
+ memmove((ptr), &__tmp, sizeof(*(ptr))); \
+ (void)0; })
+
+
+#endif /* _ASM_M32R_UNALIGNED_H */
--- /dev/null
+#ifndef _ASM_M32R_UNISTD_H
+#define _ASM_M32R_UNISTD_H
+
+/* $Id$ */
+
+#include <asm/syscall.h> /* SYSCALL_* */
+
+/*
+ * This file contains the system call numbers.
+ */
+
+#define __NR_restart_syscall 0
+#define __NR_exit 1
+#define __NR_fork 2
+#define __NR_read 3
+#define __NR_write 4
+#define __NR_open 5
+#define __NR_close 6
+#define __NR_waitpid 7
+#define __NR_creat 8
+#define __NR_link 9
+#define __NR_unlink 10
+#define __NR_execve 11
+#define __NR_chdir 12
+#define __NR_time 13
+#define __NR_mknod 14
+#define __NR_chmod 15
+#define __NR_lchown 16
+#define __NR_break 17
+#define __NR_oldstat 18
+#define __NR_lseek 19
+#define __NR_getpid 20
+#define __NR_mount 21
+#define __NR_umount 22
+#define __NR_setuid 23
+#define __NR_getuid 24
+#define __NR_stime 25
+#define __NR_ptrace 26
+#define __NR_alarm 27
+#define __NR_oldfstat 28
+#define __NR_pause 29
+#define __NR_utime 30
+#define __NR_cacheflush 31 /* old #define __NR_stty 31*/
+#define __NR_cachectl 32 /* old #define __NR_gtty 32*/
+#define __NR_access 33
+#define __NR_nice 34
+#define __NR_ftime 35
+#define __NR_sync 36
+#define __NR_kill 37
+#define __NR_rename 38
+#define __NR_mkdir 39
+#define __NR_rmdir 40
+#define __NR_dup 41
+#define __NR_pipe 42
+#define __NR_times 43
+#define __NR_prof 44
+#define __NR_brk 45
+#define __NR_setgid 46
+#define __NR_getgid 47
+#define __NR_signal 48
+#define __NR_geteuid 49
+#define __NR_getegid 50
+#define __NR_acct 51
+#define __NR_umount2 52
+#define __NR_lock 53
+#define __NR_ioctl 54
+#define __NR_fcntl 55
+#define __NR_mpx 56
+#define __NR_setpgid 57
+#define __NR_ulimit 58
+#define __NR_oldolduname 59
+#define __NR_umask 60
+#define __NR_chroot 61
+#define __NR_ustat 62
+#define __NR_dup2 63
+#define __NR_getppid 64
+#define __NR_getpgrp 65
+#define __NR_setsid 66
+#define __NR_sigaction 67
+#define __NR_sgetmask 68
+#define __NR_ssetmask 69
+#define __NR_setreuid 70
+#define __NR_setregid 71
+#define __NR_sigsuspend 72
+#define __NR_sigpending 73
+#define __NR_sethostname 74
+#define __NR_setrlimit 75
+#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage 77
+#define __NR_gettimeofday 78
+#define __NR_settimeofday 79
+#define __NR_getgroups 80
+#define __NR_setgroups 81
+#define __NR_select 82
+#define __NR_symlink 83
+#define __NR_oldlstat 84
+#define __NR_readlink 85
+#define __NR_uselib 86
+#define __NR_swapon 87
+#define __NR_reboot 88
+#define __NR_readdir 89
+#define __NR_mmap 90
+#define __NR_munmap 91
+#define __NR_truncate 92
+#define __NR_ftruncate 93
+#define __NR_fchmod 94
+#define __NR_fchown 95
+#define __NR_getpriority 96
+#define __NR_setpriority 97
+#define __NR_profil 98
+#define __NR_statfs 99
+#define __NR_fstatfs 100
+#define __NR_ioperm 101
+#define __NR_socketcall 102
+#define __NR_syslog 103
+#define __NR_setitimer 104
+#define __NR_getitimer 105
+#define __NR_stat 106
+#define __NR_lstat 107
+#define __NR_fstat 108
+#define __NR_olduname 109
+#define __NR_iopl 110
+#define __NR_vhangup 111
+#define __NR_idle 112
+#define __NR_vm86old 113
+#define __NR_wait4 114
+#define __NR_swapoff 115
+#define __NR_sysinfo 116
+#define __NR_ipc 117
+#define __NR_fsync 118
+#define __NR_sigreturn 119
+#define __NR_clone 120
+#define __NR_setdomainname 121
+#define __NR_uname 122
+#define __NR_modify_ldt 123
+#define __NR_adjtimex 124
+#define __NR_mprotect 125
+#define __NR_sigprocmask 126
+#define __NR_create_module 127
+#define __NR_init_module 128
+#define __NR_delete_module 129
+#define __NR_get_kernel_syms 130
+#define __NR_quotactl 131
+#define __NR_getpgid 132
+#define __NR_fchdir 133
+#define __NR_bdflush 134
+#define __NR_sysfs 135
+#define __NR_personality 136
+#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
+#define __NR_setfsuid 138
+#define __NR_setfsgid 139
+#define __NR__llseek 140
+#define __NR_getdents 141
+#define __NR__newselect 142
+#define __NR_flock 143
+#define __NR_msync 144
+#define __NR_readv 145
+#define __NR_writev 146
+#define __NR_getsid 147
+#define __NR_fdatasync 148
+#define __NR__sysctl 149
+#define __NR_mlock 150
+#define __NR_munlock 151
+#define __NR_mlockall 152
+#define __NR_munlockall 153
+#define __NR_sched_setparam 154
+#define __NR_sched_getparam 155
+#define __NR_sched_setscheduler 156
+#define __NR_sched_getscheduler 157
+#define __NR_sched_yield 158
+#define __NR_sched_get_priority_max 159
+#define __NR_sched_get_priority_min 160
+#define __NR_sched_rr_get_interval 161
+#define __NR_nanosleep 162
+#define __NR_mremap 163
+#define __NR_setresuid 164
+#define __NR_getresuid 165
+#define __NR_tas 166
+#define __NR_query_module 167
+#define __NR_poll 168
+#define __NR_nfsservctl 169
+#define __NR_setresgid 170
+#define __NR_getresgid 171
+#define __NR_prctl 172
+#define __NR_rt_sigreturn 173
+#define __NR_rt_sigaction 174
+#define __NR_rt_sigprocmask 175
+#define __NR_rt_sigpending 176
+#define __NR_rt_sigtimedwait 177
+#define __NR_rt_sigqueueinfo 178
+#define __NR_rt_sigsuspend 179
+#define __NR_pread64 180
+#define __NR_pwrite64 181
+#define __NR_chown 182
+#define __NR_getcwd 183
+#define __NR_capget 184
+#define __NR_capset 185
+#define __NR_sigaltstack 186
+#define __NR_sendfile 187
+#define __NR_getpmsg 188 /* some people actually want streams */
+#define __NR_putpmsg 189 /* some people actually want streams */
+#define __NR_vfork 190
+#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
+#define __NR_mmap2 192
+#define __NR_truncate64 193
+#define __NR_ftruncate64 194
+#define __NR_stat64 195
+#define __NR_lstat64 196
+#define __NR_fstat64 197
+#define __NR_lchown32 198
+#define __NR_getuid32 199
+#define __NR_getgid32 200
+#define __NR_geteuid32 201
+#define __NR_getegid32 202
+#define __NR_setreuid32 203
+#define __NR_setregid32 204
+#define __NR_getgroups32 205
+#define __NR_setgroups32 206
+#define __NR_fchown32 207
+#define __NR_setresuid32 208
+#define __NR_getresuid32 209
+#define __NR_setresgid32 210
+#define __NR_getresgid32 211
+#define __NR_chown32 212
+#define __NR_setuid32 213
+#define __NR_setgid32 214
+#define __NR_setfsuid32 215
+#define __NR_setfsgid32 216
+#define __NR_pivot_root 217
+#define __NR_mincore 218
+#define __NR_madvise 219
+#define __NR_madvise1 219 /* delete when C lib stub is removed */
+#define __NR_getdents64 220
+#define __NR_fcntl64 221
+#define __NR_security 223 /* syscall for security modules */
+#define __NR_gettid 224
+#define __NR_readahead 225
+#define __NR_setxattr 226
+#define __NR_lsetxattr 227
+#define __NR_fsetxattr 228
+#define __NR_getxattr 229
+#define __NR_lgetxattr 230
+#define __NR_fgetxattr 231
+#define __NR_listxattr 232
+#define __NR_llistxattr 233
+#define __NR_flistxattr 234
+#define __NR_removexattr 235
+#define __NR_lremovexattr 236
+#define __NR_fremovexattr 237
+#define __NR_tkill 238
+#define __NR_sendfile64 239
+#define __NR_futex 240
+#define __NR_sched_setaffinity 241
+#define __NR_sched_getaffinity 242
+#define __NR_set_thread_area 243
+#define __NR_get_thread_area 244
+#define __NR_io_setup 245
+#define __NR_io_destroy 246
+#define __NR_io_getevents 247
+#define __NR_io_submit 248
+#define __NR_io_cancel 249
+#define __NR_fadvise64 250
+
+#define __NR_exit_group 252
+#define __NR_lookup_dcookie 253
+#define __NR_epoll_create 254
+#define __NR_epoll_ctl 255
+#define __NR_epoll_wait 256
+#define __NR_remap_file_pages 257
+#define __NR_set_tid_address 258
+#define __NR_timer_create 259
+#define __NR_timer_settime (__NR_timer_create+1)
+#define __NR_timer_gettime (__NR_timer_create+2)
+#define __NR_timer_getoverrun (__NR_timer_create+3)
+#define __NR_timer_delete (__NR_timer_create+4)
+#define __NR_clock_settime (__NR_timer_create+5)
+#define __NR_clock_gettime (__NR_timer_create+6)
+#define __NR_clock_getres (__NR_timer_create+7)
+#define __NR_clock_nanosleep (__NR_timer_create+8)
+#define __NR_statfs64 268
+#define __NR_fstatfs64 269
+#define __NR_tgkill 270
+#define __NR_utimes 271
+#define __NR_fadvise64_64 272
+#define __NR_vserver 273
+#define __NR_mbind 274
+#define __NR_get_mempolicy 275
+#define __NR_set_mempolicy 276
+#define __NR_mq_open 277
+#define __NR_mq_unlink (__NR_mq_open+1)
+#define __NR_mq_timedsend (__NR_mq_open+2)
+#define __NR_mq_timedreceive (__NR_mq_open+3)
+#define __NR_mq_notify (__NR_mq_open+4)
+#define __NR_mq_getsetattr (__NR_mq_open+5)
+#define __NR_sys_kexec_load 283
+#define __NR_waitid 284
+
+#define NR_syscalls 285
+
+/* user-visible error numbers are in the range -1 - -124: see
+ * <asm-m32r/errno.h>
+ */
+
+#define __syscall_return(type, res) \
+do { \
+ if ((unsigned long)(res) >= (unsigned long)(-(124 + 1))) { \
+ /* Avoid using "res" which is declared to be in register r0; \
+ errno might expand to a function call and clobber it. */ \
+ int __err = -(res); \
+ errno = __err; \
+ res = -1; \
+ } \
+ return (type) (res); \
+} while (0)
+
+#define _syscall0(type,name) \
+type name(void) \
+{ \
+register long __scno __asm__ ("r7") = __NR_##name; \
+register long __res __asm__("r0"); \
+__asm__ __volatile__ (\
+ "trap #" SYSCALL_VECTOR \
+ : "=r" (__res) \
+ : "r" (__scno) \
+ : "memory"); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall1(type,name,type1,arg1) \
+type name(type1 arg1) \
+{ \
+register long __scno __asm__ ("r7") = __NR_##name; \
+register long __res __asm__ ("r0") = (long)(arg1); \
+__asm__ __volatile__ (\
+ "trap #" SYSCALL_VECTOR \
+ : "=r" (__res) \
+ : "r" (__scno), "0" (__res) \
+ : "memory"); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall2(type,name,type1,arg1,type2,arg2) \
+type name(type1 arg1,type2 arg2) \
+{ \
+register long __scno __asm__ ("r7") = __NR_##name; \
+register long __arg2 __asm__ ("r1") = (long)(arg2); \
+register long __res __asm__ ("r0") = (long)(arg1); \
+__asm__ __volatile__ (\
+ "trap #" SYSCALL_VECTOR \
+ : "=r" (__res) \
+ : "r" (__scno), "0" (__res), "r" (__arg2) \
+ : "memory"); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
+type name(type1 arg1,type2 arg2,type3 arg3) \
+{ \
+register long __scno __asm__ ("r7") = __NR_##name; \
+register long __arg3 __asm__ ("r2") = (long)(arg3); \
+register long __arg2 __asm__ ("r1") = (long)(arg2); \
+register long __res __asm__ ("r0") = (long)(arg1); \
+__asm__ __volatile__ (\
+ "trap #" SYSCALL_VECTOR \
+ : "=r" (__res) \
+ : "r" (__scno), "0" (__res), "r" (__arg2), \
+ "r" (__arg3) \
+ : "memory"); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+type name(type1 arg1,type2 arg2,type3 arg3,type4 arg4) \
+{ \
+register long __scno __asm__ ("r7") = __NR_##name; \
+register long __arg4 __asm__ ("r3") = (long)(arg4); \
+register long __arg3 __asm__ ("r2") = (long)(arg3); \
+register long __arg2 __asm__ ("r1") = (long)(arg2); \
+register long __res __asm__ ("r0") = (long)(arg1); \
+__asm__ __volatile__ (\
+ "trap #" SYSCALL_VECTOR \
+ : "=r" (__res) \
+ : "r" (__scno), "0" (__res), "r" (__arg2), \
+ "r" (__arg3), "r" (__arg4) \
+ : "memory"); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+ type5,arg5) \
+type name(type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
+{ \
+register long __scno __asm__ ("r7") = __NR_##name; \
+register long __arg5 __asm__ ("r4") = (long)(arg5); \
+register long __arg4 __asm__ ("r3") = (long)(arg4); \
+register long __arg3 __asm__ ("r2") = (long)(arg3); \
+register long __arg2 __asm__ ("r1") = (long)(arg2); \
+register long __res __asm__ ("r0") = (long)(arg1); \
+__asm__ __volatile__ (\
+ "trap #" SYSCALL_VECTOR \
+ : "=r" (__res) \
+ : "r" (__scno), "0" (__res), "r" (__arg2), \
+ "r" (__arg3), "r" (__arg4), "r" (__arg5) \
+ : "memory"); \
+__syscall_return(type,__res); \
+}
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#endif
+
+#ifdef __KERNEL_SYSCALLS__
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+
+/*
+ * we need this inline - forking from kernel space will result
+ * in NO COPY ON WRITE (!!!), until an execve is executed. This
+ * is no problem, but for the stack. This is handled by not letting
+ * main() use the stack at all after fork(). Thus, no function
+ * calls - which means inline code for fork too, as otherwise we
+ * would use the stack upon exit from 'fork()'.
+ *
+ * Actually only pause and fork are needed inline, so that there
+ * won't be any messing with the stack from main(), but we define
+ * some others too.
+ */
+static __inline__ _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
+
+asmlinkage int sys_modify_ldt(int func, void __user *ptr, unsigned long bytecount);
+asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
+ unsigned long prot, unsigned long flags,
+ unsigned long fd, unsigned long pgoff);
+asmlinkage int sys_execve(struct pt_regs regs);
+asmlinkage int sys_clone(struct pt_regs regs);
+asmlinkage int sys_fork(struct pt_regs regs);
+asmlinkage int sys_vfork(struct pt_regs regs);
+asmlinkage int sys_pipe(unsigned long __user *fildes);
+asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
+asmlinkage long sys_iopl(unsigned long unused);
+struct sigaction;
+asmlinkage long sys_rt_sigaction(int sig,
+ const struct sigaction __user *act,
+ struct sigaction __user *oact,
+ size_t sigsetsize);
+
+#endif /* __KERNEL_SYSCALLS__ */
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
+#endif
+
+#endif /* _ASM_M32R_UNISTD_H */
--- /dev/null
+#ifndef _ASM_M32R_USER_H
+#define _ASM_M32R_USER_H
+
+/* $Id$ */
+
+/* orig : sh 2.4.18
+ * mod : remove fpu registers
+ */
+
+#include <linux/types.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd).
+ *
+ * The actual file contents are as follows:
+ * UPAGE: 1 page consisting of a user struct that tells gdb
+ * what is present in the file. Directly after this is a
+ * copy of the task_struct, which is currently not used by gdb,
+ * but it may come in handy at some point. All of the registers
+ * are stored as part of the upage. The upage should always be
+ * only one page.
+ * DATA: The data area is stored. We use current->end_text to
+ * current->brk to pick up all of the user variables, plus any memory
+ * that may have been sbrk'ed. No attempt is made to determine if a
+ * page is demand-zero or if a page is totally unused, we just cover
+ * the entire range. All of the addresses are rounded in such a way
+ * that an integral number of pages is written.
+ * STACK: We need the stack information in order to get a meaningful
+ * backtrace. We need to write the data from usp to
+ * current->start_stack, so we round each of these off in order to be
+ * able to write an integer number of pages.
+ */
+
+struct user {
+ struct pt_regs regs; /* entire machine state */
+ size_t u_tsize; /* text size (pages) */
+ size_t u_dsize; /* data size (pages) */
+ size_t u_ssize; /* stack size (pages) */
+ unsigned long start_code; /* text starting address */
+ unsigned long start_data; /* data starting address */
+ unsigned long start_stack; /* stack starting address */
+ long int signal; /* signal causing core dump */
+ struct regs * u_ar0; /* help gdb find registers */
+ unsigned long magic; /* identifies a core file */
+ char u_comm[32]; /* user command name */
+};
+
+#define NBPG PAGE_SIZE
+#define UPAGES 1
+#define HOST_TEXT_START_ADDR (u.start_code)
+#define HOST_DATA_START_ADDR (u.start_data)
+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _ASM_M32R_USER_H */
--- /dev/null
+#ifndef _ASM_M32R_VGA_H
+#define _ASM_M32R_VGA_H
+
+/* $Id$ */
+
+/*
+ * Access to VGA videoram
+ *
+ * (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+/*
+ * On the PC, we can just recalculate addresses and then
+ * access the videoram directly without any black magic.
+ */
+
+#define VGA_MAP_MEM(x) (unsigned long)phys_to_virt(x)
+
+#define vga_readb(x) (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif /* _ASM_M32R_VGA_H */
--- /dev/null
+#ifndef _ASM_M32R_XOR_H
+#define _ASM_M32R_XOR_H
+
+/* $Id$ */
+
+#include <asm-generic/xor.h>
+
+#endif /* _ASM_M32R_XOR_H */
--- /dev/null
+/*
+ * 8253/8254 Programmable Interval Timer
+ */
+
+#ifndef _8253PIT_H
+#define _8253PIT_H
+
+#define PIT_TICK_RATE 1193182UL
+
+#endif
--- /dev/null
+/*
+ * 8253/8254 Programmable Interval Timer
+ */
+
+#ifndef _8253PIT_H
+#define _8253PIT_H
+
+#define PIT_TICK_RATE 1193182UL
+
+#endif
--- /dev/null
+#ifndef _PPC64_PLPAR_WRAPPERS_H
+#define _PPC64_PLPAR_WRAPPERS_H
+
+#include <asm/hvcall.h>
+
+static inline long poll_pending(void)
+{
+ unsigned long dummy;
+ return plpar_hcall(H_POLL_PENDING, 0, 0, 0, 0,
+ &dummy, &dummy, &dummy);
+}
+
+static inline long prod_processor(void)
+{
+ plpar_hcall_norets(H_PROD);
+ return(0);
+}
+
+static inline long cede_processor(void)
+{
+ plpar_hcall_norets(H_CEDE);
+ return(0);
+}
+
+static inline long register_vpa(unsigned long flags, unsigned long proc, unsigned long vpa)
+{
+ plpar_hcall_norets(H_REGISTER_VPA, flags, proc, vpa);
+ return(0);
+}
+
+static inline long plpar_pte_remove(unsigned long flags,
+ unsigned long ptex,
+ unsigned long avpn,
+ unsigned long *old_pteh_ret,
+ unsigned long *old_ptel_ret)
+{
+ unsigned long dummy;
+ return plpar_hcall(H_REMOVE, flags, ptex, avpn, 0,
+ old_pteh_ret, old_ptel_ret, &dummy);
+}
+
+static inline long plpar_pte_read(unsigned long flags,
+ unsigned long ptex,
+ unsigned long *old_pteh_ret, unsigned long *old_ptel_ret)
+{
+ unsigned long dummy;
+ return plpar_hcall(H_READ, flags, ptex, 0, 0,
+ old_pteh_ret, old_ptel_ret, &dummy);
+}
+
+static inline long plpar_pte_protect(unsigned long flags,
+ unsigned long ptex,
+ unsigned long avpn)
+{
+ return plpar_hcall_norets(H_PROTECT, flags, ptex, avpn);
+}
+
+static inline long plpar_tce_get(unsigned long liobn,
+ unsigned long ioba,
+ unsigned long *tce_ret)
+{
+ unsigned long dummy;
+ return plpar_hcall(H_GET_TCE, liobn, ioba, 0, 0,
+ tce_ret, &dummy, &dummy);
+}
+
+static inline long plpar_tce_put(unsigned long liobn,
+ unsigned long ioba,
+ unsigned long tceval)
+{
+ return plpar_hcall_norets(H_PUT_TCE, liobn, ioba, tceval);
+}
+
+static inline long plpar_tce_put_indirect(unsigned long liobn,
+ unsigned long ioba,
+ unsigned long page,
+ unsigned long count)
+{
+ return plpar_hcall_norets(H_PUT_TCE_INDIRECT, liobn, ioba, page, count);
+}
+
+static inline long plpar_tce_stuff(unsigned long liobn,
+ unsigned long ioba,
+ unsigned long tceval,
+ unsigned long count)
+{
+ return plpar_hcall_norets(H_STUFF_TCE, liobn, ioba, tceval, count);
+}
+
+static inline long plpar_get_term_char(unsigned long termno,
+ unsigned long *len_ret,
+ char *buf_ret)
+{
+ unsigned long *lbuf = (unsigned long *)buf_ret; /* ToDo: alignment? */
+ return plpar_hcall(H_GET_TERM_CHAR, termno, 0, 0, 0,
+ len_ret, lbuf+0, lbuf+1);
+}
+
+static inline long plpar_put_term_char(unsigned long termno,
+ unsigned long len,
+ const char *buffer)
+{
+ unsigned long *lbuf = (unsigned long *)buffer; /* ToDo: alignment? */
+ return plpar_hcall_norets(H_PUT_TERM_CHAR, termno, len, lbuf[0],
+ lbuf[1]);
+}
+
+
+#endif /* _PPC64_PLPAR_WRAPPERS_H */
--- /dev/null
+#ifndef _SPARC64_KPROBES_H
+#define _SPARC64_KPROBES_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+typedef u32 kprobe_opcode_t;
+
+#define BREAKPOINT_INSTRUCTION 0x91d02070 /* ta 0x70 */
+#define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */
+#define MAX_INSN_SIZE 2
+
+#ifdef CONFIG_KPROBES
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data);
+#else /* !CONFIG_KPROBES */
+static inline int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ return 0;
+}
+#endif
+
+#endif /* _SPARC64_KPROBES_H */
--- /dev/null
+#ifndef __UM_MODULE_I386_H
+#define __UM_MODULE_I386_H
+
+/* UML is simple */
+struct mod_arch_specific
+{
+};
+
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+
+#endif
--- /dev/null
+#ifndef _ASM_SWIOTLB_H
+#define _ASM_SWTIOLB_H 1
+
+#include <linux/config.h>
+
+/* SWIOTLB interface */
+
+extern dma_addr_t swiotlb_map_single(struct device *hwdev, void *ptr, size_t size,
+ int dir);
+extern void swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr,
+ size_t size, int dir);
+extern void swiotlb_sync_single_for_cpu(struct device *hwdev,
+ dma_addr_t dev_addr,
+ size_t size, int dir);
+extern void swiotlb_sync_single_for_device(struct device *hwdev,
+ dma_addr_t dev_addr,
+ size_t size, int dir);
+extern void swiotlb_sync_sg_for_cpu(struct device *hwdev,
+ struct scatterlist *sg, int nelems,
+ int dir);
+extern void swiotlb_sync_sg_for_device(struct device *hwdev,
+ struct scatterlist *sg, int nelems,
+ int dir);
+extern int swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg,
+ int nents, int direction);
+extern void swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg,
+ int nents, int direction);
+extern int swiotlb_dma_mapping_error(dma_addr_t dma_addr);
+
+#ifdef CONFIG_SWIOTLB
+extern int swiotlb;
+#else
+#define swiotlb 0
+#endif
+
+#endif
--- /dev/null
+#ifndef __LINUX_GEN_STATS_H
+#define __LINUX_GEN_STATS_H
+
+#include <linux/types.h>
+
+enum {
+ TCA_STATS_UNSPEC,
+ TCA_STATS_BASIC,
+ TCA_STATS_RATE_EST,
+ TCA_STATS_QUEUE,
+ TCA_STATS_APP,
+ __TCA_STATS_MAX,
+};
+#define TCA_STATS_MAX (__TCA_STATS_MAX - 1)
+
+/**
+ * @bytes: number of seen bytes
+ * @packets: number of seen packets
+ */
+struct gnet_stats_basic
+{
+ __u64 bytes;
+ __u32 packets;
+};
+
+/**
+ * @bps: current byte rate
+ * @pps: current packet rate
+ */
+struct gnet_stats_rate_est
+{
+ __u32 bps;
+ __u32 pps;
+};
+
+/**
+ * @qlen: queue length
+ * @backlog: backlog size of queue
+ * @drops: number of dropped packets
+ * @requeues: number of requeues
+ */
+struct gnet_stats_queue
+{
+ __u32 qlen;
+ __u32 backlog;
+ __u32 drops;
+ __u32 requeues;
+ __u32 overlimits;
+};
+
+/**
+ * @interval: sampling period
+ * @ewma_log: the log of measurement window weight
+ */
+struct gnet_estimator
+{
+ signed char interval;
+ unsigned char ewma_log;
+};
+
+
+#endif /* __LINUX_GEN_STATS_H */
--- /dev/null
+#ifndef LINUX_HARDIRQ_H
+#define LINUX_HARDIRQ_H
+
+#include <linux/config.h>
+#include <linux/smp_lock.h>
+#include <asm/hardirq.h>
+
+#define __IRQ_MASK(x) ((1UL << (x))-1)
+
+#define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT)
+#define HARDIRQ_MASK (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT)
+#define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT)
+
+#define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT)
+#define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT)
+#define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT)
+
+#define hardirq_count() (preempt_count() & HARDIRQ_MASK)
+#define softirq_count() (preempt_count() & SOFTIRQ_MASK)
+#define irq_count() (preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK))
+
+/*
+ * Are we doing bottom half or hardware interrupt processing?
+ * Are we in a softirq context? Interrupt context?
+ */
+#define in_irq() (hardirq_count())
+#define in_softirq() (softirq_count())
+#define in_interrupt() (irq_count())
+
+#ifdef CONFIG_PREEMPT
+# define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != kernel_locked())
+# define preemptible() (preempt_count() == 0 && !irqs_disabled())
+# define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1)
+#else
+# define in_atomic() (preempt_count() != 0)
+# define preemptible() 0
+# define IRQ_EXIT_OFFSET HARDIRQ_OFFSET
+#endif
+
+#ifdef CONFIG_SMP
+extern void synchronize_irq(unsigned int irq);
+#else
+# define synchronize_irq(irq) barrier()
+#endif
+
+#endif /* LINUX_HARDIRQ_H */
--- /dev/null
+#ifndef _LINUX_I2C_ALGO_PCA_H
+#define _LINUX_I2C_ALGO_PCA_H
+
+struct i2c_algo_pca_data {
+ int (*get_own) (struct i2c_algo_pca_data *adap); /* Obtain own address */
+ int (*get_clock) (struct i2c_algo_pca_data *adap);
+ void (*write_byte) (struct i2c_algo_pca_data *adap, int reg, int val);
+ int (*read_byte) (struct i2c_algo_pca_data *adap, int reg);
+ int (*wait_for_interrupt) (struct i2c_algo_pca_data *adap);
+};
+
+#define I2C_PCA_ADAP_MAX 16
+
+int i2c_pca_add_bus(struct i2c_adapter *);
+int i2c_pca_del_bus(struct i2c_adapter *);
+
+#endif /* _LINUX_I2C_ALGO_PCA_H */
--- /dev/null
+#ifndef LINUX_KEXEC_H
+#define LINUX_KEXEC_H
+
+#ifdef CONFIG_KEXEC
+#include <linux/types.h>
+#include <linux/list.h>
+#include <asm/kexec.h>
+
+/*
+ * This structure is used to hold the arguments that are used when loading
+ * kernel binaries.
+ */
+
+typedef unsigned long kimage_entry_t;
+#define IND_DESTINATION 0x1
+#define IND_INDIRECTION 0x2
+#define IND_DONE 0x4
+#define IND_SOURCE 0x8
+
+#define KEXEC_SEGMENT_MAX 8
+struct kexec_segment {
+ void *buf;
+ size_t bufsz;
+ void *mem;
+ size_t memsz;
+};
+
+struct kimage {
+ kimage_entry_t head;
+ kimage_entry_t *entry;
+ kimage_entry_t *last_entry;
+
+ unsigned long destination;
+
+ unsigned long start;
+ struct page *control_code_page;
+
+ unsigned long nr_segments;
+ struct kexec_segment segment[KEXEC_SEGMENT_MAX];
+
+ struct list_head control_pages;
+ struct list_head dest_pages;
+ struct list_head unuseable_pages;
+};
+
+
+/* kexec interface functions */
+extern void machine_kexec(struct kimage *image);
+extern int machine_kexec_prepare(struct kimage *image);
+extern void machine_kexec_cleanup(struct kimage *image);
+extern asmlinkage long sys_kexec(unsigned long entry, long nr_segments,
+ struct kexec_segment *segments);
+extern struct page *kimage_alloc_control_pages(struct kimage *image, unsigned int order);
+extern struct kimage *kexec_image;
+#endif
+#endif /* LINUX_KEXEC_H */
--- /dev/null
+#ifndef _LINUX_KPROBES_H
+#define _LINUX_KPROBES_H
+/*
+ * Kernel Probes (KProbes)
+ * include/linux/kprobes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ *
+ * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
+ * Probes initial implementation ( includes suggestions from
+ * Rusty Russell).
+ * 2004-July Suparna Bhattacharya <suparna@in.ibm.com> added jumper probes
+ * interface to access function arguments.
+ */
+#include <linux/config.h>
+#include <linux/list.h>
+#include <linux/notifier.h>
+#include <linux/smp.h>
+#include <asm/kprobes.h>
+
+struct kprobe;
+struct pt_regs;
+typedef int (*kprobe_pre_handler_t) (struct kprobe *, struct pt_regs *);
+typedef int (*kprobe_break_handler_t) (struct kprobe *, struct pt_regs *);
+typedef void (*kprobe_post_handler_t) (struct kprobe *, struct pt_regs *,
+ unsigned long flags);
+typedef int (*kprobe_fault_handler_t) (struct kprobe *, struct pt_regs *,
+ int trapnr);
+struct kprobe {
+ struct hlist_node hlist;
+
+ /* location of the probe point */
+ kprobe_opcode_t *addr;
+
+ /* Called before addr is executed. */
+ kprobe_pre_handler_t pre_handler;
+
+ /* Called after addr is executed, unless... */
+ kprobe_post_handler_t post_handler;
+
+ /* ... called if executing addr causes a fault (eg. page fault).
+ * Return 1 if it handled fault, otherwise kernel will see it. */
+ kprobe_fault_handler_t fault_handler;
+
+ /* ... called if breakpoint trap occurs in probe handler.
+ * Return 1 if it handled break, otherwise kernel will see it. */
+ kprobe_break_handler_t break_handler;
+
+ /* Saved opcode (which has been replaced with breakpoint) */
+ kprobe_opcode_t opcode;
+
+ /* copy of the original instruction */
+ kprobe_opcode_t insn[MAX_INSN_SIZE];
+};
+
+/*
+ * Special probe type that uses setjmp-longjmp type tricks to resume
+ * execution at a specified entry with a matching prototype corresponding
+ * to the probed function - a trick to enable arguments to become
+ * accessible seamlessly by probe handling logic.
+ * Note:
+ * Because of the way compilers allocate stack space for local variables
+ * etc upfront, regardless of sub-scopes within a function, this mirroring
+ * principle currently works only for probes placed on function entry points.
+ */
+struct jprobe {
+ struct kprobe kp;
+ kprobe_opcode_t *entry; /* probe handling code to jump to */
+};
+
+#ifdef CONFIG_KPROBES
+/* Locks kprobe: irq must be disabled */
+void lock_kprobes(void);
+void unlock_kprobes(void);
+
+/* kprobe running now on this CPU? */
+static inline int kprobe_running(void)
+{
+ extern unsigned int kprobe_cpu;
+ return kprobe_cpu == smp_processor_id();
+}
+
+extern void arch_prepare_kprobe(struct kprobe *p);
+extern void show_registers(struct pt_regs *regs);
+
+/* Get the kprobe at this addr (if any). Must have called lock_kprobes */
+struct kprobe *get_kprobe(void *addr);
+
+int register_kprobe(struct kprobe *p);
+void unregister_kprobe(struct kprobe *p);
+int setjmp_pre_handler(struct kprobe *, struct pt_regs *);
+int longjmp_break_handler(struct kprobe *, struct pt_regs *);
+int register_jprobe(struct jprobe *p);
+void unregister_jprobe(struct jprobe *p);
+void jprobe_return(void);
+
+#else
+static inline int kprobe_running(void)
+{
+ return 0;
+}
+static inline int register_kprobe(struct kprobe *p)
+{
+ return -ENOSYS;
+}
+static inline void unregister_kprobe(struct kprobe *p)
+{
+}
+static inline int register_jprobe(struct jprobe *p)
+{
+ return -ENOSYS;
+}
+static inline void unregister_jprobe(struct jprobe *p)
+{
+}
+static inline void jprobe_return(void)
+{
+}
+#endif
+#endif /* _LINUX_KPROBES_H */
--- /dev/null
+/*
+ * linux/include/linux/mmc/card.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Card driver specific definitions.
+ */
+#ifndef LINUX_MMC_CARD_H
+#define LINUX_MMC_CARD_H
+
+#include <linux/mmc/mmc.h>
+
+struct mmc_cid {
+ unsigned int manfid;
+ char prod_name[8];
+ unsigned int serial;
+ unsigned short oemid;
+ unsigned short year;
+ unsigned char hwrev;
+ unsigned char fwrev;
+ unsigned char month;
+};
+
+struct mmc_csd {
+ unsigned char mmca_vsn;
+ unsigned short cmdclass;
+ unsigned short tacc_clks;
+ unsigned int tacc_ns;
+ unsigned int max_dtr;
+ unsigned int read_blkbits;
+ unsigned int capacity;
+};
+
+struct mmc_host;
+
+/*
+ * MMC device
+ */
+struct mmc_card {
+ struct list_head node; /* node in hosts devices list */
+ struct mmc_host *host; /* the host this device belongs to */
+ struct device dev; /* the device */
+ unsigned int rca; /* relative card address of device */
+ unsigned int state; /* (our) card state */
+#define MMC_STATE_PRESENT (1<<0) /* present in sysfs */
+#define MMC_STATE_DEAD (1<<1) /* device no longer in stack */
+#define MMC_STATE_BAD (1<<2) /* unrecognised device */
+ u32 raw_cid[4]; /* raw card CID */
+ u32 raw_csd[4]; /* raw card CSD */
+ struct mmc_cid cid; /* card identification */
+ struct mmc_csd csd; /* card specific */
+};
+
+#define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT)
+#define mmc_card_dead(c) ((c)->state & MMC_STATE_DEAD)
+#define mmc_card_bad(c) ((c)->state & MMC_STATE_BAD)
+
+#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT)
+#define mmc_card_set_dead(c) ((c)->state |= MMC_STATE_DEAD)
+#define mmc_card_set_bad(c) ((c)->state |= MMC_STATE_BAD)
+
+#define mmc_card_name(c) ((c)->cid.prod_name)
+#define mmc_card_id(c) ((c)->dev.bus_id)
+
+#define mmc_list_to_card(l) container_of(l, struct mmc_card, node)
+#define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev)
+#define mmc_set_drvdata(c,d) dev_set_drvdata(&(c)->dev, d)
+
+/*
+ * MMC device driver (e.g., Flash card, I/O card...)
+ */
+struct mmc_driver {
+ struct device_driver drv;
+ int (*probe)(struct mmc_card *);
+ void (*remove)(struct mmc_card *);
+ int (*suspend)(struct mmc_card *, u32);
+ int (*resume)(struct mmc_card *);
+};
+
+extern int mmc_register_driver(struct mmc_driver *);
+extern void mmc_unregister_driver(struct mmc_driver *);
+
+static inline int mmc_card_claim_host(struct mmc_card *card)
+{
+ return __mmc_claim_host(card->host, card);
+}
+
+#define mmc_card_release_host(c) mmc_release_host((c)->host)
+
+#endif
--- /dev/null
+/*
+ * linux/include/linux/mmc/host.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Host driver specific definitions.
+ */
+#ifndef LINUX_MMC_HOST_H
+#define LINUX_MMC_HOST_H
+
+#include <linux/mmc/mmc.h>
+
+struct mmc_ios {
+ unsigned int clock; /* clock rate */
+ unsigned short vdd;
+
+#define MMC_VDD_150 0
+#define MMC_VDD_155 1
+#define MMC_VDD_160 2
+#define MMC_VDD_165 3
+#define MMC_VDD_170 4
+#define MMC_VDD_180 5
+#define MMC_VDD_190 6
+#define MMC_VDD_200 7
+#define MMC_VDD_210 8
+#define MMC_VDD_220 9
+#define MMC_VDD_230 10
+#define MMC_VDD_240 11
+#define MMC_VDD_250 12
+#define MMC_VDD_260 13
+#define MMC_VDD_270 14
+#define MMC_VDD_280 15
+#define MMC_VDD_290 16
+#define MMC_VDD_300 17
+#define MMC_VDD_310 18
+#define MMC_VDD_320 19
+#define MMC_VDD_330 20
+#define MMC_VDD_340 21
+#define MMC_VDD_350 22
+#define MMC_VDD_360 23
+
+ unsigned char bus_mode; /* command output mode */
+
+#define MMC_BUSMODE_OPENDRAIN 1
+#define MMC_BUSMODE_PUSHPULL 2
+
+ unsigned char power_mode; /* power supply mode */
+
+#define MMC_POWER_OFF 0
+#define MMC_POWER_UP 1
+#define MMC_POWER_ON 2
+};
+
+struct mmc_host_ops {
+ void (*request)(struct mmc_host *host, struct mmc_request *req);
+ void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
+};
+
+struct mmc_card;
+struct device;
+
+struct mmc_host {
+ struct device *dev;
+ struct mmc_host_ops *ops;
+ unsigned int f_min;
+ unsigned int f_max;
+ u32 ocr_avail;
+ char host_name[8];
+
+ /* host specific block data */
+ unsigned int max_seg_size; /* see blk_queue_max_segment_size */
+ unsigned short max_hw_segs; /* see blk_queue_max_hw_segments */
+ unsigned short max_phys_segs; /* see blk_queue_max_phys_segments */
+ unsigned short max_sectors; /* see blk_queue_max_sectors */
+ unsigned short unused;
+
+ /* private data */
+ struct mmc_ios ios; /* current io bus settings */
+ u32 ocr; /* the current OCR setting */
+
+ struct list_head cards; /* devices attached to this host */
+
+ wait_queue_head_t wq;
+ spinlock_t lock; /* card_busy lock */
+ struct mmc_card *card_busy; /* the MMC card claiming host */
+ struct mmc_card *card_selected; /* the selected MMC card */
+
+ struct work_struct detect;
+};
+
+extern struct mmc_host *mmc_alloc_host(int extra, struct device *);
+extern int mmc_add_host(struct mmc_host *);
+extern void mmc_remove_host(struct mmc_host *);
+extern void mmc_free_host(struct mmc_host *);
+
+#define mmc_priv(x) ((void *)((x) + 1))
+#define mmc_dev(x) ((x)->dev)
+
+extern int mmc_suspend_host(struct mmc_host *, u32);
+extern int mmc_resume_host(struct mmc_host *);
+
+extern void mmc_detect_change(struct mmc_host *);
+extern void mmc_request_done(struct mmc_host *, struct mmc_request *);
+
+#endif
+
--- /dev/null
+/*
+ * linux/include/linux/mmc/mmc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef MMC_H
+#define MMC_H
+
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+
+struct request;
+struct mmc_data;
+struct mmc_request;
+
+struct mmc_command {
+ u32 opcode;
+ u32 arg;
+ u32 resp[4];
+ unsigned int flags; /* expected response type */
+#define MMC_RSP_NONE (0 << 0)
+#define MMC_RSP_SHORT (1 << 0)
+#define MMC_RSP_LONG (2 << 0)
+#define MMC_RSP_MASK (3 << 0)
+#define MMC_RSP_CRC (1 << 3) /* expect valid crc */
+#define MMC_RSP_BUSY (1 << 4) /* card may send busy */
+
+/*
+ * These are the response types, and correspond to valid bit
+ * patterns of the above flags. One additional valid pattern
+ * is all zeros, which means we don't expect a response.
+ */
+#define MMC_RSP_R1 (MMC_RSP_SHORT|MMC_RSP_CRC)
+#define MMC_RSP_R1B (MMC_RSP_SHORT|MMC_RSP_CRC|MMC_RSP_BUSY)
+#define MMC_RSP_R2 (MMC_RSP_LONG|MMC_RSP_CRC)
+#define MMC_RSP_R3 (MMC_RSP_SHORT)
+
+ unsigned int retries; /* max number of retries */
+ unsigned int error; /* command error */
+
+#define MMC_ERR_NONE 0
+#define MMC_ERR_TIMEOUT 1
+#define MMC_ERR_BADCRC 2
+#define MMC_ERR_FIFO 3
+#define MMC_ERR_FAILED 4
+#define MMC_ERR_INVALID 5
+
+ struct mmc_data *data; /* data segment associated with cmd */
+ struct mmc_request *mrq; /* assoicated request */
+};
+
+struct mmc_data {
+ unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */
+ unsigned int timeout_clks; /* data timeout (in clocks) */
+ unsigned int blksz_bits; /* data block size */
+ unsigned int blocks; /* number of blocks */
+ struct request *req; /* request structure */
+ unsigned int error; /* data error */
+ unsigned int flags;
+
+#define MMC_DATA_WRITE (1 << 8)
+#define MMC_DATA_READ (1 << 9)
+#define MMC_DATA_STREAM (1 << 10)
+
+ unsigned int bytes_xfered;
+
+ struct mmc_command *stop; /* stop command */
+ struct mmc_request *mrq; /* assoicated request */
+};
+
+struct mmc_request {
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+ struct mmc_command *stop;
+
+ void *done_data; /* completion data */
+ void (*done)(struct mmc_request *);/* completion function */
+};
+
+struct mmc_host;
+struct mmc_card;
+
+extern int mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
+extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
+
+extern int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card);
+
+static inline void mmc_claim_host(struct mmc_host *host)
+{
+ __mmc_claim_host(host, (struct mmc_card *)-1);
+}
+
+extern void mmc_release_host(struct mmc_host *host);
+
+#endif
--- /dev/null
+/*
+ * Header for MultiMediaCard (MMC)
+ *
+ * Copyright 2002 Hewlett-Packard Company
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Many thanks to Alessandro Rubini and Jonathan Corbet!
+ *
+ * Based strongly on code by:
+ *
+ * Author: Yong-iL Joh <tolkien@mizi.com>
+ * Date : $Date: 2002/06/18 12:37:30 $
+ *
+ * Author: Andrew Christian
+ * 15 May 2002
+ */
+
+#ifndef MMC_MMC_PROTOCOL_H
+#define MMC_MMC_PROTOCOL_H
+
+/* Standard MMC commands (3.1) type argument response */
+ /* class 1 */
+#define MMC_GO_IDLE_STATE 0 /* bc */
+#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
+#define MMC_ALL_SEND_CID 2 /* bcr R2 */
+#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
+#define MMC_SET_DSR 4 /* bc [31:16] RCA */
+#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
+#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
+#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
+#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
+#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
+#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
+#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
+
+ /* class 2 */
+#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
+#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
+#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
+
+ /* class 3 */
+#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
+
+ /* class 4 */
+#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
+#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
+#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
+#define MMC_PROGRAM_CID 26 /* adtc R1 */
+#define MMC_PROGRAM_CSD 27 /* adtc R1 */
+
+ /* class 6 */
+#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
+#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
+#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
+
+ /* class 5 */
+#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
+#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
+#define MMC_ERASE 37 /* ac R1b */
+
+ /* class 9 */
+#define MMC_FAST_IO 39 /* ac <Complex> R4 */
+#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
+
+ /* class 7 */
+#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
+
+ /* class 8 */
+#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
+#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
+
+/*
+ MMC status in R1
+ Type
+ e : error bit
+ s : status bit
+ r : detected and set for the actual command response
+ x : detected and set during command execution. the host must poll
+ the card by sending status command in order to read these bits.
+ Clear condition
+ a : according to the card state
+ b : always related to the previous command. Reception of
+ a valid command will clear it (with a delay of one command)
+ c : clear by read
+ */
+
+#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
+#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
+#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
+#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
+#define R1_ERASE_PARAM (1 << 27) /* ex, c */
+#define R1_WP_VIOLATION (1 << 26) /* erx, c */
+#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
+#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
+#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
+#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
+#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
+#define R1_CC_ERROR (1 << 20) /* erx, c */
+#define R1_ERROR (1 << 19) /* erx, c */
+#define R1_UNDERRUN (1 << 18) /* ex, c */
+#define R1_OVERRUN (1 << 17) /* ex, c */
+#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
+#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
+#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
+#define R1_ERASE_RESET (1 << 13) /* sr, c */
+#define R1_STATUS(x) (x & 0xFFFFE000)
+#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
+#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
+#define R1_APP_CMD (1 << 7) /* sr, c */
+
+/* These are unpacked versions of the actual responses */
+
+struct _mmc_csd {
+ u8 csd_structure;
+ u8 spec_vers;
+ u8 taac;
+ u8 nsac;
+ u8 tran_speed;
+ u16 ccc;
+ u8 read_bl_len;
+ u8 read_bl_partial;
+ u8 write_blk_misalign;
+ u8 read_blk_misalign;
+ u8 dsr_imp;
+ u16 c_size;
+ u8 vdd_r_curr_min;
+ u8 vdd_r_curr_max;
+ u8 vdd_w_curr_min;
+ u8 vdd_w_curr_max;
+ u8 c_size_mult;
+ union {
+ struct { /* MMC system specification version 3.1 */
+ u8 erase_grp_size;
+ u8 erase_grp_mult;
+ } v31;
+ struct { /* MMC system specification version 2.2 */
+ u8 sector_size;
+ u8 erase_grp_size;
+ } v22;
+ } erase;
+ u8 wp_grp_size;
+ u8 wp_grp_enable;
+ u8 default_ecc;
+ u8 r2w_factor;
+ u8 write_bl_len;
+ u8 write_bl_partial;
+ u8 file_format_grp;
+ u8 copy;
+ u8 perm_write_protect;
+ u8 tmp_write_protect;
+ u8 file_format;
+ u8 ecc;
+};
+
+#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
+#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
+#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
+#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
+#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
+#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
+#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
+#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
+#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
+#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
+
+
+/*
+ * CSD field definitions
+ */
+
+#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
+#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
+#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */
+
+#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
+#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
+#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
+#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */
+
+#endif /* MMC_MMC_PROTOCOL_H */
+
--- /dev/null
+/*
+ * Intel Multimedia Timer device interface
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * This file should define an interface compatible with the IA-PC Multimedia
+ * Timers Draft Specification (rev. 0.97) from Intel. Note that some
+ * hardware may not be able to safely export its registers to userspace,
+ * so the ioctl interface should support all necessary functionality.
+ *
+ * 11/01/01 - jbarnes - initial revision
+ * 9/10/04 - Christoph Lameter - remove interrupt support
+ * 9/17/04 - jbarnes - remove test program, move some #defines to the driver
+ */
+
+#ifndef _LINUX_MMTIMER_H
+#define _LINUX_MMTIMER_H
+
+/*
+ * Breakdown of the ioctl's available. An 'optional' next to the command
+ * indicates that supporting this command is optional, while 'required'
+ * commands must be implemented if conformance is desired.
+ *
+ * MMTIMER_GETOFFSET - optional
+ * Should return the offset (relative to the start of the page where the
+ * registers are mapped) for the counter in question.
+ *
+ * MMTIMER_GETRES - required
+ * The resolution of the clock in femto (10^-15) seconds
+ *
+ * MMTIMER_GETFREQ - required
+ * Frequency of the clock in Hz
+ *
+ * MMTIMER_GETBITS - required
+ * Number of bits in the clock's counter
+ *
+ * MMTIMER_MMAPAVAIL - required
+ * Returns nonzero if the registers can be mmap'd into userspace, 0 otherwise
+ *
+ * MMTIMER_GETCOUNTER - required
+ * Gets the current value in the counter
+ */
+#define MMTIMER_IOCTL_BASE 'm'
+
+#define MMTIMER_GETOFFSET _IO(MMTIMER_IOCTL_BASE, 0)
+#define MMTIMER_GETRES _IOR(MMTIMER_IOCTL_BASE, 1, unsigned long)
+#define MMTIMER_GETFREQ _IOR(MMTIMER_IOCTL_BASE, 2, unsigned long)
+#define MMTIMER_GETBITS _IO(MMTIMER_IOCTL_BASE, 4)
+#define MMTIMER_MMAPAVAIL _IO(MMTIMER_IOCTL_BASE, 6)
+#define MMTIMER_GETCOUNTER _IOR(MMTIMER_IOCTL_BASE, 9, unsigned long)
+
+#endif /* _LINUX_MMTIMER_H */
--- /dev/null
+/*
+ * mv64340.h - MV-64340 Internal registers definition file.
+ *
+ * Copyright 2002 Momentum Computer, Inc.
+ * Author: Matthew Dharm <mdharm@momenco.com>
+ * Copyright 2002 GALILEO TECHNOLOGY, LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_MV64340_H
+#define __ASM_MV64340_H
+
+#include <asm/addrspace.h>
+#include <asm/marvell.h>
+
+/****************************************/
+/* Processor Address Space */
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64340_CS_0_BASE_ADDR 0x008
+#define MV64340_CS_0_SIZE 0x010
+#define MV64340_CS_1_BASE_ADDR 0x208
+#define MV64340_CS_1_SIZE 0x210
+#define MV64340_CS_2_BASE_ADDR 0x018
+#define MV64340_CS_2_SIZE 0x020
+#define MV64340_CS_3_BASE_ADDR 0x218
+#define MV64340_CS_3_SIZE 0x220
+
+/* Devices BAR and size registers */
+
+#define MV64340_DEV_CS0_BASE_ADDR 0x028
+#define MV64340_DEV_CS0_SIZE 0x030
+#define MV64340_DEV_CS1_BASE_ADDR 0x228
+#define MV64340_DEV_CS1_SIZE 0x230
+#define MV64340_DEV_CS2_BASE_ADDR 0x248
+#define MV64340_DEV_CS2_SIZE 0x250
+#define MV64340_DEV_CS3_BASE_ADDR 0x038
+#define MV64340_DEV_CS3_SIZE 0x040
+#define MV64340_BOOTCS_BASE_ADDR 0x238
+#define MV64340_BOOTCS_SIZE 0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64340_PCI_0_IO_BASE_ADDR 0x048
+#define MV64340_PCI_0_IO_SIZE 0x050
+#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058
+#define MV64340_PCI_0_MEMORY0_SIZE 0x060
+#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080
+#define MV64340_PCI_0_MEMORY1_SIZE 0x088
+#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258
+#define MV64340_PCI_0_MEMORY2_SIZE 0x260
+#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280
+#define MV64340_PCI_0_MEMORY3_SIZE 0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64340_PCI_1_IO_BASE_ADDR 0x090
+#define MV64340_PCI_1_IO_SIZE 0x098
+#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0
+#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8
+#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0
+#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8
+#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0
+#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8
+#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0
+#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8
+
+/* SRAM base address */
+#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268
+
+/* internal registers space base address */
+#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+ windows above */
+#define MV64340_BASE_ADDR_ENABLE 0x278
+
+/****************************************/
+/* PCI remap registers */
+/****************************************/
+ /* PCI 0 */
+#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0
+#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
+#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
+#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
+#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
+#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
+#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
+#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
+#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
+ /* PCI 1 */
+#define MV64340_PCI_1_IO_ADDR_REMAP 0x108
+#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
+#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
+#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
+#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
+#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
+#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
+#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
+#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
+
+#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
+#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
+#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
+#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
+#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
+#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
+#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
+#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
+
+/****************************************/
+/* CPU Control Registers */
+/****************************************/
+
+#define MV64340_CPU_CONFIG 0x000
+#define MV64340_CPU_MODE 0x120
+#define MV64340_CPU_MASTER_CONTROL 0x160
+#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150
+#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158
+#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168
+
+/****************************************/
+/* SMP RegisterS */
+/****************************************/
+
+#define MV64340_SMP_WHO_AM_I 0x200
+#define MV64340_SMP_CPU0_DOORBELL 0x214
+#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C
+#define MV64340_SMP_CPU1_DOORBELL 0x224
+#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C
+#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234
+#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C
+#define MV64340_SMP_SEMAPHOR0 0x244
+#define MV64340_SMP_SEMAPHOR1 0x24c
+#define MV64340_SMP_SEMAPHOR2 0x254
+#define MV64340_SMP_SEMAPHOR3 0x25c
+#define MV64340_SMP_SEMAPHOR4 0x264
+#define MV64340_SMP_SEMAPHOR5 0x26c
+#define MV64340_SMP_SEMAPHOR6 0x274
+#define MV64340_SMP_SEMAPHOR7 0x27c
+
+/****************************************/
+/* CPU Sync Barrier Register */
+/****************************************/
+
+#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
+#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
+#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
+#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
+
+/****************************************/
+/* CPU Access Protect */
+/****************************************/
+
+#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
+#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188
+#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
+#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198
+#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
+#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
+#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
+#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
+
+
+/****************************************/
+/* CPU Error Report */
+/****************************************/
+
+#define MV64340_CPU_ERROR_ADDR_LOW 0x070
+#define MV64340_CPU_ERROR_ADDR_HIGH 0x078
+#define MV64340_CPU_ERROR_DATA_LOW 0x128
+#define MV64340_CPU_ERROR_DATA_HIGH 0x130
+#define MV64340_CPU_ERROR_PARITY 0x138
+#define MV64340_CPU_ERROR_CAUSE 0x140
+#define MV64340_CPU_ERROR_MASK 0x148
+
+/****************************************/
+/* CPU Interface Debug Registers */
+/****************************************/
+
+#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360
+#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368
+#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370
+#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378
+#define MV64340_PUNIT_MMASK 0x3e4
+
+/****************************************/
+/* Integrated SRAM Registers */
+/****************************************/
+
+#define MV64340_SRAM_CONFIG 0x380
+#define MV64340_SRAM_TEST_MODE 0X3F4
+#define MV64340_SRAM_ERROR_CAUSE 0x388
+#define MV64340_SRAM_ERROR_ADDR 0x390
+#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8
+#define MV64340_SRAM_ERROR_DATA_LOW 0x398
+#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0
+#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8
+
+/****************************************/
+/* SDRAM Configuration */
+/****************************************/
+
+#define MV64340_SDRAM_CONFIG 0x1400
+#define MV64340_D_UNIT_CONTROL_LOW 0x1404
+#define MV64340_D_UNIT_CONTROL_HIGH 0x1424
+#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408
+#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c
+#define MV64340_SDRAM_ADDR_CONTROL 0x1410
+#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414
+#define MV64340_SDRAM_OPERATION 0x1418
+#define MV64340_SDRAM_MODE 0x141c
+#define MV64340_EXTENDED_DRAM_MODE 0x1420
+#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
+#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
+#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438
+#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
+#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4
+
+/****************************************/
+/* SDRAM Error Report */
+/****************************************/
+
+#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444
+#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440
+#define MV64340_SDRAM_ERROR_ADDR 0x1450
+#define MV64340_SDRAM_RECEIVED_ECC 0x1448
+#define MV64340_SDRAM_CALCULATED_ECC 0x144c
+#define MV64340_SDRAM_ECC_CONTROL 0x1454
+#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458
+
+/******************************************/
+/* Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64340_DFCDL_CONFIG0 0x1480
+#define MV64340_DFCDL_CONFIG1 0x1484
+#define MV64340_DLL_WRITE 0x1488
+#define MV64340_DLL_READ 0x148c
+#define MV64340_SRAM_ADDR 0x1490
+#define MV64340_SRAM_DATA0 0x1494
+#define MV64340_SRAM_DATA1 0x1498
+#define MV64340_SRAM_DATA2 0x149c
+#define MV64340_DFCL_PROBE 0x14a0
+
+/******************************************/
+/* Debug Registers */
+/******************************************/
+
+#define MV64340_DUNIT_DEBUG_LOW 0x1460
+#define MV64340_DUNIT_DEBUG_HIGH 0x1464
+#define MV64340_DUNIT_MMASK 0X1b40
+
+/****************************************/
+/* Device Parameters */
+/****************************************/
+
+#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c
+#define MV64340_DEVICE_BANK1_PARAMETERS 0x460
+#define MV64340_DEVICE_BANK2_PARAMETERS 0x464
+#define MV64340_DEVICE_BANK3_PARAMETERS 0x468
+#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c
+#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0
+#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
+#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
+#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
+
+/****************************************/
+/* Device interrupt registers */
+/****************************************/
+
+#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0
+#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4
+#define MV64340_DEVICE_ERROR_ADDR 0x4d8
+#define MV64340_DEVICE_ERROR_DATA 0x4dc
+#define MV64340_DEVICE_ERROR_PARITY 0x4e0
+
+/****************************************/
+/* Device debug registers */
+/****************************************/
+
+#define MV64340_DEVICE_DEBUG_LOW 0x4e4
+#define MV64340_DEVICE_DEBUG_HIGH 0x4e8
+#define MV64340_RUNIT_MMASK 0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08
+#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88
+#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08
+#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88
+#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c
+#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c
+#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c
+#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c
+#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10
+#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90
+#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10
+#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90
+#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18
+#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98
+#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14
+#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94
+#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
+#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
+#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
+#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
+#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
+#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
+#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24
+#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4
+#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28
+#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8
+#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
+#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
+#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
+#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
+#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
+#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
+#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
+#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
+#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
+#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
+#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
+#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
+#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
+#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
+#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
+#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
+#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
+#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
+#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
+#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
+#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
+#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
+#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
+#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
+#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
+#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
+#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
+#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
+#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
+#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
+#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
+#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
+#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
+#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
+#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
+#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
+#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
+#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
+#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
+#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
+#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
+#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
+#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
+#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
+#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
+#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
+#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
+#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
+#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
+#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
+#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c
+#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc
+#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
+#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
+#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44
+#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4
+#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48
+#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
+
+/***********************************/
+/* PCI Control Register Map */
+/***********************************/
+
+#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
+#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
+#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
+#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
+#define MV64340_PCI_0_COMMAND 0xc00
+#define MV64340_PCI_1_COMMAND 0xc80
+#define MV64340_PCI_0_MODE 0xd00
+#define MV64340_PCI_1_MODE 0xd80
+#define MV64340_PCI_0_RETRY 0xc04
+#define MV64340_PCI_1_RETRY 0xc84
+#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
+#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
+#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38
+#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8
+#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00
+#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80
+#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
+#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
+#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
+#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
+#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
+#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
+#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
+#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
+#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
+#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
+#define MV64340_PCI_0_P2P_CONFIG 0x1d14
+#define MV64340_PCI_1_P2P_CONFIG 0x1d94
+
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
+
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
+
+/****************************************/
+/* PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64340_PCI_0_CONFIG_ADDR 0xcf8
+#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
+#define MV64340_PCI_1_CONFIG_ADDR 0xc78
+#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
+#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
+#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
+
+/****************************************/
+/* PCI Error Report Registers */
+/****************************************/
+
+#define MV64340_PCI_0_SERR_MASK 0xc28
+#define MV64340_PCI_1_SERR_MASK 0xca8
+#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40
+#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0
+#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44
+#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4
+#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48
+#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8
+#define MV64340_PCI_0_ERROR_COMMAND 0x1d50
+#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0
+#define MV64340_PCI_0_ERROR_CAUSE 0x1d58
+#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8
+#define MV64340_PCI_0_ERROR_MASK 0x1d5c
+#define MV64340_PCI_1_ERROR_MASK 0x1ddc
+
+/****************************************/
+/* PCI Debug Registers */
+/****************************************/
+
+#define MV64340_PCI_0_MMASK 0X1D24
+#define MV64340_PCI_1_MMASK 0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers */
+/*********************************************/
+
+#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000
+#define MV64340_PCI_STATUS_AND_COMMAND 0x004
+#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
+
+#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010
+#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014
+#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018
+#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
+#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
+#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
+#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
+#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
+#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034
+#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C
+ /* capability list */
+#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
+#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
+#define MV64340_PCI_VPD_ADDR 0x048
+#define MV64340_PCI_VPD_DATA 0x04c
+#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050
+#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054
+#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
+#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c
+#define MV64340_PCI_X_COMMAND 0x060
+#define MV64340_PCI_X_STATUS 0x064
+#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068
+
+/***********************************************/
+/* PCI Configuration, Function 1, Registers */
+/***********************************************/
+
+#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110
+#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114
+#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118
+#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
+#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
+#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
+
+/***********************************************/
+/* PCI Configuration, Function 2, Registers */
+/***********************************************/
+
+#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
+#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
+#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
+#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
+#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
+#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
+
+/***********************************************/
+/* PCI Configuration, Function 3, Registers */
+/***********************************************/
+
+#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
+#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
+#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
+#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
+#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220
+#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224
+
+/***********************************************/
+/* PCI Configuration, Function 4, Registers */
+/***********************************************/
+
+#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
+#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
+#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
+#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
+#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420
+#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20) */
+/****************************************/
+
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
+#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
+
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
+#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
+
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
+#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
+#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
+
+/****************************************/
+/* Ethernet Unit Registers */
+/****************************************/
+
+#define MV64340_ETH_PHY_ADDR_REG 0x2000
+#define MV64340_ETH_SMI_REG 0x2004
+#define MV64340_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
+#define MV64340_ETH_UNIT_DEFAULTID_REG 0x200c
+#define MV64340_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
+#define MV64340_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
+#define MV64340_ETH_UNIT_INTERNAL_USE_REG 0x24fc
+#define MV64340_ETH_UNIT_ERROR_ADDR_REG 0x2094
+#define MV64340_ETH_BAR_0 0x2200
+#define MV64340_ETH_BAR_1 0x2208
+#define MV64340_ETH_BAR_2 0x2210
+#define MV64340_ETH_BAR_3 0x2218
+#define MV64340_ETH_BAR_4 0x2220
+#define MV64340_ETH_BAR_5 0x2228
+#define MV64340_ETH_SIZE_REG_0 0x2204
+#define MV64340_ETH_SIZE_REG_1 0x220c
+#define MV64340_ETH_SIZE_REG_2 0x2214
+#define MV64340_ETH_SIZE_REG_3 0x221c
+#define MV64340_ETH_SIZE_REG_4 0x2224
+#define MV64340_ETH_SIZE_REG_5 0x222c
+#define MV64340_ETH_HEADERS_RETARGET_BASE_REG 0x2230
+#define MV64340_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
+#define MV64340_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
+#define MV64340_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
+#define MV64340_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
+#define MV64340_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
+#define MV64340_ETH_BASE_ADDR_ENABLE_REG 0x2290
+#define MV64340_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
+#define MV64340_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
+#define MV64340_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
+#define MV64340_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
+#define MV64340_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
+#define MV64340_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
+#define MV64340_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
+#define MV64340_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
+#define MV64340_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
+#define MV64340_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
+#define MV64340_ETH_DSCP_0(port) (0x2420 + (port<<10))
+#define MV64340_ETH_DSCP_1(port) (0x2424 + (port<<10))
+#define MV64340_ETH_DSCP_2(port) (0x2428 + (port<<10))
+#define MV64340_ETH_DSCP_3(port) (0x242c + (port<<10))
+#define MV64340_ETH_DSCP_4(port) (0x2430 + (port<<10))
+#define MV64340_ETH_DSCP_5(port) (0x2434 + (port<<10))
+#define MV64340_ETH_DSCP_6(port) (0x2438 + (port<<10))
+#define MV64340_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
+#define MV64340_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
+#define MV64340_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
+#define MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
+#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
+#define MV64340_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
+#define MV64340_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
+#define MV64340_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
+#define MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
+#define MV64340_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
+#define MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
+#define MV64340_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
+#define MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
+#define MV64340_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
+#define MV64340_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
+#define MV64340_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
+#define MV64340_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
+#define MV64340_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
+#define MV64340_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
+#define MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
+#define MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
+#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
+#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
+#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
+#define MV64340_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
+#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
+#define MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
+#define MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
+#define MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
+
+/*******************************************/
+/* CUNIT Registers */
+/*******************************************/
+
+ /* Address Decoding Register Map */
+
+#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200
+#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208
+#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210
+#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218
+#define MV64340_CUNIT_SIZE0 0xf204
+#define MV64340_CUNIT_SIZE1 0xf20c
+#define MV64340_CUNIT_SIZE2 0xf214
+#define MV64340_CUNIT_SIZE3 0xf21c
+#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
+#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
+#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
+#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254
+#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258
+#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
+
+ /* Error Report Registers */
+
+#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310
+#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314
+#define MV64340_CUNIT_ERROR_ADDR 0xf318
+
+ /* Cunit Control Registers */
+
+#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300
+#define MV64340_CUNIT_CONFIG_REG 0xb40c
+#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
+
+ /* Cunit Debug Registers */
+
+#define MV64340_CUNIT_DEBUG_LOW 0xf340
+#define MV64340_CUNIT_DEBUG_HIGH 0xf344
+#define MV64340_CUNIT_MMASK 0xf380
+
+ /* MPSCs Clocks Routing Registers */
+
+#define MV64340_MPSC_ROUTING_REG 0xb400
+#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404
+#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408
+
+ /* MPSCs Interrupts Registers */
+
+#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
+#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3))
+
+#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
+#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
+#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
+#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
+
+ /* MPSC0 Registers */
+
+
+/***************************************/
+/* SDMA Registers */
+/***************************************/
+
+#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
+#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
+#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
+#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
+#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
+
+#define MV64340_SDMA_CAUSE_REG 0xb800
+#define MV64340_SDMA_MASK_REG 0xb880
+
+/* BRG Interrupts */
+
+#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
+#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
+#define MV64340_BRG_CAUSE_REG 0xb834
+#define MV64340_BRG_MASK_REG 0xb8b4
+
+/****************************************/
+/* DMA Channel Control */
+/****************************************/
+
+#define MV64340_DMA_CHANNEL0_CONTROL 0x840
+#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880
+#define MV64340_DMA_CHANNEL1_CONTROL 0x844
+#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884
+#define MV64340_DMA_CHANNEL2_CONTROL 0x848
+#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888
+#define MV64340_DMA_CHANNEL3_CONTROL 0x84C
+#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C
+
+
+/****************************************/
+/* IDMA Registers */
+/****************************************/
+
+#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800
+#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804
+#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808
+#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C
+#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810
+#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814
+#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818
+#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c
+#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820
+#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824
+#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828
+#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
+#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
+#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
+#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
+#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
+#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
+#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
+#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
+#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
+
+ /* IDMA Address Decoding Base Address Registers */
+
+#define MV64340_DMA_BASE_ADDR_REG0 0xa00
+#define MV64340_DMA_BASE_ADDR_REG1 0xa08
+#define MV64340_DMA_BASE_ADDR_REG2 0xa10
+#define MV64340_DMA_BASE_ADDR_REG3 0xa18
+#define MV64340_DMA_BASE_ADDR_REG4 0xa20
+#define MV64340_DMA_BASE_ADDR_REG5 0xa28
+#define MV64340_DMA_BASE_ADDR_REG6 0xa30
+#define MV64340_DMA_BASE_ADDR_REG7 0xa38
+
+ /* IDMA Address Decoding Size Address Register */
+
+#define MV64340_DMA_SIZE_REG0 0xa04
+#define MV64340_DMA_SIZE_REG1 0xa0c
+#define MV64340_DMA_SIZE_REG2 0xa14
+#define MV64340_DMA_SIZE_REG3 0xa1c
+#define MV64340_DMA_SIZE_REG4 0xa24
+#define MV64340_DMA_SIZE_REG5 0xa2c
+#define MV64340_DMA_SIZE_REG6 0xa34
+#define MV64340_DMA_SIZE_REG7 0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+ Protection Registers */
+
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
+#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80
+#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
+#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
+#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
+#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
+#define MV64340_DMA_ARBITER_CONTROL 0x860
+#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0
+
+ /* IDMA Headers Retarget Registers */
+
+#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84
+#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88
+
+ /* IDMA Interrupt Register */
+
+#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0
+#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4
+#define MV64340_DMA_ERROR_ADDR 0x8c8
+#define MV64340_DMA_ERROR_SELECT 0x8cc
+
+ /* IDMA Debug Register ( for internal use ) */
+
+#define MV64340_DMA_DEBUG_LOW 0x8e0
+#define MV64340_DMA_DEBUG_HIGH 0x8e4
+#define MV64340_DMA_SPARE 0xA8C
+
+/****************************************/
+/* Timer_Counter */
+/****************************************/
+
+#define MV64340_TIMER_COUNTER0 0x850
+#define MV64340_TIMER_COUNTER1 0x854
+#define MV64340_TIMER_COUNTER2 0x858
+#define MV64340_TIMER_COUNTER3 0x85C
+#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864
+#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
+#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
+
+/****************************************/
+/* Watchdog registers */
+/****************************************/
+
+#define MV64340_WATCHDOG_CONFIG_REG 0xb410
+#define MV64340_WATCHDOG_VALUE_REG 0xb414
+
+/****************************************/
+/* I2C Registers */
+/****************************************/
+
+#define MV64340_I2C_SLAVE_ADDR 0xc000
+#define MV64340_I2C_EXTENDED_SLAVE_ADDR 0xc010
+#define MV64340_I2C_DATA 0xc004
+#define MV64340_I2C_CONTROL 0xc008
+#define MV64340_I2C_STATUS_BAUDE_RATE 0xc00C
+#define MV64340_I2C_SOFT_RESET 0xc01c
+
+/****************************************/
+/* GPP Interface Registers */
+/****************************************/
+
+#define MV64340_GPP_IO_CONTROL 0xf100
+#define MV64340_GPP_LEVEL_CONTROL 0xf110
+#define MV64340_GPP_VALUE 0xf104
+#define MV64340_GPP_INTERRUPT_CAUSE 0xf108
+#define MV64340_GPP_INTERRUPT_MASK0 0xf10c
+#define MV64340_GPP_INTERRUPT_MASK1 0xf114
+#define MV64340_GPP_VALUE_SET 0xf118
+#define MV64340_GPP_VALUE_CLEAR 0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers */
+/****************************************/
+
+/****************************************/
+/* Interrupts */
+/****************************************/
+
+#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004
+#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
+#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014
+#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c
+#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024
+#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034
+#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c
+#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044
+#define MV64340_INTERRUPT0_MASK_0_LOW 0x054
+#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c
+#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064
+#define MV64340_INTERRUPT1_MASK_0_LOW 0x074
+#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c
+#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084
+
+/****************************************/
+/* MPP Interface Registers */
+/****************************************/
+
+#define MV64340_MPP_CONTROL0 0xf000
+#define MV64340_MPP_CONTROL1 0xf004
+#define MV64340_MPP_CONTROL2 0xf008
+#define MV64340_MPP_CONTROL3 0xf00c
+
+/****************************************/
+/* Serial Initialization registers */
+/****************************************/
+
+#define MV64340_SERIAL_INIT_LAST_DATA 0xf324
+#define MV64340_SERIAL_INIT_CONTROL 0xf328
+#define MV64340_SERIAL_INIT_STATUS 0xf32c
+
+extern void mv64340_irq_init(unsigned int base);
+
+#endif /* __ASM_MV64340_H */
--- /dev/null
+/* PPTP constants and structs */
+#ifndef _CONNTRACK_PPTP_H
+#define _CONNTRACK_PPTP_H
+
+/* state of the control session */
+enum pptp_ctrlsess_state {
+ PPTP_SESSION_NONE, /* no session present */
+ PPTP_SESSION_ERROR, /* some session error */
+ PPTP_SESSION_STOPREQ, /* stop_sess request seen */
+ PPTP_SESSION_REQUESTED, /* start_sess request seen */
+ PPTP_SESSION_CONFIRMED, /* session established */
+};
+
+/* state of the call inside the control session */
+enum pptp_ctrlcall_state {
+ PPTP_CALL_NONE,
+ PPTP_CALL_ERROR,
+ PPTP_CALL_OUT_REQ,
+ PPTP_CALL_OUT_CONF,
+ PPTP_CALL_IN_REQ,
+ PPTP_CALL_IN_REP,
+ PPTP_CALL_IN_CONF,
+ PPTP_CALL_CLEAR_REQ,
+};
+
+
+/* conntrack private data */
+struct ip_ct_pptp_master {
+ enum pptp_ctrlsess_state sstate; /* session state */
+
+ /* everything below is going to be per-expectation in newnat,
+ * since there could be more than one call within one session */
+ enum pptp_ctrlcall_state cstate; /* call state */
+ u_int16_t pac_call_id; /* call id of PAC, host byte order */
+ u_int16_t pns_call_id; /* call id of PNS, host byte order */
+};
+
+/* conntrack_expect private member */
+struct ip_ct_pptp_expect {
+ enum pptp_ctrlcall_state cstate; /* call state */
+ u_int16_t pac_call_id; /* call id of PAC */
+ u_int16_t pns_call_id; /* call id of PNS */
+};
+
+
+#ifdef __KERNEL__
+
+#include <linux/netfilter_ipv4/lockhelp.h>
+DECLARE_LOCK_EXTERN(ip_pptp_lock);
+
+#define IP_CONNTR_PPTP PPTP_CONTROL_PORT
+
+#define PPTP_CONTROL_PORT 1723
+
+#define PPTP_PACKET_CONTROL 1
+#define PPTP_PACKET_MGMT 2
+
+#define PPTP_MAGIC_COOKIE 0x1a2b3c4d
+
+struct pptp_pkt_hdr {
+ __u16 packetLength;
+ __u16 packetType;
+ __u32 magicCookie;
+};
+
+/* PptpControlMessageType values */
+#define PPTP_START_SESSION_REQUEST 1
+#define PPTP_START_SESSION_REPLY 2
+#define PPTP_STOP_SESSION_REQUEST 3
+#define PPTP_STOP_SESSION_REPLY 4
+#define PPTP_ECHO_REQUEST 5
+#define PPTP_ECHO_REPLY 6
+#define PPTP_OUT_CALL_REQUEST 7
+#define PPTP_OUT_CALL_REPLY 8
+#define PPTP_IN_CALL_REQUEST 9
+#define PPTP_IN_CALL_REPLY 10
+#define PPTP_IN_CALL_CONNECT 11
+#define PPTP_CALL_CLEAR_REQUEST 12
+#define PPTP_CALL_DISCONNECT_NOTIFY 13
+#define PPTP_WAN_ERROR_NOTIFY 14
+#define PPTP_SET_LINK_INFO 15
+
+#define PPTP_MSG_MAX 15
+
+/* PptpGeneralError values */
+#define PPTP_ERROR_CODE_NONE 0
+#define PPTP_NOT_CONNECTED 1
+#define PPTP_BAD_FORMAT 2
+#define PPTP_BAD_VALUE 3
+#define PPTP_NO_RESOURCE 4
+#define PPTP_BAD_CALLID 5
+#define PPTP_REMOVE_DEVICE_ERROR 6
+
+struct PptpControlHeader {
+ __u16 messageType;
+ __u16 reserved;
+};
+
+/* FramingCapability Bitmap Values */
+#define PPTP_FRAME_CAP_ASYNC 0x1
+#define PPTP_FRAME_CAP_SYNC 0x2
+
+/* BearerCapability Bitmap Values */
+#define PPTP_BEARER_CAP_ANALOG 0x1
+#define PPTP_BEARER_CAP_DIGITAL 0x2
+
+struct PptpStartSessionRequest {
+ __u16 protocolVersion;
+ __u8 reserved1;
+ __u8 reserved2;
+ __u32 framingCapability;
+ __u32 bearerCapability;
+ __u16 maxChannels;
+ __u16 firmwareRevision;
+ __u8 hostName[64];
+ __u8 vendorString[64];
+};
+
+/* PptpStartSessionResultCode Values */
+#define PPTP_START_OK 1
+#define PPTP_START_GENERAL_ERROR 2
+#define PPTP_START_ALREADY_CONNECTED 3
+#define PPTP_START_NOT_AUTHORIZED 4
+#define PPTP_START_UNKNOWN_PROTOCOL 5
+
+struct PptpStartSessionReply {
+ __u16 protocolVersion;
+ __u8 resultCode;
+ __u8 generalErrorCode;
+ __u32 framingCapability;
+ __u32 bearerCapability;
+ __u16 maxChannels;
+ __u16 firmwareRevision;
+ __u8 hostName[64];
+ __u8 vendorString[64];
+};
+
+/* PptpStopReasons */
+#define PPTP_STOP_NONE 1
+#define PPTP_STOP_PROTOCOL 2
+#define PPTP_STOP_LOCAL_SHUTDOWN 3
+
+struct PptpStopSessionRequest {
+ __u8 reason;
+};
+
+/* PptpStopSessionResultCode */
+#define PPTP_STOP_OK 1
+#define PPTP_STOP_GENERAL_ERROR 2
+
+struct PptpStopSessionReply {
+ __u8 resultCode;
+ __u8 generalErrorCode;
+};
+
+struct PptpEchoRequest {
+ __u32 identNumber;
+};
+
+/* PptpEchoReplyResultCode */
+#define PPTP_ECHO_OK 1
+#define PPTP_ECHO_GENERAL_ERROR 2
+
+struct PptpEchoReply {
+ __u32 identNumber;
+ __u8 resultCode;
+ __u8 generalErrorCode;
+ __u16 reserved;
+};
+
+/* PptpFramingType */
+#define PPTP_ASYNC_FRAMING 1
+#define PPTP_SYNC_FRAMING 2
+#define PPTP_DONT_CARE_FRAMING 3
+
+/* PptpCallBearerType */
+#define PPTP_ANALOG_TYPE 1
+#define PPTP_DIGITAL_TYPE 2
+#define PPTP_DONT_CARE_BEARER_TYPE 3
+
+struct PptpOutCallRequest {
+ __u16 callID;
+ __u16 callSerialNumber;
+ __u32 minBPS;
+ __u32 maxBPS;
+ __u32 bearerType;
+ __u32 framingType;
+ __u16 packetWindow;
+ __u16 packetProcDelay;
+ __u16 reserved1;
+ __u16 phoneNumberLength;
+ __u16 reserved2;
+ __u8 phoneNumber[64];
+ __u8 subAddress[64];
+};
+
+/* PptpCallResultCode */
+#define PPTP_OUTCALL_CONNECT 1
+#define PPTP_OUTCALL_GENERAL_ERROR 2
+#define PPTP_OUTCALL_NO_CARRIER 3
+#define PPTP_OUTCALL_BUSY 4
+#define PPTP_OUTCALL_NO_DIAL_TONE 5
+#define PPTP_OUTCALL_TIMEOUT 6
+#define PPTP_OUTCALL_DONT_ACCEPT 7
+
+struct PptpOutCallReply {
+ __u16 callID;
+ __u16 peersCallID;
+ __u8 resultCode;
+ __u8 generalErrorCode;
+ __u16 causeCode;
+ __u32 connectSpeed;
+ __u16 packetWindow;
+ __u16 packetProcDelay;
+ __u32 physChannelID;
+};
+
+struct PptpInCallRequest {
+ __u16 callID;
+ __u16 callSerialNumber;
+ __u32 callBearerType;
+ __u32 physChannelID;
+ __u16 dialedNumberLength;
+ __u16 dialingNumberLength;
+ __u8 dialedNumber[64];
+ __u8 dialingNumber[64];
+ __u8 subAddress[64];
+};
+
+/* PptpInCallResultCode */
+#define PPTP_INCALL_ACCEPT 1
+#define PPTP_INCALL_GENERAL_ERROR 2
+#define PPTP_INCALL_DONT_ACCEPT 3
+
+struct PptpInCallReply {
+ __u16 callID;
+ __u16 peersCallID;
+ __u8 resultCode;
+ __u8 generalErrorCode;
+ __u16 packetWindow;
+ __u16 packetProcDelay;
+ __u16 reserved;
+};
+
+struct PptpInCallConnected {
+ __u16 peersCallID;
+ __u16 reserved;
+ __u32 connectSpeed;
+ __u16 packetWindow;
+ __u16 packetProcDelay;
+ __u32 callFramingType;
+};
+
+struct PptpClearCallRequest {
+ __u16 callID;
+ __u16 reserved;
+};
+
+struct PptpCallDisconnectNotify {
+ __u16 callID;
+ __u8 resultCode;
+ __u8 generalErrorCode;
+ __u16 causeCode;
+ __u16 reserved;
+ __u8 callStatistics[128];
+};
+
+struct PptpWanErrorNotify {
+ __u16 peersCallID;
+ __u16 reserved;
+ __u32 crcErrors;
+ __u32 framingErrors;
+ __u32 hardwareOverRuns;
+ __u32 bufferOverRuns;
+ __u32 timeoutErrors;
+ __u32 alignmentErrors;
+};
+
+struct PptpSetLinkInfo {
+ __u16 peersCallID;
+ __u16 reserved;
+ __u32 sendAccm;
+ __u32 recvAccm;
+};
+
+
+struct pptp_priv_data {
+ __u16 call_id;
+ __u16 mcall_id;
+ __u16 pcall_id;
+};
+
+union pptp_ctrl_union {
+ struct PptpStartSessionRequest sreq;
+ struct PptpStartSessionReply srep;
+ struct PptpStopSessionRequest streq;
+ struct PptpStopSessionReply strep;
+ struct PptpOutCallRequest ocreq;
+ struct PptpOutCallReply ocack;
+ struct PptpInCallRequest icreq;
+ struct PptpInCallReply icack;
+ struct PptpInCallConnected iccon;
+ struct PptpClearCallRequest clrreq;
+ struct PptpCallDisconnectNotify disc;
+ struct PptpWanErrorNotify wanerr;
+ struct PptpSetLinkInfo setlink;
+};
+
+#endif /* __KERNEL__ */
+#endif /* _CONNTRACK_PPTP_H */
--- /dev/null
+#ifndef _CONNTRACK_PROTO_GRE_H
+#define _CONNTRACK_PROTO_GRE_H
+#include <asm/byteorder.h>
+
+/* GRE PROTOCOL HEADER */
+
+/* GRE Version field */
+#define GRE_VERSION_1701 0x0
+#define GRE_VERSION_PPTP 0x1
+
+/* GRE Protocol field */
+#define GRE_PROTOCOL_PPTP 0x880B
+
+/* GRE Flags */
+#define GRE_FLAG_C 0x80
+#define GRE_FLAG_R 0x40
+#define GRE_FLAG_K 0x20
+#define GRE_FLAG_S 0x10
+#define GRE_FLAG_A 0x80
+
+#define GRE_IS_C(f) ((f)&GRE_FLAG_C)
+#define GRE_IS_R(f) ((f)&GRE_FLAG_R)
+#define GRE_IS_K(f) ((f)&GRE_FLAG_K)
+#define GRE_IS_S(f) ((f)&GRE_FLAG_S)
+#define GRE_IS_A(f) ((f)&GRE_FLAG_A)
+
+/* GRE is a mess: Four different standards */
+struct gre_hdr {
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+ __u16 rec:3,
+ srr:1,
+ seq:1,
+ key:1,
+ routing:1,
+ csum:1,
+ version:3,
+ reserved:4,
+ ack:1;
+#elif defined(__BIG_ENDIAN_BITFIELD)
+ __u16 csum:1,
+ routing:1,
+ key:1,
+ seq:1,
+ srr:1,
+ rec:3,
+ ack:1,
+ reserved:4,
+ version:3;
+#else
+#error "Adjust your <asm/byteorder.h> defines"
+#endif
+ __u16 protocol;
+};
+
+/* modified GRE header for PPTP */
+struct gre_hdr_pptp {
+ __u8 flags; /* bitfield */
+ __u8 version; /* should be GRE_VERSION_PPTP */
+ __u16 protocol; /* should be GRE_PROTOCOL_PPTP */
+ __u16 payload_len; /* size of ppp payload, not inc. gre header */
+ __u16 call_id; /* peer's call_id for this session */
+ __u32 seq; /* sequence number. Present if S==1 */
+ __u32 ack; /* seq number of highest packet recieved by */
+ /* sender in this session */
+};
+
+
+/* this is part of ip_conntrack */
+struct ip_ct_gre {
+ unsigned int stream_timeout;
+ unsigned int timeout;
+};
+
+/* this is part of ip_conntrack_expect */
+struct ip_ct_gre_expect {
+ struct ip_ct_gre_keymap *keymap_orig, *keymap_reply;
+};
+
+#ifdef __KERNEL__
+struct ip_conntrack_expect;
+
+/* structure for original <-> reply keymap */
+struct ip_ct_gre_keymap {
+ struct list_head list;
+
+ struct ip_conntrack_tuple tuple;
+};
+
+
+/* add new tuple->key_reply pair to keymap */
+int ip_ct_gre_keymap_add(struct ip_conntrack_expect *exp,
+ struct ip_conntrack_tuple *t,
+ int reply);
+
+/* change an existing keymap entry */
+void ip_ct_gre_keymap_change(struct ip_ct_gre_keymap *km,
+ struct ip_conntrack_tuple *t);
+
+/* delete keymap entries */
+void ip_ct_gre_keymap_destroy(struct ip_conntrack_expect *exp);
+
+
+/* get pointer to gre key, if present */
+static inline u_int32_t *gre_key(struct gre_hdr *greh)
+{
+ if (!greh->key)
+ return NULL;
+ if (greh->csum || greh->routing)
+ return (u_int32_t *) (greh+sizeof(*greh)+4);
+ return (u_int32_t *) (greh+sizeof(*greh));
+}
+
+/* get pointer ot gre csum, if present */
+static inline u_int16_t *gre_csum(struct gre_hdr *greh)
+{
+ if (!greh->csum)
+ return NULL;
+ return (u_int16_t *) (greh+sizeof(*greh));
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _CONNTRACK_PROTO_GRE_H */
--- /dev/null
+#ifndef _IP_CONNTRACK_SCTP_H
+#define _IP_CONNTRACK_SCTP_H
+/* SCTP tracking. */
+
+enum sctp_conntrack {
+ SCTP_CONNTRACK_NONE,
+ SCTP_CONNTRACK_CLOSED,
+ SCTP_CONNTRACK_COOKIE_WAIT,
+ SCTP_CONNTRACK_COOKIE_ECHOED,
+ SCTP_CONNTRACK_ESTABLISHED,
+ SCTP_CONNTRACK_SHUTDOWN_SENT,
+ SCTP_CONNTRACK_SHUTDOWN_RECD,
+ SCTP_CONNTRACK_SHUTDOWN_ACK_SENT,
+ SCTP_CONNTRACK_MAX
+};
+
+struct ip_ct_sctp
+{
+ enum sctp_conntrack state;
+
+ u_int32_t vtag[IP_CT_DIR_MAX];
+ u_int32_t ttag[IP_CT_DIR_MAX];
+};
+
+#endif /* _IP_CONNTRACK_SCTP_H */
--- /dev/null
+/* PPTP constants and structs */
+#ifndef _NAT_PPTP_H
+#define _NAT_PPTP_H
+
+/* conntrack private data */
+struct ip_nat_pptp {
+ u_int16_t pns_call_id; /* NAT'ed PNS call id */
+ u_int16_t pac_call_id; /* NAT'ed PAC call id */
+};
+
+#endif /* _NAT_PPTP_H */
--- /dev/null
+#ifndef _IPT_COMMENT_H
+#define _IPT_COMMENT_H
+
+#define IPT_MAX_COMMENT_LEN 256
+
+struct ipt_comment_info {
+ unsigned char comment[IPT_MAX_COMMENT_LEN];
+};
+
+#endif /* _IPT_COMMENT_H */
--- /dev/null
+#ifndef _IPT_SCTP_H_
+#define _IPT_SCTP_H_
+
+#define IPT_SCTP_SRC_PORTS 0x01
+#define IPT_SCTP_DEST_PORTS 0x02
+#define IPT_SCTP_CHUNK_TYPES 0x04
+
+#define IPT_SCTP_VALID_FLAGS 0x07
+
+#define ELEMCOUNT(x) (sizeof(x)/sizeof(x[0]))
+
+
+struct ipt_sctp_flag_info {
+ u_int8_t chunktype;
+ u_int8_t flag;
+ u_int8_t flag_mask;
+};
+
+#define IPT_NUM_SCTP_FLAGS 4
+
+struct ipt_sctp_info {
+ u_int16_t dpts[2]; /* Min, Max */
+ u_int16_t spts[2]; /* Min, Max */
+
+ u_int32_t chunkmap[256 / sizeof (u_int32_t)]; /* Bit mask of chunks to be matched according to RFC 2960 */
+
+#define SCTP_CHUNK_MATCH_ANY 0x01 /* Match if any of the chunk types are present */
+#define SCTP_CHUNK_MATCH_ALL 0x02 /* Match if all of the chunk types are present */
+#define SCTP_CHUNK_MATCH_ONLY 0x04 /* Match if these are the only chunk types present */
+
+ u_int32_t chunk_match_type;
+ struct ipt_sctp_flag_info flag_info[IPT_NUM_SCTP_FLAGS];
+ int flag_count;
+
+ u_int32_t flags;
+ u_int32_t invflags;
+};
+
+#define bytes(type) (sizeof(type) * 8)
+
+#define SCTP_CHUNKMAP_SET(chunkmap, type) \
+ do { \
+ chunkmap[type / bytes(u_int32_t)] |= \
+ 1 << (type % bytes(u_int32_t)); \
+ } while (0)
+
+#define SCTP_CHUNKMAP_CLEAR(chunkmap, type) \
+ do { \
+ chunkmap[type / bytes(u_int32_t)] &= \
+ ~(1 << (type % bytes(u_int32_t))); \
+ } while (0)
+
+#define SCTP_CHUNKMAP_IS_SET(chunkmap, type) \
+({ \
+ (chunkmap[type / bytes (u_int32_t)] & \
+ (1 << (type % bytes (u_int32_t)))) ? 1: 0; \
+})
+
+#define SCTP_CHUNKMAP_RESET(chunkmap) \
+ do { \
+ int i; \
+ for (i = 0; i < ELEMCOUNT(chunkmap); i++) \
+ chunkmap[i] = 0; \
+ } while (0)
+
+#define SCTP_CHUNKMAP_SET_ALL(chunkmap) \
+ do { \
+ int i; \
+ for (i = 0; i < ELEMCOUNT(chunkmap); i++) \
+ chunkmap[i] = ~0; \
+ } while (0)
+
+#define SCTP_CHUNKMAP_COPY(destmap, srcmap) \
+ do { \
+ int i; \
+ for (i = 0; i < ELEMCOUNT(chunkmap); i++) \
+ destmap[i] = srcmap[i]; \
+ } while (0)
+
+#define SCTP_CHUNKMAP_IS_CLEAR(chunkmap) \
+({ \
+ int i; \
+ int flag = 1; \
+ for (i = 0; i < ELEMCOUNT(chunkmap); i++) { \
+ if (chunkmap[i]) { \
+ flag = 0; \
+ break; \
+ } \
+ } \
+ flag; \
+})
+
+#define SCTP_CHUNKMAP_IS_ALL_SET(chunkmap) \
+({ \
+ int i; \
+ int flag = 1; \
+ for (i = 0; i < ELEMCOUNT(chunkmap); i++) { \
+ if (chunkmap[i] != ~0) { \
+ flag = 0; \
+ break; \
+ } \
+ } \
+ flag; \
+})
+
+#endif /* _IPT_SCTP_H_ */
+
--- /dev/null
+#ifndef _IP6T_PHYSDEV_H
+#define _IP6T_PHYSDEV_H
+
+#ifdef __KERNEL__
+#include <linux/if.h>
+#endif
+
+#define IP6T_PHYSDEV_OP_IN 0x01
+#define IP6T_PHYSDEV_OP_OUT 0x02
+#define IP6T_PHYSDEV_OP_BRIDGED 0x04
+#define IP6T_PHYSDEV_OP_ISIN 0x08
+#define IP6T_PHYSDEV_OP_ISOUT 0x10
+#define IP6T_PHYSDEV_OP_MASK (0x20 - 1)
+
+struct ip6t_physdev_info {
+ char physindev[IFNAMSIZ];
+ char in_mask[IFNAMSIZ];
+ char physoutdev[IFNAMSIZ];
+ char out_mask[IFNAMSIZ];
+ u_int8_t invert;
+ u_int8_t bitmask;
+};
+
+#endif /*_IP6T_PHYSDEV_H*/
--- /dev/null
+/*
+ * include/linux/nfs4_acl.c
+ *
+ * Common NFSv4 ACL handling definitions.
+ *
+ * Copyright (c) 2002 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Marius Aamodt Eriksen <marius@umich.edu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LINUX_NFS4_ACL_H
+#define LINUX_NFS4_ACL_H
+
+#include <linux/posix_acl.h>
+
+struct nfs4_acl *nfs4_acl_new(void);
+void nfs4_acl_free(struct nfs4_acl *);
+int nfs4_acl_add_ace(struct nfs4_acl *, u32, u32, u32, int, uid_t);
+int nfs4_acl_get_whotype(char *, u32);
+int nfs4_acl_write_who(int who, char *p);
+int nfs4_acl_permission(struct nfs4_acl *acl, uid_t owner, gid_t group,
+ uid_t who, u32 mask);
+
+#define NFS4_ACL_TYPE_DEFAULT 0x01
+#define NFS4_ACL_DIR 0x02
+#define NFS4_ACL_OWNER 0x04
+
+struct nfs4_acl *nfs4_acl_posix_to_nfsv4(struct posix_acl *,
+ struct posix_acl *, unsigned int flags);
+int nfs4_acl_nfsv4_to_posix(struct nfs4_acl *, struct posix_acl **,
+ struct posix_acl **, unsigned int flags);
+
+#endif /* LINUX_NFS4_ACL_H */
--- /dev/null
+#ifndef _RAID10_H
+#define _RAID10_H
+
+#include <linux/raid/md.h>
+
+typedef struct mirror_info mirror_info_t;
+
+struct mirror_info {
+ mdk_rdev_t *rdev;
+ sector_t head_position;
+};
+
+typedef struct r10bio_s r10bio_t;
+
+struct r10_private_data_s {
+ mddev_t *mddev;
+ mirror_info_t *mirrors;
+ int raid_disks;
+ int working_disks;
+ spinlock_t device_lock;
+
+ /* geometry */
+ int near_copies; /* number of copies layed out raid0 style */
+ int far_copies; /* number of copies layed out
+ * at large strides across drives
+ */
+ int copies; /* near_copies * far_copies.
+ * must be <= raid_disks
+ */
+ sector_t stride; /* distance between far copies.
+ * This is size / far_copies
+ */
+
+ int chunk_shift; /* shift from chunks to sectors */
+ sector_t chunk_mask;
+
+ struct list_head retry_list;
+ /* for use when syncing mirrors: */
+
+ spinlock_t resync_lock;
+ int nr_pending;
+ int barrier;
+ sector_t next_resync;
+
+ wait_queue_head_t wait_idle;
+ wait_queue_head_t wait_resume;
+
+ mempool_t *r10bio_pool;
+ mempool_t *r10buf_pool;
+};
+
+typedef struct r10_private_data_s conf_t;
+
+/*
+ * this is the only point in the RAID code where we violate
+ * C type safety. mddev->private is an 'opaque' pointer.
+ */
+#define mddev_to_conf(mddev) ((conf_t *) mddev->private)
+
+/*
+ * this is our 'private' RAID10 bio.
+ *
+ * it contains information about what kind of IO operations were started
+ * for this RAID10 operation, and about their status:
+ */
+
+struct r10bio_s {
+ atomic_t remaining; /* 'have we finished' count,
+ * used from IRQ handlers
+ */
+ sector_t sector; /* virtual sector number */
+ int sectors;
+ unsigned long state;
+ mddev_t *mddev;
+ /*
+ * original bio going to /dev/mdx
+ */
+ struct bio *master_bio;
+ /*
+ * if the IO is in READ direction, then this is where we read
+ */
+ int read_slot;
+
+ struct list_head retry_list;
+ /*
+ * if the IO is in WRITE direction, then multiple bios are used,
+ * one for each copy.
+ * When resyncing we also use one for each copy.
+ * When reconstructing, we use 2 bios, one for read, one for write.
+ * We choose the number when they are allocated.
+ */
+ struct {
+ struct bio *bio;
+ sector_t addr;
+ int devnum;
+ } devs[0];
+};
+
+/* bits for r10bio.state */
+#define R10BIO_Uptodate 0
+#define R10BIO_IsSync 1
+#define R10BIO_IsRecover 2
+#endif
--- /dev/null
+#ifndef _LINUX_RAMFS_H
+#define _LINUX_RAMFS_H
+
+struct inode *ramfs_get_inode(struct super_block *sb, int mode, dev_t dev);
+struct super_block *ramfs_get_sb(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data);
+
+extern struct file_operations ramfs_file_operations;
+extern struct vm_operations_struct generic_file_vm_ops;
+
+#endif
--- /dev/null
+/*
+ * linux/include/linux/sunrpc/gss_spkm3.h
+ *
+ * Copyright (c) 2000 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Andy Adamson <andros@umich.edu>
+ */
+
+#include <linux/sunrpc/auth_gss.h>
+#include <linux/sunrpc/gss_err.h>
+#include <linux/sunrpc/gss_asn1.h>
+
+struct spkm3_ctx {
+ struct xdr_netobj ctx_id; /* per message context id */
+ int qop; /* negotiated qop */
+ struct xdr_netobj mech_used;
+ unsigned int ret_flags ;
+ unsigned int req_flags ;
+ struct xdr_netobj share_key;
+ int conf_alg;
+ struct crypto_tfm* derived_conf_key;
+ int intg_alg;
+ struct crypto_tfm* derived_integ_key;
+ int keyestb_alg; /* alg used to get share_key */
+ int owf_alg; /* one way function */
+};
+
+/* from openssl/objects.h */
+/* XXX need SEAL_ALG_NONE */
+#define NID_md5 4
+#define NID_dhKeyAgreement 28
+#define NID_des_cbc 31
+#define NID_sha1 64
+#define NID_cast5_cbc 108
+
+/* SPKM InnerContext Token types */
+
+#define SPKM_ERROR_TOK 3
+#define SPKM_MIC_TOK 4
+#define SPKM_WRAP_TOK 5
+#define SPKM_DEL_TOK 6
+
+u32 spkm3_make_token(struct spkm3_ctx *ctx, int qop_req, struct xdr_buf * text, struct xdr_netobj * token, int toktype);
+
+u32 spkm3_read_token(struct spkm3_ctx *ctx, struct xdr_netobj *read_token, struct xdr_buf *message_buffer, int *qop_state, int toktype);
+
+#define CKSUMTYPE_RSA_MD5 0x0007
+
+s32 make_checksum(s32 cksumtype, char *header, int hdrlen, struct xdr_buf *body,
+ struct xdr_netobj *cksum);
+void asn1_bitstring_len(struct xdr_netobj *in, int *enclen, int *zerobits);
+int decode_asn1_bitstring(struct xdr_netobj *out, char *in, int enclen,
+ int explen);
+void spkm3_mic_header(unsigned char **hdrbuf, unsigned int *hdrlen,
+ unsigned char *ctxhdr, int elen, int zbit);
+void spkm3_make_mic_token(unsigned char **tokp, int toklen,
+ struct xdr_netobj *mic_hdr,
+ struct xdr_netobj *md5cksum, int md5elen, int md5zbit);
+u32 spkm3_verify_mic_token(unsigned char **tokp, int *mic_hdrlen,
+ unsigned char **cksum);
--- /dev/null
+#ifndef __LINUX_TC_GACT_H
+#define __LINUX_TC_GACT_H
+
+#include <linux/pkt_cls.h>
+
+#define TCA_ACT_GACT 5
+struct tc_gact
+{
+ tc_gen;
+
+};
+
+struct tc_gact_p
+{
+#define PGACT_NONE 0
+#define PGACT_NETRAND 1
+#define PGACT_DETERM 2
+#define MAX_RAND (PGACT_DETERM + 1 )
+ __u16 ptype;
+ __u16 pval;
+ int paction;
+};
+
+enum
+{
+ TCA_GACT_UNSPEC,
+ TCA_GACT_TM,
+ TCA_GACT_PARMS,
+ TCA_GACT_PROB,
+ __TCA_GACT_MAX
+};
+#define TCA_GACT_MAX (__TCA_GACT_MAX - 1)
+
+#endif
--- /dev/null
+// include/linux/usb_otg.h
+
+/*
+ * These APIs may be used between USB controllers. USB device drivers
+ * (for either host or peripheral roles) don't use these calls; they
+ * continue to use just usb_device and usb_gadget.
+ */
+
+
+/* OTG defines lots of enumeration states before device reset */
+enum usb_otg_state {
+ OTG_STATE_UNDEFINED = 0,
+
+ /* single-role peripheral, and dual-role default-b */
+ OTG_STATE_B_IDLE,
+ OTG_STATE_B_SRP_INIT,
+ OTG_STATE_B_PERIPHERAL,
+
+ /* extra dual-role default-b states */
+ OTG_STATE_B_WAIT_ACON,
+ OTG_STATE_B_HOST,
+
+ /* dual-role default-a */
+ OTG_STATE_A_IDLE,
+ OTG_STATE_A_WAIT_VRISE,
+ OTG_STATE_A_WAIT_BCON,
+ OTG_STATE_A_HOST,
+ OTG_STATE_A_SUSPEND,
+ OTG_STATE_A_PERIPHERAL,
+ OTG_STATE_A_WAIT_VFALL,
+ OTG_STATE_A_VBUS_ERR,
+};
+
+/*
+ * the otg driver needs to interact with both device side and host side
+ * usb controllers. it decides which controller is active at a given
+ * moment, using the transceiver, ID signal, HNP and sometimes static
+ * configuration information (including "board isn't wired for otg").
+ */
+struct otg_transceiver {
+ struct device *dev;
+ const char *label;
+
+ u8 default_a;
+ enum usb_otg_state state;
+
+ struct usb_bus *host;
+ struct usb_gadget *gadget;
+
+ /* to pass extra port status to the root hub */
+ u16 port_status;
+ u16 port_change;
+
+ /* bind/unbind the host controller */
+ int (*set_host)(struct otg_transceiver *otg,
+ struct usb_bus *host);
+
+ /* bind/unbind the peripheral controller */
+ int (*set_peripheral)(struct otg_transceiver *otg,
+ struct usb_gadget *gadget);
+
+ /* effective for B devices, ignored for A-peripheral */
+ int (*set_power)(struct otg_transceiver *otg,
+ unsigned mA);
+
+ /* for B devices only: start session with A-Host */
+ int (*start_srp)(struct otg_transceiver *otg);
+
+ /* start or continue HNP role switch */
+ int (*start_hnp)(struct otg_transceiver *otg);
+
+};
+
+
+/* for board-specific init logic */
+extern int otg_set_transceiver(struct otg_transceiver *);
+
+
+/* for usb host and peripheral controller drivers */
+extern struct otg_transceiver *otg_get_transceiver(void);
+
+static inline int
+otg_start_hnp(struct otg_transceiver *otg)
+{
+ return otg->start_hnp(otg);
+}
+
+
+/* for HCDs */
+static inline int
+otg_set_host(struct otg_transceiver *otg, struct usb_bus *host)
+{
+ return otg->set_host(otg, host);
+}
+
+
+/* for usb peripheral controller drivers */
+static inline int
+otg_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *periph)
+{
+ return otg->set_peripheral(otg, periph);
+}
+
+static inline int
+otg_set_power(struct otg_transceiver *otg, unsigned mA)
+{
+ return otg->set_power(otg, mA);
+}
+
+static inline int
+otg_start_srp(struct otg_transceiver *otg)
+{
+ return otg->start_srp(otg);
+}
+
+
+/* for OTG controller drivers (and maybe other stuff) */
+extern int usb_bus_start_enum(struct usb_bus *bus, unsigned port_num);
--- /dev/null
+#ifndef __NET_GEN_STATS_H
+#define __NET_GEN_STATS_H
+
+#include <linux/gen_stats.h>
+#include <linux/socket.h>
+#include <linux/rtnetlink.h>
+#include <linux/pkt_sched.h>
+
+struct gnet_dump
+{
+ spinlock_t * lock;
+ struct sk_buff * skb;
+ struct rtattr * tail;
+
+ /* Backward compatability */
+ int compat_tc_stats;
+ int compat_xstats;
+ struct rtattr * xstats;
+ struct tc_stats tc_stats;
+};
+
+extern int gnet_stats_start_copy(struct sk_buff *skb, int type,
+ spinlock_t *lock, struct gnet_dump *d);
+
+extern int gnet_stats_start_copy_compat(struct sk_buff *skb, int type,
+ int tc_stats_type,int xstats_type,
+ spinlock_t *lock, struct gnet_dump *d);
+
+extern int gnet_stats_copy_basic(struct gnet_dump *d,
+ struct gnet_stats_basic *b);
+extern int gnet_stats_copy_rate_est(struct gnet_dump *d,
+ struct gnet_stats_rate_est *r);
+extern int gnet_stats_copy_queue(struct gnet_dump *d,
+ struct gnet_stats_queue *q);
+extern int gnet_stats_copy_app(struct gnet_dump *d, void *st, int len);
+
+extern int gnet_stats_finish_copy(struct gnet_dump *d);
+
+extern int gen_new_estimator(struct gnet_stats_basic *bstats,
+ struct gnet_stats_rate_est *rate_est,
+ spinlock_t *stats_lock, struct rtattr *opt);
+extern void gen_kill_estimator(struct gnet_stats_basic *bstats,
+ struct gnet_stats_rate_est *rate_est);
+
+#endif
--- /dev/null
+#ifndef __NET_TC_GACT_H
+#define __NET_TC_GACT_H
+
+#include <net/pkt_sched.h>
+
+struct tcf_gact
+{
+ tca_gen(gact);
+#ifdef CONFIG_GACT_PROB
+ u16 ptype;
+ u16 pval;
+ int paction;
+#endif
+
+};
+
+#endif
--- /dev/null
+/*
+ * Helper functions for indirect PCM data transfer
+ *
+ * Copyright (c) by Takashi Iwai <tiwai@suse.de>
+ * Jaroslav Kysela <perex@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __SOUND_PCM_INDIRECT_H
+#define __SOUND_PCM_INDIRECT_H
+
+#include <sound/pcm.h>
+
+typedef struct sndrv_pcm_indirect {
+ unsigned int hw_buffer_size; /* Byte size of hardware buffer */
+ unsigned int hw_queue_size; /* Max queue size of hw buffer (0 = buffer size) */
+ unsigned int hw_data; /* Offset to next dst (or src) in hw ring buffer */
+ unsigned int hw_io; /* Ring buffer hw pointer */
+ int hw_ready; /* Bytes ready for play (or captured) in hw ring buffer */
+ unsigned int sw_buffer_size; /* Byte size of software buffer */
+ unsigned int sw_data; /* Offset to next dst (or src) in sw ring buffer */
+ unsigned int sw_io; /* Current software pointer in bytes */
+ int sw_ready; /* Bytes ready to be transferred to/from hw */
+ snd_pcm_uframes_t appl_ptr; /* Last seen appl_ptr */
+} snd_pcm_indirect_t;
+
+typedef void (*snd_pcm_indirect_copy_t)(snd_pcm_substream_t *substream,
+ snd_pcm_indirect_t *rec, size_t bytes);
+
+/*
+ * helper function for playback ack callback
+ */
+static inline void
+snd_pcm_indirect_playback_transfer(snd_pcm_substream_t *substream,
+ snd_pcm_indirect_t *rec,
+ snd_pcm_indirect_copy_t copy)
+{
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
+ snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr;
+ int qsize;
+
+ if (diff) {
+ if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
+ diff += runtime->boundary;
+ rec->sw_ready += (int)frames_to_bytes(runtime, diff);
+ rec->appl_ptr = appl_ptr;
+ }
+ qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size;
+ while (rec->hw_ready < qsize && rec->sw_ready > 0) {
+ unsigned int hw_to_end = rec->hw_buffer_size - rec->hw_data;
+ unsigned int sw_to_end = rec->sw_buffer_size - rec->sw_data;
+ unsigned int bytes = qsize - rec->hw_ready;
+ if (rec->sw_ready < (int)bytes)
+ bytes = rec->sw_ready;
+ if (hw_to_end < bytes)
+ bytes = hw_to_end;
+ if (sw_to_end < bytes)
+ bytes = sw_to_end;
+ if (! bytes)
+ break;
+ copy(substream, rec, bytes);
+ rec->hw_data += bytes;
+ if (rec->hw_data == rec->hw_buffer_size)
+ rec->hw_data = 0;
+ rec->sw_data += bytes;
+ if (rec->sw_data == rec->sw_buffer_size)
+ rec->sw_data = 0;
+ rec->hw_ready += bytes;
+ rec->sw_ready -= bytes;
+ }
+}
+
+/*
+ * helper function for playback pointer callback
+ * ptr = current byte pointer
+ */
+static inline snd_pcm_uframes_t
+snd_pcm_indirect_playback_pointer(snd_pcm_substream_t *substream,
+ snd_pcm_indirect_t *rec, unsigned int ptr)
+{
+ int bytes = ptr - rec->hw_io;
+ if (bytes < 0)
+ bytes += rec->hw_buffer_size;
+ rec->hw_io = ptr;
+ rec->hw_ready -= bytes;
+ rec->sw_io += bytes;
+ if (rec->sw_io >= rec->sw_buffer_size)
+ rec->sw_io -= rec->sw_buffer_size;
+ if (substream->ops->ack)
+ substream->ops->ack(substream);
+ return bytes_to_frames(substream->runtime, rec->sw_io);
+}
+
+
+/*
+ * helper function for capture ack callback
+ */
+static inline void
+snd_pcm_indirect_capture_transfer(snd_pcm_substream_t *substream,
+ snd_pcm_indirect_t *rec,
+ snd_pcm_indirect_copy_t copy)
+{
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
+ snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr;
+
+ if (diff) {
+ if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
+ diff += runtime->boundary;
+ rec->sw_ready -= frames_to_bytes(runtime, diff);
+ rec->appl_ptr = appl_ptr;
+ }
+ while (rec->hw_ready > 0 &&
+ rec->sw_ready < (int)rec->sw_buffer_size) {
+ size_t hw_to_end = rec->hw_buffer_size - rec->hw_data;
+ size_t sw_to_end = rec->sw_buffer_size - rec->sw_data;
+ size_t bytes = rec->sw_buffer_size - rec->sw_ready;
+ if (rec->hw_ready < (int)bytes)
+ bytes = rec->hw_ready;
+ if (hw_to_end < bytes)
+ bytes = hw_to_end;
+ if (sw_to_end < bytes)
+ bytes = sw_to_end;
+ if (! bytes)
+ break;
+ copy(substream, rec, bytes);
+ rec->hw_data += bytes;
+ if ((int)rec->hw_data == rec->hw_buffer_size)
+ rec->hw_data = 0;
+ rec->sw_data += bytes;
+ if (rec->sw_data == rec->sw_buffer_size)
+ rec->sw_data = 0;
+ rec->hw_ready -= bytes;
+ rec->sw_ready += bytes;
+ }
+}
+
+/*
+ * helper function for capture pointer callback,
+ * ptr = current byte pointer
+ */
+static inline snd_pcm_uframes_t
+snd_pcm_indirect_capture_pointer(snd_pcm_substream_t *substream,
+ snd_pcm_indirect_t *rec, unsigned int ptr)
+{
+ int qsize;
+ int bytes = ptr - rec->hw_io;
+ if (bytes < 0)
+ bytes += rec->hw_buffer_size;
+ rec->hw_io = ptr;
+ rec->hw_ready += bytes;
+ qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size;
+ if (rec->hw_ready > qsize)
+ return SNDRV_PCM_POS_XRUN;
+ rec->sw_io += bytes;
+ if (rec->sw_io >= rec->sw_buffer_size)
+ rec->sw_io -= rec->sw_buffer_size;
+ if (substream->ops->ack)
+ substream->ops->ack(substream);
+ return bytes_to_frames(substream->runtime, rec->sw_io);
+}
+
+#endif /* __SOUND_PCM_INDIRECT_H */
--- /dev/null
+/*
+ * include/video/epson13xx.h -- Epson 13xx frame buffer
+ *
+ * Copyright (C) Hewlett-Packard Company. All rights reserved.
+ *
+ * Written by Christopher Hoover <ch@hpl.hp.com>
+ *
+ */
+
+#ifndef _EPSON13XX_H_
+#define _EPSON13XX_H_
+
+#define REG_REVISION_CODE 0x00
+#define REG_MEMORY_CONFIG 0x01
+#define REG_PANEL_TYPE 0x02
+#define REG_MOD_RATE 0x03
+#define REG_HORZ_DISP_WIDTH 0x04
+#define REG_HORZ_NONDISP_PERIOD 0x05
+#define REG_HRTC_START_POSITION 0x06
+#define REG_HRTC_PULSE_WIDTH 0x07
+#define REG_VERT_DISP_HEIGHT0 0x08
+#define REG_VERT_DISP_HEIGHT1 0x09
+#define REG_VERT_NONDISP_PERIOD 0x0A
+#define REG_VRTC_START_POSITION 0x0B
+#define REG_VRTC_PULSE_WIDTH 0x0C
+#define REG_DISPLAY_MODE 0x0D
+#define REG_SCRN1_LINE_COMPARE0 0x0E
+#define REG_SCRN1_LINE_COMPARE1 0x0F
+#define REG_SCRN1_DISP_START_ADDR0 0x10
+#define REG_SCRN1_DISP_START_ADDR1 0x11
+#define REG_SCRN1_DISP_START_ADDR2 0x12
+#define REG_SCRN2_DISP_START_ADDR0 0x13
+#define REG_SCRN2_DISP_START_ADDR1 0x14
+#define REG_SCRN2_DISP_START_ADDR2 0x15
+#define REG_MEM_ADDR_OFFSET0 0x16
+#define REG_MEM_ADDR_OFFSET1 0x17
+#define REG_PIXEL_PANNING 0x18
+#define REG_CLOCK_CONFIG 0x19
+#define REG_POWER_SAVE_CONFIG 0x1A
+#define REG_MISC 0x1B
+#define REG_MD_CONFIG_READBACK0 0x1C
+#define REG_MD_CONFIG_READBACK1 0x1D
+#define REG_GPIO_CONFIG0 0x1E
+#define REG_GPIO_CONFIG1 0x1F
+#define REG_GPIO_CONTROL0 0x20
+#define REG_GPIO_CONTROL1 0x21
+#define REG_PERF_ENHANCEMENT0 0x22
+#define REG_PERF_ENHANCEMENT1 0x23
+#define REG_LUT_ADDR 0x24
+#define REG_RESERVED_1 0x25
+#define REG_LUT_DATA 0x26
+#define REG_INK_CURSOR_CONTROL 0x27
+#define REG_CURSOR_X_POSITION0 0x28
+#define REG_CURSOR_X_POSITION1 0x29
+#define REG_CURSOR_Y_POSITION0 0x2A
+#define REG_CURSOR_Y_POSITION1 0x2B
+#define REG_INK_CURSOR_COLOR0_0 0x2C
+#define REG_INK_CURSOR_COLOR0_1 0x2D
+#define REG_INK_CURSOR_COLOR1_0 0x2E
+#define REG_INK_CURSOR_COLOR1_1 0x2F
+#define REG_INK_CURSOR_START_ADDR 0x30
+#define REG_ALTERNATE_FRM 0x31
+
+#endif
--- /dev/null
+/*
+ * kexec.c - kexec system call
+ * Copyright (C) 2002-2004 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/file.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/kexec.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/highmem.h>
+#include <net/checksum.h>
+#include <asm/page.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * When kexec transitions to the new kernel there is a one-to-one
+ * mapping between physical and virtual addresses. On processors
+ * where you can disable the MMU this is trivial, and easy. For
+ * others it is still a simple predictable page table to setup.
+ *
+ * In that environment kexec copies the new kernel to its final
+ * resting place. This means I can only support memory whose
+ * physical address can fit in an unsigned long. In particular
+ * addresses where (pfn << PAGE_SHIFT) > ULONG_MAX cannot be handled.
+ * If the assembly stub has more restrictive requirements
+ * KEXEC_SOURCE_MEMORY_LIMIT and KEXEC_DEST_MEMORY_LIMIT can be
+ * defined more restrictively in <asm/kexec.h>.
+ *
+ * The code for the transition from the current kernel to the
+ * the new kernel is placed in the control_code_buffer, whose size
+ * is given by KEXEC_CONTROL_CODE_SIZE. In the best case only a single
+ * page of memory is necessary, but some architectures require more.
+ * Because this memory must be identity mapped in the transition from
+ * virtual to physical addresses it must live in the range
+ * 0 - TASK_SIZE, as only the user space mappings are arbitrarily
+ * modifiable.
+ *
+ * The assembly stub in the control code buffer is passed a linked list
+ * of descriptor pages detailing the source pages of the new kernel,
+ * and the destination addresses of those source pages. As this data
+ * structure is not used in the context of the current OS, it must
+ * be self-contained.
+ *
+ * The code has been made to work with highmem pages and will use a
+ * destination page in its final resting place (if it happens
+ * to allocate it). The end product of this is that most of the
+ * physical address space, and most of RAM can be used.
+ *
+ * Future directions include:
+ * - allocating a page table with the control code buffer identity
+ * mapped, to simplify machine_kexec and make kexec_on_panic more
+ * reliable.
+ */
+
+/*
+ * KIMAGE_NO_DEST is an impossible destination address..., for
+ * allocating pages whose destination address we do not care about.
+ */
+#define KIMAGE_NO_DEST (-1UL)
+
+static int kimage_is_destination_range(
+ struct kimage *image, unsigned long start, unsigned long end);
+static struct page *kimage_alloc_page(struct kimage *image, unsigned int gfp_mask, unsigned long dest);
+
+
+static int kimage_alloc(struct kimage **rimage,
+ unsigned long nr_segments, struct kexec_segment *segments)
+{
+ int result;
+ struct kimage *image;
+ size_t segment_bytes;
+ unsigned long i;
+
+ /* Allocate a controlling structure */
+ result = -ENOMEM;
+ image = kmalloc(sizeof(*image), GFP_KERNEL);
+ if (!image) {
+ goto out;
+ }
+ memset(image, 0, sizeof(*image));
+ image->head = 0;
+ image->entry = &image->head;
+ image->last_entry = &image->head;
+
+ /* Initialize the list of control pages */
+ INIT_LIST_HEAD(&image->control_pages);
+
+ /* Initialize the list of destination pages */
+ INIT_LIST_HEAD(&image->dest_pages);
+
+ /* Initialize the list of unuseable pages */
+ INIT_LIST_HEAD(&image->unuseable_pages);
+
+ /* Read in the segments */
+ image->nr_segments = nr_segments;
+ segment_bytes = nr_segments * sizeof*segments;
+ result = copy_from_user(image->segment, segments, segment_bytes);
+ if (result)
+ goto out;
+
+ /*
+ * Verify we have good destination addresses. The caller is
+ * responsible for making certain we don't attempt to load
+ * the new image into invalid or reserved areas of RAM. This
+ * just verifies it is an address we can use.
+ */
+ result = -EADDRNOTAVAIL;
+ for (i = 0; i < nr_segments; i++) {
+ unsigned long mend;
+ mend = ((unsigned long)(image->segment[i].mem)) +
+ image->segment[i].memsz;
+ if (mend >= KEXEC_DESTINATION_MEMORY_LIMIT)
+ goto out;
+ }
+
+ /*
+ * Find a location for the control code buffer, and add it
+ * the vector of segments so that it's pages will also be
+ * counted as destination pages.
+ */
+ result = -ENOMEM;
+ image->control_code_page = kimage_alloc_control_pages(image,
+ get_order(KEXEC_CONTROL_CODE_SIZE));
+ if (!image->control_code_page) {
+ printk(KERN_ERR "Could not allocate control_code_buffer\n");
+ goto out;
+ }
+
+ result = 0;
+ out:
+ if (result == 0) {
+ *rimage = image;
+ } else {
+ kfree(image);
+ }
+ return result;
+}
+
+static int kimage_is_destination_range(
+ struct kimage *image, unsigned long start, unsigned long end)
+{
+ unsigned long i;
+
+ for (i = 0; i < image->nr_segments; i++) {
+ unsigned long mstart, mend;
+ mstart = (unsigned long)image->segment[i].mem;
+ mend = mstart + image->segment[i].memsz;
+ if ((end > mstart) && (start < mend)) {
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static struct page *kimage_alloc_pages(unsigned int gfp_mask, unsigned int order)
+{
+ struct page *pages;
+ pages = alloc_pages(gfp_mask, order);
+ if (pages) {
+ unsigned int count, i;
+ pages->mapping = NULL;
+ pages->private = order;
+ count = 1 << order;
+ for(i = 0; i < count; i++) {
+ SetPageReserved(pages + i);
+ }
+ }
+ return pages;
+}
+
+static void kimage_free_pages(struct page *page)
+{
+ unsigned int order, count, i;
+ order = page->private;
+ count = 1 << order;
+ for(i = 0; i < count; i++) {
+ ClearPageReserved(page + i);
+ }
+ __free_pages(page, order);
+}
+
+static void kimage_free_page_list(struct list_head *list)
+{
+ struct list_head *pos, *next;
+ list_for_each_safe(pos, next, list) {
+ struct page *page;
+
+ page = list_entry(pos, struct page, lru);
+ list_del(&page->lru);
+
+ kimage_free_pages(page);
+ }
+}
+
+struct page *kimage_alloc_control_pages(struct kimage *image, unsigned int order)
+{
+ /* Control pages are special, they are the intermediaries
+ * that are needed while we copy the rest of the pages
+ * to their final resting place. As such they must
+ * not conflict with either the destination addresses
+ * or memory the kernel is already using.
+ *
+ * The only case where we really need more than one of
+ * these are for architectures where we cannot disable
+ * the MMU and must instead generate an identity mapped
+ * page table for all of the memory.
+ *
+ * At worst this runs in O(N) of the image size.
+ */
+ struct list_head extra_pages;
+ struct page *pages;
+ unsigned int count;
+
+ count = 1 << order;
+ INIT_LIST_HEAD(&extra_pages);
+
+ /* Loop while I can allocate a page and the page allocated
+ * is a destination page.
+ */
+ do {
+ unsigned long pfn, epfn, addr, eaddr;
+ pages = kimage_alloc_pages(GFP_KERNEL, order);
+ if (!pages)
+ break;
+ pfn = page_to_pfn(pages);
+ epfn = pfn + count;
+ addr = pfn << PAGE_SHIFT;
+ eaddr = epfn << PAGE_SHIFT;
+ if ((epfn >= (KEXEC_CONTROL_MEMORY_LIMIT >> PAGE_SHIFT)) ||
+ kimage_is_destination_range(image, addr, eaddr))
+ {
+ list_add(&pages->lru, &extra_pages);
+ pages = NULL;
+ }
+ } while(!pages);
+ if (pages) {
+ /* Remember the allocated page... */
+ list_add(&pages->lru, &image->control_pages);
+
+ /* Because the page is already in it's destination
+ * location we will never allocate another page at
+ * that address. Therefore kimage_alloc_pages
+ * will not return it (again) and we don't need
+ * to give it an entry in image->segment[].
+ */
+ }
+ /* Deal with the destination pages I have inadvertently allocated.
+ *
+ * Ideally I would convert multi-page allocations into single
+ * page allocations, and add everyting to image->dest_pages.
+ *
+ * For now it is simpler to just free the pages.
+ */
+ kimage_free_page_list(&extra_pages);
+ return pages;
+
+}
+
+static int kimage_add_entry(struct kimage *image, kimage_entry_t entry)
+{
+ if (*image->entry != 0) {
+ image->entry++;
+ }
+ if (image->entry == image->last_entry) {
+ kimage_entry_t *ind_page;
+ struct page *page;
+ page = kimage_alloc_page(image, GFP_KERNEL, KIMAGE_NO_DEST);
+ if (!page) {
+ return -ENOMEM;
+ }
+ ind_page = page_address(page);
+ *image->entry = virt_to_phys(ind_page) | IND_INDIRECTION;
+ image->entry = ind_page;
+ image->last_entry =
+ ind_page + ((PAGE_SIZE/sizeof(kimage_entry_t)) - 1);
+ }
+ *image->entry = entry;
+ image->entry++;
+ *image->entry = 0;
+ return 0;
+}
+
+static int kimage_set_destination(
+ struct kimage *image, unsigned long destination)
+{
+ int result;
+
+ destination &= PAGE_MASK;
+ result = kimage_add_entry(image, destination | IND_DESTINATION);
+ if (result == 0) {
+ image->destination = destination;
+ }
+ return result;
+}
+
+
+static int kimage_add_page(struct kimage *image, unsigned long page)
+{
+ int result;
+
+ page &= PAGE_MASK;
+ result = kimage_add_entry(image, page | IND_SOURCE);
+ if (result == 0) {
+ image->destination += PAGE_SIZE;
+ }
+ return result;
+}
+
+
+static void kimage_free_extra_pages(struct kimage *image)
+{
+ /* Walk through and free any extra destination pages I may have */
+ kimage_free_page_list(&image->dest_pages);
+
+ /* Walk through and free any unuseable pages I have cached */
+ kimage_free_page_list(&image->unuseable_pages);
+
+}
+static int kimage_terminate(struct kimage *image)
+{
+ int result;
+
+ result = kimage_add_entry(image, IND_DONE);
+ if (result == 0) {
+ /* Point at the terminating element */
+ image->entry--;
+ kimage_free_extra_pages(image);
+ }
+ return result;
+}
+
+#define for_each_kimage_entry(image, ptr, entry) \
+ for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE); \
+ ptr = (entry & IND_INDIRECTION)? \
+ phys_to_virt((entry & PAGE_MASK)): ptr +1)
+
+static void kimage_free_entry(kimage_entry_t entry)
+{
+ struct page *page;
+
+ page = pfn_to_page(entry >> PAGE_SHIFT);
+ kimage_free_pages(page);
+}
+
+static void kimage_free(struct kimage *image)
+{
+ kimage_entry_t *ptr, entry;
+ kimage_entry_t ind = 0;
+
+ if (!image)
+ return;
+ kimage_free_extra_pages(image);
+ for_each_kimage_entry(image, ptr, entry) {
+ if (entry & IND_INDIRECTION) {
+ /* Free the previous indirection page */
+ if (ind & IND_INDIRECTION) {
+ kimage_free_entry(ind);
+ }
+ /* Save this indirection page until we are
+ * done with it.
+ */
+ ind = entry;
+ }
+ else if (entry & IND_SOURCE) {
+ kimage_free_entry(entry);
+ }
+ }
+ /* Free the final indirection page */
+ if (ind & IND_INDIRECTION) {
+ kimage_free_entry(ind);
+ }
+
+ /* Handle any machine specific cleanup */
+ machine_kexec_cleanup(image);
+
+ /* Free the kexec control pages... */
+ kimage_free_page_list(&image->control_pages);
+ kfree(image);
+}
+
+static kimage_entry_t *kimage_dst_used(struct kimage *image, unsigned long page)
+{
+ kimage_entry_t *ptr, entry;
+ unsigned long destination = 0;
+
+ for_each_kimage_entry(image, ptr, entry) {
+ if (entry & IND_DESTINATION) {
+ destination = entry & PAGE_MASK;
+ }
+ else if (entry & IND_SOURCE) {
+ if (page == destination) {
+ return ptr;
+ }
+ destination += PAGE_SIZE;
+ }
+ }
+ return 0;
+}
+
+static struct page *kimage_alloc_page(struct kimage *image, unsigned int gfp_mask, unsigned long destination)
+{
+ /*
+ * Here we implement safeguards to ensure that a source page
+ * is not copied to its destination page before the data on
+ * the destination page is no longer useful.
+ *
+ * To do this we maintain the invariant that a source page is
+ * either its own destination page, or it is not a
+ * destination page at all.
+ *
+ * That is slightly stronger than required, but the proof
+ * that no problems will not occur is trivial, and the
+ * implementation is simply to verify.
+ *
+ * When allocating all pages normally this algorithm will run
+ * in O(N) time, but in the worst case it will run in O(N^2)
+ * time. If the runtime is a problem the data structures can
+ * be fixed.
+ */
+ struct page *page;
+ unsigned long addr;
+
+ /*
+ * Walk through the list of destination pages, and see if I
+ * have a match.
+ */
+ list_for_each_entry(page, &image->dest_pages, lru) {
+ addr = page_to_pfn(page) << PAGE_SHIFT;
+ if (addr == destination) {
+ list_del(&page->lru);
+ return page;
+ }
+ }
+ page = NULL;
+ while (1) {
+ kimage_entry_t *old;
+
+ /* Allocate a page, if we run out of memory give up */
+ page = kimage_alloc_pages(gfp_mask, 0);
+ if (!page) {
+ return 0;
+ }
+ /* If the page cannot be used file it away */
+ if (page_to_pfn(page) > (KEXEC_SOURCE_MEMORY_LIMIT >> PAGE_SHIFT)) {
+ list_add(&page->lru, &image->unuseable_pages);
+ continue;
+ }
+ addr = page_to_pfn(page) << PAGE_SHIFT;
+
+ /* If it is the destination page we want use it */
+ if (addr == destination)
+ break;
+
+ /* If the page is not a destination page use it */
+ if (!kimage_is_destination_range(image, addr, addr + PAGE_SIZE))
+ break;
+
+ /*
+ * I know that the page is someones destination page.
+ * See if there is already a source page for this
+ * destination page. And if so swap the source pages.
+ */
+ old = kimage_dst_used(image, addr);
+ if (old) {
+ /* If so move it */
+ unsigned long old_addr;
+ struct page *old_page;
+
+ old_addr = *old & PAGE_MASK;
+ old_page = pfn_to_page(old_addr >> PAGE_SHIFT);
+ copy_highpage(page, old_page);
+ *old = addr | (*old & ~PAGE_MASK);
+
+ /* The old page I have found cannot be a
+ * destination page, so return it.
+ */
+ addr = old_addr;
+ page = old_page;
+ break;
+ }
+ else {
+ /* Place the page on the destination list I
+ * will use it later.
+ */
+ list_add(&page->lru, &image->dest_pages);
+ }
+ }
+ return page;
+}
+
+static int kimage_load_segment(struct kimage *image,
+ struct kexec_segment *segment)
+{
+ unsigned long mstart;
+ int result;
+ unsigned long offset;
+ unsigned long offset_end;
+ unsigned char *buf;
+
+ result = 0;
+ buf = segment->buf;
+ mstart = (unsigned long)segment->mem;
+
+ offset_end = segment->memsz;
+
+ result = kimage_set_destination(image, mstart);
+ if (result < 0) {
+ goto out;
+ }
+ for (offset = 0; offset < segment->memsz; offset += PAGE_SIZE) {
+ struct page *page;
+ char *ptr;
+ size_t size, leader;
+ page = kimage_alloc_page(image, GFP_HIGHUSER, mstart + offset);
+ if (page == 0) {
+ result = -ENOMEM;
+ goto out;
+ }
+ result = kimage_add_page(image, page_to_pfn(page) << PAGE_SHIFT);
+ if (result < 0) {
+ goto out;
+ }
+ ptr = kmap(page);
+ if (segment->bufsz < offset) {
+ /* We are past the end zero the whole page */
+ memset(ptr, 0, PAGE_SIZE);
+ kunmap(page);
+ continue;
+ }
+ size = PAGE_SIZE;
+ leader = 0;
+ if ((offset == 0)) {
+ leader = mstart & ~PAGE_MASK;
+ }
+ if (leader) {
+ /* We are on the first page zero the unused portion */
+ memset(ptr, 0, leader);
+ size -= leader;
+ ptr += leader;
+ }
+ if (size > (segment->bufsz - offset)) {
+ size = segment->bufsz - offset;
+ }
+ if (size < (PAGE_SIZE - leader)) {
+ /* zero the trailing part of the page */
+ memset(ptr + size, 0, (PAGE_SIZE - leader) - size);
+ }
+ result = copy_from_user(ptr, buf + offset, size);
+ kunmap(page);
+ if (result) {
+ result = (result < 0) ? result : -EIO;
+ goto out;
+ }
+ }
+ out:
+ return result;
+}
+
+/*
+ * Exec Kernel system call: for obvious reasons only root may call it.
+ *
+ * This call breaks up into three pieces.
+ * - A generic part which loads the new kernel from the current
+ * address space, and very carefully places the data in the
+ * allocated pages.
+ *
+ * - A generic part that interacts with the kernel and tells all of
+ * the devices to shut down. Preventing on-going dmas, and placing
+ * the devices in a consistent state so a later kernel can
+ * reinitialize them.
+ *
+ * - A machine specific part that includes the syscall number
+ * and the copies the image to it's final destination. And
+ * jumps into the image at entry.
+ *
+ * kexec does not sync, or unmount filesystems so if you need
+ * that to happen you need to do that yourself.
+ */
+struct kimage *kexec_image = NULL;
+
+asmlinkage long sys_kexec_load(unsigned long entry, unsigned long nr_segments,
+ struct kexec_segment *segments, unsigned long flags)
+{
+ struct kimage *image;
+ int result;
+
+ /* We only trust the superuser with rebooting the system. */
+ if (!capable(CAP_SYS_BOOT))
+ return -EPERM;
+
+ /*
+ * In case we need just a little bit of special behavior for
+ * reboot on panic.
+ */
+ if (flags != 0)
+ return -EINVAL;
+
+ if (nr_segments > KEXEC_SEGMENT_MAX)
+ return -EINVAL;
+
+ image = NULL;
+ result = 0;
+
+ if (nr_segments > 0) {
+ unsigned long i;
+ result = kimage_alloc(&image, nr_segments, segments);
+ if (result) {
+ goto out;
+ }
+ result = machine_kexec_prepare(image);
+ if (result) {
+ goto out;
+ }
+ image->start = entry;
+ for (i = 0; i < nr_segments; i++) {
+ result = kimage_load_segment(image, &image->segment[i]);
+ if (result) {
+ goto out;
+ }
+ }
+ result = kimage_terminate(image);
+ if (result) {
+ goto out;
+ }
+ }
+
+ image = xchg(&kexec_image, image);
+
+ out:
+ kimage_free(image);
+ return result;
+}
--- /dev/null
+/*
+ * Kernel Probes (KProbes)
+ * kernel/kprobes.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ *
+ * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
+ * Probes initial implementation (includes suggestions from
+ * Rusty Russell).
+ * 2004-Aug Updated by Prasanna S Panchamukhi <prasanna@in.ibm.com> with
+ * hlists and exceptions notifier as suggested by Andi Kleen.
+ * 2004-July Suparna Bhattacharya <suparna@in.ibm.com> added jumper probes
+ * interface to access function arguments.
+ * 2004-Sep Prasanna S Panchamukhi <prasanna@in.ibm.com> Changed Kprobes
+ * exceptions notifier to be first on the priority list.
+ */
+#include <linux/kprobes.h>
+#include <linux/spinlock.h>
+#include <linux/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <asm/cacheflush.h>
+#include <asm/errno.h>
+#include <asm/kdebug.h>
+
+#define KPROBE_HASH_BITS 6
+#define KPROBE_TABLE_SIZE (1 << KPROBE_HASH_BITS)
+
+static struct hlist_head kprobe_table[KPROBE_TABLE_SIZE];
+
+unsigned int kprobe_cpu = NR_CPUS;
+static spinlock_t kprobe_lock = SPIN_LOCK_UNLOCKED;
+
+/* Locks kprobe: irqs must be disabled */
+void lock_kprobes(void)
+{
+ spin_lock(&kprobe_lock);
+ kprobe_cpu = smp_processor_id();
+}
+
+void unlock_kprobes(void)
+{
+ kprobe_cpu = NR_CPUS;
+ spin_unlock(&kprobe_lock);
+}
+
+/* You have to be holding the kprobe_lock */
+struct kprobe *get_kprobe(void *addr)
+{
+ struct hlist_head *head;
+ struct hlist_node *node;
+
+ head = &kprobe_table[hash_ptr(addr, KPROBE_HASH_BITS)];
+ hlist_for_each(node, head) {
+ struct kprobe *p = hlist_entry(node, struct kprobe, hlist);
+ if (p->addr == addr)
+ return p;
+ }
+ return NULL;
+}
+
+int register_kprobe(struct kprobe *p)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&kprobe_lock, flags);
+ INIT_HLIST_NODE(&p->hlist);
+ if (get_kprobe(p->addr)) {
+ ret = -EEXIST;
+ goto out;
+ }
+ hlist_add_head(&p->hlist,
+ &kprobe_table[hash_ptr(p->addr, KPROBE_HASH_BITS)]);
+
+ arch_prepare_kprobe(p);
+ p->opcode = *p->addr;
+ *p->addr = BREAKPOINT_INSTRUCTION;
+ flush_icache_range((unsigned long) p->addr,
+ (unsigned long) p->addr + sizeof(kprobe_opcode_t));
+ out:
+ spin_unlock_irqrestore(&kprobe_lock, flags);
+ return ret;
+}
+
+void unregister_kprobe(struct kprobe *p)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&kprobe_lock, flags);
+ *p->addr = p->opcode;
+ hlist_del(&p->hlist);
+ flush_icache_range((unsigned long) p->addr,
+ (unsigned long) p->addr + sizeof(kprobe_opcode_t));
+ spin_unlock_irqrestore(&kprobe_lock, flags);
+}
+
+static struct notifier_block kprobe_exceptions_nb = {
+ .notifier_call = kprobe_exceptions_notify,
+ .priority = 0x7fffffff /* we need to notified first */
+};
+
+int register_jprobe(struct jprobe *jp)
+{
+ /* Todo: Verify probepoint is a function entry point */
+ jp->kp.pre_handler = setjmp_pre_handler;
+ jp->kp.break_handler = longjmp_break_handler;
+
+ return register_kprobe(&jp->kp);
+}
+
+void unregister_jprobe(struct jprobe *jp)
+{
+ unregister_kprobe(&jp->kp);
+}
+
+static int __init init_kprobes(void)
+{
+ int i, err = 0;
+
+ /* FIXME allocate the probe table, currently defined statically */
+ /* initialize all list heads */
+ for (i = 0; i < KPROBE_TABLE_SIZE; i++)
+ INIT_HLIST_HEAD(&kprobe_table[i]);
+
+ err = register_die_notifier(&kprobe_exceptions_nb);
+ return err;
+}
+
+__initcall(init_kprobes);
+
+EXPORT_SYMBOL_GPL(register_kprobe);
+EXPORT_SYMBOL_GPL(unregister_kprobe);
+EXPORT_SYMBOL_GPL(register_jprobe);
+EXPORT_SYMBOL_GPL(unregister_jprobe);
+EXPORT_SYMBOL_GPL(jprobe_return);
--- /dev/null
+/*
+ * Copyright (2004) Linus Torvalds
+ *
+ * Author: Zwane Mwaikambo <zwane@fsmlabs.com>
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <linux/preempt.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+
+int __lockfunc _spin_trylock(spinlock_t *lock)
+{
+ preempt_disable();
+ if (_raw_spin_trylock(lock))
+ return 1;
+
+ preempt_enable();
+ return 0;
+}
+EXPORT_SYMBOL(_spin_trylock);
+
+int __lockfunc _write_trylock(rwlock_t *lock)
+{
+ preempt_disable();
+ if (_raw_write_trylock(lock))
+ return 1;
+
+ preempt_enable();
+ return 0;
+}
+EXPORT_SYMBOL(_write_trylock);
+
+#ifdef CONFIG_PREEMPT
+/*
+ * This could be a long-held lock. If another CPU holds it for a long time,
+ * and that CPU is not asked to reschedule then *this* CPU will spin on the
+ * lock for a long time, even if *this* CPU is asked to reschedule.
+ *
+ * So what we do here, in the slow (contended) path is to spin on the lock by
+ * hand while permitting preemption.
+ *
+ * Called inside preempt_disable().
+ */
+static inline void __preempt_spin_lock(spinlock_t *lock)
+{
+ if (preempt_count() > 1) {
+ _raw_spin_lock(lock);
+ return;
+ }
+
+ do {
+ preempt_enable();
+ while (spin_is_locked(lock))
+ cpu_relax();
+ preempt_disable();
+ } while (!_raw_spin_trylock(lock));
+}
+
+void __lockfunc _spin_lock(spinlock_t *lock)
+{
+ preempt_disable();
+ if (unlikely(!_raw_spin_trylock(lock)))
+ __preempt_spin_lock(lock);
+}
+
+static inline void __preempt_write_lock(rwlock_t *lock)
+{
+ if (preempt_count() > 1) {
+ _raw_write_lock(lock);
+ return;
+ }
+
+ do {
+ preempt_enable();
+ while (rwlock_is_locked(lock))
+ cpu_relax();
+ preempt_disable();
+ } while (!_raw_write_trylock(lock));
+}
+
+void __lockfunc _write_lock(rwlock_t *lock)
+{
+ preempt_disable();
+ if (unlikely(!_raw_write_trylock(lock)))
+ __preempt_write_lock(lock);
+}
+#else
+void __lockfunc _spin_lock(spinlock_t *lock)
+{
+ preempt_disable();
+ _raw_spin_lock(lock);
+}
+
+void __lockfunc _write_lock(rwlock_t *lock)
+{
+ preempt_disable();
+ _raw_write_lock(lock);
+}
+#endif
+EXPORT_SYMBOL(_spin_lock);
+EXPORT_SYMBOL(_write_lock);
+
+void __lockfunc _read_lock(rwlock_t *lock)
+{
+ preempt_disable();
+ _raw_read_lock(lock);
+}
+EXPORT_SYMBOL(_read_lock);
+
+void __lockfunc _spin_unlock(spinlock_t *lock)
+{
+ _raw_spin_unlock(lock);
+ preempt_enable();
+}
+EXPORT_SYMBOL(_spin_unlock);
+
+void __lockfunc _write_unlock(rwlock_t *lock)
+{
+ _raw_write_unlock(lock);
+ preempt_enable();
+}
+EXPORT_SYMBOL(_write_unlock);
+
+void __lockfunc _read_unlock(rwlock_t *lock)
+{
+ _raw_read_unlock(lock);
+ preempt_enable();
+}
+EXPORT_SYMBOL(_read_unlock);
+
+unsigned long __lockfunc _spin_lock_irqsave(spinlock_t *lock)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ preempt_disable();
+ _raw_spin_lock_flags(lock, flags);
+ return flags;
+}
+EXPORT_SYMBOL(_spin_lock_irqsave);
+
+void __lockfunc _spin_lock_irq(spinlock_t *lock)
+{
+ local_irq_disable();
+ preempt_disable();
+ _raw_spin_lock(lock);
+}
+EXPORT_SYMBOL(_spin_lock_irq);
+
+void __lockfunc _spin_lock_bh(spinlock_t *lock)
+{
+ local_bh_disable();
+ preempt_disable();
+ _raw_spin_lock(lock);
+}
+EXPORT_SYMBOL(_spin_lock_bh);
+
+unsigned long __lockfunc _read_lock_irqsave(rwlock_t *lock)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ preempt_disable();
+ _raw_read_lock(lock);
+ return flags;
+}
+EXPORT_SYMBOL(_read_lock_irqsave);
+
+void __lockfunc _read_lock_irq(rwlock_t *lock)
+{
+ local_irq_disable();
+ preempt_disable();
+ _raw_read_lock(lock);
+}
+EXPORT_SYMBOL(_read_lock_irq);
+
+void __lockfunc _read_lock_bh(rwlock_t *lock)
+{
+ local_bh_disable();
+ preempt_disable();
+ _raw_read_lock(lock);
+}
+EXPORT_SYMBOL(_read_lock_bh);
+
+unsigned long __lockfunc _write_lock_irqsave(rwlock_t *lock)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ preempt_disable();
+ _raw_write_lock(lock);
+ return flags;
+}
+EXPORT_SYMBOL(_write_lock_irqsave);
+
+void __lockfunc _write_lock_irq(rwlock_t *lock)
+{
+ local_irq_disable();
+ preempt_disable();
+ _raw_write_lock(lock);
+}
+EXPORT_SYMBOL(_write_lock_irq);
+
+void __lockfunc _write_lock_bh(rwlock_t *lock)
+{
+ local_bh_disable();
+ preempt_disable();
+ _raw_write_lock(lock);
+}
+EXPORT_SYMBOL(_write_lock_bh);
+
+void __lockfunc _spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags)
+{
+ _raw_spin_unlock(lock);
+ local_irq_restore(flags);
+ preempt_enable();
+}
+EXPORT_SYMBOL(_spin_unlock_irqrestore);
+
+void __lockfunc _spin_unlock_irq(spinlock_t *lock)
+{
+ _raw_spin_unlock(lock);
+ local_irq_enable();
+ preempt_enable();
+}
+EXPORT_SYMBOL(_spin_unlock_irq);
+
+void __lockfunc _spin_unlock_bh(spinlock_t *lock)
+{
+ _raw_spin_unlock(lock);
+ preempt_enable();
+ local_bh_enable();
+}
+EXPORT_SYMBOL(_spin_unlock_bh);
+
+void __lockfunc _read_unlock_irqrestore(rwlock_t *lock, unsigned long flags)
+{
+ _raw_read_unlock(lock);
+ local_irq_restore(flags);
+ preempt_enable();
+}
+EXPORT_SYMBOL(_read_unlock_irqrestore);
+
+void __lockfunc _read_unlock_irq(rwlock_t *lock)
+{
+ _raw_read_unlock(lock);
+ local_irq_enable();
+ preempt_enable();
+}
+EXPORT_SYMBOL(_read_unlock_irq);
+
+void __lockfunc _read_unlock_bh(rwlock_t *lock)
+{
+ _raw_read_unlock(lock);
+ preempt_enable();
+ local_bh_enable();
+}
+EXPORT_SYMBOL(_read_unlock_bh);
+
+void __lockfunc _write_unlock_irqrestore(rwlock_t *lock, unsigned long flags)
+{
+ _raw_write_unlock(lock);
+ local_irq_restore(flags);
+ preempt_enable();
+}
+EXPORT_SYMBOL(_write_unlock_irqrestore);
+
+void __lockfunc _write_unlock_irq(rwlock_t *lock)
+{
+ _raw_write_unlock(lock);
+ local_irq_enable();
+ preempt_enable();
+}
+EXPORT_SYMBOL(_write_unlock_irq);
+
+void __lockfunc _write_unlock_bh(rwlock_t *lock)
+{
+ _raw_write_unlock(lock);
+ preempt_enable();
+ local_bh_enable();
+}
+EXPORT_SYMBOL(_write_unlock_bh);
+
+int __lockfunc _spin_trylock_bh(spinlock_t *lock)
+{
+ local_bh_disable();
+ preempt_disable();
+ if (_raw_spin_trylock(lock))
+ return 1;
+
+ preempt_enable();
+ local_bh_enable();
+ return 0;
+}
+EXPORT_SYMBOL(_spin_trylock_bh);
+
+int in_lock_functions(unsigned long addr)
+{
+ /* Linker adds these: start and end of __lockfunc functions */
+ extern char __lock_text_start[], __lock_text_end[];
+
+ return addr >= (unsigned long)__lock_text_start
+ && addr < (unsigned long)__lock_text_end;
+}
+EXPORT_SYMBOL(in_lock_functions);
--- /dev/null
+
+config DEBUG_KERNEL
+ bool "Kernel debugging"
+ depends on (ALPHA || ARM || CRIS || H8300 || X86 || IA64 || M68K || M68KNOMMU || MIPS || PARISC || PPC32 || PPC64 || ARCH_S390 || SUPERH || SUPERH64 || SPARC32 || SPARC64 || USERMODE || V850 || X86_64)
+ help
+ Say Y here if you are developing drivers or trying to debug and
+ identify kernel problems.
+
+config MAGIC_SYSRQ
+ bool "Magic SysRq key"
+ depends on DEBUG_KERNEL && (ALPHA || ARM || X86 || IA64 || M68K || MIPS || PARISC || PPC32 || PPC64 || ARCH_S390 || SUPERH || SUPERH64 || SPARC32 || SPARC64 || X86_64)
+ help
+ If you say Y here, you will have some control over the system even
+ if the system crashes for example during kernel debugging (e.g., you
+ will be able to flush the buffer cache to disk, reboot the system
+ immediately or dump some status information). This is accomplished
+ by pressing various keys while holding SysRq (Alt+PrintScreen). It
+ also works on a serial console (on PC hardware at least), if you
+ send a BREAK and then within 5 seconds a command keypress. The
+ keys are documented in <file:Documentation/sysrq.txt>. Don't say Y
+ unless you really know what this hack does.
+
+config MAGIC_SYSRQ
+ bool "Magic SysRq key"
+ depends on DEBUG_KERNEL && (H8300 || M68KNOMMU || V850)
+ depends (USERMODE && MCONSOLE)
+ help
+ Enables console device to interpret special characters as
+ commands to dump state information.
+
+config DEBUG_SLAB
+ bool "Debug memory allocations"
+ depends on DEBUG_KERNEL && (ALPHA || ARM || X86 || IA64 || M68K || MIPS || PARISC || PPC32 || PPC64 || ARCH_S390 || SPARC32 || SPARC64 || USERMODE || X86_64)
+ help
+ Say Y here to have the kernel do limited verification on memory
+ allocation as well as poisoning memory on free to catch use of freed
+ memory.
+
+config DEBUG_SPINLOCK
+ bool "Spinlock debugging"
+ depends on DEBUG_KERNEL && (ALPHA || ARM || X86 || IA64 || MIPS || PPC32 || (SUPERH && !SUPERH64) || SPARC32 || SPARC64 || USERMODE || X86_64)
+ help
+ Say Y here and build SMP to catch missing spinlock initialization
+ and certain other kinds of spinlock errors commonly made. This is
+ best used in conjunction with the NMI watchdog so that spinlock
+ deadlocks are also debuggable.
+
+config DEBUG_SPINLOCK_SLEEP
+ bool "Sleep-inside-spinlock checking"
+ depends on DEBUG_KERNEL && (X86 || IA64 || MIPS || PPC32 || PPC64 || ARCH_S390 || SPARC32 || SPARC64)
+ help
+ If you say Y here, various routines which may sleep will become very
+ noisy if they are called with a spinlock held.
+
+config DEBUG_HIGHMEM
+ bool "Highmem debugging"
+ depends on DEBUG_KERNEL && HIGHMEM && (X86 || PPC32 || MIPS || SPARC32)
+ help
+ This options enables addition error checking for high memory systems.
+ Disable for production systems.
+
+config DEBUG_BUGVERBOSE
+ bool "Verbose BUG() reporting (adds 70K)"
+ depends on DEBUG_KERNEL && (ARM || ARM26 || M68K || SPARC32 || SPARC64)
+ help
+ Say Y here to make BUG() panics output the file name and line number
+ of the BUG call as well as the EIP and oops trace. This aids
+ debugging but costs about 70-100K of memory.
+
+config DEBUG_INFO
+ bool "Compile the kernel with debug info"
+ depends on DEBUG_KERNEL && (ALPHA || CRIS || X86 || IA64 || M68K || MIPS || PARISC || PPC32 || PPC64 || ARCH_S390 || (SUPERH && !SUPERH64) || SPARC64 || V850 || X86_64)
+ help
+ If you say Y here the resulting kernel image will include
+ debugging info resulting in a larger kernel image.
+ Say Y here only if you plan to use gdb to debug the kernel.
+ If you don't debug the kernel, you can say N.
+
+config DEBUG_INFO
+ bool "Enable kernel debugging symbols"
+ depends on DEBUG_KERNEL && USERMODE
+ help
+ When this is enabled, the User-Mode Linux binary will include
+ debugging symbols. This enlarges the binary by a few megabytes,
+ but aids in tracking down kernel problems in UML. It is required
+ if you intend to do any kernel development.
+
+ If you're truly short on disk space or don't expect to report any
+ bugs back to the UML developers, say N, otherwise say Y.
+
+if !X86_64
+config FRAME_POINTER
+ bool "Compile the kernel with frame pointers"
+ depends on X86 || CRIS || M68KNOMMU || PARISC
+ help
+ If you say Y here the resulting kernel image will be slightly larger
+ and slower, but it will give very useful debugging information.
+ If you don't debug the kernel, you can say N, but we may not be able
+ to solve problems without frame pointers.
+endif
--- /dev/null
+/*
+ * Implement the default iomap interfaces
+ */
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <asm/io.h>
+
+/*
+ * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
+ * access or a MMIO access, these functions don't care. The info is
+ * encoded in the hardware mapping set up by the mapping functions
+ * (or the cookie itself, depending on implementation and hw).
+ *
+ * The generic routines don't assume any hardware mappings, and just
+ * encode the PIO/MMIO as part of the cookie. They coldly assume that
+ * the MMIO IO mappings are not in the low address range.
+ *
+ * Architectures for which this is not true can't use this generic
+ * implementation and should do their own copy.
+ *
+ * We encode the physical PIO addresses (0-0xffff) into the
+ * pointer by offsetting them with a constant (0x10000) and
+ * assuming that all the low addresses are always PIO. That means
+ * we can do some sanity checks on the low bits, and don't
+ * need to just take things for granted.
+ */
+#define PIO_OFFSET 0x10000UL
+#define PIO_MASK 0x0ffffUL
+#define PIO_RESERVED 0x40000UL
+
+/*
+ * Ugly macros are a way of life.
+ */
+#define VERIFY_PIO(port) BUG_ON((port & ~PIO_MASK) != PIO_OFFSET)
+
+#define IO_COND(addr, is_pio, is_mmio) do { \
+ unsigned long port = (unsigned long __force)addr; \
+ if (port < PIO_RESERVED) { \
+ VERIFY_PIO(port); \
+ port &= PIO_MASK; \
+ is_pio; \
+ } else { \
+ is_mmio; \
+ } \
+} while (0)
+
+unsigned int fastcall ioread8(void __iomem *addr)
+{
+ IO_COND(addr, return inb(port), return readb(addr));
+}
+unsigned int fastcall ioread16(void __iomem *addr)
+{
+ IO_COND(addr, return inw(port), return readw(addr));
+}
+unsigned int fastcall ioread32(void __iomem *addr)
+{
+ IO_COND(addr, return inl(port), return readl(addr));
+}
+EXPORT_SYMBOL(ioread8);
+EXPORT_SYMBOL(ioread16);
+EXPORT_SYMBOL(ioread32);
+
+void fastcall iowrite8(u8 val, void __iomem *addr)
+{
+ IO_COND(addr, outb(val,port), writeb(val, addr));
+}
+void fastcall iowrite16(u16 val, void __iomem *addr)
+{
+ IO_COND(addr, outw(val,port), writew(val, addr));
+}
+void fastcall iowrite32(u32 val, void __iomem *addr)
+{
+ IO_COND(addr, outl(val,port), writel(val, addr));
+}
+EXPORT_SYMBOL(iowrite8);
+EXPORT_SYMBOL(iowrite16);
+EXPORT_SYMBOL(iowrite32);
+
+/*
+ * These are the "repeat MMIO read/write" functions.
+ * Note the "__raw" accesses, since we don't want to
+ * convert to CPU byte order. We write in "IO byte
+ * order" (we also don't have IO barriers).
+ */
+static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
+{
+ while (--count >= 0) {
+ u8 data = __raw_readb(addr);
+ *dst = data;
+ dst++;
+ }
+}
+static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
+{
+ while (--count >= 0) {
+ u16 data = __raw_readw(addr);
+ *dst = data;
+ dst++;
+ }
+}
+static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
+{
+ while (--count >= 0) {
+ u32 data = __raw_readl(addr);
+ *dst = data;
+ dst++;
+ }
+}
+
+static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
+{
+ while (--count >= 0) {
+ __raw_writeb(*src, addr);
+ src++;
+ }
+}
+static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
+{
+ while (--count >= 0) {
+ __raw_writew(*src, addr);
+ src++;
+ }
+}
+static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
+{
+ while (--count >= 0) {
+ __raw_writel(*src, addr);
+ src++;
+ }
+}
+
+void fastcall ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
+}
+void fastcall ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
+}
+void fastcall ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+ IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
+}
+EXPORT_SYMBOL(ioread8_rep);
+EXPORT_SYMBOL(ioread16_rep);
+EXPORT_SYMBOL(ioread32_rep);
+
+void fastcall iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
+}
+void fastcall iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
+}
+void fastcall iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+ IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
+}
+EXPORT_SYMBOL(iowrite8_rep);
+EXPORT_SYMBOL(iowrite16_rep);
+EXPORT_SYMBOL(iowrite32_rep);
+
+/* Create a virtual mapping cookie for an IO port range */
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+ if (port > PIO_MASK)
+ return NULL;
+ return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
+}
+
+void ioport_unmap(void __iomem *addr)
+{
+ /* Nothing to do */
+}
+EXPORT_SYMBOL(ioport_map);
+EXPORT_SYMBOL(ioport_unmap);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
+{
+ unsigned long start = pci_resource_start(dev, bar);
+ unsigned long len = pci_resource_len(dev, bar);
+ unsigned long flags = pci_resource_flags(dev, bar);
+
+ if (!len || !start)
+ return NULL;
+ if (maxlen && len > maxlen)
+ len = maxlen;
+ if (flags & IORESOURCE_IO)
+ return ioport_map(start, len);
+ if (flags & IORESOURCE_MEM) {
+ if (flags & IORESOURCE_CACHEABLE)
+ return ioremap(start, len);
+ return ioremap_nocache(start, len);
+ }
+ /* What? */
+ return NULL;
+}
+
+void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
+{
+ IO_COND(addr, /* nothing */, iounmap(addr));
+}
+EXPORT_SYMBOL(pci_iomap);
+EXPORT_SYMBOL(pci_iounmap);
--- /dev/null
+/* inflate.c -- zlib interface to inflate modules
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#include <linux/zutil.h>
+#include "infblock.h"
+#include "infutil.h"
+
+int zlib_inflateSync(
+ z_streamp z
+)
+{
+ uInt n; /* number of bytes to look at */
+ Byte *p; /* pointer to bytes */
+ uInt m; /* number of marker bytes found in a row */
+ uLong r, w; /* temporaries to save total_in and total_out */
+
+ /* set up */
+ if (z == NULL || z->state == NULL)
+ return Z_STREAM_ERROR;
+ if (z->state->mode != I_BAD)
+ {
+ z->state->mode = I_BAD;
+ z->state->sub.marker = 0;
+ }
+ if ((n = z->avail_in) == 0)
+ return Z_BUF_ERROR;
+ p = z->next_in;
+ m = z->state->sub.marker;
+
+ /* search */
+ while (n && m < 4)
+ {
+ static const Byte mark[4] = {0, 0, 0xff, 0xff};
+ if (*p == mark[m])
+ m++;
+ else if (*p)
+ m = 0;
+ else
+ m = 4 - m;
+ p++, n--;
+ }
+
+ /* restore */
+ z->total_in += p - z->next_in;
+ z->next_in = p;
+ z->avail_in = n;
+ z->state->sub.marker = m;
+
+ /* return no joy or set up to restart on a new block */
+ if (m != 4)
+ return Z_DATA_ERROR;
+ r = z->total_in; w = z->total_out;
+ zlib_inflateReset(z);
+ z->total_in = r; z->total_out = w;
+ z->state->mode = BLOCKS;
+ return Z_OK;
+}
+
+
+/* Returns true if inflate is currently at the end of a block generated
+ * by Z_SYNC_FLUSH or Z_FULL_FLUSH. This function is used by one PPP
+ * implementation to provide an additional safety check. PPP uses Z_SYNC_FLUSH
+ * but removes the length bytes of the resulting empty stored block. When
+ * decompressing, PPP checks that at the end of input packet, inflate is
+ * waiting for these length bytes.
+ */
+int zlib_inflateSyncPoint(
+ z_streamp z
+)
+{
+ if (z == NULL || z->state == NULL || z->state->blocks == NULL)
+ return Z_STREAM_ERROR;
+ return zlib_inflate_blocks_sync_point(z->state->blocks);
+}
+
+/*
+ * This subroutine adds the data at next_in/avail_in to the output history
+ * without performing any output. The output buffer must be "caught up";
+ * i.e. no pending output (hence s->read equals s->write), and the state must
+ * be BLOCKS (i.e. we should be willing to see the start of a series of
+ * BLOCKS). On exit, the output will also be caught up, and the checksum
+ * will have been updated if need be.
+ */
+static int zlib_inflate_addhistory(inflate_blocks_statef *s,
+ z_stream *z)
+{
+ uLong b; /* bit buffer */ /* NOT USED HERE */
+ uInt k; /* bits in bit buffer */ /* NOT USED HERE */
+ uInt t; /* temporary storage */
+ Byte *p; /* input data pointer */
+ uInt n; /* bytes available there */
+ Byte *q; /* output window write pointer */
+ uInt m; /* bytes to end of window or read pointer */
+
+ if (s->read != s->write)
+ return Z_STREAM_ERROR;
+ if (s->mode != TYPE)
+ return Z_DATA_ERROR;
+
+ /* we're ready to rock */
+ LOAD
+ /* while there is input ready, copy to output buffer, moving
+ * pointers as needed.
+ */
+ while (n) {
+ t = n; /* how many to do */
+ /* is there room until end of buffer? */
+ if (t > m) t = m;
+ /* update check information */
+ if (s->checkfn != NULL)
+ s->check = (*s->checkfn)(s->check, q, t);
+ memcpy(q, p, t);
+ q += t;
+ p += t;
+ n -= t;
+ z->total_out += t;
+ s->read = q; /* drag read pointer forward */
+/* WWRAP */ /* expand WWRAP macro by hand to handle s->read */
+ if (q == s->end) {
+ s->read = q = s->window;
+ m = WAVAIL;
+ }
+ }
+ UPDATE
+ return Z_OK;
+}
+
+
+/*
+ * This subroutine adds the data at next_in/avail_in to the output history
+ * without performing any output. The output buffer must be "caught up";
+ * i.e. no pending output (hence s->read equals s->write), and the state must
+ * be BLOCKS (i.e. we should be willing to see the start of a series of
+ * BLOCKS). On exit, the output will also be caught up, and the checksum
+ * will have been updated if need be.
+ */
+
+int zlib_inflateIncomp(
+ z_stream *z
+
+)
+{
+ if (z->state->mode != BLOCKS)
+ return Z_DATA_ERROR;
+ return zlib_inflate_addhistory(z->state->blocks, z);
+}
--- /dev/null
+/*
+ * mm/thrash.c
+ *
+ * Copyright (C) 2004, Red Hat, Inc.
+ * Copyright (C) 2004, Rik van Riel <riel@redhat.com>
+ * Released under the GPL, see the file COPYING for details.
+ *
+ * Simple token based thrashing protection, using the algorithm
+ * described in: http://www.cs.wm.edu/~sjiang/token.pdf
+ */
+#include <linux/jiffies.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/swap.h>
+
+static spinlock_t swap_token_lock = SPIN_LOCK_UNLOCKED;
+static unsigned long swap_token_timeout;
+unsigned long swap_token_check;
+struct mm_struct * swap_token_mm = &init_mm;
+
+#define SWAP_TOKEN_CHECK_INTERVAL (HZ * 2)
+#define SWAP_TOKEN_TIMEOUT (HZ * 300)
+
+/*
+ * Take the token away if the process had no page faults
+ * in the last interval, or if it has held the token for
+ * too long.
+ */
+#define SWAP_TOKEN_ENOUGH_RSS 1
+#define SWAP_TOKEN_TIMED_OUT 2
+static int should_release_swap_token(struct mm_struct *mm)
+{
+ int ret = 0;
+ if (!mm->recent_pagein)
+ ret = SWAP_TOKEN_ENOUGH_RSS;
+ else if (time_after(jiffies, swap_token_timeout))
+ ret = SWAP_TOKEN_TIMED_OUT;
+ mm->recent_pagein = 0;
+ return ret;
+}
+
+/*
+ * Try to grab the swapout protection token. We only try to
+ * grab it once every TOKEN_CHECK_INTERVAL, both to prevent
+ * SMP lock contention and to check that the process that held
+ * the token before is no longer thrashing.
+ */
+void grab_swap_token(void)
+{
+ struct mm_struct *mm;
+ int reason;
+
+ /* We have the token. Let others know we still need it. */
+ if (has_swap_token(current->mm)) {
+ current->mm->recent_pagein = 1;
+ return;
+ }
+
+ if (time_after(jiffies, swap_token_check)) {
+
+ /* Can't get swapout protection if we exceed our RSS limit. */
+ // if (current->mm->rss > current->mm->rlimit_rss)
+ // return;
+
+ /* ... or if we recently held the token. */
+ if (time_before(jiffies, current->mm->swap_token_time))
+ return;
+
+ if (!spin_trylock(&swap_token_lock))
+ return;
+
+ swap_token_check = jiffies + SWAP_TOKEN_CHECK_INTERVAL;
+
+ mm = swap_token_mm;
+ if ((reason = should_release_swap_token(mm))) {
+ unsigned long eligible = jiffies;
+ if (reason == SWAP_TOKEN_TIMED_OUT) {
+ eligible += SWAP_TOKEN_TIMEOUT;
+ }
+ mm->swap_token_time = eligible;
+ swap_token_timeout = jiffies + SWAP_TOKEN_TIMEOUT;
+ swap_token_mm = current->mm;
+ }
+ spin_unlock(&swap_token_lock);
+ }
+ return;
+}
+
+/* Called on process exit. */
+void __put_swap_token(struct mm_struct *mm)
+{
+ spin_lock(&swap_token_lock);
+ if (likely(mm == swap_token_mm)) {
+ swap_token_mm = &init_mm;
+ swap_token_check = jiffies;
+ }
+ spin_unlock(&swap_token_lock);
+}
--- /dev/null
+/*
+ * tiny-shmem.c: simple shmemfs and tmpfs using ramfs code
+ *
+ * Matt Mackall <mpm@selenic.com> January, 2004
+ * derived from mm/shmem.c and fs/ramfs/inode.c
+ *
+ * This is intended for small system where the benefits of the full
+ * shmem code (swap-backed and resource-limited) are outweighed by
+ * their complexity. On systems without swap this code should be
+ * effectively equivalent, but much lighter weight.
+ */
+
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/vfs.h>
+#include <linux/mount.h>
+#include <linux/file.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/swap.h>
+#include <linux/ramfs.h>
+
+static struct file_system_type tmpfs_fs_type = {
+ .name = "tmpfs",
+ .get_sb = ramfs_get_sb,
+ .kill_sb = kill_litter_super,
+};
+
+static struct vfsmount *shm_mnt;
+
+static int __init init_tmpfs(void)
+{
+ register_filesystem(&tmpfs_fs_type);
+#ifdef CONFIG_TMPFS
+ devfs_mk_dir("shm");
+#endif
+ shm_mnt = kern_mount(&tmpfs_fs_type);
+ return 0;
+}
+module_init(init_tmpfs)
+
+/*
+ * shmem_file_setup - get an unlinked file living in tmpfs
+ *
+ * @name: name for dentry (to be seen in /proc/<pid>/maps
+ * @size: size to be set for the file
+ *
+ */
+struct file *shmem_file_setup(char *name, loff_t size, unsigned long flags)
+{
+ int error;
+ struct file *file;
+ struct inode *inode;
+ struct dentry *dentry, *root;
+ struct qstr this;
+
+ if (IS_ERR(shm_mnt))
+ return (void *)shm_mnt;
+
+ error = -ENOMEM;
+ this.name = name;
+ this.len = strlen(name);
+ this.hash = 0; /* will go */
+ root = shm_mnt->mnt_root;
+ dentry = d_alloc(root, &this);
+ if (!dentry)
+ goto put_memory;
+
+ error = -ENFILE;
+ file = get_empty_filp();
+ if (!file)
+ goto put_dentry;
+
+ error = -ENOSPC;
+ inode = ramfs_get_inode(root->d_sb, S_IFREG | S_IRWXUGO, 0);
+ if (!inode)
+ goto close_file;
+
+ d_instantiate(dentry, inode);
+ inode->i_size = size;
+ inode->i_nlink = 0; /* It is unlinked */
+ file->f_vfsmnt = mntget(shm_mnt);
+ file->f_dentry = dentry;
+ file->f_mapping = inode->i_mapping;
+ file->f_op = &ramfs_file_operations;
+ file->f_mode = FMODE_WRITE | FMODE_READ;
+ return file;
+
+close_file:
+ put_filp(file);
+put_dentry:
+ dput(dentry);
+put_memory:
+ return ERR_PTR(error);
+}
+
+/*
+ * shmem_zero_setup - setup a shared anonymous mapping
+ *
+ * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
+ */
+int shmem_zero_setup(struct vm_area_struct *vma)
+{
+ struct file *file;
+ loff_t size = vma->vm_end - vma->vm_start;
+
+ file = shmem_file_setup("dev/zero", size, vma->vm_flags);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ if (vma->vm_file)
+ fput(vma->vm_file);
+ vma->vm_file = file;
+ vma->vm_ops = &generic_file_vm_ops;
+ return 0;
+}
+
+int shmem_unuse(swp_entry_t entry, struct page *page)
+{
+ return 0;
+}
+
+EXPORT_SYMBOL(shmem_file_setup);
--- /dev/null
+/*
+ * net/sched/gen_estimator.c Simple rate estimator.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Authors: Alexey Kuznetsov, <kuznet@ms2.inr.ac.ru>
+ *
+ * Changes:
+ * Jamal Hadi Salim - moved it to net/core and reshulfed
+ * names to make it usable in general net subsystem.
+ */
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/jiffies.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/socket.h>
+#include <linux/sockios.h>
+#include <linux/in.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/rtnetlink.h>
+#include <linux/init.h>
+#include <net/sock.h>
+#include <net/gen_stats.h>
+
+/*
+ This code is NOT intended to be used for statistics collection,
+ its purpose is to provide a base for statistical multiplexing
+ for controlled load service.
+ If you need only statistics, run a user level daemon which
+ periodically reads byte counters.
+
+ Unfortunately, rate estimation is not a very easy task.
+ F.e. I did not find a simple way to estimate the current peak rate
+ and even failed to formulate the problem 8)8)
+
+ So I preferred not to built an estimator into the scheduler,
+ but run this task separately.
+ Ideally, it should be kernel thread(s), but for now it runs
+ from timers, which puts apparent top bounds on the number of rated
+ flows, has minimal overhead on small, but is enough
+ to handle controlled load service, sets of aggregates.
+
+ We measure rate over A=(1<<interval) seconds and evaluate EWMA:
+
+ avrate = avrate*(1-W) + rate*W
+
+ where W is chosen as negative power of 2: W = 2^(-ewma_log)
+
+ The resulting time constant is:
+
+ T = A/(-ln(1-W))
+
+
+ NOTES.
+
+ * The stored value for avbps is scaled by 2^5, so that maximal
+ rate is ~1Gbit, avpps is scaled by 2^10.
+
+ * Minimal interval is HZ/4=250msec (it is the greatest common divisor
+ for HZ=100 and HZ=1024 8)), maximal interval
+ is (HZ*2^EST_MAX_INTERVAL)/4 = 8sec. Shorter intervals
+ are too expensive, longer ones can be implemented
+ at user level painlessly.
+ */
+
+#define EST_MAX_INTERVAL 5
+
+struct gen_estimator
+{
+ struct gen_estimator *next;
+ struct gnet_stats_basic *bstats;
+ struct gnet_stats_rate_est *rate_est;
+ spinlock_t *stats_lock;
+ unsigned interval;
+ int ewma_log;
+ u64 last_bytes;
+ u32 last_packets;
+ u32 avpps;
+ u32 avbps;
+};
+
+struct gen_estimator_head
+{
+ struct timer_list timer;
+ struct gen_estimator *list;
+};
+
+static struct gen_estimator_head elist[EST_MAX_INTERVAL+1];
+
+/* Estimator array lock */
+static rwlock_t est_lock = RW_LOCK_UNLOCKED;
+
+static void est_timer(unsigned long arg)
+{
+ int idx = (int)arg;
+ struct gen_estimator *e;
+
+ read_lock(&est_lock);
+ for (e = elist[idx].list; e; e = e->next) {
+ u64 nbytes;
+ u32 npackets;
+ u32 rate;
+
+ spin_lock(e->stats_lock);
+ nbytes = e->bstats->bytes;
+ npackets = e->bstats->packets;
+ rate = (nbytes - e->last_bytes)<<(7 - idx);
+ e->last_bytes = nbytes;
+ e->avbps += ((long)rate - (long)e->avbps) >> e->ewma_log;
+ e->rate_est->bps = (e->avbps+0xF)>>5;
+
+ rate = (npackets - e->last_packets)<<(12 - idx);
+ e->last_packets = npackets;
+ e->avpps += ((long)rate - (long)e->avpps) >> e->ewma_log;
+ e->rate_est->pps = (e->avpps+0x1FF)>>10;
+ spin_unlock(e->stats_lock);
+ }
+
+ mod_timer(&elist[idx].timer, jiffies + ((HZ<<idx)/4));
+ read_unlock(&est_lock);
+}
+
+int gen_new_estimator(struct gnet_stats_basic *bstats,
+ struct gnet_stats_rate_est *rate_est, spinlock_t *stats_lock, struct rtattr *opt)
+{
+ struct gen_estimator *est;
+ struct gnet_estimator *parm = RTA_DATA(opt);
+
+ if (RTA_PAYLOAD(opt) < sizeof(*parm))
+ return -EINVAL;
+
+ if (parm->interval < -2 || parm->interval > 3)
+ return -EINVAL;
+
+ est = kmalloc(sizeof(*est), GFP_KERNEL);
+ if (est == NULL)
+ return -ENOBUFS;
+
+ memset(est, 0, sizeof(*est));
+ est->interval = parm->interval + 2;
+ est->bstats = bstats;
+ est->rate_est = rate_est;
+ est->stats_lock = stats_lock;
+ est->ewma_log = parm->ewma_log;
+ est->last_bytes = bstats->bytes;
+ est->avbps = rate_est->bps<<5;
+ est->last_packets = bstats->packets;
+ est->avpps = rate_est->pps<<10;
+
+ est->next = elist[est->interval].list;
+ if (est->next == NULL) {
+ init_timer(&elist[est->interval].timer);
+ elist[est->interval].timer.data = est->interval;
+ elist[est->interval].timer.expires = jiffies + ((HZ<<est->interval)/4);
+ elist[est->interval].timer.function = est_timer;
+ add_timer(&elist[est->interval].timer);
+ }
+ write_lock_bh(&est_lock);
+ elist[est->interval].list = est;
+ write_unlock_bh(&est_lock);
+ return 0;
+}
+
+void gen_kill_estimator(struct gnet_stats_basic *bstats,
+ struct gnet_stats_rate_est *rate_est)
+{
+ int idx;
+ struct gen_estimator *est, **pest;
+
+ for (idx=0; idx <= EST_MAX_INTERVAL; idx++) {
+ int killed = 0;
+ pest = &elist[idx].list;
+ while ((est=*pest) != NULL) {
+ if (est->rate_est != rate_est || est->bstats != bstats) {
+ pest = &est->next;
+ continue;
+ }
+
+ write_lock_bh(&est_lock);
+ *pest = est->next;
+ write_unlock_bh(&est_lock);
+
+ kfree(est);
+ killed++;
+ }
+ if (killed && elist[idx].list == NULL)
+ del_timer(&elist[idx].timer);
+ }
+}
+
+EXPORT_SYMBOL(gen_kill_estimator);
+EXPORT_SYMBOL(gen_new_estimator);
--- /dev/null
+/*
+ * net/core/gen_stats.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Authors: Thomas Graf <tgraf@suug.ch>
+ * Jamal Hadi Salim
+ * Alexey Kuznetsov, <kuznet@ms2.inr.ac.ru>
+ *
+ * See Documentation/networking/gen_stats.txt
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/socket.h>
+#include <linux/rtnetlink.h>
+#include <linux/gen_stats.h>
+#include <net/gen_stats.h>
+
+
+static inline int
+gnet_stats_copy(struct gnet_dump *d, int type, void *buf, int size)
+{
+ RTA_PUT(d->skb, type, size, buf);
+ return 0;
+
+rtattr_failure:
+ spin_unlock_bh(d->lock);
+ return -1;
+}
+
+int
+gnet_stats_start_copy_compat(struct sk_buff *skb, int type, int tc_stats_type,
+ int xstats_type, spinlock_t *lock, struct gnet_dump *d)
+{
+ spin_lock_bh(lock);
+ d->lock = lock;
+ d->tail = (struct rtattr *) skb->tail;
+ d->skb = skb;
+ d->compat_tc_stats = tc_stats_type;
+ d->compat_xstats = xstats_type;
+ d->xstats = NULL;
+
+ if (d->compat_tc_stats)
+ memset(&d->tc_stats, 0, sizeof(d->tc_stats));
+
+ return gnet_stats_copy(d, type, NULL, 0);
+}
+
+int
+gnet_stats_start_copy(struct sk_buff *skb, int type, spinlock_t *lock,
+ struct gnet_dump *d)
+{
+ return gnet_stats_start_copy_compat(skb, type, 0, 0, lock, d);
+}
+
+
+int
+gnet_stats_copy_basic(struct gnet_dump *d, struct gnet_stats_basic *b)
+{
+ if (d->compat_tc_stats) {
+ d->tc_stats.bytes = b->bytes;
+ d->tc_stats.packets = b->packets;
+ }
+
+ return gnet_stats_copy(d, TCA_STATS_BASIC, b, sizeof(*b));
+}
+
+int
+gnet_stats_copy_rate_est(struct gnet_dump *d, struct gnet_stats_rate_est *r)
+{
+ if (d->compat_tc_stats) {
+ d->tc_stats.bps = r->bps;
+ d->tc_stats.pps = r->pps;
+ }
+
+ return gnet_stats_copy(d, TCA_STATS_RATE_EST, r, sizeof(*r));
+}
+
+int
+gnet_stats_copy_queue(struct gnet_dump *d, struct gnet_stats_queue *q)
+{
+ if (d->compat_tc_stats) {
+ d->tc_stats.drops = q->drops;
+ d->tc_stats.qlen = q->qlen;
+ d->tc_stats.backlog = q->backlog;
+ d->tc_stats.overlimits = q->overlimits;
+ }
+
+ return gnet_stats_copy(d, TCA_STATS_QUEUE, q, sizeof(*q));
+}
+
+int
+gnet_stats_copy_app(struct gnet_dump *d, void *st, int len)
+{
+ if (d->compat_xstats)
+ d->xstats = (struct rtattr *) d->skb->tail;
+ return gnet_stats_copy(d, TCA_STATS_APP, st, len);
+}
+
+int
+gnet_stats_finish_copy(struct gnet_dump *d)
+{
+ d->tail->rta_len = d->skb->tail - (u8 *) d->tail;
+
+ if (d->compat_tc_stats)
+ if (gnet_stats_copy(d, d->compat_tc_stats, &d->tc_stats,
+ sizeof(d->tc_stats)) < 0)
+ return -1;
+
+ if (d->compat_xstats && d->xstats) {
+ if (gnet_stats_copy(d, d->compat_xstats, RTA_DATA(d->xstats),
+ RTA_PAYLOAD(d->xstats)) < 0)
+ return -1;
+ }
+
+ spin_unlock_bh(d->lock);
+ return 0;
+}
+
+
+EXPORT_SYMBOL(gnet_stats_start_copy);
+EXPORT_SYMBOL(gnet_stats_copy_basic);
+EXPORT_SYMBOL(gnet_stats_copy_rate_est);
+EXPORT_SYMBOL(gnet_stats_copy_queue);
+EXPORT_SYMBOL(gnet_stats_copy_app);
+EXPORT_SYMBOL(gnet_stats_finish_copy);
--- /dev/null
+#ifndef _FIB_LOOKUP_H
+#define _FIB_LOOKUP_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+#include <net/ip_fib.h>
+
+struct fib_alias {
+ struct list_head fa_list;
+ struct fib_info *fa_info;
+ u8 fa_tos;
+ u8 fa_type;
+ u8 fa_scope;
+ u8 fa_state;
+};
+
+#define FA_S_ACCESSED 0x01
+
+/* Exported by fib_semantics.c */
+extern int fib_semantic_match(struct list_head *head,
+ const struct flowi *flp,
+ struct fib_result *res, int prefixlen);
+extern void fib_release_info(struct fib_info *);
+extern struct fib_info *fib_create_info(const struct rtmsg *r,
+ struct kern_rta *rta,
+ const struct nlmsghdr *,
+ int *err);
+extern int fib_nh_match(struct rtmsg *r, struct nlmsghdr *,
+ struct kern_rta *rta, struct fib_info *fi);
+extern int fib_dump_info(struct sk_buff *skb, u32 pid, u32 seq, int event,
+ u8 tb_id, u8 type, u8 scope, void *dst,
+ int dst_len, u8 tos, struct fib_info *fi);
+
+#endif /* _FIB_LOOKUP_H */
--- /dev/null
+/*
+ * ip_conntrack_proto_gre.c - Version 2.0
+ *
+ * Connection tracking protocol helper module for GRE.
+ *
+ * GRE is a generic encapsulation protocol, which is generally not very
+ * suited for NAT, as it has no protocol-specific part as port numbers.
+ *
+ * It has an optional key field, which may help us distinguishing two
+ * connections between the same two hosts.
+ *
+ * GRE is defined in RFC 1701 and RFC 1702, as well as RFC 2784
+ *
+ * PPTP is built on top of a modified version of GRE, and has a mandatory
+ * field called "CallID", which serves us for the same purpose as the key
+ * field in plain GRE.
+ *
+ * Documentation about PPTP can be found in RFC 2637
+ *
+ * (C) 2000-2004 by Harald Welte <laforge@gnumonks.org>
+ *
+ * Development of this code funded by Astaro AG (http://www.astaro.com/)
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <linux/netfilter.h>
+#include <linux/ip.h>
+#include <linux/in.h>
+#include <linux/list.h>
+
+#include <linux/netfilter_ipv4/lockhelp.h>
+
+DECLARE_RWLOCK(ip_ct_gre_lock);
+#define ASSERT_READ_LOCK(x) MUST_BE_READ_LOCKED(&ip_ct_gre_lock)
+#define ASSERT_WRITE_LOCK(x) MUST_BE_WRITE_LOCKED(&ip_ct_gre_lock)
+
+#include <linux/netfilter_ipv4/listhelp.h>
+#include <linux/netfilter_ipv4/ip_conntrack_protocol.h>
+#include <linux/netfilter_ipv4/ip_conntrack_helper.h>
+#include <linux/netfilter_ipv4/ip_conntrack_core.h>
+
+#include <linux/netfilter_ipv4/ip_conntrack_proto_gre.h>
+#include <linux/netfilter_ipv4/ip_conntrack_pptp.h>
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Harald Welte <laforge@gnumonks.org>");
+MODULE_DESCRIPTION("netfilter connection tracking protocol helper for GRE");
+
+/* shamelessly stolen from ip_conntrack_proto_udp.c */
+#define GRE_TIMEOUT (30*HZ)
+#define GRE_STREAM_TIMEOUT (180*HZ)
+
+#if 0
+#define DEBUGP(format, args...) printk(KERN_DEBUG __FILE__ ":" __FUNCTION__ \
+ ": " format, ## args)
+#define DUMP_TUPLE_GRE(x) printk("%u.%u.%u.%u:0x%x -> %u.%u.%u.%u:0x%x:%u:0x%x\n", \
+ NIPQUAD((x)->src.ip), ntohl((x)->src.u.gre.key), \
+ NIPQUAD((x)->dst.ip), ntohl((x)->dst.u.gre.key))
+#else
+#define DEBUGP(x, args...)
+#define DUMP_TUPLE_GRE(x)
+#endif
+
+/* GRE KEYMAP HANDLING FUNCTIONS */
+static LIST_HEAD(gre_keymap_list);
+
+static inline int gre_key_cmpfn(const struct ip_ct_gre_keymap *km,
+ const struct ip_conntrack_tuple *t)
+{
+ return ((km->tuple.src.ip == t->src.ip) &&
+ (km->tuple.dst.ip == t->dst.ip) &&
+ (km->tuple.dst.protonum == t->dst.protonum) &&
+ (km->tuple.dst.u.all == t->dst.u.all));
+}
+
+/* look up the source key for a given tuple */
+static u_int32_t gre_keymap_lookup(struct ip_conntrack_tuple *t)
+{
+ struct ip_ct_gre_keymap *km;
+ u_int32_t key;
+
+ READ_LOCK(&ip_ct_gre_lock);
+ km = LIST_FIND(&gre_keymap_list, gre_key_cmpfn,
+ struct ip_ct_gre_keymap *, t);
+ if (!km) {
+ READ_UNLOCK(&ip_ct_gre_lock);
+ return 0;
+ }
+
+ key = km->tuple.src.u.gre.key;
+ READ_UNLOCK(&ip_ct_gre_lock);
+
+ return key;
+}
+
+/* add a single keymap entry, associate with specified expect */
+int ip_ct_gre_keymap_add(struct ip_conntrack_expect *exp,
+ struct ip_conntrack_tuple *t, int reply)
+{
+ struct ip_ct_gre_keymap *km;
+
+ km = kmalloc(sizeof(*km), GFP_ATOMIC);
+ if (!km)
+ return -1;
+
+ /* initializing list head should be sufficient */
+ memset(km, 0, sizeof(*km));
+
+ memcpy(&km->tuple, t, sizeof(*t));
+
+ if (!reply)
+ exp->proto.gre.keymap_orig = km;
+ else
+ exp->proto.gre.keymap_reply = km;
+
+ DEBUGP("adding new entry %p: ", km);
+ DUMP_TUPLE_GRE(&km->tuple);
+
+ WRITE_LOCK(&ip_ct_gre_lock);
+ list_append(&gre_keymap_list, km);
+ WRITE_UNLOCK(&ip_ct_gre_lock);
+
+ return 0;
+}
+
+/* change the tuple of a keymap entry (used by nat helper) */
+void ip_ct_gre_keymap_change(struct ip_ct_gre_keymap *km,
+ struct ip_conntrack_tuple *t)
+{
+ DEBUGP("changing entry %p to: ", km);
+ DUMP_TUPLE_GRE(t);
+
+ WRITE_LOCK(&ip_ct_gre_lock);
+ memcpy(&km->tuple, t, sizeof(km->tuple));
+ WRITE_UNLOCK(&ip_ct_gre_lock);
+}
+
+/* destroy the keymap entries associated with specified expect */
+void ip_ct_gre_keymap_destroy(struct ip_conntrack_expect *exp)
+{
+ DEBUGP("entering for exp %p\n", exp);
+ WRITE_LOCK(&ip_ct_gre_lock);
+ if (exp->proto.gre.keymap_orig) {
+ DEBUGP("removing %p from list\n", exp->proto.gre.keymap_orig);
+ list_del(&exp->proto.gre.keymap_orig->list);
+ kfree(exp->proto.gre.keymap_orig);
+ exp->proto.gre.keymap_orig = NULL;
+ }
+ if (exp->proto.gre.keymap_reply) {
+ DEBUGP("removing %p from list\n", exp->proto.gre.keymap_reply);
+ list_del(&exp->proto.gre.keymap_reply->list);
+ kfree(exp->proto.gre.keymap_reply);
+ exp->proto.gre.keymap_reply = NULL;
+ }
+ WRITE_UNLOCK(&ip_ct_gre_lock);
+}
+
+
+/* PUBLIC CONNTRACK PROTO HELPER FUNCTIONS */
+
+/* invert gre part of tuple */
+static int gre_invert_tuple(struct ip_conntrack_tuple *tuple,
+ const struct ip_conntrack_tuple *orig)
+{
+ tuple->dst.u.gre.key = orig->src.u.gre.key;
+ tuple->src.u.gre.key = orig->dst.u.gre.key;
+
+ return 1;
+}
+
+/* gre hdr info to tuple */
+static int gre_pkt_to_tuple(const struct sk_buff *skb,
+ unsigned int dataoff,
+ struct ip_conntrack_tuple *tuple)
+{
+ struct gre_hdr _grehdr, *grehdr;
+ struct gre_hdr_pptp _pgrehdr, *pgrehdr;
+ u_int32_t srckey;
+
+ grehdr = skb_header_pointer(skb, dataoff, sizeof(_grehdr), &_grehdr);
+ pgrehdr = skb_header_pointer(skb, dataoff, sizeof(_pgrehdr), &_pgrehdr);
+
+ if (!grehdr || !pgrehdr)
+ return 0;
+
+ switch (grehdr->version) {
+ case GRE_VERSION_1701:
+ if (!grehdr->key) {
+ DEBUGP("Can't track GRE without key\n");
+ return 0;
+ }
+ tuple->dst.u.gre.key = *(gre_key(grehdr));
+ break;
+
+ case GRE_VERSION_PPTP:
+ if (ntohs(grehdr->protocol) != GRE_PROTOCOL_PPTP) {
+ DEBUGP("GRE_VERSION_PPTP but unknown proto\n");
+ return 0;
+ }
+ tuple->dst.u.gre.key = htonl(ntohs(pgrehdr->call_id));
+ break;
+
+ default:
+ printk(KERN_WARNING "unknown GRE version %hu\n",
+ grehdr->version);
+ return 0;
+ }
+
+ srckey = gre_keymap_lookup(tuple);
+
+#if 0
+ DEBUGP("found src key %x for tuple ", ntohl(srckey));
+ DUMP_TUPLE_GRE(tuple);
+#endif
+ tuple->src.u.gre.key = srckey;
+
+ return 1;
+}
+
+/* print gre part of tuple */
+static int gre_print_tuple(struct seq_file *s,
+ const struct ip_conntrack_tuple *tuple)
+{
+ return seq_printf(s, "srckey=0x%x dstkey=0x%x ",
+ ntohl(tuple->src.u.gre.key),
+ ntohl(tuple->dst.u.gre.key));
+}
+
+/* print private data for conntrack */
+static int gre_print_conntrack(struct seq_file *s,
+ const struct ip_conntrack *ct)
+{
+ return seq_printf(s, "timeout=%u, stream_timeout=%u ",
+ (ct->proto.gre.timeout / HZ),
+ (ct->proto.gre.stream_timeout / HZ));
+}
+
+/* Returns verdict for packet, and may modify conntrack */
+static int gre_packet(struct ip_conntrack *ct,
+ const struct sk_buff *skb,
+ enum ip_conntrack_info conntrackinfo)
+{
+ /* If we've seen traffic both ways, this is a GRE connection.
+ * Extend timeout. */
+ if (ct->status & IPS_SEEN_REPLY) {
+ ip_ct_refresh_acct(ct, conntrackinfo, skb,
+ ct->proto.gre.stream_timeout);
+ /* Also, more likely to be important, and not a probe. */
+ set_bit(IPS_ASSURED_BIT, &ct->status);
+ } else
+ ip_ct_refresh_acct(ct, conntrackinfo, skb,
+ ct->proto.gre.timeout);
+
+ return NF_ACCEPT;
+}
+
+/* Called when a new connection for this protocol found. */
+static int gre_new(struct ip_conntrack *ct,
+ const struct sk_buff *skb)
+{
+ DEBUGP(": ");
+ DUMP_TUPLE_GRE(&ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
+
+ /* initialize to sane value. Ideally a conntrack helper
+ * (e.g. in case of pptp) is increasing them */
+ ct->proto.gre.stream_timeout = GRE_STREAM_TIMEOUT;
+ ct->proto.gre.timeout = GRE_TIMEOUT;
+
+ return 1;
+}
+
+/* Called when a conntrack entry has already been removed from the hashes
+ * and is about to be deleted from memory */
+static void gre_destroy(struct ip_conntrack *ct)
+{
+ struct ip_conntrack_expect *master = ct->master;
+
+ DEBUGP(" entering\n");
+
+ if (!master) {
+ DEBUGP("no master exp for ct %p\n", ct);
+ return;
+ }
+
+ ip_ct_gre_keymap_destroy(master);
+}
+
+/* protocol helper struct */
+static struct ip_conntrack_protocol gre = {
+ .proto = IPPROTO_GRE,
+ .name = "gre",
+ .pkt_to_tuple = gre_pkt_to_tuple,
+ .invert_tuple = gre_invert_tuple,
+ .print_tuple = gre_print_tuple,
+ .print_conntrack = gre_print_conntrack,
+ .packet = gre_packet,
+ .new = gre_new,
+ .destroy = gre_destroy,
+ .exp_matches_pkt = NULL,
+ .me = THIS_MODULE
+};
+
+/* ip_conntrack_proto_gre initialization */
+static int __init init(void)
+{
+ int retcode;
+
+ if ((retcode = ip_conntrack_protocol_register(&gre))) {
+ printk(KERN_ERR "Unable to register conntrack protocol "
+ "helper for gre: %d\n", retcode);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void __exit fini(void)
+{
+ struct list_head *pos, *n;
+
+ /* delete all keymap entries */
+ WRITE_LOCK(&ip_ct_gre_lock);
+ list_for_each_safe(pos, n, &gre_keymap_list) {
+ DEBUGP("deleting keymap %p at module unload time\n", pos);
+ list_del(pos);
+ kfree(pos);
+ }
+ WRITE_UNLOCK(&ip_ct_gre_lock);
+
+ ip_conntrack_protocol_unregister(&gre);
+}
+
+EXPORT_SYMBOL(ip_ct_gre_keymap_add);
+EXPORT_SYMBOL(ip_ct_gre_keymap_change);
+EXPORT_SYMBOL(ip_ct_gre_keymap_destroy);
+
+module_init(init);
+module_exit(fini);
--- /dev/null
+/*
+ * Connection tracking protocol helper module for SCTP.
+ *
+ * SCTP is defined in RFC 2960. References to various sections in this code
+ * are to this RFC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Added support for proc manipulation of timeouts.
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/netfilter.h>
+#include <linux/module.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/sctp.h>
+#include <linux/string.h>
+#include <linux/seq_file.h>
+
+#include <linux/netfilter_ipv4/ip_conntrack.h>
+#include <linux/netfilter_ipv4/ip_conntrack_protocol.h>
+#include <linux/netfilter_ipv4/lockhelp.h>
+
+#if 0
+#define DEBUGP(format, ...) printk(format, ## __VA_ARGS__)
+#else
+#define DEBUGP(format, args...)
+#endif
+
+/* Protects conntrack->proto.sctp */
+static DECLARE_RWLOCK(sctp_lock);
+
+/* FIXME: Examine ipfilter's timeouts and conntrack transitions more
+ closely. They're more complex. --RR
+
+ And so for me for SCTP :D -Kiran */
+
+static const char *sctp_conntrack_names[] = {
+ "NONE",
+ "CLOSED",
+ "COOKIE_WAIT",
+ "COOKIE_ECHOED",
+ "ESTABLISHED",
+ "SHUTDOWN_SENT",
+ "SHUTDOWN_RECD",
+ "SHUTDOWN_ACK_SENT",
+};
+
+#define SECS * HZ
+#define MINS * 60 SECS
+#define HOURS * 60 MINS
+#define DAYS * 24 HOURS
+
+unsigned long ip_ct_sctp_timeout_closed = 10 SECS;
+unsigned long ip_ct_sctp_timeout_cookie_wait = 3 SECS;
+unsigned long ip_ct_sctp_timeout_cookie_echoed = 3 SECS;
+unsigned long ip_ct_sctp_timeout_established = 5 DAYS;
+unsigned long ip_ct_sctp_timeout_shutdown_sent = 300 SECS / 1000;
+unsigned long ip_ct_sctp_timeout_shutdown_recd = 300 SECS / 1000;
+unsigned long ip_ct_sctp_timeout_shutdown_ack_sent = 3 SECS;
+
+static unsigned long * sctp_timeouts[]
+= { NULL, /* SCTP_CONNTRACK_NONE */
+ &ip_ct_sctp_timeout_closed, /* SCTP_CONNTRACK_CLOSED */
+ &ip_ct_sctp_timeout_cookie_wait, /* SCTP_CONNTRACK_COOKIE_WAIT */
+ &ip_ct_sctp_timeout_cookie_echoed, /* SCTP_CONNTRACK_COOKIE_ECHOED */
+ &ip_ct_sctp_timeout_established, /* SCTP_CONNTRACK_ESTABLISHED */
+ &ip_ct_sctp_timeout_shutdown_sent, /* SCTP_CONNTRACK_SHUTDOWN_SENT */
+ &ip_ct_sctp_timeout_shutdown_recd, /* SCTP_CONNTRACK_SHUTDOWN_RECD */
+ &ip_ct_sctp_timeout_shutdown_ack_sent /* SCTP_CONNTRACK_SHUTDOWN_ACK_SENT */
+ };
+
+#define sNO SCTP_CONNTRACK_NONE
+#define sCL SCTP_CONNTRACK_CLOSED
+#define sCW SCTP_CONNTRACK_COOKIE_WAIT
+#define sCE SCTP_CONNTRACK_COOKIE_ECHOED
+#define sES SCTP_CONNTRACK_ESTABLISHED
+#define sSS SCTP_CONNTRACK_SHUTDOWN_SENT
+#define sSR SCTP_CONNTRACK_SHUTDOWN_RECD
+#define sSA SCTP_CONNTRACK_SHUTDOWN_ACK_SENT
+#define sIV SCTP_CONNTRACK_MAX
+
+/*
+ These are the descriptions of the states:
+
+NOTE: These state names are tantalizingly similar to the states of an
+SCTP endpoint. But the interpretation of the states is a little different,
+considering that these are the states of the connection and not of an end
+point. Please note the subtleties. -Kiran
+
+NONE - Nothing so far.
+COOKIE WAIT - We have seen an INIT chunk in the original direction, or also
+ an INIT_ACK chunk in the reply direction.
+COOKIE ECHOED - We have seen a COOKIE_ECHO chunk in the original direction.
+ESTABLISHED - We have seen a COOKIE_ACK in the reply direction.
+SHUTDOWN_SENT - We have seen a SHUTDOWN chunk in the original direction.
+SHUTDOWN_RECD - We have seen a SHUTDOWN chunk in the reply directoin.
+SHUTDOWN_ACK_SENT - We have seen a SHUTDOWN_ACK chunk in the direction opposite
+ to that of the SHUTDOWN chunk.
+CLOSED - We have seen a SHUTDOWN_COMPLETE chunk in the direction of
+ the SHUTDOWN chunk. Connection is closed.
+*/
+
+/* TODO
+ - I have assumed that the first INIT is in the original direction.
+ This messes things when an INIT comes in the reply direction in CLOSED
+ state.
+ - Check the error type in the reply dir before transitioning from
+cookie echoed to closed.
+ - Sec 5.2.4 of RFC 2960
+ - Multi Homing support.
+*/
+
+/* SCTP conntrack state transitions */
+static enum sctp_conntrack sctp_conntracks[2][9][SCTP_CONNTRACK_MAX] = {
+ {
+/* ORIGINAL */
+/* sNO, sCL, sCW, sCE, sES, sSS, sSR, sSA */
+/* init */ {sCW, sCW, sCW, sCE, sES, sSS, sSR, sSA},
+/* init_ack */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA},
+/* abort */ {sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL},
+/* shutdown */ {sCL, sCL, sCW, sCE, sSS, sSS, sSR, sSA},
+/* shutdown_ack */ {sSA, sCL, sCW, sCE, sES, sSA, sSA, sSA},
+/* error */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA},/* Cant have Stale cookie*/
+/* cookie_echo */ {sCL, sCL, sCE, sCE, sES, sSS, sSR, sSA},/* 5.2.4 - Big TODO */
+/* cookie_ack */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA},/* Cant come in orig dir */
+/* shutdown_comp*/ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sCL}
+ },
+ {
+/* REPLY */
+/* sNO, sCL, sCW, sCE, sES, sSS, sSR, sSA */
+/* init */ {sIV, sCL, sCW, sCE, sES, sSS, sSR, sSA},/* INIT in sCL Big TODO */
+/* init_ack */ {sIV, sCL, sCW, sCE, sES, sSS, sSR, sSA},
+/* abort */ {sIV, sCL, sCL, sCL, sCL, sCL, sCL, sCL},
+/* shutdown */ {sIV, sCL, sCW, sCE, sSR, sSS, sSR, sSA},
+/* shutdown_ack */ {sIV, sCL, sCW, sCE, sES, sSA, sSA, sSA},
+/* error */ {sIV, sCL, sCW, sCL, sES, sSS, sSR, sSA},
+/* cookie_echo */ {sIV, sCL, sCW, sCE, sES, sSS, sSR, sSA},/* Cant come in reply dir */
+/* cookie_ack */ {sIV, sCL, sCW, sES, sES, sSS, sSR, sSA},
+/* shutdown_comp*/ {sIV, sCL, sCW, sCE, sES, sSS, sSR, sCL}
+ }
+};
+
+static int sctp_pkt_to_tuple(const struct sk_buff *skb,
+ unsigned int dataoff,
+ struct ip_conntrack_tuple *tuple)
+{
+ sctp_sctphdr_t _hdr, *hp;
+
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ /* Actually only need first 8 bytes. */
+ hp = skb_header_pointer(skb, dataoff, 8, &_hdr);
+ if (hp == NULL)
+ return 0;
+
+ tuple->src.u.sctp.port = hp->source;
+ tuple->dst.u.sctp.port = hp->dest;
+ return 1;
+}
+
+static int sctp_invert_tuple(struct ip_conntrack_tuple *tuple,
+ const struct ip_conntrack_tuple *orig)
+{
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ tuple->src.u.sctp.port = orig->dst.u.sctp.port;
+ tuple->dst.u.sctp.port = orig->src.u.sctp.port;
+ return 1;
+}
+
+/* Print out the per-protocol part of the tuple. */
+static int sctp_print_tuple(struct seq_file *s,
+ const struct ip_conntrack_tuple *tuple)
+{
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ return seq_printf(s, "sport=%hu dport=%hu ",
+ ntohs(tuple->src.u.sctp.port),
+ ntohs(tuple->dst.u.sctp.port));
+}
+
+/* Print out the private part of the conntrack. */
+static int sctp_print_conntrack(struct seq_file *s,
+ const struct ip_conntrack *conntrack)
+{
+ enum sctp_conntrack state;
+
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ READ_LOCK(&sctp_lock);
+ state = conntrack->proto.sctp.state;
+ READ_UNLOCK(&sctp_lock);
+
+ return seq_printf(s, "%s ", sctp_conntrack_names[state]);
+}
+
+#define for_each_sctp_chunk(skb, sch, _sch, offset, count) \
+for (offset = skb->nh.iph->ihl * 4 + sizeof(sctp_sctphdr_t), count = 0; \
+ offset < skb->len && \
+ (sch = skb_header_pointer(skb, offset, sizeof(_sch), &_sch)); \
+ offset += (htons(sch->length) + 3) & ~3, count++)
+
+/* Some validity checks to make sure the chunks are fine */
+static int do_basic_checks(struct ip_conntrack *conntrack,
+ const struct sk_buff *skb,
+ char *map)
+{
+ u_int32_t offset, count;
+ sctp_chunkhdr_t _sch, *sch;
+ int flag;
+
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ flag = 0;
+
+ for_each_sctp_chunk (skb, sch, _sch, offset, count) {
+ DEBUGP("Chunk Num: %d Type: %d\n", count, sch->type);
+
+ if (sch->type == SCTP_CID_INIT
+ || sch->type == SCTP_CID_INIT_ACK
+ || sch->type == SCTP_CID_SHUTDOWN_COMPLETE) {
+ flag = 1;
+ }
+
+ /* Cookie Ack/Echo chunks not the first OR
+ Init / Init Ack / Shutdown compl chunks not the only chunks */
+ if ((sch->type == SCTP_CID_COOKIE_ACK
+ || sch->type == SCTP_CID_COOKIE_ECHO
+ || flag)
+ && count !=0 ) {
+ DEBUGP("Basic checks failed\n");
+ return 1;
+ }
+
+ if (map) {
+ set_bit(sch->type, (void *)map);
+ }
+ }
+
+ DEBUGP("Basic checks passed\n");
+ return 0;
+}
+
+static int new_state(enum ip_conntrack_dir dir,
+ enum sctp_conntrack cur_state,
+ int chunk_type)
+{
+ int i;
+
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ DEBUGP("Chunk type: %d\n", chunk_type);
+
+ switch (chunk_type) {
+ case SCTP_CID_INIT:
+ DEBUGP("SCTP_CID_INIT\n");
+ i = 0; break;
+ case SCTP_CID_INIT_ACK:
+ DEBUGP("SCTP_CID_INIT_ACK\n");
+ i = 1; break;
+ case SCTP_CID_ABORT:
+ DEBUGP("SCTP_CID_ABORT\n");
+ i = 2; break;
+ case SCTP_CID_SHUTDOWN:
+ DEBUGP("SCTP_CID_SHUTDOWN\n");
+ i = 3; break;
+ case SCTP_CID_SHUTDOWN_ACK:
+ DEBUGP("SCTP_CID_SHUTDOWN_ACK\n");
+ i = 4; break;
+ case SCTP_CID_ERROR:
+ DEBUGP("SCTP_CID_ERROR\n");
+ i = 5; break;
+ case SCTP_CID_COOKIE_ECHO:
+ DEBUGP("SCTP_CID_COOKIE_ECHO\n");
+ i = 6; break;
+ case SCTP_CID_COOKIE_ACK:
+ DEBUGP("SCTP_CID_COOKIE_ACK\n");
+ i = 7; break;
+ case SCTP_CID_SHUTDOWN_COMPLETE:
+ DEBUGP("SCTP_CID_SHUTDOWN_COMPLETE\n");
+ i = 8; break;
+ default:
+ /* Other chunks like DATA, SACK, HEARTBEAT and
+ its ACK do not cause a change in state */
+ DEBUGP("Unknown chunk type, Will stay in %s\n",
+ sctp_conntrack_names[cur_state]);
+ return cur_state;
+ }
+
+ DEBUGP("dir: %d cur_state: %s chunk_type: %d new_state: %s\n",
+ dir, sctp_conntrack_names[cur_state], chunk_type,
+ sctp_conntrack_names[sctp_conntracks[dir][i][cur_state]]);
+
+ return sctp_conntracks[dir][i][cur_state];
+}
+
+/* Returns verdict for packet, or -1 for invalid. */
+static int sctp_packet(struct ip_conntrack *conntrack,
+ const struct sk_buff *skb,
+ enum ip_conntrack_info ctinfo)
+{
+ enum sctp_conntrack newconntrack, oldsctpstate;
+ struct iphdr *iph = skb->nh.iph;
+ sctp_sctphdr_t _sctph, *sh;
+ sctp_chunkhdr_t _sch, *sch;
+ u_int32_t offset, count;
+ char map[256 / sizeof (char)] = {0};
+
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ sh = skb_header_pointer(skb, iph->ihl * 4, sizeof(_sctph), &_sctph);
+ if (sh == NULL)
+ return -1;
+
+ if (do_basic_checks(conntrack, skb, map) != 0)
+ return -1;
+
+ /* Check the verification tag (Sec 8.5) */
+ if (!test_bit(SCTP_CID_INIT, (void *)map)
+ && !test_bit(SCTP_CID_SHUTDOWN_COMPLETE, (void *)map)
+ && !test_bit(SCTP_CID_COOKIE_ECHO, (void *)map)
+ && !test_bit(SCTP_CID_ABORT, (void *)map)
+ && !test_bit(SCTP_CID_SHUTDOWN_ACK, (void *)map)
+ && (sh->vtag != conntrack->proto.sctp.vtag[CTINFO2DIR(ctinfo)])) {
+ DEBUGP("Verification tag check failed\n");
+ return -1;
+ }
+
+ oldsctpstate = newconntrack = SCTP_CONNTRACK_MAX;
+ for_each_sctp_chunk (skb, sch, _sch, offset, count) {
+ WRITE_LOCK(&sctp_lock);
+
+ /* Special cases of Verification tag check (Sec 8.5.1) */
+ if (sch->type == SCTP_CID_INIT) {
+ /* Sec 8.5.1 (A) */
+ if (sh->vtag != 0) {
+ WRITE_UNLOCK(&sctp_lock);
+ return -1;
+ }
+ } else if (sch->type == SCTP_CID_ABORT) {
+ /* Sec 8.5.1 (B) */
+ if (!(sh->vtag == conntrack->proto.sctp.vtag[CTINFO2DIR(ctinfo)])
+ && !(sh->vtag == conntrack->proto.sctp.vtag
+ [1 - CTINFO2DIR(ctinfo)])) {
+ WRITE_UNLOCK(&sctp_lock);
+ return -1;
+ }
+ } else if (sch->type == SCTP_CID_SHUTDOWN_COMPLETE) {
+ /* Sec 8.5.1 (C) */
+ if (!(sh->vtag == conntrack->proto.sctp.vtag[CTINFO2DIR(ctinfo)])
+ && !(sh->vtag == conntrack->proto.sctp.vtag
+ [1 - CTINFO2DIR(ctinfo)]
+ && (sch->flags & 1))) {
+ WRITE_UNLOCK(&sctp_lock);
+ return -1;
+ }
+ } else if (sch->type == SCTP_CID_COOKIE_ECHO) {
+ /* Sec 8.5.1 (D) */
+ if (!(sh->vtag == conntrack->proto.sctp.vtag[CTINFO2DIR(ctinfo)])) {
+ WRITE_UNLOCK(&sctp_lock);
+ return -1;
+ }
+ }
+
+ oldsctpstate = conntrack->proto.sctp.state;
+ newconntrack = new_state(CTINFO2DIR(ctinfo), oldsctpstate, sch->type);
+
+ /* Invalid */
+ if (newconntrack == SCTP_CONNTRACK_MAX) {
+ DEBUGP("ip_conntrack_sctp: Invalid dir=%i ctype=%u conntrack=%u\n",
+ CTINFO2DIR(ctinfo), sch->type, oldsctpstate);
+ WRITE_UNLOCK(&sctp_lock);
+ return -1;
+ }
+
+ /* If it is an INIT or an INIT ACK note down the vtag */
+ if (sch->type == SCTP_CID_INIT
+ || sch->type == SCTP_CID_INIT_ACK) {
+ sctp_inithdr_t _inithdr, *ih;
+
+ ih = skb_header_pointer(skb, offset + sizeof(sctp_chunkhdr_t),
+ sizeof(_inithdr), &_inithdr);
+ if (ih == NULL) {
+ WRITE_UNLOCK(&sctp_lock);
+ return -1;
+ }
+ DEBUGP("Setting vtag %x for dir %d\n",
+ ih->init_tag, CTINFO2DIR(ctinfo));
+ conntrack->proto.sctp.vtag[IP_CT_DIR_ORIGINAL] = ih->init_tag;
+ }
+
+ conntrack->proto.sctp.state = newconntrack;
+ WRITE_UNLOCK(&sctp_lock);
+ }
+
+ ip_ct_refresh_acct(conntrack, ctinfo, skb, *sctp_timeouts[newconntrack]);
+
+ if (oldsctpstate == SCTP_CONNTRACK_COOKIE_ECHOED
+ && CTINFO2DIR(ctinfo) == IP_CT_DIR_REPLY
+ && newconntrack == SCTP_CONNTRACK_ESTABLISHED) {
+ DEBUGP("Setting assured bit\n");
+ set_bit(IPS_ASSURED_BIT, &conntrack->status);
+ }
+
+ return NF_ACCEPT;
+}
+
+/* Called when a new connection for this protocol found. */
+static int sctp_new(struct ip_conntrack *conntrack,
+ const struct sk_buff *skb)
+{
+ enum sctp_conntrack newconntrack;
+ struct iphdr *iph = skb->nh.iph;
+ sctp_sctphdr_t _sctph, *sh;
+ sctp_chunkhdr_t _sch, *sch;
+ u_int32_t offset, count;
+ char map[256 / sizeof (char)] = {0};
+
+ DEBUGP(__FUNCTION__);
+ DEBUGP("\n");
+
+ sh = skb_header_pointer(skb, iph->ihl * 4, sizeof(_sctph), &_sctph);
+ if (sh == NULL)
+ return 0;
+
+ if (do_basic_checks(conntrack, skb, map) != 0)
+ return 0;
+
+ /* If an OOTB packet has any of these chunks discard (Sec 8.4) */
+ if ((test_bit (SCTP_CID_ABORT, (void *)map))
+ || (test_bit (SCTP_CID_SHUTDOWN_COMPLETE, (void *)map))
+ || (test_bit (SCTP_CID_COOKIE_ACK, (void *)map))) {
+ return 0;
+ }
+
+ newconntrack = SCTP_CONNTRACK_MAX;
+ for_each_sctp_chunk (skb, sch, _sch, offset, count) {
+ /* Don't need lock here: this conntrack not in circulation yet */
+ newconntrack = new_state (IP_CT_DIR_ORIGINAL,
+ SCTP_CONNTRACK_NONE, sch->type);
+
+ /* Invalid: delete conntrack */
+ if (newconntrack == SCTP_CONNTRACK_MAX) {
+ DEBUGP("ip_conntrack_sctp: invalid new deleting.\n");
+ return 0;
+ }
+
+ /* Copy the vtag into the state info */
+ if (sch->type == SCTP_CID_INIT) {
+ if (sh->vtag == 0) {
+ sctp_inithdr_t _inithdr, *ih;
+
+ ih = skb_header_pointer(skb, offset + sizeof(sctp_chunkhdr_t),
+ sizeof(_inithdr), &_inithdr);
+ if (ih == NULL)
+ return 0;
+
+ DEBUGP("Setting vtag %x for new conn\n",
+ ih->init_tag);
+
+ conntrack->proto.sctp.vtag[IP_CT_DIR_REPLY] =
+ ih->init_tag;
+ } else {
+ /* Sec 8.5.1 (A) */
+ return 0;
+ }
+ }
+ /* If it is a shutdown ack OOTB packet, we expect a return
+ shutdown complete, otherwise an ABORT Sec 8.4 (5) and (8) */
+ else {
+ DEBUGP("Setting vtag %x for new conn OOTB\n",
+ sh->vtag);
+ conntrack->proto.sctp.vtag[IP_CT_DIR_REPLY] = sh->vtag;
+ }
+
+ conntrack->proto.sctp.state = newconntrack;
+ }
+
+ return 1;
+}
+
+static int sctp_exp_matches_pkt(struct ip_conntrack_expect *exp,
+ const struct sk_buff *skb)
+{
+ /* To be implemented */
+ return 0;
+}
+
+struct ip_conntrack_protocol ip_conntrack_protocol_sctp = {
+ .proto = IPPROTO_SCTP,
+ .name = "sctp",
+ .pkt_to_tuple = sctp_pkt_to_tuple,
+ .invert_tuple = sctp_invert_tuple,
+ .print_tuple = sctp_print_tuple,
+ .print_conntrack = sctp_print_conntrack,
+ .packet = sctp_packet,
+ .new = sctp_new,
+ .destroy = NULL,
+ .exp_matches_pkt = sctp_exp_matches_pkt,
+ .me = THIS_MODULE
+};
+
+#ifdef CONFIG_SYSCTL
+static ctl_table ip_ct_sysctl_table[] = {
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_CLOSED,
+ .procname = "ip_conntrack_sctp_timeout_closed",
+ .data = &ip_ct_sctp_timeout_closed,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_COOKIE_WAIT,
+ .procname = "ip_conntrack_sctp_timeout_cookie_wait",
+ .data = &ip_ct_sctp_timeout_cookie_wait,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_COOKIE_ECHOED,
+ .procname = "ip_conntrack_sctp_timeout_cookie_echoed",
+ .data = &ip_ct_sctp_timeout_cookie_echoed,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_ESTABLISHED,
+ .procname = "ip_conntrack_sctp_timeout_established",
+ .data = &ip_ct_sctp_timeout_established,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_SENT,
+ .procname = "ip_conntrack_sctp_timeout_shutdown_sent",
+ .data = &ip_ct_sctp_timeout_shutdown_sent,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_RECD,
+ .procname = "ip_conntrack_sctp_timeout_shutdown_recd",
+ .data = &ip_ct_sctp_timeout_shutdown_recd,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ {
+ .ctl_name = NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_ACK_SENT,
+ .procname = "ip_conntrack_sctp_timeout_shutdown_ack_sent",
+ .data = &ip_ct_sctp_timeout_shutdown_ack_sent,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_jiffies,
+ },
+ { .ctl_name = 0 }
+};
+
+static ctl_table ip_ct_netfilter_table[] = {
+ {
+ .ctl_name = NET_IPV4_NETFILTER,
+ .procname = "netfilter",
+ .mode = 0555,
+ .child = ip_ct_sysctl_table,
+ },
+ { .ctl_name = 0 }
+};
+
+static ctl_table ip_ct_ipv4_table[] = {
+ {
+ .ctl_name = NET_IPV4,
+ .procname = "ipv4",
+ .mode = 0555,
+ .child = ip_ct_netfilter_table,
+ },
+ { .ctl_name = 0 }
+};
+
+static ctl_table ip_ct_net_table[] = {
+ {
+ .ctl_name = CTL_NET,
+ .procname = "net",
+ .mode = 0555,
+ .child = ip_ct_ipv4_table,
+ },
+ { .ctl_name = 0 }
+};
+
+static struct ctl_table_header *ip_ct_sysctl_header;
+#endif
+
+int __init init(void)
+{
+ int ret;
+
+ ret = ip_conntrack_protocol_register(&ip_conntrack_protocol_sctp);
+ if (ret) {
+ printk("ip_conntrack_proto_sctp: protocol register failed\n");
+ goto out;
+ }
+
+#ifdef CONFIG_SYSCTL
+ ip_ct_sysctl_header = register_sysctl_table(ip_ct_net_table, 0);
+ if (ip_ct_sysctl_header == NULL) {
+ printk("ip_conntrack_proto_sctp: can't register to sysctl.\n");
+ goto cleanup;
+ }
+#endif
+
+ return ret;
+
+#ifdef CONFIG_SYSCTL
+ cleanup:
+ ip_conntrack_protocol_unregister(&ip_conntrack_protocol_sctp);
+#endif
+ out:
+ DEBUGP("SCTP conntrack module loading %s\n",
+ ret ? "failed": "succeeded");
+ return ret;
+}
+
+void __exit fini(void)
+{
+ ip_conntrack_protocol_unregister(&ip_conntrack_protocol_sctp);
+#ifdef CONFIG_SYSCTL
+ unregister_sysctl_table(ip_ct_sysctl_header);
+#endif
+ DEBUGP("SCTP conntrack module unloaded\n");
+}
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kiran Kumar Immidi");
+MODULE_DESCRIPTION("Netfilter connection tracking protocol helper for SCTP");
--- /dev/null
+/*
+ * ip_nat_proto_gre.c - Version 2.0
+ *
+ * NAT protocol helper module for GRE.
+ *
+ * GRE is a generic encapsulation protocol, which is generally not very
+ * suited for NAT, as it has no protocol-specific part as port numbers.
+ *
+ * It has an optional key field, which may help us distinguishing two
+ * connections between the same two hosts.
+ *
+ * GRE is defined in RFC 1701 and RFC 1702, as well as RFC 2784
+ *
+ * PPTP is built on top of a modified version of GRE, and has a mandatory
+ * field called "CallID", which serves us for the same purpose as the key
+ * field in plain GRE.
+ *
+ * Documentation about PPTP can be found in RFC 2637
+ *
+ * (C) 2000-2004 by Harald Welte <laforge@gnumonks.org>
+ *
+ * Development of this code funded by Astaro AG (http://www.astaro.com/)
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/ip.h>
+#include <linux/netfilter_ipv4/ip_nat.h>
+#include <linux/netfilter_ipv4/ip_nat_rule.h>
+#include <linux/netfilter_ipv4/ip_nat_protocol.h>
+#include <linux/netfilter_ipv4/ip_conntrack_proto_gre.h>
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Harald Welte <laforge@gnumonks.org>");
+MODULE_DESCRIPTION("Netfilter NAT protocol helper module for GRE");
+
+#if 0
+#define DEBUGP(format, args...) printk(KERN_DEBUG __FILE__ ":" __FUNCTION__ \
+ ": " format, ## args)
+#else
+#define DEBUGP(x, args...)
+#endif
+
+/* is key in given range between min and max */
+static int
+gre_in_range(const struct ip_conntrack_tuple *tuple,
+ enum ip_nat_manip_type maniptype,
+ const union ip_conntrack_manip_proto *min,
+ const union ip_conntrack_manip_proto *max)
+{
+ u_int32_t key;
+
+ if (maniptype == IP_NAT_MANIP_SRC)
+ key = tuple->src.u.gre.key;
+ else
+ key = tuple->dst.u.gre.key;
+
+ return ntohl(key) >= ntohl(min->gre.key)
+ && ntohl(key) <= ntohl(max->gre.key);
+}
+
+/* generate unique tuple ... */
+static int
+gre_unique_tuple(struct ip_conntrack_tuple *tuple,
+ const struct ip_nat_range *range,
+ enum ip_nat_manip_type maniptype,
+ const struct ip_conntrack *conntrack)
+{
+ u_int32_t min, i, range_size;
+ u_int32_t key = 0, *keyptr;
+
+ if (maniptype == IP_NAT_MANIP_SRC)
+ keyptr = &tuple->src.u.gre.key;
+ else
+ keyptr = &tuple->dst.u.gre.key;
+
+ if (!(range->flags & IP_NAT_RANGE_PROTO_SPECIFIED)) {
+ DEBUGP("%p: NATing GRE PPTP\n", conntrack);
+ min = 1;
+ range_size = 0xffff;
+ } else {
+ min = ntohl(range->min.gre.key);
+ range_size = ntohl(range->max.gre.key) - min + 1;
+ }
+
+ DEBUGP("min = %u, range_size = %u\n", min, range_size);
+
+ for (i = 0; i < range_size; i++, key++) {
+ *keyptr = htonl(min + key % range_size);
+ if (!ip_nat_used_tuple(tuple, conntrack))
+ return 1;
+ }
+
+ DEBUGP("%p: no NAT mapping\n", conntrack);
+
+ return 0;
+}
+
+/* manipulate a GRE packet according to maniptype */
+static int
+gre_manip_pkt(struct sk_buff **pskb,
+ unsigned int hdroff,
+ const struct ip_conntrack_manip *manip,
+ enum ip_nat_manip_type maniptype)
+{
+ struct gre_hdr *greh;
+ struct gre_hdr_pptp *pgreh;
+
+ if (!skb_ip_make_writable(pskb, hdroff + sizeof(*pgreh)))
+ return 0;
+
+ greh = (void *)(*pskb)->data + hdroff;
+ pgreh = (struct gre_hdr_pptp *) greh;
+
+ /* we only have destination manip of a packet, since 'source key'
+ * is not present in the packet itself */
+ if (maniptype == IP_NAT_MANIP_DST) {
+ /* key manipulation is always dest */
+ switch (greh->version) {
+ case 0:
+ if (!greh->key) {
+ DEBUGP("can't nat GRE w/o key\n");
+ break;
+ }
+ if (greh->csum) {
+ /* FIXME: Never tested this code... */
+ *(gre_csum(greh)) =
+ ip_nat_cheat_check(~*(gre_key(greh)),
+ manip->u.gre.key,
+ *(gre_csum(greh)));
+ }
+ *(gre_key(greh)) = manip->u.gre.key;
+ break;
+ case GRE_VERSION_PPTP:
+ DEBUGP("call_id -> 0x%04x\n",
+ ntohl(manip->u.gre.key));
+ pgreh->call_id = htons(ntohl(manip->u.gre.key));
+ break;
+ default:
+ DEBUGP("can't nat unknown GRE version\n");
+ return 0;
+ break;
+ }
+ }
+ return 1;
+}
+
+/* print out a nat tuple */
+static unsigned int
+gre_print(char *buffer,
+ const struct ip_conntrack_tuple *match,
+ const struct ip_conntrack_tuple *mask)
+{
+ unsigned int len = 0;
+
+ if (mask->src.u.gre.key)
+ len += sprintf(buffer + len, "srckey=0x%x ",
+ ntohl(match->src.u.gre.key));
+
+ if (mask->dst.u.gre.key)
+ len += sprintf(buffer + len, "dstkey=0x%x ",
+ ntohl(match->src.u.gre.key));
+
+ return len;
+}
+
+/* print a range of keys */
+static unsigned int
+gre_print_range(char *buffer, const struct ip_nat_range *range)
+{
+ if (range->min.gre.key != 0
+ || range->max.gre.key != 0xFFFF) {
+ if (range->min.gre.key == range->max.gre.key)
+ return sprintf(buffer, "key 0x%x ",
+ ntohl(range->min.gre.key));
+ else
+ return sprintf(buffer, "keys 0x%u-0x%u ",
+ ntohl(range->min.gre.key),
+ ntohl(range->max.gre.key));
+ } else
+ return 0;
+}
+
+/* nat helper struct */
+static struct ip_nat_protocol gre = {
+ .name = "GRE",
+ .protonum = IPPROTO_GRE,
+ .manip_pkt = gre_manip_pkt,
+ .in_range = gre_in_range,
+ .unique_tuple = gre_unique_tuple,
+ .print = gre_print,
+ .print_range = gre_print_range
+};
+
+static int __init init(void)
+{
+ if (ip_nat_protocol_register(&gre))
+ return -EIO;
+
+ return 0;
+}
+
+static void __exit fini(void)
+{
+ ip_nat_protocol_unregister(&gre);
+}
+
+module_init(init);
+module_exit(fini);
--- /dev/null
+/*
+ * Implements a dummy match to allow attaching comments to rules
+ *
+ * 2003-05-13 Brad Fisher (brad@info-link.net)
+ */
+
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <linux/netfilter_ipv4/ipt_comment.h>
+
+MODULE_AUTHOR("Brad Fisher <brad@info-link.net>");
+MODULE_DESCRIPTION("iptables comment match module");
+MODULE_LICENSE("GPL");
+
+static int
+match(const struct sk_buff *skb,
+ const struct net_device *in,
+ const struct net_device *out,
+ const void *matchinfo,
+ int offset,
+ int *hotdrop)
+{
+ /* We always match */
+ return 1;
+}
+
+static int
+checkentry(const char *tablename,
+ const struct ipt_ip *ip,
+ void *matchinfo,
+ unsigned int matchsize,
+ unsigned int hook_mask)
+{
+ /* Check the size */
+ if (matchsize != IPT_ALIGN(sizeof(struct ipt_comment_info)))
+ return 0;
+ return 1;
+}
+
+static struct ipt_match comment_match = {
+ .name = "comment",
+ .match = match,
+ .checkentry = checkentry,
+ .me = THIS_MODULE
+};
+
+static int __init init(void)
+{
+ return ipt_register_match(&comment_match);
+}
+
+static void __exit fini(void)
+{
+ ipt_unregister_match(&comment_match);
+}
+
+module_init(init);
+module_exit(fini);
--- /dev/null
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <net/ip.h>
+#include <linux/sctp.h>
+
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <linux/netfilter_ipv4/ipt_sctp.h>
+
+#ifdef DEBUG_SCTP
+#define duprintf(format, args...) printk(format , ## args)
+#else
+#define duprintf(format, args...)
+#endif
+
+#define SCCHECK(cond, option, flag, invflag) (!((flag) & (option)) \
+ || (!!((invflag) & (option)) ^ (cond)))
+
+static int
+match_flags(const struct ipt_sctp_flag_info *flag_info,
+ const int flag_count,
+ u_int8_t chunktype,
+ u_int8_t chunkflags)
+{
+ int i;
+
+ for (i = 0; i < flag_count; i++) {
+ if (flag_info[i].chunktype == chunktype) {
+ return (chunkflags & flag_info[i].flag_mask) == flag_info[i].flag;
+ }
+ }
+
+ return 1;
+}
+
+static int
+match_packet(const struct sk_buff *skb,
+ const u_int32_t *chunkmap,
+ int chunk_match_type,
+ const struct ipt_sctp_flag_info *flag_info,
+ const int flag_count,
+ int *hotdrop)
+{
+ int offset;
+ u_int32_t chunkmapcopy[256 / sizeof (u_int32_t)];
+ sctp_chunkhdr_t _sch, *sch;
+
+#ifdef DEBUG_SCTP
+ int i = 0;
+#endif
+
+ if (chunk_match_type == SCTP_CHUNK_MATCH_ALL) {
+ SCTP_CHUNKMAP_COPY(chunkmapcopy, chunkmap);
+ }
+
+ offset = skb->nh.iph->ihl * 4 + sizeof (sctp_sctphdr_t);
+ do {
+ sch = skb_header_pointer(skb, offset, sizeof(_sch), &_sch);
+ if (sch == NULL) {
+ duprintf("Dropping invalid SCTP packet.\n");
+ *hotdrop = 1;
+ return 0;
+ }
+
+ duprintf("Chunk num: %d\toffset: %d\ttype: %d\tlength: %d\tflags: %x\n",
+ ++i, offset, sch->type, htons(sch->length), sch->flags);
+
+ offset += (htons(sch->length) + 3) & ~3;
+
+ duprintf("skb->len: %d\toffset: %d\n", skb->len, offset);
+
+ if (SCTP_CHUNKMAP_IS_SET(chunkmap, sch->type)) {
+ switch (chunk_match_type) {
+ case SCTP_CHUNK_MATCH_ANY:
+ if (match_flags(flag_info, flag_count,
+ sch->type, sch->flags)) {
+ return 1;
+ }
+ break;
+
+ case SCTP_CHUNK_MATCH_ALL:
+ if (match_flags(flag_info, flag_count,
+ sch->type, sch->flags)) {
+ SCTP_CHUNKMAP_CLEAR(chunkmapcopy, sch->type);
+ }
+ break;
+
+ case SCTP_CHUNK_MATCH_ONLY:
+ if (!match_flags(flag_info, flag_count,
+ sch->type, sch->flags)) {
+ return 0;
+ }
+ break;
+ }
+ } else {
+ switch (chunk_match_type) {
+ case SCTP_CHUNK_MATCH_ONLY:
+ return 0;
+ }
+ }
+ } while (offset < skb->len);
+
+ switch (chunk_match_type) {
+ case SCTP_CHUNK_MATCH_ALL:
+ return SCTP_CHUNKMAP_IS_CLEAR(chunkmap);
+ case SCTP_CHUNK_MATCH_ANY:
+ return 0;
+ case SCTP_CHUNK_MATCH_ONLY:
+ return 1;
+ }
+
+ /* This will never be reached, but required to stop compiler whine */
+ return 0;
+}
+
+static int
+match(const struct sk_buff *skb,
+ const struct net_device *in,
+ const struct net_device *out,
+ const void *matchinfo,
+ int offset,
+ int *hotdrop)
+{
+ const struct ipt_sctp_info *info;
+ sctp_sctphdr_t _sh, *sh;
+
+ info = (const struct ipt_sctp_info *)matchinfo;
+
+ if (offset) {
+ duprintf("Dropping non-first fragment.. FIXME\n");
+ return 0;
+ }
+
+ sh = skb_header_pointer(skb, skb->nh.iph->ihl*4, sizeof(_sh), &_sh);
+ if (sh == NULL) {
+ duprintf("Dropping evil TCP offset=0 tinygram.\n");
+ *hotdrop = 1;
+ return 0;
+ }
+ duprintf("spt: %d\tdpt: %d\n", ntohs(sh->source), ntohs(sh->dest));
+
+ return SCCHECK(((ntohs(sh->source) >= info->spts[0])
+ && (ntohs(sh->source) <= info->spts[1])),
+ IPT_SCTP_SRC_PORTS, info->flags, info->invflags)
+ && SCCHECK(((ntohs(sh->dest) >= info->dpts[0])
+ && (ntohs(sh->dest) <= info->dpts[1])),
+ IPT_SCTP_DEST_PORTS, info->flags, info->invflags)
+ && SCCHECK(match_packet(skb, info->chunkmap, info->chunk_match_type,
+ info->flag_info, info->flag_count,
+ hotdrop),
+ IPT_SCTP_CHUNK_TYPES, info->flags, info->invflags);
+}
+
+static int
+checkentry(const char *tablename,
+ const struct ipt_ip *ip,
+ void *matchinfo,
+ unsigned int matchsize,
+ unsigned int hook_mask)
+{
+ const struct ipt_sctp_info *info;
+
+ info = (const struct ipt_sctp_info *)matchinfo;
+
+ return ip->proto == IPPROTO_SCTP
+ && !(ip->invflags & IPT_INV_PROTO)
+ && matchsize == IPT_ALIGN(sizeof(struct ipt_sctp_info))
+ && !(info->flags & ~IPT_SCTP_VALID_FLAGS)
+ && !(info->invflags & ~IPT_SCTP_VALID_FLAGS)
+ && !(info->invflags & ~info->flags)
+ && ((!(info->flags & IPT_SCTP_CHUNK_TYPES)) ||
+ (info->chunk_match_type &
+ (SCTP_CHUNK_MATCH_ALL
+ | SCTP_CHUNK_MATCH_ANY
+ | SCTP_CHUNK_MATCH_ONLY)));
+}
+
+static struct ipt_match sctp_match =
+{
+ .list = { NULL, NULL},
+ .name = "sctp",
+ .match = &match,
+ .checkentry = &checkentry,
+ .destroy = NULL,
+ .me = THIS_MODULE
+};
+
+static int __init init(void)
+{
+ return ipt_register_match(&sctp_match);
+}
+
+static void __exit fini(void)
+{
+ ipt_unregister_match(&sctp_match);
+}
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kiran Kumar Immidi");
+MODULE_DESCRIPTION("Match for SCTP protocol packets");
+
--- /dev/null
+/* Kernel module to match the bridge port in and
+ * out device for IP packets coming into contact with a bridge. */
+
+/* (C) 2001-2003 Bart De Schuymer <bdschuym@pandora.be>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/netfilter_ipv6/ip6t_physdev.h>
+#include <linux/netfilter_ipv6/ip6_tables.h>
+#include <linux/netfilter_bridge.h>
+#define MATCH 1
+#define NOMATCH 0
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Bart De Schuymer <bdschuym@pandora.be>");
+MODULE_DESCRIPTION("iptables bridge physical device match module");
+
+static int
+match(const struct sk_buff *skb,
+ const struct net_device *in,
+ const struct net_device *out,
+ const void *matchinfo,
+ int offset,
+ const void *hdr,
+ u_int16_t datalen,
+ int *hotdrop)
+{
+ int i;
+ static const char nulldevname[IFNAMSIZ];
+ const struct ip6t_physdev_info *info = matchinfo;
+ unsigned int ret;
+ const char *indev, *outdev;
+ struct nf_bridge_info *nf_bridge;
+
+ /* Not a bridged IP packet or no info available yet:
+ * LOCAL_OUT/mangle and LOCAL_OUT/nat don't know if
+ * the destination device will be a bridge. */
+ if (!(nf_bridge = skb->nf_bridge)) {
+ /* Return MATCH if the invert flags of the used options are on */
+ if ((info->bitmask & IP6T_PHYSDEV_OP_BRIDGED) &&
+ !(info->invert & IP6T_PHYSDEV_OP_BRIDGED))
+ return NOMATCH;
+ if ((info->bitmask & IP6T_PHYSDEV_OP_ISIN) &&
+ !(info->invert & IP6T_PHYSDEV_OP_ISIN))
+ return NOMATCH;
+ if ((info->bitmask & IP6T_PHYSDEV_OP_ISOUT) &&
+ !(info->invert & IP6T_PHYSDEV_OP_ISOUT))
+ return NOMATCH;
+ if ((info->bitmask & IP6T_PHYSDEV_OP_IN) &&
+ !(info->invert & IP6T_PHYSDEV_OP_IN))
+ return NOMATCH;
+ if ((info->bitmask & IP6T_PHYSDEV_OP_OUT) &&
+ !(info->invert & IP6T_PHYSDEV_OP_OUT))
+ return NOMATCH;
+ return MATCH;
+ }
+
+ /* This only makes sense in the FORWARD and POSTROUTING chains */
+ if ((info->bitmask & IP6T_PHYSDEV_OP_BRIDGED) &&
+ (!!(nf_bridge->mask & BRNF_BRIDGED) ^
+ !(info->invert & IP6T_PHYSDEV_OP_BRIDGED)))
+ return NOMATCH;
+
+ if ((info->bitmask & IP6T_PHYSDEV_OP_ISIN &&
+ (!nf_bridge->physindev ^ !!(info->invert & IP6T_PHYSDEV_OP_ISIN))) ||
+ (info->bitmask & IP6T_PHYSDEV_OP_ISOUT &&
+ (!nf_bridge->physoutdev ^ !!(info->invert & IP6T_PHYSDEV_OP_ISOUT))))
+ return NOMATCH;
+
+ if (!(info->bitmask & IP6T_PHYSDEV_OP_IN))
+ goto match_outdev;
+ indev = nf_bridge->physindev ? nf_bridge->physindev->name : nulldevname;
+ for (i = 0, ret = 0; i < IFNAMSIZ/sizeof(unsigned int); i++) {
+ ret |= (((const unsigned int *)indev)[i]
+ ^ ((const unsigned int *)info->physindev)[i])
+ & ((const unsigned int *)info->in_mask)[i];
+ }
+
+ if ((ret == 0) ^ !(info->invert & IP6T_PHYSDEV_OP_IN))
+ return NOMATCH;
+
+match_outdev:
+ if (!(info->bitmask & IP6T_PHYSDEV_OP_OUT))
+ return MATCH;
+ outdev = nf_bridge->physoutdev ?
+ nf_bridge->physoutdev->name : nulldevname;
+ for (i = 0, ret = 0; i < IFNAMSIZ/sizeof(unsigned int); i++) {
+ ret |= (((const unsigned int *)outdev)[i]
+ ^ ((const unsigned int *)info->physoutdev)[i])
+ & ((const unsigned int *)info->out_mask)[i];
+ }
+
+ return (ret != 0) ^ !(info->invert & IP6T_PHYSDEV_OP_OUT);
+}
+
+static int
+checkentry(const char *tablename,
+ const struct ip6t_ip6 *ip,
+ void *matchinfo,
+ unsigned int matchsize,
+ unsigned int hook_mask)
+{
+ const struct ip6t_physdev_info *info = matchinfo;
+
+ if (matchsize != IP6T_ALIGN(sizeof(struct ip6t_physdev_info)))
+ return 0;
+ if (!(info->bitmask & IP6T_PHYSDEV_OP_MASK) ||
+ info->bitmask & ~IP6T_PHYSDEV_OP_MASK)
+ return 0;
+ return 1;
+}
+
+static struct ip6t_match physdev_match = {
+ .name = "physdev",
+ .match = &match,
+ .checkentry = &checkentry,
+ .me = THIS_MODULE,
+};
+
+static int __init init(void)
+{
+ return ip6t_register_match(&physdev_match);
+}
+
+static void __exit fini(void)
+{
+ ip6t_unregister_match(&physdev_match);
+}
+
+module_init(init);
+module_exit(fini);
--- /dev/null
+/*
+ * net/sched/gact.c Generic actions
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * copyright Jamal Hadi Salim (2002-4)
+ *
+ */
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/socket.h>
+#include <linux/sockios.h>
+#include <linux/in.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/rtnetlink.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+#include <net/sock.h>
+#include <net/pkt_sched.h>
+#include <linux/tc_act/tc_gact.h>
+#include <net/tc_act/tc_gact.h>
+
+/* use generic hash table */
+#define MY_TAB_SIZE 16
+#define MY_TAB_MASK 15
+static u32 idx_gen;
+static struct tcf_gact *tcf_gact_ht[MY_TAB_SIZE];
+static rwlock_t gact_lock = RW_LOCK_UNLOCKED;
+
+/* ovewrride the defaults */
+#define tcf_st tcf_gact
+#define tc_st tc_gact
+#define tcf_t_lock gact_lock
+#define tcf_ht tcf_gact_ht
+
+#define CONFIG_NET_ACT_INIT 1
+#include <net/pkt_act.h>
+
+#ifdef CONFIG_GACT_PROB
+typedef int (*g_rand)(struct tcf_gact *p);
+int
+gact_net_rand(struct tcf_gact *p) {
+ if (net_random()%p->pval)
+ return p->action;
+ return p->paction;
+}
+
+int
+gact_determ(struct tcf_gact *p) {
+ if (p->stats.packets%p->pval)
+ return p->action;
+ return p->paction;
+}
+
+
+g_rand gact_rand[MAX_RAND]= { NULL,gact_net_rand, gact_determ};
+
+#endif
+int
+tcf_gact_init(struct rtattr *rta, struct rtattr *est, struct tc_action *a,int ovr,int bind)
+{
+ struct rtattr *tb[TCA_GACT_MAX];
+ struct tc_gact *parm = NULL;
+#ifdef CONFIG_GACT_PROB
+ struct tc_gact_p *p_parm = NULL;
+#endif
+ struct tcf_gact *p = NULL;
+ int ret = 0;
+ int size = sizeof (*p);
+
+ if (rtattr_parse(tb, TCA_GACT_MAX, RTA_DATA(rta), RTA_PAYLOAD(rta)) < 0)
+ return -1;
+
+ if (NULL == a || NULL == tb[TCA_GACT_PARMS - 1]) {
+ printk("BUG: tcf_gact_init called with NULL params\n");
+ return -1;
+ }
+
+ parm = RTA_DATA(tb[TCA_GACT_PARMS - 1]);
+#ifdef CONFIG_GACT_PROB
+ if (NULL != tb[TCA_GACT_PROB - 1]) {
+ p_parm = RTA_DATA(tb[TCA_GACT_PROB - 1]);
+ }
+#endif
+
+ p = tcf_hash_check(parm, a, ovr, bind);
+
+ if (NULL == p) {
+ p = tcf_hash_create(parm,est,a,size,ovr, bind);
+
+ if (NULL == p) {
+ return -1;
+ } else {
+ p->refcnt = 1;
+ ret = 1;
+ goto override;
+ }
+ }
+
+ if (ovr) {
+override:
+ p->action = parm->action;
+#ifdef CONFIG_GACT_PROB
+ if (NULL != p_parm) {
+ p->paction = p_parm->paction;
+ p->pval = p_parm->pval;
+ p->ptype = p_parm->ptype;
+ } else {
+ p->paction = p->pval = p->ptype = 0;
+ }
+#endif
+ }
+
+ return ret;
+}
+
+int
+tcf_gact_cleanup(struct tc_action *a, int bind)
+{
+ struct tcf_gact *p;
+ p = PRIV(a,gact);
+ if (NULL != p)
+ return tcf_hash_release(p, bind);
+ return 0;
+}
+
+int
+tcf_gact(struct sk_buff **pskb, struct tc_action *a)
+{
+ struct tcf_gact *p;
+ struct sk_buff *skb = *pskb;
+ int action = TC_ACT_SHOT;
+
+ p = PRIV(a,gact);
+
+ if (NULL == p) {
+ if (net_ratelimit())
+ printk("BUG: tcf_gact called with NULL params\n");
+ return -1;
+ }
+
+ spin_lock(&p->lock);
+#ifdef CONFIG_GACT_PROB
+ if (p->ptype && NULL != gact_rand[p->ptype])
+ action = gact_rand[p->ptype](p);
+ else
+ action = p->action;
+#else
+ action = p->action;
+#endif
+ p->stats.bytes += skb->len;
+ p->stats.packets++;
+ if (TC_ACT_SHOT == action)
+ p->stats.drops++;
+ p->tm.lastuse = jiffies;
+ spin_unlock(&p->lock);
+
+ return action;
+}
+
+int
+tcf_gact_dump(struct sk_buff *skb, struct tc_action *a, int bind, int ref)
+{
+ unsigned char *b = skb->tail;
+ struct tc_gact opt;
+#ifdef CONFIG_GACT_PROB
+ struct tc_gact_p p_opt;
+#endif
+ struct tcf_gact *p;
+ struct tcf_t t;
+
+ p = PRIV(a,gact);
+ if (NULL == p) {
+ printk("BUG: tcf_gact_dump called with NULL params\n");
+ goto rtattr_failure;
+ }
+
+ opt.index = p->index;
+ opt.refcnt = p->refcnt - ref;
+ opt.bindcnt = p->bindcnt - bind;
+ opt.action = p->action;
+ RTA_PUT(skb, TCA_GACT_PARMS, sizeof (opt), &opt);
+#ifdef CONFIG_GACT_PROB
+ if (p->ptype) {
+ p_opt.paction = p->paction;
+ p_opt.pval = p->pval;
+ p_opt.ptype = p->ptype;
+ RTA_PUT(skb, TCA_GACT_PROB, sizeof (p_opt), &p_opt);
+ }
+#endif
+ t.install = jiffies - p->tm.install;
+ t.lastuse = jiffies - p->tm.lastuse;
+ t.expires = p->tm.expires;
+ RTA_PUT(skb, TCA_GACT_TM, sizeof (t), &t);
+ return skb->len;
+
+ rtattr_failure:
+ skb_trim(skb, b - skb->data);
+ return -1;
+}
+
+int
+tcf_gact_stats(struct sk_buff *skb, struct tc_action *a)
+{
+ struct tcf_gact *p;
+ p = PRIV(a,gact);
+ if (NULL != p)
+ return qdisc_copy_stats(skb, &p->stats,p->stats_lock);
+
+ return 1;
+}
+
+struct tc_action_ops act_gact_ops = {
+ .next = NULL,
+ .kind = "gact",
+ .type = TCA_ACT_GACT,
+ .capab = TCA_CAP_NONE,
+ .owner = THIS_MODULE,
+ .act = tcf_gact,
+ .get_stats = tcf_gact_stats,
+ .dump = tcf_gact_dump,
+ .cleanup = tcf_gact_cleanup,
+ .lookup = tcf_hash_search,
+ .init = tcf_gact_init,
+ .walk = tcf_generic_walker
+};
+
+MODULE_AUTHOR("Jamal Hadi Salim(2002-4)");
+MODULE_DESCRIPTION("Generic Classifier actions");
+MODULE_LICENSE("GPL");
+
+static int __init
+gact_init_module(void)
+{
+#ifdef CONFIG_GACT_PROB
+ printk("GACT probability on\n");
+#else
+ printk("GACT probability NOT on\n");
+#endif
+ return tcf_register_action(&act_gact_ops);
+}
+
+static void __exit
+gact_cleanup_module(void)
+{
+ tcf_unregister_action(&act_gact_ops);
+}
+
+module_init(gact_init_module);
+module_exit(gact_cleanup_module);
--- /dev/null
+/*
+ * linux/net/sunrpc/gss_spkm3_mech.c
+ *
+ * Copyright (c) 2003 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Andy Adamson <andros@umich.edu>
+ * J. Bruce Fields <bfields@umich.edu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/sunrpc/auth.h>
+#include <linux/in.h>
+#include <linux/sunrpc/svcauth_gss.h>
+#include <linux/sunrpc/gss_spkm3.h>
+#include <linux/sunrpc/xdr.h>
+#include <linux/crypto.h>
+
+#ifdef RPC_DEBUG
+# define RPCDBG_FACILITY RPCDBG_AUTH
+#endif
+
+struct xdr_netobj gss_mech_spkm3_oid =
+ {7, "\053\006\001\005\005\001\003"};
+
+static inline int
+get_bytes(char **ptr, const char *end, void *res, int len)
+{
+ char *p, *q;
+ p = *ptr;
+ q = p + len;
+ if (q > end || q < p)
+ return -1;
+ memcpy(res, p, len);
+ *ptr = q;
+ return 0;
+}
+
+static inline int
+get_netobj(char **ptr, const char *end, struct xdr_netobj *res)
+{
+ char *p, *q;
+ p = *ptr;
+ if (get_bytes(&p, end, &res->len, sizeof(res->len)))
+ return -1;
+ q = p + res->len;
+ if(res->len == 0)
+ goto out_nocopy;
+ if (q > end || q < p)
+ return -1;
+ if (!(res->data = kmalloc(res->len, GFP_KERNEL)))
+ return -1;
+ memcpy(res->data, p, res->len);
+out_nocopy:
+ *ptr = q;
+ return 0;
+}
+
+static inline int
+get_key(char **p, char *end, struct crypto_tfm **res, int *resalg)
+{
+ struct xdr_netobj key = {
+ .len = 0,
+ .data = NULL,
+ };
+ int alg_mode,setkey = 0;
+ char *alg_name;
+
+ if (get_bytes(p, end, resalg, sizeof(int)))
+ goto out_err;
+ if ((get_netobj(p, end, &key)))
+ goto out_err;
+
+ switch (*resalg) {
+ case NID_des_cbc:
+ alg_name = "des";
+ alg_mode = CRYPTO_TFM_MODE_CBC;
+ setkey = 1;
+ break;
+ case NID_md5:
+ if (key.len == 0) {
+ dprintk("RPC: SPKM3 get_key: NID_md5 zero Key length\n");
+ }
+ alg_name = "md5";
+ alg_mode = 0;
+ setkey = 0;
+ break;
+ case NID_cast5_cbc:
+ dprintk("RPC: SPKM3 get_key: case cast5_cbc, UNSUPPORTED \n");
+ goto out_err;
+ break;
+ default:
+ dprintk("RPC: SPKM3 get_key: unsupported algorithm %d", *resalg);
+ goto out_err_free_key;
+ }
+ if (!(*res = crypto_alloc_tfm(alg_name, alg_mode)))
+ goto out_err_free_key;
+ if (setkey) {
+ if (crypto_cipher_setkey(*res, key.data, key.len))
+ goto out_err_free_tfm;
+ }
+
+ if(key.len > 0)
+ kfree(key.data);
+ return 0;
+
+out_err_free_tfm:
+ crypto_free_tfm(*res);
+out_err_free_key:
+ if(key.len > 0)
+ kfree(key.data);
+out_err:
+ return -1;
+}
+
+static u32
+gss_import_sec_context_spkm3(struct xdr_netobj *inbuf,
+ struct gss_ctx *ctx_id)
+{
+ char *p = inbuf->data;
+ char *end = inbuf->data + inbuf->len;
+ struct spkm3_ctx *ctx;
+
+ if (!(ctx = kmalloc(sizeof(*ctx), GFP_KERNEL)))
+ goto out_err;
+ memset(ctx, 0, sizeof(*ctx));
+
+ if (get_netobj(&p, end, &ctx->ctx_id))
+ goto out_err_free_ctx;
+
+ if (get_bytes(&p, end, &ctx->qop, sizeof(ctx->qop)))
+ goto out_err_free_ctx_id;
+
+ if (get_netobj(&p, end, &ctx->mech_used))
+ goto out_err_free_mech;
+
+ if (get_bytes(&p, end, &ctx->ret_flags, sizeof(ctx->ret_flags)))
+ goto out_err_free_mech;
+
+ if (get_bytes(&p, end, &ctx->req_flags, sizeof(ctx->req_flags)))
+ goto out_err_free_mech;
+
+ if (get_netobj(&p, end, &ctx->share_key))
+ goto out_err_free_s_key;
+
+ if (get_key(&p, end, &ctx->derived_conf_key, &ctx->conf_alg)) {
+ dprintk("RPC: SPKM3 confidentiality key will be NULL\n");
+ }
+
+ if (get_key(&p, end, &ctx->derived_integ_key, &ctx->intg_alg)) {
+ dprintk("RPC: SPKM3 integrity key will be NULL\n");
+ }
+
+ if (get_bytes(&p, end, &ctx->owf_alg, sizeof(ctx->owf_alg)))
+ goto out_err_free_s_key;
+
+ if (get_bytes(&p, end, &ctx->owf_alg, sizeof(ctx->owf_alg)))
+ goto out_err_free_s_key;
+
+ if (p != end)
+ goto out_err_free_s_key;
+
+ ctx_id->internal_ctx_id = ctx;
+
+ dprintk("Succesfully imported new spkm context.\n");
+ return 0;
+
+out_err_free_s_key:
+ kfree(ctx->share_key.data);
+out_err_free_mech:
+ kfree(ctx->mech_used.data);
+out_err_free_ctx_id:
+ kfree(ctx->ctx_id.data);
+out_err_free_ctx:
+ kfree(ctx);
+out_err:
+ return GSS_S_FAILURE;
+}
+
+void
+gss_delete_sec_context_spkm3(void *internal_ctx) {
+ struct spkm3_ctx *sctx = internal_ctx;
+
+ if(sctx->derived_integ_key)
+ crypto_free_tfm(sctx->derived_integ_key);
+ if(sctx->derived_conf_key)
+ crypto_free_tfm(sctx->derived_conf_key);
+ if(sctx->share_key.data)
+ kfree(sctx->share_key.data);
+ if(sctx->mech_used.data)
+ kfree(sctx->mech_used.data);
+ kfree(sctx);
+}
+
+u32
+gss_verify_mic_spkm3(struct gss_ctx *ctx,
+ struct xdr_buf *signbuf,
+ struct xdr_netobj *checksum,
+ u32 *qstate) {
+ u32 maj_stat = 0;
+ int qop_state = 0;
+ struct spkm3_ctx *sctx = ctx->internal_ctx_id;
+
+ dprintk("RPC: gss_verify_mic_spkm3 calling spkm3_read_token\n");
+ maj_stat = spkm3_read_token(sctx, checksum, signbuf, &qop_state,
+ SPKM_MIC_TOK);
+
+ if (!maj_stat && qop_state)
+ *qstate = qop_state;
+
+ dprintk("RPC: gss_verify_mic_spkm3 returning %d\n", maj_stat);
+ return maj_stat;
+}
+
+u32
+gss_get_mic_spkm3(struct gss_ctx *ctx,
+ u32 qop,
+ struct xdr_buf *message_buffer,
+ struct xdr_netobj *message_token) {
+ u32 err = 0;
+ struct spkm3_ctx *sctx = ctx->internal_ctx_id;
+
+ dprintk("RPC: gss_get_mic_spkm3\n");
+
+ err = spkm3_make_token(sctx, qop, message_buffer,
+ message_token, SPKM_MIC_TOK);
+ return err;
+}
+
+static struct gss_api_ops gss_spkm3_ops = {
+ .gss_import_sec_context = gss_import_sec_context_spkm3,
+ .gss_get_mic = gss_get_mic_spkm3,
+ .gss_verify_mic = gss_verify_mic_spkm3,
+ .gss_delete_sec_context = gss_delete_sec_context_spkm3,
+};
+
+static struct pf_desc gss_spkm3_pfs[] = {
+ {RPC_AUTH_GSS_SPKM, 0, RPC_GSS_SVC_NONE, "spkm3"},
+ {RPC_AUTH_GSS_SPKMI, 0, RPC_GSS_SVC_INTEGRITY, "spkm3i"},
+};
+
+static struct gss_api_mech gss_spkm3_mech = {
+ .gm_name = "spkm3",
+ .gm_owner = THIS_MODULE,
+ .gm_ops = &gss_spkm3_ops,
+ .gm_pf_num = ARRAY_SIZE(gss_spkm3_pfs),
+ .gm_pfs = gss_spkm3_pfs,
+};
+
+static int __init init_spkm3_module(void)
+{
+ int status;
+
+ status = gss_mech_register(&gss_spkm3_mech);
+ if (status)
+ printk("Failed to register spkm3 gss mechanism!\n");
+ return 0;
+}
+
+static void __exit cleanup_spkm3_module(void)
+{
+ gss_mech_unregister(&gss_spkm3_mech);
+}
+
+MODULE_LICENSE("GPL");
+module_init(init_spkm3_module);
+module_exit(cleanup_spkm3_module);
--- /dev/null
+/*
+ * linux/net/sunrpc/gss_spkm3_seal.c
+ *
+ * Copyright (c) 2003 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Andy Adamson <andros@umich.edu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/sunrpc/gss_spkm3.h>
+#include <linux/random.h>
+#include <linux/crypto.h>
+
+#ifdef RPC_DEBUG
+# define RPCDBG_FACILITY RPCDBG_AUTH
+#endif
+
+/*
+ * spkm3_make_token()
+ *
+ * Only SPKM_MIC_TOK with md5 intg-alg is supported
+ */
+
+u32
+spkm3_make_token(struct spkm3_ctx *ctx, int qop_req,
+ struct xdr_buf * text, struct xdr_netobj * token,
+ int toktype)
+{
+ s32 checksum_type;
+ char tokhdrbuf[25];
+ struct xdr_netobj md5cksum = {.len = 0, .data = NULL};
+ struct xdr_netobj mic_hdr = {.len = 0, .data = tokhdrbuf};
+ int tmsglen, tokenlen = 0;
+ unsigned char *ptr;
+ s32 now;
+ int ctxelen = 0, ctxzbit = 0;
+ int md5elen = 0, md5zbit = 0;
+
+ dprintk("RPC: spkm3_make_token\n");
+
+ now = jiffies;
+ if (qop_req != 0)
+ goto out_err;
+
+ if (ctx->ctx_id.len != 16) {
+ dprintk("RPC: spkm3_make_token BAD ctx_id.len %d\n",
+ ctx->ctx_id.len);
+ goto out_err;
+ }
+
+ switch (ctx->intg_alg) {
+ case NID_md5:
+ checksum_type = CKSUMTYPE_RSA_MD5;
+ break;
+ default:
+ dprintk("RPC: gss_spkm3_seal: ctx->signalg %d not"
+ " supported\n", ctx->intg_alg);
+ goto out_err;
+ }
+ /* XXX since we don't support WRAP, perhaps we don't care... */
+ if (ctx->conf_alg != NID_cast5_cbc) {
+ dprintk("RPC: gss_spkm3_seal: ctx->sealalg %d not supported\n",
+ ctx->conf_alg);
+ goto out_err;
+ }
+
+ if (toktype == SPKM_MIC_TOK) {
+ tmsglen = 0;
+ /* Calculate checksum over the mic-header */
+ asn1_bitstring_len(&ctx->ctx_id, &ctxelen, &ctxzbit);
+ spkm3_mic_header(&mic_hdr.data, &mic_hdr.len, ctx->ctx_id.data,
+ ctxelen, ctxzbit);
+
+ if (make_checksum(checksum_type, mic_hdr.data, mic_hdr.len,
+ text, &md5cksum))
+ goto out_err;
+
+ asn1_bitstring_len(&md5cksum, &md5elen, &md5zbit);
+ tokenlen = 10 + ctxelen + 1 + 2 + md5elen + 1;
+
+ /* Create token header using generic routines */
+ token->len = g_token_size(&ctx->mech_used, tokenlen + tmsglen);
+
+ ptr = token->data;
+ g_make_token_header(&ctx->mech_used, tokenlen + tmsglen, &ptr);
+
+ spkm3_make_mic_token(&ptr, tokenlen, &mic_hdr, &md5cksum, md5elen, md5zbit);
+ } else if (toktype == SPKM_WRAP_TOK) { /* Not Supported */
+ dprintk("RPC: gss_spkm3_seal: SPKM_WRAP_TOK not supported\n");
+ goto out_err;
+ }
+ kfree(md5cksum.data);
+
+ /* XXX need to implement sequence numbers, and ctx->expired */
+
+ return GSS_S_COMPLETE;
+out_err:
+ if (md5cksum.data)
+ kfree(md5cksum.data);
+ token->data = NULL;
+ token->len = 0;
+ return GSS_S_FAILURE;
+}
--- /dev/null
+/*
+ * linux/net/sunrpc/gss_spkm3_token.c
+ *
+ * Copyright (c) 2003 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Andy Adamson <andros@umich.edu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/sunrpc/gss_spkm3.h>
+#include <linux/random.h>
+#include <linux/crypto.h>
+
+#ifdef RPC_DEBUG
+# define RPCDBG_FACILITY RPCDBG_AUTH
+#endif
+
+/*
+ * asn1_bitstring_len()
+ *
+ * calculate the asn1 bitstring length of the xdr_netobject
+ */
+void
+asn1_bitstring_len(struct xdr_netobj *in, int *enclen, int *zerobits)
+{
+ int i, zbit = 0,elen = in->len;
+ char *ptr;
+
+ ptr = &in->data[in->len -1];
+
+ /* count trailing 0's */
+ for(i = in->len; i > 0; i--) {
+ if (*ptr == 0) {
+ ptr--;
+ elen--;
+ } else
+ break;
+ }
+
+ /* count number of 0 bits in final octet */
+ ptr = &in->data[elen - 1];
+ for(i = 0; i < 8; i++) {
+ short mask = 0x01;
+
+ if (!((mask << i) & *ptr))
+ zbit++;
+ else
+ break;
+ }
+ *enclen = elen;
+ *zerobits = zbit;
+}
+
+/*
+ * decode_asn1_bitstring()
+ *
+ * decode a bitstring into a buffer of the expected length.
+ * enclen = bit string length
+ * explen = expected length (define in rfc)
+ */
+int
+decode_asn1_bitstring(struct xdr_netobj *out, char *in, int enclen, int explen)
+{
+ if (!(out->data = kmalloc(explen,GFP_KERNEL)))
+ return 0;
+ out->len = explen;
+ memset(out->data, 0, explen);
+ memcpy(out->data, in, enclen);
+ return 1;
+}
+
+/*
+ * SPKMInnerContextToken choice SPKM_MIC asn1 token layout
+ *
+ * contextid is always 16 bytes plain data. max asn1 bitstring len = 17.
+ *
+ * tokenlen = pos[0] to end of token (max pos[45] with MD5 cksum)
+ *
+ * pos value
+ * ----------
+ * [0] a4 SPKM-MIC tag
+ * [1] ?? innertoken length (max 44)
+ *
+ *
+ * tok_hdr piece of checksum data starts here
+ *
+ * the maximum mic-header len = 9 + 17 = 26
+ * mic-header
+ * ----------
+ * [2] 30 SEQUENCE tag
+ * [3] ?? mic-header length: (max 23) = TokenID + ContextID
+ *
+ * TokenID - all fields constant and can be hardcoded
+ * -------
+ * [4] 02 Type 2
+ * [5] 02 Length 2
+ * [6][7] 01 01 TokenID (SPKM_MIC_TOK)
+ *
+ * ContextID - encoded length not constant, calculated
+ * ---------
+ * [8] 03 Type 3
+ * [9] ?? encoded length
+ * [10] ?? ctxzbit
+ * [11] contextid
+ *
+ * mic_header piece of checksum data ends here.
+ *
+ * int-cksum - encoded length not constant, calculated
+ * ---------
+ * [??] 03 Type 3
+ * [??] ?? encoded length
+ * [??] ?? md5zbit
+ * [??] int-cksum (NID_md5 = 16)
+ *
+ * maximum SPKM-MIC innercontext token length =
+ * 10 + encoded contextid_size(17 max) + 2 + encoded
+ * cksum_size (17 maxfor NID_md5) = 46
+ */
+
+/*
+ * spkm3_mic_header()
+ *
+ * Prepare the SPKM_MIC_TOK mic-header for check-sum calculation
+ * elen: 16 byte context id asn1 bitstring encoded length
+ */
+void
+spkm3_mic_header(unsigned char **hdrbuf, unsigned int *hdrlen, unsigned char *ctxdata, int elen, int zbit)
+{
+ char *hptr = *hdrbuf;
+ char *top = *hdrbuf;
+
+ *(u8 *)hptr++ = 0x30;
+ *(u8 *)hptr++ = elen + 7; /* on the wire header length */
+
+ /* tokenid */
+ *(u8 *)hptr++ = 0x02;
+ *(u8 *)hptr++ = 0x02;
+ *(u8 *)hptr++ = 0x01;
+ *(u8 *)hptr++ = 0x01;
+
+ /* coniextid */
+ *(u8 *)hptr++ = 0x03;
+ *(u8 *)hptr++ = elen + 1; /* add 1 to include zbit */
+ *(u8 *)hptr++ = zbit;
+ memcpy(hptr, ctxdata, elen);
+ hptr += elen;
+ *hdrlen = hptr - top;
+}
+
+/*
+ * spkm3_mic_innercontext_token()
+ *
+ * *tokp points to the beginning of the SPKM_MIC token described
+ * in rfc 2025, section 3.2.1:
+ *
+ */
+void
+spkm3_make_mic_token(unsigned char **tokp, int toklen, struct xdr_netobj *mic_hdr, struct xdr_netobj *md5cksum, int md5elen, int md5zbit)
+{
+ unsigned char *ict = *tokp;
+
+ *(u8 *)ict++ = 0xa4;
+ *(u8 *)ict++ = toklen - 2;
+ memcpy(ict, mic_hdr->data, mic_hdr->len);
+ ict += mic_hdr->len;
+
+ *(u8 *)ict++ = 0x03;
+ *(u8 *)ict++ = md5elen + 1; /* add 1 to include zbit */
+ *(u8 *)ict++ = md5zbit;
+ memcpy(ict, md5cksum->data, md5elen);
+}
+
+u32
+spkm3_verify_mic_token(unsigned char **tokp, int *mic_hdrlen, unsigned char **cksum)
+{
+ struct xdr_netobj spkm3_ctx_id = {.len =0, .data = NULL};
+ unsigned char *ptr = *tokp;
+ int ctxelen;
+ u32 ret = GSS_S_DEFECTIVE_TOKEN;
+
+ /* spkm3 innercontext token preamble */
+ if ((ptr[0] != 0xa4) || (ptr[2] != 0x30)) {
+ dprintk("RPC: BAD SPKM ictoken preamble\n");
+ goto out;
+ }
+
+ *mic_hdrlen = ptr[3];
+
+ /* token type */
+ if ((ptr[4] != 0x02) || (ptr[5] != 0x02)) {
+ dprintk("RPC: BAD asn1 SPKM3 token type\n");
+ goto out;
+ }
+
+ /* only support SPKM_MIC_TOK */
+ if((ptr[6] != 0x01) || (ptr[7] != 0x01)) {
+ dprintk("RPC: ERROR unsupported SPKM3 token \n");
+ goto out;
+ }
+
+ /* contextid */
+ if (ptr[8] != 0x03) {
+ dprintk("RPC: BAD SPKM3 asn1 context-id type\n");
+ goto out;
+ }
+
+ ctxelen = ptr[9];
+ if (ctxelen > 17) { /* length includes asn1 zbit octet */
+ dprintk("RPC: BAD SPKM3 contextid len %d\n", ctxelen);
+ goto out;
+ }
+
+ /* ignore ptr[10] */
+
+ if(!decode_asn1_bitstring(&spkm3_ctx_id, &ptr[11], ctxelen - 1, 16))
+ goto out;
+
+ /*
+ * in the current implementation: the optional int-alg is not present
+ * so the default int-alg (md5) is used the optional snd-seq field is
+ * also not present
+ */
+
+ if (*mic_hdrlen != 6 + ctxelen) {
+ dprintk("RPC: BAD SPKM_ MIC_TOK header len %d: we only support default int-alg (should be absent) and do not support snd-seq\n", *mic_hdrlen);
+ goto out;
+ }
+ /* checksum */
+ *cksum = (&ptr[10] + ctxelen); /* ctxelen includes ptr[10] */
+
+ ret = GSS_S_COMPLETE;
+out:
+ if (spkm3_ctx_id.data)
+ kfree(spkm3_ctx_id.data);
+ return ret;
+}
+
--- /dev/null
+/*
+ * linux/net/sunrpc/gss_spkm3_unseal.c
+ *
+ * Copyright (c) 2003 The Regents of the University of Michigan.
+ * All rights reserved.
+ *
+ * Andy Adamson <andros@umich.edu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/sunrpc/gss_spkm3.h>
+#include <linux/crypto.h>
+
+#ifdef RPC_DEBUG
+# define RPCDBG_FACILITY RPCDBG_AUTH
+#endif
+
+/*
+ * spkm3_read_token()
+ *
+ * only SPKM_MIC_TOK with md5 intg-alg is supported
+ */
+u32
+spkm3_read_token(struct spkm3_ctx *ctx,
+ struct xdr_netobj *read_token, /* checksum */
+ struct xdr_buf *message_buffer, /* signbuf */
+ int *qop_state, int toktype)
+{
+ s32 code;
+ struct xdr_netobj wire_cksum = {.len =0, .data = NULL};
+ struct xdr_netobj md5cksum = {.len = 0, .data = NULL};
+ unsigned char *ptr = (unsigned char *)read_token->data;
+ unsigned char *cksum;
+ int bodysize, md5elen;
+ int mic_hdrlen;
+ u32 ret = GSS_S_DEFECTIVE_TOKEN;
+
+ dprintk("RPC: spkm3_read_token read_token->len %d\n", read_token->len);
+
+ if (g_verify_token_header((struct xdr_netobj *) &ctx->mech_used,
+ &bodysize, &ptr, read_token->len))
+ goto out;
+
+ /* decode the token */
+
+ if (toktype == SPKM_MIC_TOK) {
+
+ if ((ret = spkm3_verify_mic_token(&ptr, &mic_hdrlen, &cksum)))
+ goto out;
+
+ if (*cksum++ != 0x03) {
+ dprintk("RPC: spkm3_read_token BAD checksum type\n");
+ goto out;
+ }
+ md5elen = *cksum++;
+ cksum++; /* move past the zbit */
+
+ if(!decode_asn1_bitstring(&wire_cksum, cksum, md5elen - 1, 16))
+ goto out;
+
+ /* HARD CODED FOR MD5 */
+
+ /* compute the checksum of the message.
+ * ptr + 2 = start of header piece of checksum
+ * mic_hdrlen + 2 = length of header piece of checksum
+ */
+ ret = GSS_S_DEFECTIVE_TOKEN;
+ code = make_checksum(CKSUMTYPE_RSA_MD5, ptr + 2,
+ mic_hdrlen + 2,
+ message_buffer, &md5cksum);
+
+ if (code)
+ goto out;
+
+ dprintk("RPC: spkm3_read_token: digest wire_cksum.len %d:\n",
+ wire_cksum.len);
+ dprintk(" md5cksum.data\n");
+ print_hexl((u32 *) md5cksum.data, 16, 0);
+ dprintk(" cksum.data:\n");
+ print_hexl((u32 *) wire_cksum.data, wire_cksum.len, 0);
+
+ ret = GSS_S_BAD_SIG;
+ code = memcmp(md5cksum.data, wire_cksum.data, wire_cksum.len);
+ if (code)
+ goto out;
+
+ } else {
+ dprintk("RPC: BAD or UNSUPPORTED SPKM3 token type: %d\n",toktype);
+ goto out;
+ }
+
+ /* XXX: need to add expiration and sequencing */
+ ret = GSS_S_COMPLETE;
+out:
+ if (md5cksum.data)
+ kfree(md5cksum.data);
+ if (wire_cksum.data)
+ kfree(wire_cksum.data);
+ return ret;
+}
--- /dev/null
+# ==========================================================================
+# Building binaries on the host system
+# Binaries are used during the compilation of the kernel, for example
+# to preprocess a data file.
+#
+# Both C and C++ is supported, but preferred language is C for such utilities.
+#
+# Samle syntax (see Documentation/kbuild/makefile.txt for reference)
+# hostprogs-y := bin2hex
+# Will compile bin2hex.c and create an executable named bin2hex
+#
+# hostprogs-y := lxdialog
+# lxdialog-objs := checklist.o lxdialog.o
+# Will compile lxdialog.c and checklist.c, and then link the executable
+# lxdialog, based on checklist.o and lxdialog.o
+#
+# hostprogs-y := qconf
+# qconf-cxxobjs := qconf.o
+# qconf-objs := menu.o
+# Will compile qconf as a C++ program, and menu as a C program.
+# They are linked as C++ code to the executable qconf
+
+# hostprogs-y := conf
+# conf-objs := conf.o libkconfig.so
+# libkconfig-objs := expr.o type.o
+# Will create a shared library named libkconfig.so that consist of
+# expr.o and type.o (they are both compiled as C code and the object file
+# are made as position independent code).
+# conf.c is compiled as a c program, and conf.o is linked together with
+# libkconfig.so as the executable conf.
+# Note: Shared libraries consisting of C++ files are not supported
+
+__hostprogs := $(sort $(hostprogs-y)$(hostprogs-m))
+
+# hostprogs-y := tools/build may have been specified. Retreive directory
+obj-dirs += $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f))))
+obj-dirs := $(strip $(sort $(filter-out ./,$(obj-dirs))))
+
+
+# C code
+# Executables compiled from a single .c file
+host-csingle := $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m)))
+
+# C executables linked based on several .o files
+host-cmulti := $(foreach m,$(__hostprogs),\
+ $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m))))
+
+# Object (.o) files compiled from .c files
+host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs)))
+
+# C++ code
+# C++ executables compiled from at least on .cc file
+# and zero or more .c files
+host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m)))
+
+# C++ Object (.o) files compiled from .cc files
+host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs)))
+
+# Shared libaries (only .c supported)
+# Shared libraries (.so) - all .so files referenced in "xxx-objs"
+host-cshlib := $(sort $(filter %.so, $(host-cobjs)))
+# Remove .so files from "xxx-objs"
+host-cobjs := $(filter-out %.so,$(host-cobjs))
+
+#Object (.o) files used by the shared libaries
+host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs))))
+
+__hostprogs := $(addprefix $(obj)/,$(__hostprogs))
+host-csingle := $(addprefix $(obj)/,$(host-csingle))
+host-cmulti := $(addprefix $(obj)/,$(host-cmulti))
+host-cobjs := $(addprefix $(obj)/,$(host-cobjs))
+host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti))
+host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs))
+host-cshlib := $(addprefix $(obj)/,$(host-cshlib))
+host-cshobjs := $(addprefix $(obj)/,$(host-cshobjs))
+obj-dirs := $(addprefix $(obj)/,$(obj-dirs))
+
+#####
+# Handle options to gcc. Support building with separate output directory
+
+_hostc_flags = $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOSTCFLAGS_$(*F).o)
+_hostcxx_flags = $(HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) $(HOSTCXXFLAGS_$(*F).o)
+
+ifeq ($(KBUILD_SRC),)
+__hostc_flags = $(_hostc_flags)
+__hostcxx_flags = $(_hostcxx_flags)
+else
+__hostc_flags = -I$(obj) $(call flags,_hostc_flags)
+__hostcxx_flags = -I$(obj) $(call flags,_hostcxx_flags)
+endif
+
+hostc_flags = -Wp,-MD,$(depfile) $(__hostc_flags)
+hostcxx_flags = -Wp,-MD,$(depfile) $(__hostcxx_flags)
+
+#####
+# Compile programs on the host
+
+# Create executable from a single .c file
+# host-csingle -> Executable
+quiet_cmd_host-csingle = HOSTCC $@
+ cmd_host-csingle = $(HOSTCC) $(hostc_flags) $(HOST_LOADLIBES) -o $@ $<
+$(host-csingle): %: %.c FORCE
+ $(call if_changed_dep,host-csingle)
+
+# Link an executable based on list of .o files, all plain c
+# host-cmulti -> executable
+quiet_cmd_host-cmulti = HOSTLD $@
+ cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \
+ $(addprefix $(obj)/,$($(@F)-objs)) \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cmulti): %: $(host-cobjs) $(host-cshlib) FORCE
+ $(call if_changed,host-cmulti)
+
+# Create .o file from a single .c file
+# host-cobjs -> .o
+quiet_cmd_host-cobjs = HOSTCC $@
+ cmd_host-cobjs = $(HOSTCC) $(hostc_flags) -c -o $@ $<
+$(host-cobjs): %.o: %.c FORCE
+ $(call if_changed_dep,host-cobjs)
+
+# Link an executable based on list of .o files, a mixture of .c and .cc
+# host-cxxmulti -> executable
+quiet_cmd_host-cxxmulti = HOSTLD $@
+ cmd_host-cxxmulti = $(HOSTCXX) $(HOSTLDFLAGS) -o $@ \
+ $(foreach o,objs cxxobjs,\
+ $(addprefix $(obj)/,$($(@F)-$(o)))) \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cxxmulti): %: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE
+ $(call if_changed,host-cxxmulti)
+
+# Create .o file from a single .cc (C++) file
+quiet_cmd_host-cxxobjs = HOSTCXX $@
+ cmd_host-cxxobjs = $(HOSTCXX) $(hostcxx_flags) -c -o $@ $<
+$(host-cxxobjs): %.o: %.cc FORCE
+ $(call if_changed_dep,host-cxxobjs)
+
+# Compile .c file, create position independent .o file
+# host-cshobjs -> .o
+quiet_cmd_host-cshobjs = HOSTCC -fPIC $@
+ cmd_host-cshobjs = $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $<
+$(host-cshobjs): %.o: %.c FORCE
+ $(call if_changed_dep,host-cshobjs)
+
+# Link a shared library, based on position independent .o files
+# *.o -> .so shared library (host-cshlib)
+quiet_cmd_host-cshlib = HOSTLLD -shared $@
+ cmd_host-cshlib = $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \
+ $(addprefix $(obj)/,$($(@F:.so=-objs))) \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cshlib): %: $(host-cshobjs) FORCE
+ $(call if_changed,host-cshlib)
+
+targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\
+ $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs)
+
--- /dev/null
+#!/bin/sh -x
+# Based on the vmlinux file create the System.map file
+# System.map is used by module-init tools and some debugging
+# tools to retreive the actual addresses of symbols in the kernel.
+#
+# Usage
+# mksysmap vmlinux System.map
+
+
+#####
+# Generate System.map (actual filename passed as second argument)
+
+# $NM produces the following output:
+# f0081e80 T alloc_vfsmnt
+
+# The second row specify the type of the symbol:
+# A = Absolute
+# B = Uninitialised data (.bss)
+# C = Comon symbol
+# D = Initialised data
+# G = Initialised data for small objects
+# I = Indirect reference to another symbol
+# N = Debugging symbol
+# R = Read only
+# S = Uninitialised data for small objects
+# T = Text code symbol
+# U = Undefined symbol
+# V = Weak symbol
+# W = Weak symbol
+# Corresponding small letters are local symbols
+
+# For System.map filter away:
+# a - local absolute symbols
+# U - undefined global symbols
+# w - local weak symbols
+
+# readprofile starts reading symbols when _stext is found, and
+# continue until it finds a symbol which is not either of 'T', 't',
+# 'W' or 'w'. __crc_ are 'A' and placed in the middle
+# so we just ignore them to let readprofile continue to work.
+# (At least sparc64 has __crc_ in the middle).
+
+$NM -n $1 | grep -v '\( [aUw] \)\|\(__crc_\)' > $2
+
--- /dev/null
+#!/usr/bin/perl -w
+#
+# namespace.pl. Mon Aug 30 2004
+#
+# Perform a name space analysis on the linux kernel.
+#
+# Copyright Keith Owens <kaos@ocs.com.au>. GPL.
+#
+# Invoke by changing directory to the top of the kernel object
+# tree then namespace.pl, no parameters.
+#
+# Tuned for 2.1.x kernels with the new module handling, it will
+# work with 2.0 kernels as well.
+#
+# Last change 2.6.9-rc1, adding support for separate source and object
+# trees.
+#
+# The source must be compiled/assembled first, the object files
+# are the primary input to this script. Incomplete or missing
+# objects will result in a flawed analysis. Compile both vmlinux
+# and modules.
+#
+# Even with complete objects, treat the result of the analysis
+# with caution. Some external references are only used by
+# certain architectures, others with certain combinations of
+# configuration parameters. Ideally the source should include
+# something like
+#
+# #ifndef CONFIG_...
+# static
+# #endif
+# symbol_definition;
+#
+# so the symbols are defined as static unless a particular
+# CONFIG_... requires it to be external.
+#
+# A symbol that is suffixed with '(export only)' has these properties
+#
+# * It is global.
+# * It is marked EXPORT_SYMBOL or EXPORT_SYMBOL_GPL, either in the same
+# source file or a different source file.
+# * Given the current .config, nothing uses the symbol.
+#
+# The symbol is a candidate for conversion to static, plus removal of the
+# export. But be careful that a different .config might use the symbol.
+#
+#
+# Name space analysis and cleanup is an iterative process. You cannot
+# expect to find all the problems in a single pass.
+#
+# * Identify possibly unnecessary global declarations, verify that they
+# really are unnecessary and change them to static.
+# * Compile and fix up gcc warnings about static, removing dead symbols
+# as necessary.
+# * make clean and rebuild with different configs (especially
+# CONFIG_MODULES=n) to see which symbols are being defined when the
+# config does not require them. These symbols bloat the kernel object
+# for no good reason, which is frustrating for embedded systems.
+# * Wrap config sensitive symbols in #ifdef CONFIG_foo, as long as the
+# code does not get too ugly.
+# * Repeat the name space analysis until you can live with with the
+# result.
+#
+
+require 5; # at least perl 5
+use strict;
+use File::Find;
+
+my $nm = "/usr/bin/nm -p";
+my $objdump = "/usr/bin/objdump -s -j .comment";
+my $srctree = "";
+my $objtree = "";
+$srctree = "$ENV{'srctree'}/" if (exists($ENV{'srctree'}));
+$objtree = "$ENV{'objtree'}/" if (exists($ENV{'objtree'}));
+
+if ($#ARGV != -1) {
+ print STDERR "usage: $0 takes no parameters\n";
+ die("giving up\n");
+}
+
+my %nmdata = (); # nm data for each object
+my %def = (); # all definitions for each name
+my %ksymtab = (); # names that appear in __ksymtab_
+my %ref = (); # $ref{$name} exists if there is a true external reference to $name
+my %export = (); # $export{$name} exists if there is an EXPORT_... of $name
+
+&find(\&linux_objects, '.'); # find the objects and do_nm on them
+&list_multiply_defined();
+&resolve_external_references();
+&list_extra_externals();
+
+exit(0);
+
+sub linux_objects
+{
+ # Select objects, ignoring objects which are only created by
+ # merging other objects. Also ignore all of modules, scripts
+ # and compressed. Most conglomerate objects are handled by do_nm,
+ # this list only contains the special cases. These include objects
+ # that are linked from just one other object and objects for which
+ # there is really no permanent source file.
+ my $basename = $_;
+ $_ = $File::Find::name;
+ s:^\./::;
+ if (/.*\.o$/ &&
+ ! (
+ m:/built-in.o$:
+ || m:arch/i386/kernel/vsyscall-syms.o$:
+ || m:arch/ia64/ia32/ia32.o$:
+ || m:arch/ia64/kernel/gate-syms.o$:
+ || m:arch/ia64/lib/__divdi3.o$:
+ || m:arch/ia64/lib/__divsi3.o$:
+ || m:arch/ia64/lib/__moddi3.o$:
+ || m:arch/ia64/lib/__modsi3.o$:
+ || m:arch/ia64/lib/__udivdi3.o$:
+ || m:arch/ia64/lib/__udivsi3.o$:
+ || m:arch/ia64/lib/__umoddi3.o$:
+ || m:arch/ia64/lib/__umodsi3.o$:
+ || m:arch/ia64/scripts/check_gas_for_hint.o$:
+ || m:arch/ia64/sn/kernel/xp.o$:
+ || m:boot/bbootsect.o$:
+ || m:boot/bsetup.o$:
+ || m:/bootsect.o$:
+ || m:/boot/setup.o$:
+ || m:/compressed/:
+ || m:drivers/cdrom/driver.o$:
+ || m:drivers/char/drm/tdfx_drv.o$:
+ || m:drivers/ide/ide-detect.o$:
+ || m:drivers/ide/pci/idedriver-pci.o$:
+ || m:drivers/media/media.o$:
+ || m:drivers/scsi/sd_mod.o$:
+ || m:drivers/video/video.o$:
+ || m:fs/devpts/devpts.o$:
+ || m:fs/exportfs/exportfs.o$:
+ || m:fs/hugetlbfs/hugetlbfs.o$:
+ || m:fs/msdos/msdos.o$:
+ || m:fs/nls/nls.o$:
+ || m:fs/ramfs/ramfs.o$:
+ || m:fs/romfs/romfs.o$:
+ || m:fs/vfat/vfat.o$:
+ || m:init/mounts.o$:
+ || m:^modules/:
+ || m:net/netlink/netlink.o$:
+ || m:net/sched/sched.o$:
+ || m:/piggy.o$:
+ || m:^scripts/:
+ || m:sound/.*/snd-:
+ || m:^.*/\.tmp_:
+ || m:^\.tmp_:
+ || m:/vmlinux-obj.o$:
+ )
+ ) {
+ do_nm($basename, $_);
+ }
+ $_ = $basename; # File::Find expects $_ untouched (undocumented)
+}
+
+sub do_nm
+{
+ my ($basename, $fullname) = @_;
+ my ($source, $type, $name);
+ if (! -e $basename) {
+ printf STDERR "$basename does not exist\n";
+ return;
+ }
+ if ($fullname !~ /\.o$/) {
+ printf STDERR "$fullname is not an object file\n";
+ return;
+ }
+ ($source = $fullname) =~ s/\.o$//;
+ if (-e "$objtree$source.c" || -e "$objtree$source.S") {
+ $source = "$objtree$source";
+ } else {
+ $source = "$srctree$source";
+ }
+ if (! -e "$source.c" && ! -e "$source.S") {
+ # No obvious source, exclude the object if it is conglomerate
+ if (! open(OBJDUMPDATA, "$objdump $basename|")) {
+ printf STDERR "$objdump $fullname failed $!\n";
+ return;
+ }
+ my $comment;
+ while (<OBJDUMPDATA>) {
+ chomp();
+ if (/^In archive/) {
+ # Archives are always conglomerate
+ $comment = "GCC:GCC:";
+ last;
+ }
+ next if (! /^[ 0-9a-f]{5,} /);
+ $comment .= substr($_, 43);
+ }
+ close(OBJDUMPDATA);
+ if (!defined($comment) || $comment !~ /GCC\:.*GCC\:/m) {
+ printf STDERR "No source file found for $fullname\n";
+ }
+ return;
+ }
+ if (! open(NMDATA, "$nm $basename|")) {
+ printf STDERR "$nm $fullname failed $!\n";
+ return;
+ }
+ my @nmdata;
+ while (<NMDATA>) {
+ chop;
+ ($type, $name) = (split(/ +/, $_, 3))[1..2];
+ # Expected types
+ # A absolute symbol
+ # B weak external reference to data that has been resolved
+ # C global variable, uninitialised
+ # D global variable, initialised
+ # G global variable, initialised, small data section
+ # R global array, initialised
+ # S global variable, uninitialised, small bss
+ # T global label/procedure
+ # U external reference
+ # W weak external reference to text that has been resolved
+ # a assembler equate
+ # b static variable, uninitialised
+ # d static variable, initialised
+ # g static variable, initialised, small data section
+ # r static array, initialised
+ # s static variable, uninitialised, small bss
+ # t static label/procedures
+ # w weak external reference to text that has not been resolved
+ # ? undefined type, used a lot by modules
+ if ($type !~ /^[ABCDGRSTUWabdgrstw?]$/) {
+ printf STDERR "nm output for $fullname contains unknown type '$_'\n";
+ }
+ elsif ($name =~ /\./) {
+ # name with '.' is local static
+ }
+ else {
+ $type = 'R' if ($type eq '?'); # binutils replaced ? with R at one point
+ # binutils keeps changing the type for exported symbols, force it to R
+ $type = 'R' if ($name =~ /^__ksymtab/ || $name =~ /^__kstrtab/);
+ $name =~ s/_R[a-f0-9]{8}$//; # module versions adds this
+ if ($type =~ /[ABCDGRSTW]/ &&
+ $name ne 'init_module' &&
+ $name ne 'cleanup_module' &&
+ $name ne 'Using_Versions' &&
+ $name !~ /^Version_[0-9]+$/ &&
+ $name !~ /^__parm_/ &&
+ $name !~ /^__kstrtab/ &&
+ $name !~ /^__ksymtab/ &&
+ $name !~ /^__kcrctab_/ &&
+ $name !~ /^__exitcall_/ &&
+ $name !~ /^__initcall_/ &&
+ $name !~ /^__kdb_initcall_/ &&
+ $name !~ /^__kdb_exitcall_/ &&
+ $name !~ /^__module_/ &&
+ $name !~ /^__mod_/ &&
+ $name !~ /^__crc_/ &&
+ $name ne '__this_module' &&
+ $name ne 'kernel_version') {
+ if (!exists($def{$name})) {
+ $def{$name} = [];
+ }
+ push(@{$def{$name}}, $fullname);
+ }
+ push(@nmdata, "$type $name");
+ if ($name =~ /^__ksymtab_/) {
+ $name = substr($name, 10);
+ if (!exists($ksymtab{$name})) {
+ $ksymtab{$name} = [];
+ }
+ push(@{$ksymtab{$name}}, $fullname);
+ }
+ }
+ }
+ close(NMDATA);
+ if ($#nmdata < 0) {
+ if (
+ $fullname ne "lib/brlock.o"
+ && $fullname ne "lib/dec_and_lock.o"
+ && $fullname ne "fs/xfs/xfs_macros.o"
+ && $fullname ne "drivers/ide/ide-probe-mini.o"
+ && $fullname ne "usr/initramfs_data.o"
+ && $fullname ne "drivers/acpi/executer/exdump.o"
+ && $fullname ne "drivers/acpi/resources/rsdump.o"
+ && $fullname ne "drivers/acpi/namespace/nsdumpdv.o"
+ && $fullname ne "drivers/acpi/namespace/nsdump.o"
+ && $fullname ne "arch/ia64/sn/kernel/sn2/io.o"
+ && $fullname ne "arch/ia64/kernel/gate-data.o"
+ && $fullname ne "drivers/ieee1394/oui.o"
+ && $fullname ne "security/capability.o"
+ && $fullname ne "sound/core/wrappers.o"
+ && $fullname ne "fs/ntfs/sysctl.o"
+ && $fullname ne "fs/jfs/jfs_debug.o"
+ ) {
+ printf "No nm data for $fullname\n";
+ }
+ return;
+ }
+ $nmdata{$fullname} = \@nmdata;
+}
+
+sub drop_def
+{
+ my ($object, $name) = @_;
+ my $nmdata = $nmdata{$object};
+ my ($i, $j);
+ for ($i = 0; $i <= $#{$nmdata}; ++$i) {
+ if ($name eq (split(' ', $nmdata->[$i], 2))[1]) {
+ splice(@{$nmdata{$object}}, $i, 1);
+ my $def = $def{$name};
+ for ($j = 0; $j < $#{$def{$name}}; ++$j) {
+ if ($def{$name}[$j] eq $object) {
+ splice(@{$def{$name}}, $j, 1);
+ }
+ }
+ last;
+ }
+ }
+}
+
+sub list_multiply_defined
+{
+ my ($name, $module);
+ foreach $name (keys(%def)) {
+ if ($#{$def{$name}} > 0) {
+ # Special case for cond_syscall
+ if ($#{$def{$name}} == 1 && $name =~ /^sys_/ &&
+ ($def{$name}[0] eq "kernel/sys.o" ||
+ $def{$name}[1] eq "kernel/sys.o")) {
+ &drop_def("kernel/sys.o", $name);
+ next;
+ }
+ # Special case for i386 entry code
+ if ($#{$def{$name}} == 1 && $name =~ /^__kernel_/ &&
+ $def{$name}[0] eq "arch/i386/kernel/vsyscall-int80.o" &&
+ $def{$name}[1] eq "arch/i386/kernel/vsyscall-sysenter.o") {
+ &drop_def("arch/i386/kernel/vsyscall-sysenter.o", $name);
+ next;
+ }
+ printf "$name is multiply defined in :-\n";
+ foreach $module (@{$def{$name}}) {
+ printf "\t$module\n";
+ }
+ }
+ }
+}
+
+sub resolve_external_references
+{
+ my ($object, $type, $name, $i, $j, $kstrtab, $ksymtab, $export);
+ printf "\n";
+ foreach $object (keys(%nmdata)) {
+ my $nmdata = $nmdata{$object};
+ for ($i = 0; $i <= $#{$nmdata}; ++$i) {
+ ($type, $name) = split(' ', $nmdata->[$i], 2);
+ if ($type eq "U" || $type eq "w") {
+ if (exists($def{$name}) || exists($ksymtab{$name})) {
+ # add the owning object to the nmdata
+ $nmdata->[$i] = "$type $name $object";
+ # only count as a reference if it is not EXPORT_...
+ $kstrtab = "R __kstrtab_$name";
+ $ksymtab = "R __ksymtab_$name";
+ $export = 0;
+ for ($j = 0; $j <= $#{$nmdata}; ++$j) {
+ if ($nmdata->[$j] eq $kstrtab ||
+ $nmdata->[$j] eq $ksymtab) {
+ $export = 1;
+ last;
+ }
+ }
+ if ($export) {
+ $export{$name} = "";
+ }
+ else {
+ $ref{$name} = ""
+ }
+ }
+ elsif ( $name ne "mod_use_count_"
+ && $name ne "__initramfs_end"
+ && $name ne "__initramfs_start"
+ && $name ne "_einittext"
+ && $name ne "_sinittext"
+ && $name ne "kallsyms_names"
+ && $name ne "kallsyms_num_syms"
+ && $name ne "kallsyms_addresses"
+ && $name ne "__this_module"
+ && $name ne "_etext"
+ && $name ne "_edata"
+ && $name ne "_end"
+ && $name ne "__bss_start"
+ && $name ne "_text"
+ && $name ne "_stext"
+ && $name ne "__gp"
+ && $name ne "ia64_unw_start"
+ && $name ne "ia64_unw_end"
+ && $name ne "__init_begin"
+ && $name ne "__init_end"
+ && $name ne "__bss_stop"
+ && $name ne "__nosave_begin"
+ && $name ne "__nosave_end"
+ && $name ne "pg0"
+ && $name ne "__module_text_address"
+ && $name !~ /^__sched_text_/
+ && $name !~ /^__start_/
+ && $name !~ /^__end_/
+ && $name !~ /^__stop_/
+ && $name !~ /^__scheduling_functions_.*_here/
+ && $name !~ /^__.*initcall_/
+ && $name !~ /^__.*per_cpu_start/
+ && $name !~ /^__.*per_cpu_end/
+ && $name !~ /^__alt_instructions/
+ && $name !~ /^__setup_/
+ ) {
+ printf "Cannot resolve ";
+ printf "weak " if ($type eq "w");
+ printf "reference to $name from $object\n";
+ }
+ }
+ }
+ }
+}
+
+sub list_extra_externals
+{
+ my %noref = ();
+ my ($name, @module, $module, $export);
+ foreach $name (keys(%def)) {
+ if (! exists($ref{$name})) {
+ @module = @{$def{$name}};
+ foreach $module (@module) {
+ if (! exists($noref{$module})) {
+ $noref{$module} = [];
+ }
+ push(@{$noref{$module}}, $name);
+ }
+ }
+ }
+ if (%noref) {
+ printf "\nExternally defined symbols with no external references\n";
+ foreach $module (sort(keys(%noref))) {
+ printf " $module\n";
+ foreach (sort(@{$noref{$module}})) {
+ if (exists($export{$_})) {
+ $export = " (export only)";
+ }
+ else {
+ $export = "";
+ }
+ printf " $_$export\n";
+ }
+ }
+ }
+}
--- /dev/null
+/*
+ * ALSA driver for ATI IXP 150/200/250 AC97 modem controllers
+ *
+ * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <sound/driver.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/moduleparam.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/info.h>
+#include <sound/ac97_codec.h>
+#include <sound/initval.h>
+
+MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
+MODULE_DESCRIPTION("ATI IXP MC97 controller");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250}}");
+
+static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
+static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
+static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
+static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 48000};
+static int boot_devs;
+
+module_param_array(index, int, boot_devs, 0444);
+MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
+module_param_array(id, charp, boot_devs, 0444);
+MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
+module_param_array(enable, bool, boot_devs, 0444);
+MODULE_PARM_DESC(enable, "Enable audio part of ATI IXP controller.");
+module_param_array(ac97_clock, int, boot_devs, 0444);
+MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
+
+
+/*
+ */
+
+#define ATI_REG_ISR 0x00 /* interrupt source */
+#define ATI_REG_ISR_MODEM_IN_XRUN (1U<<0)
+#define ATI_REG_ISR_MODEM_IN_STATUS (1U<<1)
+#define ATI_REG_ISR_MODEM_OUT1_XRUN (1U<<2)
+#define ATI_REG_ISR_MODEM_OUT1_STATUS (1U<<3)
+#define ATI_REG_ISR_MODEM_OUT2_XRUN (1U<<4)
+#define ATI_REG_ISR_MODEM_OUT2_STATUS (1U<<5)
+#define ATI_REG_ISR_MODEM_OUT3_XRUN (1U<<6)
+#define ATI_REG_ISR_MODEM_OUT3_STATUS (1U<<7)
+#define ATI_REG_ISR_PHYS_INTR (1U<<8)
+#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
+#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
+#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
+#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
+#define ATI_REG_ISR_NEW_FRAME (1U<<13)
+#define ATI_REG_ISR_MODEM_GPIO_DATA (1U<<14)
+
+#define ATI_REG_IER 0x04 /* interrupt enable */
+#define ATI_REG_IER_MODEM_IN_XRUN_EN (1U<<0)
+#define ATI_REG_IER_MODEM_STATUS_EN (1U<<1)
+#define ATI_REG_IER_MODEM_OUT1_XRUN_EN (1U<<2)
+#define ATI_REG_IER_MODEM_OUT2_XRUN_EN (1U<<4)
+#define ATI_REG_IER_MODEM_OUT3_XRUN_EN (1U<<6)
+#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
+#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
+#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
+#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
+#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
+#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
+#define ATI_REG_IER_MODEM_GPIO_DATA_EN (1U<<14) /* (WO) modem is running */
+#define ATI_REG_IER_MODEM_SET_BUS_BUSY (1U<<15)
+
+#define ATI_REG_CMD 0x08 /* command */
+#define ATI_REG_CMD_POWERDOWN (1U<<0)
+#define ATI_REG_CMD_MODEM_RECEIVE_EN (1U<<1) /* modem only */
+#define ATI_REG_CMD_MODEM_SEND1_EN (1U<<2) /* modem only */
+#define ATI_REG_CMD_MODEM_SEND2_EN (1U<<3) /* modem only */
+#define ATI_REG_CMD_MODEM_SEND3_EN (1U<<4) /* modem only */
+#define ATI_REG_CMD_MODEM_STATUS_MEM (1U<<5) /* modem only */
+#define ATI_REG_CMD_MODEM_IN_DMA_EN (1U<<8) /* modem only */
+#define ATI_REG_CMD_MODEM_OUT_DMA1_EN (1U<<9) /* modem only */
+#define ATI_REG_CMD_MODEM_OUT_DMA2_EN (1U<<10) /* modem only */
+#define ATI_REG_CMD_MODEM_OUT_DMA3_EN (1U<<11) /* modem only */
+#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
+#define ATI_REG_CMD_MODEM_GPIO_THRU_DMA (1U<<22) /* modem only */
+#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
+#define ATI_REG_CMD_PACKED_DIS (1U<<24)
+#define ATI_REG_CMD_BURST_EN (1U<<25)
+#define ATI_REG_CMD_PANIC_EN (1U<<26)
+#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
+#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
+#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
+#define ATI_REG_CMD_AC_SYNC (1U<<30)
+#define ATI_REG_CMD_AC_RESET (1U<<31)
+
+#define ATI_REG_PHYS_OUT_ADDR 0x0c
+#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
+#define ATI_REG_PHYS_OUT_RW (1U<<2)
+#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
+#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
+#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
+
+#define ATI_REG_PHYS_IN_ADDR 0x10
+#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
+#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
+#define ATI_REG_PHYS_IN_DATA_SHIFT 16
+
+#define ATI_REG_SLOTREQ 0x14
+
+#define ATI_REG_COUNTER 0x18
+#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
+#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
+
+#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
+
+#define ATI_REG_MODEM_IN_DMA_LINKPTR 0x20
+#define ATI_REG_MODEM_IN_DMA_DT_START 0x24 /* RO */
+#define ATI_REG_MODEM_IN_DMA_DT_NEXT 0x28 /* RO */
+#define ATI_REG_MODEM_IN_DMA_DT_CUR 0x2c /* RO */
+#define ATI_REG_MODEM_IN_DMA_DT_SIZE 0x30
+#define ATI_REG_MODEM_OUT_FIFO 0x34 /* output threshold */
+#define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK (0xf<<16)
+#define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT 16
+#define ATI_REG_MODEM_OUT_DMA1_LINKPTR 0x38
+#define ATI_REG_MODEM_OUT_DMA2_LINKPTR 0x3c
+#define ATI_REG_MODEM_OUT_DMA3_LINKPTR 0x40
+#define ATI_REG_MODEM_OUT_DMA1_DT_START 0x44
+#define ATI_REG_MODEM_OUT_DMA1_DT_NEXT 0x48
+#define ATI_REG_MODEM_OUT_DMA1_DT_CUR 0x4c
+#define ATI_REG_MODEM_OUT_DMA2_DT_START 0x50
+#define ATI_REG_MODEM_OUT_DMA2_DT_NEXT 0x54
+#define ATI_REG_MODEM_OUT_DMA2_DT_CUR 0x58
+#define ATI_REG_MODEM_OUT_DMA3_DT_START 0x5c
+#define ATI_REG_MODEM_OUT_DMA3_DT_NEXT 0x60
+#define ATI_REG_MODEM_OUT_DMA3_DT_CUR 0x64
+#define ATI_REG_MODEM_OUT_DMA12_DT_SIZE 0x68
+#define ATI_REG_MODEM_OUT_DMA3_DT_SIZE 0x6c
+#define ATI_REG_MODEM_OUT_FIFO_USED 0x70
+#define ATI_REG_MODEM_OUT_GPIO 0x74
+#define ATI_REG_MODEM_OUT_GPIO_EN 1
+#define ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT 5
+#define ATI_REG_MODEM_IN_GPIO 0x78
+
+#define ATI_REG_MODEM_MIRROR 0x7c
+#define ATI_REG_AUDIO_MIRROR 0x80
+
+#define ATI_REG_MODEM_FIFO_FLUSH 0x88
+#define ATI_REG_MODEM_FIFO_OUT1_FLUSH (1U<<0)
+#define ATI_REG_MODEM_FIFO_OUT2_FLUSH (1U<<1)
+#define ATI_REG_MODEM_FIFO_OUT3_FLUSH (1U<<2)
+#define ATI_REG_MODEM_FIFO_IN_FLUSH (1U<<3)
+
+/* LINKPTR */
+#define ATI_REG_LINKPTR_EN (1U<<0)
+
+#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
+
+
+/*
+ */
+
+typedef struct snd_atiixp atiixp_t;
+typedef struct snd_atiixp_dma atiixp_dma_t;
+typedef struct snd_atiixp_dma_ops atiixp_dma_ops_t;
+
+
+/*
+ * DMA packate descriptor
+ */
+
+typedef struct atiixp_dma_desc {
+ u32 addr; /* DMA buffer address */
+ u16 status; /* status bits */
+ u16 size; /* size of the packet in dwords */
+ u32 next; /* address of the next packet descriptor */
+} atiixp_dma_desc_t;
+
+/*
+ * stream enum
+ */
+enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, NUM_ATI_DMAS }; /* DMAs */
+enum { ATI_PCM_OUT, ATI_PCM_IN, NUM_ATI_PCMS }; /* AC97 pcm slots */
+enum { ATI_PCMDEV_ANALOG, NUM_ATI_PCMDEVS }; /* pcm devices */
+
+#define NUM_ATI_CODECS 3
+
+
+/*
+ * constants and callbacks for each DMA type
+ */
+struct snd_atiixp_dma_ops {
+ int type; /* ATI_DMA_XXX */
+ unsigned int llp_offset; /* LINKPTR offset */
+ unsigned int dt_cur; /* DT_CUR offset */
+ void (*enable_dma)(atiixp_t *chip, int on); /* called from open callback */
+ void (*enable_transfer)(atiixp_t *chip, int on); /* called from trigger (START/STOP) */
+ void (*flush_dma)(atiixp_t *chip); /* called from trigger (STOP only) */
+};
+
+/*
+ * DMA stream
+ */
+struct snd_atiixp_dma {
+ const atiixp_dma_ops_t *ops;
+ struct snd_dma_buffer desc_buf;
+ snd_pcm_substream_t *substream; /* assigned PCM substream */
+ unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
+ unsigned int period_bytes, periods;
+ int opened;
+ int running;
+ int pcm_open_flag;
+ int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
+};
+
+/*
+ * ATI IXP chip
+ */
+struct snd_atiixp {
+ snd_card_t *card;
+ struct pci_dev *pci;
+
+ struct resource *res; /* memory i/o */
+ unsigned long addr;
+ void __iomem *remap_addr;
+ int irq;
+
+ ac97_bus_t *ac97_bus;
+ ac97_t *ac97[NUM_ATI_CODECS];
+
+ spinlock_t reg_lock;
+ spinlock_t ac97_lock;
+
+ atiixp_dma_t dmas[NUM_ATI_DMAS];
+ struct ac97_pcm *pcms[NUM_ATI_PCMS];
+ snd_pcm_t *pcmdevs[NUM_ATI_PCMDEVS];
+
+ int max_channels; /* max. channels for PCM out */
+
+ unsigned int codec_not_ready_bits; /* for codec detection */
+
+ int spdif_over_aclink; /* passed from the module option */
+ struct semaphore open_mutex; /* playback open mutex */
+};
+
+
+/*
+ */
+static struct pci_device_id snd_atiixp_ids[] = {
+ { 0x1002, 0x434d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
+
+
+/*
+ * lowlevel functions
+ */
+
+/*
+ * update the bits of the given register.
+ * return 1 if the bits changed.
+ */
+static int snd_atiixp_update_bits(atiixp_t *chip, unsigned int reg,
+ unsigned int mask, unsigned int value)
+{
+ void __iomem *addr = chip->remap_addr + reg;
+ unsigned int data, old_data;
+ old_data = data = readl(addr);
+ data &= ~mask;
+ data |= value;
+ if (old_data == data)
+ return 0;
+ writel(data, addr);
+ return 1;
+}
+
+/*
+ * macros for easy use
+ */
+#define atiixp_write(chip,reg,value) \
+ writel(value, chip->remap_addr + ATI_REG_##reg)
+#define atiixp_read(chip,reg) \
+ readl(chip->remap_addr + ATI_REG_##reg)
+#define atiixp_update(chip,reg,mask,val) \
+ snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
+
+/* delay for one tick */
+#define do_delay() do { \
+ set_current_state(TASK_UNINTERRUPTIBLE); \
+ schedule_timeout(1); \
+} while (0)
+
+
+/*
+ * handling DMA packets
+ *
+ * we allocate a linear buffer for the DMA, and split it to each packet.
+ * in a future version, a scatter-gather buffer should be implemented.
+ */
+
+#define ATI_DESC_LIST_SIZE \
+ PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(atiixp_dma_desc_t))
+
+/*
+ * build packets ring for the given buffer size.
+ *
+ * IXP handles the buffer descriptors, which are connected as a linked
+ * list. although we can change the list dynamically, in this version,
+ * a static RING of buffer descriptors is used.
+ *
+ * the ring is built in this function, and is set up to the hardware.
+ */
+static int atiixp_build_dma_packets(atiixp_t *chip, atiixp_dma_t *dma,
+ snd_pcm_substream_t *substream,
+ unsigned int periods,
+ unsigned int period_bytes)
+{
+ unsigned int i;
+ u32 addr, desc_addr;
+ unsigned long flags;
+
+ if (periods > ATI_MAX_DESCRIPTORS)
+ return -ENOMEM;
+
+ if (dma->desc_buf.area == NULL) {
+ if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
+ ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0)
+ return -ENOMEM;
+ dma->period_bytes = dma->periods = 0; /* clear */
+ }
+
+ if (dma->periods == periods && dma->period_bytes == period_bytes)
+ return 0;
+
+ /* reset DMA before changing the descriptor table */
+ spin_lock_irqsave(&chip->reg_lock, flags);
+ writel(0, chip->remap_addr + dma->ops->llp_offset);
+ dma->ops->enable_dma(chip, 0);
+ dma->ops->enable_dma(chip, 1);
+ spin_unlock_irqrestore(&chip->reg_lock, flags);
+
+ /* fill the entries */
+ addr = (u32)substream->runtime->dma_addr;
+ desc_addr = (u32)dma->desc_buf.addr;
+ for (i = 0; i < periods; i++) {
+ atiixp_dma_desc_t *desc = &((atiixp_dma_desc_t *)dma->desc_buf.area)[i];
+ desc->addr = cpu_to_le32(addr);
+ desc->status = 0;
+ desc->size = period_bytes >> 2; /* in dwords */
+ desc_addr += sizeof(atiixp_dma_desc_t);
+ if (i == periods - 1)
+ desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
+ else
+ desc->next = cpu_to_le32(desc_addr);
+ addr += period_bytes;
+ }
+
+ writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
+ chip->remap_addr + dma->ops->llp_offset);
+
+ dma->period_bytes = period_bytes;
+ dma->periods = periods;
+
+ return 0;
+}
+
+/*
+ * remove the ring buffer and release it if assigned
+ */
+static void atiixp_clear_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, snd_pcm_substream_t *substream)
+{
+ if (dma->desc_buf.area) {
+ writel(0, chip->remap_addr + dma->ops->llp_offset);
+ snd_dma_free_pages(&dma->desc_buf);
+ dma->desc_buf.area = NULL;
+ }
+}
+
+/*
+ * AC97 interface
+ */
+static int snd_atiixp_acquire_codec(atiixp_t *chip)
+{
+ int timeout = 1000;
+
+ while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
+ if (! timeout--) {
+ snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
+ return -EBUSY;
+ }
+ udelay(1);
+ }
+ return 0;
+}
+
+static unsigned short snd_atiixp_codec_read(atiixp_t *chip, unsigned short codec, unsigned short reg)
+{
+ unsigned int data;
+ int timeout;
+
+ if (snd_atiixp_acquire_codec(chip) < 0)
+ return 0xffff;
+ data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
+ ATI_REG_PHYS_OUT_ADDR_EN |
+ ATI_REG_PHYS_OUT_RW |
+ codec;
+ atiixp_write(chip, PHYS_OUT_ADDR, data);
+ if (snd_atiixp_acquire_codec(chip) < 0)
+ return 0xffff;
+ timeout = 1000;
+ do {
+ data = atiixp_read(chip, PHYS_IN_ADDR);
+ if (data & ATI_REG_PHYS_IN_READ_FLAG)
+ return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
+ udelay(1);
+ } while (--timeout);
+ /* time out may happen during reset */
+ if (reg < 0x7c)
+ snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
+ return 0xffff;
+}
+
+
+static void snd_atiixp_codec_write(atiixp_t *chip, unsigned short codec, unsigned short reg, unsigned short val)
+{
+ unsigned int data;
+
+ if (snd_atiixp_acquire_codec(chip) < 0)
+ return;
+ data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
+ ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
+ ATI_REG_PHYS_OUT_ADDR_EN | codec;
+ atiixp_write(chip, PHYS_OUT_ADDR, data);
+}
+
+
+static unsigned short snd_atiixp_ac97_read(ac97_t *ac97, unsigned short reg)
+{
+ atiixp_t *chip = ac97->private_data;
+ unsigned short data;
+ spin_lock(&chip->ac97_lock);
+ data = snd_atiixp_codec_read(chip, ac97->num, reg);
+ spin_unlock(&chip->ac97_lock);
+ return data;
+
+}
+
+static void snd_atiixp_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
+{
+ atiixp_t *chip = ac97->private_data;
+ spin_lock(&chip->ac97_lock);
+ snd_atiixp_codec_write(chip, ac97->num, reg, val);
+ spin_unlock(&chip->ac97_lock);
+}
+
+/*
+ * reset AC link
+ */
+static int snd_atiixp_aclink_reset(atiixp_t *chip)
+{
+ int timeout;
+
+ /* reset powerdoewn */
+ if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
+ udelay(10);
+
+ /* perform a software reset */
+ atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
+ atiixp_read(chip, CMD);
+ udelay(10);
+ atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
+
+ timeout = 10;
+ while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
+ /* do a hard reset */
+ atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
+ ATI_REG_CMD_AC_SYNC);
+ atiixp_read(chip, CMD);
+ do_delay();
+ atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
+ if (--timeout) {
+ snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
+ break;
+ }
+ }
+
+ /* deassert RESET and assert SYNC to make sure */
+ atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
+ ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int snd_atiixp_aclink_down(atiixp_t *chip)
+{
+ // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
+ // return -EBUSY;
+ atiixp_update(chip, CMD,
+ ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
+ ATI_REG_CMD_POWERDOWN);
+ return 0;
+}
+#endif
+
+/*
+ * auto-detection of codecs
+ *
+ * the IXP chip can generate interrupts for the non-existing codecs.
+ * NEW_FRAME interrupt is used to make sure that the interrupt is generated
+ * even if all three codecs are connected.
+ */
+
+#define ALL_CODEC_NOT_READY \
+ (ATI_REG_ISR_CODEC0_NOT_READY |\
+ ATI_REG_ISR_CODEC1_NOT_READY |\
+ ATI_REG_ISR_CODEC2_NOT_READY)
+#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
+
+static int snd_atiixp_codec_detect(atiixp_t *chip)
+{
+ int timeout;
+
+ chip->codec_not_ready_bits = 0;
+ atiixp_write(chip, IER, CODEC_CHECK_BITS);
+ /* wait for the interrupts */
+ timeout = HZ / 10;
+ while (timeout-- > 0) {
+ do_delay();
+ if (chip->codec_not_ready_bits)
+ break;
+ }
+ atiixp_write(chip, IER, 0); /* disable irqs */
+
+ if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
+ snd_printk(KERN_ERR "atiixp: no codec detected!\n");
+ return -ENXIO;
+ }
+ return 0;
+}
+
+
+/*
+ * enable DMA and irqs
+ */
+static int snd_atiixp_chip_start(atiixp_t *chip)
+{
+ unsigned int reg;
+
+ /* set up spdif, enable burst mode */
+ reg = atiixp_read(chip, CMD);
+ reg |= ATI_REG_CMD_BURST_EN;
+ if(!(reg & ATI_REG_CMD_MODEM_PRESENT))
+ reg |= ATI_REG_CMD_MODEM_PRESENT;
+ atiixp_write(chip, CMD, reg);
+
+ /* clear all interrupt source */
+ atiixp_write(chip, ISR, 0xffffffff);
+ /* enable irqs */
+ atiixp_write(chip, IER,
+ ATI_REG_IER_MODEM_STATUS_EN |
+ ATI_REG_IER_MODEM_IN_XRUN_EN |
+ ATI_REG_IER_MODEM_OUT1_XRUN_EN);
+ return 0;
+}
+
+
+/*
+ * disable DMA and IRQs
+ */
+static int snd_atiixp_chip_stop(atiixp_t *chip)
+{
+ /* clear interrupt source */
+ atiixp_write(chip, ISR, atiixp_read(chip, ISR));
+ /* disable irqs */
+ atiixp_write(chip, IER, 0);
+ return 0;
+}
+
+
+/*
+ * PCM section
+ */
+
+/*
+ * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
+ * position. when SG-buffer is implemented, the offset must be calculated
+ * correctly...
+ */
+static snd_pcm_uframes_t snd_atiixp_pcm_pointer(snd_pcm_substream_t *substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ atiixp_dma_t *dma = (atiixp_dma_t *)runtime->private_data;
+ unsigned int curptr;
+
+ spin_lock(&chip->reg_lock);
+ curptr = readl(chip->remap_addr + dma->ops->dt_cur);
+ if (curptr < dma->buf_addr) {
+ snd_printdd("curptr = %x, base = %x\n", curptr, dma->buf_addr);
+ curptr = 0;
+ } else {
+ curptr -= dma->buf_addr;
+ if (curptr >= dma->buf_bytes) {
+ snd_printdd("curptr = %x, size = %x\n", curptr, dma->buf_bytes);
+ curptr = 0;
+ }
+ }
+ spin_unlock(&chip->reg_lock);
+ return bytes_to_frames(runtime, curptr);
+}
+
+/*
+ * XRUN detected, and stop the PCM substream
+ */
+static void snd_atiixp_xrun_dma(atiixp_t *chip, atiixp_dma_t *dma)
+{
+ if (! dma->substream || ! dma->running)
+ return;
+ snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
+ snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
+}
+
+/*
+ * the period ack. update the substream.
+ */
+static void snd_atiixp_update_dma(atiixp_t *chip, atiixp_dma_t *dma)
+{
+ if (! dma->substream || ! dma->running)
+ return;
+ snd_pcm_period_elapsed(dma->substream);
+}
+
+/* set BUS_BUSY interrupt bit if any DMA is running */
+/* call with spinlock held */
+static void snd_atiixp_check_bus_busy(atiixp_t *chip)
+{
+ unsigned int bus_busy;
+ if (atiixp_read(chip, CMD) & (ATI_REG_CMD_MODEM_SEND1_EN |
+ ATI_REG_CMD_MODEM_RECEIVE_EN))
+ bus_busy = ATI_REG_IER_MODEM_SET_BUS_BUSY;
+ else
+ bus_busy = 0;
+ atiixp_update(chip, IER, ATI_REG_IER_MODEM_SET_BUS_BUSY, bus_busy);
+}
+
+/* common trigger callback
+ * calling the lowlevel callbacks in it
+ */
+static int snd_atiixp_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
+ unsigned int reg = 0;
+ int i;
+
+ snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL);
+
+ if (cmd != SNDRV_PCM_TRIGGER_START && cmd != SNDRV_PCM_TRIGGER_STOP)
+ return -EINVAL;
+
+ spin_lock(&chip->reg_lock);
+
+ /* hook off/on: via GPIO_OUT */
+ for (i = 0; i < NUM_ATI_CODECS; i++) {
+ if (chip->ac97[i]) {
+ reg = snd_ac97_read(chip->ac97[i], AC97_GPIO_STATUS);
+ break;
+ }
+ }
+ if(cmd == SNDRV_PCM_TRIGGER_START)
+ reg |= AC97_GPIO_LINE1_OH;
+ else
+ reg &= ~AC97_GPIO_LINE1_OH;
+ reg = (reg << ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT) | ATI_REG_MODEM_OUT_GPIO_EN ;
+ atiixp_write(chip, MODEM_OUT_GPIO, reg);
+
+ if (cmd == SNDRV_PCM_TRIGGER_START) {
+ dma->ops->enable_transfer(chip, 1);
+ dma->running = 1;
+ } else {
+ dma->ops->enable_transfer(chip, 0);
+ dma->running = 0;
+ }
+ snd_atiixp_check_bus_busy(chip);
+ if (cmd == SNDRV_PCM_TRIGGER_STOP) {
+ dma->ops->flush_dma(chip);
+ snd_atiixp_check_bus_busy(chip);
+ }
+ spin_unlock(&chip->reg_lock);
+ return 0;
+}
+
+
+/*
+ * lowlevel callbacks for each DMA type
+ *
+ * every callback is supposed to be called in chip->reg_lock spinlock
+ */
+
+/* flush FIFO of analog OUT DMA */
+static void atiixp_out_flush_dma(atiixp_t *chip)
+{
+ atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_OUT1_FLUSH);
+}
+
+/* enable/disable analog OUT DMA */
+static void atiixp_out_enable_dma(atiixp_t *chip, int on)
+{
+ unsigned int data;
+ data = atiixp_read(chip, CMD);
+ if (on) {
+ if (data & ATI_REG_CMD_MODEM_OUT_DMA1_EN)
+ return;
+ atiixp_out_flush_dma(chip);
+ data |= ATI_REG_CMD_MODEM_OUT_DMA1_EN;
+ } else
+ data &= ~ATI_REG_CMD_MODEM_OUT_DMA1_EN;
+ atiixp_write(chip, CMD, data);
+}
+
+/* start/stop transfer over OUT DMA */
+static void atiixp_out_enable_transfer(atiixp_t *chip, int on)
+{
+ atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_SEND1_EN,
+ on ? ATI_REG_CMD_MODEM_SEND1_EN : 0);
+}
+
+/* enable/disable analog IN DMA */
+static void atiixp_in_enable_dma(atiixp_t *chip, int on)
+{
+ atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_IN_DMA_EN,
+ on ? ATI_REG_CMD_MODEM_IN_DMA_EN : 0);
+}
+
+/* start/stop analog IN DMA */
+static void atiixp_in_enable_transfer(atiixp_t *chip, int on)
+{
+ if (on) {
+ unsigned int data = atiixp_read(chip, CMD);
+ if (! (data & ATI_REG_CMD_MODEM_RECEIVE_EN)) {
+ data |= ATI_REG_CMD_MODEM_RECEIVE_EN;
+ atiixp_write(chip, CMD, data);
+ }
+ } else
+ atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_RECEIVE_EN, 0);
+}
+
+/* flush FIFO of analog IN DMA */
+static void atiixp_in_flush_dma(atiixp_t *chip)
+{
+ atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_IN_FLUSH);
+}
+
+/* set up slots and formats for analog OUT */
+static int snd_atiixp_playback_prepare(snd_pcm_substream_t *substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ unsigned int data;
+
+ spin_lock_irq(&chip->reg_lock);
+ /* set output threshold */
+ data = atiixp_read(chip, MODEM_OUT_FIFO);
+ data &= ~ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK;
+ data |= 0x04 << ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT;
+ atiixp_write(chip, MODEM_OUT_FIFO, data);
+ spin_unlock_irq(&chip->reg_lock);
+ return 0;
+}
+
+/* set up slots and formats for analog IN */
+static int snd_atiixp_capture_prepare(snd_pcm_substream_t *substream)
+{
+ return 0;
+}
+
+/*
+ * hw_params - allocate the buffer and set up buffer descriptors
+ */
+static int snd_atiixp_pcm_hw_params(snd_pcm_substream_t *substream,
+ snd_pcm_hw_params_t *hw_params)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
+ int err;
+ int i;
+
+ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
+ if (err < 0)
+ return err;
+ dma->buf_addr = substream->runtime->dma_addr;
+ dma->buf_bytes = params_buffer_bytes(hw_params);
+
+ err = atiixp_build_dma_packets(chip, dma, substream,
+ params_periods(hw_params),
+ params_period_bytes(hw_params));
+ if (err < 0)
+ return err;
+
+ /* set up modem rate */
+ for (i = 0; i < NUM_ATI_CODECS; i++) {
+ if (! chip->ac97[i])
+ continue;
+ snd_ac97_write(chip->ac97[i], AC97_LINE1_RATE, params_rate(hw_params));
+ snd_ac97_write(chip->ac97[i], AC97_LINE1_LEVEL, 0);
+ }
+
+ return err;
+}
+
+static int snd_atiixp_pcm_hw_free(snd_pcm_substream_t * substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
+
+ atiixp_clear_dma_packets(chip, dma, substream);
+ snd_pcm_lib_free_pages(substream);
+ return 0;
+}
+
+
+/*
+ * pcm hardware definition, identical for all DMA types
+ */
+static snd_pcm_hardware_t snd_atiixp_pcm_hw =
+{
+ .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP_VALID),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
+ .rate_min = 8000,
+ .rate_max = 16000,
+ .channels_min = 2,
+ .channels_max = 2,
+ .buffer_bytes_max = 256 * 1024,
+ .period_bytes_min = 32,
+ .period_bytes_max = 128 * 1024,
+ .periods_min = 2,
+ .periods_max = ATI_MAX_DESCRIPTORS,
+};
+
+static int snd_atiixp_pcm_open(snd_pcm_substream_t *substream, atiixp_dma_t *dma, int pcm_type)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ int err;
+ static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
+ static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
+ .count = ARRAY_SIZE(rates),
+ .list = rates,
+ .mask = 0,
+ };
+
+ snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
+
+ if (dma->opened)
+ return -EBUSY;
+ dma->substream = substream;
+ runtime->hw = snd_atiixp_pcm_hw;
+ dma->ac97_pcm_type = pcm_type;
+ if ((err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates)) < 0)
+ return err;
+ if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
+ return err;
+ runtime->private_data = dma;
+
+ /* enable DMA bits */
+ spin_lock_irq(&chip->reg_lock);
+ dma->ops->enable_dma(chip, 1);
+ spin_unlock_irq(&chip->reg_lock);
+ dma->opened = 1;
+
+ return 0;
+}
+
+static int snd_atiixp_pcm_close(snd_pcm_substream_t *substream, atiixp_dma_t *dma)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ /* disable DMA bits */
+ snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
+ spin_lock_irq(&chip->reg_lock);
+ dma->ops->enable_dma(chip, 0);
+ spin_unlock_irq(&chip->reg_lock);
+ dma->substream = NULL;
+ dma->opened = 0;
+ return 0;
+}
+
+/*
+ */
+static int snd_atiixp_playback_open(snd_pcm_substream_t *substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ int err;
+
+ down(&chip->open_mutex);
+ err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
+ up(&chip->open_mutex);
+ if (err < 0)
+ return err;
+ return 0;
+}
+
+static int snd_atiixp_playback_close(snd_pcm_substream_t *substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ int err;
+ down(&chip->open_mutex);
+ err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
+ up(&chip->open_mutex);
+ return err;
+}
+
+static int snd_atiixp_capture_open(snd_pcm_substream_t *substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
+}
+
+static int snd_atiixp_capture_close(snd_pcm_substream_t *substream)
+{
+ atiixp_t *chip = snd_pcm_substream_chip(substream);
+ return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
+}
+
+
+/* AC97 playback */
+static snd_pcm_ops_t snd_atiixp_playback_ops = {
+ .open = snd_atiixp_playback_open,
+ .close = snd_atiixp_playback_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = snd_atiixp_pcm_hw_params,
+ .hw_free = snd_atiixp_pcm_hw_free,
+ .prepare = snd_atiixp_playback_prepare,
+ .trigger = snd_atiixp_pcm_trigger,
+ .pointer = snd_atiixp_pcm_pointer,
+};
+
+/* AC97 capture */
+static snd_pcm_ops_t snd_atiixp_capture_ops = {
+ .open = snd_atiixp_capture_open,
+ .close = snd_atiixp_capture_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = snd_atiixp_pcm_hw_params,
+ .hw_free = snd_atiixp_pcm_hw_free,
+ .prepare = snd_atiixp_capture_prepare,
+ .trigger = snd_atiixp_pcm_trigger,
+ .pointer = snd_atiixp_pcm_pointer,
+};
+
+static atiixp_dma_ops_t snd_atiixp_playback_dma_ops = {
+ .type = ATI_DMA_PLAYBACK,
+ .llp_offset = ATI_REG_MODEM_OUT_DMA1_LINKPTR,
+ .dt_cur = ATI_REG_MODEM_OUT_DMA1_DT_CUR,
+ .enable_dma = atiixp_out_enable_dma,
+ .enable_transfer = atiixp_out_enable_transfer,
+ .flush_dma = atiixp_out_flush_dma,
+};
+
+static atiixp_dma_ops_t snd_atiixp_capture_dma_ops = {
+ .type = ATI_DMA_CAPTURE,
+ .llp_offset = ATI_REG_MODEM_IN_DMA_LINKPTR,
+ .dt_cur = ATI_REG_MODEM_IN_DMA_DT_CUR,
+ .enable_dma = atiixp_in_enable_dma,
+ .enable_transfer = atiixp_in_enable_transfer,
+ .flush_dma = atiixp_in_flush_dma,
+};
+
+static int __devinit snd_atiixp_pcm_new(atiixp_t *chip)
+{
+ snd_pcm_t *pcm;
+ int err;
+
+ /* initialize constants */
+ chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
+ chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
+
+ /* PCM #0: analog I/O */
+ err = snd_pcm_new(chip->card, "ATI IXP MC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm);
+ if (err < 0)
+ return err;
+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
+ pcm->private_data = chip;
+ strcpy(pcm->name, "ATI IXP MC97");
+ chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
+
+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
+ snd_dma_pci_data(chip->pci), 64*1024, 128*1024);
+
+ return 0;
+}
+
+
+
+/*
+ * interrupt handler
+ */
+static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ atiixp_t *chip = dev_id;
+ unsigned int status;
+
+ status = atiixp_read(chip, ISR);
+
+ if (! status)
+ return IRQ_NONE;
+
+ /* process audio DMA */
+ if (status & ATI_REG_ISR_MODEM_OUT1_XRUN)
+ snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
+ else if (status & ATI_REG_ISR_MODEM_OUT1_STATUS)
+ snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
+ if (status & ATI_REG_ISR_MODEM_IN_XRUN)
+ snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
+ else if (status & ATI_REG_ISR_MODEM_IN_STATUS)
+ snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
+
+ /* for codec detection */
+ if (status & CODEC_CHECK_BITS) {
+ unsigned int detected;
+ detected = status & CODEC_CHECK_BITS;
+ spin_lock(&chip->reg_lock);
+ chip->codec_not_ready_bits |= detected;
+ atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
+ spin_unlock(&chip->reg_lock);
+ }
+
+ /* ack */
+ atiixp_write(chip, ISR, status);
+
+ return IRQ_HANDLED;
+}
+
+
+/*
+ * ac97 mixer section
+ */
+
+static int __devinit snd_atiixp_mixer_new(atiixp_t *chip, int clock)
+{
+ ac97_bus_t *pbus;
+ ac97_template_t ac97;
+ int i, err;
+ int codec_count;
+ static ac97_bus_ops_t ops = {
+ .write = snd_atiixp_ac97_write,
+ .read = snd_atiixp_ac97_read,
+ };
+ static unsigned int codec_skip[NUM_ATI_CODECS] = {
+ ATI_REG_ISR_CODEC0_NOT_READY,
+ ATI_REG_ISR_CODEC1_NOT_READY,
+ ATI_REG_ISR_CODEC2_NOT_READY,
+ };
+
+ if (snd_atiixp_codec_detect(chip) < 0)
+ return -ENXIO;
+
+ if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
+ return err;
+ pbus->clock = clock;
+ pbus->shared_type = AC97_SHARED_TYPE_ATIIXP; /* shared with audio driver */
+ chip->ac97_bus = pbus;
+
+ codec_count = 0;
+ for (i = 0; i < NUM_ATI_CODECS; i++) {
+ if (chip->codec_not_ready_bits & codec_skip[i])
+ continue;
+ memset(&ac97, 0, sizeof(ac97));
+ ac97.private_data = chip;
+ ac97.pci = chip->pci;
+ ac97.num = i;
+ ac97.scaps = AC97_SCAP_SKIP_AUDIO;
+ if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
+ chip->ac97[i] = NULL; /* to be sure */
+ snd_printdd("atiixp: codec %d not available for modem\n", i);
+ continue;
+ }
+ codec_count++;
+ }
+
+ if (! codec_count) {
+ snd_printk(KERN_ERR "atiixp: no codec available\n");
+ return -ENODEV;
+ }
+
+ /* snd_ac97_tune_hardware(chip->ac97, ac97_quirks); */
+
+ return 0;
+}
+
+
+#ifdef CONFIG_PM
+/*
+ * power management
+ */
+static int snd_atiixp_suspend(snd_card_t *card, unsigned int state)
+{
+ atiixp_t *chip = card->pm_private_data;
+ int i;
+
+ for (i = 0; i < NUM_ATI_PCMDEVS; i++)
+ if (chip->pcmdevs[i])
+ snd_pcm_suspend_all(chip->pcmdevs[i]);
+ for (i = 0; i < NUM_ATI_CODECS; i++)
+ if (chip->ac97[i])
+ snd_ac97_suspend(chip->ac97[i]);
+ snd_atiixp_aclink_down(chip);
+ snd_atiixp_chip_stop(chip);
+
+ pci_set_power_state(chip->pci, 3);
+ pci_disable_device(chip->pci);
+ snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
+ return 0;
+}
+
+static int snd_atiixp_resume(snd_card_t *card, unsigned int state)
+{
+ atiixp_t *chip = card->pm_private_data;
+ int i;
+
+ pci_enable_device(chip->pci);
+ pci_set_power_state(chip->pci, 0);
+
+ snd_atiixp_aclink_reset(chip);
+ snd_atiixp_chip_start(chip);
+
+ for (i = 0; i < NUM_ATI_CODECS; i++)
+ if (chip->ac97[i])
+ snd_ac97_resume(chip->ac97[i]);
+
+ snd_power_change_state(card, SNDRV_CTL_POWER_D0);
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+
+/*
+ * proc interface for register dump
+ */
+
+static void snd_atiixp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
+{
+ atiixp_t *chip = entry->private_data;
+ int i;
+
+ for (i = 0; i < 256; i += 4)
+ snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
+}
+
+static void __devinit snd_atiixp_proc_init(atiixp_t *chip)
+{
+ snd_info_entry_t *entry;
+
+ if (! snd_card_proc_new(chip->card, "atiixp", &entry))
+ snd_info_set_text_ops(entry, chip, 1024, snd_atiixp_proc_read);
+}
+
+
+
+/*
+ * destructor
+ */
+
+static int snd_atiixp_free(atiixp_t *chip)
+{
+ if (chip->irq < 0)
+ goto __hw_end;
+ snd_atiixp_chip_stop(chip);
+ synchronize_irq(chip->irq);
+ __hw_end:
+ if (chip->irq >= 0)
+ free_irq(chip->irq, (void *)chip);
+ if (chip->remap_addr)
+ iounmap(chip->remap_addr);
+ pci_release_regions(chip->pci);
+ kfree(chip);
+ return 0;
+}
+
+static int snd_atiixp_dev_free(snd_device_t *device)
+{
+ atiixp_t *chip = device->device_data;
+ return snd_atiixp_free(chip);
+}
+
+/*
+ * constructor for chip instance
+ */
+static int __devinit snd_atiixp_create(snd_card_t *card,
+ struct pci_dev *pci,
+ atiixp_t **r_chip)
+{
+ static snd_device_ops_t ops = {
+ .dev_free = snd_atiixp_dev_free,
+ };
+ atiixp_t *chip;
+ int err;
+
+ if ((err = pci_enable_device(pci)) < 0)
+ return err;
+
+ chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
+ if (chip == NULL)
+ return -ENOMEM;
+
+ spin_lock_init(&chip->reg_lock);
+ spin_lock_init(&chip->ac97_lock);
+ init_MUTEX(&chip->open_mutex);
+ chip->card = card;
+ chip->pci = pci;
+ chip->irq = -1;
+ if ((err = pci_request_regions(pci, "ATI IXP MC97")) < 0) {
+ kfree(chip);
+ return err;
+ }
+ chip->addr = pci_resource_start(pci, 0);
+ chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0));
+ if (chip->remap_addr == 0) {
+ snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
+ snd_atiixp_free(chip);
+ return -EIO;
+ }
+
+ if (request_irq(pci->irq, snd_atiixp_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
+ snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
+ snd_atiixp_free(chip);
+ return -EBUSY;
+ }
+ chip->irq = pci->irq;
+ pci_set_master(pci);
+ synchronize_irq(chip->irq);
+
+ if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
+ snd_atiixp_free(chip);
+ return err;
+ }
+
+ snd_card_set_dev(card, &pci->dev);
+
+ *r_chip = chip;
+ return 0;
+}
+
+
+static int __devinit snd_atiixp_probe(struct pci_dev *pci,
+ const struct pci_device_id *pci_id)
+{
+ static int dev;
+ snd_card_t *card;
+ atiixp_t *chip;
+ unsigned char revision;
+ int err;
+
+ if (dev >= SNDRV_CARDS)
+ return -ENODEV;
+ if (!enable[dev]) {
+ dev++;
+ return -ENOENT;
+ }
+
+ card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
+ if (card == NULL)
+ return -ENOMEM;
+
+ pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
+
+ strcpy(card->driver, "ATIIXP-MODEM");
+ strcpy(card->shortname, "ATI IXP Modem");
+ if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
+ goto __error;
+
+ if ((err = snd_atiixp_aclink_reset(chip)) < 0)
+ goto __error;
+
+ if ((err = snd_atiixp_mixer_new(chip, ac97_clock[dev])) < 0)
+ goto __error;
+
+ if ((err = snd_atiixp_pcm_new(chip)) < 0)
+ goto __error;
+
+ snd_atiixp_proc_init(chip);
+
+ snd_atiixp_chip_start(chip);
+
+ sprintf(card->longname, "%s rev %x at 0x%lx, irq %i",
+ card->shortname, revision, chip->addr, chip->irq);
+
+ snd_card_set_pm_callback(card, snd_atiixp_suspend, snd_atiixp_resume, chip);
+
+ if ((err = snd_card_register(card)) < 0)
+ goto __error;
+
+ pci_set_drvdata(pci, card);
+ dev++;
+ return 0;
+
+ __error:
+ snd_card_free(card);
+ return err;
+}
+
+static void __devexit snd_atiixp_remove(struct pci_dev *pci)
+{
+ snd_card_free(pci_get_drvdata(pci));
+ pci_set_drvdata(pci, NULL);
+}
+
+static struct pci_driver driver = {
+ .name = "ATI IXP MC97 controller",
+ .id_table = snd_atiixp_ids,
+ .probe = snd_atiixp_probe,
+ .remove = __devexit_p(snd_atiixp_remove),
+ SND_PCI_PM_CALLBACKS
+};
+
+
+static int __init alsa_card_atiixp_init(void)
+{
+ return pci_module_init(&driver);
+}
+
+static void __exit alsa_card_atiixp_exit(void)
+{
+ pci_unregister_driver(&driver);
+}
+
+module_init(alsa_card_atiixp_init)
+module_exit(alsa_card_atiixp_exit)
--- /dev/null
+/*
+ * ALSA driver for ICEnsemble VT1724 (Envy24HT)
+ *
+ * Lowlevel functions for Pontis MS300
+ *
+ * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <sound/driver.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/info.h>
+
+#include "ice1712.h"
+#include "envy24ht.h"
+#include "pontis.h"
+
+/* I2C addresses */
+#define WM_DEV 0x34
+#define CS_DEV 0x20
+
+/* WM8776 registers */
+#define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
+#define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
+#define WM_HP_MASTER 0x02 /* headphone master (both channels), override LLR */
+#define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
+#define WM_DAC_ATTEN_R 0x04
+#define WM_DAC_MASTER 0x05
+#define WM_PHASE_SWAP 0x06 /* DAC phase swap */
+#define WM_DAC_CTRL1 0x07
+#define WM_DAC_MUTE 0x08
+#define WM_DAC_CTRL2 0x09
+#define WM_DAC_INT 0x0a
+#define WM_ADC_INT 0x0b
+#define WM_MASTER_CTRL 0x0c
+#define WM_POWERDOWN 0x0d
+#define WM_ADC_ATTEN_L 0x0e
+#define WM_ADC_ATTEN_R 0x0f
+#define WM_ALC_CTRL1 0x10
+#define WM_ALC_CTRL2 0x11
+#define WM_ALC_CTRL3 0x12
+#define WM_NOISE_GATE 0x13
+#define WM_LIMITER 0x14
+#define WM_ADC_MUX 0x15
+#define WM_OUT_MUX 0x16
+#define WM_RESET 0x17
+
+/*
+ * GPIO
+ */
+#define PONTIS_CS_CS (1<<4) /* CS */
+#define PONTIS_CS_CLK (1<<5) /* CLK */
+#define PONTIS_CS_RDATA (1<<6) /* CS8416 -> VT1720 */
+#define PONTIS_CS_WDATA (1<<7) /* VT1720 -> CS8416 */
+
+
+/*
+ * get the current register value of WM codec
+ */
+static unsigned short wm_get(ice1712_t *ice, int reg)
+{
+ reg <<= 1;
+ return ((unsigned short)ice->akm[0].images[reg] << 8) |
+ ice->akm[0].images[reg + 1];
+}
+
+/*
+ * set the register value of WM codec and remember it
+ */
+static void wm_put_nocache(ice1712_t *ice, int reg, unsigned short val)
+{
+ unsigned short cval;
+ cval = (reg << 9) | val;
+ snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
+}
+
+static void wm_put(ice1712_t *ice, int reg, unsigned short val)
+{
+ wm_put_nocache(ice, reg, val);
+ reg <<= 1;
+ ice->akm[0].images[reg] = val >> 8;
+ ice->akm[0].images[reg + 1] = val;
+}
+
+/*
+ * DAC volume attenuation mixer control (-64dB to 0dB)
+ */
+
+#define DAC_0dB 0xff
+#define DAC_RES 128
+#define DAC_MIN (DAC_0dB - DAC_RES)
+
+static int wm_dac_vol_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 2;
+ uinfo->value.integer.min = 0; /* mute */
+ uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
+ return 0;
+}
+
+static int wm_dac_vol_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned short val;
+ int i;
+
+ down(&ice->gpio_mutex);
+ for (i = 0; i < 2; i++) {
+ val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
+ val = val > DAC_MIN ? (val - DAC_MIN) : 0;
+ ucontrol->value.integer.value[i] = val;
+ }
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int wm_dac_vol_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned short oval, nval;
+ int i, idx, change = 0;
+
+ down(&ice->gpio_mutex);
+ for (i = 0; i < 2; i++) {
+ nval = ucontrol->value.integer.value[i];
+ nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
+ idx = WM_DAC_ATTEN_L + i;
+ oval = wm_get(ice, idx) & 0xff;
+ if (oval != nval) {
+ wm_put(ice, idx, nval);
+ wm_put_nocache(ice, idx, nval | 0x100);
+ change = 1;
+ }
+ }
+ up(&ice->gpio_mutex);
+ return change;
+}
+
+/*
+ * ADC gain mixer control (-64dB to 0dB)
+ */
+
+#define ADC_0dB 0xcf
+#define ADC_RES 128
+#define ADC_MIN (ADC_0dB - ADC_RES)
+
+static int wm_adc_vol_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 2;
+ uinfo->value.integer.min = 0; /* mute (-64dB) */
+ uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
+ return 0;
+}
+
+static int wm_adc_vol_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned short val;
+ int i;
+
+ down(&ice->gpio_mutex);
+ for (i = 0; i < 2; i++) {
+ val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
+ val = val > ADC_MIN ? (val - ADC_MIN) : 0;
+ ucontrol->value.integer.value[i] = val;
+ }
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int wm_adc_vol_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned short ovol, nvol;
+ int i, idx, change = 0;
+
+ down(&ice->gpio_mutex);
+ for (i = 0; i < 2; i++) {
+ nvol = ucontrol->value.integer.value[i];
+ nvol = nvol ? (nvol + ADC_MIN) : 0;
+ idx = WM_ADC_ATTEN_L + i;
+ ovol = wm_get(ice, idx) & 0xff;
+ if (ovol != nvol) {
+ wm_put(ice, idx, nvol);
+ change = 1;
+ }
+ }
+ up(&ice->gpio_mutex);
+ return change;
+}
+
+/*
+ * ADC input mux mixer control
+ */
+static int wm_adc_mux_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+ return 0;
+}
+
+static int wm_adc_mux_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ int bit = kcontrol->private_value;
+
+ down(&ice->gpio_mutex);
+ ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int wm_adc_mux_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ int bit = kcontrol->private_value;
+ unsigned short oval, nval;
+ int change;
+
+ down(&ice->gpio_mutex);
+ nval = oval = wm_get(ice, WM_ADC_MUX);
+ if (ucontrol->value.integer.value[0])
+ nval |= (1 << bit);
+ else
+ nval &= ~(1 << bit);
+ change = nval != oval;
+ if (change) {
+ wm_put(ice, WM_ADC_MUX, nval);
+ }
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+/*
+ * Analog bypass (In -> Out)
+ */
+static int wm_bypass_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+ return 0;
+}
+
+static int wm_bypass_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+
+ down(&ice->gpio_mutex);
+ ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int wm_bypass_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned short val, oval;
+ int change = 0;
+
+ down(&ice->gpio_mutex);
+ val = oval = wm_get(ice, WM_OUT_MUX);
+ if (ucontrol->value.integer.value[0])
+ val |= 0x04;
+ else
+ val &= ~0x04;
+ if (val != oval) {
+ wm_put(ice, WM_OUT_MUX, val);
+ change = 1;
+ }
+ up(&ice->gpio_mutex);
+ return change;
+}
+
+/*
+ * Left/Right swap
+ */
+static int wm_chswap_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+ return 0;
+}
+
+static int wm_chswap_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+
+ down(&ice->gpio_mutex);
+ ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int wm_chswap_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned short val, oval;
+ int change = 0;
+
+ down(&ice->gpio_mutex);
+ oval = wm_get(ice, WM_DAC_CTRL1);
+ val = oval & 0x0f;
+ if (ucontrol->value.integer.value[0])
+ val |= 0x60;
+ else
+ val |= 0x90;
+ if (val != oval) {
+ wm_put(ice, WM_DAC_CTRL1, val);
+ wm_put_nocache(ice, WM_DAC_CTRL1, val);
+ change = 1;
+ }
+ up(&ice->gpio_mutex);
+ return change;
+}
+
+/*
+ * write data in the SPI mode
+ */
+static void set_gpio_bit(ice1712_t *ice, unsigned int bit, int val)
+{
+ unsigned int tmp = snd_ice1712_gpio_read(ice);
+ if (val)
+ tmp |= bit;
+ else
+ tmp &= ~bit;
+ snd_ice1712_gpio_write(ice, tmp);
+}
+
+static void spi_send_byte(ice1712_t *ice, unsigned char data)
+{
+ int i;
+ for (i = 0; i < 8; i++) {
+ set_gpio_bit(ice, PONTIS_CS_CLK, 0);
+ udelay(1);
+ set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
+ udelay(1);
+ set_gpio_bit(ice, PONTIS_CS_CLK, 1);
+ udelay(1);
+ data <<= 1;
+ }
+}
+
+static unsigned int spi_read_byte(ice1712_t *ice)
+{
+ int i;
+ unsigned int val = 0;
+
+ for (i = 0; i < 8; i++) {
+ val <<= 1;
+ set_gpio_bit(ice, PONTIS_CS_CLK, 0);
+ udelay(1);
+ if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
+ val |= 1;
+ udelay(1);
+ set_gpio_bit(ice, PONTIS_CS_CLK, 1);
+ udelay(1);
+ }
+ return val;
+}
+
+
+static void spi_write(ice1712_t *ice, unsigned int dev, unsigned int reg, unsigned int data)
+{
+ snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
+ snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
+ set_gpio_bit(ice, PONTIS_CS_CS, 0);
+ spi_send_byte(ice, dev & ~1); /* WRITE */
+ spi_send_byte(ice, reg); /* MAP */
+ spi_send_byte(ice, data); /* DATA */
+ /* trigger */
+ set_gpio_bit(ice, PONTIS_CS_CS, 1);
+ udelay(1);
+ /* restore */
+ snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
+ snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
+}
+
+static unsigned int spi_read(ice1712_t *ice, unsigned int dev, unsigned int reg)
+{
+ unsigned int val;
+ snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
+ snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
+ set_gpio_bit(ice, PONTIS_CS_CS, 0);
+ spi_send_byte(ice, dev & ~1); /* WRITE */
+ spi_send_byte(ice, reg); /* MAP */
+ /* trigger */
+ set_gpio_bit(ice, PONTIS_CS_CS, 1);
+ udelay(1);
+ set_gpio_bit(ice, PONTIS_CS_CS, 0);
+ spi_send_byte(ice, dev | 1); /* READ */
+ val = spi_read_byte(ice);
+ /* trigger */
+ set_gpio_bit(ice, PONTIS_CS_CS, 1);
+ udelay(1);
+ /* restore */
+ snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
+ snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
+ return val;
+}
+
+
+/*
+ * SPDIF input source
+ */
+static int cs_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ static char *texts[] = {
+ "Coax", /* RXP0 */
+ "Optical", /* RXP1 */
+ "CD", /* RXP2 */
+ };
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+ uinfo->count = 1;
+ uinfo->value.enumerated.items = 3;
+ if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
+ uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
+ strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
+ return 0;
+}
+
+static int cs_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+
+ down(&ice->gpio_mutex);
+ ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int cs_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned char val;
+ int change = 0;
+
+ down(&ice->gpio_mutex);
+ if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
+ ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
+ val = 0x80 | (ice->gpio.saved[0] << 3);
+ spi_write(ice, CS_DEV, 0x04, val);
+ change = 1;
+ }
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+
+/*
+ * GPIO controls
+ */
+static int pontis_gpio_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 0xffff; /* 16bit */
+ return 0;
+}
+
+static int pontis_gpio_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ down(&ice->gpio_mutex);
+ /* 4-7 reserved */
+ ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int pontis_gpio_mask_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned int val;
+ int changed;
+ down(&ice->gpio_mutex);
+ /* 4-7 reserved */
+ val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
+ changed = val != ice->gpio.write_mask;
+ ice->gpio.write_mask = val;
+ up(&ice->gpio_mutex);
+ return changed;
+}
+
+static int pontis_gpio_dir_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ down(&ice->gpio_mutex);
+ /* 4-7 reserved */
+ ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int pontis_gpio_dir_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned int val;
+ int changed;
+ down(&ice->gpio_mutex);
+ /* 4-7 reserved */
+ val = ucontrol->value.integer.value[0] & 0xff0f;
+ changed = (val != ice->gpio.direction);
+ ice->gpio.direction = val;
+ up(&ice->gpio_mutex);
+ return changed;
+}
+
+static int pontis_gpio_data_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ down(&ice->gpio_mutex);
+ snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
+ snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
+ ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
+ up(&ice->gpio_mutex);
+ return 0;
+}
+
+static int pontis_gpio_data_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ ice1712_t *ice = snd_kcontrol_chip(kcontrol);
+ unsigned int val, nval;
+ int changed = 0;
+ down(&ice->gpio_mutex);
+ snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
+ snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
+ val = snd_ice1712_gpio_read(ice) & 0xffff;
+ nval = ucontrol->value.integer.value[0] & 0xffff;
+ if (val != nval) {
+ snd_ice1712_gpio_write(ice, nval);
+ changed = 1;
+ }
+ up(&ice->gpio_mutex);
+ return changed;
+}
+
+/*
+ * mixers
+ */
+
+static snd_kcontrol_new_t pontis_controls[] __devinitdata = {
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "PCM Playback Volume",
+ .info = wm_dac_vol_info,
+ .get = wm_dac_vol_get,
+ .put = wm_dac_vol_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Capture Volume",
+ .info = wm_adc_vol_info,
+ .get = wm_adc_vol_get,
+ .put = wm_adc_vol_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "CD Capture Switch",
+ .info = wm_adc_mux_info,
+ .get = wm_adc_mux_get,
+ .put = wm_adc_mux_put,
+ .private_value = 0,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Line Capture Switch",
+ .info = wm_adc_mux_info,
+ .get = wm_adc_mux_get,
+ .put = wm_adc_mux_put,
+ .private_value = 1,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Analog Bypass Switch",
+ .info = wm_bypass_info,
+ .get = wm_bypass_get,
+ .put = wm_bypass_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Swap Output Channels",
+ .info = wm_chswap_info,
+ .get = wm_chswap_get,
+ .put = wm_chswap_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "IEC958 Input Source",
+ .info = cs_source_info,
+ .get = cs_source_get,
+ .put = cs_source_put,
+ },
+ /* FIXME: which interface? */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_CARD,
+ .name = "GPIO Mask",
+ .info = pontis_gpio_mask_info,
+ .get = pontis_gpio_mask_get,
+ .put = pontis_gpio_mask_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_CARD,
+ .name = "GPIO Direction",
+ .info = pontis_gpio_mask_info,
+ .get = pontis_gpio_dir_get,
+ .put = pontis_gpio_dir_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_CARD,
+ .name = "GPIO Data",
+ .info = pontis_gpio_mask_info,
+ .get = pontis_gpio_data_get,
+ .put = pontis_gpio_data_put,
+ },
+};
+
+
+/*
+ * WM codec registers
+ */
+static void wm_proc_regs_write(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
+{
+ ice1712_t *ice = (ice1712_t *)entry->private_data;
+ char line[64];
+ unsigned int reg, val;
+ down(&ice->gpio_mutex);
+ while (!snd_info_get_line(buffer, line, sizeof(line))) {
+ if (sscanf(line, "%x %x", ®, &val) != 2)
+ continue;
+ if (reg <= 0x17 && val <= 0xffff)
+ wm_put(ice, reg, val);
+ }
+ up(&ice->gpio_mutex);
+}
+
+static void wm_proc_regs_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
+{
+ ice1712_t *ice = (ice1712_t *)entry->private_data;
+ int reg, val;
+
+ down(&ice->gpio_mutex);
+ for (reg = 0; reg <= 0x17; reg++) {
+ val = wm_get(ice, reg);
+ snd_iprintf(buffer, "%02x = %04x\n", reg, val);
+ }
+ up(&ice->gpio_mutex);
+}
+
+static void wm_proc_init(ice1712_t *ice)
+{
+ snd_info_entry_t *entry;
+ if (! snd_card_proc_new(ice->card, "wm_codec", &entry)) {
+ snd_info_set_text_ops(entry, ice, 1024, wm_proc_regs_read);
+ entry->mode |= S_IWUSR;
+ entry->c.text.write_size = 1024;
+ entry->c.text.write = wm_proc_regs_write;
+ }
+}
+
+static void cs_proc_regs_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
+{
+ ice1712_t *ice = (ice1712_t *)entry->private_data;
+ int reg, val;
+
+ down(&ice->gpio_mutex);
+ for (reg = 0; reg <= 0x26; reg++) {
+ val = spi_read(ice, CS_DEV, reg);
+ snd_iprintf(buffer, "%02x = %02x\n", reg, val);
+ }
+ val = spi_read(ice, CS_DEV, 0x7f);
+ snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
+ up(&ice->gpio_mutex);
+}
+
+static void cs_proc_init(ice1712_t *ice)
+{
+ snd_info_entry_t *entry;
+ if (! snd_card_proc_new(ice->card, "cs_codec", &entry)) {
+ snd_info_set_text_ops(entry, ice, 1024, cs_proc_regs_read);
+ }
+}
+
+
+static int __devinit pontis_add_controls(ice1712_t *ice)
+{
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
+ err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
+ if (err < 0)
+ return err;
+ }
+
+ wm_proc_init(ice);
+ cs_proc_init(ice);
+
+ return 0;
+}
+
+
+/*
+ * initialize the chip
+ */
+static int __devinit pontis_init(ice1712_t *ice)
+{
+ static unsigned short wm_inits[] = {
+ /* These come first to reduce init pop noise */
+ WM_ADC_MUX, 0x00c0, /* ADC mute */
+ WM_DAC_MUTE, 0x0001, /* DAC softmute */
+ WM_DAC_CTRL1, 0x0000, /* DAC mute */
+
+ WM_POWERDOWN, 0x0008, /* All power-up except HP */
+ WM_RESET, 0x0000, /* reset */
+ };
+ static unsigned short wm_inits2[] = {
+ WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
+ WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
+ WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
+ WM_DAC_CTRL1, 0x0090, /* DAC L/R */
+ WM_OUT_MUX, 0x0001, /* OUT DAC */
+ WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
+ WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
+ WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
+ WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
+ WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
+ WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
+ // WM_DAC_MASTER, 0x0100, /* DAC master muted */
+ WM_PHASE_SWAP, 0x0000, /* phase normal */
+ WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
+ WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
+ WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
+#if 0
+ WM_ALC_CTRL1, 0x007b, /* */
+ WM_ALC_CTRL2, 0x0000, /* */
+ WM_ALC_CTRL3, 0x0000, /* */
+ WM_NOISE_GATE, 0x0000, /* */
+#endif
+ WM_DAC_MUTE, 0x0000, /* DAC unmute */
+ WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
+ };
+ static unsigned char cs_inits[] = {
+ 0x04, 0x80, /* RUN, RXP0 */
+ 0x05, 0x05, /* slave, 24bit */
+ 0x01, 0x00,
+ 0x02, 0x00,
+ 0x03, 0x00,
+ };
+ unsigned int i;
+
+ ice->vt1720 = 1;
+ ice->num_total_dacs = 2;
+ ice->num_total_adcs = 2;
+
+ /* to remeber the register values */
+ ice->akm = kcalloc(1, sizeof(akm4xxx_t), GFP_KERNEL);
+ if (! ice->akm)
+ return -ENOMEM;
+ ice->akm_codecs = 1;
+
+ /* HACK - use this as the SPDIF source.
+ * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
+ */
+ ice->gpio.saved[0] = 0;
+
+ /* initialize WM8776 codec */
+ for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
+ wm_put(ice, wm_inits[i], wm_inits[i+1]);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+ for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
+ wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
+
+ /* initialize CS8416 codec */
+ /* assert PRST#; MT05 bit 7 */
+ outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
+ mdelay(5);
+ /* deassert PRST# */
+ outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
+
+ for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
+ spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
+
+ return 0;
+}
+
+
+/*
+ * Pontis boards don't provide the EEPROM data at all.
+ * hence the driver needs to sets up it properly.
+ */
+
+static unsigned char pontis_eeprom[] __devinitdata = {
+ 0x08, /* SYSCONF: clock 256, mpu401, spdif-in/ADC, 1DAC */
+ 0x80, /* ACLINK: I2S */
+ 0xf8, /* I2S: vol, 96k, 24bit, 192k */
+ 0xc3, /* SPDIF: out-en, out-int, spdif-in */
+ 0x07, /* GPIO_DIR */
+ 0x00, /* GPIO_DIR1 */
+ 0x00, /* GPIO_DIR2 (ignored) */
+ 0x0f, /* GPIO_MASK (4-7 reserved for CS8416) */
+ 0xff, /* GPIO_MASK1 */
+ 0x00, /* GPIO_MASK2 (ignored) */
+ 0x06, /* GPIO_STATE (0-low, 1-high, 2-high) */
+ 0x00, /* GPIO_STATE1 */
+ 0x00, /* GPIO_STATE2 (ignored) */
+};
+
+/* entry point */
+struct snd_ice1712_card_info snd_vt1720_pontis_cards[] __devinitdata = {
+ {
+ .subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
+ .name = "Pontis MS300",
+ .model = "ms300",
+ .chip_init = pontis_init,
+ .build_controls = pontis_add_controls,
+ .eeprom_size = sizeof(pontis_eeprom),
+ .eeprom_data = pontis_eeprom,
+ },
+ { } /* terminator */
+};
--- /dev/null
+#ifndef __SOUND_PONTIS_H
+#define __SOUND_PONTIS_H
+
+/*
+ * ALSA driver for VIA VT1724 (Envy24HT)
+ *
+ * Lowlevel functions for Pontis MS300 boards
+ *
+ * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#define PONTIS_DEVICE_DESC "{Pontis,MS300},"
+
+#define VT1720_SUBDEVICE_PONTIS_MS300 0x00020002 /* a dummy id for MS300 */
+
+extern struct snd_ice1712_card_info snd_vt1720_pontis_cards[];
+
+#endif /* __SOUND_PONTIS_H */
--- /dev/null
+/*
+ * ALSA driver for VT1720/VT1724 (Envy24PT/Envy24HT)
+ *
+ * Lowlevel functions for VT1720-based motherboards
+ *
+ * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <sound/driver.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+
+#include "ice1712.h"
+#include "vt1720_mobo.h"
+
+
+static int __devinit k8x800_init(ice1712_t *ice)
+{
+ ice->vt1720 = 1;
+
+ /* VT1616 codec */
+ ice->num_total_dacs = 6;
+ ice->num_total_adcs = 2;
+
+ /* WM8728 codec */
+ /* FIXME: TODO */
+
+ return 0;
+}
+
+static int __devinit k8x800_add_controls(ice1712_t *ice)
+{
+ /* FIXME: needs some quirks for VT1616? */
+ return 0;
+}
+
+/* EEPROM image */
+
+static unsigned char k8x800_eeprom[] __devinitdata = {
+ 0x01, /* SYSCONF: clock 256, 1ADC, 2DACs */
+ 0x02, /* ACLINK: ACLINK, packed */
+ 0x00, /* I2S: - */
+ 0x00, /* SPDIF: - */
+ 0xff, /* GPIO_DIR */
+ 0xff, /* GPIO_DIR1 */
+ 0x00, /* - */
+ 0xff, /* GPIO_MASK */
+ 0xff, /* GPIO_MASK1 */
+ 0x00, /* - */
+ 0x00, /* GPIO_STATE */
+ 0x00, /* GPIO_STATE1 */
+ 0x00, /* - */
+};
+
+
+/* entry point */
+struct snd_ice1712_card_info snd_vt1720_mobo_cards[] __devinitdata = {
+ {
+ .subvendor = VT1720_SUBDEVICE_K8X800,
+ .name = "Albatron K8X800 Pro II",
+ .model = "k8x800",
+ .chip_init = k8x800_init,
+ .build_controls = k8x800_add_controls,
+ .eeprom_size = sizeof(k8x800_eeprom),
+ .eeprom_data = k8x800_eeprom,
+ },
+ {
+ .subvendor = VT1720_SUBDEVICE_ZNF3_150,
+ .name = "Chaintech ZNF3-150",
+ /* identical with k8x800 */
+ .chip_init = k8x800_init,
+ .build_controls = k8x800_add_controls,
+ .eeprom_size = sizeof(k8x800_eeprom),
+ .eeprom_data = k8x800_eeprom,
+ },
+ {
+ .subvendor = VT1720_SUBDEVICE_ZNF3_250,
+ .name = "Chaintech ZNF3-250",
+ /* identical with k8x800 */
+ .chip_init = k8x800_init,
+ .build_controls = k8x800_add_controls,
+ .eeprom_size = sizeof(k8x800_eeprom),
+ .eeprom_data = k8x800_eeprom,
+ },
+ { } /* terminator */
+};
+
--- /dev/null
+#ifndef __SOUND_VT1720_MOBO_H
+#define __SOUND_VT1720_MOBO_H
+
+/*
+ * ALSA driver for VT1720/VT1724 (Envy24PT/Envy24HT)
+ *
+ * Lowlevel functions for VT1720-based motherboards
+ *
+ * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#define VT1720_MOBO_DEVICE_DESC "{Albatron,K8X800 Pro II},"\
+ "{Chaintech,ZNF3-150},"\
+ "{Chaintech,ZNF3-250},"
+
+#define VT1720_SUBDEVICE_K8X800 0xf217052c
+#define VT1720_SUBDEVICE_ZNF3_150 0x0f2741f6
+#define VT1720_SUBDEVICE_ZNF3_250 0x0f2745f6
+
+extern struct snd_ice1712_card_info snd_vt1720_mobo_cards[];
+
+#endif /* __SOUND_VT1720_MOBO_H */
--- /dev/null
+/*
+ * Beep using pcm
+ *
+ * Copyright (c) by Takashi Iwai <tiwai@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <sound/driver.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <sound/core.h>
+#include <sound/control.h>
+#include "pmac.h"
+
+struct snd_pmac_beep {
+ int running; /* boolean */
+ int volume; /* mixer volume: 0-100 */
+ int volume_play; /* currently playing volume */
+ int hz;
+ int nsamples;
+ short *buf; /* allocated wave buffer */
+ unsigned long addr; /* physical address of buffer */
+ struct input_dev dev;
+};
+
+/*
+ * stop beep if running
+ */
+void snd_pmac_beep_stop(pmac_t *chip)
+{
+ pmac_beep_t *beep = chip->beep;
+ if (beep && beep->running) {
+ beep->running = 0;
+ snd_pmac_beep_dma_stop(chip);
+ }
+}
+
+/*
+ * Stuff for outputting a beep. The values range from -327 to +327
+ * so we can multiply by an amplitude in the range 0..100 to get a
+ * signed short value to put in the output buffer.
+ */
+static short beep_wform[256] = {
+ 0, 40, 79, 117, 153, 187, 218, 245,
+ 269, 288, 304, 316, 323, 327, 327, 324,
+ 318, 310, 299, 288, 275, 262, 249, 236,
+ 224, 213, 204, 196, 190, 186, 183, 182,
+ 182, 183, 186, 189, 192, 196, 200, 203,
+ 206, 208, 209, 209, 209, 207, 204, 201,
+ 197, 193, 188, 183, 179, 174, 170, 166,
+ 163, 161, 160, 159, 159, 160, 161, 162,
+ 164, 166, 168, 169, 171, 171, 171, 170,
+ 169, 167, 163, 159, 155, 150, 144, 139,
+ 133, 128, 122, 117, 113, 110, 107, 105,
+ 103, 103, 103, 103, 104, 104, 105, 105,
+ 105, 103, 101, 97, 92, 86, 78, 68,
+ 58, 45, 32, 18, 3, -11, -26, -41,
+ -55, -68, -79, -88, -95, -100, -102, -102,
+ -99, -93, -85, -75, -62, -48, -33, -16,
+ 0, 16, 33, 48, 62, 75, 85, 93,
+ 99, 102, 102, 100, 95, 88, 79, 68,
+ 55, 41, 26, 11, -3, -18, -32, -45,
+ -58, -68, -78, -86, -92, -97, -101, -103,
+ -105, -105, -105, -104, -104, -103, -103, -103,
+ -103, -105, -107, -110, -113, -117, -122, -128,
+ -133, -139, -144, -150, -155, -159, -163, -167,
+ -169, -170, -171, -171, -171, -169, -168, -166,
+ -164, -162, -161, -160, -159, -159, -160, -161,
+ -163, -166, -170, -174, -179, -183, -188, -193,
+ -197, -201, -204, -207, -209, -209, -209, -208,
+ -206, -203, -200, -196, -192, -189, -186, -183,
+ -182, -182, -183, -186, -190, -196, -204, -213,
+ -224, -236, -249, -262, -275, -288, -299, -310,
+ -318, -324, -327, -327, -323, -316, -304, -288,
+ -269, -245, -218, -187, -153, -117, -79, -40,
+};
+
+#define BEEP_SRATE 22050 /* 22050 Hz sample rate */
+#define BEEP_BUFLEN 512
+#define BEEP_VOLUME 15 /* 0 - 100 */
+
+static int snd_pmac_beep_event(struct input_dev *dev, unsigned int type, unsigned int code, int hz)
+{
+ pmac_t *chip;
+ pmac_beep_t *beep;
+ unsigned long flags;
+ int beep_speed = 0;
+ int srate;
+ int period, ncycles, nsamples;
+ int i, j, f;
+ short *p;
+
+ if (type != EV_SND)
+ return -1;
+
+ switch (code) {
+ case SND_BELL: if (hz) hz = 1000;
+ case SND_TONE: break;
+ default: return -1;
+ }
+
+ chip = dev->private;
+ if (! chip || (beep = chip->beep) == NULL)
+ return -1;
+
+ if (! hz) {
+ spin_lock_irqsave(&chip->reg_lock, flags);
+ if (beep->running)
+ snd_pmac_beep_stop(chip);
+ spin_unlock_irqrestore(&chip->reg_lock, flags);
+ return 0;
+ }
+
+ beep_speed = snd_pmac_rate_index(chip, &chip->playback, BEEP_SRATE);
+ srate = chip->freq_table[beep_speed];
+
+ if (hz <= srate / BEEP_BUFLEN || hz > srate / 2)
+ hz = 1000;
+
+ spin_lock_irqsave(&chip->reg_lock, flags);
+ if (chip->playback.running || chip->capture.running || beep->running) {
+ spin_unlock_irqrestore(&chip->reg_lock, flags);
+ return 0;
+ }
+ beep->running = 1;
+ spin_unlock_irqrestore(&chip->reg_lock, flags);
+
+ if (hz == beep->hz && beep->volume == beep->volume_play) {
+ nsamples = beep->nsamples;
+ } else {
+ period = srate * 256 / hz; /* fixed point */
+ ncycles = BEEP_BUFLEN * 256 / period;
+ nsamples = (period * ncycles) >> 8;
+ f = ncycles * 65536 / nsamples;
+ j = 0;
+ p = beep->buf;
+ for (i = 0; i < nsamples; ++i, p += 2) {
+ p[0] = p[1] = beep_wform[j >> 8] * beep->volume;
+ j = (j + f) & 0xffff;
+ }
+ beep->hz = hz;
+ beep->volume_play = beep->volume;
+ beep->nsamples = nsamples;
+ }
+
+ spin_lock_irqsave(&chip->reg_lock, flags);
+ snd_pmac_beep_dma_start(chip, beep->nsamples * 4, beep->addr, beep_speed);
+ spin_unlock_irqrestore(&chip->reg_lock, flags);
+ return 0;
+}
+
+/*
+ * beep volume mixer
+ */
+
+#define chip_t pmac_t
+
+static int snd_pmac_info_beep(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 100;
+ return 0;
+}
+
+static int snd_pmac_get_beep(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ pmac_t *chip = snd_kcontrol_chip(kcontrol);
+ snd_assert(chip->beep, return -ENXIO);
+ ucontrol->value.integer.value[0] = chip->beep->volume;
+ return 0;
+}
+
+static int snd_pmac_put_beep(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+ pmac_t *chip = snd_kcontrol_chip(kcontrol);
+ int oval;
+ snd_assert(chip->beep, return -ENXIO);
+ oval = chip->beep->volume;
+ chip->beep->volume = ucontrol->value.integer.value[0];
+ return oval != chip->beep->volume;
+}
+
+static snd_kcontrol_new_t snd_pmac_beep_mixer = {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Beep Playback Volume",
+ .info = snd_pmac_info_beep,
+ .get = snd_pmac_get_beep,
+ .put = snd_pmac_put_beep,
+};
+
+/* Initialize beep stuff */
+int __init snd_pmac_attach_beep(pmac_t *chip)
+{
+ pmac_beep_t *beep;
+ int err;
+
+ beep = kmalloc(sizeof(*beep), GFP_KERNEL);
+ if (! beep)
+ return -ENOMEM;
+
+ memset(beep, 0, sizeof(*beep));
+ beep->buf = (short *) kmalloc(BEEP_BUFLEN * 4, GFP_KERNEL);
+ if (! beep->buf) {
+ kfree(beep);
+ return -ENOMEM;
+ }
+ beep->addr = virt_to_bus(beep->buf);
+
+ beep->dev.evbit[0] = BIT(EV_SND);
+ beep->dev.sndbit[0] = BIT(SND_BELL) | BIT(SND_TONE);
+ beep->dev.event = snd_pmac_beep_event;
+ beep->dev.private = chip;
+
+ /* FIXME: set more better values */
+ beep->dev.name = "PowerMac Beep";
+ beep->dev.phys = "powermac/beep";
+ beep->dev.id.bustype = BUS_ADB;
+ beep->dev.id.vendor = 0x001f;
+ beep->dev.id.product = 0x0001;
+ beep->dev.id.version = 0x0100;
+
+ beep->volume = BEEP_VOLUME;
+ beep->running = 0;
+ if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_pmac_beep_mixer, chip))) < 0) {
+ kfree(beep->buf);
+ kfree(beep);
+ return err;
+ }
+
+ chip->beep = beep;
+ input_register_device(&beep->dev);
+
+ return 0;
+}
+
+void snd_pmac_detach_beep(pmac_t *chip)
+{
+ if (chip->beep) {
+ input_unregister_device(&chip->beep->dev);
+ kfree(chip->beep->buf);
+ kfree(chip->beep);
+ chip->beep = NULL;
+ }
+}
--- /dev/null
+snd-usb-usx2y-objs := usbusx2y.o usbusx2yaudio.o usX2Yhwdep.o
+
+obj-$(CONFIG_SND_USB_USX2Y) += snd-usb-usx2y.o
--- /dev/null
+/*
+ * Driver for Tascam US-X2Y USB soundcards
+ *
+ * FPGA Loader + ALSA Startup
+ *
+ * Copyright (c) 2003 by Karsten Wiese <annabellesgarden@yahoo.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <sound/driver.h>
+#include <linux/interrupt.h>
+#include <linux/usb.h>
+#include <sound/core.h>
+#include <sound/memalloc.h>
+#include <sound/pcm.h>
+#include <sound/hwdep.h>
+#include "usx2y.h"
+#include "usbusx2y.h"
+#include "usX2Yhwdep.h"
+
+
+static struct page * snd_us428ctls_vm_nopage(struct vm_area_struct *area, unsigned long address, int *type)
+{
+ unsigned long offset;
+ struct page * page;
+ void *vaddr;
+
+ snd_printdd("ENTER, start %lXh, ofs %lXh, pgoff %ld, addr %lXh\n",
+ area->vm_start,
+ address - area->vm_start,
+ (address - area->vm_start) >> PAGE_SHIFT,
+ address);
+
+ offset = area->vm_pgoff << PAGE_SHIFT;
+ offset += address - area->vm_start;
+ snd_assert((offset % PAGE_SIZE) == 0, return NOPAGE_OOM);
+ vaddr = (char*)((usX2Ydev_t*)area->vm_private_data)->us428ctls_sharedmem + offset;
+ page = virt_to_page(vaddr);
+ get_page(page);
+ snd_printdd( "vaddr=%p made us428ctls_vm_nopage() return %p; offset=%lX\n", vaddr, page, offset);
+
+ if (type)
+ *type = VM_FAULT_MINOR;
+
+ return page;
+}
+
+static struct vm_operations_struct us428ctls_vm_ops = {
+ .nopage = snd_us428ctls_vm_nopage,
+};
+
+static int snd_us428ctls_mmap(snd_hwdep_t * hw, struct file *filp, struct vm_area_struct *area)
+{
+ unsigned long size = (unsigned long)(area->vm_end - area->vm_start);
+ usX2Ydev_t *us428 = (usX2Ydev_t*)hw->private_data;
+
+ // FIXME this hwdep interface is used twice: fpga download and mmap for controlling Lights etc. Maybe better using 2 hwdep devs?
+ // so as long as the device isn't fully initialised yet we return -EBUSY here.
+ if (!(((usX2Ydev_t*)hw->private_data)->chip_status & USX2Y_STAT_CHIP_INIT))
+ return -EBUSY;
+
+ /* if userspace tries to mmap beyond end of our buffer, fail */
+ if (size > ((PAGE_SIZE - 1 + sizeof(us428ctls_sharedmem_t)) / PAGE_SIZE) * PAGE_SIZE) {
+ snd_printd( "%lu > %lu\n", size, (unsigned long)sizeof(us428ctls_sharedmem_t));
+ return -EINVAL;
+ }
+
+ if (!us428->us428ctls_sharedmem) {
+ init_waitqueue_head(&us428->us428ctls_wait_queue_head);
+ if(!(us428->us428ctls_sharedmem = snd_malloc_pages(sizeof(us428ctls_sharedmem_t), GFP_KERNEL)))
+ return -ENOMEM;
+ memset(us428->us428ctls_sharedmem, -1, sizeof(us428ctls_sharedmem_t));
+ us428->us428ctls_sharedmem->CtlSnapShotLast = -2;
+ }
+ area->vm_ops = &us428ctls_vm_ops;
+ area->vm_flags |= VM_RESERVED;
+ area->vm_private_data = hw->private_data;
+ return 0;
+}
+
+static unsigned int snd_us428ctls_poll(snd_hwdep_t *hw, struct file *file, poll_table *wait)
+{
+ unsigned int mask = 0;
+ usX2Ydev_t *us428 = (usX2Ydev_t*)hw->private_data;
+ static unsigned LastN;
+
+ if (us428->chip_status & USX2Y_STAT_CHIP_HUP)
+ return POLLHUP;
+
+ poll_wait(file, &us428->us428ctls_wait_queue_head, wait);
+
+ down(&us428->open_mutex);
+ if (us428->us428ctls_sharedmem
+ && us428->us428ctls_sharedmem->CtlSnapShotLast != LastN) {
+ mask |= POLLIN;
+ LastN = us428->us428ctls_sharedmem->CtlSnapShotLast;
+ }
+ up(&us428->open_mutex);
+
+ return mask;
+}
+
+
+static int snd_usX2Y_hwdep_open(snd_hwdep_t *hw, struct file *file)
+{
+ return 0;
+}
+
+static int snd_usX2Y_hwdep_release(snd_hwdep_t *hw, struct file *file)
+{
+ return 0;
+}
+
+static int snd_usX2Y_hwdep_dsp_status(snd_hwdep_t *hw, snd_hwdep_dsp_status_t *info)
+{
+ static char *type_ids[USX2Y_TYPE_NUMS] = {
+ [USX2Y_TYPE_122] = "us122",
+ [USX2Y_TYPE_224] = "us224",
+ [USX2Y_TYPE_428] = "us428",
+ };
+ int id = -1;
+
+ switch (((usX2Ydev_t*)hw->private_data)->chip.dev->descriptor.idProduct) {
+ case USB_ID_US122:
+ id = USX2Y_TYPE_122;
+ break;
+ case USB_ID_US224:
+ id = USX2Y_TYPE_224;
+ break;
+ case USB_ID_US428:
+ id = USX2Y_TYPE_428;
+ break;
+ }
+ if (0 > id)
+ return -ENODEV;
+ strcpy(info->id, type_ids[id]);
+ info->num_dsps = 2; // 0: Prepad Data, 1: FPGA Code
+ if (((usX2Ydev_t*)hw->private_data)->chip_status & USX2Y_STAT_CHIP_INIT)
+ info->chip_ready = 1;
+ info->version = USX2Y_DRIVER_VERSION;
+ return 0;
+}
+
+
+static int usX2Y_create_usbmidi(snd_card_t* card )
+{
+ static snd_usb_midi_endpoint_info_t quirk_data_1 = {
+ .out_ep =0x06,
+ .in_ep = 0x06,
+ .out_cables = 0x001,
+ .in_cables = 0x001
+ };
+ static snd_usb_audio_quirk_t quirk_1 = {
+ .vendor_name = "TASCAM",
+ .product_name = NAME_ALLCAPS,
+ .ifnum = 0,
+ .type = QUIRK_MIDI_FIXED_ENDPOINT,
+ .data = &quirk_data_1
+ };
+ static snd_usb_midi_endpoint_info_t quirk_data_2 = {
+ .out_ep =0x06,
+ .in_ep = 0x06,
+ .out_cables = 0x003,
+ .in_cables = 0x003
+ };
+ static snd_usb_audio_quirk_t quirk_2 = {
+ .vendor_name = "TASCAM",
+ .product_name = "US428",
+ .ifnum = 0,
+ .type = QUIRK_MIDI_FIXED_ENDPOINT,
+ .data = &quirk_data_2
+ };
+ struct usb_device *dev = usX2Y(card)->chip.dev;
+ struct usb_interface *iface = usb_ifnum_to_if(dev, 0);
+ snd_usb_audio_quirk_t *quirk = dev->descriptor.idProduct == USB_ID_US428 ? &quirk_2 : &quirk_1;
+
+ snd_printdd("usX2Y_create_usbmidi \n");
+ return snd_usb_create_midi_interface(&usX2Y(card)->chip, iface, quirk);
+}
+
+static int usX2Y_create_alsa_devices(snd_card_t* card)
+{
+ int err;
+
+ do {
+ if ((err = usX2Y_create_usbmidi(card)) < 0) {
+ snd_printk("usX2Y_create_alsa_devices: usX2Y_create_usbmidi error %i \n", err);
+ break;
+ }
+ if ((err = usX2Y_audio_create(card)) < 0)
+ break;
+ if ((err = snd_card_register(card)) < 0)
+ break;
+ } while (0);
+
+ return err;
+}
+
+static int snd_usX2Y_hwdep_dsp_load(snd_hwdep_t *hw, snd_hwdep_dsp_image_t *dsp)
+{
+ usX2Ydev_t *priv = hw->private_data;
+ int lret, err = -EINVAL;
+ snd_printdd( "dsp_load %s\n", dsp->name);
+
+ if (access_ok(VERIFY_READ, dsp->image, dsp->length)) {
+ struct usb_device* dev = priv->chip.dev;
+ char *buf = kmalloc(dsp->length, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+ if (copy_from_user(buf, dsp->image, dsp->length)) {
+ kfree(buf);
+ return -EFAULT;
+ }
+ err = usb_set_interface(dev, 0, 1);
+ if (err)
+ snd_printk("usb_set_interface error \n");
+ else
+ err = usb_bulk_msg(dev, usb_sndbulkpipe(dev, 2), buf, dsp->length, &lret, 6*HZ);
+ kfree(buf);
+ }
+ if (err)
+ return err;
+ if (dsp->index == 1) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ/4); // give the device some time
+ err = usX2Y_AsyncSeq04_init(priv);
+ if (err) {
+ snd_printk("usX2Y_AsyncSeq04_init error \n");
+ return err;
+ }
+ err = usX2Y_In04_init(priv);
+ if (err) {
+ snd_printk("usX2Y_In04_init error \n");
+ return err;
+ }
+ err = usX2Y_create_alsa_devices(hw->card);
+ if (err) {
+ snd_printk("usX2Y_create_alsa_devices error %i \n", err);
+ snd_card_free(hw->card);
+ return err;
+ }
+ priv->chip_status |= USX2Y_STAT_CHIP_INIT;
+ snd_printdd("%s: alsa all started\n", hw->name);
+ }
+ return err;
+}
+
+
+int usX2Y_hwdep_new(snd_card_t* card, struct usb_device* device)
+{
+ int err;
+ snd_hwdep_t *hw;
+
+ if ((err = snd_hwdep_new(card, SND_USX2Y_LOADER_ID, 0, &hw)) < 0)
+ return err;
+
+ hw->iface = SNDRV_HWDEP_IFACE_USX2Y;
+ hw->private_data = usX2Y(card);
+ hw->ops.open = snd_usX2Y_hwdep_open;
+ hw->ops.release = snd_usX2Y_hwdep_release;
+ hw->ops.dsp_status = snd_usX2Y_hwdep_dsp_status;
+ hw->ops.dsp_load = snd_usX2Y_hwdep_dsp_load;
+ hw->ops.mmap = snd_us428ctls_mmap;
+ hw->ops.poll = snd_us428ctls_poll;
+ hw->exclusive = 1;
+ sprintf(hw->name, "/proc/bus/usb/%03d/%03d", device->bus->busnum, device->devnum);
+ return 0;
+}
+
--- /dev/null
+#ifndef USX2YHWDEP_H
+#define USX2YHWDEP_H
+
+int usX2Y_hwdep_new(snd_card_t* card, struct usb_device* device);
+
+#endif
--- /dev/null
+/*
+ *
+ * Copyright (c) 2003 by Karsten Wiese <annabellesgarden@yahoo.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+enum E_In84{
+ eFader0 = 0,
+ eFader1,
+ eFader2,
+ eFader3,
+ eFader4,
+ eFader5,
+ eFader6,
+ eFader7,
+ eFaderM,
+ eTransport,
+ eModifier = 10,
+ eFilterSelect,
+ eSelect,
+ eMute,
+
+ eSwitch = 15,
+ eWheelGain,
+ eWheelFreq,
+ eWheelQ,
+ eWheelPan,
+ eWheel = 20
+};
+
+#define T_RECORD 1
+#define T_PLAY 2
+#define T_STOP 4
+#define T_F_FWD 8
+#define T_REW 0x10
+#define T_SOLO 0x20
+#define T_REC 0x40
+#define T_NULL 0x80
+
+
+struct us428_ctls{
+ unsigned char Fader[9];
+ unsigned char Transport;
+ unsigned char Modifier;
+ unsigned char FilterSelect;
+ unsigned char Select;
+ unsigned char Mute;
+ unsigned char UNKNOWN;
+ unsigned char Switch;
+ unsigned char Wheel[5];
+};
+
+typedef struct us428_ctls us428_ctls_t;
+
+typedef struct us428_setByte{
+ unsigned char Offset,
+ Value;
+}us428_setByte_t;
+
+enum {
+ eLT_Volume = 0,
+ eLT_Light
+};
+
+typedef struct usX2Y_volume {
+ unsigned char Channel,
+ LH,
+ LL,
+ RH,
+ RL;
+} usX2Y_volume_t;
+
+struct us428_lights{
+ us428_setByte_t Light[7];
+};
+typedef struct us428_lights us428_lights_t;
+
+typedef struct {
+ char type;
+ union {
+ usX2Y_volume_t vol;
+ us428_lights_t lights;
+ } val;
+} us428_p4out_t;
+
+#define N_us428_ctl_BUFS 16
+#define N_us428_p4out_BUFS 16
+struct us428ctls_sharedmem{
+ us428_ctls_t CtlSnapShot[N_us428_ctl_BUFS];
+ int CtlSnapShotDiffersAt[N_us428_ctl_BUFS];
+ int CtlSnapShotLast, CtlSnapShotRed;
+ us428_p4out_t p4out[N_us428_p4out_BUFS];
+ int p4outLast, p4outSent;
+};
+typedef struct us428ctls_sharedmem us428ctls_sharedmem_t;
--- /dev/null
+/*
+ * usbus428.c - ALSA USB US-428 Driver
+ *
+2004-07-13 Karsten Wiese
+ Version 0.7.1:
+ Don't sleep in START/STOP callbacks anymore.
+ us428 channels C/D not handled just for this version, sorry.
+
+2004-06-21 Karsten Wiese
+ Version 0.6.4:
+ Temporarely suspend midi input
+ to sanely call usb_set_interface() when setting format.
+
+2004-06-12 Karsten Wiese
+ Version 0.6.3:
+ Made it thus the following rule is enforced:
+ "All pcm substreams of one usX2Y have to operate at the same rate & format."
+
+2004-04-06 Karsten Wiese
+ Version 0.6.0:
+ Runs on 2.6.5 kernel without any "--with-debug=" things.
+ us224 reported running.
+
+2004-01-14 Karsten Wiese
+ Version 0.5.1:
+ Runs with 2.6.1 kernel.
+
+2003-12-30 Karsten Wiese
+ Version 0.4.1:
+ Fix 24Bit 4Channel capturing for the us428.
+
+2003-11-27 Karsten Wiese, Martin Langer
+ Version 0.4:
+ us122 support.
+ us224 could be tested by uncommenting the sections containing USB_ID_US224
+
+2003-11-03 Karsten Wiese
+ Version 0.3:
+ 24Bit support.
+ "arecord -D hw:1 -c 2 -r 48000 -M -f S24_3LE|aplay -D hw:1 -c 2 -r 48000 -M -f S24_3LE" works.
+
+2003-08-22 Karsten Wiese
+ Version 0.0.8:
+ Removed EZUSB Firmware. First Stage Firmwaredownload is now done by tascam-firmware downloader.
+ See:
+ http://usb-midi-fw.sourceforge.net/tascam-firmware.tar.gz
+
+2003-06-18 Karsten Wiese
+ Version 0.0.5:
+ changed to compile with kernel 2.4.21 and alsa 0.9.4
+
+2002-10-16 Karsten Wiese
+ Version 0.0.4:
+ compiles again with alsa-current.
+ USB_ISO_ASAP not used anymore (most of the time), instead
+ urb->start_frame is calculated here now, some calls inside usb-driver don't need to happen anymore.
+
+ To get the best out of this:
+ Disable APM-support in the kernel as APM-BIOS calls (once each second) hard disable interrupt for many precious milliseconds.
+ This helped me much on my slowish PII 400 & PIII 500.
+ ACPI yet untested but might cause the same bad behaviour.
+ Use a kernel with lowlatency and preemptiv patches applied.
+ To autoload snd-usb-midi append a line
+ post-install snd-usb-us428 modprobe snd-usb-midi
+ to /etc/modules.conf.
+
+ known problems:
+ sliders, knobs, lights not yet handled except MASTER Volume slider.
+ "pcm -c 2" doesn't work. "pcm -c 2 -m direct_interleaved" does.
+ KDE3: "Enable full duplex operation" deadlocks.
+
+
+2002-08-31 Karsten Wiese
+ Version 0.0.3: audio also simplex;
+ simplifying: iso urbs only 1 packet, melted structs.
+ ASYNC_UNLINK not used anymore: no more crashes so far.....
+ for alsa 0.9 rc3.
+
+2002-08-09 Karsten Wiese
+ Version 0.0.2: midi works with snd-usb-midi, audio (only fullduplex now) with i.e. bristol.
+ The firmware has been sniffed from win2k us-428 driver 3.09.
+
+ * Copyright (c) 2002 Karsten Wiese
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <sound/driver.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/interrupt.h>
+#include <linux/usb.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+
+#include <sound/rawmidi.h>
+#include "usx2y.h"
+#include "usbusx2y.h"
+#include "usX2Yhwdep.h"
+
+
+
+MODULE_AUTHOR("Karsten Wiese <annabellesgarden@yahoo.de>");
+MODULE_DESCRIPTION("TASCAM "NAME_ALLCAPS" Version 0.7.2");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("{{TASCAM(0x1604), "NAME_ALLCAPS"(0x8001)(0x8005)(0x8007) }}");
+
+static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-max */
+static char* id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* Id for this card */
+static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
+static int boot_devs;
+
+module_param_array(index, int, boot_devs, 0444);
+MODULE_PARM_DESC(index, "Index value for "NAME_ALLCAPS".");
+module_param_array(id, charp, boot_devs, 0444);
+MODULE_PARM_DESC(id, "ID string for "NAME_ALLCAPS".");
+module_param_array(enable, bool, boot_devs, 0444);
+MODULE_PARM_DESC(enable, "Enable "NAME_ALLCAPS".");
+
+
+static int snd_usX2Y_card_used[SNDRV_CARDS];
+
+static void usX2Y_usb_disconnect(struct usb_device* usb_device, void* ptr);
+static void snd_usX2Y_card_private_free(snd_card_t *card);
+
+/*
+ * pipe 4 is used for switching the lamps, setting samplerate, volumes ....
+ */
+static void i_usX2Y_Out04Int(struct urb* urb, struct pt_regs *regs)
+{
+#ifdef CONFIG_SND_DEBUG
+ if (urb->status) {
+ int i;
+ usX2Ydev_t* usX2Y = urb->context;
+ for (i = 0; i < 10 && usX2Y->AS04.urb[i] != urb; i++);
+ snd_printdd("i_usX2Y_Out04Int() urb %i status=%i\n", i, urb->status);
+ }
+#endif
+}
+
+static void i_usX2Y_In04Int(struct urb* urb, struct pt_regs *regs)
+{
+ int err = 0;
+ usX2Ydev_t *usX2Y = urb->context;
+ us428ctls_sharedmem_t *us428ctls = usX2Y->us428ctls_sharedmem;
+
+ usX2Y->In04IntCalls++;
+
+ if (urb->status) {
+ snd_printdd("Interrupt Pipe 4 came back with status=%i\n", urb->status);
+ return;
+ }
+
+ // printk("%i:0x%02X ", 8, (int)((unsigned char*)usX2Y->In04Buf)[8]); Master volume shows 0 here if fader is at max during boot ?!?
+ if (us428ctls) {
+ int diff = -1;
+ if (-2 == us428ctls->CtlSnapShotLast) {
+ diff = 0;
+ memcpy(usX2Y->In04Last, usX2Y->In04Buf, sizeof(usX2Y->In04Last));
+ us428ctls->CtlSnapShotLast = -1;
+ } else {
+ int i;
+ for (i = 0; i < 21; i++) {
+ if (usX2Y->In04Last[i] != ((char*)usX2Y->In04Buf)[i]) {
+ if (diff < 0)
+ diff = i;
+ usX2Y->In04Last[i] = ((char*)usX2Y->In04Buf)[i];
+ }
+ }
+ }
+ if (0 <= diff) {
+ int n = us428ctls->CtlSnapShotLast + 1;
+ if (n >= N_us428_ctl_BUFS || n < 0)
+ n = 0;
+ memcpy(us428ctls->CtlSnapShot + n, usX2Y->In04Buf, sizeof(us428ctls->CtlSnapShot[0]));
+ us428ctls->CtlSnapShotDiffersAt[n] = diff;
+ us428ctls->CtlSnapShotLast = n;
+ wake_up(&usX2Y->us428ctls_wait_queue_head);
+ }
+ }
+
+
+ if (usX2Y->US04) {
+ if (0 == usX2Y->US04->submitted)
+ do
+ err = usb_submit_urb(usX2Y->US04->urb[usX2Y->US04->submitted++], GFP_ATOMIC);
+ while (!err && usX2Y->US04->submitted < usX2Y->US04->len);
+ } else
+ if (us428ctls && us428ctls->p4outLast >= 0 && us428ctls->p4outLast < N_us428_p4out_BUFS) {
+ if (us428ctls->p4outLast != us428ctls->p4outSent) {
+ int j, send = us428ctls->p4outSent + 1;
+ if (send >= N_us428_p4out_BUFS)
+ send = 0;
+ for (j = 0; j < URBS_AsyncSeq && !err; ++j)
+ if (0 == usX2Y->AS04.urb[j]->status) {
+ us428_p4out_t *p4out = us428ctls->p4out + send; // FIXME if more then 1 p4out is new, 1 gets lost.
+ usb_fill_bulk_urb(usX2Y->AS04.urb[j], usX2Y->chip.dev,
+ usb_sndbulkpipe(usX2Y->chip.dev, 0x04), &p4out->val.vol,
+ p4out->type == eLT_Light ? sizeof(us428_lights_t) : 5,
+ i_usX2Y_Out04Int, usX2Y);
+ err = usb_submit_urb(usX2Y->AS04.urb[j], GFP_ATOMIC);
+ us428ctls->p4outSent = send;
+ break;
+ }
+ }
+ }
+
+ if (err) {
+ snd_printk("In04Int() usb_submit_urb err=%i\n", err);
+ }
+
+ urb->dev = usX2Y->chip.dev;
+ usb_submit_urb(urb, GFP_ATOMIC);
+}
+
+/*
+ * Prepare some urbs
+ */
+int usX2Y_AsyncSeq04_init(usX2Ydev_t* usX2Y)
+{
+ int err = 0,
+ i;
+
+ if (NULL == (usX2Y->AS04.buffer = kmalloc(URB_DataLen_AsyncSeq*URBS_AsyncSeq, GFP_KERNEL))) {
+ err = -ENOMEM;
+ } else
+ for (i = 0; i < URBS_AsyncSeq; ++i) {
+ if (NULL == (usX2Y->AS04.urb[i] = usb_alloc_urb(0, GFP_KERNEL))) {
+ err = -ENOMEM;
+ break;
+ }
+ usb_fill_bulk_urb( usX2Y->AS04.urb[i], usX2Y->chip.dev,
+ usb_sndbulkpipe(usX2Y->chip.dev, 0x04),
+ usX2Y->AS04.buffer + URB_DataLen_AsyncSeq*i, 0,
+ i_usX2Y_Out04Int, usX2Y
+ );
+ }
+ return err;
+}
+
+int usX2Y_In04_init(usX2Ydev_t* usX2Y)
+{
+ int err = 0;
+ if (! (usX2Y->In04urb = usb_alloc_urb(0, GFP_KERNEL)))
+ return -ENOMEM;
+
+ if (! (usX2Y->In04Buf = kmalloc(21, GFP_KERNEL))) {
+ usb_free_urb(usX2Y->In04urb);
+ return -ENOMEM;
+ }
+
+ init_waitqueue_head(&usX2Y->In04WaitQueue);
+ usb_fill_int_urb(usX2Y->In04urb, usX2Y->chip.dev, usb_rcvintpipe(usX2Y->chip.dev, 0x4),
+ usX2Y->In04Buf, 21,
+ i_usX2Y_In04Int, usX2Y,
+ 10);
+ err = usb_submit_urb(usX2Y->In04urb, GFP_KERNEL);
+ return err;
+}
+
+static void usX2Y_unlinkSeq(snd_usX2Y_AsyncSeq_t* S)
+{
+ int i;
+ for (i = 0; i < URBS_AsyncSeq; ++i) {
+ if (S[i].urb) {
+ usb_unlink_urb(S->urb[i]);
+ usb_free_urb(S->urb[i]);
+ S->urb[i] = NULL;
+ }
+ }
+ if (S->buffer)
+ kfree(S->buffer);
+}
+
+
+static struct usb_device_id snd_usX2Y_usb_id_table[] = {
+ {
+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE,
+ .idVendor = 0x1604,
+ .idProduct = USB_ID_US428
+ },
+ {
+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE,
+ .idVendor = 0x1604,
+ .idProduct = USB_ID_US122
+ },
+ {
+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE,
+ .idVendor = 0x1604,
+ .idProduct = USB_ID_US224
+ },
+ { /* terminator */ }
+};
+
+static snd_card_t* usX2Y_create_card(struct usb_device* device)
+{
+ int dev;
+ snd_card_t* card;
+ for (dev = 0; dev < SNDRV_CARDS; ++dev)
+ if (enable[dev] && !snd_usX2Y_card_used[dev])
+ break;
+ if (dev >= SNDRV_CARDS)
+ return NULL;
+ card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(usX2Ydev_t));
+ if (!card)
+ return NULL;
+ snd_usX2Y_card_used[usX2Y(card)->chip.index = dev] = 1;
+ card->private_free = snd_usX2Y_card_private_free;
+ usX2Y(card)->chip.dev = device;
+ usX2Y(card)->chip.card = card;
+ init_MUTEX (&usX2Y(card)->open_mutex);
+ INIT_LIST_HEAD(&usX2Y(card)->chip.midi_list);
+ strcpy(card->driver, "USB "NAME_ALLCAPS"");
+ sprintf(card->shortname, "TASCAM "NAME_ALLCAPS"");
+ sprintf(card->longname, "%s (%x:%x if %d at %03d/%03d)",
+ card->shortname,
+ device->descriptor.idVendor, device->descriptor.idProduct,
+ 0,//us428(card)->usbmidi.ifnum,
+ usX2Y(card)->chip.dev->bus->busnum, usX2Y(card)->chip.dev->devnum
+ );
+ snd_card_set_dev(card, &device->dev);
+ return card;
+}
+
+
+static void* usX2Y_usb_probe(struct usb_device* device, struct usb_interface *intf, const struct usb_device_id* device_id)
+{
+ int err;
+ snd_card_t* card;
+ if (device->descriptor.idVendor != 0x1604 ||
+ (device->descriptor.idProduct != USB_ID_US122 &&
+ device->descriptor.idProduct != USB_ID_US224 &&
+ device->descriptor.idProduct != USB_ID_US428) ||
+ !(card = usX2Y_create_card(device)))
+ return NULL;
+ if ((err = usX2Y_hwdep_new(card, device)) < 0 ||
+ (err = snd_card_register(card)) < 0) {
+ snd_card_free(card);
+ return NULL;
+ }
+ return card;
+}
+
+/*
+ * new 2.5 USB kernel API
+ */
+static int snd_usX2Y_probe(struct usb_interface *intf, const struct usb_device_id *id)
+{
+ void *chip;
+ chip = usX2Y_usb_probe(interface_to_usbdev(intf), intf, id);
+ if (chip) {
+ dev_set_drvdata(&intf->dev, chip);
+ return 0;
+ } else
+ return -EIO;
+}
+
+static void snd_usX2Y_disconnect(struct usb_interface *intf)
+{
+ usX2Y_usb_disconnect(interface_to_usbdev(intf),
+ dev_get_drvdata(&intf->dev));
+}
+
+MODULE_DEVICE_TABLE(usb, snd_usX2Y_usb_id_table);
+static struct usb_driver snd_usX2Y_usb_driver = {
+ .owner = THIS_MODULE,
+ .name = "snd-usb-usx2y",
+ .probe = snd_usX2Y_probe,
+ .disconnect = snd_usX2Y_disconnect,
+ .id_table = snd_usX2Y_usb_id_table,
+};
+
+static void snd_usX2Y_card_private_free(snd_card_t *card)
+{
+ if (usX2Y(card)->In04Buf)
+ kfree(usX2Y(card)->In04Buf);
+ usb_free_urb(usX2Y(card)->In04urb);
+ if (usX2Y(card)->us428ctls_sharedmem)
+ snd_free_pages(usX2Y(card)->us428ctls_sharedmem, sizeof(*usX2Y(card)->us428ctls_sharedmem));
+ if (usX2Y(card)->chip.index >= 0 && usX2Y(card)->chip.index < SNDRV_CARDS)
+ snd_usX2Y_card_used[usX2Y(card)->chip.index] = 0;
+}
+
+/*
+ * Frees the device.
+ */
+static void usX2Y_usb_disconnect(struct usb_device* device, void* ptr)
+{
+ if (ptr) {
+ usX2Ydev_t* usX2Y = usX2Y((snd_card_t*)ptr);
+ struct list_head* p;
+ if (usX2Y->chip_status == USX2Y_STAT_CHIP_HUP) // on 2.6.1 kernel snd_usbmidi_disconnect()
+ return; // calls us back. better leave :-) .
+ usX2Y->chip.shutdown = 1;
+ usX2Y->chip_status = USX2Y_STAT_CHIP_HUP;
+ usX2Y_unlinkSeq(&usX2Y->AS04);
+ usb_unlink_urb(usX2Y->In04urb);
+ snd_card_disconnect((snd_card_t*)ptr);
+ /* release the midi resources */
+ list_for_each(p, &usX2Y->chip.midi_list) {
+ snd_usbmidi_disconnect(p, &snd_usX2Y_usb_driver);
+ }
+ if (usX2Y->us428ctls_sharedmem)
+ wake_up(&usX2Y->us428ctls_wait_queue_head);
+ snd_card_free_in_thread((snd_card_t*)ptr);
+ }
+}
+
+static int __init snd_usX2Y_module_init(void)
+{
+ return usb_register(&snd_usX2Y_usb_driver);
+}
+
+static void __exit snd_usX2Y_module_exit(void)
+{
+ usb_deregister(&snd_usX2Y_usb_driver);
+}
+
+module_init(snd_usX2Y_module_init)
+module_exit(snd_usX2Y_module_exit)
--- /dev/null
+#ifndef USBUSX2Y_H
+#define USBUSX2Y_H
+#include "../usbaudio.h"
+#include "usbus428ctldefs.h"
+
+#define NRURBS 2 /* */
+#define NRPACKS 1 /* FIXME: Currently only 1 works.
+ usb-frames/ms per urb: 1 and 2 are supported.
+ setting to 2 will PERHAPS make it easier for slow machines.
+ Jitter will be higher though.
+ On my PIII 500Mhz Laptop setting to 1 is the only way to go
+ for PLAYING synths. i.e. Jack & Aeolus sound quit nicely
+ at 4 periods 64 frames.
+ */
+
+#define URBS_AsyncSeq 10
+#define URB_DataLen_AsyncSeq 32
+typedef struct {
+ struct urb* urb[URBS_AsyncSeq];
+ char* buffer;
+} snd_usX2Y_AsyncSeq_t;
+
+typedef struct {
+ int submitted;
+ int len;
+ struct urb* urb[0];
+} snd_usX2Y_urbSeq_t;
+
+typedef struct snd_usX2Y_substream snd_usX2Y_substream_t;
+
+typedef struct {
+ snd_usb_audio_t chip;
+ int stride;
+ struct urb *In04urb;
+ void *In04Buf;
+ char In04Last[24];
+ unsigned In04IntCalls;
+ snd_usX2Y_urbSeq_t *US04;
+ wait_queue_head_t In04WaitQueue;
+ snd_usX2Y_AsyncSeq_t AS04;
+ unsigned int rate,
+ format;
+ int refframes;
+ int chip_status;
+ struct semaphore open_mutex;
+ us428ctls_sharedmem_t *us428ctls_sharedmem;
+ wait_queue_head_t us428ctls_wait_queue_head;
+ snd_usX2Y_substream_t *substream[4];
+} usX2Ydev_t;
+
+
+#define usX2Y(c) ((usX2Ydev_t*)(c)->private_data)
+
+int usX2Y_audio_create(snd_card_t* card);
+
+int usX2Y_AsyncSeq04_init(usX2Ydev_t* usX2Y);
+int usX2Y_In04_init(usX2Ydev_t* usX2Y);
+
+#define NAME_ALLCAPS "US-X2Y"
+
+#endif
--- /dev/null
+/*
+ * US-428 AUDIO
+
+ * Copyright (c) 2002-2003 by Karsten Wiese
+
+ * based on
+
+ * (Tentative) USB Audio Driver for ALSA
+ *
+ * Main and PCM part
+ *
+ * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
+ *
+ * Many codes borrowed from audio.c by
+ * Alan Cox (alan@lxorguk.ukuu.org.uk)
+ * Thomas Sailer (sailer@ife.ee.ethz.ch)
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+#include <sound/driver.h>
+#include <linux/interrupt.h>
+#include <linux/usb.h>
+#include <sound/core.h>
+#include <sound/info.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include "usx2y.h"
+#include "usbusx2y.h"
+
+
+struct snd_usX2Y_substream {
+ usX2Ydev_t *usX2Y;
+ snd_pcm_substream_t *pcm_substream;
+
+ unsigned char endpoint;
+ unsigned int datapipe; /* the data i/o pipe */
+ unsigned int maxpacksize; /* max packet size in bytes */
+
+ char prepared,
+ running,
+ stalled;
+
+ int hwptr; /* free frame position in the buffer (only for playback) */
+ int hwptr_done; /* processed frame position in the buffer */
+ int transfer_done; /* processed frames since last period update */
+
+ struct urb *urb[NRURBS]; /* data urb table */
+ int next_urb_complete;
+ struct urb *completed_urb;
+ char *tmpbuf; /* temporary buffer for playback */
+ volatile int submitted_urbs;
+ wait_queue_head_t wait_queue;
+};
+
+
+
+
+
+
+static int usX2Y_urb_capt_retire(snd_usX2Y_substream_t *subs)
+{
+ struct urb *urb = subs->completed_urb;
+ snd_pcm_runtime_t *runtime = subs->pcm_substream->runtime;
+ unsigned char *cp;
+ int i, len, lens = 0, hwptr_done = subs->hwptr_done;
+ usX2Ydev_t *usX2Y = subs->usX2Y;
+
+ for (i = 0; i < NRPACKS; i++) {
+ cp = (unsigned char*)urb->transfer_buffer + urb->iso_frame_desc[i].offset;
+ if (urb->iso_frame_desc[i].status) { /* active? hmm, skip this */
+ snd_printdd("activ frame status %i\n", urb->iso_frame_desc[i].status);
+ return urb->iso_frame_desc[i].status;
+ }
+ len = urb->iso_frame_desc[i].actual_length / usX2Y->stride;
+ if (! len) {
+ snd_printk("0 == len ERROR!\n");
+ continue;
+ }
+
+ /* copy a data chunk */
+ if ((hwptr_done + len) > runtime->buffer_size) {
+ int cnt = runtime->buffer_size - hwptr_done;
+ int blen = cnt * usX2Y->stride;
+ memcpy(runtime->dma_area + hwptr_done * usX2Y->stride, cp, blen);
+ memcpy(runtime->dma_area, cp + blen, len * usX2Y->stride - blen);
+ } else {
+ memcpy(runtime->dma_area + hwptr_done * usX2Y->stride, cp, len * usX2Y->stride);
+ }
+ lens += len;
+ if ((hwptr_done += len) >= runtime->buffer_size)
+ hwptr_done -= runtime->buffer_size;
+ }
+
+ subs->hwptr_done = hwptr_done;
+ subs->transfer_done += lens;
+ /* update the pointer, call callback if necessary */
+ if (subs->transfer_done >= runtime->period_size) {
+ subs->transfer_done -= runtime->period_size;
+ snd_pcm_period_elapsed(subs->pcm_substream);
+ }
+ return 0;
+}
+/*
+ * prepare urb for playback data pipe
+ *
+ * we copy the data directly from the pcm buffer.
+ * the current position to be copied is held in hwptr field.
+ * since a urb can handle only a single linear buffer, if the total
+ * transferred area overflows the buffer boundary, we cannot send
+ * it directly from the buffer. thus the data is once copied to
+ * a temporary buffer and urb points to that.
+ */
+static int usX2Y_urb_play_prepare(snd_usX2Y_substream_t *subs,
+ struct urb *cap_urb,
+ struct urb *urb)
+{
+ int count, counts, pack;
+ usX2Ydev_t* usX2Y = subs->usX2Y;
+ snd_pcm_runtime_t *runtime = subs->pcm_substream->runtime;
+
+ count = 0;
+ for (pack = 0; pack < NRPACKS; pack++) {
+ /* calculate the size of a packet */
+ counts = cap_urb->iso_frame_desc[pack].actual_length / usX2Y->stride;
+ count += counts;
+ if (counts < 43 || counts > 50) {
+ snd_printk("should not be here with counts=%i\n", counts);
+ return -EPIPE;
+ }
+
+ /* set up descriptor */
+ urb->iso_frame_desc[pack].offset = pack ? urb->iso_frame_desc[pack - 1].offset + urb->iso_frame_desc[pack - 1].length : 0;
+ urb->iso_frame_desc[pack].length = counts * usX2Y->stride;
+ }
+ if (subs->hwptr + count > runtime->buffer_size) {
+ /* err, the transferred area goes over buffer boundary.
+ * copy the data to the temp buffer.
+ */
+ int len;
+ len = runtime->buffer_size - subs->hwptr;
+ urb->transfer_buffer = subs->tmpbuf;
+ memcpy(subs->tmpbuf, runtime->dma_area + subs->hwptr * usX2Y->stride, len * usX2Y->stride);
+ memcpy(subs->tmpbuf + len * usX2Y->stride, runtime->dma_area, (count - len) * usX2Y->stride);
+ subs->hwptr += count;
+ subs->hwptr -= runtime->buffer_size;
+ } else {
+ /* set the buffer pointer */
+ urb->transfer_buffer = runtime->dma_area + subs->hwptr * usX2Y->stride;
+ if ((subs->hwptr += count) >= runtime->buffer_size)
+ subs->hwptr -= runtime->buffer_size;
+ }
+ urb->transfer_buffer_length = count * usX2Y->stride;
+ return 0;
+}
+
+/*
+ * process after playback data complete
+ *
+ * update the current position and call callback if a period is processed.
+ */
+inline static int usX2Y_urb_play_retire(snd_usX2Y_substream_t *subs, struct urb *urb)
+{
+ snd_pcm_runtime_t *runtime = subs->pcm_substream->runtime;
+ int len = (urb->iso_frame_desc[0].actual_length
+#if NRPACKS > 1
+ + urb->iso_frame_desc[1].actual_length
+#endif
+ ) / subs->usX2Y->stride;
+
+ subs->transfer_done += len;
+ subs->hwptr_done += len;
+ if (subs->hwptr_done >= runtime->buffer_size)
+ subs->hwptr_done -= runtime->buffer_size;
+ if (subs->transfer_done >= runtime->period_size) {
+ subs->transfer_done -= runtime->period_size;
+ snd_pcm_period_elapsed(subs->pcm_substream);
+ }
+ return 0;
+}
+
+inline static int usX2Y_urb_submit(snd_usX2Y_substream_t *subs, struct urb *urb, int frame)
+{
+ int err;
+ if (!urb)
+ return -ENODEV;
+ urb->start_frame = (frame + NRURBS*NRPACKS) & (1024 - 1);
+ urb->hcpriv = NULL;
+ urb->dev = subs->usX2Y->chip.dev; /* we need to set this at each time */
+ if ((err = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
+ snd_printk("%i\n", err);
+ return err;
+ } else {
+ subs->submitted_urbs++;
+ if (subs->next_urb_complete < 0)
+ subs->next_urb_complete = 0;
+ }
+ return 0;
+}
+
+
+static inline int frame_distance(int from, int to)
+{
+ int distance = to - from;
+ if (distance < -512)
+ distance += 1024;
+ else
+ if (distance > 511)
+ distance -= 1024;
+ return distance;
+}
+
+
+static void usX2Y_subs_set_next_urb_complete(snd_usX2Y_substream_t *subs)
+{
+ int next_urb_complete = subs->next_urb_complete + 1;
+ int distance;
+ if (next_urb_complete >= NRURBS)
+ next_urb_complete = 0;
+ distance = frame_distance(subs->completed_urb->start_frame,
+ subs->urb[next_urb_complete]->start_frame);
+ if (1 == distance) {
+ subs->next_urb_complete = next_urb_complete;
+ } else {
+ snd_printdd("distance %i not set_nuc %i %i %i \n", distance, subs->endpoint, next_urb_complete, subs->urb[next_urb_complete]->status);
+ subs->next_urb_complete = -1;
+ }
+}
+
+
+static inline void usX2Y_usbframe_complete(snd_usX2Y_substream_t *capsubs, snd_usX2Y_substream_t *playbacksubs, int frame)
+{
+ {
+ struct urb *urb;
+ if ((urb = playbacksubs->completed_urb)) {
+ if (playbacksubs->prepared)
+ usX2Y_urb_play_retire(playbacksubs, urb);
+ usX2Y_subs_set_next_urb_complete(playbacksubs);
+ }
+ if (playbacksubs->running) {
+ if (NULL == urb)
+ urb = playbacksubs->urb[playbacksubs->next_urb_complete + 1];
+ if (urb && 0 == usX2Y_urb_play_prepare(playbacksubs,
+ capsubs->completed_urb,
+ urb)) {
+ if (usX2Y_urb_submit(playbacksubs, urb, frame) < 0)
+ return;
+ } else
+ snd_pcm_stop(playbacksubs->pcm_substream, SNDRV_PCM_STATE_XRUN);
+ }
+ playbacksubs->completed_urb = NULL;
+ }
+ if (capsubs->running)
+ usX2Y_urb_capt_retire(capsubs);
+ usX2Y_subs_set_next_urb_complete(capsubs);
+ if (capsubs->prepared)
+ usX2Y_urb_submit(capsubs, capsubs->completed_urb, frame);
+ capsubs->completed_urb = NULL;
+}
+
+
+static void usX2Y_clients_stop(snd_usX2Y_substream_t *subs)
+{
+ usX2Ydev_t *usX2Y = subs->usX2Y;
+ int i;
+ for (i = 0; i < 4; i++) {
+ snd_usX2Y_substream_t *substream = usX2Y->substream[i];
+ if (substream && substream->running)
+ snd_pcm_stop(substream->pcm_substream, SNDRV_PCM_STATE_XRUN);
+ }
+}
+
+
+static void i_usX2Y_urb_complete(struct urb *urb, struct pt_regs *regs)
+{
+ snd_usX2Y_substream_t *subs = (snd_usX2Y_substream_t*)urb->context;
+
+ subs->submitted_urbs--;
+ if (urb->status) {
+ snd_printk("ep=%i stalled with status=%i\n", subs->endpoint, urb->status);
+ subs->stalled = 1;
+ usX2Y_clients_stop(subs);
+ urb->status = 0;
+ return;
+ }
+ if (urb == subs->urb[subs->next_urb_complete]) {
+ subs->completed_urb = urb;
+ } else {
+ snd_printk("Sequence Error!(ep=%i;nuc=%i,frame=%i)\n",
+ subs->endpoint, subs->next_urb_complete, urb->start_frame);
+ subs->stalled = 1;
+ usX2Y_clients_stop(subs);
+ return;
+ }
+ if (waitqueue_active(&subs->wait_queue))
+ wake_up(&subs->wait_queue);
+ {
+ snd_usX2Y_substream_t *capsubs = subs->usX2Y->substream[SNDRV_PCM_STREAM_CAPTURE],
+ *playbacksubs = subs->usX2Y->substream[SNDRV_PCM_STREAM_PLAYBACK];
+ if (capsubs->completed_urb &&
+ (playbacksubs->completed_urb ||
+ !playbacksubs->prepared ||
+ (playbacksubs->prepared && (playbacksubs->next_urb_complete < 0 || // not started yet
+ frame_distance(capsubs->completed_urb->start_frame,
+ playbacksubs->urb[playbacksubs->next_urb_complete]->start_frame)
+ > 0 || // other expected later
+ playbacksubs->stalled))))
+ usX2Y_usbframe_complete(capsubs, playbacksubs, urb->start_frame);
+ }
+}
+
+
+static int usX2Y_urbs_capt_start(snd_usX2Y_substream_t *subs)
+{
+ int i, err;
+
+ for (i = 0; i < NRURBS; i++) {
+ unsigned long pack;
+ struct urb *urb = subs->urb[i];
+ urb->dev = subs->usX2Y->chip.dev;
+ urb->transfer_flags = URB_ISO_ASAP;
+ for (pack = 0; pack < NRPACKS; pack++) {
+ urb->iso_frame_desc[pack].offset = subs->maxpacksize * pack;
+ urb->iso_frame_desc[pack].length = subs->maxpacksize;
+ }
+ urb->transfer_buffer_length = subs->maxpacksize * NRPACKS;
+ if ((err = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
+ snd_printk (KERN_ERR "cannot submit datapipe for urb %d, err = %d\n", i, err);
+ return -EPIPE;
+ } else {
+ subs->submitted_urbs++;
+ }
+ urb->transfer_flags = 0;
+ }
+ subs->stalled = 0;
+ subs->next_urb_complete = 0;
+ subs->prepared = 1;
+ return 0;
+}
+
+/*
+ * wait until all urbs are processed.
+ */
+static int usX2Y_urbs_wait_clear(snd_usX2Y_substream_t *subs)
+{
+ int timeout = HZ;
+
+ do {
+ if (0 == subs->submitted_urbs)
+ break;
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ snd_printdd("snd_usX2Y_urbs_wait_clear waiting\n");
+ schedule_timeout(1);
+ } while (--timeout > 0);
+ if (subs->submitted_urbs)
+ snd_printk(KERN_ERR "timeout: still %d active urbs..\n", subs->submitted_urbs);
+ return 0;
+}
+/*
+ * return the current pcm pointer. just return the hwptr_done value.
+ */
+static snd_pcm_uframes_t snd_usX2Y_pcm_pointer(snd_pcm_substream_t *substream)
+{
+ snd_usX2Y_substream_t *subs = (snd_usX2Y_substream_t *)substream->runtime->private_data;
+ return subs->hwptr_done;
+}
+/*
+ * start/stop substream
+ */
+static int snd_usX2Y_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
+{
+ snd_usX2Y_substream_t *subs = (snd_usX2Y_substream_t *)substream->runtime->private_data;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ snd_printdd("snd_usX2Y_pcm_trigger(START)\n");
+ if (subs->usX2Y->substream[SNDRV_PCM_STREAM_CAPTURE]->stalled)
+ return -EPIPE;
+ else
+ subs->running = 1;
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ snd_printdd("snd_usX2Y_pcm_trigger(STOP)\n");
+ subs->running = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+
+
+static void usX2Y_urb_release(struct urb** urb, int free_tb)
+{
+ if (*urb) {
+ if (free_tb)
+ kfree((*urb)->transfer_buffer);
+ usb_free_urb(*urb);
+ *urb = NULL;
+ }
+}
+/*
+ * release a substream
+ */
+static void usX2Y_urbs_release(snd_usX2Y_substream_t *subs)
+{
+ int i;
+ snd_printdd("snd_usX2Y_urbs_release() %i\n", subs->endpoint);
+ usX2Y_urbs_wait_clear(subs);
+ for (i = 0; i < NRURBS; i++)
+ usX2Y_urb_release(subs->urb + i, subs != subs->usX2Y->substream[SNDRV_PCM_STREAM_PLAYBACK]);
+
+ if (subs->tmpbuf) {
+ kfree(subs->tmpbuf);
+ subs->tmpbuf = NULL;
+ }
+}
+
+static void usX2Y_substream_prepare(snd_usX2Y_substream_t *subs)
+{
+ snd_printdd("usX2Y_substream_prepare() ep=%i urb0=%p urb1=%p\n", subs->endpoint, subs->urb[0], subs->urb[1]);
+ /* reset the pointer */
+ subs->hwptr = 0;
+ subs->hwptr_done = 0;
+ subs->transfer_done = 0;
+}
+
+
+/*
+ * initialize a substream's urbs
+ */
+static int usX2Y_urbs_allocate(snd_usX2Y_substream_t *subs)
+{
+ int i;
+ int is_playback = subs == subs->usX2Y->substream[SNDRV_PCM_STREAM_PLAYBACK];
+ struct usb_device *dev = subs->usX2Y->chip.dev;
+
+ snd_assert(!subs->prepared, return 0);
+
+ if (is_playback) { /* allocate a temporary buffer for playback */
+ subs->datapipe = usb_sndisocpipe(dev, subs->endpoint);
+ subs->maxpacksize = dev->epmaxpacketout[subs->endpoint];
+ if (NULL == subs->tmpbuf) {
+ subs->tmpbuf = kcalloc(NRPACKS, subs->maxpacksize, GFP_KERNEL);
+ if (NULL == subs->tmpbuf) {
+ snd_printk(KERN_ERR "cannot malloc tmpbuf\n");
+ return -ENOMEM;
+ }
+ }
+ } else {
+ subs->datapipe = usb_rcvisocpipe(dev, subs->endpoint);
+ subs->maxpacksize = dev->epmaxpacketin[subs->endpoint];
+ }
+
+ /* allocate and initialize data urbs */
+ for (i = 0; i < NRURBS; i++) {
+ struct urb** purb = subs->urb + i;
+ if (*purb)
+ continue;
+ *purb = usb_alloc_urb(NRPACKS, GFP_KERNEL);
+ if (NULL == *purb) {
+ usX2Y_urbs_release(subs);
+ return -ENOMEM;
+ }
+ if (!is_playback && !(*purb)->transfer_buffer) {
+ /* allocate a capture buffer per urb */
+ (*purb)->transfer_buffer = kmalloc(subs->maxpacksize*NRPACKS, GFP_KERNEL);
+ if (NULL == (*purb)->transfer_buffer) {
+ usX2Y_urbs_release(subs);
+ return -ENOMEM;
+ }
+ }
+ (*purb)->dev = dev;
+ (*purb)->pipe = subs->datapipe;
+ (*purb)->number_of_packets = NRPACKS;
+ (*purb)->context = subs;
+ (*purb)->interval = 1;
+ (*purb)->complete = snd_usb_complete_callback(i_usX2Y_urb_complete);
+ }
+ return 0;
+}
+
+static void i_usX2Y_04Int(struct urb* urb, struct pt_regs *regs)
+{
+ usX2Ydev_t* usX2Y = urb->context;
+
+ if (urb->status) {
+ snd_printk("snd_usX2Y_04Int() urb->status=%i\n", urb->status);
+ return;
+ }
+ if (0 == --usX2Y->US04->len)
+ wake_up(&usX2Y->In04WaitQueue);
+}
+/*
+ * allocate a buffer, setup samplerate
+ *
+ * so far we use a physically linear buffer although packetize transfer
+ * doesn't need a continuous area.
+ * if sg buffer is supported on the later version of alsa, we'll follow
+ * that.
+ */
+static struct s_c2
+{
+ char c1, c2;
+}
+ SetRate44100[] =
+{
+ { 0x14, 0x08}, // this line sets 44100, well actually a little less
+ { 0x18, 0x40}, // only tascam / frontier design knows the further lines .......
+ { 0x18, 0x42},
+ { 0x18, 0x45},
+ { 0x18, 0x46},
+ { 0x18, 0x48},
+ { 0x18, 0x4A},
+ { 0x18, 0x4C},
+ { 0x18, 0x4E},
+ { 0x18, 0x50},
+ { 0x18, 0x52},
+ { 0x18, 0x54},
+ { 0x18, 0x56},
+ { 0x18, 0x58},
+ { 0x18, 0x5A},
+ { 0x18, 0x5C},
+ { 0x18, 0x5E},
+ { 0x18, 0x60},
+ { 0x18, 0x62},
+ { 0x18, 0x64},
+ { 0x18, 0x66},
+ { 0x18, 0x68},
+ { 0x18, 0x6A},
+ { 0x18, 0x6C},
+ { 0x18, 0x6E},
+ { 0x18, 0x70},
+ { 0x18, 0x72},
+ { 0x18, 0x74},
+ { 0x18, 0x76},
+ { 0x18, 0x78},
+ { 0x18, 0x7A},
+ { 0x18, 0x7C},
+ { 0x18, 0x7E}
+};
+static struct s_c2 SetRate48000[] =
+{
+ { 0x14, 0x09}, // this line sets 48000, well actually a little less
+ { 0x18, 0x40}, // only tascam / frontier design knows the further lines .......
+ { 0x18, 0x42},
+ { 0x18, 0x45},
+ { 0x18, 0x46},
+ { 0x18, 0x48},
+ { 0x18, 0x4A},
+ { 0x18, 0x4C},
+ { 0x18, 0x4E},
+ { 0x18, 0x50},
+ { 0x18, 0x52},
+ { 0x18, 0x54},
+ { 0x18, 0x56},
+ { 0x18, 0x58},
+ { 0x18, 0x5A},
+ { 0x18, 0x5C},
+ { 0x18, 0x5E},
+ { 0x18, 0x60},
+ { 0x18, 0x62},
+ { 0x18, 0x64},
+ { 0x18, 0x66},
+ { 0x18, 0x68},
+ { 0x18, 0x6A},
+ { 0x18, 0x6C},
+ { 0x18, 0x6E},
+ { 0x18, 0x70},
+ { 0x18, 0x73},
+ { 0x18, 0x74},
+ { 0x18, 0x76},
+ { 0x18, 0x78},
+ { 0x18, 0x7A},
+ { 0x18, 0x7C},
+ { 0x18, 0x7E}
+};
+#define NOOF_SETRATE_URBS ARRAY_SIZE(SetRate48000)
+
+static int usX2Y_rate_set(usX2Ydev_t *usX2Y, int rate)
+{
+ int err = 0, i;
+ snd_usX2Y_urbSeq_t *us = NULL;
+ int *usbdata = NULL;
+ DECLARE_WAITQUEUE(wait, current);
+ struct s_c2 *ra = rate == 48000 ? SetRate48000 : SetRate44100;
+
+ if (usX2Y->rate != rate) {
+ do {
+ us = kmalloc(sizeof(*us) + sizeof(struct urb*) * NOOF_SETRATE_URBS, GFP_KERNEL);
+ if (NULL == us) {
+ err = -ENOMEM;
+ break;
+ }
+ memset(us, 0, sizeof(*us) + sizeof(struct urb*) * NOOF_SETRATE_URBS);
+ usbdata = kmalloc(sizeof(int)*NOOF_SETRATE_URBS, GFP_KERNEL);
+ if (NULL == usbdata) {
+ err = -ENOMEM;
+ break;
+ }
+ for (i = 0; i < NOOF_SETRATE_URBS; ++i) {
+ if (NULL == (us->urb[i] = usb_alloc_urb(0, GFP_KERNEL))) {
+ err = -ENOMEM;
+ break;
+ }
+ ((char*)(usbdata + i))[0] = ra[i].c1;
+ ((char*)(usbdata + i))[1] = ra[i].c2;
+ usb_fill_bulk_urb(us->urb[i], usX2Y->chip.dev, usb_sndbulkpipe(usX2Y->chip.dev, 4),
+ usbdata + i, 2, i_usX2Y_04Int, usX2Y);
+#ifdef OLD_USB
+ us->urb[i]->transfer_flags = USB_QUEUE_BULK;
+#endif
+ }
+ if (err)
+ break;
+
+ add_wait_queue(&usX2Y->In04WaitQueue, &wait);
+ set_current_state(TASK_INTERRUPTIBLE);
+ us->submitted = 0;
+ us->len = NOOF_SETRATE_URBS;
+ usX2Y->US04 = us;
+
+ do {
+ signed long timeout = schedule_timeout(HZ/2);
+
+ if (signal_pending(current)) {
+ err = -ERESTARTSYS;
+ break;
+ }
+ if (0 == timeout) {
+ err = -ENODEV;
+ break;
+ }
+ usX2Y->rate = rate;
+ usX2Y->refframes = rate == 48000 ? 47 : 44;
+ } while (0);
+
+ remove_wait_queue(&usX2Y->In04WaitQueue, &wait);
+ } while (0);
+
+ if (us) {
+ us->submitted = 2*NOOF_SETRATE_URBS;
+ for (i = 0; i < NOOF_SETRATE_URBS; ++i) {
+ usb_unlink_urb(us->urb[i]);
+ usb_free_urb(us->urb[i]);
+ }
+ usX2Y->US04 = NULL;
+ kfree(usbdata);
+ kfree(us);
+ }
+ }
+
+ return err;
+}
+
+
+static int usX2Y_format_set(usX2Ydev_t *usX2Y, snd_pcm_format_t format)
+{
+ int alternate, unlink_err, err;
+ struct list_head* p;
+ if (format == SNDRV_PCM_FORMAT_S24_3LE) {
+ alternate = 2;
+ usX2Y->stride = 6;
+ } else {
+ alternate = 1;
+ usX2Y->stride = 4;
+ }
+ list_for_each(p, &usX2Y->chip.midi_list) {
+ snd_usbmidi_input_stop(p);
+ }
+ unlink_err = usb_unlink_urb(usX2Y->In04urb);
+ if ((err = usb_set_interface(usX2Y->chip.dev, 0, alternate))) {
+ snd_printk("usb_set_interface error \n");
+ return err;
+ }
+ if (0 == unlink_err) {
+ usX2Y->In04urb->dev = usX2Y->chip.dev;
+ err = usb_submit_urb(usX2Y->In04urb, GFP_KERNEL);
+ }
+ list_for_each(p, &usX2Y->chip.midi_list) {
+ snd_usbmidi_input_start(p);
+ }
+ usX2Y->format = format;
+ usX2Y->rate = 0;
+ return err;
+}
+
+
+static int snd_usX2Y_pcm_hw_params(snd_pcm_substream_t *substream,
+ snd_pcm_hw_params_t *hw_params)
+{
+ int err = 0;
+ unsigned int rate = params_rate(hw_params);
+ snd_pcm_format_t format = params_format(hw_params);
+ snd_printdd("snd_usX2Y_hw_params(%p, %p)\n", substream, hw_params);
+
+ { // all pcm substreams off one usX2Y have to operate at the same rate & format
+ snd_card_t *card = substream->pstr->pcm->card;
+ struct list_head *list;
+ list_for_each(list, &card->devices) {
+ snd_device_t *dev;
+ snd_pcm_t *pcm;
+ int s;
+ dev = snd_device(list);
+ if (dev->type != SNDRV_DEV_PCM)
+ continue;
+ pcm = dev->device_data;
+ for (s = 0; s < 2; ++s) {
+ snd_pcm_substream_t *test_substream;
+ test_substream = pcm->streams[s].substream;
+ if (test_substream && test_substream != substream &&
+ test_substream->runtime &&
+ ((test_substream->runtime->format &&
+ test_substream->runtime->format != format) ||
+ (test_substream->runtime->rate &&
+ test_substream->runtime->rate != rate)))
+ return -EINVAL;
+ }
+ }
+ }
+ if (0 > (err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)))) {
+ snd_printk("snd_pcm_lib_malloc_pages(%p, %i) returned %i\n", substream, params_buffer_bytes(hw_params), err);
+ return err;
+ }
+ return 0;
+}
+
+/*
+ * free the buffer
+ */
+static int snd_usX2Y_pcm_hw_free(snd_pcm_substream_t *substream)
+{
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ snd_usX2Y_substream_t *subs = (snd_usX2Y_substream_t *)runtime->private_data;
+ snd_printdd("snd_usX2Y_hw_free(%p)\n", substream);
+
+ if (SNDRV_PCM_STREAM_PLAYBACK == substream->stream) {
+ snd_usX2Y_substream_t *cap_subs = subs->usX2Y->substream[SNDRV_PCM_STREAM_CAPTURE];
+ subs->prepared = 0;
+ usX2Y_urbs_release(subs);
+ if (!cap_subs->pcm_substream ||
+ !cap_subs->pcm_substream->runtime ||
+ !cap_subs->pcm_substream->runtime->status ||
+ cap_subs->pcm_substream->runtime->status->state < SNDRV_PCM_STATE_PREPARED) {
+ cap_subs->prepared = 0;
+ usX2Y_urbs_release(cap_subs);
+ }
+ } else {
+ snd_usX2Y_substream_t *playback_subs = subs->usX2Y->substream[SNDRV_PCM_STREAM_PLAYBACK];
+ if (!playback_subs->prepared) {
+ subs->prepared = 0;
+ usX2Y_urbs_release(subs);
+ }
+ }
+
+ return snd_pcm_lib_free_pages(substream);
+}
+/*
+ * prepare callback
+ *
+ * set format and initialize urbs
+ */
+static int snd_usX2Y_pcm_prepare(snd_pcm_substream_t *substream)
+{
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ snd_usX2Y_substream_t *subs = (snd_usX2Y_substream_t *)runtime->private_data;
+ snd_usX2Y_substream_t *capsubs = subs->usX2Y->substream[SNDRV_PCM_STREAM_CAPTURE];
+ int err = 0;
+ snd_printdd("snd_usX2Y_pcm_prepare(%p)\n", substream);
+
+// Start hardware streams
+// SyncStream first....
+ if (! capsubs->prepared) {
+ if (subs->usX2Y->format != runtime->format)
+ if ((err = usX2Y_format_set(subs->usX2Y, runtime->format)) < 0)
+ return err;
+ if (subs->usX2Y->rate != runtime->rate)
+ if ((err = usX2Y_rate_set(subs->usX2Y, runtime->rate)) < 0)
+ return err;
+ snd_printdd("starting capture pipe for playpipe\n");
+ usX2Y_urbs_allocate(capsubs);
+ capsubs->completed_urb = NULL;
+ {
+ DECLARE_WAITQUEUE(wait, current);
+ add_wait_queue(&capsubs->wait_queue, &wait);
+ if (0 <= (err = usX2Y_urbs_capt_start(capsubs))) {
+ signed long timeout;
+ set_current_state(TASK_INTERRUPTIBLE);
+ timeout = schedule_timeout(HZ/4);
+ if (signal_pending(current))
+ err = -ERESTARTSYS;
+ else {
+ snd_printdd("%li\n", HZ/4 - timeout);
+ if (0 == timeout)
+ err = -EPIPE;
+ }
+ }
+ remove_wait_queue(&capsubs->wait_queue, &wait);
+ if (0 > err)
+ return err;
+ }
+ }
+
+ if (subs != capsubs) {
+ int u;
+ if (!subs->prepared) {
+ if ((err = usX2Y_urbs_allocate(subs)) < 0)
+ return err;
+ subs->prepared = 1;
+ }
+ while (subs->submitted_urbs)
+ for (u = 0; u < NRURBS; u++) {
+ snd_printdd("%i\n", subs->urb[u]->status);
+ while(subs->urb[u]->status || NULL != subs->urb[u]->hcpriv) {
+ signed long timeout;
+ snd_printdd("ep=%i waiting for urb=%p status=%i hcpriv=%p\n",
+ subs->endpoint, subs->urb[u],
+ subs->urb[u]->status, subs->urb[u]->hcpriv);
+ set_current_state(TASK_INTERRUPTIBLE);
+ timeout = schedule_timeout(HZ/10);
+ if (signal_pending(current)) {
+ return -ERESTARTSYS;
+ }
+ }
+ }
+ subs->completed_urb = NULL;
+ subs->next_urb_complete = -1;
+ subs->stalled = 0;
+ }
+
+ usX2Y_substream_prepare(subs);
+ return err;
+}
+
+static snd_pcm_hardware_t snd_usX2Y_2c =
+{
+ .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP_VALID),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_3LE,
+ .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+ .rate_min = 44100,
+ .rate_max = 48000,
+ .channels_min = 2,
+ .channels_max = 2,
+ .buffer_bytes_max = (2*128*1024),
+ .period_bytes_min = 64,
+ .period_bytes_max = (128*1024),
+ .periods_min = 2,
+ .periods_max = 1024,
+ .fifo_size = 0
+};
+
+
+
+static int snd_usX2Y_pcm_open(snd_pcm_substream_t *substream)
+{
+ snd_usX2Y_substream_t *subs = ((snd_usX2Y_substream_t **)
+ snd_pcm_substream_chip(substream))[substream->stream];
+ snd_pcm_runtime_t *runtime = substream->runtime;
+
+ runtime->hw = snd_usX2Y_2c;
+ runtime->private_data = subs;
+ subs->pcm_substream = substream;
+ snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 1000, 200000);
+ return 0;
+}
+
+
+
+static int snd_usX2Y_pcm_close(snd_pcm_substream_t *substream)
+{
+ snd_pcm_runtime_t *runtime = substream->runtime;
+ snd_usX2Y_substream_t *subs = (snd_usX2Y_substream_t *)runtime->private_data;
+ int err = 0;
+
+ subs->pcm_substream = NULL;
+
+ return err;
+}
+
+
+static snd_pcm_ops_t snd_usX2Y_pcm_ops =
+{
+ .open = snd_usX2Y_pcm_open,
+ .close = snd_usX2Y_pcm_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = snd_usX2Y_pcm_hw_params,
+ .hw_free = snd_usX2Y_pcm_hw_free,
+ .prepare = snd_usX2Y_pcm_prepare,
+ .trigger = snd_usX2Y_pcm_trigger,
+ .pointer = snd_usX2Y_pcm_pointer,
+};
+
+
+/*
+ * free a usb stream instance
+ */
+static void usX2Y_audio_stream_free(snd_usX2Y_substream_t **usX2Y_substream)
+{
+ if (NULL != usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK]) {
+ kfree(usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK]);
+ usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK] = NULL;
+ }
+ kfree(usX2Y_substream[SNDRV_PCM_STREAM_CAPTURE]);
+ usX2Y_substream[SNDRV_PCM_STREAM_CAPTURE] = NULL;
+}
+
+static void snd_usX2Y_pcm_private_free(snd_pcm_t *pcm)
+{
+ snd_usX2Y_substream_t **usX2Y_stream = pcm->private_data;
+ if (usX2Y_stream) {
+ snd_pcm_lib_preallocate_free_for_all(pcm);
+ usX2Y_audio_stream_free(usX2Y_stream);
+ }
+}
+
+static int usX2Y_audio_stream_new(snd_card_t *card, int playback_endpoint, int capture_endpoint)
+{
+ snd_pcm_t *pcm;
+ int err, i;
+ snd_usX2Y_substream_t **usX2Y_substream =
+ usX2Y(card)->substream + 2 * usX2Y(card)->chip.pcm_devs;
+
+ for (i = playback_endpoint ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
+ i <= SNDRV_PCM_STREAM_CAPTURE; ++i) {
+ usX2Y_substream[i] = kcalloc(1, sizeof(snd_usX2Y_substream_t), GFP_KERNEL);
+ if (NULL == usX2Y_substream[i]) {
+ snd_printk(KERN_ERR "cannot malloc\n");
+ return -ENOMEM;
+ }
+ init_waitqueue_head(&usX2Y_substream[i]->wait_queue);
+ usX2Y_substream[i]->usX2Y = usX2Y(card);
+ }
+
+ if (playback_endpoint)
+ usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK]->endpoint = playback_endpoint;
+ usX2Y_substream[SNDRV_PCM_STREAM_CAPTURE]->endpoint = capture_endpoint;
+
+ err = snd_pcm_new(card, NAME_ALLCAPS" Audio", usX2Y(card)->chip.pcm_devs,
+ playback_endpoint ? 1 : 0, 1,
+ &pcm);
+ if (err < 0) {
+ usX2Y_audio_stream_free(usX2Y_substream);
+ return err;
+ }
+
+ if (playback_endpoint)
+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_usX2Y_pcm_ops);
+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_usX2Y_pcm_ops);
+
+ pcm->private_data = usX2Y_substream;
+ pcm->private_free = snd_usX2Y_pcm_private_free;
+ pcm->info_flags = 0;
+
+ sprintf(pcm->name, NAME_ALLCAPS" Audio #%d", usX2Y(card)->chip.pcm_devs);
+
+ if ((playback_endpoint &&
+ 0 > (err = snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
+ SNDRV_DMA_TYPE_CONTINUOUS,
+ snd_dma_continuous_data(GFP_KERNEL),
+ 64*1024, 128*1024))) ||
+ 0 > (err = snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
+ SNDRV_DMA_TYPE_CONTINUOUS,
+ snd_dma_continuous_data(GFP_KERNEL),
+ 64*1024, 128*1024))) {
+ snd_usX2Y_pcm_private_free(pcm);
+ return err;
+ }
+ usX2Y(card)->chip.pcm_devs++;
+
+ return 0;
+}
+
+/*
+ * free the chip instance
+ *
+ * here we have to do not much, since pcm and controls are already freed
+ *
+ */
+static int snd_usX2Y_device_dev_free(snd_device_t *device)
+{
+ return 0;
+}
+
+
+/*
+ * create a chip instance and set its names.
+ */
+int usX2Y_audio_create(snd_card_t* card)
+{
+ int err = 0;
+ static snd_device_ops_t ops = {
+ .dev_free = snd_usX2Y_device_dev_free,
+ };
+
+ INIT_LIST_HEAD(&usX2Y(card)->chip.pcm_list);
+
+ if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, usX2Y(card), &ops)) < 0) {
+// snd_usX2Y_audio_free(usX2Y(card));
+ return err;
+ }
+
+ if (0 > (err = usX2Y_audio_stream_new(card, 0xA, 0x8)))
+ return err;
+ if (usX2Y(card)->chip.dev->descriptor.idProduct == USB_ID_US428)
+ if (0 > (err = usX2Y_audio_stream_new(card, 0, 0xA)))
+ return err;
+ if (usX2Y(card)->chip.dev->descriptor.idProduct != USB_ID_US122)
+ err = usX2Y_rate_set(usX2Y(card), 44100); // Lets us428 recognize output-volume settings, disturbs us122.
+ return err;
+}
--- /dev/null
+/*
+ * Driver for Tascam US-X2Y USB soundcards
+ *
+ * Copyright (c) 2003 by Karsten Wiese <annabellesgarden@yahoo.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __SOUND_USX2Y_COMMON_H
+#define __SOUND_USX2Y_COMMON_H
+
+
+#define USX2Y_DRIVER_VERSION 0x0100 /* 0.1.0 */
+
+
+/* hwdep id string */
+#define SND_USX2Y_LOADER_ID "USX2Y Loader"
+
+/* hardware type */
+enum {
+ USX2Y_TYPE_122,
+ USX2Y_TYPE_224,
+ USX2Y_TYPE_428,
+ USX2Y_TYPE_NUMS
+};
+
+#define USB_ID_US122 0x8007
+#define USB_ID_US224 0x8005
+#define USB_ID_US428 0x8001
+
+/* chip status */
+enum {
+ USX2Y_STAT_CHIP_INIT = (1 << 0), /* all operational */
+ USX2Y_STAT_CHIP_HUP = (1 << 31), /* all operational */
+};
+
+#endif /* __SOUND_USX2Y_COMMON_H */
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